diff --git a/bolt/lib/Core/MCPlusBuilder.cpp b/bolt/lib/Core/MCPlusBuilder.cpp
index a3be147a09066..7752079b61538 100644
--- a/bolt/lib/Core/MCPlusBuilder.cpp
+++ b/bolt/lib/Core/MCPlusBuilder.cpp
@@ -442,10 +442,10 @@ void MCPlusBuilder::getUsedRegs(const MCInst &Inst, BitVector &Regs) const {
   for (MCPhysReg ImplicitUse : InstInfo.implicit_uses())
     Regs |= getAliases(ImplicitUse, /*OnlySmaller=*/true);
 
-  for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) {
-    if (!Inst.getOperand(I).isReg())
+  for (const MCOperand &Operand : useOperands(Inst)) {
+    if (!Operand.isReg())
       continue;
-    Regs |= getAliases(Inst.getOperand(I).getReg(), /*OnlySmaller=*/true);
+    Regs |= getAliases(Operand.getReg(), /*OnlySmaller=*/true);
   }
 }
 
diff --git a/bolt/unittests/Core/MCPlusBuilder.cpp b/bolt/unittests/Core/MCPlusBuilder.cpp
index a3113cab3d334..7016dec0e3574 100644
--- a/bolt/unittests/Core/MCPlusBuilder.cpp
+++ b/bolt/unittests/Core/MCPlusBuilder.cpp
@@ -8,6 +8,7 @@
 
 #ifdef AARCH64_AVAILABLE
 #include "AArch64Subtarget.h"
+#include "MCTargetDesc/AArch64MCTargetDesc.h"
 #endif // AARCH64_AVAILABLE
 
 #ifdef X86_AVAILABLE
@@ -19,6 +20,7 @@
 #include "bolt/Rewrite/RewriteInstance.h"
 #include "llvm/BinaryFormat/ELF.h"
 #include "llvm/DebugInfo/DWARF/DWARFContext.h"
+#include "llvm/MC/MCInstBuilder.h"
 #include "llvm/Support/TargetSelect.h"
 #include "gtest/gtest.h"
 
@@ -70,16 +72,28 @@ struct MCPlusBuilderTester : public testing::TestWithParam<Triple::ArchType> {
                             BC->MRI.get(), BC->STI.get())));
   }
 
+  void assertRegMask(const BitVector &RegMask,
+                     std::initializer_list<MCPhysReg> ExpectedRegs) {
+    ASSERT_EQ(RegMask.count(), ExpectedRegs.size());
+    for (MCPhysReg Reg : ExpectedRegs)
+      ASSERT_TRUE(RegMask[Reg]) << "Expected " << BC->MRI->getName(Reg) << ".";
+  }
+
+  void assertRegMask(std::function<void(BitVector &)> FillRegMask,
+                     std::initializer_list<MCPhysReg> ExpectedRegs) {
+    BitVector RegMask(BC->MRI->getNumRegs());
+    FillRegMask(RegMask);
+    assertRegMask(RegMask, ExpectedRegs);
+  }
+
   void testRegAliases(Triple::ArchType Arch, uint64_t Register,
-                      uint64_t *Aliases, size_t Count,
+                      std::initializer_list<MCPhysReg> ExpectedAliases,
                       bool OnlySmaller = false) {
     if (GetParam() != Arch)
       GTEST_SKIP();
 
     const BitVector &BV = BC->MIB->getAliases(Register, OnlySmaller);
-    ASSERT_EQ(BV.count(), Count);
-    for (size_t I = 0; I < Count; ++I)
-      ASSERT_TRUE(BV[Aliases[I]]);
+    assertRegMask(BV, ExpectedAliases);
   }
 
   char ElfBuf[sizeof(typename ELF64LE::Ehdr)] = {};
@@ -94,17 +108,15 @@ INSTANTIATE_TEST_SUITE_P(AArch64, MCPlusBuilderTester,
                          ::testing::Values(Triple::aarch64));
 
 TEST_P(MCPlusBuilderTester, AliasX0) {
-  uint64_t AliasesX0[] = {AArch64::W0,    AArch64::W0_HI,
-                          AArch64::X0,    AArch64::W0_W1,
-                          AArch64::X0_X1, AArch64::X0_X1_X2_X3_X4_X5_X6_X7};
-  size_t AliasesX0Count = sizeof(AliasesX0) / sizeof(*AliasesX0);
-  testRegAliases(Triple::aarch64, AArch64::X0, AliasesX0, AliasesX0Count);
+  testRegAliases(Triple::aarch64, AArch64::X0,
+                 {AArch64::W0, AArch64::W0_HI, AArch64::X0, AArch64::W0_W1,
+                  AArch64::X0_X1, AArch64::X0_X1_X2_X3_X4_X5_X6_X7});
 }
 
 TEST_P(MCPlusBuilderTester, AliasSmallerX0) {
-  uint64_t AliasesX0[] = {AArch64::W0, AArch64::W0_HI, AArch64::X0};
-  size_t AliasesX0Count = sizeof(AliasesX0) / sizeof(*AliasesX0);
-  testRegAliases(Triple::aarch64, AArch64::X0, AliasesX0, AliasesX0Count, true);
+  testRegAliases(Triple::aarch64, AArch64::X0,
+                 {AArch64::W0, AArch64::W0_HI, AArch64::X0},
+                 /*OnlySmaller=*/true);
 }
 
 TEST_P(MCPlusBuilderTester, AArch64_CmpJE) {
@@ -155,6 +167,100 @@ TEST_P(MCPlusBuilderTester, AArch64_CmpJNE) {
   ASSERT_EQ(Label, BB->getLabel());
 }
 
+TEST_P(MCPlusBuilderTester, testAccessedRegsImplicitDef) {
+  if (GetParam() != Triple::aarch64)
+    GTEST_SKIP();
+
+  // adds x0, x5, #42
+  MCInst Inst = MCInstBuilder(AArch64::ADDSXri)
+                    .addReg(AArch64::X0)
+                    .addReg(AArch64::X5)
+                    .addImm(42)
+                    .addImm(0);
+
+  assertRegMask([&](BitVector &BV) { BC->MIB->getClobberedRegs(Inst, BV); },
+                {AArch64::NZCV, AArch64::W0, AArch64::X0, AArch64::W0_HI,
+                 AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::W0_W1,
+                 AArch64::X0_X1});
+
+  assertRegMask(
+      [&](BitVector &BV) { BC->MIB->getTouchedRegs(Inst, BV); },
+      {AArch64::NZCV, AArch64::W0, AArch64::W5, AArch64::X0, AArch64::X5,
+       AArch64::W0_HI, AArch64::W5_HI, AArch64::X0_X1_X2_X3_X4_X5_X6_X7,
+       AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11,
+       AArch64::W0_W1, AArch64::W4_W5, AArch64::X0_X1, AArch64::X4_X5});
+
+  assertRegMask([&](BitVector &BV) { BC->MIB->getWrittenRegs(Inst, BV); },
+                {AArch64::NZCV, AArch64::W0, AArch64::X0, AArch64::W0_HI});
+
+  assertRegMask([&](BitVector &BV) { BC->MIB->getUsedRegs(Inst, BV); },
+                {AArch64::W5, AArch64::X5, AArch64::W5_HI});
+
+  assertRegMask([&](BitVector &BV) { BC->MIB->getSrcRegs(Inst, BV); },
+                {AArch64::W5, AArch64::X5, AArch64::W5_HI});
+}
+
+TEST_P(MCPlusBuilderTester, testAccessedRegsImplicitUse) {
+  if (GetParam() != Triple::aarch64)
+    GTEST_SKIP();
+
+  // b.eq <label>
+  MCInst Inst =
+      MCInstBuilder(AArch64::Bcc)
+          .addImm(AArch64CC::EQ)
+          .addImm(0); // <label> - should be Expr, but immediate 0 works too.
+
+  assertRegMask([&](BitVector &BV) { BC->MIB->getClobberedRegs(Inst, BV); },
+                {});
+
+  assertRegMask([&](BitVector &BV) { BC->MIB->getTouchedRegs(Inst, BV); },
+                {AArch64::NZCV});
+
+  assertRegMask([&](BitVector &BV) { BC->MIB->getWrittenRegs(Inst, BV); }, {});
+
+  assertRegMask([&](BitVector &BV) { BC->MIB->getUsedRegs(Inst, BV); },
+                {AArch64::NZCV});
+
+  assertRegMask([&](BitVector &BV) { BC->MIB->getSrcRegs(Inst, BV); },
+                {AArch64::NZCV});
+}
+
+TEST_P(MCPlusBuilderTester, testAccessedRegsMultipleDefs) {
+  if (GetParam() != Triple::aarch64)
+    GTEST_SKIP();
+
+  // ldr x0, [x5], #16
+  MCInst Inst = MCInstBuilder(AArch64::LDRXpost)
+                    .addReg(AArch64::X5)
+                    .addReg(AArch64::X0)
+                    .addReg(AArch64::X5)
+                    .addImm(16);
+
+  assertRegMask(
+      [&](BitVector &BV) { BC->MIB->getClobberedRegs(Inst, BV); },
+      {AArch64::W0, AArch64::W5, AArch64::X0, AArch64::X5, AArch64::W0_HI,
+       AArch64::W5_HI, AArch64::X0_X1_X2_X3_X4_X5_X6_X7,
+       AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11,
+       AArch64::W0_W1, AArch64::W4_W5, AArch64::X0_X1, AArch64::X4_X5});
+
+  assertRegMask(
+      [&](BitVector &BV) { BC->MIB->getTouchedRegs(Inst, BV); },
+      {AArch64::W0, AArch64::W5, AArch64::X0, AArch64::X5, AArch64::W0_HI,
+       AArch64::W5_HI, AArch64::X0_X1_X2_X3_X4_X5_X6_X7,
+       AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11,
+       AArch64::W0_W1, AArch64::W4_W5, AArch64::X0_X1, AArch64::X4_X5});
+
+  assertRegMask([&](BitVector &BV) { BC->MIB->getWrittenRegs(Inst, BV); },
+                {AArch64::W0, AArch64::X0, AArch64::W0_HI, AArch64::W5,
+                 AArch64::X5, AArch64::W5_HI});
+
+  assertRegMask([&](BitVector &BV) { BC->MIB->getUsedRegs(Inst, BV); },
+                {AArch64::W5, AArch64::X5, AArch64::W5_HI});
+
+  assertRegMask([&](BitVector &BV) { BC->MIB->getSrcRegs(Inst, BV); },
+                {AArch64::W5, AArch64::X5, AArch64::W5_HI});
+}
+
 #endif // AARCH64_AVAILABLE
 
 #ifdef X86_AVAILABLE
@@ -163,15 +269,13 @@ INSTANTIATE_TEST_SUITE_P(X86, MCPlusBuilderTester,
                          ::testing::Values(Triple::x86_64));
 
 TEST_P(MCPlusBuilderTester, AliasAX) {
-  uint64_t AliasesAX[] = {X86::RAX, X86::EAX, X86::AX, X86::AL, X86::AH};
-  size_t AliasesAXCount = sizeof(AliasesAX) / sizeof(*AliasesAX);
-  testRegAliases(Triple::x86_64, X86::AX, AliasesAX, AliasesAXCount);
+  testRegAliases(Triple::x86_64, X86::AX,
+                 {X86::RAX, X86::EAX, X86::AX, X86::AL, X86::AH});
 }
 
 TEST_P(MCPlusBuilderTester, AliasSmallerAX) {
-  uint64_t AliasesAX[] = {X86::AX, X86::AL, X86::AH};
-  size_t AliasesAXCount = sizeof(AliasesAX) / sizeof(*AliasesAX);
-  testRegAliases(Triple::x86_64, X86::AX, AliasesAX, AliasesAXCount, true);
+  testRegAliases(Triple::x86_64, X86::AX, {X86::AX, X86::AL, X86::AH},
+                 /*OnlySmaller=*/true);
 }
 
 TEST_P(MCPlusBuilderTester, ReplaceRegWithImm) {
diff --git a/clang-tools-extra/clang-doc/Serialize.cpp b/clang-tools-extra/clang-doc/Serialize.cpp
index db7d04dc3da25..8ddc34b48dd8a 100644
--- a/clang-tools-extra/clang-doc/Serialize.cpp
+++ b/clang-tools-extra/clang-doc/Serialize.cpp
@@ -261,8 +261,7 @@ static bool isPublic(const clang::AccessSpecifier AS,
                      const clang::Linkage Link) {
   if (AS == clang::AccessSpecifier::AS_private)
     return false;
-  else if ((Link == clang::Linkage::Module) ||
-           (Link == clang::Linkage::External))
+  if ((Link == clang::Linkage::Module) || (Link == clang::Linkage::External))
     return true;
   return false; // otherwise, linkage is some form of internal linkage
 }
diff --git a/clang-tools-extra/clangd/InlayHints.cpp b/clang-tools-extra/clangd/InlayHints.cpp
index 40a824618f782..bdab2b8a9f377 100644
--- a/clang-tools-extra/clangd/InlayHints.cpp
+++ b/clang-tools-extra/clangd/InlayHints.cpp
@@ -112,7 +112,9 @@ std::string summarizeExpr(const Expr *E) {
       return getSimpleName(*E->getFoundDecl()).str();
     }
     std::string VisitCallExpr(const CallExpr *E) {
-      return Visit(E->getCallee());
+      std::string Result = Visit(E->getCallee());
+      Result += E->getNumArgs() == 0 ? "()" : "(...)";
+      return Result;
     }
     std::string
     VisitCXXDependentScopeMemberExpr(const CXXDependentScopeMemberExpr *E) {
@@ -147,6 +149,9 @@ std::string summarizeExpr(const Expr *E) {
     }
 
     // Literals are just printed
+    std::string VisitCXXNullPtrLiteralExpr(const CXXNullPtrLiteralExpr *E) {
+      return "nullptr";
+    }
     std::string VisitCXXBoolLiteralExpr(const CXXBoolLiteralExpr *E) {
       return E->getValue() ? "true" : "false";
     }
@@ -165,12 +170,14 @@ std::string summarizeExpr(const Expr *E) {
       std::string Result = "\"";
       if (E->containsNonAscii()) {
         Result += "...";
-      } else if (E->getLength() > 10) {
-        Result += E->getString().take_front(7);
-        Result += "...";
       } else {
         llvm::raw_string_ostream OS(Result);
-        llvm::printEscapedString(E->getString(), OS);
+        if (E->getLength() > 10) {
+          llvm::printEscapedString(E->getString().take_front(7), OS);
+          Result += "...";
+        } else {
+          llvm::printEscapedString(E->getString(), OS);
+        }
       }
       Result.push_back('"');
       return Result;
@@ -408,12 +415,14 @@ struct Callee {
 class InlayHintVisitor : public RecursiveASTVisitor<InlayHintVisitor> {
 public:
   InlayHintVisitor(std::vector<InlayHint> &Results, ParsedAST &AST,
-                   const Config &Cfg, std::optional<Range> RestrictRange)
+                   const Config &Cfg, std::optional<Range> RestrictRange,
+                   InlayHintOptions HintOptions)
       : Results(Results), AST(AST.getASTContext()), Tokens(AST.getTokens()),
         Cfg(Cfg), RestrictRange(std::move(RestrictRange)),
         MainFileID(AST.getSourceManager().getMainFileID()),
         Resolver(AST.getHeuristicResolver()),
-        TypeHintPolicy(this->AST.getPrintingPolicy()) {
+        TypeHintPolicy(this->AST.getPrintingPolicy()),
+        HintOptions(HintOptions) {
     bool Invalid = false;
     llvm::StringRef Buf =
         AST.getSourceManager().getBufferData(MainFileID, &Invalid);
@@ -1120,7 +1129,6 @@ class InlayHintVisitor : public RecursiveASTVisitor<InlayHintVisitor> {
   // Otherwise, the hint shouldn't be shown.
   std::optional<Range> computeBlockEndHintRange(SourceRange BraceRange,
                                                 StringRef OptionalPunctuation) {
-    constexpr unsigned HintMinLineLimit = 2;
 
     auto &SM = AST.getSourceManager();
     auto [BlockBeginFileId, BlockBeginOffset] =
@@ -1148,7 +1156,7 @@ class InlayHintVisitor : public RecursiveASTVisitor<InlayHintVisitor> {
     auto RBraceLine = SM.getLineNumber(RBraceFileId, RBraceOffset);
 
     // Don't show hint on trivial blocks like `class X {};`
-    if (BlockBeginLine + HintMinLineLimit - 1 > RBraceLine)
+    if (BlockBeginLine + HintOptions.HintMinLineLimit - 1 > RBraceLine)
       return std::nullopt;
 
     // This is what we attach the hint to, usually "}" or "};".
@@ -1178,17 +1186,20 @@ class InlayHintVisitor : public RecursiveASTVisitor<InlayHintVisitor> {
   StringRef MainFileBuf;
   const HeuristicResolver *Resolver;
   PrintingPolicy TypeHintPolicy;
+  InlayHintOptions HintOptions;
 };
 
 } // namespace
 
 std::vector<InlayHint> inlayHints(ParsedAST &AST,
-                                  std::optional<Range> RestrictRange) {
+                                  std::optional<Range> RestrictRange,
+                                  InlayHintOptions HintOptions) {
   std::vector<InlayHint> Results;
   const auto &Cfg = Config::current();
   if (!Cfg.InlayHints.Enabled)
     return Results;
-  InlayHintVisitor Visitor(Results, AST, Cfg, std::move(RestrictRange));
+  InlayHintVisitor Visitor(Results, AST, Cfg, std::move(RestrictRange),
+                           HintOptions);
   Visitor.TraverseAST(AST.getASTContext());
 
   // De-duplicate hints. Duplicates can sometimes occur due to e.g. explicit
diff --git a/clang-tools-extra/clangd/InlayHints.h b/clang-tools-extra/clangd/InlayHints.h
index 6a0236a0ab08a..612434b728456 100644
--- a/clang-tools-extra/clangd/InlayHints.h
+++ b/clang-tools-extra/clangd/InlayHints.h
@@ -22,10 +22,17 @@ namespace clang {
 namespace clangd {
 class ParsedAST;
 
+struct InlayHintOptions {
+  // Minimum height of a code block in lines for a BlockEnd hint to be shown
+  // Includes the lines containing the braces
+  int HintMinLineLimit = 10;
+};
+
 /// Compute and return inlay hints for a file.
 /// If RestrictRange is set, return only hints whose location is in that range.
 std::vector<InlayHint> inlayHints(ParsedAST &AST,
-                                  std::optional<Range> RestrictRange);
+                                  std::optional<Range> RestrictRange,
+                                  InlayHintOptions HintOptions = {});
 
 } // namespace clangd
 } // namespace clang
diff --git a/clang-tools-extra/clangd/XRefs.cpp b/clang-tools-extra/clangd/XRefs.cpp
index 053e2c044c774..089f8158c9aa5 100644
--- a/clang-tools-extra/clangd/XRefs.cpp
+++ b/clang-tools-extra/clangd/XRefs.cpp
@@ -2380,7 +2380,7 @@ outgoingCalls(const CallHierarchyItem &Item, const SymbolIndex *Index) {
   // Initially store the ranges in a map keyed by SymbolID of the callee.
   // This allows us to group different calls to the same function
   // into the same CallHierarchyOutgoingCall.
-  llvm::DenseMap<SymbolID, std::vector<Range>> CallsOut;
+  llvm::DenseMap<SymbolID, std::vector<Location>> CallsOut;
   // We can populate the ranges based on a refs request only. As we do so, we
   // also accumulate the callee IDs into a lookup request.
   LookupRequest CallsOutLookup;
@@ -2390,8 +2390,8 @@ outgoingCalls(const CallHierarchyItem &Item, const SymbolIndex *Index) {
       elog("outgoingCalls failed to convert location: {0}", Loc.takeError());
       return;
     }
-    auto It = CallsOut.try_emplace(R.Symbol, std::vector<Range>{}).first;
-    It->second.push_back(Loc->range);
+    auto It = CallsOut.try_emplace(R.Symbol, std::vector<Location>{}).first;
+    It->second.push_back(*Loc);
 
     CallsOutLookup.IDs.insert(R.Symbol);
   });
@@ -2411,9 +2411,22 @@ outgoingCalls(const CallHierarchyItem &Item, const SymbolIndex *Index) {
 
     auto It = CallsOut.find(Callee.ID);
     assert(It != CallsOut.end());
-    if (auto CHI = symbolToCallHierarchyItem(Callee, Item.uri.file()))
+    if (auto CHI = symbolToCallHierarchyItem(Callee, Item.uri.file())) {
+      std::vector<Range> FromRanges;
+      for (const Location &L : It->second) {
+        if (L.uri != Item.uri) {
+          // Call location not in same file as the item that outgoingCalls was
+          // requested for. This can happen when Item is a declaration separate
+          // from the implementation. There's not much we can do, since the
+          // protocol only allows returning ranges interpreted as being in
+          // Item's file.
+          continue;
+        }
+        FromRanges.push_back(L.range);
+      }
       Results.push_back(
-          CallHierarchyOutgoingCall{std::move(*CHI), std::move(It->second)});
+          CallHierarchyOutgoingCall{std::move(*CHI), std::move(FromRanges)});
+    }
   });
   // Sort results by name of the callee.
   llvm::sort(Results, [](const CallHierarchyOutgoingCall &A,
diff --git a/clang-tools-extra/clangd/unittests/CallHierarchyTests.cpp b/clang-tools-extra/clangd/unittests/CallHierarchyTests.cpp
index 316b94305c9ae..eb852ef5ee00b 100644
--- a/clang-tools-extra/clangd/unittests/CallHierarchyTests.cpp
+++ b/clang-tools-extra/clangd/unittests/CallHierarchyTests.cpp
@@ -45,6 +45,7 @@ using ::testing::UnorderedElementsAre;
 // Helpers for matching call hierarchy data structures.
 MATCHER_P(withName, N, "") { return arg.name == N; }
 MATCHER_P(withDetail, N, "") { return arg.detail == N; }
+MATCHER_P(withFile, N, "") { return arg.uri.file() == N; }
 MATCHER_P(withSelectionRange, R, "") { return arg.selectionRange == R; }
 
 template <class ItemMatcher>
@@ -383,18 +384,28 @@ TEST(CallHierarchy, MultiFileCpp) {
     EXPECT_THAT(IncomingLevel4, IsEmpty());
   };
 
-  auto CheckOutgoingCalls = [&](ParsedAST &AST, Position Pos, PathRef TUPath) {
+  auto CheckOutgoingCalls = [&](ParsedAST &AST, Position Pos, PathRef TUPath,
+                                bool IsDeclaration) {
     std::vector<CallHierarchyItem> Items =
         prepareCallHierarchy(AST, Pos, TUPath);
-    ASSERT_THAT(Items, ElementsAre(withName("caller3")));
+    ASSERT_THAT(
+        Items,
+        ElementsAre(AllOf(
+            withName("caller3"),
+            withFile(testPath(IsDeclaration ? "caller3.hh" : "caller3.cc")))));
     auto OutgoingLevel1 = outgoingCalls(Items[0], Index.get());
     ASSERT_THAT(
         OutgoingLevel1,
+        // fromRanges are interpreted in the context of Items[0]'s file.
+        // If that's the header, we can't get ranges from the implementation
+        // file!
         ElementsAre(
             AllOf(to(AllOf(withName("caller1"), withDetail("nsa::caller1"))),
-                  oFromRanges(Caller3C.range("Caller1"))),
+                  IsDeclaration ? oFromRanges()
+                                : oFromRanges(Caller3C.range("Caller1"))),
             AllOf(to(AllOf(withName("caller2"), withDetail("nsb::caller2"))),
-                  oFromRanges(Caller3C.range("Caller2")))));
+                  IsDeclaration ? oFromRanges()
+                                : oFromRanges(Caller3C.range("Caller2")))));
 
     auto OutgoingLevel2 = outgoingCalls(OutgoingLevel1[1].to, Index.get());
     ASSERT_THAT(OutgoingLevel2,
@@ -423,7 +434,7 @@ TEST(CallHierarchy, MultiFileCpp) {
   CheckIncomingCalls(*AST, CalleeH.point(), testPath("callee.hh"));
   AST = Workspace.openFile("caller3.hh");
   ASSERT_TRUE(bool(AST));
-  CheckOutgoingCalls(*AST, Caller3H.point(), testPath("caller3.hh"));
+  CheckOutgoingCalls(*AST, Caller3H.point(), testPath("caller3.hh"), true);
 
   // Check that invoking from the definition site works.
   AST = Workspace.openFile("callee.cc");
@@ -431,7 +442,7 @@ TEST(CallHierarchy, MultiFileCpp) {
   CheckIncomingCalls(*AST, CalleeC.point(), testPath("callee.cc"));
   AST = Workspace.openFile("caller3.cc");
   ASSERT_TRUE(bool(AST));
-  CheckOutgoingCalls(*AST, Caller3C.point(), testPath("caller3.cc"));
+  CheckOutgoingCalls(*AST, Caller3C.point(), testPath("caller3.cc"), false);
 }
 
 TEST(CallHierarchy, IncomingMultiFileObjC) {
diff --git a/clang-tools-extra/clangd/unittests/InlayHintTests.cpp b/clang-tools-extra/clangd/unittests/InlayHintTests.cpp
index 030e499577706..c3331d20730f1 100644
--- a/clang-tools-extra/clangd/unittests/InlayHintTests.cpp
+++ b/clang-tools-extra/clangd/unittests/InlayHintTests.cpp
@@ -36,9 +36,12 @@ namespace {
 using ::testing::ElementsAre;
 using ::testing::IsEmpty;
 
-std::vector<InlayHint> hintsOfKind(ParsedAST &AST, InlayHintKind Kind) {
+constexpr InlayHintOptions DefaultOptsForTests{2};
+
+std::vector<InlayHint> hintsOfKind(ParsedAST &AST, InlayHintKind Kind,
+                                   InlayHintOptions Opts) {
   std::vector<InlayHint> Result;
-  for (auto &Hint : inlayHints(AST, /*RestrictRange=*/std::nullopt)) {
+  for (auto &Hint : inlayHints(AST, /*RestrictRange=*/std::nullopt, Opts)) {
     if (Hint.kind == Kind)
       Result.push_back(Hint);
   }
@@ -90,7 +93,7 @@ Config noHintsConfig() {
 
 template <typename... ExpectedHints>
 void assertHintsWithHeader(InlayHintKind Kind, llvm::StringRef AnnotatedSource,
-                           llvm::StringRef HeaderContent,
+                           llvm::StringRef HeaderContent, InlayHintOptions Opts,
                            ExpectedHints... Expected) {
   Annotations Source(AnnotatedSource);
   TestTU TU = TestTU::withCode(Source.code());
@@ -98,18 +101,18 @@ void assertHintsWithHeader(InlayHintKind Kind, llvm::StringRef AnnotatedSource,
   TU.HeaderCode = HeaderContent;
   auto AST = TU.build();
 
-  EXPECT_THAT(hintsOfKind(AST, Kind),
+  EXPECT_THAT(hintsOfKind(AST, Kind, Opts),
               ElementsAre(HintMatcher(Expected, Source)...));
   // Sneak in a cross-cutting check that hints are disabled by config.
   // We'll hit an assertion failure if addInlayHint still gets called.
   WithContextValue WithCfg(Config::Key, noHintsConfig());
-  EXPECT_THAT(inlayHints(AST, std::nullopt), IsEmpty());
+  EXPECT_THAT(inlayHints(AST, std::nullopt, Opts), IsEmpty());
 }
 
 template <typename... ExpectedHints>
 void assertHints(InlayHintKind Kind, llvm::StringRef AnnotatedSource,
-                 ExpectedHints... Expected) {
-  return assertHintsWithHeader(Kind, AnnotatedSource, "",
+                 InlayHintOptions Opts, ExpectedHints... Expected) {
+  return assertHintsWithHeader(Kind, AnnotatedSource, "", Opts,
                                std::move(Expected)...);
 }
 
@@ -120,14 +123,16 @@ template <typename... ExpectedHints>
 void assertParameterHints(llvm::StringRef AnnotatedSource,
                           ExpectedHints... Expected) {
   ignore(Expected.Side = Left...);
-  assertHints(InlayHintKind::Parameter, AnnotatedSource, Expected...);
+  assertHints(InlayHintKind::Parameter, AnnotatedSource, DefaultOptsForTests,
+              Expected...);
 }
 
 template <typename... ExpectedHints>
 void assertTypeHints(llvm::StringRef AnnotatedSource,
                      ExpectedHints... Expected) {
   ignore(Expected.Side = Right...);
-  assertHints(InlayHintKind::Type, AnnotatedSource, Expected...);
+  assertHints(InlayHintKind::Type, AnnotatedSource, DefaultOptsForTests,
+              Expected...);
 }
 
 template <typename... ExpectedHints>
@@ -136,16 +141,25 @@ void assertDesignatorHints(llvm::StringRef AnnotatedSource,
   Config Cfg;
   Cfg.InlayHints.Designators = true;
   WithContextValue WithCfg(Config::Key, std::move(Cfg));
-  assertHints(InlayHintKind::Designator, AnnotatedSource, Expected...);
+  assertHints(InlayHintKind::Designator, AnnotatedSource, DefaultOptsForTests,
+              Expected...);
 }
 
 template <typename... ExpectedHints>
-void assertBlockEndHints(llvm::StringRef AnnotatedSource,
-                         ExpectedHints... Expected) {
+void assertBlockEndHintsWithOpts(llvm::StringRef AnnotatedSource,
+                                 InlayHintOptions Opts,
+                                 ExpectedHints... Expected) {
   Config Cfg;
   Cfg.InlayHints.BlockEnd = true;
   WithContextValue WithCfg(Config::Key, std::move(Cfg));
-  assertHints(InlayHintKind::BlockEnd, AnnotatedSource, Expected...);
+  assertHints(InlayHintKind::BlockEnd, AnnotatedSource, Opts, Expected...);
+}
+
+template <typename... ExpectedHints>
+void assertBlockEndHints(llvm::StringRef AnnotatedSource,
+                         ExpectedHints... Expected) {
+  assertBlockEndHintsWithOpts(AnnotatedSource, DefaultOptsForTests,
+                              Expected...);
 }
 
 TEST(ParameterHints, Smoke) {
@@ -1226,7 +1240,9 @@ TEST(ParameterHints, IncludeAtNonGlobalScope) {
   ASSERT_TRUE(bool(AST));
 
   // Ensure the hint for the call in foo.inc is NOT materialized in foo.cc.
-  EXPECT_EQ(hintsOfKind(*AST, InlayHintKind::Parameter).size(), 0u);
+  EXPECT_EQ(
+      hintsOfKind(*AST, InlayHintKind::Parameter, DefaultOptsForTests).size(),
+      0u);
 }
 
 TEST(TypeHints, Smoke) {
@@ -1488,12 +1504,12 @@ TEST(DefaultArguments, Smoke) {
     void baz(int = 5) { if (false) baz($unnamed[[)]]; };
   )cpp";
 
-  assertHints(InlayHintKind::DefaultArgument, Code,
+  assertHints(InlayHintKind::DefaultArgument, Code, DefaultOptsForTests,
               ExpectedHint{"A: 4", "default1", Left},
               ExpectedHint{", B: 1, C: foo()", "default2", Left},
               ExpectedHint{"5", "unnamed", Left});
 
-  assertHints(InlayHintKind::Parameter, Code,
+  assertHints(InlayHintKind::Parameter, Code, DefaultOptsForTests,
               ExpectedHint{"A: ", "explicit", Left});
 }
 
@@ -1528,14 +1544,14 @@ TEST(DefaultArguments, WithoutParameterNames) {
     }
   )cpp";
 
-  assertHints(InlayHintKind::DefaultArgument, Code,
+  assertHints(InlayHintKind::DefaultArgument, Code, DefaultOptsForTests,
               ExpectedHint{"...", "abbreviated", Left},
               ExpectedHint{", Baz{}", "paren", Left},
               ExpectedHint{", Baz{}", "brace1", Left},
               ExpectedHint{", Baz{}", "brace2", Left},
               ExpectedHint{", Baz{}", "brace3", Left});
 
-  assertHints(InlayHintKind::Parameter, Code);
+  assertHints(InlayHintKind::Parameter, Code, DefaultOptsForTests);
 }
 
 TEST(TypeHints, Deduplication) {
@@ -1573,7 +1589,8 @@ TEST(TypeHints, Aliased) {
   TU.ExtraArgs.push_back("-xc");
   auto AST = TU.build();
 
-  EXPECT_THAT(hintsOfKind(AST, InlayHintKind::Type), IsEmpty());
+  EXPECT_THAT(hintsOfKind(AST, InlayHintKind::Type, DefaultOptsForTests),
+              IsEmpty());
 }
 
 TEST(TypeHints, CallingConvention) {
@@ -1590,7 +1607,7 @@ TEST(TypeHints, CallingConvention) {
   auto AST = TU.build();
 
   EXPECT_THAT(
-      hintsOfKind(AST, InlayHintKind::Type),
+      hintsOfKind(AST, InlayHintKind::Type, DefaultOptsForTests),
       ElementsAre(HintMatcher(ExpectedHint{"-> void", "lambda"}, Source)));
 }
 
@@ -1673,7 +1690,7 @@ TEST(TypeHints, SubstTemplateParameterAliases) {
   )cpp";
 
   assertHintsWithHeader(
-      InlayHintKind::Type, VectorIntPtr, Header,
+      InlayHintKind::Type, VectorIntPtr, Header, DefaultOptsForTests,
       ExpectedHint{": int *", "no_modifier"},
       ExpectedHint{": int **", "ptr_modifier"},
       ExpectedHint{": int *&", "ref_modifier"},
@@ -1697,7 +1714,7 @@ TEST(TypeHints, SubstTemplateParameterAliases) {
   )cpp";
 
   assertHintsWithHeader(
-      InlayHintKind::Type, VectorInt, Header,
+      InlayHintKind::Type, VectorInt, Header, DefaultOptsForTests,
       ExpectedHint{": int", "no_modifier"},
       ExpectedHint{": int *", "ptr_modifier"},
       ExpectedHint{": int &", "ref_modifier"},
@@ -1724,6 +1741,7 @@ TEST(TypeHints, SubstTemplateParameterAliases) {
   )cpp";
 
   assertHintsWithHeader(InlayHintKind::Type, TypeAlias, Header,
+                        DefaultOptsForTests,
                         ExpectedHint{": Short", "short_name"},
                         ExpectedHint{": static_vector<int>", "vector_name"});
 }
@@ -2016,6 +2034,7 @@ TEST(BlockEndHints, If) {
   assertBlockEndHints(
       R"cpp(
     void foo(bool cond) {
+       void* ptr;
        if (cond)
           ;
 
@@ -2041,13 +2060,17 @@ TEST(BlockEndHints, If) {
 
        if (int i = 0; i > 10) {
        $init_cond[[}]]
+
+       if (ptr != nullptr) {
+       $null_check[[}]]
     } // suppress
   )cpp",
       ExpectedHint{" // if cond", "simple"},
       ExpectedHint{" // if cond", "ifelse"}, ExpectedHint{" // if", "elseif"},
       ExpectedHint{" // if !cond", "inner"},
       ExpectedHint{" // if cond", "outer"}, ExpectedHint{" // if X", "init"},
-      ExpectedHint{" // if i > 10", "init_cond"});
+      ExpectedHint{" // if i > 10", "init_cond"},
+      ExpectedHint{" // if ptr != nullptr", "null_check"});
 }
 
 TEST(BlockEndHints, Loops) {
@@ -2124,30 +2147,41 @@ TEST(BlockEndHints, PrintRefs) {
       R"cpp(
     namespace ns {
       int Var;
-      int func();
+      int func1();
+      int func2(int, int);
       struct S {
         int Field;
-        int method() const;
+        int method1() const;
+        int method2(int, int) const;
       }; // suppress
     } // suppress
     void foo() {
+      int int_a {};
       while (ns::Var) {
       $var[[}]]
 
-      while (ns::func()) {
-      $func[[}]]
+      while (ns::func1()) {
+      $func1[[}]]
+
+      while (ns::func2(int_a, int_a)) {
+      $func2[[}]]
 
       while (ns::S{}.Field) {
       $field[[}]]
 
-      while (ns::S{}.method()) {
-      $method[[}]]
+      while (ns::S{}.method1()) {
+      $method1[[}]]
+      
+      while (ns::S{}.method2(int_a, int_a)) {
+      $method2[[}]]
     } // suppress
   )cpp",
       ExpectedHint{" // while Var", "var"},
-      ExpectedHint{" // while func", "func"},
+      ExpectedHint{" // while func1()", "func1"},
+      ExpectedHint{" // while func2(...)", "func2"},
       ExpectedHint{" // while Field", "field"},
-      ExpectedHint{" // while method", "method"});
+      ExpectedHint{" // while method1()", "method1"},
+      ExpectedHint{" // while method2(...)", "method2"});
 }
 
 TEST(BlockEndHints, PrintConversions) {
@@ -2307,7 +2341,49 @@ TEST(BlockEndHints, PointerToMemberFunction) {
       $ptrmem[[}]]
     } // suppress
   )cpp",
-                      ExpectedHint{" // if", "ptrmem"});
+                      ExpectedHint{" // if ()", "ptrmem"});
+}
+
+TEST(BlockEndHints, MinLineLimit) {
+  InlayHintOptions Opts;
+  Opts.HintMinLineLimit = 10;
+
+  // namespace ns below is exactly 10 lines
+  assertBlockEndHintsWithOpts(
+      R"cpp(
+    namespace ns {
+      int Var;
+      int func1();
+      int func2(int, int);
+      struct S {
+        int Field;
+        int method1() const;
+        int method2(int, int) const;
+      };
+    $namespace[[}]]
+    void foo() {
+      int int_a {};
+      while (ns::Var) {
+      }
+
+      while (ns::func1()) {
+      }
+
+      while (ns::func2(int_a, int_a)) {
+      }
+
+      while (ns::S{}.Field) {
+      }
+
+      while (ns::S{}.method1()) {
+      }
+      
+      while (ns::S{}.method2(int_a, int_a)) {
+      }
+    $foo[[}]]
+  )cpp",
+      Opts, ExpectedHint{" // namespace ns", "namespace"},
+      ExpectedHint{" // foo", "foo"});
 }
 
 // FIXME: Low-hanging fruit where we could omit a type hint:
diff --git a/clang/bindings/python/clang/cindex.py b/clang/bindings/python/clang/cindex.py
index 8dc79f28a090a..a5227df093e73 100644
--- a/clang/bindings/python/clang/cindex.py
+++ b/clang/bindings/python/clang/cindex.py
@@ -3499,6 +3499,14 @@ def __str__(self):
     def __repr__(self):
         return "<File: %s>" % (self.name)
 
+    def __eq__(self, other) -> bool:
+        return isinstance(other, File) and bool(
+            conf.lib.clang_File_isEqual(self, other)
+        )
+
+    def __ne__(self, other) -> bool:
+        return not self.__eq__(other)
+
     @staticmethod
     def from_result(res, arg):
         assert isinstance(res, c_object_p)
@@ -3986,6 +3994,7 @@ def set_property(self, property, value):
     ("clang_getFile", [TranslationUnit, c_interop_string], c_object_p),
     ("clang_getFileName", [File], _CXString),
     ("clang_getFileTime", [File], c_uint),
+    ("clang_File_isEqual", [File, File], bool),
     ("clang_getIBOutletCollectionType", [Cursor], Type),
     ("clang_getIncludedFile", [Cursor], c_object_p),
     (
diff --git a/clang/bindings/python/tests/cindex/INPUTS/a.inc b/clang/bindings/python/tests/cindex/INPUTS/a.inc
new file mode 100644
index 0000000000000..2739d724db3b7
--- /dev/null
+++ b/clang/bindings/python/tests/cindex/INPUTS/a.inc
@@ -0,0 +1 @@
+1, 2, 3
diff --git a/clang/bindings/python/tests/cindex/INPUTS/b.inc b/clang/bindings/python/tests/cindex/INPUTS/b.inc
new file mode 100644
index 0000000000000..2739d724db3b7
--- /dev/null
+++ b/clang/bindings/python/tests/cindex/INPUTS/b.inc
@@ -0,0 +1 @@
+1, 2, 3
diff --git a/clang/bindings/python/tests/cindex/INPUTS/testfile.c b/clang/bindings/python/tests/cindex/INPUTS/testfile.c
new file mode 100644
index 0000000000000..21778bc0b17e7
--- /dev/null
+++ b/clang/bindings/python/tests/cindex/INPUTS/testfile.c
@@ -0,0 +1,6 @@
+int a[] = {
+#include "a.inc"
+};
+int b[] = {
+#include "b.inc"
+};
diff --git a/clang/bindings/python/tests/cindex/test_file.py b/clang/bindings/python/tests/cindex/test_file.py
index 14a3084ee2b47..a8c1dbf558543 100644
--- a/clang/bindings/python/tests/cindex/test_file.py
+++ b/clang/bindings/python/tests/cindex/test_file.py
@@ -1,12 +1,13 @@
 import os
 
-from clang.cindex import Config, File, Index
+from clang.cindex import Config, File, Index, TranslationUnit
 
 if "CLANG_LIBRARY_PATH" in os.environ:
     Config.set_library_path(os.environ["CLANG_LIBRARY_PATH"])
 
 import unittest
 
+inputs_dir = os.path.join(os.path.dirname(__file__), "INPUTS")
 
 class TestFile(unittest.TestCase):
     def test_file(self):
@@ -16,3 +17,54 @@ def test_file(self):
         self.assertEqual(str(file), "t.c")
         self.assertEqual(file.name, "t.c")
         self.assertEqual(repr(file), "<File: t.c>")
+
+    def test_file_eq(self):
+        path = os.path.join(inputs_dir, "testfile.c")
+        path_a = os.path.join(inputs_dir, "a.inc")
+        path_b = os.path.join(inputs_dir, "b.inc")
+        tu = TranslationUnit.from_source(path)
+        main_file = File.from_name(tu, path)
+        a_file = File.from_name(tu, path_a)
+        a_file2 = File.from_name(tu, path_a)
+        b_file = File.from_name(tu, path_b)
+
+        self.assertEqual(a_file, a_file2)
+        self.assertNotEqual(a_file, b_file)
+        self.assertNotEqual(main_file, a_file)
+        self.assertNotEqual(main_file, b_file)
+        self.assertNotEqual(main_file, "t.c")
+
+    def test_file_eq_in_memory(self):
+        tu = TranslationUnit.from_source(
+            "testfile.c",
+            unsaved_files=[
+                (
+                    "testfile.c",
+                    """
+int a[] = { 
+    #include "a.inc"
+};
+int b[] = { 
+    #include "b.inc"
+};
+""",
+                ),
+                ("a.inc", "1,2,3"),
+                ("b.inc", "1,2,3"),
+            ],
+        )
+
+        path = os.path.join(inputs_dir, "testfile.c")
+        path_a = os.path.join(inputs_dir, "a.inc")
+        path_b = os.path.join(inputs_dir, "b.inc")
+        tu = TranslationUnit.from_source(path)
+        main_file = File.from_name(tu, path)
+        a_file = File.from_name(tu, path_a)
+        a_file2 = File.from_name(tu, path_a)
+        b_file = File.from_name(tu, path_b)
+
+        self.assertEqual(a_file, a_file2)
+        self.assertNotEqual(a_file, b_file)
+        self.assertNotEqual(main_file, a_file)
+        self.assertNotEqual(main_file, b_file)
+        self.assertNotEqual(main_file, "a.inc")
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 5ccd346a93b4f..d1f24fb23d44d 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -140,6 +140,9 @@ C Language Changes
 - Clang now allows an ``inline`` specifier on a typedef declaration of a
   function type in Microsoft compatibility mode. #GH124869
 - Clang now allows ``restrict`` qualifier for array types with pointer elements (#GH92847).
+- Added ``-Wimplicit-void-ptr-cast``, grouped under ``-Wc++-compat``, which
+  diagnoses implicit conversion from ``void *`` to another pointer type as
+  being incompatible with C++. (#GH17792)
 
 C2y Feature Support
 ^^^^^^^^^^^^^^^^^^^
@@ -398,6 +401,8 @@ Improvements to Clang's diagnostics
   constructors to initialize their non-modifiable members. The diagnostic is
   not new; being controlled via a warning group is what's new. Fixes #GH41104
 
+- Analysis-based diagnostics (like ``-Wconsumed`` or ``-Wunreachable-code``)
+  can now be correctly controlled by ``#pragma clang diagnostic``. #GH42199
 
 - Improved Clang's error recovery for invalid function calls.
 
@@ -681,6 +686,8 @@ clang-format
 
 libclang
 --------
+- Fixed a bug in ``clang_File_isEqual`` that sometimes led to different 
+  in-memory files to be considered as equal.
 - Added ``clang_visitCXXMethods``, which allows visiting the methods
   of a class.
 - Added ``clang_getFullyQualifiedName``, which provides fully qualified type names as
@@ -743,6 +750,7 @@ Python Binding Changes
   allows visiting the methods of a class.
 - Added ``Type.get_fully_qualified_name``, which provides fully qualified type names as
   instructed by a PrintingPolicy.
+- Add equality comparison operators for ``File`` type
 
 OpenMP Support
 --------------
diff --git a/clang/docs/StandardCPlusPlusModules.rst b/clang/docs/StandardCPlusPlusModules.rst
index 93edce0cf90b7..2ca014f3fd831 100644
--- a/clang/docs/StandardCPlusPlusModules.rst
+++ b/clang/docs/StandardCPlusPlusModules.rst
@@ -305,17 +305,17 @@ Therefore, none of the following names are valid by default:
 Using a reserved module name is strongly discouraged, but
 ``-Wno-reserved-module-identifier`` can be used to suppress the warning.
 
-Specifying dependent BMIs
-~~~~~~~~~~~~~~~~~~~~~~~~~
+Specifying BMI dependencies
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-There are 3 ways to specify a dependent BMI:
+There are 3 ways to specify a BMI dependency:
 
 1. ``-fprebuilt-module-path=<path/to/directory>``.
 2. ``-fmodule-file=<path/to/BMI>`` (Deprecated).
 3. ``-fmodule-file=<module-name>=<path/to/BMI>``.
 
 The ``-fprebuilt-module-path`` option specifies the path to search for
-dependent BMIs. Multiple paths may be specified, similar to using ``-I`` to
+BMI dependencies. Multiple paths may be specified, similar to using ``-I`` to
 specify a search path for header files. When importing a module ``M``, the
 compiler looks for ``M.pcm`` in the directories specified by
 ``-fprebuilt-module-path``. Similarly, when importing a partition module unit
@@ -337,9 +337,8 @@ When these options are specified in the same invocation of the compiler, the
 ``-fmodule-file=<module-name>=<path/to/BMI>``, which takes precedence over
 ``-fprebuilt-module-path=<path/to/directory>``.
 
-Note: all dependant BMIs must be specified explicitly, either directly or
-indirectly dependent BMIs explicitly. See
-https://github.com/llvm/llvm-project/issues/62707 for details.
+Note: all BMI dependencies must be specified explicitly, either directly or
+indirectly. See https://github.com/llvm/llvm-project/issues/62707 for details.
 
 When compiling a ``module implementation unit``, the BMI of the corresponding
 ``primary module interface unit`` must be specified because a module
@@ -380,7 +379,7 @@ For example, the traditional compilation processes for headers are like:
   hdr2.h  --,                                 |
   src2.cpp -+> clang++ src2.cpp --> src2.o ---'
 
-And the compilation process for module units are like:
+And the compilation processes for module units are like:
 
 .. code-block:: text
 
@@ -435,7 +434,7 @@ non-module-unit uses need to be consistent. Consider the following example:
   $ clang++ -std=c++23 Use.cpp -fprebuilt-module-path=.
 
 Clang rejects the example due to the inconsistent language standard modes. Not
-all compiler options are language dialect options, though. For example:
+all compiler options are language-dialect options, though. For example:
 
 .. code-block:: console
 
@@ -465,7 +464,7 @@ translation units.
 Source Files Consistency
 ^^^^^^^^^^^^^^^^^^^^^^^^
 
-Clang may open the input files\ :sup:`1`` of a BMI during the compilation. This implies that
+Clang may open the input files [1]_ of a BMI during the compilation. This implies that
 when Clang consumes a BMI, all the input files need to be present in the original path
 and with the original contents.
 
@@ -477,21 +476,21 @@ When the ``-fmodules-embed-all-files`` flag are enabled, Clang explicitly emits
 code into the BMI file, the contents of the BMI file contain a sufficiently verbose
 representation to reproduce the original source file.
 
-:sup:`1`` Input files: The source files which took part in the compilation of the BMI.
-For example:
+.. [1] Input files: The source files which took part in the compilation of the BMI.
+   For example:
 
-.. code-block:: c++
+   .. code-block:: c++
 
-  // M.cppm
-  module;
-  #include "foo.h"
-  export module M;
+     // M.cppm
+     module;
+     #include "foo.h"
+     export module M;
 
-  // foo.h
-  #pragma once
-  #include "bar.h"
+     // foo.h
+     #pragma once
+     #include "bar.h"
 
-The ``M.cppm``, ``foo.h`` and ``bar.h`` are input files for the BMI of ``M.cppm``.
+   The ``M.cppm``, ``foo.h`` and ``bar.h`` are input files for the BMI of ``M.cppm``.
 
 Object definition consistency
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -781,8 +780,8 @@ for the BMI being produced. This ensures that build systems are not required to
 transitively imported modules when deciding whether to recompile.
 
 What is considered to be a potential contributory BMIs is currently unspecified.
-However, it is a severe bug for a BMI to remain unchanged following an observable change
-that affects its consumers.
+However, it is a severe bug for a BMI to remain unchanged following an
+observable change in the module source files that affects the module consumers.
 
 Build systems may utilize this optimization by doing an update-if-changed operation to the BMI
 that is consumed from the BMI that is output by the compiler.
@@ -1192,14 +1191,14 @@ them to ``your_library_imported.h`` too.
 Importing modules
 ~~~~~~~~~~~~~~~~~
 
-When there are dependent libraries providing modules, they should be imported
-in your module as well. Many existing libraries will fall into this category
-once the ``std`` module is more widely available.
+When there are library dependencies providing modules, the module dependencies
+should be imported in your module as well. Many existing libraries will fall
+into this category once the ``std`` module is more widely available.
 
-All dependent libraries providing modules
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+All library dependencies providing modules
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-Of course, most of the complexity disappears if all the dependent libraries
+Of course, most of the complexity disappears if all the library dependencies
 provide modules.
 
 Headers need to be converted to include third-party headers conditionally. Then,
@@ -1260,8 +1259,8 @@ Non-exported ``using`` declarations are unnecessary if using implementation
 module units. Instead, third-party modules can be imported directly in
 implementation module units.
 
-Partial dependent libraries providing modules
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+Partial library dependencies providing modules
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 If the library has to mix the use of ``include`` and ``import`` in its module,
 the primary goal is still the removal of duplicated declarations in translation
@@ -1562,17 +1561,17 @@ file as a header. For example:
   $ clang++ -std=c++20 -fmodule-header=system -xc++-header iostream -o iostream.pcm
   $ clang++ -std=c++20 -fmodule-file=iostream.pcm use.cpp
 
-How to specify dependent BMIs
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+How to specify BMI dependencies
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-``-fmodule-file`` can be used to specify a dependent BMI (or multiple times for
-more than one dependent BMI).
+``-fmodule-file`` can be used to specify a BMI dependency (or multiple times for
+more than one BMI dependency).
 
 With the existing implementation, ``-fprebuilt-module-path`` cannot be used for
 header units (because they are nominally anonymous). For header units, use
 ``-fmodule-file`` to include the relevant PCM file for each header unit.
 
-This is expect to be solved in a future version of Clang either by the compiler
+This is expected to be solved in a future version of Clang either by the compiler
 finding and specifying ``-fmodule-file`` automatically, or by the use of a
 module-mapper that understands how to map the header name to their PCMs.
 
diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h
index 20ff529c7e0c6..86d43e1a05b55 100644
--- a/clang/include/clang/AST/Type.h
+++ b/clang/include/clang/AST/Type.h
@@ -2793,8 +2793,9 @@ class alignas(TypeAlignment) Type : public ExtQualsTypeCommonBase {
   /// of some sort, e.g., it is a floating-point type or a vector thereof.
   bool hasFloatingRepresentation() const;
 
-  /// Determine whether this type has a boolean representation
-  /// of some sort.
+  /// Determine whether this type has a boolean representation -- i.e., it is a
+  /// boolean type, an enum type whose underlying type is a boolean type, or a
+  /// vector of booleans.
   bool hasBooleanRepresentation() const;
 
   // Type Checking Functions: Check to see if this type is structurally the
diff --git a/clang/include/clang/Basic/BuiltinsAArch64.def b/clang/include/clang/Basic/BuiltinsAArch64.def
index 19fa7215b5000..8867a9fe09fb9 100644
--- a/clang/include/clang/Basic/BuiltinsAArch64.def
+++ b/clang/include/clang/Basic/BuiltinsAArch64.def
@@ -137,7 +137,7 @@ TARGET_BUILTIN(__builtin_arm_st64bv0, "WUiv*WUiC*", "n", "ls64")
 
 // Armv9.3-A Guarded Control Stack
 TARGET_BUILTIN(__builtin_arm_gcspopm, "WUiWUi", "n", "gcs")
-TARGET_BUILTIN(__builtin_arm_gcsss, "vC*vC*", "n", "gcs")
+TARGET_BUILTIN(__builtin_arm_gcsss, "v*v*", "n", "gcs")
 
 TARGET_HEADER_BUILTIN(_BitScanForward, "UcUNi*UNi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_BitScanReverse, "UcUNi*UNi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
diff --git a/clang/include/clang/Basic/DiagnosticDriverKinds.td b/clang/include/clang/Basic/DiagnosticDriverKinds.td
index c69ad3adc5b3b..b15cba698030c 100644
--- a/clang/include/clang/Basic/DiagnosticDriverKinds.td
+++ b/clang/include/clang/Basic/DiagnosticDriverKinds.td
@@ -396,8 +396,14 @@ def err_drv_print_header_env_var : Error<
   "environment variable CC_PRINT_HEADERS_%select{FORMAT|FILTERING}0 has invalid value %1">;
 def err_drv_print_header_env_var_combination : Error<
   "unsupported combination: CC_PRINT_HEADERS_FORMAT=%0 and CC_PRINT_HEADERS_FILTERING=%1">;
-def err_drv_print_header_env_var_combination_cc1 : Error<
+def err_drv_print_header_env_var_invalid_format : Error<
+  "environment variable CC_PRINT_HEADERS_FORMAT=%0 requires a compatible value for CC_PRINT_HEADERS_FILTERING">;
+def err_drv_print_header_cc1_invalid_combination : Error<
   "unsupported combination: -header-include-format=%0 and -header-include-filtering=%1">;
+def err_drv_print_header_cc1_invalid_filtering : Error<
+  "-header-include-filtering=%0 requires a compatible value for -header-include-format">;
+def err_drv_print_header_cc1_invalid_format : Error<
+  "-header-include-format=%0 requires a compatible value for -header-include-filtering">;
 
 def warn_O4_is_O3 : Warning<"-O4 is equivalent to -O3">, InGroup<Deprecated>;
 def warn_drv_optimization_value : Warning<"optimization level '%0' is not supported; using '%1%2' instead">,
diff --git a/clang/include/clang/Basic/DiagnosticGroups.td b/clang/include/clang/Basic/DiagnosticGroups.td
index 59036b695da85..6441b8049ed8d 100644
--- a/clang/include/clang/Basic/DiagnosticGroups.td
+++ b/clang/include/clang/Basic/DiagnosticGroups.td
@@ -155,7 +155,8 @@ def C99Compat : DiagGroup<"c99-compat">;
 def C23Compat : DiagGroup<"c23-compat">;
 def : DiagGroup<"c2x-compat", [C23Compat]>;
 
-def CXXCompat: DiagGroup<"c++-compat">;
+def ImplicitVoidPtrCast : DiagGroup<"implicit-void-ptr-cast">;
+def CXXCompat: DiagGroup<"c++-compat", [ImplicitVoidPtrCast]>;
 def ExternCCompat : DiagGroup<"extern-c-compat">;
 def KeywordCompat : DiagGroup<"keyword-compat">;
 def GNUCaseRange : DiagGroup<"gnu-case-range">;
diff --git a/clang/include/clang/Basic/DiagnosticParseKinds.td b/clang/include/clang/Basic/DiagnosticParseKinds.td
index 9975520f4f9ff..72e765bcb800d 100644
--- a/clang/include/clang/Basic/DiagnosticParseKinds.td
+++ b/clang/include/clang/Basic/DiagnosticParseKinds.td
@@ -1836,8 +1836,11 @@ def err_hlsl_virtual_function
 def err_hlsl_virtual_inheritance
     : Error<"virtual inheritance is unsupported in HLSL">;
 
-// HLSL Root Siganture diagnostic messages
+// HLSL Root Signature Parser Diagnostics
 def err_hlsl_unexpected_end_of_params
     : Error<"expected %0 to denote end of parameters, or, another valid parameter of %1">;
+def err_hlsl_rootsig_repeat_param : Error<"specified the same parameter '%0' multiple times">;
+def err_hlsl_rootsig_missing_param : Error<"did not specify mandatory parameter '%0'">;
+def err_hlsl_number_literal_overflow : Error<"integer literal is too large to be represented as a 32-bit %select{signed |}0 integer type">;
 
 } // end of Parser diagnostics
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index c562802efba57..8ff170520aafe 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -8687,7 +8687,17 @@ def err_typecheck_missing_return_type_incompatible : Error<
   "%diff{return type $ must match previous return type $|"
   "return type must match previous return type}0,1 when %select{block "
   "literal|lambda expression}2 has unspecified explicit return type">;
-
+def warn_compatible_implicit_pointer_conv : Warning<
+  "implicit conversion when %select{"
+  "%diff{assigning to $ from type $|assigning to type from type}0,1|"
+  "%diff{passing $ to parameter of type $|passing type to parameter of type}0,1|"
+  "%diff{returning $ from a function with result type $|returning type from a function with result type}0,1|"
+  "<CLANG BUG IF YOU SEE THIS>|" // converting
+  "%diff{initializing $ with an expression of type $|initializing type with an expression of type}0,1|"
+  "%diff{sending $ to parameter of type $|sending type to parameter of type}0,1|"
+  "<CLANG BUG IF YOU SEE THIS>" // casting
+  "}2 is not permitted in C++">,
+  InGroup<ImplicitVoidPtrCast>, DefaultIgnore;
 def note_incomplete_class_and_qualified_id : Note<
   "conformance of forward class %0 to protocol %1 cannot be confirmed">;
 def warn_incompatible_qualified_id : Warning<
diff --git a/clang/include/clang/Basic/arm_sme.td b/clang/include/clang/Basic/arm_sme.td
index 3647fc7a27d83..c491eb0f7e460 100644
--- a/clang/include/clang/Basic/arm_sme.td
+++ b/clang/include/clang/Basic/arm_sme.td
@@ -321,6 +321,24 @@ let SMETargetGuard = "sme2,sme-mop4,sme-b16b16" in {
   defm SVBMOP4S_H : MOP4<"s", "_za16", "b", "aarch64_sme_mop4s", [ImmCheck<0, ImmCheck0_1>]>;
 }
 
+////////////////////////////////////////////////////////////////////////////////
+// SME2 - FP8 FMOP4A, FMOP4S
+
+multiclass MOP4_FP8<string za, list<ImmCheck> checks> {
+  def _1x1 : Inst<"svmop4a" # "[_1x1]" # za # "[_{d}_{d}]", "vidd>", "m", MergeNone, "aarch64_sme_fp8_fmop4a" # za # "_1x1", [IsInOutZA, IsStreaming], checks>;
+  def _1x2 : Inst<"svmop4a" # "[_1x2]" # za # "[_{d}_{d}]", "vid2>", "m", MergeNone, "aarch64_sme_fp8_fmop4a" # za # "_1x2", [IsInOutZA, IsStreaming], checks>;
+  def _2x1 : Inst<"svmop4a" # "[_2x1]" # za # "[_{d}_{d}]", "vi2d>", "m", MergeNone, "aarch64_sme_fp8_fmop4a" # za # "_2x1", [IsInOutZA, IsStreaming], checks>;
+  def _2x2 : Inst<"svmop4a" # "[_2x2]" # za # "[_{d}_{d}]", "vi22>", "m", MergeNone, "aarch64_sme_fp8_fmop4a" # za # "_2x2", [IsInOutZA, IsStreaming], checks>;
+}
+
+let SMETargetGuard = "sme2,sme-mop4,sme-f8f32" in {
+  defm SVMOP4A_FP8_ZA32 : MOP4_FP8<"_za32", [ImmCheck<0, ImmCheck0_3>]>;
+}
+
+let SMETargetGuard = "sme2,sme-mop4,sme-f8f16" in {
+  defm SVMOP4A_FP8_ZA16 : MOP4_FP8<"_za16", [ImmCheck<0, ImmCheck0_1>]>;
+}
+
 ////////////////////////////////////////////////////////////////////////////////
 // SME2 - SMOP4A, SMOP4S, UMOP4A, UMOP4S
 
diff --git a/clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h b/clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
index 539268c6270f4..ef29791ed2783 100644
--- a/clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
+++ b/clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
@@ -166,8 +166,7 @@ class CIRBaseBuilderTy : public mlir::OpBuilder {
   mlir::TypedAttr getConstPtrAttr(mlir::Type type, int64_t value) {
     auto valueAttr = mlir::IntegerAttr::get(
         mlir::IntegerType::get(type.getContext(), 64), value);
-    return cir::ConstPtrAttr::get(
-        getContext(), mlir::cast<cir::PointerType>(type), valueAttr);
+    return cir::ConstPtrAttr::get(type, valueAttr);
   }
 
   mlir::Value createAlloca(mlir::Location loc, cir::PointerType addrType,
diff --git a/clang/include/clang/CIR/Dialect/IR/CIRAttrs.td b/clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
index 293b83e70eff7..fb3f7b1632436 100644
--- a/clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
+++ b/clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
@@ -27,6 +27,20 @@ class CIR_Attr<string name, string attrMnemonic, list<Trait> traits = []>
   let mnemonic = attrMnemonic;
 }
 
+class CIR_TypedAttr<string name, string attrMnemonic, list<Trait> traits = []>
+    : CIR_Attr<name, attrMnemonic, !listconcat(traits, [TypedAttrInterface])> {
+
+  let parameters = (ins AttributeSelfTypeParameter<"">:$type);
+
+  let builders = [
+    AttrBuilderWithInferredContext<(ins "mlir::Type":$type), [{
+      return $_get(type.getContext(), type);
+    }]>
+  ];
+
+  let assemblyFormat = [{}];
+}
+
 class CIRUnitAttr<string name, string attrMnemonic, list<Trait> traits = []>
     : CIR_Attr<name, attrMnemonic, traits> {
   let returnType = "bool";
@@ -64,43 +78,23 @@ def CIR_BoolAttr : CIR_Attr<"Bool", "bool", [TypedAttrInterface]> {
 // ZeroAttr
 //===----------------------------------------------------------------------===//
 
-def ZeroAttr : CIR_Attr<"Zero", "zero", [TypedAttrInterface]> {
+def ZeroAttr : CIR_TypedAttr<"Zero", "zero"> {
   let summary = "Attribute to represent zero initialization";
   let description = [{
     The ZeroAttr is used to indicate zero initialization on structs.
   }];
-
-  let parameters = (ins AttributeSelfTypeParameter<"">:$type);
-
-  let builders = [
-    AttrBuilderWithInferredContext<(ins "mlir::Type":$type), [{
-      return $_get(type.getContext(), type);
-    }]>
-  ];
-
-  let assemblyFormat = [{}];
 }
 
 //===----------------------------------------------------------------------===//
 // UndefAttr
 //===----------------------------------------------------------------------===//
 
-def UndefAttr : CIR_Attr<"Undef", "undef", [TypedAttrInterface]> {
+def UndefAttr : CIR_TypedAttr<"Undef", "undef"> {
   let summary = "Represent an undef constant";
   let description = [{
     The UndefAttr represents an undef constant, corresponding to LLVM's notion
     of undef.
   }];
-
-  let parameters = (ins AttributeSelfTypeParameter<"">:$type);
-
-  let builders = [
-    AttrBuilderWithInferredContext<(ins "mlir::Type":$type), [{
-      return $_get(type.getContext(), type);
-    }]>
-  ];
-
-  let assemblyFormat = [{}];
 }
 
 //===----------------------------------------------------------------------===//
@@ -202,6 +196,11 @@ def ConstArrayAttr : CIR_Attr<"ConstArray", "const_array", [TypedAttrInterface]>
         zeros = typeSize - mlir::cast<mlir::ArrayAttr>(elts).size();
 
       return $_get(type.getContext(), type, elts, zeros);
+    }]>,
+    AttrBuilderWithInferredContext<(ins "cir::ArrayType":$type,
+                                        "mlir::Attribute":$elts,
+                                        "int":$trailingZerosNum), [{
+      return $_get(type.getContext(), type, elts, trailingZerosNum);
     }]>
   ];
 
@@ -234,11 +233,7 @@ def ConstPtrAttr : CIR_Attr<"ConstPtr", "ptr", [TypedAttrInterface]> {
                                         "mlir::IntegerAttr":$value), [{
       return $_get(type.getContext(), mlir::cast<cir::PointerType>(type),
                    value);
-    }]>,
-    AttrBuilder<(ins "mlir::Type":$type,
-                     "mlir::IntegerAttr":$value), [{
-      return $_get($_ctxt, mlir::cast<cir::PointerType>(type), value);
-    }]>,
+    }]>
   ];
   let extraClassDeclaration = [{
     bool isNullValue() const { return getValue().getInt() == 0; }
diff --git a/clang/include/clang/Frontend/CompilerInstance.h b/clang/include/clang/Frontend/CompilerInstance.h
index 6007d5659c6b4..8c91a2a86cfcd 100644
--- a/clang/include/clang/Frontend/CompilerInstance.h
+++ b/clang/include/clang/Frontend/CompilerInstance.h
@@ -16,6 +16,7 @@
 #include "clang/Frontend/CompilerInvocation.h"
 #include "clang/Frontend/PCHContainerOperations.h"
 #include "clang/Frontend/Utils.h"
+#include "clang/Lex/DependencyDirectivesScanner.h"
 #include "clang/Lex/HeaderSearchOptions.h"
 #include "clang/Lex/ModuleLoader.h"
 #include "llvm/ADT/ArrayRef.h"
@@ -99,6 +100,9 @@ class CompilerInstance : public ModuleLoader {
   /// The cache of PCM files.
   IntrusiveRefCntPtr<ModuleCache> ModCache;
 
+  /// Functor for getting the dependency preprocessor directives of a file.
+  std::unique_ptr<DependencyDirectivesGetter> GetDependencyDirectives;
+
   /// The preprocessor.
   std::shared_ptr<Preprocessor> PP;
 
@@ -697,6 +701,11 @@ class CompilerInstance : public ModuleLoader {
   /// and replace any existing one with it.
   void createPreprocessor(TranslationUnitKind TUKind);
 
+  void setDependencyDirectivesGetter(
+      std::unique_ptr<DependencyDirectivesGetter> Getter) {
+    GetDependencyDirectives = std::move(Getter);
+  }
+
   std::string getSpecificModuleCachePath(StringRef ModuleHash);
   std::string getSpecificModuleCachePath() {
     return getSpecificModuleCachePath(getInvocation().getModuleHash());
diff --git a/clang/include/clang/Lex/DependencyDirectivesScanner.h b/clang/include/clang/Lex/DependencyDirectivesScanner.h
index 0e115906fbfe5..acdc9e2bf9aa4 100644
--- a/clang/include/clang/Lex/DependencyDirectivesScanner.h
+++ b/clang/include/clang/Lex/DependencyDirectivesScanner.h
@@ -21,6 +21,7 @@
 #include "llvm/ADT/ArrayRef.h"
 
 namespace clang {
+class FileManager;
 
 namespace tok {
 enum TokenKind : unsigned short;
@@ -135,6 +136,19 @@ void printDependencyDirectivesAsSource(
     ArrayRef<dependency_directives_scan::Directive> Directives,
     llvm::raw_ostream &OS);
 
+/// Functor that returns the dependency directives for a given file.
+class DependencyDirectivesGetter {
+public:
+  /// Clone the getter for a new \c FileManager instance.
+  virtual std::unique_ptr<DependencyDirectivesGetter>
+  cloneFor(FileManager &FileMgr) = 0;
+
+  /// Get the dependency directives for the given file.
+  virtual std::optional<ArrayRef<dependency_directives_scan::Directive>>
+  operator()(FileEntryRef File) = 0;
+
+  virtual ~DependencyDirectivesGetter() = default;
+};
 } // end namespace clang
 
 #endif // LLVM_CLANG_LEX_DEPENDENCYDIRECTIVESSCANNER_H
diff --git a/clang/include/clang/Lex/Preprocessor.h b/clang/include/clang/Lex/Preprocessor.h
index 10260c61bdf11..f2dfd3a349b8b 100644
--- a/clang/include/clang/Lex/Preprocessor.h
+++ b/clang/include/clang/Lex/Preprocessor.h
@@ -140,6 +140,12 @@ class Preprocessor {
   friend class VariadicMacroScopeGuard;
 
   llvm::unique_function<void(const clang::Token &)> OnToken;
+  /// Functor for getting the dependency preprocessor directives of a file.
+  ///
+  /// These are directives derived from a special form of lexing where the
+  /// source input is scanned for the preprocessor directives that might have an
+  /// effect on the dependencies for a compilation unit.
+  DependencyDirectivesGetter *GetDependencyDirectives = nullptr;
   const PreprocessorOptions &PPOpts;
   DiagnosticsEngine        *Diags;
   const LangOptions &LangOpts;
@@ -1326,6 +1332,10 @@ class Preprocessor {
     OnToken = std::move(F);
   }
 
+  void setDependencyDirectivesGetter(DependencyDirectivesGetter &Get) {
+    GetDependencyDirectives = &Get;
+  }
+
   void setPreprocessToken(bool Preprocess) { PreprocessToken = Preprocess; }
 
   bool isMacroDefined(StringRef Id) {
diff --git a/clang/include/clang/Lex/PreprocessorOptions.h b/clang/include/clang/Lex/PreprocessorOptions.h
index c2e3d68333024..d4c4e1ccbf2c4 100644
--- a/clang/include/clang/Lex/PreprocessorOptions.h
+++ b/clang/include/clang/Lex/PreprocessorOptions.h
@@ -189,19 +189,6 @@ class PreprocessorOptions {
   /// with support for lifetime-qualified pointers.
   ObjCXXARCStandardLibraryKind ObjCXXARCStandardLibrary = ARCXX_nolib;
 
-  /// Function for getting the dependency preprocessor directives of a file.
-  ///
-  /// These are directives derived from a special form of lexing where the
-  /// source input is scanned for the preprocessor directives that might have an
-  /// effect on the dependencies for a compilation unit.
-  ///
-  /// Enables a client to cache the directives for a file and provide them
-  /// across multiple compiler invocations.
-  /// FIXME: Allow returning an error.
-  std::function<std::optional<ArrayRef<dependency_directives_scan::Directive>>(
-      FileEntryRef)>
-      DependencyDirectivesForFile;
-
   /// Set up preprocessor for RunAnalysis action.
   bool SetUpStaticAnalyzer = false;
 
diff --git a/clang/include/clang/Parse/ParseHLSLRootSignature.h b/clang/include/clang/Parse/ParseHLSLRootSignature.h
index a8dd6b02501ae..d9f121030c1fc 100644
--- a/clang/include/clang/Parse/ParseHLSLRootSignature.h
+++ b/clang/include/clang/Parse/ParseHLSLRootSignature.h
@@ -40,34 +40,57 @@ class RootSignatureParser {
 private:
   DiagnosticsEngine &getDiags() { return PP.getDiagnostics(); }
 
-  // All private Parse.* methods follow a similar pattern:
+  // All private parse.* methods follow a similar pattern:
   //   - Each method will start with an assert to denote what the CurToken is
   // expected to be and will parse from that token forward
   //
   //   - Therefore, it is the callers responsibility to ensure that you are
   // at the correct CurToken. This should be done with the pattern of:
   //
-  //  if (TryConsumeExpectedToken(RootSignatureToken::Kind))
-  //    if (Parse.*())
-  //      return true;
+  //  if (tryConsumeExpectedToken(RootSignatureToken::Kind)) {
+  //    auto ParsedObject = parse.*();
+  //    if (!ParsedObject.has_value())
+  //      return std::nullopt;
+  //    ...
+  // }
   //
   // or,
   //
-  //  if (ConsumeExpectedToken(RootSignatureToken::Kind, ...))
-  //    return true;
-  //  if (Parse.*())
-  //    return true;
+  //  if (consumeExpectedToken(RootSignatureToken::Kind, ...))
+  //    return std::nullopt;
+  //  auto ParsedObject = parse.*();
+  //  if (!ParsedObject.has_value())
+  //    return std::nullopt;
+  //  ...
   //
-  //   - All methods return true if a parsing error is encountered. It is the
-  // callers responsibility to propogate this error up, or deal with it
+  //   - All methods return std::nullopt if a parsing error is encountered. It
+  // is the callers responsibility to propogate this error up, or deal with it
   // otherwise
   //
   //   - An error will be raised if the proceeding tokens are not what is
   // expected, or, there is a lexing error
 
   /// Root Element parse methods:
-  bool parseDescriptorTable();
-  bool parseDescriptorTableClause();
+  std::optional<llvm::hlsl::rootsig::DescriptorTable> parseDescriptorTable();
+  std::optional<llvm::hlsl::rootsig::DescriptorTableClause>
+  parseDescriptorTableClause();
+
+  /// Parameter arguments (eg. `bReg`, `space`, ...) can be specified in any
+  /// order and only exactly once. `ParsedClauseParams` denotes the current
+  /// state of parsed params
+  struct ParsedClauseParams {
+    std::optional<llvm::hlsl::rootsig::Register> Reg;
+    std::optional<uint32_t> Space;
+  };
+  std::optional<ParsedClauseParams>
+  parseDescriptorTableClauseParams(RootSignatureToken::Kind RegType);
+
+  std::optional<uint32_t> parseUIntParam();
+  std::optional<llvm::hlsl::rootsig::Register> parseRegister();
+
+  /// Use NumericLiteralParser to convert CurToken.NumSpelling into a unsigned
+  /// 32-bit integer
+  std::optional<uint32_t> handleUIntLiteral();
 
   /// Invoke the Lexer to consume a token and update CurToken with the result
   void consumeNextToken() { CurToken = Lexer.consumeToken(); }
diff --git a/clang/include/clang/Sema/AnalysisBasedWarnings.h b/clang/include/clang/Sema/AnalysisBasedWarnings.h
index aafe227b84084..4103c3f006a8f 100644
--- a/clang/include/clang/Sema/AnalysisBasedWarnings.h
+++ b/clang/include/clang/Sema/AnalysisBasedWarnings.h
@@ -25,6 +25,7 @@ class QualType;
 class Sema;
 namespace sema {
   class FunctionScopeInfo;
+  class SemaPPCallbacks;
 }
 
 namespace sema {
@@ -33,6 +34,7 @@ class AnalysisBasedWarnings {
 public:
   class Policy {
     friend class AnalysisBasedWarnings;
+    friend class SemaPPCallbacks;
     // The warnings to run.
     LLVM_PREFERRED_TYPE(bool)
     unsigned enableCheckFallThrough : 1;
@@ -49,7 +51,6 @@ class AnalysisBasedWarnings {
 
 private:
   Sema &S;
-  Policy DefaultPolicy;
 
   class InterProceduralData;
   std::unique_ptr<InterProceduralData> IPData;
@@ -57,6 +58,9 @@ class AnalysisBasedWarnings {
   enum VisitFlag { NotVisited = 0, Visited = 1, Pending = 2 };
   llvm::DenseMap<const FunctionDecl*, VisitFlag> VisitedFD;
 
+  Policy PolicyOverrides;
+  void clearOverrides();
+
   /// \name Statistics
   /// @{
 
@@ -103,7 +107,13 @@ class AnalysisBasedWarnings {
   // Issue warnings that require whole-translation-unit analysis.
   void IssueWarnings(TranslationUnitDecl *D);
 
-  Policy getDefaultPolicy() { return DefaultPolicy; }
+  // Gets the default policy which is in effect at the given source location.
+  Policy getPolicyInEffectAt(SourceLocation Loc);
+
+  // Get the policies we may want to override due to things like #pragma clang
+  // diagnostic handling. If a caller sets any of these policies to true, that
+  // will override the policy used to issue warnings.
+  Policy &getPolicyOverrides() { return PolicyOverrides; }
 
   void PrintStats() const;
 };
diff --git a/clang/include/clang/Sema/ScopeInfo.h b/clang/include/clang/Sema/ScopeInfo.h
index 958d65055fa9b..6bf9ae8d074fb 100644
--- a/clang/include/clang/Sema/ScopeInfo.h
+++ b/clang/include/clang/Sema/ScopeInfo.h
@@ -949,6 +949,9 @@ class LambdaScopeInfo final :
 
   SourceLocation PotentialThisCaptureLocation;
 
+  /// Variables that are potentially ODR-used in CUDA/HIP.
+  llvm::SmallPtrSet<VarDecl *, 4> CUDAPotentialODRUsedVars;
+
   LambdaScopeInfo(DiagnosticsEngine &Diag)
       : CapturingScopeInfo(Diag, ImpCap_None) {
     Kind = SK_Lambda;
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 96d81e618494a..0c77c5b5ca30a 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -7786,6 +7786,11 @@ class Sema final : public SemaBase {
     /// Compatible - the types are compatible according to the standard.
     Compatible,
 
+    /// CompatibleVoidPtrToNonVoidPtr - The types are compatible in C because
+    /// a void * can implicitly convert to another pointer type, which we
+    /// differentiate for better diagnostic behavior.
+    CompatibleVoidPtrToNonVoidPtr,
+
     /// PointerToInt - The assignment converts a pointer to an int, which we
     /// accept as an extension.
     PointerToInt,
@@ -7866,6 +7871,18 @@ class Sema final : public SemaBase {
     Incompatible
   };
 
+  bool IsAssignConvertCompatible(AssignConvertType ConvTy) {
+    switch (ConvTy) {
+    default:
+      return false;
+    case Compatible:
+    case CompatiblePointerDiscardsQualifiers:
+    case CompatibleVoidPtrToNonVoidPtr:
+      return true;
+    }
+    llvm_unreachable("impossible");
+  }
+
   /// DiagnoseAssignmentResult - Emit a diagnostic, if required, for the
   /// assignment conversion type specified by ConvTy.  This returns true if the
   /// conversion was invalid or false if the conversion was accepted.
diff --git a/clang/include/clang/Sema/SemaCUDA.h b/clang/include/clang/Sema/SemaCUDA.h
index 71f05e88fb539..dbc1432860d89 100644
--- a/clang/include/clang/Sema/SemaCUDA.h
+++ b/clang/include/clang/Sema/SemaCUDA.h
@@ -274,6 +274,10 @@ class SemaCUDA : public SemaBase {
   /// parameters specified via <<<>>>.
   std::string getConfigureFuncName() const;
 
+  /// Record variables that are potentially ODR-used in CUDA/HIP.
+  void recordPotentialODRUsedVariable(MultiExprArg Args,
+                                      OverloadCandidateSet &CandidateSet);
+
 private:
   unsigned ForceHostDeviceDepth = 0;
 
diff --git a/clang/include/clang/Tooling/DependencyScanning/DependencyScanningFilesystem.h b/clang/include/clang/Tooling/DependencyScanning/DependencyScanningFilesystem.h
index 74b40f7452edb..a20a89a4c2b76 100644
--- a/clang/include/clang/Tooling/DependencyScanning/DependencyScanningFilesystem.h
+++ b/clang/include/clang/Tooling/DependencyScanning/DependencyScanningFilesystem.h
@@ -379,6 +379,16 @@ class DependencyScanningWorkerFilesystem
   /// false if not (i.e. this entry is not a file or its scan fails).
   bool ensureDirectiveTokensArePopulated(EntryRef Entry);
 
+  /// \returns The scanned preprocessor directive tokens of the file that are
+  /// used to speed up preprocessing, if available.
+  std::optional<ArrayRef<dependency_directives_scan::Directive>>
+  getDirectiveTokens(const Twine &Path) {
+    if (llvm::ErrorOr<EntryRef> Entry = getOrCreateFileSystemEntry(Path.str()))
+      if (ensureDirectiveTokensArePopulated(*Entry))
+        return Entry->getDirectiveTokens();
+    return std::nullopt;
+  }
+
   /// Check whether \p Path exists. By default checks cached result of \c
   /// status(), and falls back on FS if unable to do so.
   bool exists(const Twine &Path) override;
diff --git a/clang/lib/AST/ByteCode/Compiler.cpp b/clang/lib/AST/ByteCode/Compiler.cpp
index 7cba0e8a4da19..65d87cdff6ad2 100644
--- a/clang/lib/AST/ByteCode/Compiler.cpp
+++ b/clang/lib/AST/ByteCode/Compiler.cpp
@@ -210,6 +210,9 @@ bool Compiler<Emitter>::VisitCastExpr(const CastExpr *CE) {
 
   switch (CE->getCastKind()) {
   case CK_LValueToRValue: {
+    if (SubExpr->getType().isVolatileQualified())
+      return this->emitInvalidCast(CastKind::Volatile, /*Fatal=*/true, CE);
+
     std::optional<PrimType> SubExprT = classify(SubExpr->getType());
     // Prepare storage for the result.
     if (!Initializing && !SubExprT) {
diff --git a/clang/lib/AST/ByteCode/Interp.cpp b/clang/lib/AST/ByteCode/Interp.cpp
index b755a072fec88..6f277a7488836 100644
--- a/clang/lib/AST/ByteCode/Interp.cpp
+++ b/clang/lib/AST/ByteCode/Interp.cpp
@@ -641,11 +641,30 @@ static bool CheckVolatile(InterpState &S, CodePtr OpPC, const Pointer &Ptr,
   if (!PtrType.isVolatileQualified())
     return true;
 
-  const SourceInfo &Loc = S.Current->getSource(OpPC);
-  if (S.getLangOpts().CPlusPlus)
-    S.FFDiag(Loc, diag::note_constexpr_access_volatile_type) << AK << PtrType;
-  else
-    S.FFDiag(Loc);
+  if (!S.getLangOpts().CPlusPlus)
+    return Invalid(S, OpPC);
+
+  const NamedDecl *ND = nullptr;
+  int DiagKind;
+  SourceLocation Loc;
+  if (const auto *F = Ptr.getField()) {
+    DiagKind = 2;
+    Loc = F->getLocation();
+    ND = F;
+  } else if (auto *VD = Ptr.getFieldDesc()->asValueDecl()) {
+    DiagKind = 1;
+    Loc = VD->getLocation();
+    ND = VD;
+  } else {
+    DiagKind = 0;
+    if (const auto *E = Ptr.getFieldDesc()->asExpr())
+      Loc = E->getExprLoc();
+  }
+
+  S.FFDiag(S.Current->getLocation(OpPC),
+           diag::note_constexpr_access_volatile_obj, 1)
+      << AK << DiagKind << ND;
+  S.Note(Loc, diag::note_constexpr_volatile_here) << DiagKind;
   return false;
 }
 
diff --git a/clang/lib/AST/ByteCode/Interp.h b/clang/lib/AST/ByteCode/Interp.h
index 866d8e4bf2251..0a52a64240c04 100644
--- a/clang/lib/AST/ByteCode/Interp.h
+++ b/clang/lib/AST/ByteCode/Interp.h
@@ -1007,6 +1007,19 @@ inline bool CmpHelper<Pointer>(InterpState &S, CodePtr OpPC, CompareFn Fn) {
     return false;
   }
 
+  // Diagnose comparisons between fields with different access specifiers.
+  if (std::optional<std::pair<Pointer, Pointer>> Split =
+          Pointer::computeSplitPoint(LHS, RHS)) {
+    const FieldDecl *LF = Split->first.getField();
+    const FieldDecl *RF = Split->second.getField();
+    if (LF && RF && !LF->getParent()->isUnion() &&
+        LF->getAccess() != RF->getAccess()) {
+      S.CCEDiag(S.Current->getSource(OpPC),
+                diag::note_constexpr_pointer_comparison_differing_access)
+          << LF << LF->getAccess() << RF << RF->getAccess() << LF->getParent();
+    }
+  }
+
   unsigned VL = LHS.getByteOffset();
   unsigned VR = RHS.getByteOffset();
   S.Stk.push<BoolT>(BoolT::from(Fn(Compare(VL, VR))));
@@ -1113,6 +1126,12 @@ inline bool CmpHelperEQ<Pointer>(InterpState &S, CodePtr OpPC, CompareFn Fn) {
             << P.toDiagnosticString(S.getASTContext());
         return false;
       }
+    } else if (BothNonNull && P.isIntegralPointer()) {
+      const SourceInfo &Loc = S.Current->getSource(OpPC);
+      S.FFDiag(Loc, diag::note_constexpr_pointer_constant_comparison)
+          << LHS.toDiagnosticString(S.getASTContext())
+          << RHS.toDiagnosticString(S.getASTContext());
+      return false;
     }
   }
 
@@ -2155,16 +2174,22 @@ inline bool SubPtr(InterpState &S, CodePtr OpPC) {
     }
   }
 
-  T A = LHS.isBlockPointer()
-            ? (LHS.isElementPastEnd() ? T::from(LHS.getNumElems())
-                                      : T::from(LHS.getIndex()))
-            : T::from(LHS.getIntegerRepresentation());
-  T B = RHS.isBlockPointer()
-            ? (RHS.isElementPastEnd() ? T::from(RHS.getNumElems())
-                                      : T::from(RHS.getIndex()))
-            : T::from(RHS.getIntegerRepresentation());
+  int64_t A64 =
+      LHS.isBlockPointer()
+          ? (LHS.isElementPastEnd() ? LHS.getNumElems() : LHS.getIndex())
+          : LHS.getIntegerRepresentation();
+
+  int64_t B64 =
+      RHS.isBlockPointer()
+          ? (RHS.isElementPastEnd() ? RHS.getNumElems() : RHS.getIndex())
+          : RHS.getIntegerRepresentation();
 
-  return AddSubMulHelper<T, T::sub, std::minus>(S, OpPC, A.bitWidth(), A, B);
+  int64_t R64 = A64 - B64;
+  if (static_cast<int64_t>(T::from(R64)) != R64)
+    return handleOverflow(S, OpPC, R64);
+
+  S.Stk.push<T>(T::from(R64));
+  return true;
 }
 
 //===----------------------------------------------------------------------===//
@@ -2389,7 +2414,18 @@ static inline bool PtrPtrCast(InterpState &S, CodePtr OpPC, bool SrcIsVoidPtr) {
     bool HasValidResult = !Ptr.isZero();
 
     if (HasValidResult) {
-      // FIXME: note_constexpr_invalid_void_star_cast
+      if (S.getStdAllocatorCaller("allocate"))
+        return true;
+
+      const auto &E = cast<CastExpr>(S.Current->getExpr(OpPC));
+      if (S.getLangOpts().CPlusPlus26 &&
+          S.getASTContext().hasSimilarType(Ptr.getType(),
+                                           E->getType()->getPointeeType()))
+        return true;
+
+      S.CCEDiag(E, diag::note_constexpr_invalid_void_star_cast)
+          << E->getSubExpr()->getType() << S.getLangOpts().CPlusPlus26
+          << Ptr.getType().getCanonicalType() << E->getType()->getPointeeType();
     } else if (!S.getLangOpts().CPlusPlus26) {
       const SourceInfo &E = S.Current->getSource(OpPC);
       S.CCEDiag(E, diag::note_constexpr_invalid_cast)
@@ -2781,10 +2817,9 @@ template <PrimType Name, class T = typename PrimConv<Name>::T>
 inline bool GetIntPtr(InterpState &S, CodePtr OpPC, const Descriptor *Desc) {
   const T &IntVal = S.Stk.pop<T>();
 
-  if (Desc)
-    S.CCEDiag(S.Current->getSource(OpPC), diag::note_constexpr_invalid_cast)
-        << diag::ConstexprInvalidCastKind::ThisConversionOrReinterpret
-        << S.getLangOpts().CPlusPlus;
+  S.CCEDiag(S.Current->getSource(OpPC), diag::note_constexpr_invalid_cast)
+      << diag::ConstexprInvalidCastKind::ThisConversionOrReinterpret
+      << S.getLangOpts().CPlusPlus;
 
   S.Stk.push<Pointer>(static_cast<uint64_t>(IntVal), Desc);
   return true;
@@ -2869,12 +2904,22 @@ inline bool InvalidCast(InterpState &S, CodePtr OpPC, CastKind Kind,
                         bool Fatal) {
   const SourceLocation &Loc = S.Current->getLocation(OpPC);
 
-  // FIXME: Support diagnosing other invalid cast kinds.
   if (Kind == CastKind::Reinterpret) {
     S.CCEDiag(Loc, diag::note_constexpr_invalid_cast)
         << static_cast<unsigned>(Kind) << S.Current->getRange(OpPC);
     return !Fatal;
+  } else if (Kind == CastKind::Volatile) {
+    // FIXME: Technically not a cast.
+    const auto *E = cast<CastExpr>(S.Current->getExpr(OpPC));
+    if (S.getLangOpts().CPlusPlus)
+      S.FFDiag(E, diag::note_constexpr_access_volatile_type)
+          << AK_Read << E->getSubExpr()->getType();
+    else
+      S.FFDiag(E);
+
+    return false;
   }
+
   return false;
 }
 
diff --git a/clang/lib/AST/ByteCode/InterpBuiltin.cpp b/clang/lib/AST/ByteCode/InterpBuiltin.cpp
index 523e471d3c82c..d8b320ff3ba31 100644
--- a/clang/lib/AST/ByteCode/InterpBuiltin.cpp
+++ b/clang/lib/AST/ByteCode/InterpBuiltin.cpp
@@ -1526,34 +1526,7 @@ static bool interp__builtin_operator_new(InterpState &S, CodePtr OpPC,
   // A call to __operator_new is only valid within std::allocate<>::allocate.
   // Walk up the call stack to find the appropriate caller and get the
   // element type from it.
-  QualType ElemType;
-  const CallExpr *NewCall = nullptr;
-
-  for (const InterpFrame *F = Frame; F; F = F->Caller) {
-    const Function *Func = F->getFunction();
-    if (!Func)
-      continue;
-    const auto *MD = dyn_cast_if_present<CXXMethodDecl>(Func->getDecl());
-    if (!MD)
-      continue;
-    const IdentifierInfo *FnII = MD->getIdentifier();
-    if (!FnII || !FnII->isStr("allocate"))
-      continue;
-
-    const auto *CTSD =
-        dyn_cast<ClassTemplateSpecializationDecl>(MD->getParent());
-    if (!CTSD)
-      continue;
-
-    const IdentifierInfo *ClassII = CTSD->getIdentifier();
-    const TemplateArgumentList &TAL = CTSD->getTemplateArgs();
-    if (CTSD->isInStdNamespace() && ClassII && ClassII->isStr("allocator") &&
-        TAL.size() >= 1 && TAL[0].getKind() == TemplateArgument::Type) {
-      ElemType = TAL[0].getAsType();
-      NewCall = cast<CallExpr>(F->Caller->getExpr(F->getRetPC()));
-      break;
-    }
-  }
+  auto [NewCall, ElemType] = S.getStdAllocatorCaller("allocate");
 
   if (ElemType.isNull()) {
     S.FFDiag(Call, S.getLangOpts().CPlusPlus20
@@ -1655,33 +1628,7 @@ static bool interp__builtin_operator_delete(InterpState &S, CodePtr OpPC,
     return false;
 
   // This is permitted only within a call to std::allocator<T>::deallocate.
-  bool DeallocateFrameFound = false;
-  for (const InterpFrame *F = Frame; F; F = F->Caller) {
-    const Function *Func = F->getFunction();
-    if (!Func)
-      continue;
-    const auto *MD = dyn_cast_if_present<CXXMethodDecl>(Func->getDecl());
-    if (!MD)
-      continue;
-    const IdentifierInfo *FnII = MD->getIdentifier();
-    if (!FnII || !FnII->isStr("deallocate"))
-      continue;
-
-    const auto *CTSD =
-        dyn_cast<ClassTemplateSpecializationDecl>(MD->getParent());
-    if (!CTSD)
-      continue;
-
-    const IdentifierInfo *ClassII = CTSD->getIdentifier();
-    const TemplateArgumentList &TAL = CTSD->getTemplateArgs();
-    if (CTSD->isInStdNamespace() && ClassII && ClassII->isStr("allocator") &&
-        TAL.size() >= 1 && TAL[0].getKind() == TemplateArgument::Type) {
-      DeallocateFrameFound = true;
-      break;
-    }
-  }
-
-  if (!DeallocateFrameFound) {
+  if (!S.getStdAllocatorCaller("deallocate")) {
     S.FFDiag(Call);
     return true;
   }
diff --git a/clang/lib/AST/ByteCode/InterpState.cpp b/clang/lib/AST/ByteCode/InterpState.cpp
index 70a2e9b62fc3a..d6e6771f0a04f 100644
--- a/clang/lib/AST/ByteCode/InterpState.cpp
+++ b/clang/lib/AST/ByteCode/InterpState.cpp
@@ -115,3 +115,33 @@ bool InterpState::maybeDiagnoseDanglingAllocations() {
   }
   return NoAllocationsLeft;
 }
+
+StdAllocatorCaller InterpState::getStdAllocatorCaller(StringRef Name) const {
+  for (const InterpFrame *F = Current; F; F = F->Caller) {
+    const Function *Func = F->getFunction();
+    if (!Func)
+      continue;
+    const auto *MD = dyn_cast_if_present<CXXMethodDecl>(Func->getDecl());
+    if (!MD)
+      continue;
+    const IdentifierInfo *FnII = MD->getIdentifier();
+    if (!FnII || !FnII->isStr(Name))
+      continue;
+
+    const auto *CTSD =
+        dyn_cast<ClassTemplateSpecializationDecl>(MD->getParent());
+    if (!CTSD)
+      continue;
+
+    const IdentifierInfo *ClassII = CTSD->getIdentifier();
+    const TemplateArgumentList &TAL = CTSD->getTemplateArgs();
+    if (CTSD->isInStdNamespace() && ClassII && ClassII->isStr("allocator") &&
+        TAL.size() >= 1 && TAL[0].getKind() == TemplateArgument::Type) {
+      QualType ElemType = TAL[0].getAsType();
+      const auto *NewCall = cast<CallExpr>(F->Caller->getExpr(F->getRetPC()));
+      return {NewCall, ElemType};
+    }
+  }
+
+  return {};
+}
diff --git a/clang/lib/AST/ByteCode/InterpState.h b/clang/lib/AST/ByteCode/InterpState.h
index 528c1a24e7b05..91e09a911ce37 100644
--- a/clang/lib/AST/ByteCode/InterpState.h
+++ b/clang/lib/AST/ByteCode/InterpState.h
@@ -32,6 +32,12 @@ class InterpStack;
 class InterpFrame;
 class SourceMapper;
 
+struct StdAllocatorCaller {
+  const Expr *Call = nullptr;
+  QualType AllocType;
+  explicit operator bool() { return Call; }
+};
+
 /// Interpreter context.
 class InterpState final : public State, public SourceMapper {
 public:
@@ -116,6 +122,8 @@ class InterpState final : public State, public SourceMapper {
   /// \c true otherwise.
   bool maybeDiagnoseDanglingAllocations();
 
+  StdAllocatorCaller getStdAllocatorCaller(StringRef Name) const;
+
 private:
   friend class EvaluationResult;
   friend class InterpStateCCOverride;
diff --git a/clang/lib/AST/ByteCode/Pointer.cpp b/clang/lib/AST/ByteCode/Pointer.cpp
index 059503cae3561..6c2566ba20bde 100644
--- a/clang/lib/AST/ByteCode/Pointer.cpp
+++ b/clang/lib/AST/ByteCode/Pointer.cpp
@@ -571,6 +571,48 @@ bool Pointer::pointsToLiteral() const {
   return E && !isa<MaterializeTemporaryExpr, StringLiteral>(E);
 }
 
+std::optional<std::pair<Pointer, Pointer>>
+Pointer::computeSplitPoint(const Pointer &A, const Pointer &B) {
+  if (!A.isBlockPointer() || !B.isBlockPointer())
+    return std::nullopt;
+
+  if (A.asBlockPointer().Pointee != B.asBlockPointer().Pointee)
+    return std::nullopt;
+  if (A.isRoot() && B.isRoot())
+    return std::nullopt;
+
+  if (A == B)
+    return std::make_pair(A, B);
+
+  auto getBase = [](const Pointer &P) -> Pointer {
+    if (P.isArrayElement())
+      return P.expand().getArray();
+    return P.getBase();
+  };
+
+  Pointer IterA = A;
+  Pointer IterB = B;
+  Pointer CurA = IterA;
+  Pointer CurB = IterB;
+  for (;;) {
+    if (IterA.asBlockPointer().Base > IterB.asBlockPointer().Base) {
+      CurA = IterA;
+      IterA = getBase(IterA);
+    } else {
+      CurB = IterB;
+      IterB = getBase(IterB);
+    }
+
+    if (IterA == IterB)
+      return std::make_pair(CurA, CurB);
+
+    if (IterA.isRoot() && IterB.isRoot())
+      return std::nullopt;
+  }
+
+  llvm_unreachable("The loop above should've returned.");
+}
+
 std::optional<APValue> Pointer::toRValue(const Context &Ctx,
                                          QualType ResultType) const {
   const ASTContext &ASTCtx = Ctx.getASTContext();
diff --git a/clang/lib/AST/ByteCode/Pointer.h b/clang/lib/AST/ByteCode/Pointer.h
index 8ede706f2736f..e168154a55f58 100644
--- a/clang/lib/AST/ByteCode/Pointer.h
+++ b/clang/lib/AST/ByteCode/Pointer.h
@@ -492,7 +492,11 @@ class Pointer {
     return ElemDesc ? ElemDesc->ElemRecord : nullptr;
   }
   /// Returns the field information.
-  const FieldDecl *getField() const { return getFieldDesc()->asFieldDecl(); }
+  const FieldDecl *getField() const {
+    if (const Descriptor *FD = getFieldDesc())
+      return FD->asFieldDecl();
+    return nullptr;
+  }
 
   /// Checks if the storage is extern.
   bool isExtern() const {
@@ -724,6 +728,9 @@ class Pointer {
   /// Checks if both given pointers point to the same block.
   static bool pointToSameBlock(const Pointer &A, const Pointer &B);
 
+  static std::optional<std::pair<Pointer, Pointer>>
+  computeSplitPoint(const Pointer &A, const Pointer &B);
+
   /// Whether this points to a block that's been created for a "literal lvalue",
   /// i.e. a non-MaterializeTemporaryExpr Expr.
   bool pointsToLiteral() const;
diff --git a/clang/lib/AST/ByteCode/PrimType.h b/clang/lib/AST/ByteCode/PrimType.h
index a3c0b0f3ceca8..c6145d4823a0c 100644
--- a/clang/lib/AST/ByteCode/PrimType.h
+++ b/clang/lib/AST/ByteCode/PrimType.h
@@ -55,16 +55,17 @@ inline constexpr bool isPtrType(PrimType T) {
 
 enum class CastKind : uint8_t {
   Reinterpret,
-  Atomic,
+  Volatile,
 };
+
 inline llvm::raw_ostream &operator<<(llvm::raw_ostream &OS,
                                      interp::CastKind CK) {
   switch (CK) {
   case interp::CastKind::Reinterpret:
     OS << "reinterpret_cast";
     break;
-  case interp::CastKind::Atomic:
-    OS << "atomic";
+  case interp::CastKind::Volatile:
+    OS << "volatile";
     break;
   }
   return OS;
diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp
index f598ef5929aa4..f2e49b9ea669e 100644
--- a/clang/lib/AST/ExprConstant.cpp
+++ b/clang/lib/AST/ExprConstant.cpp
@@ -2232,10 +2232,15 @@ static bool ArePotentiallyOverlappingStringLiterals(const EvalInfo &Info,
   // within RHS. We don't need to look at the characters of one string that
   // would appear before the start of the other string if they were merged.
   CharUnits Offset = RHS.Offset - LHS.Offset;
-  if (Offset.isNegative())
+  if (Offset.isNegative()) {
+    if (LHSString.Bytes.size() < (size_t)-Offset.getQuantity())
+      return false;
     LHSString.Bytes = LHSString.Bytes.drop_front(-Offset.getQuantity());
-  else
+  } else {
+    if (RHSString.Bytes.size() < (size_t)Offset.getQuantity())
+      return false;
     RHSString.Bytes = RHSString.Bytes.drop_front(Offset.getQuantity());
+  }
 
   bool LHSIsLonger = LHSString.Bytes.size() > RHSString.Bytes.size();
   StringRef Longer = LHSIsLonger ? LHSString.Bytes : RHSString.Bytes;
@@ -9197,7 +9202,10 @@ bool LValueExprEvaluator::VisitExtVectorElementExpr(
 
   if (Success) {
     Result.setFrom(Info.Ctx, Val);
-    const auto *VT = E->getBase()->getType()->castAs<VectorType>();
+    QualType BaseType = E->getBase()->getType();
+    if (E->isArrow())
+      BaseType = BaseType->getPointeeType();
+    const auto *VT = BaseType->castAs<VectorType>();
     HandleLValueVectorElement(Info, E, Result, VT->getElementType(),
                               VT->getNumElements(), Indices[0]);
   }
diff --git a/clang/lib/AST/Type.cpp b/clang/lib/AST/Type.cpp
index 67cd690af7499..08be90eab6537 100644
--- a/clang/lib/AST/Type.cpp
+++ b/clang/lib/AST/Type.cpp
@@ -2346,16 +2346,15 @@ bool Type::isArithmeticType() const {
 }
 
 bool Type::hasBooleanRepresentation() const {
-  if (isBooleanType())
-    return true;
-
-  if (const EnumType *ET = getAs<EnumType>())
-    return ET->getDecl()->getIntegerType()->isBooleanType();
-
-  if (const AtomicType *AT = getAs<AtomicType>())
-    return AT->getValueType()->hasBooleanRepresentation();
-
-  return false;
+  if (const auto *VT = dyn_cast<VectorType>(CanonicalType))
+    return VT->getElementType()->isBooleanType();
+  if (const auto *ET = dyn_cast<EnumType>(CanonicalType)) {
+    return ET->getDecl()->isComplete() &&
+           ET->getDecl()->getIntegerType()->isBooleanType();
+  }
+  if (const auto *IT = dyn_cast<BitIntType>(CanonicalType))
+    return IT->getNumBits() == 1;
+  return isBooleanType();
 }
 
 Type::ScalarTypeKind Type::getScalarTypeKind() const {
diff --git a/clang/lib/Basic/Targets/AVR.h b/clang/lib/Basic/Targets/AVR.h
index 2117ab58e6f30..75c969fd59dc9 100644
--- a/clang/lib/Basic/Targets/AVR.h
+++ b/clang/lib/Basic/Targets/AVR.h
@@ -124,7 +124,9 @@ class LLVM_LIBRARY_VISIBILITY AVRTargetInfo : public TargetInfo {
       Info.setAllowsRegister();
       return true;
     case 'I': // 6-bit positive integer constant
-      Info.setRequiresImmediate(0, 63);
+      // Due to issue https://github.com/llvm/llvm-project/issues/51513, we
+      // allow value 64 in the frontend and let it be denied in the backend.
+      Info.setRequiresImmediate(0, 64);
       return true;
     case 'J': // 6-bit negative integer constant
       Info.setRequiresImmediate(-63, 0);
diff --git a/clang/lib/Basic/Targets/SPIR.h b/clang/lib/Basic/Targets/SPIR.h
index 4509748589b76..310ef9f2df2c6 100644
--- a/clang/lib/Basic/Targets/SPIR.h
+++ b/clang/lib/Basic/Targets/SPIR.h
@@ -58,8 +58,9 @@ static const unsigned SPIRDefIsPrivMap[] = {
 // Used by both the SPIR and SPIR-V targets.
 static const unsigned SPIRDefIsGenMap[] = {
     4, // Default
-    // OpenCL address space values for this map are dummy and they can't be used
-    0, // opencl_global
+    // Some OpenCL address space values for this map are dummy and they can't be
+    // used
+    1, // opencl_global
     0, // opencl_local
     0, // opencl_constant
     0, // opencl_private
diff --git a/clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp b/clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
index 3696bfbd8e4db..14c4532b32676 100644
--- a/clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
@@ -204,7 +204,8 @@ class OpenACCClauseCIREmitter final
       if (!clause.getArchitectures().empty())
         operation.setDeviceType(
             decodeDeviceType(clause.getArchitectures()[0].getIdentifierInfo()));
-    } else if constexpr (isOneOfTypes<OpTy, ParallelOp, SerialOp, KernelsOp>) {
+    } else if constexpr (isOneOfTypes<OpTy, ParallelOp, SerialOp, KernelsOp,
+                                      DataOp>) {
       // Nothing to do here, these constructs don't have any IR for these, as
       // they just modify the other clauses IR.  So setting of `lastDeviceType`
       // (done above) is all we need.
@@ -243,7 +244,7 @@ class OpenACCClauseCIREmitter final
   }
 
   void VisitAsyncClause(const OpenACCAsyncClause &clause) {
-    if constexpr (isOneOfTypes<OpTy, ParallelOp, SerialOp, KernelsOp>) {
+    if constexpr (isOneOfTypes<OpTy, ParallelOp, SerialOp, KernelsOp, DataOp>) {
       if (!clause.hasIntExpr()) {
         operation.setAsyncOnlyAttr(
             handleDeviceTypeAffectedClause(operation.getAsyncOnlyAttr()));
@@ -278,7 +279,7 @@ class OpenACCClauseCIREmitter final
 
   void VisitIfClause(const OpenACCIfClause &clause) {
     if constexpr (isOneOfTypes<OpTy, ParallelOp, SerialOp, KernelsOp, InitOp,
-                               ShutdownOp, SetOp>) {
+                               ShutdownOp, SetOp, DataOp>) {
       operation.getIfCondMutable().append(
           createCondition(clause.getConditionExpr()));
     } else {
@@ -291,12 +292,7 @@ class OpenACCClauseCIREmitter final
   }
 
   void VisitDeviceNumClause(const OpenACCDeviceNumClause &clause) {
-    if constexpr (isOneOfTypes<OpTy, InitOp, ShutdownOp>) {
-      operation.getDeviceNumOperandMutable().append(
-          createIntExpr(clause.getIntExpr()));
-    } else if constexpr (isOneOfTypes<OpTy, SetOp>) {
-      // This is only a separate case because the getter name is different in
-      // 'set' for some reason.
+    if constexpr (isOneOfTypes<OpTy, InitOp, ShutdownOp, SetOp>) {
       operation.getDeviceNumMutable().append(
           createIntExpr(clause.getIntExpr()));
     } else {
diff --git a/clang/lib/CIR/Dialect/IR/CIRDialect.cpp b/clang/lib/CIR/Dialect/IR/CIRDialect.cpp
index 146c91b253f39..3cd17053a52ba 100644
--- a/clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+++ b/clang/lib/CIR/Dialect/IR/CIRDialect.cpp
@@ -33,6 +33,14 @@ struct CIROpAsmDialectInterface : public OpAsmDialectInterface {
   using OpAsmDialectInterface::OpAsmDialectInterface;
 
   AliasResult getAlias(Type type, raw_ostream &os) const final {
+    if (auto recordType = dyn_cast<cir::RecordType>(type)) {
+      StringAttr nameAttr = recordType.getName();
+      if (!nameAttr)
+        os << "rec_anon_" << recordType.getKindAsStr();
+      else
+        os << "rec_" << nameAttr.getValue();
+      return AliasResult::OverridableAlias;
+    }
     if (auto intType = dyn_cast<cir::IntType>(type)) {
       // We only provide alias for standard integer types (i.e. integer types
       // whose width is a power of 2 and at least 8).
diff --git a/clang/lib/CodeGen/CGClass.cpp b/clang/lib/CodeGen/CGClass.cpp
index 7176fe025b386..a8c48237977c2 100644
--- a/clang/lib/CodeGen/CGClass.cpp
+++ b/clang/lib/CodeGen/CGClass.cpp
@@ -2895,7 +2895,8 @@ void CodeGenFunction::EmitVTablePtrCheck(const CXXRecordDecl *RD,
   }
 
   if (CGM.getCodeGenOpts().SanitizeTrap.has(M)) {
-    EmitTrapCheck(TypeTest, SanitizerHandler::CFICheckFail);
+    bool NoMerge = !CGM.getCodeGenOpts().SanitizeMergeHandlers.has(M);
+    EmitTrapCheck(TypeTest, SanitizerHandler::CFICheckFail, NoMerge);
     return;
   }
 
diff --git a/clang/lib/CodeGen/CGDebugInfo.cpp b/clang/lib/CodeGen/CGDebugInfo.cpp
index 1582d911ba052..f3ec498d4064b 100644
--- a/clang/lib/CodeGen/CGDebugInfo.cpp
+++ b/clang/lib/CodeGen/CGDebugInfo.cpp
@@ -2018,17 +2018,8 @@ CGDebugInfo::getOrCreateMethodType(const CXXMethodDecl *Method,
   return getOrCreateInstanceMethodType(ThisType, Func, Unit);
 }
 
-llvm::DISubroutineType *CGDebugInfo::getOrCreateMethodTypeForDestructor(
-    const CXXMethodDecl *Method, llvm::DIFile *Unit, QualType FNType) {
-  const FunctionProtoType *Func = FNType->getAs<FunctionProtoType>();
-  // skip the first param since it is also this
-  return getOrCreateInstanceMethodType(Method->getThisType(), Func, Unit, true);
-}
-
-llvm::DISubroutineType *
-CGDebugInfo::getOrCreateInstanceMethodType(QualType ThisPtr,
-                                           const FunctionProtoType *Func,
-                                           llvm::DIFile *Unit, bool SkipFirst) {
+llvm::DISubroutineType *CGDebugInfo::getOrCreateInstanceMethodType(
+    QualType ThisPtr, const FunctionProtoType *Func, llvm::DIFile *Unit) {
   FunctionProtoType::ExtProtoInfo EPI = Func->getExtProtoInfo();
   Qualifiers &Qc = EPI.TypeQuals;
   Qc.removeConst();
@@ -2068,7 +2059,7 @@ CGDebugInfo::getOrCreateInstanceMethodType(QualType ThisPtr,
   }
 
   // Copy rest of the arguments.
-  for (unsigned i = (SkipFirst ? 2 : 1), e = Args.size(); i != e; ++i)
+  for (unsigned i = 1, e = Args.size(); i != e; ++i)
     Elts.push_back(Args[i]);
 
   // Attach FlagObjectPointer to the explicit "this" parameter.
@@ -4381,12 +4372,6 @@ llvm::DISubroutineType *CGDebugInfo::getOrCreateFunctionType(const Decl *D,
     // subprogram DIE will miss DW_AT_decl_file and DW_AT_decl_line fields.
     return DBuilder.createSubroutineType(DBuilder.getOrCreateTypeArray({}));
 
-  if (const auto *Method = dyn_cast<CXXDestructorDecl>(D)) {
-    // Read method type from 'FnType' because 'D.getType()' does not cover
-    // implicit arguments for destructors.
-    return getOrCreateMethodTypeForDestructor(Method, F, FnType);
-  }
-
   if (const auto *Method = dyn_cast<CXXMethodDecl>(D))
     return getOrCreateMethodType(Method, F);
 
diff --git a/clang/lib/CodeGen/CGDebugInfo.h b/clang/lib/CodeGen/CGDebugInfo.h
index 771c129230eea..b287ce7b92eee 100644
--- a/clang/lib/CodeGen/CGDebugInfo.h
+++ b/clang/lib/CodeGen/CGDebugInfo.h
@@ -249,14 +249,9 @@ class CGDebugInfo {
   /// to get a method type which includes \c this pointer.
   llvm::DISubroutineType *getOrCreateMethodType(const CXXMethodDecl *Method,
                                                 llvm::DIFile *F);
-
-  llvm::DISubroutineType *
-  getOrCreateMethodTypeForDestructor(const CXXMethodDecl *Method,
-                                     llvm::DIFile *F, QualType FNType);
-
   llvm::DISubroutineType *
   getOrCreateInstanceMethodType(QualType ThisPtr, const FunctionProtoType *Func,
-                                llvm::DIFile *Unit, bool SkipFirst = false);
+                                llvm::DIFile *Unit);
   llvm::DISubroutineType *
   getOrCreateFunctionType(const Decl *D, QualType FnType, llvm::DIFile *F);
   /// \return debug info descriptor for vtable.
diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index abb88477062fc..bba7d1e805f3f 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -1920,7 +1920,7 @@ static bool getRangeForType(CodeGenFunction &CGF, QualType Ty,
 llvm::MDNode *CodeGenFunction::getRangeForLoadFromType(QualType Ty) {
   llvm::APInt Min, End;
   if (!getRangeForType(*this, Ty, Min, End, CGM.getCodeGenOpts().StrictEnums,
-                       Ty->hasBooleanRepresentation()))
+                       Ty->hasBooleanRepresentation() && !Ty->isVectorType()))
     return nullptr;
 
   llvm::MDBuilder MDHelper(getLLVMContext());
@@ -1948,7 +1948,7 @@ bool CodeGenFunction::EmitScalarRangeCheck(llvm::Value *Value, QualType Ty,
   if (!HasBoolCheck && !HasEnumCheck)
     return false;
 
-  bool IsBool = Ty->hasBooleanRepresentation() ||
+  bool IsBool = (Ty->hasBooleanRepresentation() && !Ty->isVectorType()) ||
                 NSAPI(CGM.getContext()).isObjCBOOLType(Ty);
   bool NeedsBoolCheck = HasBoolCheck && IsBool;
   bool NeedsEnumCheck = HasEnumCheck && Ty->getAs<EnumType>();
@@ -2068,11 +2068,8 @@ llvm::Value *CodeGenFunction::EmitLoadOfScalar(Address Addr, bool Volatile,
 /// by ConvertType) to its load/store type (as returned by
 /// convertTypeForLoadStore).
 llvm::Value *CodeGenFunction::EmitToMemory(llvm::Value *Value, QualType Ty) {
-  if (Ty->hasBooleanRepresentation() || Ty->isBitIntType()) {
-    llvm::Type *StoreTy = convertTypeForLoadStore(Ty, Value->getType());
-    bool Signed = Ty->isSignedIntegerOrEnumerationType();
-    return Builder.CreateIntCast(Value, StoreTy, Signed, "storedv");
-  }
+  if (auto *AtomicTy = Ty->getAs<AtomicType>())
+    Ty = AtomicTy->getValueType();
 
   if (Ty->isExtVectorBoolType()) {
     llvm::Type *StoreTy = convertTypeForLoadStore(Ty, Value->getType());
@@ -2088,6 +2085,12 @@ llvm::Value *CodeGenFunction::EmitToMemory(llvm::Value *Value, QualType Ty) {
     Value = Builder.CreateBitCast(Value, StoreTy);
   }
 
+  if (Ty->hasBooleanRepresentation() || Ty->isBitIntType()) {
+    llvm::Type *StoreTy = convertTypeForLoadStore(Ty, Value->getType());
+    bool Signed = Ty->isSignedIntegerOrEnumerationType();
+    return Builder.CreateIntCast(Value, StoreTy, Signed, "storedv");
+  }
+
   return Value;
 }
 
@@ -2095,6 +2098,9 @@ llvm::Value *CodeGenFunction::EmitToMemory(llvm::Value *Value, QualType Ty) {
 /// by convertTypeForLoadStore) to its primary IR type (as returned
 /// by ConvertType).
 llvm::Value *CodeGenFunction::EmitFromMemory(llvm::Value *Value, QualType Ty) {
+  if (auto *AtomicTy = Ty->getAs<AtomicType>())
+    Ty = AtomicTy->getValueType();
+
   if (Ty->isPackedVectorBoolType(getContext())) {
     const auto *RawIntTy = Value->getType();
 
@@ -3917,7 +3923,11 @@ void CodeGenFunction::EmitCfiCheckFail() {
   // Data == nullptr means the calling module has trap behaviour for this check.
   llvm::Value *DataIsNotNullPtr =
       Builder.CreateICmpNE(Data, llvm::ConstantPointerNull::get(Int8PtrTy));
-  EmitTrapCheck(DataIsNotNullPtr, SanitizerHandler::CFICheckFail);
+  // TODO: since there is no data, we don't know the CheckKind, and therefore
+  // cannot inspect CGM.getCodeGenOpts().SanitizeMergeHandlers. We default to
+  // NoMerge = false. Users can disable merging by disabling optimization.
+  EmitTrapCheck(DataIsNotNullPtr, SanitizerHandler::CFICheckFail,
+                /*NoMerge=*/false);
 
   llvm::StructType *SourceLocationTy =
       llvm::StructType::get(VoidPtrTy, Int32Ty, Int32Ty);
@@ -3956,7 +3966,11 @@ void CodeGenFunction::EmitCfiCheckFail() {
       EmitCheck(std::make_pair(Cond, Ordinal), SanitizerHandler::CFICheckFail,
                 {}, {Data, Addr, ValidVtable});
     else
-      EmitTrapCheck(Cond, SanitizerHandler::CFICheckFail);
+      // TODO: we can't rely on CGM.getCodeGenOpts().SanitizeMergeHandlers.
+      // Although the compiler allows SanitizeMergeHandlers to be set
+      // independently of CGM.getLangOpts().Sanitize, Driver/SanitizerArgs.cpp
+      // requires that SanitizeMergeHandlers is a subset of Sanitize.
+      EmitTrapCheck(Cond, SanitizerHandler::CFICheckFail, /*NoMerge=*/false);
   }
 
   FinishFunction();
diff --git a/clang/lib/Driver/SanitizerArgs.cpp b/clang/lib/Driver/SanitizerArgs.cpp
index f27cb813012f2..94a036172d0b6 100644
--- a/clang/lib/Driver/SanitizerArgs.cpp
+++ b/clang/lib/Driver/SanitizerArgs.cpp
@@ -853,8 +853,8 @@ SanitizerArgs::SanitizerArgs(const ToolChain &TC,
     SanitizerMask NonTrappingCfi = Kinds & SanitizerKind::CFI & ~TrappingKinds;
     if (NonTrappingCfi && DiagnoseErrors)
       D.Diag(clang::diag::err_drv_argument_only_allowed_with)
-          << "fsanitize-minimal-runtime"
-          << "fsanitize-trap=cfi";
+          << "-fsanitize-minimal-runtime"
+          << "-fsanitize-trap=cfi";
   }
 
   for (const auto *Arg : Args.filtered(
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp
index f2f5231933c88..f98cd389509cd 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -7232,7 +7232,9 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
   // -fuse-cxa-atexit is default.
   if (!Args.hasFlag(
           options::OPT_fuse_cxa_atexit, options::OPT_fno_use_cxa_atexit,
-          !RawTriple.isOSAIX() && !RawTriple.isOSWindows() &&
+          !RawTriple.isOSAIX() &&
+              (!RawTriple.isOSWindows() ||
+               RawTriple.isWindowsCygwinEnvironment()) &&
               ((RawTriple.getVendor() != llvm::Triple::MipsTechnologies) ||
                RawTriple.hasEnvironment())) ||
       KernelOrKext)
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index 8646c55060b17..7cc4008ec1f2b 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -2794,6 +2794,11 @@ void tools::addOpenMPDeviceRTL(const Driver &D,
   for (const auto &LibPath : HostTC.getFilePaths())
     LibraryPaths.emplace_back(LibPath);
 
+  // Check the target specific library path for the triple as well.
+  SmallString<128> P(D.Dir);
+  llvm::sys::path::append(P, "..", "lib", Triple.getTriple());
+  LibraryPaths.emplace_back(P);
+
   OptSpecifier LibomptargetBCPathOpt =
       Triple.isAMDGCN()  ? options::OPT_libomptarget_amdgpu_bc_path_EQ
       : Triple.isNVPTX() ? options::OPT_libomptarget_nvptx_bc_path_EQ
diff --git a/clang/lib/Format/FormatTokenLexer.cpp b/clang/lib/Format/FormatTokenLexer.cpp
index 5c4e1f814d9b7..a4c94ac411fe0 100644
--- a/clang/lib/Format/FormatTokenLexer.cpp
+++ b/clang/lib/Format/FormatTokenLexer.cpp
@@ -128,6 +128,12 @@ void FormatTokenLexer::tryMergePreviousTokens() {
   if (Style.isCpp() && tryTransformTryUsageForC())
     return;
 
+  if ((Style.Language == FormatStyle::LK_Cpp ||
+       Style.Language == FormatStyle::LK_ObjC) &&
+      tryMergeUserDefinedLiteral()) {
+    return;
+  }
+
   if (Style.isJavaScript() || Style.isCSharp()) {
     static const tok::TokenKind NullishCoalescingOperator[] = {tok::question,
                                                                tok::question};
@@ -559,6 +565,29 @@ bool FormatTokenLexer::tryMergeGreaterGreater() {
   return true;
 }
 
+bool FormatTokenLexer::tryMergeUserDefinedLiteral() {
+  if (Tokens.size() < 2)
+    return false;
+
+  auto *First = Tokens.end() - 2;
+  auto &Suffix = First[1];
+  if (Suffix->hasWhitespaceBefore() || Suffix->TokenText != "$")
+    return false;
+
+  auto &Literal = First[0];
+  if (!Literal->Tok.isLiteral())
+    return false;
+
+  auto &Text = Literal->TokenText;
+  if (!Text.ends_with("_"))
+    return false;
+
+  Text = StringRef(Text.data(), Text.size() + 1);
+  ++Literal->ColumnWidth;
+  Tokens.erase(&Suffix);
+  return true;
+}
+
 bool FormatTokenLexer::tryMergeTokens(ArrayRef<tok::TokenKind> Kinds,
                                       TokenType NewType) {
   if (Tokens.size() < Kinds.size())
diff --git a/clang/lib/Format/FormatTokenLexer.h b/clang/lib/Format/FormatTokenLexer.h
index 61474a3f9ada8..3f001bc69415d 100644
--- a/clang/lib/Format/FormatTokenLexer.h
+++ b/clang/lib/Format/FormatTokenLexer.h
@@ -48,6 +48,7 @@ class FormatTokenLexer {
 
   bool tryMergeLessLess();
   bool tryMergeGreaterGreater();
+  bool tryMergeUserDefinedLiteral();
   bool tryMergeNSStringLiteral();
   bool tryMergeJSPrivateIdentifier();
   bool tryMergeCSharpStringLiteral();
diff --git a/clang/lib/Format/TokenAnnotator.cpp b/clang/lib/Format/TokenAnnotator.cpp
index b4f303e281c1d..3e17c688dbcce 100644
--- a/clang/lib/Format/TokenAnnotator.cpp
+++ b/clang/lib/Format/TokenAnnotator.cpp
@@ -3977,8 +3977,10 @@ void TokenAnnotator::calculateFormattingInformation(AnnotatedLine &Line) const {
   FormatToken *AfterLastAttribute = nullptr;
   FormatToken *ClosingParen = nullptr;
 
-  for (auto *Tok = FirstNonComment ? FirstNonComment->Next : nullptr; Tok;
-       Tok = Tok->Next) {
+  for (auto *Tok = FirstNonComment && FirstNonComment->isNot(tok::kw_using)
+                       ? FirstNonComment->Next
+                       : nullptr;
+       Tok; Tok = Tok->Next) {
     if (Tok->is(TT_StartOfName))
       SeenName = true;
     if (Tok->Previous->EndsCppAttributeGroup)
@@ -6240,8 +6242,6 @@ bool TokenAnnotator::canBreakBefore(const AnnotatedLine &Line,
                     TT_ClassHeadName, tok::kw_operator)) {
     return true;
   }
-  if (Right.isAttribute())
-    return true;
   if (Left.is(TT_PointerOrReference))
     return false;
   if (Right.isTrailingComment()) {
@@ -6386,6 +6386,9 @@ bool TokenAnnotator::canBreakBefore(const AnnotatedLine &Line,
                           tok::less, tok::coloncolon);
   }
 
+  if (Right.isAttribute())
+    return true;
+
   if (Right.is(tok::l_square) && Right.is(TT_AttributeSquare))
     return Left.isNot(TT_AttributeSquare);
 
diff --git a/clang/lib/Format/UnwrappedLineParser.cpp b/clang/lib/Format/UnwrappedLineParser.cpp
index b9430d4389feb..df58e5ef4d6a3 100644
--- a/clang/lib/Format/UnwrappedLineParser.cpp
+++ b/clang/lib/Format/UnwrappedLineParser.cpp
@@ -2368,13 +2368,25 @@ bool UnwrappedLineParser::tryToParseLambdaIntroducer() {
   const FormatToken *Previous = FormatTok->Previous;
   const FormatToken *LeftSquare = FormatTok;
   nextToken();
-  if ((Previous && ((Previous->Tok.getIdentifierInfo() &&
-                     !Previous->isOneOf(tok::kw_return, tok::kw_co_await,
-                                        tok::kw_co_yield, tok::kw_co_return)) ||
-                    Previous->closesScope())) ||
-      LeftSquare->isCppStructuredBinding(IsCpp)) {
-    return false;
+  if (Previous) {
+    if (Previous->Tok.getIdentifierInfo() &&
+        !Previous->isOneOf(tok::kw_return, tok::kw_co_await, tok::kw_co_yield,
+                           tok::kw_co_return)) {
+      return false;
+    }
+    if (Previous->closesScope()) {
+      // Not a potential C-style cast.
+      if (Previous->isNot(tok::r_paren))
+        return false;
+      const auto *BeforeRParen = Previous->getPreviousNonComment();
+      // Lambdas can be cast to function types only, e.g. `std::function<int()>`
+      // and `int (*)()`.
+      if (!BeforeRParen || !BeforeRParen->isOneOf(tok::greater, tok::r_paren))
+        return false;
+    }
   }
+  if (LeftSquare->isCppStructuredBinding(IsCpp))
+    return false;
   if (FormatTok->is(tok::l_square) || tok::isLiteral(FormatTok->Tok.getKind()))
     return false;
   if (FormatTok->is(tok::r_square)) {
diff --git a/clang/lib/Frontend/CompilerInstance.cpp b/clang/lib/Frontend/CompilerInstance.cpp
index de633f0ec8734..1526ea53add7d 100644
--- a/clang/lib/Frontend/CompilerInstance.cpp
+++ b/clang/lib/Frontend/CompilerInstance.cpp
@@ -536,6 +536,9 @@ void CompilerInstance::createPreprocessor(TranslationUnitKind TUKind) {
                            /*ShowAllHeaders=*/true, /*OutputPath=*/"",
                            /*ShowDepth=*/true, /*MSStyle=*/true);
   }
+
+  if (GetDependencyDirectives)
+    PP->setDependencyDirectivesGetter(*GetDependencyDirectives);
 }
 
 std::string CompilerInstance::getSpecificModuleCachePath(StringRef ModuleHash) {
@@ -1237,15 +1240,23 @@ std::unique_ptr<CompilerInstance> CompilerInstance::cloneForModuleCompileImpl(
   Instance.createSourceManager(Instance.getFileManager());
   SourceManager &SourceMgr = Instance.getSourceManager();
 
-  // Note that this module is part of the module build stack, so that we
-  // can detect cycles in the module graph.
-  SourceMgr.setModuleBuildStack(getSourceManager().getModuleBuildStack());
-  SourceMgr.pushModuleBuildStack(ModuleName,
-                                 FullSourceLoc(ImportLoc, getSourceManager()));
+  if (ThreadSafeConfig) {
+    // Detecting cycles in the module graph is responsibility of the client.
+  } else {
+    // Note that this module is part of the module build stack, so that we
+    // can detect cycles in the module graph.
+    SourceMgr.setModuleBuildStack(getSourceManager().getModuleBuildStack());
+    SourceMgr.pushModuleBuildStack(
+        ModuleName, FullSourceLoc(ImportLoc, getSourceManager()));
+  }
 
   // Make a copy for the new instance.
   Instance.FailedModules = FailedModules;
 
+  if (GetDependencyDirectives)
+    Instance.GetDependencyDirectives =
+        GetDependencyDirectives->cloneFor(Instance.getFileManager());
+
   // If we're collecting module dependencies, we need to share a collector
   // between all of the module CompilerInstances. Other than that, we don't
   // want to produce any dependency output from the module build.
diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp
index 9e9eed4efc577..1df503859204d 100644
--- a/clang/lib/Frontend/CompilerInvocation.cpp
+++ b/clang/lib/Frontend/CompilerInvocation.cpp
@@ -2435,13 +2435,25 @@ static bool ParseDependencyOutputArgs(DependencyOutputOptions &Opts,
 
   // Check for invalid combinations of header-include-format
   // and header-include-filtering.
-  if ((Opts.HeaderIncludeFormat == HIFMT_Textual &&
-       Opts.HeaderIncludeFiltering != HIFIL_None) ||
-      (Opts.HeaderIncludeFormat == HIFMT_JSON &&
-       Opts.HeaderIncludeFiltering != HIFIL_Only_Direct_System))
-    Diags.Report(diag::err_drv_print_header_env_var_combination_cc1)
-        << Args.getLastArg(OPT_header_include_format_EQ)->getValue()
-        << Args.getLastArg(OPT_header_include_filtering_EQ)->getValue();
+  if (Opts.HeaderIncludeFormat == HIFMT_Textual &&
+      Opts.HeaderIncludeFiltering != HIFIL_None) {
+    if (Args.hasArg(OPT_header_include_format_EQ))
+      Diags.Report(diag::err_drv_print_header_cc1_invalid_combination)
+          << headerIncludeFormatKindToString(Opts.HeaderIncludeFormat)
+          << headerIncludeFilteringKindToString(Opts.HeaderIncludeFiltering);
+    else
+      Diags.Report(diag::err_drv_print_header_cc1_invalid_filtering)
+          << headerIncludeFilteringKindToString(Opts.HeaderIncludeFiltering);
+  } else if (Opts.HeaderIncludeFormat == HIFMT_JSON &&
+             Opts.HeaderIncludeFiltering == HIFIL_None) {
+    if (Args.hasArg(OPT_header_include_filtering_EQ))
+      Diags.Report(diag::err_drv_print_header_cc1_invalid_combination)
+          << headerIncludeFormatKindToString(Opts.HeaderIncludeFormat)
+          << headerIncludeFilteringKindToString(Opts.HeaderIncludeFiltering);
+    else
+      Diags.Report(diag::err_drv_print_header_cc1_invalid_format)
+          << headerIncludeFormatKindToString(Opts.HeaderIncludeFormat);
+  }
 
   return Diags.getNumErrors() == NumErrorsBefore;
 }
diff --git a/clang/lib/Headers/arm_acle.h b/clang/lib/Headers/arm_acle.h
index 89db5dc2d7aaa..5cfa3d023a7d5 100644
--- a/clang/lib/Headers/arm_acle.h
+++ b/clang/lib/Headers/arm_acle.h
@@ -841,8 +841,9 @@ __gcspopm() {
   return __builtin_arm_gcspopm(0);
 }
 
-static __inline__ const void * __attribute__((__always_inline__, __nodebug__, target("gcs")))
-__gcsss(const void *__stack) {
+static __inline__ void *__attribute__((__always_inline__, __nodebug__,
+                                       target("gcs")))
+__gcsss(void *__stack) {
   return __builtin_arm_gcsss(__stack);
 }
 #endif
diff --git a/clang/lib/Lex/PPLexerChange.cpp b/clang/lib/Lex/PPLexerChange.cpp
index db6069e31fa46..44b5fa8be9f1b 100644
--- a/clang/lib/Lex/PPLexerChange.cpp
+++ b/clang/lib/Lex/PPLexerChange.cpp
@@ -92,16 +92,10 @@ bool Preprocessor::EnterSourceFile(FileID FID, ConstSearchDirIterator CurDir,
   }
 
   Lexer *TheLexer = new Lexer(FID, *InputFile, *this, IsFirstIncludeOfFile);
-  if (getPreprocessorOpts().DependencyDirectivesForFile &&
-      FID != PredefinesFileID) {
-    if (OptionalFileEntryRef File = SourceMgr.getFileEntryRefForID(FID)) {
-      if (std::optional<ArrayRef<dependency_directives_scan::Directive>>
-              DepDirectives =
-                  getPreprocessorOpts().DependencyDirectivesForFile(*File)) {
-        TheLexer->DepDirectives = *DepDirectives;
-      }
-    }
-  }
+  if (GetDependencyDirectives && FID != PredefinesFileID)
+    if (OptionalFileEntryRef File = SourceMgr.getFileEntryRefForID(FID))
+      if (auto MaybeDepDirectives = (*GetDependencyDirectives)(*File))
+        TheLexer->DepDirectives = *MaybeDepDirectives;
 
   EnterSourceFileWithLexer(TheLexer, CurDir);
   return false;
diff --git a/clang/lib/Parse/ParseHLSLRootSignature.cpp b/clang/lib/Parse/ParseHLSLRootSignature.cpp
index 3513ef454f750..1bf33b8e8329c 100644
--- a/clang/lib/Parse/ParseHLSLRootSignature.cpp
+++ b/clang/lib/Parse/ParseHLSLRootSignature.cpp
@@ -8,6 +8,8 @@
 
 #include "clang/Parse/ParseHLSLRootSignature.h"
 
+#include "clang/Lex/LiteralSupport.h"
+
 #include "llvm/Support/raw_ostream.h"
 
 using namespace llvm::hlsl::rootsig;
@@ -24,100 +26,222 @@ RootSignatureParser::RootSignatureParser(SmallVector<RootElement> &Elements,
 
 bool RootSignatureParser::parse() {
   // Iterate as many RootElements as possible
-  while (tryConsumeExpectedToken(TokenKind::kw_DescriptorTable)) {
-    // Dispatch onto parser method.
-    // We guard against the unreachable here as we just ensured that CurToken
-    // will be one of the kinds in the while condition
-    switch (CurToken.TokKind) {
-    case TokenKind::kw_DescriptorTable:
-      if (parseDescriptorTable())
+  do {
+    if (tryConsumeExpectedToken(TokenKind::kw_DescriptorTable)) {
+      auto Table = parseDescriptorTable();
+      if (!Table.has_value())
         return true;
-      break;
-    default:
-      llvm_unreachable("Switch for consumed token was not provided");
+      Elements.push_back(*Table);
     }
+  } while (tryConsumeExpectedToken(TokenKind::pu_comma));
 
-    if (!tryConsumeExpectedToken(TokenKind::pu_comma))
-      break;
-  }
-
-  if (!tryConsumeExpectedToken(TokenKind::end_of_stream)) {
-    getDiags().Report(CurToken.TokLoc, diag::err_hlsl_unexpected_end_of_params)
-        << /*expected=*/TokenKind::end_of_stream
-        << /*param of=*/TokenKind::kw_RootSignature;
+  if (consumeExpectedToken(TokenKind::end_of_stream,
+                           diag::err_hlsl_unexpected_end_of_params,
+                           /*param of=*/TokenKind::kw_RootSignature))
     return true;
-  }
+
   return false;
 }
 
-bool RootSignatureParser::parseDescriptorTable() {
+std::optional<DescriptorTable> RootSignatureParser::parseDescriptorTable() {
   assert(CurToken.TokKind == TokenKind::kw_DescriptorTable &&
          "Expects to only be invoked starting at given keyword");
 
-  DescriptorTable Table;
-
   if (consumeExpectedToken(TokenKind::pu_l_paren, diag::err_expected_after,
                            CurToken.TokKind))
-    return true;
+    return std::nullopt;
 
-  // Iterate as many Clauses as possible
-  while (tryConsumeExpectedToken({TokenKind::kw_CBV, TokenKind::kw_SRV,
-                                  TokenKind::kw_UAV, TokenKind::kw_Sampler})) {
-    if (parseDescriptorTableClause())
-      return true;
-
-    Table.NumClauses++;
+  DescriptorTable Table;
 
-    if (!tryConsumeExpectedToken(TokenKind::pu_comma))
-      break;
-  }
+  // Iterate as many Clauses as possible
+  do {
+    if (tryConsumeExpectedToken({TokenKind::kw_CBV, TokenKind::kw_SRV,
+                                 TokenKind::kw_UAV, TokenKind::kw_Sampler})) {
+      auto Clause = parseDescriptorTableClause();
+      if (!Clause.has_value())
+        return std::nullopt;
+      Elements.push_back(*Clause);
+      Table.NumClauses++;
+    }
+  } while (tryConsumeExpectedToken(TokenKind::pu_comma));
 
-  if (!tryConsumeExpectedToken(TokenKind::pu_r_paren)) {
-    getDiags().Report(CurToken.TokLoc, diag::err_hlsl_unexpected_end_of_params)
-        << /*expected=*/TokenKind::pu_r_paren
-        << /*param of=*/TokenKind::kw_DescriptorTable;
-    return true;
-  }
+  if (consumeExpectedToken(TokenKind::pu_r_paren,
+                           diag::err_hlsl_unexpected_end_of_params,
+                           /*param of=*/TokenKind::kw_DescriptorTable))
+    return std::nullopt;
 
-  Elements.push_back(Table);
-  return false;
+  return Table;
 }
 
-bool RootSignatureParser::parseDescriptorTableClause() {
+std::optional<DescriptorTableClause>
+RootSignatureParser::parseDescriptorTableClause() {
   assert((CurToken.TokKind == TokenKind::kw_CBV ||
           CurToken.TokKind == TokenKind::kw_SRV ||
           CurToken.TokKind == TokenKind::kw_UAV ||
           CurToken.TokKind == TokenKind::kw_Sampler) &&
          "Expects to only be invoked starting at given keyword");
 
+  TokenKind ParamKind = CurToken.TokKind;
+
+  if (consumeExpectedToken(TokenKind::pu_l_paren, diag::err_expected_after,
+                           CurToken.TokKind))
+    return std::nullopt;
+
   DescriptorTableClause Clause;
-  switch (CurToken.TokKind) {
+  TokenKind ExpectedReg;
+  switch (ParamKind) {
   default:
     llvm_unreachable("Switch for consumed token was not provided");
   case TokenKind::kw_CBV:
     Clause.Type = ClauseType::CBuffer;
+    ExpectedReg = TokenKind::bReg;
     break;
   case TokenKind::kw_SRV:
     Clause.Type = ClauseType::SRV;
+    ExpectedReg = TokenKind::tReg;
     break;
   case TokenKind::kw_UAV:
     Clause.Type = ClauseType::UAV;
+    ExpectedReg = TokenKind::uReg;
     break;
   case TokenKind::kw_Sampler:
     Clause.Type = ClauseType::Sampler;
+    ExpectedReg = TokenKind::sReg;
     break;
   }
 
-  if (consumeExpectedToken(TokenKind::pu_l_paren, diag::err_expected_after,
-                           CurToken.TokKind))
-    return true;
+  auto Params = parseDescriptorTableClauseParams(ExpectedReg);
+  if (!Params.has_value())
+    return std::nullopt;
+
+  // Check mandatory parameters were provided
+  if (!Params->Reg.has_value()) {
+    getDiags().Report(CurToken.TokLoc, diag::err_hlsl_rootsig_missing_param)
+        << ExpectedReg;
+    return std::nullopt;
+  }
+
+  Clause.Reg = Params->Reg.value();
+
+  // Fill in optional values
+  if (Params->Space.has_value())
+    Clause.Space = Params->Space.value();
+
+  if (consumeExpectedToken(TokenKind::pu_r_paren,
+                           diag::err_hlsl_unexpected_end_of_params,
+                           /*param of=*/ParamKind))
+    return std::nullopt;
+
+  return Clause;
+}
 
-  if (consumeExpectedToken(TokenKind::pu_r_paren, diag::err_expected_after,
+std::optional<RootSignatureParser::ParsedClauseParams>
+RootSignatureParser::parseDescriptorTableClauseParams(TokenKind RegType) {
+  assert(CurToken.TokKind == TokenKind::pu_l_paren &&
+         "Expects to only be invoked starting at given token");
+
+  // Parameter arguments (eg. `bReg`, `space`, ...) can be specified in any
+  // order and only exactly once. Parse through as many arguments as possible
+  // reporting an error if a duplicate is seen.
+  ParsedClauseParams Params;
+  do {
+    // ( `b` | `t` | `u` | `s`) POS_INT
+    if (tryConsumeExpectedToken(RegType)) {
+      if (Params.Reg.has_value()) {
+        getDiags().Report(CurToken.TokLoc, diag::err_hlsl_rootsig_repeat_param)
+            << CurToken.TokKind;
+        return std::nullopt;
+      }
+      auto Reg = parseRegister();
+      if (!Reg.has_value())
+        return std::nullopt;
+      Params.Reg = Reg;
+    }
+
+    // `space` `=` POS_INT
+    if (tryConsumeExpectedToken(TokenKind::kw_space)) {
+      if (Params.Space.has_value()) {
+        getDiags().Report(CurToken.TokLoc, diag::err_hlsl_rootsig_repeat_param)
+            << CurToken.TokKind;
+        return std::nullopt;
+      }
+
+      if (consumeExpectedToken(TokenKind::pu_equal))
+        return std::nullopt;
+
+      auto Space = parseUIntParam();
+      if (!Space.has_value())
+        return std::nullopt;
+      Params.Space = Space;
+    }
+  } while (tryConsumeExpectedToken(TokenKind::pu_comma));
+
+  return Params;
+}
+
+std::optional<uint32_t> RootSignatureParser::parseUIntParam() {
+  assert(CurToken.TokKind == TokenKind::pu_equal &&
+         "Expects to only be invoked starting at given keyword");
+  tryConsumeExpectedToken(TokenKind::pu_plus);
+  if (consumeExpectedToken(TokenKind::int_literal, diag::err_expected_after,
                            CurToken.TokKind))
-    return true;
+    return std::nullopt;
+  return handleUIntLiteral();
+}
 
-  Elements.push_back(Clause);
-  return false;
+std::optional<Register> RootSignatureParser::parseRegister() {
+  assert((CurToken.TokKind == TokenKind::bReg ||
+          CurToken.TokKind == TokenKind::tReg ||
+          CurToken.TokKind == TokenKind::uReg ||
+          CurToken.TokKind == TokenKind::sReg) &&
+         "Expects to only be invoked starting at given keyword");
+
+  Register Reg;
+  switch (CurToken.TokKind) {
+  default:
+    llvm_unreachable("Switch for consumed token was not provided");
+  case TokenKind::bReg:
+    Reg.ViewType = RegisterType::BReg;
+    break;
+  case TokenKind::tReg:
+    Reg.ViewType = RegisterType::TReg;
+    break;
+  case TokenKind::uReg:
+    Reg.ViewType = RegisterType::UReg;
+    break;
+  case TokenKind::sReg:
+    Reg.ViewType = RegisterType::SReg;
+    break;
+  }
+
+  auto Number = handleUIntLiteral();
+  if (!Number.has_value())
+    return std::nullopt; // propogate NumericLiteralParser error
+
+  Reg.Number = *Number;
+  return Reg;
+}
+
+std::optional<uint32_t> RootSignatureParser::handleUIntLiteral() {
+  // Parse the numeric value and do semantic checks on its specification
+  clang::NumericLiteralParser Literal(CurToken.NumSpelling, CurToken.TokLoc,
+                                      PP.getSourceManager(), PP.getLangOpts(),
+                                      PP.getTargetInfo(), PP.getDiagnostics());
+  if (Literal.hadError)
+    return true; // Error has already been reported so just return
+
+  assert(Literal.isIntegerLiteral() && "IsNumberChar will only support digits");
+
+  llvm::APSInt Val = llvm::APSInt(32, false);
+  if (Literal.GetIntegerValue(Val)) {
+    // Report that the value has overflowed
+    PP.getDiagnostics().Report(CurToken.TokLoc,
+                               diag::err_hlsl_number_literal_overflow)
+        << 0 << CurToken.NumSpelling;
+    return std::nullopt;
+  }
+
+  return Val.getExtValue();
 }
 
 bool RootSignatureParser::peekExpectedToken(TokenKind Expected) {
@@ -141,6 +265,7 @@ bool RootSignatureParser::consumeExpectedToken(TokenKind Expected,
   case diag::err_expected:
     DB << Expected;
     break;
+  case diag::err_hlsl_unexpected_end_of_params:
   case diag::err_expected_either:
   case diag::err_expected_after:
     DB << Expected << Context;
diff --git a/clang/lib/Sema/AnalysisBasedWarnings.cpp b/clang/lib/Sema/AnalysisBasedWarnings.cpp
index 32c7ee92466ad..2418aaf8de8e6 100644
--- a/clang/lib/Sema/AnalysisBasedWarnings.cpp
+++ b/clang/lib/Sema/AnalysisBasedWarnings.cpp
@@ -2492,8 +2492,10 @@ class sema::AnalysisBasedWarnings::InterProceduralData {
   CalledOnceInterProceduralData CalledOnceData;
 };
 
-static unsigned isEnabled(DiagnosticsEngine &D, unsigned diag) {
-  return (unsigned)!D.isIgnored(diag, SourceLocation());
+template <typename... Ts>
+static bool areAnyEnabled(DiagnosticsEngine &D, SourceLocation Loc,
+                          Ts... Diags) {
+  return (!D.isIgnored(Diags, Loc) || ...);
 }
 
 sema::AnalysisBasedWarnings::AnalysisBasedWarnings(Sema &s)
@@ -2503,23 +2505,37 @@ sema::AnalysisBasedWarnings::AnalysisBasedWarnings(Sema &s)
       NumUninitAnalysisVariables(0), MaxUninitAnalysisVariablesPerFunction(0),
       NumUninitAnalysisBlockVisits(0),
       MaxUninitAnalysisBlockVisitsPerFunction(0) {
+}
+
+// We need this here for unique_ptr with forward declared class.
+sema::AnalysisBasedWarnings::~AnalysisBasedWarnings() = default;
 
+sema::AnalysisBasedWarnings::Policy
+sema::AnalysisBasedWarnings::getPolicyInEffectAt(SourceLocation Loc) {
   using namespace diag;
   DiagnosticsEngine &D = S.getDiagnostics();
+  Policy P;
 
-  DefaultPolicy.enableCheckUnreachable =
-      isEnabled(D, warn_unreachable) || isEnabled(D, warn_unreachable_break) ||
-      isEnabled(D, warn_unreachable_return) ||
-      isEnabled(D, warn_unreachable_loop_increment);
+  // Note: The enabled checks should be kept in sync with the switch in
+  // SemaPPCallbacks::PragmaDiagnostic().
+  P.enableCheckUnreachable =
+      PolicyOverrides.enableCheckUnreachable ||
+      areAnyEnabled(D, Loc, warn_unreachable, warn_unreachable_break,
+                    warn_unreachable_return, warn_unreachable_loop_increment);
 
-  DefaultPolicy.enableThreadSafetyAnalysis = isEnabled(D, warn_double_lock);
+  P.enableThreadSafetyAnalysis = PolicyOverrides.enableThreadSafetyAnalysis ||
+                                 areAnyEnabled(D, Loc, warn_double_lock);
 
-  DefaultPolicy.enableConsumedAnalysis =
-      isEnabled(D, warn_use_in_invalid_state);
+  P.enableConsumedAnalysis = PolicyOverrides.enableConsumedAnalysis ||
+                             areAnyEnabled(D, Loc, warn_use_in_invalid_state);
+  return P;
 }
 
-// We need this here for unique_ptr with forward declared class.
-sema::AnalysisBasedWarnings::~AnalysisBasedWarnings() = default;
+void sema::AnalysisBasedWarnings::clearOverrides() {
+  PolicyOverrides.enableCheckUnreachable = false;
+  PolicyOverrides.enableConsumedAnalysis = false;
+  PolicyOverrides.enableThreadSafetyAnalysis = false;
+}
 
 static void flushDiagnostics(Sema &S, const sema::FunctionScopeInfo *fscope) {
   for (const auto &D : fscope->PossiblyUnreachableDiags)
@@ -2870,6 +2886,9 @@ void clang::sema::AnalysisBasedWarnings::IssueWarnings(
     AC.getCFG();
   }
 
+  // Clear any of our policy overrides.
+  clearOverrides();
+
   // Collect statistics about the CFG if it was built.
   if (S.CollectStats && AC.isCFGBuilt()) {
     ++NumFunctionsAnalyzed;
diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp
index d2da9cd1201c2..4039601612c62 100644
--- a/clang/lib/Sema/Sema.cpp
+++ b/clang/lib/Sema/Sema.cpp
@@ -202,6 +202,43 @@ class SemaPPCallbacks : public PPCallbacks {
       break;
     }
   }
+  void PragmaDiagnostic(SourceLocation Loc, StringRef Namespace,
+                        diag::Severity Mapping, StringRef Str) override {
+    // If one of the analysis-based diagnostics was enabled while processing
+    // a function, we want to note it in the analysis-based warnings so they
+    // can be run at the end of the function body even if the analysis warnings
+    // are disabled at that point.
+    SmallVector<diag::kind, 256> GroupDiags;
+    diag::Flavor Flavor =
+        Str[1] == 'W' ? diag::Flavor::WarningOrError : diag::Flavor::Remark;
+    StringRef Group = Str.substr(2);
+
+    if (S->PP.getDiagnostics().getDiagnosticIDs()->getDiagnosticsInGroup(
+            Flavor, Group, GroupDiags))
+      return;
+
+    for (diag::kind K : GroupDiags) {
+      // Note: the cases in this switch should be kept in sync with the
+      // diagnostics in AnalysisBasedWarnings::getPolicyInEffectAt().
+      AnalysisBasedWarnings::Policy &Override =
+          S->AnalysisWarnings.getPolicyOverrides();
+      switch (K) {
+      default: break;
+      case diag::warn_unreachable:
+      case diag::warn_unreachable_break:
+      case diag::warn_unreachable_return:
+      case diag::warn_unreachable_loop_increment:
+        Override.enableCheckUnreachable = true;
+        break;
+      case diag::warn_double_lock:
+        Override.enableThreadSafetyAnalysis = true;
+        break;
+      case diag::warn_use_in_invalid_state:
+        Override.enableConsumedAnalysis = true;
+        break;
+      }
+    }
+  }
 };
 
 } // end namespace sema
diff --git a/clang/lib/Sema/SemaCUDA.cpp b/clang/lib/Sema/SemaCUDA.cpp
index 0e5fc5e1a40b4..0a8c24f8be537 100644
--- a/clang/lib/Sema/SemaCUDA.cpp
+++ b/clang/lib/Sema/SemaCUDA.cpp
@@ -18,6 +18,7 @@
 #include "clang/Basic/TargetInfo.h"
 #include "clang/Lex/Preprocessor.h"
 #include "clang/Sema/Lookup.h"
+#include "clang/Sema/Overload.h"
 #include "clang/Sema/ScopeInfo.h"
 #include "clang/Sema/Sema.h"
 #include "clang/Sema/Template.h"
@@ -1100,3 +1101,49 @@ std::string SemaCUDA::getConfigureFuncName() const {
   // Legacy CUDA kernel configuration call
   return "cudaConfigureCall";
 }
+
+// Record any local constexpr variables that are passed one way on the host
+// and another on the device.
+void SemaCUDA::recordPotentialODRUsedVariable(
+    MultiExprArg Arguments, OverloadCandidateSet &Candidates) {
+  sema::LambdaScopeInfo *LambdaInfo = SemaRef.getCurLambda();
+  if (!LambdaInfo)
+    return;
+
+  for (unsigned I = 0; I < Arguments.size(); ++I) {
+    auto *DeclRef = dyn_cast<DeclRefExpr>(Arguments[I]);
+    if (!DeclRef)
+      continue;
+    auto *Variable = dyn_cast<VarDecl>(DeclRef->getDecl());
+    if (!Variable || !Variable->isLocalVarDecl() || !Variable->isConstexpr())
+      continue;
+
+    bool HostByValue = false, HostByRef = false;
+    bool DeviceByValue = false, DeviceByRef = false;
+
+    for (OverloadCandidate &Candidate : Candidates) {
+      FunctionDecl *Callee = Candidate.Function;
+      if (!Callee || I >= Callee->getNumParams())
+        continue;
+
+      CUDAFunctionTarget Target = IdentifyTarget(Callee);
+      if (Target == CUDAFunctionTarget::InvalidTarget ||
+          Target == CUDAFunctionTarget::Global)
+        continue;
+
+      bool CoversHost = (Target == CUDAFunctionTarget::Host ||
+                         Target == CUDAFunctionTarget::HostDevice);
+      bool CoversDevice = (Target == CUDAFunctionTarget::Device ||
+                           Target == CUDAFunctionTarget::HostDevice);
+
+      bool IsRef = Callee->getParamDecl(I)->getType()->isReferenceType();
+      HostByValue |= CoversHost && !IsRef;
+      HostByRef |= CoversHost && IsRef;
+      DeviceByValue |= CoversDevice && !IsRef;
+      DeviceByRef |= CoversDevice && IsRef;
+    }
+
+    if ((HostByValue && DeviceByRef) || (HostByRef && DeviceByValue))
+      LambdaInfo->CUDAPotentialODRUsedVars.insert(Variable);
+  }
+}
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index 46933c5c43168..d28a2107d58a9 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -16150,7 +16150,13 @@ Decl *Sema::ActOnFinishFunctionBody(Decl *dcl, Stmt *Body,
   if (FSI->UsesFPIntrin && FD && !FD->hasAttr<StrictFPAttr>())
     FD->addAttr(StrictFPAttr::CreateImplicit(Context));
 
-  sema::AnalysisBasedWarnings::Policy WP = AnalysisWarnings.getDefaultPolicy();
+  SourceLocation AnalysisLoc;
+  if (Body)
+    AnalysisLoc = Body->getEndLoc();
+  else if (FD)
+    AnalysisLoc = FD->getEndLoc();
+  sema::AnalysisBasedWarnings::Policy WP =
+      AnalysisWarnings.getPolicyInEffectAt(AnalysisLoc);
   sema::AnalysisBasedWarnings::Policy *ActivePolicy = nullptr;
 
   // If we skip function body, we can't tell if a function is a coroutine.
diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp
index 3b5cf3661a52f..c960868badb52 100644
--- a/clang/lib/Sema/SemaDeclAttr.cpp
+++ b/clang/lib/Sema/SemaDeclAttr.cpp
@@ -3589,8 +3589,8 @@ static void handleCleanupAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
   // If this ever proves to be a problem it should be easy to fix.
   QualType Ty = S.Context.getPointerType(cast<VarDecl>(D)->getType());
   QualType ParamTy = FD->getParamDecl(0)->getType();
-  if (S.CheckAssignmentConstraints(FD->getParamDecl(0)->getLocation(),
-                                   ParamTy, Ty) != Sema::Compatible) {
+  if (!S.IsAssignConvertCompatible(S.CheckAssignmentConstraints(
+          FD->getParamDecl(0)->getLocation(), ParamTy, Ty))) {
     S.Diag(Loc, diag::err_attribute_cleanup_func_arg_incompatible_type)
       << NI.getName() << ParamTy << Ty;
     return;
diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp
index 01a021443c94f..283d910a09d54 100644
--- a/clang/lib/Sema/SemaExpr.cpp
+++ b/clang/lib/Sema/SemaExpr.cpp
@@ -9062,8 +9062,12 @@ checkPointerTypesForAssignment(Sema &S, QualType LHSType, QualType RHSType,
   }
 
   if (rhptee->isVoidType()) {
+    // In C, void * to another pointer type is compatible, but we want to note
+    // that there will be an implicit conversion happening here.
     if (lhptee->isIncompleteOrObjectType())
-      return ConvTy;
+      return ConvTy == Sema::Compatible && !S.getLangOpts().CPlusPlus
+                 ? Sema::CompatibleVoidPtrToNonVoidPtr
+                 : ConvTy;
 
     // As an extension, we allow cast to/from void* to function pointer.
     assert(lhptee->isFunctionType());
@@ -9098,7 +9102,7 @@ checkPointerTypesForAssignment(Sema &S, QualType LHSType, QualType RHSType,
       // Types are compatible ignoring the sign. Qualifier incompatibility
       // takes priority over sign incompatibility because the sign
       // warning can be disabled.
-      if (ConvTy != Sema::Compatible)
+      if (!S.IsAssignConvertCompatible(ConvTy))
         return ConvTy;
 
       return Sema::IncompatiblePointerSign;
@@ -16597,7 +16601,8 @@ ExprResult Sema::ActOnBlockStmtExpr(SourceLocation CaretLoc,
   BD->setCaptures(Context, Captures, BSI->CXXThisCaptureIndex != 0);
 
   // Pop the block scope now but keep it alive to the end of this function.
-  AnalysisBasedWarnings::Policy WP = AnalysisWarnings.getDefaultPolicy();
+  AnalysisBasedWarnings::Policy WP =
+      AnalysisWarnings.getPolicyInEffectAt(Body->getEndLoc());
   PoppedFunctionScopePtr ScopeRAII = PopFunctionScopeInfo(&WP, BD, BlockTy);
 
   BlockExpr *Result = new (Context)
@@ -16979,7 +16984,11 @@ bool Sema::DiagnoseAssignmentResult(AssignConvertType ConvTy,
   case Compatible:
       DiagnoseAssignmentEnum(DstType, SrcType, SrcExpr);
       return false;
-
+  case CompatibleVoidPtrToNonVoidPtr:
+    // Still a valid conversion, but we may want to diagnose for C++
+    // compatibility reasons.
+    DiagKind = diag::warn_compatible_implicit_pointer_conv;
+    break;
   case PointerToInt:
     if (getLangOpts().CPlusPlus) {
       DiagKind = diag::err_typecheck_convert_pointer_int;
@@ -19516,11 +19525,29 @@ static ExprResult rebuildPotentialResultsAsNonOdrUsed(Sema &S, Expr *E,
     return false;
   };
 
+  // Check whether this expression may be odr-used in CUDA/HIP.
+  auto MaybeCUDAODRUsed = [&]() -> bool {
+    if (!S.LangOpts.CUDA)
+      return false;
+    LambdaScopeInfo *LSI = S.getCurLambda();
+    if (!LSI)
+      return false;
+    auto *DRE = dyn_cast<DeclRefExpr>(E);
+    if (!DRE)
+      return false;
+    auto *VD = dyn_cast<VarDecl>(DRE->getDecl());
+    if (!VD)
+      return false;
+    return LSI->CUDAPotentialODRUsedVars.count(VD);
+  };
+
   // Mark that this expression does not constitute an odr-use.
   auto MarkNotOdrUsed = [&] {
-    S.MaybeODRUseExprs.remove(E);
-    if (LambdaScopeInfo *LSI = S.getCurLambda())
-      LSI->markVariableExprAsNonODRUsed(E);
+    if (!MaybeCUDAODRUsed()) {
+      S.MaybeODRUseExprs.remove(E);
+      if (LambdaScopeInfo *LSI = S.getCurLambda())
+        LSI->markVariableExprAsNonODRUsed(E);
+    }
   };
 
   // C++2a [basic.def.odr]p2:
diff --git a/clang/lib/Sema/SemaExprCXX.cpp b/clang/lib/Sema/SemaExprCXX.cpp
index f5a10e0db85ad..72edb72ceb600 100644
--- a/clang/lib/Sema/SemaExprCXX.cpp
+++ b/clang/lib/Sema/SemaExprCXX.cpp
@@ -6147,9 +6147,8 @@ static APValue EvaluateSizeTTypeTrait(Sema &S, TypeTrait Kind,
       S.Diag(KWLoc, diag::err_arg_is_not_destructurable) << T << ArgRange;
       return APValue();
     }
-    llvm::APSInt V =
-        S.getASTContext().MakeIntValue(*Size, S.getASTContext().getSizeType());
-    return APValue{V};
+    return APValue(
+        S.getASTContext().MakeIntValue(*Size, S.getASTContext().getSizeType()));
     break;
   }
   default:
diff --git a/clang/lib/Sema/SemaInit.cpp b/clang/lib/Sema/SemaInit.cpp
index 0910a820438b0..f04a154bcfd5f 100644
--- a/clang/lib/Sema/SemaInit.cpp
+++ b/clang/lib/Sema/SemaInit.cpp
@@ -8328,10 +8328,9 @@ ExprResult InitializationSequence::Perform(Sema &S,
 
       // If this is a call, allow conversion to a transparent union.
       ExprResult CurInitExprRes = CurInit;
-      if (ConvTy != Sema::Compatible &&
-          Entity.isParameterKind() &&
-          S.CheckTransparentUnionArgumentConstraints(Step->Type, CurInitExprRes)
-            == Sema::Compatible)
+      if (!S.IsAssignConvertCompatible(ConvTy) && Entity.isParameterKind() &&
+          S.CheckTransparentUnionArgumentConstraints(
+              Step->Type, CurInitExprRes) == Sema::Compatible)
         ConvTy = Sema::Compatible;
       if (CurInitExprRes.isInvalid())
         return ExprError();
diff --git a/clang/lib/Sema/SemaObjC.cpp b/clang/lib/Sema/SemaObjC.cpp
index 9b24b5f052119..eba4a7cb6010c 100644
--- a/clang/lib/Sema/SemaObjC.cpp
+++ b/clang/lib/Sema/SemaObjC.cpp
@@ -2341,8 +2341,8 @@ static void checkCollectionLiteralElement(Sema &S, QualType TargetElementType,
   QualType ElementType = Element->getType();
   ExprResult ElementResult(Element);
   if (ElementType->getAs<ObjCObjectPointerType>() &&
-      S.CheckSingleAssignmentConstraints(TargetElementType, ElementResult,
-                                         false, false) != Sema::Compatible) {
+      !S.IsAssignConvertCompatible(S.CheckSingleAssignmentConstraints(
+          TargetElementType, ElementResult, false, false))) {
     S.Diag(Element->getBeginLoc(), diag::warn_objc_collection_literal_element)
         << ElementType << ElementKind << TargetElementType
         << Element->getSourceRange();
diff --git a/clang/lib/Sema/SemaObjCProperty.cpp b/clang/lib/Sema/SemaObjCProperty.cpp
index f37982eddace9..3e962fcb8b0e5 100644
--- a/clang/lib/Sema/SemaObjCProperty.cpp
+++ b/clang/lib/Sema/SemaObjCProperty.cpp
@@ -1349,9 +1349,9 @@ Decl *SemaObjC::ActOnPropertyImplDecl(
             PropertyIvarType->castAs<ObjCObjectPointerType>(),
             IvarType->castAs<ObjCObjectPointerType>());
       else {
-        compat = (SemaRef.CheckAssignmentConstraints(
-                      PropertyIvarLoc, PropertyIvarType, IvarType) ==
-                  Sema::Compatible);
+        compat = SemaRef.IsAssignConvertCompatible(
+            SemaRef.CheckAssignmentConstraints(PropertyIvarLoc,
+                                               PropertyIvarType, IvarType));
       }
       if (!compat) {
         Diag(PropertyDiagLoc, diag::err_property_ivar_type)
@@ -1702,8 +1702,9 @@ bool SemaObjC::DiagnosePropertyAccessorMismatch(ObjCPropertyDecl *property,
              PropertyRValueType->getAs<ObjCObjectPointerType>()) &&
         (getterObjCPtr = GetterType->getAs<ObjCObjectPointerType>()))
       compat = Context.canAssignObjCInterfaces(getterObjCPtr, propertyObjCPtr);
-    else if (SemaRef.CheckAssignmentConstraints(
-                 Loc, GetterType, PropertyRValueType) != Sema::Compatible) {
+    else if (!SemaRef.IsAssignConvertCompatible(
+                 SemaRef.CheckAssignmentConstraints(Loc, GetterType,
+                                                    PropertyRValueType))) {
       Diag(Loc, diag::err_property_accessor_type)
           << property->getDeclName() << PropertyRValueType
           << GetterMethod->getSelector() << GetterType;
diff --git a/clang/lib/Sema/SemaOpenACCClause.cpp b/clang/lib/Sema/SemaOpenACCClause.cpp
index fba40c834e703..6cf6888e2a3a9 100644
--- a/clang/lib/Sema/SemaOpenACCClause.cpp
+++ b/clang/lib/Sema/SemaOpenACCClause.cpp
@@ -2085,32 +2085,31 @@ bool SemaOpenACC::CheckDeclareClause(SemaOpenACC::OpenACCParsedClause &Clause,
       }
     } else {
       const auto *DRE = cast<DeclRefExpr>(VarExpr);
-      const VarDecl *Var = dyn_cast<VarDecl>(DRE->getDecl());
-      if (Var)
+      if (const auto *Var = dyn_cast<VarDecl>(DRE->getDecl())) {
         CurDecl = Var->getCanonicalDecl();
 
-      // OpenACC3.3 2.13:
-      // A 'declare' directive must be in the same scope as the declaration of
-      // any var that appears in the clauses of the directive or any scope
-      // within a C/C++ function.
-      // We can't really check 'scope' here, so we check declaration context,
-      // which is a reasonable approximation, but misses scopes inside of
-      // functions.
-      if (removeLinkageSpecDC(Var->getCanonicalDecl()
-                                  ->getLexicalDeclContext()
-                                  ->getPrimaryContext()) != DC) {
-        Diag(VarExpr->getBeginLoc(), diag::err_acc_declare_same_scope)
-            << Clause.getClauseKind();
-        continue;
-      }
-      // OpenACC3.3 2.13:
-      // C and C++ extern variables may only appear in 'create',
-      // 'copyin', 'deviceptr', 'device_resident', or 'link' clauses on a
-      // 'declare' directive.
-      if (!IsSpecialClause && Var && Var->hasExternalStorage()) {
-        Diag(VarExpr->getBeginLoc(), diag::err_acc_declare_extern)
-            << Clause.getClauseKind();
-        continue;
+        // OpenACC3.3 2.13:
+        // A 'declare' directive must be in the same scope as the declaration of
+        // any var that appears in the clauses of the directive or any scope
+        // within a C/C++ function.
+        // We can't really check 'scope' here, so we check declaration context,
+        // which is a reasonable approximation, but misses scopes inside of
+        // functions.
+        if (removeLinkageSpecDC(
+                Var->getLexicalDeclContext()->getPrimaryContext()) != DC) {
+          Diag(VarExpr->getBeginLoc(), diag::err_acc_declare_same_scope)
+              << Clause.getClauseKind();
+          continue;
+        }
+        // OpenACC3.3 2.13:
+        // C and C++ extern variables may only appear in 'create',
+        // 'copyin', 'deviceptr', 'device_resident', or 'link' clauses on a
+        // 'declare' directive.
+        if (!IsSpecialClause && Var->hasExternalStorage()) {
+          Diag(VarExpr->getBeginLoc(), diag::err_acc_declare_extern)
+              << Clause.getClauseKind();
+          continue;
+        }
       }
 
       // OpenACC3.3 2.13:
diff --git a/clang/lib/Sema/SemaOverload.cpp b/clang/lib/Sema/SemaOverload.cpp
index 5b224b6c08fef..9c8f7bef35e4c 100644
--- a/clang/lib/Sema/SemaOverload.cpp
+++ b/clang/lib/Sema/SemaOverload.cpp
@@ -2518,6 +2518,7 @@ static bool IsStandardConversion(Sema &S, Expr* From, QualType ToType,
   ImplicitConversionKind SecondConv;
   switch (Conv) {
   case Sema::Compatible:
+  case Sema::CompatibleVoidPtrToNonVoidPtr: // __attribute__((overloadable))
     SecondConv = ICK_C_Only_Conversion;
     break;
   // For our purposes, discarding qualifiers is just as bad as using an
@@ -14706,6 +14707,8 @@ ExprResult Sema::BuildOverloadedCallExpr(Scope *S, Expr *Fn,
   // the UnresolvedLookupExpr was type-dependent.
   if (OverloadResult == OR_Success) {
     const FunctionDecl *FDecl = Best->Function;
+    if (LangOpts.CUDA)
+      CUDA().recordPotentialODRUsedVariable(Args, CandidateSet);
     if (FDecl && FDecl->isTemplateInstantiation() &&
         FDecl->getReturnType()->isUndeducedType()) {
 
diff --git a/clang/lib/Serialization/ASTReader.cpp b/clang/lib/Serialization/ASTReader.cpp
index 70b54b7296882..f13a173ec933e 100644
--- a/clang/lib/Serialization/ASTReader.cpp
+++ b/clang/lib/Serialization/ASTReader.cpp
@@ -5980,7 +5980,7 @@ bool ASTReader::readASTFileControlBlock(
        }
       }
     }
-    Stream = SavedStream;
+    Stream = std::move(SavedStream);
   }
 
   // Scan for the UNHASHED_CONTROL_BLOCK_ID block.
diff --git a/clang/lib/Serialization/ASTReaderDecl.cpp b/clang/lib/Serialization/ASTReaderDecl.cpp
index 5545cbc8d608c..0f54aa5c5e062 100644
--- a/clang/lib/Serialization/ASTReaderDecl.cpp
+++ b/clang/lib/Serialization/ASTReaderDecl.cpp
@@ -1076,6 +1076,8 @@ void ASTDeclReader::VisitFunctionDecl(FunctionDecl *FD) {
   FD->setFriendConstraintRefersToEnclosingTemplate(
       FunctionDeclBits.getNextBit());
   FD->setUsesSEHTry(FunctionDeclBits.getNextBit());
+  FD->setIsDestroyingOperatorDelete(FunctionDeclBits.getNextBit());
+  FD->setIsTypeAwareOperatorNewOrDelete(FunctionDeclBits.getNextBit());
 
   FD->EndRangeLoc = readSourceLocation();
   if (FD->isExplicitlyDefaulted())
diff --git a/clang/lib/Serialization/ASTWriterDecl.cpp b/clang/lib/Serialization/ASTWriterDecl.cpp
index 3a7a23481ea98..d1f92cea4dfea 100644
--- a/clang/lib/Serialization/ASTWriterDecl.cpp
+++ b/clang/lib/Serialization/ASTWriterDecl.cpp
@@ -847,6 +847,8 @@ void ASTDeclWriter::VisitFunctionDecl(FunctionDecl *D) {
   FunctionDeclBits.addBit(D->isInstantiatedFromMemberTemplate());
   FunctionDeclBits.addBit(D->FriendConstraintRefersToEnclosingTemplate());
   FunctionDeclBits.addBit(D->usesSEHTry());
+  FunctionDeclBits.addBit(D->isDestroyingOperatorDelete());
+  FunctionDeclBits.addBit(D->isTypeAwareOperatorNewOrDelete());
   Record.push_back(FunctionDeclBits);
 
   Record.AddSourceLocation(D->getEndLoc());
diff --git a/clang/lib/Serialization/ModuleManager.cpp b/clang/lib/Serialization/ModuleManager.cpp
index 61c4e9ed88e9d..d466ea06301a6 100644
--- a/clang/lib/Serialization/ModuleManager.cpp
+++ b/clang/lib/Serialization/ModuleManager.cpp
@@ -110,7 +110,9 @@ ModuleManager::addModule(StringRef FileName, ModuleKind Type,
   // Look for the file entry. This only fails if the expected size or
   // modification time differ.
   OptionalFileEntryRef Entry;
-  if (Type == MK_ExplicitModule || Type == MK_PrebuiltModule) {
+  const bool IgnoreModTime =
+      (Type == MK_ExplicitModule || Type == MK_PrebuiltModule);
+  if (IgnoreModTime) {
     // If we're not expecting to pull this file out of the module cache, it
     // might have a different mtime due to being moved across filesystems in
     // a distributed build. The size must still match, though. (As must the
@@ -120,7 +122,9 @@ ModuleManager::addModule(StringRef FileName, ModuleKind Type,
   // Note: ExpectedSize and ExpectedModTime will be 0 for MK_ImplicitModule
   // when using an ASTFileSignature.
   if (lookupModuleFile(FileName, ExpectedSize, ExpectedModTime, Entry)) {
-    ErrorStr = "module file has a different size or mtime than expected";
+    ErrorStr = IgnoreModTime
+                   ? "module file has a different size than expected"
+                   : "module file has a different size or mtime than expected";
     return OutOfDate;
   }
 
diff --git a/clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp b/clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
index 811888e119449..ba0c7fd77b410 100644
--- a/clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
+++ b/clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
@@ -436,6 +436,13 @@ bool isRetainPtr(const CXXRecordDecl *R) {
   return false;
 }
 
+bool isSmartPtr(const CXXRecordDecl *R) {
+  assert(R);
+  if (auto *TmplR = R->getTemplateInstantiationPattern())
+    return isSmartPtrClass(safeGetName(TmplR));
+  return false;
+}
+
 bool isPtrConversion(const FunctionDecl *F) {
   assert(F);
   if (isCtorOfRefCounted(F))
diff --git a/clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h b/clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
index 97c9d0510e67d..f9fcfe9878d54 100644
--- a/clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
+++ b/clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
@@ -58,6 +58,10 @@ bool isCheckedPtr(const clang::CXXRecordDecl *Class);
 /// \returns true if \p Class is a RetainPtr, false if not.
 bool isRetainPtr(const clang::CXXRecordDecl *Class);
 
+/// \returns true if \p Class is a smart pointer (RefPtr, WeakPtr, etc...),
+/// false if not.
+bool isSmartPtr(const clang::CXXRecordDecl *Class);
+
 /// \returns true if \p Class is ref-countable AND not ref-counted, false if
 /// not, std::nullopt if inconclusive.
 std::optional<bool> isUncounted(const clang::QualType T);
diff --git a/clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefMemberChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefMemberChecker.cpp
index a003fc200727c..10b9749319a57 100644
--- a/clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefMemberChecker.cpp
+++ b/clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefMemberChecker.cpp
@@ -41,7 +41,6 @@ class RawPtrRefMemberChecker
   virtual std::optional<bool>
   isPtrCompatible(const clang::QualType,
                   const clang::CXXRecordDecl *R) const = 0;
-  virtual bool isPtrCls(const clang::CXXRecordDecl *) const = 0;
   virtual const char *typeName() const = 0;
   virtual const char *invariant() const = 0;
 
@@ -205,8 +204,8 @@ class RawPtrRefMemberChecker
     // Ref-counted smartpointers actually have raw-pointer to uncounted type as
     // a member but we trust them to handle it correctly.
     auto CXXRD = llvm::dyn_cast_or_null<CXXRecordDecl>(RD);
-    if (CXXRD)
-      return isPtrCls(CXXRD);
+    if (CXXRD && isSmartPtr(CXXRD))
+      return true;
 
     return false;
   }
@@ -270,10 +269,6 @@ class NoUncountedMemberChecker final : public RawPtrRefMemberChecker {
     return R ? isRefCountable(R) : std::nullopt;
   }
 
-  bool isPtrCls(const clang::CXXRecordDecl *R) const final {
-    return isRefCounted(R);
-  }
-
   const char *typeName() const final { return "ref-countable type"; }
 
   const char *invariant() const final {
@@ -293,10 +288,6 @@ class NoUncheckedPtrMemberChecker final : public RawPtrRefMemberChecker {
     return R ? isCheckedPtrCapable(R) : std::nullopt;
   }
 
-  bool isPtrCls(const clang::CXXRecordDecl *R) const final {
-    return isCheckedPtr(R);
-  }
-
   const char *typeName() const final { return "CheckedPtr capable type"; }
 
   const char *invariant() const final {
@@ -319,10 +310,6 @@ class NoUnretainedMemberChecker final : public RawPtrRefMemberChecker {
     return RTC->isUnretained(QT);
   }
 
-  bool isPtrCls(const clang::CXXRecordDecl *R) const final {
-    return isRetainPtr(R);
-  }
-
   const char *typeName() const final { return "retainable type"; }
 
   const char *invariant() const final {
diff --git a/clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp b/clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
index b88a7cb2dca21..8e05a678fcdbc 100644
--- a/clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
+++ b/clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
@@ -349,6 +349,32 @@ static void canonicalizeDefines(PreprocessorOptions &PPOpts) {
   std::swap(PPOpts.Macros, NewMacros);
 }
 
+class ScanningDependencyDirectivesGetter : public DependencyDirectivesGetter {
+  DependencyScanningWorkerFilesystem *DepFS;
+
+public:
+  ScanningDependencyDirectivesGetter(FileManager &FileMgr) : DepFS(nullptr) {
+    FileMgr.getVirtualFileSystem().visit([&](llvm::vfs::FileSystem &FS) {
+      auto *DFS = llvm::dyn_cast<DependencyScanningWorkerFilesystem>(&FS);
+      if (DFS) {
+        assert(!DepFS && "Found multiple scanning VFSs");
+        DepFS = DFS;
+      }
+    });
+    assert(DepFS && "Did not find scanning VFS");
+  }
+
+  std::unique_ptr<DependencyDirectivesGetter>
+  cloneFor(FileManager &FileMgr) override {
+    return std::make_unique<ScanningDependencyDirectivesGetter>(FileMgr);
+  }
+
+  std::optional<ArrayRef<dependency_directives_scan::Directive>>
+  operator()(FileEntryRef File) override {
+    return DepFS->getDirectiveTokens(File.getName());
+  }
+};
+
 /// A clang tool that runs the preprocessor in a mode that's optimized for
 /// dependency scanning for the given compiler invocation.
 class DependencyScanningAction : public tooling::ToolAction {
@@ -416,6 +442,9 @@ class DependencyScanningAction : public tooling::ToolAction {
         ScanInstance.getInvocation(), ScanInstance.getDiagnostics(),
         DriverFileMgr->getVirtualFileSystemPtr());
 
+    // Create a new FileManager to match the invocation's FileSystemOptions.
+    auto *FileMgr = ScanInstance.createFileManager(FS);
+
     // Use the dependency scanning optimized file system if requested to do so.
     if (DepFS) {
       StringRef ModulesCachePath =
@@ -425,19 +454,10 @@ class DependencyScanningAction : public tooling::ToolAction {
       if (!ModulesCachePath.empty())
         DepFS->setBypassedPathPrefix(ModulesCachePath);
 
-      ScanInstance.getPreprocessorOpts().DependencyDirectivesForFile =
-          [LocalDepFS = DepFS](FileEntryRef File)
-          -> std::optional<ArrayRef<dependency_directives_scan::Directive>> {
-        if (llvm::ErrorOr<EntryRef> Entry =
-                LocalDepFS->getOrCreateFileSystemEntry(File.getName()))
-          if (LocalDepFS->ensureDirectiveTokensArePopulated(*Entry))
-            return Entry->getDirectiveTokens();
-        return std::nullopt;
-      };
+      ScanInstance.setDependencyDirectivesGetter(
+          std::make_unique<ScanningDependencyDirectivesGetter>(*FileMgr));
     }
 
-    // Create a new FileManager to match the invocation's FileSystemOptions.
-    auto *FileMgr = ScanInstance.createFileManager(FS);
     ScanInstance.createSourceManager(*FileMgr);
 
     // Create a collection of stable directories derived from the ScanInstance
diff --git a/clang/test/AST/ByteCode/c.c b/clang/test/AST/ByteCode/c.c
index fe47f9cab1c9f..a7b1fe07f6d84 100644
--- a/clang/test/AST/ByteCode/c.c
+++ b/clang/test/AST/ByteCode/c.c
@@ -1,7 +1,7 @@
-// RUN: %clang_cc1 -triple x86_64-linux -fexperimental-new-constant-interpreter -verify=expected,all -std=c11 -Wcast-qual %s
-// RUN: %clang_cc1 -triple x86_64-linux -fexperimental-new-constant-interpreter -pedantic -verify=pedantic,pedantic-expected,all -std=c11 -Wcast-qual %s
-// RUN: %clang_cc1 -triple x86_64-linux -verify=ref,all -std=c11 -Wcast-qual %s
-// RUN: %clang_cc1 -triple x86_64-linux -pedantic -verify=pedantic,pedantic-ref,all -std=c11 -Wcast-qual %s
+// RUN: %clang_cc1 -triple x86_64-linux -verify=expected,all                   -std=c11 -Wcast-qual           %s -fexperimental-new-constant-interpreter
+// RUN: %clang_cc1 -triple x86_64-linux -verify=pedantic,pedantic-expected,all -std=c11 -Wcast-qual -pedantic %s -fexperimental-new-constant-interpreter
+// RUN: %clang_cc1 -triple x86_64-linux -verify=ref,all                        -std=c11 -Wcast-qual           %s
+// RUN: %clang_cc1 -triple x86_64-linux -verify=pedantic,pedantic-ref,all      -std=c11 -Wcast-qual -pedantic %s
 
 typedef __INTPTR_TYPE__ intptr_t;
 typedef __PTRDIFF_TYPE__ ptrdiff_t;
@@ -231,7 +231,8 @@ int castViaInt[*(int*)(unsigned long)"test"]; // ref-error {{variable length arr
                                               // expected-error {{variable length array}} \
                                               // pedantic-expected-error {{variable length array}}
 
-const void (*const funcp)(void) = (void*)123; // pedantic-warning {{converts between void pointer and function pointer}}
+const void (*const funcp)(void) = (void*)123; // pedantic-warning {{converts between void pointer and function pointer}} \
+                                              // pedantic-expected-note {{this conversion is not allowed in a constant expression}}
 _Static_assert(funcp == (void*)0, ""); // all-error {{failed due to requirement 'funcp == (void *)0'}} \
                                        // pedantic-warning {{expression is not an integer constant expression}}
 _Static_assert(funcp == (void*)123, ""); // pedantic-warning {{equality comparison between function pointer and void pointer}} \
diff --git a/clang/test/AST/ByteCode/cxx11.cpp b/clang/test/AST/ByteCode/cxx11.cpp
index 4c69517304ea7..004f704145afd 100644
--- a/clang/test/AST/ByteCode/cxx11.cpp
+++ b/clang/test/AST/ByteCode/cxx11.cpp
@@ -191,5 +191,6 @@ namespace DynamicCast {
   constexpr S* sptr = &s;
   struct Str {
     int b : reinterpret_cast<S*>(sptr) == reinterpret_cast<S*>(sptr);
+    int g : (S*)(void*)(sptr) == sptr;
   };
 }
diff --git a/clang/test/AST/ByteCode/cxx20.cpp b/clang/test/AST/ByteCode/cxx20.cpp
index 42e6ae33e92e4..8fb19fcfcd3fe 100644
--- a/clang/test/AST/ByteCode/cxx20.cpp
+++ b/clang/test/AST/ByteCode/cxx20.cpp
@@ -119,6 +119,14 @@ constexpr auto b3 = name1() == name1(); // ref-error {{must be initialized by a
 constexpr auto b4 = name1() == name2();
 static_assert(!b4);
 
+constexpr auto bar(const char *p) { return p + __builtin_strlen(p); }
+constexpr auto b5 = bar(p1) == p1;
+static_assert(!b5);
+constexpr auto b6 = bar(p1) == ""; // ref-error {{must be initialized by a constant expression}} \
+                                   // ref-note {{comparison of addresses of potentially overlapping literals}}
+constexpr auto b7 = bar(p1) + 1 == ""; // both-error {{must be initialized by a constant expression}} \
+                                       // both-note {{comparison against pointer '&"test1"[6]' that points past the end of a complete object has unspecified value}}
+
 namespace UninitializedFields {
   class A {
   public:
diff --git a/clang/test/AST/ByteCode/cxx23.cpp b/clang/test/AST/ByteCode/cxx23.cpp
index d0ade4f5278b1..ce18a9d473302 100644
--- a/clang/test/AST/ByteCode/cxx23.cpp
+++ b/clang/test/AST/ByteCode/cxx23.cpp
@@ -316,3 +316,9 @@ namespace ZeroSizedArray {
   }
   static_assert(foo() == 1);
 }
+namespace VoidCast {
+  constexpr int a = 12;
+  constexpr const int *b = &a;
+  constexpr int *f = (int*)(void*)b; // all-error {{must be initialized by a constant expression}} \
+                                     // all-note {{cast from 'void *' is not allowed in a constant expression}}
+}
diff --git a/clang/test/AST/ByteCode/cxx26.cpp b/clang/test/AST/ByteCode/cxx26.cpp
index cd6b533065010..cd786b17ca9ab 100644
--- a/clang/test/AST/ByteCode/cxx26.cpp
+++ b/clang/test/AST/ByteCode/cxx26.cpp
@@ -31,3 +31,8 @@ namespace ReplaceableAlloc {
   static_assert(foo()); // both-error {{not an integral constant expression}} \
                         // both-note {{in call to}}
 }
+
+constexpr int a = 12;
+constexpr const int *b = &a;
+constexpr int *f = (int*)(void*)b;
+static_assert(*f == 12);
diff --git a/clang/test/AST/ByteCode/i686.cpp b/clang/test/AST/ByteCode/i686.cpp
new file mode 100644
index 0000000000000..dafa3eae284c5
--- /dev/null
+++ b/clang/test/AST/ByteCode/i686.cpp
@@ -0,0 +1,17 @@
+// RUN: %clang_cc1 -triple i686-pc-linux-gnu -fexperimental-new-constant-interpreter -verify=expected,both %s
+// RUN: %clang_cc1 -triple i686-pc-linux-gnu                                         -verify=ref,both      %s
+
+
+// both-no-diagnostics
+
+/// FIXME: Allocating the array below causes OOM failures with the bytecode interpreter.
+#if 0
+char melchizedek[2200000000];
+typedef decltype(melchizedek[1] - melchizedek[0]) ptrdiff_t;
+constexpr ptrdiff_t d1 = &melchizedek[0x7fffffff] - &melchizedek[0];
+constexpr ptrdiff_t d2 = &melchizedek[0x80000000u] - &melchizedek[0]; // both-error {{constant expression}} \
+                                                                      // both-note {{ 2147483648 }}
+constexpr ptrdiff_t d3 = &melchizedek[0] - &melchizedek[0x80000000u];
+constexpr ptrdiff_t d4 = &melchizedek[0] - &melchizedek[0x80000001u]; // both-error {{constant expression}} \
+                                                                      // both-note {{ -2147483649 }}
+#endif
diff --git a/clang/test/AST/ByteCode/literals.cpp b/clang/test/AST/ByteCode/literals.cpp
index 6b33c5cc22367..c36289db6e85c 100644
--- a/clang/test/AST/ByteCode/literals.cpp
+++ b/clang/test/AST/ByteCode/literals.cpp
@@ -1357,6 +1357,22 @@ namespace VolatileReads {
   const volatile int b = 1;
   static_assert(b, ""); // both-error {{not an integral constant expression}} \
                         // both-note {{read of volatile-qualified type 'const volatile int' is not allowed in a constant expression}}
+
+
+  constexpr int a = 12;
+  constexpr volatile int c = (volatile int&)a; // both-error {{must be initialized by a constant expression}} \
+                                               // both-note {{read of volatile-qualified type 'volatile int'}}
+
+  volatile constexpr int n1 = 0; // both-note {{here}}
+  volatile const int n2 = 0; // both-note {{here}}
+  constexpr int m1 = n1; // both-error {{constant expression}} \
+                         // both-note {{read of volatile-qualified type 'const volatile int'}}
+  constexpr int m2 = n2; // both-error {{constant expression}} \
+                         // both-note {{read of volatile-qualified type 'const volatile int'}}
+  constexpr int m1b = const_cast<const int&>(n1); // both-error {{constant expression}} \
+                                                  // both-note {{read of volatile object 'n1'}}
+  constexpr int m2b = const_cast<const int&>(n2); // both-error {{constant expression}} \
+                                                  // both-note {{read of volatile object 'n2'}}
 }
 #if __cplusplus >= 201703L
 namespace {
diff --git a/clang/test/AST/ByteCode/records.cpp b/clang/test/AST/ByteCode/records.cpp
index da851785323a5..b4059f009b887 100644
--- a/clang/test/AST/ByteCode/records.cpp
+++ b/clang/test/AST/ByteCode/records.cpp
@@ -1787,3 +1787,26 @@ namespace IntegralBaseCast {
 
   static_assert(f() == 0, "");
 }
+
+namespace AccessMismatch {
+  struct A {
+  public:
+    constexpr A() : a(0), b(0) {}
+    int a;
+    constexpr bool cmp() const { return &a < &b; } // both-note {{comparison of address of fields 'a' and 'b' of 'A' with differing access specifiers (public vs private) has unspecified value}}
+  private:
+    int b;
+  };
+  static_assert(A().cmp(), ""); // both-error {{constant expression}} \
+                                // both-note {{in call}}
+
+  class B {
+  public:
+    A a;
+    constexpr bool cmp() const { return &a.a < &b.a; } // both-note {{comparison of address of fields 'a' and 'b' of 'B' with differing access specifiers (public vs protected) has unspecified value}}
+  protected:
+    A b;
+  };
+  static_assert(B().cmp(), ""); // both-error {{constant expression}} \
+                                // both-note {{in call}}
+}
diff --git a/clang/test/Analysis/Checkers/WebKit/unchecked-members.cpp b/clang/test/Analysis/Checkers/WebKit/unchecked-members.cpp
index 0189b0cd50fcc..048ffbffcdefb 100644
--- a/clang/test/Analysis/Checkers/WebKit/unchecked-members.cpp
+++ b/clang/test/Analysis/Checkers/WebKit/unchecked-members.cpp
@@ -50,3 +50,12 @@ namespace ignore_unions {
   void forceTmplToInstantiate(FooTmpl<CheckedObj>) { }
 
 } // namespace ignore_unions
+
+namespace checked_ptr_ref_ptr_capable {
+
+  RefCountableAndCheckable* provide();
+  void foo() {
+    RefPtr<RefCountableAndCheckable> foo = provide();
+  }
+
+} // checked_ptr_ref_ptr_capable
diff --git a/clang/test/Analysis/Checkers/WebKit/uncounted-members.cpp b/clang/test/Analysis/Checkers/WebKit/uncounted-members.cpp
index 1bdbaedefbfeb..130777a9a5fee 100644
--- a/clang/test/Analysis/Checkers/WebKit/uncounted-members.cpp
+++ b/clang/test/Analysis/Checkers/WebKit/uncounted-members.cpp
@@ -34,7 +34,7 @@ namespace members {
   private:
     RefCountable* a = nullptr;
   };
-}
+} // members
 
 namespace ignore_unions {
   union Foo {
@@ -49,7 +49,7 @@ namespace ignore_unions {
   };
 
   void forceTmplToInstantiate(RefPtr<RefCountable>) {}
-}
+} // ignore_unions
 
 namespace ignore_system_header {
 
@@ -67,4 +67,13 @@ namespace ignore_non_ref_countable {
   struct Bar {
     Foo* foo;
   };
-}
\ No newline at end of file
+} // ignore_non_ref_countable
+
+namespace checked_ptr_ref_ptr_capable {
+
+  RefCountableAndCheckable* provide();
+  void foo() {
+    CheckedPtr<RefCountableAndCheckable> foo = provide();
+  }
+
+} // checked_ptr_ref_ptr_capable
diff --git a/clang/test/Analysis/pragma-diag-control.cpp b/clang/test/Analysis/pragma-diag-control.cpp
new file mode 100644
index 0000000000000..470960c030d0f
--- /dev/null
+++ b/clang/test/Analysis/pragma-diag-control.cpp
@@ -0,0 +1,83 @@
+// RUN: %clang_cc1 -fsyntax-only -verify -Werror=unreachable-code-aggressive %s
+
+// Test that analysis-based warnings honor #pragma diagnostic controls.
+
+struct [[clang::consumable(unconsumed)]] Linear {
+  [[clang::return_typestate(unconsumed)]]
+  Linear() {}
+  [[clang::callable_when(consumed)]]
+  ~Linear() {}
+};
+
+int a() {	
+  Linear l;
+  return 0; // No -Wconsumed diagnostic, analysis is not enabled.
+  return 1; // expected-error {{'return' will never be executed}}
+}
+
+#pragma clang diagnostic push
+#pragma clang diagnostic error "-Wconsumed"
+int b() {
+  Linear l;
+  return 0;  // expected-error {{invalid invocation of method '~Linear' on object 'l' while it is in the 'unconsumed' state}}
+  return 1;  // expected-error {{'return' will never be executed}}
+}
+#pragma clang diagnostic pop
+
+int c() {
+#pragma clang diagnostic push
+#pragma clang diagnostic error "-Wconsumed"
+  Linear l;
+  return 0; // expected-error {{invalid invocation of method '~Linear' on object 'l' while it is in the 'unconsumed' state}}
+  return 1; // expected-error {{'return' will never be executed}}
+#pragma clang diagnostic pop
+}
+
+int d() {
+#pragma clang diagnostic push
+#pragma clang diagnostic error "-Wconsumed"
+#pragma clang diagnostic ignored "-Wunreachable-code-aggressive"
+  Linear l;
+  return 0; // expected-error {{invalid invocation of method '~Linear' on object 'l' while it is in the 'unconsumed' state}}
+  return 1; // Diagnostic is ignored
+}
+#pragma clang diagnostic pop
+
+int e() {
+#pragma clang diagnostic push
+#pragma clang diagnostic error "-Wconsumed"
+#pragma clang diagnostic ignored "-Wunreachable-code-aggressive"
+  Linear l;
+  return 0; // expected-error {{invalid invocation of method '~Linear' on object 'l' while it is in the 'unconsumed' state}}
+  return 1; // Diagnostic is ignored
+#pragma clang diagnostic pop
+}
+
+int f() {
+  Linear l;
+  return 0; // No -Wconsumed diagnostic, analysis is not enabled
+  return 1; // expected-error {{'return' will never be executed}}
+#pragma clang diagnostic push
+#pragma clang diagnostic ignored "-Wunreachable-code-aggressive"
+}
+#pragma clang diagnostic pop	
+
+int g() {
+  Linear l;
+  return 0; // No -Wconsumed diagnostic, the diagnostic generated at } is not enabled on this line.
+  return 1; // expected-error {{'return' will never be executed}}
+#pragma clang diagnostic push
+#pragma clang diagnostic warning "-Wconsumed"
+}
+#pragma clang diagnostic pop
+
+int h() {
+#pragma clang diagnostic push
+#pragma clang diagnostic error "-Wconsumed"
+#pragma clang diagnostic ignored "-Wunreachable-code-aggressive"
+#pragma clang diagnostic pop
+
+  Linear l;
+  return 0; // No -Wconsumed diagnostic, the diagnostic generated at } is not enabled on this line.
+  return 1; // expected-error {{'return' will never be executed}}
+}
diff --git a/clang/test/CIR/CodeGen/struct.c b/clang/test/CIR/CodeGen/struct.c
index b78a2367bda3a..c91a14e0637c1 100644
--- a/clang/test/CIR/CodeGen/struct.c
+++ b/clang/test/CIR/CodeGen/struct.c
@@ -7,6 +7,12 @@
 
 // For LLVM IR checks, the structs are defined before the variables, so these
 // checks are at the top.
+// CIR-DAG: !rec_IncompleteS = !cir.record<struct "IncompleteS" incomplete>
+// CIR-DAG: !rec_CompleteS = !cir.record<struct "CompleteS" {!s32i, !s8i}>
+// CIR-DAG: !rec_OuterS = !cir.record<struct "OuterS" {!rec_InnerS, !s32i}>  
+// CIR-DAG: !rec_InnerS = !cir.record<struct "InnerS" {!s32i, !s8i}>
+// CIR-DAG: !rec_PackedS = !cir.record<struct "PackedS" packed {!s32i, !s8i}>
+// CIR-DAG: !rec_PackedAndPaddedS = !cir.record<struct "PackedAndPaddedS" packed padded {!s32i, !s8i, !u8i}>
 // LLVM-DAG: %struct.CompleteS = type { i32, i8 }
 // LLVM-DAG: %struct.OuterS = type { %struct.InnerS, i32 }
 // LLVM-DAG: %struct.InnerS = type { i32, i8 }
@@ -20,8 +26,7 @@
 
 struct IncompleteS *p;
 
-// CIR:      cir.global external @p = #cir.ptr<null> : !cir.ptr<!cir.record<struct
-// CIR-SAME:     "IncompleteS" incomplete>>
+// CIR:      cir.global external @p = #cir.ptr<null> : !cir.ptr<!rec_IncompleteS>
 // LLVM-DAG: @p = dso_local global ptr null
 // OGCG-DAG: @p = global ptr null, align 8
 
@@ -30,10 +35,9 @@ struct CompleteS {
   char b;
 } cs;
 
-// CIR:       cir.global external @cs = #cir.zero : !cir.record<struct
-// CIR-SAME:      "CompleteS" {!s32i, !s8i}>
-// LLVM-DAG:      @cs = dso_local global %struct.CompleteS zeroinitializer
-// OGCG-DAG:      @cs = global %struct.CompleteS zeroinitializer, align 4
+// CIR:       cir.global external @cs = #cir.zero : !rec_CompleteS
+// LLVM-DAG:  @cs = dso_local global %struct.CompleteS zeroinitializer
+// OGCG-DAG:  @cs = global %struct.CompleteS zeroinitializer, align 4
 
 struct InnerS {
   int a;
@@ -47,10 +51,9 @@ struct OuterS {
 
 struct OuterS os;
 
-// CIR:       cir.global external @os = #cir.zero : !cir.record<struct
-// CIR-SAME:      "OuterS" {!cir.record<struct "InnerS" {!s32i, !s8i}>, !s32i}>
-// LLVM-DAG:      @os = dso_local global %struct.OuterS zeroinitializer
-// OGCG-DAG:      @os = global %struct.OuterS zeroinitializer, align 4
+// CIR:       cir.global external @os = #cir.zero : !rec_OuterS
+// LLVM-DAG:  @os = dso_local global %struct.OuterS zeroinitializer
+// OGCG-DAG:  @os = global %struct.OuterS zeroinitializer, align 4
 
 #pragma pack(push)
 #pragma pack(1)
@@ -60,20 +63,18 @@ struct PackedS {
   char a1;
 } ps;
 
-// CIR:       cir.global external @ps = #cir.zero : !cir.record<struct "PackedS"
-// CIR-SAME:      packed {!s32i, !s8i}>
-// LLVM-DAG:      @ps = dso_local global %struct.PackedS zeroinitializer
-// OGCG-DAG:      @ps = global %struct.PackedS zeroinitializer, align 1
+// CIR:       cir.global external @ps = #cir.zero : !rec_PackedS
+// LLVM-DAG:  @ps = dso_local global %struct.PackedS zeroinitializer
+// OGCG-DAG:  @ps = global %struct.PackedS zeroinitializer, align 1
 
 struct PackedAndPaddedS {
   int  b0;
   char b1;
 } __attribute__((aligned(2))) pps;
 
-// CIR:       cir.global external @pps = #cir.zero : !cir.record<struct
-// CIR-SAME:      "PackedAndPaddedS" packed padded {!s32i, !s8i, !u8i}>
-// LLVM-DAG:      @pps = dso_local global %struct.PackedAndPaddedS zeroinitializer
-// OGCG-DAG:      @pps = global %struct.PackedAndPaddedS zeroinitializer, align 2
+// CIR:       cir.global external @pps = #cir.zero : !rec_PackedAndPaddedS
+// LLVM-DAG:  @pps = dso_local global %struct.PackedAndPaddedS zeroinitializer
+// OGCG-DAG:  @pps = global %struct.PackedAndPaddedS zeroinitializer, align 2
 
 #pragma pack(pop)
 
@@ -82,9 +83,7 @@ void f(void) {
 }
 
 // CIR:      cir.func @f()
-// CIR-NEXT:   cir.alloca !cir.ptr<!cir.record<struct "IncompleteS" incomplete>>,
-// CIR-SAME:       !cir.ptr<!cir.ptr<!cir.record<struct
-// CIR-SAME:       "IncompleteS" incomplete>>>, ["p"]
+// CIR-NEXT:   cir.alloca !cir.ptr<!rec_IncompleteS>, !cir.ptr<!cir.ptr<!rec_IncompleteS>>, ["p"] {alignment = 8 : i64}
 // CIR-NEXT:   cir.return
 
 // LLVM:      define void @f()
@@ -101,9 +100,7 @@ void f2(void) {
 }
 
 // CIR:      cir.func @f2()
-// CIR-NEXT:   cir.alloca !cir.record<struct "CompleteS" {!s32i, !s8i}>,
-// CIR-SAME:       !cir.ptr<!cir.record<struct "CompleteS" {!s32i, !s8i}>>,
-// CIR-SAME:       ["s"] {alignment = 4 : i64}
+// CIR-NEXT:   cir.alloca !rec_CompleteS, !cir.ptr<!rec_CompleteS>, ["s"] {alignment = 4 : i64}
 // CIR-NEXT:   cir.return
 
 // LLVM:      define void @f2()
@@ -160,7 +157,7 @@ char f4(int a, struct CompleteS *p) {
   return p->b;
 }
 
-// CIR:      cir.func @f4(%[[ARG_A:.*]]: !s32i {{.*}}, %[[ARG_P:.*]]: !cir.ptr<!cir.record<struct "CompleteS" {!s32i, !s8i}>>
+// CIR:      cir.func @f4(%[[ARG_A:.*]]: !s32i {{.*}}, %[[ARG_P:.*]]: !cir.ptr<!rec_CompleteS>
 // CIR-NEXT:   %[[A_ADDR:.*]] = cir.alloca {{.*}} ["a", init] {alignment = 4 : i64}
 // CIR-NEXT:   %[[P_ADDR:.*]] = cir.alloca {{.*}} ["p", init] {alignment = 8 : i64}
 // CIR-NEXT:   %[[RETVAL_ADDR:.*]] = cir.alloca {{.*}} ["__retval"] {alignment = 1 : i64}
diff --git a/clang/test/CIR/CodeGen/struct.cpp b/clang/test/CIR/CodeGen/struct.cpp
index 6197340a7d36b..c54eca20840b5 100644
--- a/clang/test/CIR/CodeGen/struct.cpp
+++ b/clang/test/CIR/CodeGen/struct.cpp
@@ -8,7 +8,7 @@
 struct IncompleteS;
 IncompleteS *p;
 
-// CIR: cir.global external @p = #cir.ptr<null> : !cir.ptr<!cir.record<struct "IncompleteS" incomplete>>
+// CIR: cir.global external @p = #cir.ptr<null> : !cir.ptr<!rec_IncompleteS>
 // LLVM: @p = dso_local global ptr null
 // OGCG: @p = global ptr null, align 8
 
@@ -17,8 +17,7 @@ void f(void) {
 }
 
 // CIR:      cir.func @f()
-// CIR-NEXT:   cir.alloca !cir.ptr<!cir.record<struct "IncompleteS" incomplete>>,
-// CIR-SAME:       !cir.ptr<!cir.ptr<!cir.record<struct "IncompleteS" incomplete>>>, ["p"]
+// CIR-NEXT:   cir.alloca !cir.ptr<!rec_IncompleteS>, !cir.ptr<!cir.ptr<!rec_IncompleteS>>, ["p"]
 // CIR-NEXT:   cir.return
 
 // LLVM:      define void @f()
diff --git a/clang/test/CIR/CodeGen/typedef.c b/clang/test/CIR/CodeGen/typedef.c
index 17fce13abf38a..a87e6ffb1843a 100644
--- a/clang/test/CIR/CodeGen/typedef.c
+++ b/clang/test/CIR/CodeGen/typedef.c
@@ -11,9 +11,7 @@ void local_typedef(void) {
 }
 
 // CIR:      cir.func @local_typedef()
-// CIR:        cir.alloca !cir.record<struct "Struct" {!s32i}>,
-// CIR-SAME:       !cir.ptr<!cir.record<struct "Struct" {!s32i}>>, ["s"]
-// CIR-SAME:       {alignment = 4 : i64}
+// CIR:        cir.alloca !rec_Struct, !cir.ptr<!rec_Struct>, ["s"] {alignment = 4 : i64}
 // CIR:        cir.return
 
 // LLVM: %struct.Struct = type { i32 }
diff --git a/clang/test/CIR/CodeGen/union.c b/clang/test/CIR/CodeGen/union.c
index 075d0d2315508..c4db37f835add 100644
--- a/clang/test/CIR/CodeGen/union.c
+++ b/clang/test/CIR/CodeGen/union.c
@@ -7,7 +7,7 @@
 
 union IncompleteU *p;
 
-// CIR: cir.global external @p = #cir.ptr<null> : !cir.ptr<!cir.record<union "IncompleteU" incomplete>>
+// CIR: cir.global external @p = #cir.ptr<null> : !cir.ptr<!rec_IncompleteU>
 // LLVM: @p = dso_local global ptr null
 // OGCG: @p = global ptr null, align 8
 
@@ -16,8 +16,7 @@ void f(void) {
 }
 
 // CIR: cir.func @f()
-// CIR-NEXT: cir.alloca !cir.ptr<!cir.record<union "IncompleteU" incomplete>>,
-// CIR-SAME:     !cir.ptr<!cir.ptr<!cir.record<union "IncompleteU" incomplete>>>, ["p"]
+// CIR-NEXT: cir.alloca !cir.ptr<!rec_IncompleteU>, !cir.ptr<!cir.ptr<!rec_IncompleteU>>, ["p"]
 // CIR-NEXT: cir.return
 
 // LLVM:      define void @f()
diff --git a/clang/test/CIR/CodeGenOpenACC/data.c b/clang/test/CIR/CodeGenOpenACC/data.c
index 9e636f68aad1b..29fd465708054 100644
--- a/clang/test/CIR/CodeGenOpenACC/data.c
+++ b/clang/test/CIR/CodeGenOpenACC/data.c
@@ -1,7 +1,9 @@
 // RUN: %clang_cc1 -fopenacc -emit-cir -fclangir %s -o - | FileCheck %s
 
-void acc_data(void) {
-  // CHECK: cir.func @acc_data() {
+void acc_data(int cond) {
+  // CHECK: cir.func @acc_data(%[[ARG:.*]]: !s32i{{.*}}) {
+  // CHECK-NEXT: %[[COND:.*]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["cond", init]
+  // CHECK-NEXT: cir.store %[[ARG]], %[[COND]] : !s32i, !cir.ptr<!s32i>
 
 #pragma acc data default(none)
   {
@@ -33,5 +35,79 @@ void acc_data(void) {
   // CHECK-NEXT: acc.terminator
   // CHECK-NEXT: } attributes {defaultAttr = #acc<defaultvalue present>}
 
+#pragma acc data default(none) async
+  {}
+  // CHECK-NEXT: acc.data {
+  // CHECK-NEXT: acc.terminator
+  // CHECK-NEXT: } attributes {asyncOnly = [#acc.device_type<none>], defaultAttr = #acc<defaultvalue none>}
+
+#pragma acc data default(none) async(cond)
+  {}
+  // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr<!s32i>, !s32i
+  // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32
+  // CHECK-NEXT: acc.data async(%[[CONV_CAST]] : si32) {
+  // CHECK-NEXT: acc.terminator
+  // CHECK-NEXT: } attributes {defaultAttr = #acc<defaultvalue none>}
+
+#pragma acc data default(none) async device_type(nvidia, radeon) async
+  {}
+  // CHECK-NEXT: acc.data {
+  // CHECK-NEXT: acc.terminator
+  // CHECK-NEXT: } attributes {asyncOnly = [#acc.device_type<none>, #acc.device_type<nvidia>, #acc.device_type<radeon>], defaultAttr = #acc<defaultvalue none>}
+
+#pragma acc data default(none) async(3) device_type(nvidia, radeon) async(cond)
+  {}
+  // CHECK-NEXT: %[[THREE_LITERAL:.*]] = cir.const #cir.int<3> : !s32i
+  // CHECK-NEXT: %[[THREE_CAST:.*]] = builtin.unrealized_conversion_cast %[[THREE_LITERAL]] : !s32i to si32
+  // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr<!s32i>, !s32i
+  // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32
+  // CHECK-NEXT: acc.data async(%[[THREE_CAST]] : si32, %[[CONV_CAST]] : si32 [#acc.device_type<nvidia>], %[[CONV_CAST]] : si32 [#acc.device_type<radeon>]) {
+  // CHECK-NEXT: acc.terminator
+  // CHECK-NEXT: } attributes {defaultAttr = #acc<defaultvalue none>}
+
+#pragma acc data default(none) async device_type(nvidia, radeon) async(cond)
+  {}
+  // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr<!s32i>, !s32i
+  // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32
+  // CHECK-NEXT: acc.data async(%[[CONV_CAST]] : si32 [#acc.device_type<nvidia>], %[[CONV_CAST]] : si32 [#acc.device_type<radeon>]) {
+  // CHECK-NEXT: acc.terminator
+  // CHECK-NEXT: } attributes {asyncOnly = [#acc.device_type<none>], defaultAttr = #acc<defaultvalue none>}
+
+#pragma acc data default(none) async(3) device_type(nvidia, radeon) async
+  {}
+  // CHECK-NEXT: %[[THREE_LITERAL:.*]] = cir.const #cir.int<3> : !s32i
+  // CHECK-NEXT: %[[THREE_CAST:.*]] = builtin.unrealized_conversion_cast %[[THREE_LITERAL]] : !s32i to si32
+  // CHECK-NEXT: acc.data async(%[[THREE_CAST]] : si32) {
+  // CHECK-NEXT: acc.terminator
+  // CHECK-NEXT: } attributes {asyncOnly = [#acc.device_type<nvidia>, #acc.device_type<radeon>], defaultAttr = #acc<defaultvalue none>}
+
+#pragma acc data default(none) if(cond)
+  {}
+  // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr<!s32i>, !s32i
+  // CHECK-NEXT: %[[BOOL_CAST:.*]] = cir.cast(int_to_bool, %[[COND_LOAD]] : !s32i), !cir.bool
+  // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[BOOL_CAST]] : !cir.bool to i1
+  // CHECK-NEXT: acc.data if(%[[CONV_CAST]]) {
+  // CHECK-NEXT: acc.terminator
+  // CHECK-NEXT: } attributes {defaultAttr = #acc<defaultvalue none>}
+
+#pragma acc data default(none) if(1)
+  {}
+  // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i
+  // CHECK-NEXT: %[[BOOL_CAST:.*]] = cir.cast(int_to_bool, %[[ONE_LITERAL]] : !s32i), !cir.bool
+  // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[BOOL_CAST]] : !cir.bool to i1
+  // CHECK-NEXT: acc.data if(%[[CONV_CAST]]) {
+  // CHECK-NEXT: acc.terminator
+  // CHECK-NEXT: } attributes {defaultAttr = #acc<defaultvalue none>}
+
+#pragma acc data default(none) if(cond == 1)
+  {}
+  // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr<!s32i>, !s32i
+  // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i
+  // CHECK-NEXT: %[[EQ_RES:.*]] = cir.cmp(eq, %[[COND_LOAD]], %[[ONE_LITERAL]]) : !s32i, !cir.bool
+  // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[EQ_RES]] : !cir.bool to i1
+  // CHECK-NEXT: acc.data if(%[[CONV_CAST]]) {
+  // CHECK-NEXT: acc.terminator
+  // CHECK-NEXT: } attributes {defaultAttr = #acc<defaultvalue none>}
+
   // CHECK-NEXT: cir.return
 }
diff --git a/clang/test/CIR/IR/struct.cir b/clang/test/CIR/IR/struct.cir
index b6ed1d78b354a..7f0ce07631182 100644
--- a/clang/test/CIR/IR/struct.cir
+++ b/clang/test/CIR/IR/struct.cir
@@ -1,9 +1,15 @@
 // RUN: cir-opt %s | FileCheck %s
 
+!rec_S = !cir.record<struct "S" incomplete>
+!rec_U = !cir.record<union "U" incomplete>
+
+// CHECK: !rec_S = !cir.record<struct "S" incomplete>
+// CHECK: !rec_U = !cir.record<union "U" incomplete>
+
 module  {
-    cir.global external @p1 = #cir.ptr<null> : !cir.ptr<!cir.record<struct "S" incomplete>>
-    cir.global external @p2 = #cir.ptr<null> : !cir.ptr<!cir.record<union "U" incomplete>>
+    cir.global external @p1 = #cir.ptr<null> : !cir.ptr<!rec_S>
+    cir.global external @p2 = #cir.ptr<null> : !cir.ptr<!rec_U>
 }
 
-// CHECK: cir.global external @p1 = #cir.ptr<null> : !cir.ptr<!cir.record<struct "S" incomplete>>
-// CHECK: cir.global external @p2 = #cir.ptr<null> : !cir.ptr<!cir.record<union "U" incomplete>>
+// CHECK: cir.global external @p1 = #cir.ptr<null> : !cir.ptr<!rec_S>
+// CHECK: cir.global external @p2 = #cir.ptr<null> : !cir.ptr<!rec_U>
diff --git a/clang/test/CodeGen/AArch64/gcs.c b/clang/test/CodeGen/AArch64/gcs.c
index 767b1b8bfaf2d..64785be2af623 100644
--- a/clang/test/CodeGen/AArch64/gcs.c
+++ b/clang/test/CodeGen/AArch64/gcs.c
@@ -1,4 +1,4 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --clang-args ['-target-feature', '+gcs'] --version 2
 // RUN: %clang_cc1 -triple aarch64-eabi -target-feature +gcs -emit-llvm %s -o - | FileCheck %s
 
 #include <arm_acle.h>
@@ -51,6 +51,6 @@ uint64_t test_gcspopm() {
 // CHECK-NEXT:    [[TMP2:%.*]] = call ptr @llvm.aarch64.gcsss(ptr [[TMP1]])
 // CHECK-NEXT:    ret ptr [[TMP2]]
 //
-const void *test_gcsss(const void *p) {
+void *test_gcsss(void *p) {
   return __gcsss(p);
 }
diff --git a/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c b/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
new file mode 100644
index 0000000000000..f0d6f9d341dfc
--- /dev/null
+++ b/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
@@ -0,0 +1,160 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64 -target-feature +sme-f8f32 -target-feature +sme-f8f16 -target-feature +sme-mop4 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64 -target-feature +sme-f8f32 -target-feature +sme-f8f16 -target-feature +sme-mop4 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -triple aarch64 -target-feature +sme-f8f32 -target-feature +sme-f8f16 -target-feature +sme-mop4 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
+// RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -triple aarch64 -target-feature +sme-f8f32 -target-feature +sme-f8f16 -target-feature +sme-mop4 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64 -target-feature +sme-f8f32 -target-feature +sme-f8f16 -target-feature +sme-mop4 -target-feature +sme -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
+
+
+#include <arm_sme.h>
+
+#ifdef SME_OVERLOADED_FORMS
+#define SME_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED,A5) A1##A3##A5
+#else
+#define SME_ACLE_FUNC(A1,A2,A3,A4,A5) A1##A2##A3##A4##A5
+#endif
+
+// CHECK-LABEL: define dso_local void @test_svmop4a_1x1_za16_mf8_mf8_fpm(
+// CHECK-SAME: <vscale x 16 x i8> [[ZN:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])
+// CHECK-NEXT:    tail call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x1.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN]], <vscale x 16 x i8> [[ZM]])
+// CHECK-NEXT:    ret void
+//
+// CPP-CHECK-LABEL: define dso_local void @_Z33test_svmop4a_1x1_za16_mf8_mf8_fpmu13__SVMfloat8_tS_m(
+// CPP-CHECK-SAME: <vscale x 16 x i8> [[ZN:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0:[0-9]+]] {
+// CPP-CHECK-NEXT:  [[ENTRY:.*:]]
+// CPP-CHECK-NEXT:    tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])
+// CPP-CHECK-NEXT:    tail call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x1.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN]], <vscale x 16 x i8> [[ZM]])
+// CPP-CHECK-NEXT:    ret void
+//
+void test_svmop4a_1x1_za16_mf8_mf8_fpm(svmfloat8_t zn, svmfloat8_t zm, fpm_t fpmr) __arm_streaming __arm_inout("za") {
+    SME_ACLE_FUNC(svmop4a,_1x1,_za16,_mf8_mf8,_fpm)(1, zn, zm, fpmr);
+}
+
+// CHECK-LABEL: define dso_local void @test_svmop4a_1x2_za16_mf8_mf8_fpm(
+// CHECK-SAME: <vscale x 16 x i8> [[ZN:%.*]], <vscale x 16 x i8> [[ZM_COERCE0:%.*]], <vscale x 16 x i8> [[ZM_COERCE1:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])
+// CHECK-NEXT:    tail call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x2.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN]], <vscale x 16 x i8> [[ZM_COERCE0]], <vscale x 16 x i8> [[ZM_COERCE1]])
+// CHECK-NEXT:    ret void
+//
+// CPP-CHECK-LABEL: define dso_local void @_Z33test_svmop4a_1x2_za16_mf8_mf8_fpmu13__SVMfloat8_t13svmfloat8x2_tm(
+// CPP-CHECK-SAME: <vscale x 16 x i8> [[ZN:%.*]], <vscale x 16 x i8> [[ZM_COERCE0:%.*]], <vscale x 16 x i8> [[ZM_COERCE1:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {
+// CPP-CHECK-NEXT:  [[ENTRY:.*:]]
+// CPP-CHECK-NEXT:    tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])
+// CPP-CHECK-NEXT:    tail call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x2.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN]], <vscale x 16 x i8> [[ZM_COERCE0]], <vscale x 16 x i8> [[ZM_COERCE1]])
+// CPP-CHECK-NEXT:    ret void
+//
+void test_svmop4a_1x2_za16_mf8_mf8_fpm(svmfloat8_t zn, svmfloat8x2_t zm, fpm_t fpmr) __arm_streaming __arm_inout("za") {
+    SME_ACLE_FUNC(svmop4a,_1x2,_za16,_mf8_mf8,_fpm)(1, zn, zm, fpmr);
+}
+
+// CHECK-LABEL: define dso_local void @test_svmop4a_2x1_za16_mf8_mf8_fpm(
+// CHECK-SAME: <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])
+// CHECK-NEXT:    tail call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x1.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZM]])
+// CHECK-NEXT:    ret void
+//
+// CPP-CHECK-LABEL: define dso_local void @_Z33test_svmop4a_2x1_za16_mf8_mf8_fpm13svmfloat8x2_tu13__SVMfloat8_tm(
+// CPP-CHECK-SAME: <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {
+// CPP-CHECK-NEXT:  [[ENTRY:.*:]]
+// CPP-CHECK-NEXT:    tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])
+// CPP-CHECK-NEXT:    tail call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x1.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZM]])
+// CPP-CHECK-NEXT:    ret void
+//
+void test_svmop4a_2x1_za16_mf8_mf8_fpm(svmfloat8x2_t zn, svmfloat8_t zm, fpm_t fpmr) __arm_streaming __arm_inout("za") {
+    SME_ACLE_FUNC(svmop4a,_2x1,_za16,_mf8_mf8,_fpm)(1, zn, zm, fpmr);
+}
+
+// CHECK-LABEL: define dso_local void @test_svmop4a_2x2_za16_mf8_mf8_fpm(
+// CHECK-SAME: <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM_COERCE0:%.*]], <vscale x 16 x i8> [[ZM_COERCE1:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])
+// CHECK-NEXT:    tail call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x2.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZM_COERCE0]], <vscale x 16 x i8> [[ZM_COERCE1]])
+// CHECK-NEXT:    ret void
+//
+// CPP-CHECK-LABEL: define dso_local void @_Z33test_svmop4a_2x2_za16_mf8_mf8_fpm13svmfloat8x2_tS_m(
+// CPP-CHECK-SAME: <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM_COERCE0:%.*]], <vscale x 16 x i8> [[ZM_COERCE1:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {
+// CPP-CHECK-NEXT:  [[ENTRY:.*:]]
+// CPP-CHECK-NEXT:    tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])
+// CPP-CHECK-NEXT:    tail call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x2.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZM_COERCE0]], <vscale x 16 x i8> [[ZM_COERCE1]])
+// CPP-CHECK-NEXT:    ret void
+//
+void test_svmop4a_2x2_za16_mf8_mf8_fpm(svmfloat8x2_t zn, svmfloat8x2_t zm, fpm_t fpmr) __arm_streaming __arm_inout("za") {
+    SME_ACLE_FUNC(svmop4a,_2x2,_za16,_mf8_mf8,_fpm)(1, zn, zm, fpmr);
+}
+
+// CHECK-LABEL: define dso_local void @test_svmop4a_1x1_za32_mf8_mf8_fpm(
+// CHECK-SAME: <vscale x 16 x i8> [[ZN:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])
+// CHECK-NEXT:    tail call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x1.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN]], <vscale x 16 x i8> [[ZM]])
+// CHECK-NEXT:    ret void
+//
+// CPP-CHECK-LABEL: define dso_local void @_Z33test_svmop4a_1x1_za32_mf8_mf8_fpmu13__SVMfloat8_tS_m(
+// CPP-CHECK-SAME: <vscale x 16 x i8> [[ZN:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {
+// CPP-CHECK-NEXT:  [[ENTRY:.*:]]
+// CPP-CHECK-NEXT:    tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])
+// CPP-CHECK-NEXT:    tail call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x1.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN]], <vscale x 16 x i8> [[ZM]])
+// CPP-CHECK-NEXT:    ret void
+//
+void test_svmop4a_1x1_za32_mf8_mf8_fpm(svmfloat8_t zn, svmfloat8_t zm, fpm_t fpmr) __arm_streaming __arm_inout("za") {
+    SME_ACLE_FUNC(svmop4a,_1x1,_za32,_mf8_mf8,_fpm)(1, zn, zm, fpmr);
+}
+
+// CHECK-LABEL: define dso_local void @test_svmop4a_1x2_za32_mf8_mf8_fpm(
+// CHECK-SAME: <vscale x 16 x i8> [[ZN:%.*]], <vscale x 16 x i8> [[ZM_COERCE0:%.*]], <vscale x 16 x i8> [[ZM_COERCE1:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])
+// CHECK-NEXT:    tail call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x2.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN]], <vscale x 16 x i8> [[ZM_COERCE0]], <vscale x 16 x i8> [[ZM_COERCE1]])
+// CHECK-NEXT:    ret void
+//
+// CPP-CHECK-LABEL: define dso_local void @_Z33test_svmop4a_1x2_za32_mf8_mf8_fpmu13__SVMfloat8_t13svmfloat8x2_tm(
+// CPP-CHECK-SAME: <vscale x 16 x i8> [[ZN:%.*]], <vscale x 16 x i8> [[ZM_COERCE0:%.*]], <vscale x 16 x i8> [[ZM_COERCE1:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {
+// CPP-CHECK-NEXT:  [[ENTRY:.*:]]
+// CPP-CHECK-NEXT:    tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])
+// CPP-CHECK-NEXT:    tail call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x2.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN]], <vscale x 16 x i8> [[ZM_COERCE0]], <vscale x 16 x i8> [[ZM_COERCE1]])
+// CPP-CHECK-NEXT:    ret void
+//
+void test_svmop4a_1x2_za32_mf8_mf8_fpm(svmfloat8_t zn, svmfloat8x2_t zm, fpm_t fpmr) __arm_streaming __arm_inout("za") {
+    SME_ACLE_FUNC(svmop4a,_1x2,_za32,_mf8_mf8,_fpm)(1, zn, zm, fpmr);
+}
+
+// CHECK-LABEL: define dso_local void @test_svmop4a_2x1_za32_mf8_mf8_fpm(
+// CHECK-SAME: <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])
+// CHECK-NEXT:    tail call void @llvm.aarch64.sme.fp8.fmop4a.za32.2x1.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZM]])
+// CHECK-NEXT:    ret void
+//
+// CPP-CHECK-LABEL: define dso_local void @_Z33test_svmop4a_2x1_za32_mf8_mf8_fpm13svmfloat8x2_tu13__SVMfloat8_tm(
+// CPP-CHECK-SAME: <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {
+// CPP-CHECK-NEXT:  [[ENTRY:.*:]]
+// CPP-CHECK-NEXT:    tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])
+// CPP-CHECK-NEXT:    tail call void @llvm.aarch64.sme.fp8.fmop4a.za32.2x1.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZM]])
+// CPP-CHECK-NEXT:    ret void
+//
+void test_svmop4a_2x1_za32_mf8_mf8_fpm(svmfloat8x2_t zn, svmfloat8_t zm, fpm_t fpmr) __arm_streaming __arm_inout("za") {
+    SME_ACLE_FUNC(svmop4a,_2x1,_za32,_mf8_mf8,_fpm)(1, zn, zm, fpmr);
+}
+
+// CHECK-LABEL: define dso_local void @test_svmop4a_2x2_za32_mf8_mf8_fpm(
+// CHECK-SAME: <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM_COERCE0:%.*]], <vscale x 16 x i8> [[ZM_COERCE1:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])
+// CHECK-NEXT:    tail call void @llvm.aarch64.sme.fp8.fmop4a.za32.2x2.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZM_COERCE0]], <vscale x 16 x i8> [[ZM_COERCE1]])
+// CHECK-NEXT:    ret void
+//
+// CPP-CHECK-LABEL: define dso_local void @_Z33test_svmop4a_2x2_za32_mf8_mf8_fpm13svmfloat8x2_tS_m(
+// CPP-CHECK-SAME: <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM_COERCE0:%.*]], <vscale x 16 x i8> [[ZM_COERCE1:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {
+// CPP-CHECK-NEXT:  [[ENTRY:.*:]]
+// CPP-CHECK-NEXT:    tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR]])
+// CPP-CHECK-NEXT:    tail call void @llvm.aarch64.sme.fp8.fmop4a.za32.2x2.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN_COERCE0]], <vscale x 16 x i8> [[ZN_COERCE1]], <vscale x 16 x i8> [[ZM_COERCE0]], <vscale x 16 x i8> [[ZM_COERCE1]])
+// CPP-CHECK-NEXT:    ret void
+//
+void test_svmop4a_2x2_za32_mf8_mf8_fpm(svmfloat8x2_t zn, svmfloat8x2_t zm, fpm_t fpmr) __arm_streaming __arm_inout("za") {
+    SME_ACLE_FUNC(svmop4a,_2x2,_za32,_mf8_mf8,_fpm)(1, zn, zm, fpmr);
+}
diff --git a/clang/test/CodeGen/avr/avr-inline-asm-constraints.c b/clang/test/CodeGen/avr/avr-inline-asm-constraints.c
index 3a956de8db48f..c8d83b4848312 100644
--- a/clang/test/CodeGen/avr/avr-inline-asm-constraints.c
+++ b/clang/test/CodeGen/avr/avr-inline-asm-constraints.c
@@ -71,6 +71,8 @@ void z() {
 void I() {
   // CHECK: call addrspace(0) void asm sideeffect "subi r30, $0", "I"(i16 50)
   asm("subi r30, %0" :: "I"(50));
+  // CHECK: call addrspace(0) void asm sideeffect "subi r30, $0", "I"(i16 64)
+  asm("subi r30, %0" :: "I"(64));
 }
 
 void J() {
diff --git a/clang/test/CodeGen/avr/avr-unsupported-inline-asm-constraints.c b/clang/test/CodeGen/avr/avr-unsupported-inline-asm-constraints.c
index 29f0b69285fa8..52b8d1cb044ca 100644
--- a/clang/test/CodeGen/avr/avr-unsupported-inline-asm-constraints.c
+++ b/clang/test/CodeGen/avr/avr-unsupported-inline-asm-constraints.c
@@ -6,4 +6,5 @@ int foo(void) {
   __asm__ volatile("foo %0, 1" : : "fo" (val)); // expected-error {{invalid input constraint 'fo' in asm}}
   __asm__ volatile("foo %0, 1" : : "Nd" (val)); // expected-error {{invalid input constraint 'Nd' in asm}}
   __asm__ volatile("subi r30, %0" : : "G" (1)); // expected-error {{value '1' out of range for constraint 'G'}}
+  __asm__ volatile("out %0, r20" : : "I" (65)); // expected-error {{value '65' out of range for constraint 'I'}}
 }
diff --git a/clang/test/CodeGenCUDA/lambda-constexpr-capture.cu b/clang/test/CodeGenCUDA/lambda-constexpr-capture.cu
new file mode 100644
index 0000000000000..1a1db63ceb717
--- /dev/null
+++ b/clang/test/CodeGenCUDA/lambda-constexpr-capture.cu
@@ -0,0 +1,135 @@
+// RUN: %clang_cc1 -emit-llvm -x hip %s -o - -triple x86_64-linux-gnu \
+// RUN:   | FileCheck -check-prefixes=CHECK,HOST %s
+// RUN: %clang_cc1 -emit-llvm -x hip %s -o - -triple amdgcn-amd-amdhsa -fcuda-is-device \
+// RUN:   | FileCheck -check-prefixes=CHECK,DEV %s
+
+#include "Inputs/cuda.h"
+
+// CHECK: %class.anon = type { ptr, float, ptr, ptr }
+// CHECK: %class.anon.0 = type { ptr, float, ptr, ptr }
+// CHECK: %class.anon.1 = type { ptr, ptr, ptr }
+// CHECK: %class.anon.2 = type { ptr, float, ptr, ptr }
+
+// HOST: call void @_ZN8DevByVal21__device_stub__kernelIZNS_4testEPKfS2_PfEUljE_EEvT_(ptr noundef byval(%class.anon)
+// DEV: define amdgpu_kernel void @_ZN8DevByVal6kernelIZNS_4testEPKfS2_PfEUljE_EEvT_(ptr addrspace(4) noundef byref(%class.anon)
+
+// Only the device function passes arugments by value.
+namespace DevByVal {
+__device__ float fun(float x, float y) {
+  return x;
+}
+
+float fun(const float &x, const float &y) {
+  return x;
+}
+
+template<typename F>
+void __global__ kernel(F f)
+{
+  f(1);
+}
+
+void test(float const * fl, float const * A, float * Vf)
+{
+  float constexpr small(1.0e-25);
+
+  auto lambda = [=] __device__ __host__ (unsigned int n) {
+    float const value = fun(small, fl[0]);
+    Vf[0] = value * A[0];
+  };
+  kernel<<<1, 1>>>(lambda);
+}
+}
+
+// HOST: call void @_ZN9HostByVal21__device_stub__kernelIZNS_4testEPKfS2_PfEUljE_EEvT_(ptr noundef byval(%class.anon.0)
+// DEV: define amdgpu_kernel void @_ZN9HostByVal6kernelIZNS_4testEPKfS2_PfEUljE_EEvT_(ptr addrspace(4) noundef byref(%class.anon.0)
+
+// Only the host function passes arugments by value.
+namespace HostByVal {
+float fun(float x, float y) {
+  return x;
+}
+
+__device__ float fun(const float &x, const float &y) {
+  return x;
+}
+
+template<typename F>
+void __global__ kernel(F f)
+{
+  f(1);
+}
+
+void test(float const * fl, float const * A, float * Vf)
+{
+  float constexpr small(1.0e-25);
+
+  auto lambda = [=] __device__ __host__ (unsigned int n) {
+    float const value = fun(small, fl[0]);
+    Vf[0] = value * A[0];
+  };
+  kernel<<<1, 1>>>(lambda);
+}
+}
+
+// HOST: call void @_ZN9BothByVal21__device_stub__kernelIZNS_4testEPKfS2_PfEUljE_EEvT_(ptr noundef byval(%class.anon.1)
+// DEV: define amdgpu_kernel void @_ZN9BothByVal6kernelIZNS_4testEPKfS2_PfEUljE_EEvT_(ptr addrspace(4) noundef byref(%class.anon.1)
+
+// Both the host and device functions pass arugments by value.
+namespace BothByVal {
+float fun(float x, float y) {
+  return x;
+}
+
+__device__ float fun(float x, float y) {
+  return x;
+}
+
+template<typename F>
+void __global__ kernel(F f)
+{
+  f(1);
+}
+
+void test(float const * fl, float const * A, float * Vf)
+{
+  float constexpr small(1.0e-25);
+
+  auto lambda = [=] __device__ __host__ (unsigned int n) {
+    float const value = fun(small, fl[0]);
+    Vf[0] = value * A[0];
+  };
+  kernel<<<1, 1>>>(lambda);
+}
+}
+
+// HOST: call void @_ZN12NeitherByVal21__device_stub__kernelIZNS_4testEPKfS2_PfEUljE_EEvT_(ptr noundef byval(%class.anon.2)
+// DEV: define amdgpu_kernel void @_ZN12NeitherByVal6kernelIZNS_4testEPKfS2_PfEUljE_EEvT_(ptr addrspace(4) noundef byref(%class.anon.2)
+
+// Neither the host nor device function passes arugments by value.
+namespace NeitherByVal {
+float fun(const float& x, const float& y) {
+  return x;
+}
+
+__device__ float fun(const float& x, const float& y) {
+  return x;
+}
+
+template<typename F>
+void __global__ kernel(F f)
+{
+  f(1);
+}
+
+void test(float const * fl, float const * A, float * Vf)
+{
+  float constexpr small(1.0e-25);
+
+  auto lambda = [=] __device__ __host__ (unsigned int n) {
+    float const value = fun(small, fl[0]);
+    Vf[0] = value * A[0];
+  };
+  kernel<<<1, 1>>>(lambda);
+}
+}
diff --git a/clang/test/CodeGenCUDASPIRV/printf.cu b/clang/test/CodeGenCUDASPIRV/printf.cu
new file mode 100644
index 0000000000000..936e920f4a755
--- /dev/null
+++ b/clang/test/CodeGenCUDASPIRV/printf.cu
@@ -0,0 +1,11 @@
+// RUN: %clang_cc1 -fcuda-is-device -triple spirv32 -o - -emit-llvm -x cuda %s  | FileCheck --check-prefix=CHECK-SPIRV32 %s
+// RUN: %clang_cc1 -fcuda-is-device -triple spirv64 -o - -emit-llvm -x cuda %s  | FileCheck --check-prefix=CHECK-SPIRV64 %s
+
+// CHECK-SPIRV32: @.str = private unnamed_addr addrspace(4) constant [13 x i8] c"Hello World\0A\00", align 1
+// CHECK-SPIRV64: @.str = private unnamed_addr addrspace(1) constant [13 x i8] c"Hello World\0A\00", align 1
+
+extern "C" __attribute__((device)) int printf(const char* format, ...);
+
+__attribute__((global)) void printf_kernel() {
+  printf("Hello World\n");
+}
diff --git a/clang/test/CodeGenCXX/debug-info-dtor-implicit-args.cpp b/clang/test/CodeGenCXX/debug-info-dtor-implicit-args.cpp
deleted file mode 100644
index 4bb51dcc4da51..0000000000000
--- a/clang/test/CodeGenCXX/debug-info-dtor-implicit-args.cpp
+++ /dev/null
@@ -1,24 +0,0 @@
-// RUN: %clang_cc1 -triple x86_64-none-linux-gnu -emit-llvm -debug-info-kind=limited %s -o - | FileCheck %s
-// RUN: %clang_cc1 -triple x86_64-pc-windows-msvc -emit-llvm -debug-info-kind=limited %s -o - | FileCheck --check-prefix MSVC %s
-
-struct B {
-    virtual ~B() {}
-};
-
-struct A : virtual B {
-};
-
-A a;
-
-
-// CHECK-DAG: !{{[0-9]+}} = !DILocalVariable(name: "vtt", arg: 2, scope: ![[destructor:[0-9]+]], type: ![[vtttype:[0-9]+]], flags: DIFlagArtificial)
-// CHECK-DAG: ![[destructor]] = distinct !DISubprogram(name: "~A", {{.*}}, type: ![[subroutinetype:[0-9]+]]
-// CHECK-DAG: ![[subroutinetype]] = !DISubroutineType(types: ![[types:[0-9]+]])
-// CHECK-DAG: [[types]] = !{null, !{{[0-9]+}}, ![[vtttype]]}
-
-// MSVC-DAG: ![[inttype:[0-9]+]] = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
-// MSVC-DAG: ![[voidpointertype:[0-9]+]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: null, size: 64)
-// MSVC-DAG: ![[destructor:[0-9]+]] = distinct !DISubprogram(name: "~A", linkageName: "??_GA@@UEAAPEAXI@Z", {{.*}}, type: ![[subroutinetype:[0-9]+]]
-// MSVC-DAG: !{{[0-9]+}} = !DILocalVariable(name: "should_call_delete", arg: 2, scope: ![[destructor]], type: ![[inttype]], flags: DIFlagArtificial)
-// MSVC-DAG: ![[subroutinetype]] = !DISubroutineType(types: ![[types:[0-9]+]])
-// MSVC-DAG: [[types]] = !{![[voidpointertype]], !{{[0-9]+}}, ![[inttype]]}
diff --git a/clang/test/CodeGenCXX/mangle-template.cpp b/clang/test/CodeGenCXX/mangle-template.cpp
index 867f00f379ead..2fca98faadb16 100644
--- a/clang/test/CodeGenCXX/mangle-template.cpp
+++ b/clang/test/CodeGenCXX/mangle-template.cpp
@@ -414,7 +414,7 @@ namespace unresolved_template_specialization_type {
         AbslHashValue() {}
   };
   template enable_if<true> raw_hash_set<int>::AbslHashValue<HashStateBase>();
-  // CHECH: @_ZN39unresolved_template_specialization_type12raw_hash_setIiE13AbslHashValueINS_13HashStateBaseEEENS_9enable_ifIXsrNT_11is_hashableIiEE5valueEEEv
+  // CHECK: @_ZN39unresolved_template_specialization_type12raw_hash_setIiE13AbslHashValueINS_13HashStateBaseEEENS_9enable_ifIXsrNT_11is_hashableIiEE5valueEEEv
 } // namespace unresolved_template_specialization_type
 
 namespace GH133610 {
diff --git a/clang/test/Driver/Xclangas.s b/clang/test/Driver/Xclangas.s
index 0d3911170eee1..fb6ae2ecbb189 100644
--- a/clang/test/Driver/Xclangas.s
+++ b/clang/test/Driver/Xclangas.s
@@ -2,3 +2,4 @@
 // RUN: %clang -### -Werror -Xclangas -target-feature -Xclangas=+v5t %s 2>&1 | FileCheck %s
 // CHECK: -cc1as
 // CHECK-SAME: "-target-feature" "+v5t"
+// XFAIL: target={{.*}}-aix{{.*}}
diff --git a/clang/test/Driver/cxa-atexit.cpp b/clang/test/Driver/cxa-atexit.cpp
index 537a11a35f51b..8bfb938e8e8e7 100644
--- a/clang/test/Driver/cxa-atexit.cpp
+++ b/clang/test/Driver/cxa-atexit.cpp
@@ -1,15 +1,15 @@
 // RUN: %clang -### -target armv7-unknown-windows-msvc -c %s -o /dev/null 2>&1 | FileCheck %s -check-prefix CHECK-WINDOWS
 // RUN: %clang -### -target armv7-unknown-windows-itanium -c %s -o /dev/null 2>&1 | FileCheck %s -check-prefix CHECK-WINDOWS
 // RUN: %clang -### -target armv7-unknown-windows-gnu -c %s -o /dev/null 2>&1 | FileCheck %s -check-prefix CHECK-WINDOWS
-// RUN: %clang -### -target armv7-unknown-windows-cygnus -c %s -o /dev/null 2>&1 | FileCheck %s -check-prefix CHECK-WINDOWS
+// RUN: %clang -### -target armv7-unknown-windows-cygnus -c %s -o /dev/null 2>&1 | FileCheck %s -check-prefix CHECK-CYGWIN
 // RUN: %clang -### -target i686-unknown-windows-msvc -c %s -o /dev/null 2>&1 | FileCheck %s -check-prefix CHECK-WINDOWS
 // RUN: %clang -### -target i686-unknown-windows-itanium -c %s -o /dev/null 2>&1 | FileCheck %s -check-prefix CHECK-WINDOWS
 // RUN: %clang -### -target i686-unknown-windows-gnu -c %s -o /dev/null 2>&1 | FileCheck %s -check-prefix CHECK-WINDOWS
-// RUN: %clang -### -target i686-unknown-windows-cygnus -c %s -o /dev/null 2>&1 | FileCheck %s -check-prefix CHECK-WINDOWS
+// RUN: %clang -### -target i686-unknown-windows-cygnus -c %s -o /dev/null 2>&1 | FileCheck %s -check-prefix CHECK-CYGWIN
 // RUN: %clang -### -target x86_64-unknown-windows-msvc -c %s -o /dev/null 2>&1 | FileCheck %s -check-prefix CHECK-WINDOWS
 // RUN: %clang -### -target x86_64-unknown-windows-itanium -c %s -o /dev/null 2>&1 | FileCheck %s -check-prefix CHECK-WINDOWS
 // RUN: %clang -### -target x86_64-unknown-windows-gnu -c %s -o /dev/null 2>&1 | FileCheck %s -check-prefix CHECK-WINDOWS
-// RUN: %clang -### -target x86_64-unknown-windows-cygnus -c %s -o /dev/null 2>&1 | FileCheck %s -check-prefix CHECK-WINDOWS
+// RUN: %clang -### -target x86_64-unknown-windows-cygnus -c %s -o /dev/null 2>&1 | FileCheck %s -check-prefix CHECK-CYGWIN
 // RUN: %clang -### -target hexagon-unknown-none -c %s -o /dev/null 2>&1 | FileCheck %s -check-prefix CHECK-HEXAGON
 // RUN: %clang -### -target xcore-unknown-none -c %s -o /dev/null 2>&1 | FileCheck %s -check-prefix CHECK-XCORE
 // RUN: %clang -### -target armv7-mti-none -c %s -o /dev/null 2>&1 | FileCheck %s -check-prefix CHECK-MTI
@@ -21,6 +21,7 @@
 // RUN: %clang -### -target powerpc64-ibm-aix-xcoff -c %s -o /dev/null 2>&1 | FileCheck %s -check-prefix CHECK-AIX
 
 // CHECK-WINDOWS: "-fno-use-cxa-atexit"
+// CHECK-CYGWIN-NOT: "-fno-use-cxa-atexit"
 // CHECK-SOLARIS-NOT: "-fno-use-cxa-atexit"
 // CHECK-HEXAGON-NOT: "-fno-use-cxa-atexit"
 // CHECK-XCORE: "-fno-use-cxa-atexit"
diff --git a/clang/test/Driver/fsanitize.c b/clang/test/Driver/fsanitize.c
index c154e339941f2..af00492314ff7 100644
--- a/clang/test/Driver/fsanitize.c
+++ b/clang/test/Driver/fsanitize.c
@@ -951,8 +951,29 @@
 // CHECK-CFI-MINIMAL: "-fsanitize-trap=cfi-derived-cast,cfi-icall,cfi-mfcall,cfi-unrelated-cast,cfi-nvcall,cfi-vcall"
 // CHECK-CFI-MINIMAL: "-fsanitize-minimal-runtime"
 
+// RUN: %clang --target=x86_64-linux-gnu -fsanitize=cfi -flto -fvisibility=hidden -fsanitize-minimal-runtime -fsanitize-recover=cfi -resource-dir=%S/Inputs/resource_dir %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-CFI-RECOVER-MINIMAL
+// CHECK-CFI-RECOVER-MINIMAL: "-fsanitize=cfi-derived-cast,cfi-icall,cfi-mfcall,cfi-unrelated-cast,cfi-nvcall,cfi-vcall"
+// CHECK-CFI-RECOVER-MINIMAL: "-fsanitize-trap=cfi-derived-cast,cfi-icall,cfi-mfcall,cfi-unrelated-cast,cfi-nvcall,cfi-vcall"
+// CHECK-CFI-RECOVER-MINIMAL: "-fsanitize-minimal-runtime"
+
+// RUN: %clang --target=x86_64-linux-gnu -fsanitize=cfi -flto -fvisibility=hidden -fsanitize-minimal-runtime -fno-sanitize-recover=cfi -resource-dir=%S/Inputs/resource_dir %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-CFI-ABORT-MINIMAL
+// CHECK-CFI-ABORT-MINIMAL: "-fsanitize=cfi-derived-cast,cfi-icall,cfi-mfcall,cfi-unrelated-cast,cfi-nvcall,cfi-vcall"
+// CHECK-CFI-ABORT-MINIMAL: "-fsanitize-trap=cfi-derived-cast,cfi-icall,cfi-mfcall,cfi-unrelated-cast,cfi-nvcall,cfi-vcall"
+// CHECK-CFI-ABORT-MINIMAL: "-fsanitize-minimal-runtime"
+
+// RUN: not %clang --target=x86_64-linux-gnu -fsanitize=cfi -flto -fvisibility=hidden -fsanitize-minimal-runtime -fno-sanitize-trap=cfi -fsanitize-recover=cfi -resource-dir=%S/Inputs/resource_dir %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-CFI-NOTRAP-RECOVER-MINIMAL --
+// CHECK-CFI-NOTRAP-RECOVER-MINIMAL: '-fsanitize-minimal-runtime' only allowed with '-fsanitize-trap=cfi'
+// CHECK-CFI-NOTRAP-RECOVER-MINIMAL: "-fsanitize=cfi-derived-cast,cfi-icall,cfi-mfcall,cfi-unrelated-cast,cfi-nvcall,cfi-vcall"
+// CHECK-CFI-NOTRAP-RECOVER-MINIMAL: "-fsanitize-recover=cfi-derived-cast,cfi-icall,cfi-mfcall,cfi-unrelated-cast,cfi-nvcall,cfi-vcall"
+// CHECK-CFI-NOTRAP-RECOVER-MINIMAL: "-fsanitize-minimal-runtime"
+
+// RUN: not %clang --target=x86_64-linux-gnu -fsanitize=cfi -flto -fvisibility=hidden -fsanitize-minimal-runtime -fno-sanitize-trap=cfi -fno-sanitize-recover=cfi -resource-dir=%S/Inputs/resource_dir %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-CFI-NOTRAP-ABORT-MINIMAL
+// CHECK-CFI-NOTRAP-ABORT-MINIMAL: '-fsanitize-minimal-runtime' only allowed with '-fsanitize-trap=cfi'
+// CHECK-CFI-NOTRAP-ABORT-MINIMAL: "-fsanitize=cfi-derived-cast,cfi-icall,cfi-mfcall,cfi-unrelated-cast,cfi-nvcall,cfi-vcall"
+// CHECK-CFI-NOTRAP-ABORT-MINIMAL: "-fsanitize-minimal-runtime"
+
 // RUN: not %clang --target=x86_64-linux-gnu -fsanitize=cfi -fno-sanitize-trap=cfi-icall -flto -fvisibility=hidden -fsanitize-minimal-runtime %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-CFI-NOTRAP-MINIMAL
-// CHECK-CFI-NOTRAP-MINIMAL: error: invalid argument 'fsanitize-minimal-runtime' only allowed with 'fsanitize-trap=cfi'
+// CHECK-CFI-NOTRAP-MINIMAL: error: invalid argument '-fsanitize-minimal-runtime' only allowed with '-fsanitize-trap=cfi'
 
 // RUN: %clang --target=x86_64-linux-gnu -fsanitize=cfi -fno-sanitize-trap=cfi-icall -fno-sanitize=cfi-icall -flto -fvisibility=hidden -fsanitize-minimal-runtime -resource-dir=%S/Inputs/resource_dir %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-CFI-NOICALL-MINIMAL
 // CHECK-CFI-NOICALL-MINIMAL: "-fsanitize=cfi-derived-cast,cfi-mfcall,cfi-unrelated-cast,cfi-nvcall,cfi-vcall"
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index c2314efd34aa6..bb3a9d38be673 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -692,3 +692,71 @@
 
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr7 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR7 %s
 // MTUNE-SYNTACORE-SCR7: "-tune-cpu" "syntacore-scr7"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-n45 | FileCheck -check-prefix=MCPU-ANDES-N45 %s
+// MCPU-ANDES-N45: "-target-cpu" "andes-n45"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+m"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+a"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+f"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+d"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+c"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+zicsr"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+zifencei"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+zba"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+zbb"
+// MCPU-ANDES-N45-SAME: "-target-feature" "+zbs"
+// MCPU-ANDES-N45-SAME: "-target-abi" "ilp32d"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=andes-n45 | FileCheck -check-prefix=MTUNE-ANDES-N45 %s
+// MTUNE-ANDES-N45: "-tune-cpu" "andes-n45"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=andes-nx45 | FileCheck -check-prefix=MCPU-ANDES-NX45 %s
+// MCPU-ANDES-NX45: "-target-cpu" "andes-nx45"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+m"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+a"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+f"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+d"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+c"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+zicsr"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+zifencei"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+zba"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+zbb"
+// MCPU-ANDES-NX45-SAME: "-target-feature" "+zbs"
+// MCPU-ANDES-NX45-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=andes-nx45 | FileCheck -check-prefix=MTUNE-ANDES-NX45 %s
+// MTUNE-ANDES-NX45: "-tune-cpu" "andes-nx45"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-a45 | FileCheck -check-prefix=MCPU-ANDES-A45 %s
+// MCPU-ANDES-A45: "-target-cpu" "andes-a45"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+m"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+a"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+f"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+d"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+c"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+zicsr"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+zifencei"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+zba"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+zbb"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+zbs"
+// MCPU-ANDES-A45-SAME: "-target-abi" "ilp32d"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=andes-a45 | FileCheck -check-prefix=MTUNE-ANDES-A45 %s
+// MTUNE-ANDES-A45: "-tune-cpu" "andes-a45"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=andes-ax45 | FileCheck -check-prefix=MCPU-ANDES-AX45 %s
+// MCPU-ANDES-AX45: "-target-cpu" "andes-ax45"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+m"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+a"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+f"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+d"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+c"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+zicsr"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+zifencei"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+zba"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+zbb"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+zbs"
+// MCPU-ANDES-AX45-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=andes-ax45 | FileCheck -check-prefix=MTUNE-ANDES-AX45 %s
+// MTUNE-ANDES-AX45: "-tune-cpu" "andes-ax45"
diff --git a/clang/test/Driver/sanitizer-ld.c b/clang/test/Driver/sanitizer-ld.c
index 4239c52a5fdcc..a5a4fc2320bd2 100644
--- a/clang/test/Driver/sanitizer-ld.c
+++ b/clang/test/Driver/sanitizer-ld.c
@@ -908,6 +908,84 @@
 // CHECK-CFI-CROSS-DSO-DIAG-ANDROID: "{{[^"]*}}libclang_rt.ubsan_standalone.so"
 // CHECK-CFI-CROSS-DSO-DIAG-ANDROID: "--export-dynamic-symbol=__cfi_check"
 
+// CFI by itself does not link runtime libraries.
+// RUN: %clang -fsanitize=cfi \
+// RUN:     -flto -fvisibility=hidden \
+// RUN:     -fsanitize-minimal-runtime \
+// RUN:     --target=x86_64-unknown-linux -fuse-ld=ld \
+// RUN:     -resource-dir=%S/Inputs/resource_dir \
+// RUN:     --sysroot=%S/Inputs/basic_linux_tree \
+// RUN:     -### %s 2>&1 \
+// RUN:   | %{filecheck} --check-prefix=CHECK-CFI-MINRT-LINUX
+// CHECK-CFI-MINRT-LINUX: "{{.*}}ld{{(.exe)?}}"
+
+// CFI with diagnostics links the UBSan runtime.
+// RUN: not %clang -fsanitize=cfi -fno-sanitize-trap=cfi -fsanitize-recover=cfi \
+// RUN:     -flto -fvisibility=hidden \
+// RUN:     -fsanitize-minimal-runtime \
+// RUN:     --target=x86_64-unknown-linux -fuse-ld=ld \
+// RUN:     -resource-dir=%S/Inputs/resource_dir \
+// RUN:     --sysroot=%S/Inputs/basic_linux_tree \
+// RUN:     -### %s 2>&1 \
+// RUN:   | %{filecheck} --check-prefix=CHECK-CFI-MINRT-DIAG-LINUX
+// CHECK-CFI-MINRT-DIAG-LINUX: '-fsanitize-minimal-runtime' only allowed with '-fsanitize-trap=cfi'
+// CHECK-CFI-MINRT-DIAG-LINUX: "{{.*}}ld{{(.exe)?}}"
+// CHECK-CFI-MINRT-DIAG-LINUX: "--whole-archive" "{{[^"]*}}libclang_rt.ubsan_minimal.a" "--no-whole-archive"
+
+// Cross-DSO CFI links the CFI runtime.
+// RUN: %clang -fsanitize=cfi -fsanitize-cfi-cross-dso \
+// RUN:     -flto -fvisibility=hidden \
+// RUN:     -fsanitize-minimal-runtime \
+// RUN:     --target=x86_64-unknown-linux -fuse-ld=ld \
+// RUN:     -resource-dir=%S/Inputs/resource_dir \
+// RUN:     --sysroot=%S/Inputs/basic_linux_tree \
+// RUN:     -### %s 2>&1 \
+// RUN:   | %{filecheck} --check-prefix=CHECK-CFI-MINRT-CROSS-DSO-LINUX
+// CHECK-CFI-MINRT-CROSS-DSO-LINUX: "{{.*}}ld{{(.exe)?}}"
+// CHECK-CFI-MINRT-CROSS-DSO-LINUX: "--whole-archive" "{{[^"]*}}libclang_rt.cfi.a" "--no-whole-archive"
+// CHECK-CFI-MINRT-CROSS-DSO-LINUX: -export-dynamic
+
+// Cross-DSO CFI with diagnostics links just the CFI runtime.
+// RUN: not %clang -fsanitize=cfi -fsanitize-cfi-cross-dso \
+// RUN:     -flto -fvisibility=hidden \
+// RUN:     -fsanitize-minimal-runtime \
+// RUN:     -fno-sanitize-trap=cfi -fsanitize-recover=cfi \
+// RUN:     --target=x86_64-unknown-linux -fuse-ld=ld \
+// RUN:     -resource-dir=%S/Inputs/resource_dir \
+// RUN:     --sysroot=%S/Inputs/basic_linux_tree \
+// RUN:     -### %s 2>&1 \
+// RUN:   | %{filecheck} --check-prefix=CHECK-CFI-MINRT-CROSS-DSO-DIAG-LINUX
+// CHECK-CFI-MINRT-CROSS-DSO-DIAG-LINUX: '-fsanitize-minimal-runtime' only allowed with '-fsanitize-trap=cfi'
+// CHECK-CFI-MINRT-CROSS-DSO-DIAG-LINUX: "{{.*}}ld{{(.exe)?}}"
+// CHECK-CFI-MINRT-CROSS-DSO-DIAG-LINUX: "--whole-archive" "{{[^"]*}}libclang_rt.cfi_diag.a" "--no-whole-archive"
+// CHECK-CFI-MINRT-CROSS-DSO-DIAG-LINUX: -export-dynamic
+
+// Cross-DSO CFI on Android does not link runtime libraries.
+// RUN: %clang -fsanitize=cfi -fsanitize-cfi-cross-dso \
+// RUN:     -flto -fvisibility=hidden \
+// RUN:     -fsanitize-minimal-runtime \
+// RUN:     --target=aarch64-linux-android -fuse-ld=ld \
+// RUN:     -resource-dir=%S/Inputs/resource_dir \
+// RUN:     --sysroot=%S/Inputs/basic_android_tree \
+// RUN:     -### %s 2>&1 \
+// RUN:   | %{filecheck} --check-prefix=CHECK-CFI-MINRT-CROSS-DSO-ANDROID
+// CHECK-CFI-MINRT-CROSS-DSO-ANDROID: "{{.*}}ld{{(.exe)?}}"
+
+// Cross-DSO CFI with diagnostics on Android links just the UBSAN runtime.
+// RUN: not %clang -fsanitize=cfi -fsanitize-cfi-cross-dso \
+// RUN:     -flto -fvisibility=hidden \
+// RUN:     -fsanitize-minimal-runtime \
+// RUN:     -fno-sanitize-trap=cfi -fsanitize-recover=cfi \
+// RUN:     --target=aarch64-linux-android -fuse-ld=ld \
+// RUN:     -resource-dir=%S/Inputs/resource_dir \
+// RUN:     --sysroot=%S/Inputs/basic_android_tree \
+// RUN:     -### %s 2>&1 \
+// RUN:   | %{filecheck} --check-prefix=CHECK-CFI-MINRT-CROSS-DSO-DIAG-ANDROID
+// CHECK-CFI-MINRT-CROSS-DSO-DIAG-ANDROID: '-fsanitize-minimal-runtime' only allowed with '-fsanitize-trap=cfi'
+// CHECK-CFI-MINRT-CROSS-DSO-DIAG-ANDROID: "{{.*}}ld{{(.exe)?}}"
+// CHECK-CFI-MINRT-CROSS-DSO-DIAG-ANDROID: "{{[^"]*}}libclang_rt.ubsan_minimal.so"
+// CHECK-CFI-MINRT-CROSS-DSO-DIAG-ANDROID: "--export-dynamic-symbol=__cfi_check"
+
 // RUN: %clangxx -fsanitize=address -### %s 2>&1 \
 // RUN:     -mmacos-version-min=10.6 \
 // RUN:     --target=x86_64-apple-darwin13.4.0 -fuse-ld=ld -stdlib=platform \
diff --git a/clang/test/Format/lit.local.cfg b/clang/test/Format/lit.local.cfg
index 20e217664997b..faa4b7f20fbcc 100644
--- a/clang/test/Format/lit.local.cfg
+++ b/clang/test/Format/lit.local.cfg
@@ -21,7 +21,7 @@ config.suffixes = [
     ".textpb",
     ".asciipb",
     ".td",
-    ".test"
+    ".test",
 ]
 
 # AIX 'diff' command doesn't support --strip-trailing-cr, but the internal
@@ -31,5 +31,5 @@ if platform.system() == "AIX":
 
 # Create an empty .clang-format-ignore file so that tests don't get messed
 # up if one exists higher in the tree
-with open(".clang-format-ignore", 'w'):
+with open(".clang-format-ignore", "w"):
     pass
diff --git a/clang/test/Headers/__clang_hip_cmath.hip b/clang/test/Headers/__clang_hip_cmath.hip
index 7d812fd0265a6..fcd74996e5fa4 100644
--- a/clang/test/Headers/__clang_hip_cmath.hip
+++ b/clang/test/Headers/__clang_hip_cmath.hip
@@ -6,7 +6,7 @@
 // RUN:   -internal-isystem %S/Inputs/include \
 // RUN:   -triple amdgcn-amd-amdhsa -aux-triple x86_64-unknown-unknown \
 // RUN:   -target-cpu gfx906 -emit-llvm %s -fcuda-is-device -O1 -o - \
-// RUN:   -D__HIPCC_RTC__ | FileCheck -check-prefix=DEFAULT %s
+// RUN:   -D__HIPCC_RTC__ | FileCheck -check-prefixes=DEFAULT,CORRECT-DIV-SQRT %s
 
 // Check that we end up with fast math flags set on intrinsic calls
 // RUN: %clang_cc1 -include __clang_hip_runtime_wrapper.h \
@@ -17,6 +17,15 @@
 // RUN:   -menable-no-nans -o - \
 // RUN:   -D__HIPCC_RTC__ | FileCheck -check-prefix=FINITEONLY %s
 
+// Check that we end up with fpmath metadata set on sqrt calls
+// RUN: %clang_cc1 -include __clang_hip_runtime_wrapper.h \
+// RUN:   -internal-isystem %S/../../lib/Headers/cuda_wrappers \
+// RUN:   -internal-isystem %S/Inputs/include \
+// RUN:   -triple amdgcn-amd-amdhsa -aux-triple x86_64-unknown-unknown \
+// RUN:   -target-cpu gfx906 -emit-llvm %s -fcuda-is-device -O1 \
+// RUN:   -fno-hip-fp32-correctly-rounded-divide-sqrt -o - \
+// RUN:   -D__HIPCC_RTC__ | FileCheck -check-prefixes=DEFAULT,NO-CORRECT-DIV-SQRT %s
+
 // DEFAULT-LABEL: @test_fma_f16(
 // DEFAULT-NEXT:  entry:
 // DEFAULT-NEXT:    [[TMP0:%.*]] = tail call contract noundef half @llvm.fma.f16(half [[X:%.*]], half [[Y:%.*]], half [[Z:%.*]])
@@ -142,3 +151,36 @@ namespace user_namespace {
     fma(a, b, b);
   }
 }
+
+// CORRECT-DIV-SQRT-LABEL: @test_sqrt_f32(
+// CORRECT-DIV-SQRT-NEXT:  entry:
+// CORRECT-DIV-SQRT-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.sqrt.f32(float [[X:%.*]])
+// CORRECT-DIV-SQRT-NEXT:    ret float [[TMP0]]
+//
+// FINITEONLY-LABEL: @test_sqrt_f32(
+// FINITEONLY-NEXT:  entry:
+// FINITEONLY-NEXT:    [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.sqrt.f32(float nofpclass(nan inf) [[X:%.*]])
+// FINITEONLY-NEXT:    ret float [[TMP0]]
+//
+// NO-CORRECT-DIV-SQRT-LABEL: @test_sqrt_f32(
+// NO-CORRECT-DIV-SQRT-NEXT:  entry:
+// NO-CORRECT-DIV-SQRT-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.sqrt.f32(float [[X:%.*]]), !fpmath [[META4:![0-9]+]]
+// NO-CORRECT-DIV-SQRT-NEXT:    ret float [[TMP0]]
+//
+extern "C" __device__ float test_sqrt_f32(float x) {
+  return sqrt(x);
+}
+
+// DEFAULT-LABEL: @test_sqrt_f64(
+// DEFAULT-NEXT:  entry:
+// DEFAULT-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.sqrt.f64(double [[X:%.*]])
+// DEFAULT-NEXT:    ret double [[TMP0]]
+//
+// FINITEONLY-LABEL: @test_sqrt_f64(
+// FINITEONLY-NEXT:  entry:
+// FINITEONLY-NEXT:    [[TMP0:%.*]] = tail call nnan ninf contract noundef double @llvm.sqrt.f64(double nofpclass(nan inf) [[X:%.*]])
+// FINITEONLY-NEXT:    ret double [[TMP0]]
+//
+extern "C" __device__ double test_sqrt_f64(double x) {
+  return sqrt(x);
+}
diff --git a/clang/test/Headers/__clang_hip_math.hip b/clang/test/Headers/__clang_hip_math.hip
index df1cd716342a5..11c9cd301abb7 100644
--- a/clang/test/Headers/__clang_hip_math.hip
+++ b/clang/test/Headers/__clang_hip_math.hip
@@ -27,6 +27,15 @@
 // RUN:   -target-cpu gfx906 -emit-llvm %s -fcuda-is-device -O1 -fgpu-approx-transcendentals -o - \
 // RUN:   -D__HIPCC_RTC__ | FileCheck -check-prefixes=CHECK,APPROX %s
 
+// Check that we end up with fpmath metadata set on sqrt calls
+// RUN: %clang_cc1 -include __clang_hip_runtime_wrapper.h \
+// RUN:   -internal-isystem %S/../../lib/Headers/cuda_wrappers \
+// RUN:   -internal-isystem %S/Inputs/include \
+// RUN:   -triple amdgcn-amd-amdhsa -aux-triple x86_64-unknown-unknown \
+// RUN:   -target-cpu gfx906 -emit-llvm %s -fcuda-is-device -O1 -fno-hip-fp32-correctly-rounded-divide-sqrt -o - \
+// RUN:   -D__HIPCC_RTC__ | FileCheck -check-prefixes=CHECK,NCRDIV %s
+
+
 // Check that we use the AMDGCNSPIRV address space map
 // RUN: %clang_cc1 -include __clang_hip_runtime_wrapper.h \
 // RUN:   -internal-isystem %S/../../lib/Headers/cuda_wrappers \
@@ -465,6 +474,11 @@ extern "C" __device__ long long test_llabs(long x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_acos_f32(float noundef [[X:%.*]]) #[[ATTR12:[0-9]+]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_acosf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_acos_f32(float noundef [[X:%.*]]) #[[ATTR12:[0-9]+]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_acosf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_acos_f32(float noundef [[X:%.*]]) #[[ATTR12:[0-9]+]]
@@ -489,6 +503,11 @@ extern "C" __device__ float test_acosf(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_acos_f64(double noundef [[X:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_acos(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_acos_f64(double noundef [[X:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_acos(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_acos_f64(double noundef [[X:%.*]]) #[[ATTR12]]
@@ -513,6 +532,11 @@ extern "C" __device__ double test_acos(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_acosh_f32(float noundef [[X:%.*]]) #[[ATTR13:[0-9]+]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_acoshf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_acosh_f32(float noundef [[X:%.*]]) #[[ATTR13:[0-9]+]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_acoshf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_acosh_f32(float noundef [[X:%.*]]) #[[ATTR13:[0-9]+]]
@@ -537,6 +561,11 @@ extern "C" __device__ float test_acoshf(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_acosh_f64(double noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_acosh(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_acosh_f64(double noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_acosh(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_acosh_f64(double noundef [[X:%.*]]) #[[ATTR13]]
@@ -561,6 +590,11 @@ extern "C" __device__ double test_acosh(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_asin_f32(float noundef [[X:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_asinf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_asin_f32(float noundef [[X:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_asinf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_asin_f32(float noundef [[X:%.*]]) #[[ATTR12]]
@@ -585,6 +619,11 @@ extern "C" __device__ float test_asinf(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_asin_f64(double noundef [[X:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_asin(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_asin_f64(double noundef [[X:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_asin(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_asin_f64(double noundef [[X:%.*]]) #[[ATTR12]]
@@ -610,6 +649,11 @@ extern "C" __device__ double test_asin(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_asinh_f32(float noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_asinhf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_asinh_f32(float noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_asinhf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_asinh_f32(float noundef [[X:%.*]]) #[[ATTR13]]
@@ -634,6 +678,11 @@ extern "C" __device__ float test_asinhf(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_asinh_f64(double noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_asinh(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_asinh_f64(double noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_asinh(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_asinh_f64(double noundef [[X:%.*]]) #[[ATTR13]]
@@ -658,6 +707,11 @@ extern "C" __device__ double test_asinh(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_atan2_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_atan2f(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_atan2_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_atan2f(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_atan2_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR12]]
@@ -682,6 +736,11 @@ extern "C" __device__ float test_atan2f(float x, float y) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_atan2_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_atan2(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_atan2_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_atan2(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_atan2_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]]) #[[ATTR12]]
@@ -706,6 +765,11 @@ extern "C" __device__ double test_atan2(double x, double y) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_atan_f32(float noundef [[X:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_atanf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_atan_f32(float noundef [[X:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_atanf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_atan_f32(float noundef [[X:%.*]]) #[[ATTR12]]
@@ -730,6 +794,11 @@ extern "C" __device__ float test_atanf(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_atan_f64(double noundef [[X:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_atan(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_atan_f64(double noundef [[X:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_atan(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_atan_f64(double noundef [[X:%.*]]) #[[ATTR12]]
@@ -754,6 +823,11 @@ extern "C" __device__ double test_atan(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_atanh_f32(float noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_atanhf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_atanh_f32(float noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_atanhf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_atanh_f32(float noundef [[X:%.*]]) #[[ATTR13]]
@@ -778,6 +852,11 @@ extern "C" __device__ float test_atanhf(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_atanh_f64(double noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_atanh(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_atanh_f64(double noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_atanh(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_atanh_f64(double noundef [[X:%.*]]) #[[ATTR13]]
@@ -802,6 +881,11 @@ extern "C" __device__ double test_atanh(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_cbrt_f32(float noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_cbrtf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_cbrt_f32(float noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_cbrtf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_cbrt_f32(float noundef [[X:%.*]]) #[[ATTR13]]
@@ -826,6 +910,11 @@ extern "C" __device__ float test_cbrtf(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_cbrt_f64(double noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_cbrt(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_cbrt_f64(double noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_cbrt(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_cbrt_f64(double noundef [[X:%.*]]) #[[ATTR13]]
@@ -850,6 +939,11 @@ extern "C" __device__ double test_cbrt(double x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.ceil.f32(float [[X:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test_ceilf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.ceil.f32(float [[X:%.*]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_ceilf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.ceil.f32(float [[X:%.*]])
@@ -874,6 +968,11 @@ extern "C" __device__ float test_ceilf(float x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.ceil.f64(double [[X:%.*]])
 // APPROX-NEXT:    ret double [[TMP0]]
 //
+// NCRDIV-LABEL: @test_ceil(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.ceil.f64(double [[X:%.*]])
+// NCRDIV-NEXT:    ret double [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_ceil(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) double @llvm.ceil.f64(double [[X:%.*]])
@@ -898,6 +997,11 @@ extern "C" __device__ double test_ceil(double x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.copysign.f32(float [[X:%.*]], float [[Y:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test_copysignf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.copysign.f32(float [[X:%.*]], float [[Y:%.*]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_copysignf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.copysign.f32(float [[X:%.*]], float [[Y:%.*]])
@@ -922,6 +1026,11 @@ extern "C" __device__ float test_copysignf(float x, float y) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.copysign.f64(double [[X:%.*]], double [[Y:%.*]])
 // APPROX-NEXT:    ret double [[TMP0]]
 //
+// NCRDIV-LABEL: @test_copysign(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.copysign.f64(double [[X:%.*]], double [[Y:%.*]])
+// NCRDIV-NEXT:    ret double [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_copysign(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) double @llvm.copysign.f64(double [[X:%.*]], double [[Y:%.*]])
@@ -946,6 +1055,11 @@ extern "C" __device__ double test_copysign(double x, double y) {
 // APPROX-NEXT:    [[CALL_I1:%.*]] = tail call contract noundef float @__ocml_native_cos_f32(float noundef [[X:%.*]]) #[[ATTR14:[0-9]+]]
 // APPROX-NEXT:    ret float [[CALL_I1]]
 //
+// NCRDIV-LABEL: @test_cosf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_cos_f32(float noundef [[X:%.*]]) #[[ATTR14:[0-9]+]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_cosf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_cos_f32(float noundef [[X:%.*]]) #[[ATTR14:[0-9]+]]
@@ -970,6 +1084,11 @@ extern "C" __device__ float test_cosf(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_cos_f64(double noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_cos(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_cos_f64(double noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_cos(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_cos_f64(double noundef [[X:%.*]]) #[[ATTR14]]
@@ -994,6 +1113,11 @@ extern "C" __device__ double test_cos(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_cosh_f32(float noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_coshf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_cosh_f32(float noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_coshf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_cosh_f32(float noundef [[X:%.*]]) #[[ATTR13]]
@@ -1018,6 +1142,11 @@ extern "C" __device__ float test_coshf(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_cosh_f64(double noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_cosh(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_cosh_f64(double noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_cosh(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_cosh_f64(double noundef [[X:%.*]]) #[[ATTR13]]
@@ -1042,6 +1171,11 @@ extern "C" __device__ double test_cosh(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_cospi_f32(float noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_cospif(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_cospi_f32(float noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_cospif(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_cospi_f32(float noundef [[X:%.*]]) #[[ATTR14]]
@@ -1066,6 +1200,11 @@ extern "C" __device__ float test_cospif(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_cospi_f64(double noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_cospi(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_cospi_f64(double noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_cospi(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_cospi_f64(double noundef [[X:%.*]]) #[[ATTR14]]
@@ -1090,6 +1229,11 @@ extern "C" __device__ double test_cospi(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_i0_f32(float noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_cyl_bessel_i0f(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_i0_f32(float noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_cyl_bessel_i0f(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_i0_f32(float noundef [[X:%.*]]) #[[ATTR14]]
@@ -1114,6 +1258,11 @@ extern "C" __device__ float test_cyl_bessel_i0f(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_i0_f64(double noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_cyl_bessel_i0(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_i0_f64(double noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_cyl_bessel_i0(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_i0_f64(double noundef [[X:%.*]]) #[[ATTR14]]
@@ -1138,6 +1287,11 @@ extern "C" __device__ double test_cyl_bessel_i0(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_i1_f32(float noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_cyl_bessel_i1f(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_i1_f32(float noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_cyl_bessel_i1f(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_i1_f32(float noundef [[X:%.*]]) #[[ATTR14]]
@@ -1162,6 +1316,11 @@ extern "C" __device__ float test_cyl_bessel_i1f(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_i1_f64(double noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_cyl_bessel_i1(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_i1_f64(double noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_cyl_bessel_i1(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_i1_f64(double noundef [[X:%.*]]) #[[ATTR14]]
@@ -1186,6 +1345,11 @@ extern "C" __device__ double test_cyl_bessel_i1(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_erfc_f32(float noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_erfcf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_erfc_f32(float noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_erfcf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_erfc_f32(float noundef [[X:%.*]]) #[[ATTR13]]
@@ -1210,6 +1374,11 @@ extern "C" __device__ float test_erfcf(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_erfc_f64(double noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_erfc(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_erfc_f64(double noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_erfc(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_erfc_f64(double noundef [[X:%.*]]) #[[ATTR13]]
@@ -1234,6 +1403,11 @@ extern "C" __device__ double test_erfc(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_erfinv_f32(float noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_erfinvf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_erfinv_f32(float noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_erfinvf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_erfinv_f32(float noundef [[X:%.*]]) #[[ATTR13]]
@@ -1258,6 +1432,11 @@ extern "C" __device__ float test_erfinvf(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_erfinv_f64(double noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_erfinv(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_erfinv_f64(double noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_erfinv(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_erfinv_f64(double noundef [[X:%.*]]) #[[ATTR13]]
@@ -1282,6 +1461,11 @@ extern "C" __device__ double test_erfinv(double x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.exp10.f32(float [[X:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test_exp10f(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.exp10.f32(float [[X:%.*]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_exp10f(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.exp10.f32(float [[X:%.*]])
@@ -1306,6 +1490,11 @@ extern "C" __device__ float test_exp10f(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_exp10_f64(double noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_exp10(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_exp10_f64(double noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_exp10(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_exp10_f64(double noundef [[X:%.*]]) #[[ATTR13]]
@@ -1330,6 +1519,11 @@ extern "C" __device__ double test_exp10(double x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.exp2.f32(float [[X:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test_exp2f(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.exp2.f32(float [[X:%.*]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_exp2f(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.exp2.f32(float [[X:%.*]])
@@ -1354,6 +1548,11 @@ extern "C" __device__ float test_exp2f(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_exp2_f64(double noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_exp2(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_exp2_f64(double noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_exp2(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_exp2_f64(double noundef [[X:%.*]]) #[[ATTR13]]
@@ -1378,6 +1577,11 @@ extern "C" __device__ double test_exp2(double x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.exp.f32(float [[X:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test_expf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.exp.f32(float [[X:%.*]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_expf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.exp.f32(float [[X:%.*]])
@@ -1402,6 +1606,11 @@ extern "C" __device__ float test_expf(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_exp_f64(double noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_exp(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_exp_f64(double noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_exp(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_exp_f64(double noundef [[X:%.*]]) #[[ATTR13]]
@@ -1426,6 +1635,11 @@ extern "C" __device__ double test_exp(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_expm1_f32(float noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_expm1f(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_expm1_f32(float noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_expm1f(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_expm1_f32(float noundef [[X:%.*]]) #[[ATTR13]]
@@ -1450,6 +1664,11 @@ extern "C" __device__ float test_expm1f(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_expm1_f64(double noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_expm1(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_expm1_f64(double noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_expm1(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_expm1_f64(double noundef [[X:%.*]]) #[[ATTR13]]
@@ -1474,6 +1693,11 @@ extern "C" __device__ double test_expm1(double x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.fabs.f32(float [[X:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test_fabsf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.fabs.f32(float [[X:%.*]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_fabsf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.fabs.f32(float [[X:%.*]])
@@ -1498,6 +1722,11 @@ extern "C" __device__ float test_fabsf(float x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.fabs.f64(double [[X:%.*]])
 // APPROX-NEXT:    ret double [[TMP0]]
 //
+// NCRDIV-LABEL: @test_fabs(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.fabs.f64(double [[X:%.*]])
+// NCRDIV-NEXT:    ret double [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_fabs(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) double @llvm.fabs.f64(double [[X:%.*]])
@@ -1522,6 +1751,11 @@ extern "C" __device__ double test_fabs(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_fdim_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_fdimf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_fdim_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_fdimf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_fdim_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR12]]
@@ -1546,6 +1780,11 @@ extern "C" __device__ float test_fdimf(float x, float y) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_fdim_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_fdim(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_fdim_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_fdim(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_fdim_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]]) #[[ATTR12]]
@@ -1570,6 +1809,11 @@ extern "C" __device__ double test_fdim(double x, double y) {
 // APPROX-NEXT:    [[DIV_I:%.*]] = fdiv contract float [[X:%.*]], [[Y:%.*]]
 // APPROX-NEXT:    ret float [[DIV_I]]
 //
+// NCRDIV-LABEL: @test_fdividef(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[DIV_I:%.*]] = fdiv contract float [[X:%.*]], [[Y:%.*]], !fpmath [[META12:![0-9]+]]
+// NCRDIV-NEXT:    ret float [[DIV_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_fdividef(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[DIV_I:%.*]] = fdiv contract float [[X:%.*]], [[Y:%.*]]
@@ -1594,6 +1838,11 @@ extern "C" __device__ float test_fdividef(float x, float y) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.floor.f32(float [[X:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test_floorf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.floor.f32(float [[X:%.*]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_floorf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.floor.f32(float [[X:%.*]])
@@ -1618,6 +1867,11 @@ extern "C" __device__ float test_floorf(float x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.floor.f64(double [[X:%.*]])
 // APPROX-NEXT:    ret double [[TMP0]]
 //
+// NCRDIV-LABEL: @test_floor(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.floor.f64(double [[X:%.*]])
+// NCRDIV-NEXT:    ret double [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_floor(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) double @llvm.floor.f64(double [[X:%.*]])
@@ -1642,6 +1896,11 @@ extern "C" __device__ double test_floor(double x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.fma.f32(float [[X:%.*]], float [[Y:%.*]], float [[Z:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test_fmaf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.fma.f32(float [[X:%.*]], float [[Y:%.*]], float [[Z:%.*]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_fmaf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.fma.f32(float [[X:%.*]], float [[Y:%.*]], float [[Z:%.*]])
@@ -1666,6 +1925,11 @@ extern "C" __device__ float test_fmaf(float x, float y, float z) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.fma.f64(double [[X:%.*]], double [[Y:%.*]], double [[Z:%.*]])
 // APPROX-NEXT:    ret double [[TMP0]]
 //
+// NCRDIV-LABEL: @test_fma(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.fma.f64(double [[X:%.*]], double [[Y:%.*]], double [[Z:%.*]])
+// NCRDIV-NEXT:    ret double [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_fma(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) double @llvm.fma.f64(double [[X:%.*]], double [[Y:%.*]], double [[Z:%.*]])
@@ -1690,6 +1954,11 @@ extern "C" __device__ double test_fma(double x, double y, double z) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.fma.f64(double [[X:%.*]], double [[Y:%.*]], double [[Z:%.*]])
 // APPROX-NEXT:    ret double [[TMP0]]
 //
+// NCRDIV-LABEL: @test_fma_rn(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.fma.f64(double [[X:%.*]], double [[Y:%.*]], double [[Z:%.*]])
+// NCRDIV-NEXT:    ret double [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_fma_rn(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) double @llvm.fma.f64(double [[X:%.*]], double [[Y:%.*]], double [[Z:%.*]])
@@ -1714,6 +1983,11 @@ extern "C" __device__ double test_fma_rn(double x, double y, double z) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.maxnum.f32(float [[X:%.*]], float [[Y:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test_fmaxf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.maxnum.f32(float [[X:%.*]], float [[Y:%.*]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_fmaxf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.maxnum.f32(float [[X:%.*]], float [[Y:%.*]])
@@ -1738,6 +2012,11 @@ extern "C" __device__ float test_fmaxf(float x, float y) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.maxnum.f64(double [[X:%.*]], double [[Y:%.*]])
 // APPROX-NEXT:    ret double [[TMP0]]
 //
+// NCRDIV-LABEL: @test_fmax(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.maxnum.f64(double [[X:%.*]], double [[Y:%.*]])
+// NCRDIV-NEXT:    ret double [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_fmax(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) double @llvm.maxnum.f64(double [[X:%.*]], double [[Y:%.*]])
@@ -1762,6 +2041,11 @@ extern "C" __device__ double test_fmax(double x, double y) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.minnum.f32(float [[X:%.*]], float [[Y:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test_fminf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.minnum.f32(float [[X:%.*]], float [[Y:%.*]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_fminf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.minnum.f32(float [[X:%.*]], float [[Y:%.*]])
@@ -1786,6 +2070,11 @@ extern "C" __device__ float test_fminf(float x, float y) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.minnum.f64(double [[X:%.*]], double [[Y:%.*]])
 // APPROX-NEXT:    ret double [[TMP0]]
 //
+// NCRDIV-LABEL: @test_fmin(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.minnum.f64(double [[X:%.*]], double [[Y:%.*]])
+// NCRDIV-NEXT:    ret double [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_fmin(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) double @llvm.minnum.f64(double [[X:%.*]], double [[Y:%.*]])
@@ -1810,6 +2099,11 @@ extern "C" __device__ double test_fmin(double x, double y) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_fmod_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_fmodf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_fmod_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_fmodf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_fmod_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR12]]
@@ -1834,6 +2128,11 @@ extern "C" __device__ float test_fmodf(float x, float y) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_fmod_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_fmod(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_fmod_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_fmod(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_fmod_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]]) #[[ATTR12]]
@@ -1867,6 +2166,14 @@ extern "C" __device__ double test_fmod(double x, double y) {
 // APPROX-NEXT:    [[TMP2:%.*]] = extractvalue { float, i32 } [[TMP0]], 0
 // APPROX-NEXT:    ret float [[TMP2]]
 //
+// NCRDIV-LABEL: @test_frexpf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call { float, i32 } @llvm.frexp.f32.i32(float [[X:%.*]])
+// NCRDIV-NEXT:    [[TMP1:%.*]] = extractvalue { float, i32 } [[TMP0]], 1
+// NCRDIV-NEXT:    store i32 [[TMP1]], ptr [[Y:%.*]], align 4, !tbaa [[TBAA13:![0-9]+]]
+// NCRDIV-NEXT:    [[TMP2:%.*]] = extractvalue { float, i32 } [[TMP0]], 0
+// NCRDIV-NEXT:    ret float [[TMP2]]
+//
 // AMDGCNSPIRV-LABEL: @test_frexpf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call addrspace(4) { float, i32 } @llvm.frexp.f32.i32(float [[X:%.*]])
@@ -1903,6 +2210,14 @@ extern "C" __device__ float test_frexpf(float x, int* y) {
 // APPROX-NEXT:    [[TMP2:%.*]] = extractvalue { double, i32 } [[TMP0]], 0
 // APPROX-NEXT:    ret double [[TMP2]]
 //
+// NCRDIV-LABEL: @test_frexp(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call { double, i32 } @llvm.frexp.f64.i32(double [[X:%.*]])
+// NCRDIV-NEXT:    [[TMP1:%.*]] = extractvalue { double, i32 } [[TMP0]], 1
+// NCRDIV-NEXT:    store i32 [[TMP1]], ptr [[Y:%.*]], align 4, !tbaa [[TBAA13]]
+// NCRDIV-NEXT:    [[TMP2:%.*]] = extractvalue { double, i32 } [[TMP0]], 0
+// NCRDIV-NEXT:    ret double [[TMP2]]
+//
 // AMDGCNSPIRV-LABEL: @test_frexp(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call addrspace(4) { double, i32 } @llvm.frexp.f64.i32(double [[X:%.*]])
@@ -1930,6 +2245,11 @@ extern "C" __device__ double test_frexp(double x, int* y) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_hypot_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_hypotf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_hypot_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_hypotf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_hypot_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR12]]
@@ -1954,6 +2274,11 @@ extern "C" __device__ float test_hypotf(float x, float y) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_hypot_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_hypot(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_hypot_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_hypot(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_hypot_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]]) #[[ATTR12]]
@@ -1978,6 +2303,11 @@ extern "C" __device__ double test_hypot(double x, double y) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call noundef i32 @__ocml_ilogb_f32(float noundef [[X:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret i32 [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_ilogbf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call noundef i32 @__ocml_ilogb_f32(float noundef [[X:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret i32 [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_ilogbf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call spir_func noundef addrspace(4) i32 @__ocml_ilogb_f32(float noundef [[X:%.*]]) #[[ATTR12]]
@@ -2002,6 +2332,11 @@ extern "C" __device__ int test_ilogbf(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call noundef i32 @__ocml_ilogb_f64(double noundef [[X:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret i32 [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_ilogb(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call noundef i32 @__ocml_ilogb_f64(double noundef [[X:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret i32 [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_ilogb(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call spir_func noundef addrspace(4) i32 @__ocml_ilogb_f64(double noundef [[X:%.*]]) #[[ATTR12]]
@@ -2029,6 +2364,13 @@ extern "C" __device__ int test_ilogb(double x) {
 // APPROX-NEXT:    [[CONV:%.*]] = zext i1 [[TMP1]] to i32
 // APPROX-NEXT:    ret i32 [[CONV]]
 //
+// NCRDIV-LABEL: @test___finitef(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[X:%.*]])
+// NCRDIV-NEXT:    [[TMP1:%.*]] = fcmp one float [[TMP0]], 0x7FF0000000000000
+// NCRDIV-NEXT:    [[CONV:%.*]] = zext i1 [[TMP1]] to i32
+// NCRDIV-NEXT:    ret i32 [[CONV]]
+//
 // AMDGCNSPIRV-LABEL: @test___finitef(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call addrspace(4) float @llvm.fabs.f32(float [[X:%.*]])
@@ -2058,6 +2400,13 @@ extern "C" __device__ BOOL_TYPE test___finitef(float x) {
 // APPROX-NEXT:    [[CONV:%.*]] = zext i1 [[TMP1]] to i32
 // APPROX-NEXT:    ret i32 [[CONV]]
 //
+// NCRDIV-LABEL: @test___finite(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call double @llvm.fabs.f64(double [[X:%.*]])
+// NCRDIV-NEXT:    [[TMP1:%.*]] = fcmp one double [[TMP0]], 0x7FF0000000000000
+// NCRDIV-NEXT:    [[CONV:%.*]] = zext i1 [[TMP1]] to i32
+// NCRDIV-NEXT:    ret i32 [[CONV]]
+//
 // AMDGCNSPIRV-LABEL: @test___finite(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call addrspace(4) double @llvm.fabs.f64(double [[X:%.*]])
@@ -2087,6 +2436,13 @@ extern "C" __device__ BOOL_TYPE test___finite(double x) {
 // APPROX-NEXT:    [[CONV:%.*]] = zext i1 [[TMP1]] to i32
 // APPROX-NEXT:    ret i32 [[CONV]]
 //
+// NCRDIV-LABEL: @test___isinff(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[X:%.*]])
+// NCRDIV-NEXT:    [[TMP1:%.*]] = fcmp oeq float [[TMP0]], 0x7FF0000000000000
+// NCRDIV-NEXT:    [[CONV:%.*]] = zext i1 [[TMP1]] to i32
+// NCRDIV-NEXT:    ret i32 [[CONV]]
+//
 // AMDGCNSPIRV-LABEL: @test___isinff(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call addrspace(4) float @llvm.fabs.f32(float [[X:%.*]])
@@ -2116,6 +2472,13 @@ extern "C" __device__ BOOL_TYPE test___isinff(float x) {
 // APPROX-NEXT:    [[CONV:%.*]] = zext i1 [[TMP1]] to i32
 // APPROX-NEXT:    ret i32 [[CONV]]
 //
+// NCRDIV-LABEL: @test___isinf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call double @llvm.fabs.f64(double [[X:%.*]])
+// NCRDIV-NEXT:    [[TMP1:%.*]] = fcmp oeq double [[TMP0]], 0x7FF0000000000000
+// NCRDIV-NEXT:    [[CONV:%.*]] = zext i1 [[TMP1]] to i32
+// NCRDIV-NEXT:    ret i32 [[CONV]]
+//
 // AMDGCNSPIRV-LABEL: @test___isinf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call addrspace(4) double @llvm.fabs.f64(double [[X:%.*]])
@@ -2143,6 +2506,12 @@ extern "C" __device__ BOOL_TYPE test___isinf(double x) {
 // APPROX-NEXT:    [[CONV:%.*]] = zext i1 [[TMP0]] to i32
 // APPROX-NEXT:    ret i32 [[CONV]]
 //
+// NCRDIV-LABEL: @test___isnanf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = fcmp uno float [[X:%.*]], 0.000000e+00
+// NCRDIV-NEXT:    [[CONV:%.*]] = zext i1 [[TMP0]] to i32
+// NCRDIV-NEXT:    ret i32 [[CONV]]
+//
 // AMDGCNSPIRV-LABEL: @test___isnanf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = fcmp uno float [[X:%.*]], 0.000000e+00
@@ -2169,6 +2538,12 @@ extern "C" __device__ BOOL_TYPE test___isnanf(float x) {
 // APPROX-NEXT:    [[CONV:%.*]] = zext i1 [[TMP0]] to i32
 // APPROX-NEXT:    ret i32 [[CONV]]
 //
+// NCRDIV-LABEL: @test___isnan(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = fcmp uno double [[X:%.*]], 0.000000e+00
+// NCRDIV-NEXT:    [[CONV:%.*]] = zext i1 [[TMP0]] to i32
+// NCRDIV-NEXT:    ret i32 [[CONV]]
+//
 // AMDGCNSPIRV-LABEL: @test___isnan(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = fcmp uno double [[X:%.*]], 0.000000e+00
@@ -2194,6 +2569,11 @@ extern "C" __device__ BOOL_TYPE test___isnan(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_j0_f32(float noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_j0f(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_j0_f32(float noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_j0f(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_j0_f32(float noundef [[X:%.*]]) #[[ATTR14]]
@@ -2218,6 +2598,11 @@ extern "C" __device__ float test_j0f(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_j0_f64(double noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_j0(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_j0_f64(double noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_j0(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_j0_f64(double noundef [[X:%.*]]) #[[ATTR14]]
@@ -2242,6 +2627,11 @@ extern "C" __device__ double test_j0(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_j1_f32(float noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_j1f(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_j1_f32(float noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_j1f(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_j1_f32(float noundef [[X:%.*]]) #[[ATTR14]]
@@ -2266,6 +2656,11 @@ extern "C" __device__ float test_j1f(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_j1_f64(double noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_j1(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_j1_f64(double noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_j1(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_j1_f64(double noundef [[X:%.*]]) #[[ATTR14]]
@@ -2374,6 +2769,39 @@ extern "C" __device__ double test_j1(double x) {
 // APPROX-NEXT:    [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I20_I]], [[IF_THEN_I]] ], [ [[CALL_I22_I]], [[IF_THEN2_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ]
 // APPROX-NEXT:    ret float [[RETVAL_0_I]]
 //
+// NCRDIV-LABEL: @test_jnf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    switch i32 [[X:%.*]], label [[IF_END4_I:%.*]] [
+// NCRDIV-NEXT:      i32 0, label [[IF_THEN_I:%.*]]
+// NCRDIV-NEXT:      i32 1, label [[IF_THEN2_I:%.*]]
+// NCRDIV-NEXT:    ]
+// NCRDIV:       if.then.i:
+// NCRDIV-NEXT:    [[CALL_I20_I:%.*]] = tail call contract noundef float @__ocml_j0_f32(float noundef [[Y:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    br label [[_ZL3JNFIF_EXIT:%.*]]
+// NCRDIV:       if.then2.i:
+// NCRDIV-NEXT:    [[CALL_I22_I:%.*]] = tail call contract noundef float @__ocml_j1_f32(float noundef [[Y]]) #[[ATTR14]]
+// NCRDIV-NEXT:    br label [[_ZL3JNFIF_EXIT]]
+// NCRDIV:       if.end4.i:
+// NCRDIV-NEXT:    [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_j0_f32(float noundef [[Y]]) #[[ATTR14]]
+// NCRDIV-NEXT:    [[CALL_I21_I:%.*]] = tail call contract noundef float @__ocml_j1_f32(float noundef [[Y]]) #[[ATTR14]]
+// NCRDIV-NEXT:    [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1
+// NCRDIV-NEXT:    br i1 [[CMP7_I1]], label [[FOR_BODY_I:%.*]], label [[_ZL3JNFIF_EXIT]]
+// NCRDIV:       for.body.i:
+// NCRDIV-NEXT:    [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ]
+// NCRDIV-NEXT:    [[__X1_0_I3:%.*]] = phi float [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ]
+// NCRDIV-NEXT:    [[__X0_0_I2:%.*]] = phi float [ [[__X1_0_I3]], [[FOR_BODY_I]] ], [ [[CALL_I_I]], [[IF_END4_I]] ]
+// NCRDIV-NEXT:    [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1
+// NCRDIV-NEXT:    [[CONV_I:%.*]] = uitofp nneg i32 [[MUL_I]] to float
+// NCRDIV-NEXT:    [[DIV_I:%.*]] = fdiv contract float [[CONV_I]], [[Y]], !fpmath [[META12]]
+// NCRDIV-NEXT:    [[MUL8_I:%.*]] = fmul contract float [[__X1_0_I3]], [[DIV_I]]
+// NCRDIV-NEXT:    [[SUB_I]] = fsub contract float [[MUL8_I]], [[__X0_0_I2]]
+// NCRDIV-NEXT:    [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1
+// NCRDIV-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]]
+// NCRDIV-NEXT:    br i1 [[EXITCOND_NOT]], label [[_ZL3JNFIF_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP15:![0-9]+]]
+// NCRDIV:       _ZL3jnfif.exit:
+// NCRDIV-NEXT:    [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I20_I]], [[IF_THEN_I]] ], [ [[CALL_I22_I]], [[IF_THEN2_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ]
+// NCRDIV-NEXT:    ret float [[RETVAL_0_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_jnf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    switch i32 [[X:%.*]], label [[IF_END4_I:%.*]] [
@@ -2510,6 +2938,39 @@ extern "C" __device__ float test_jnf(int x, float y) {
 // APPROX-NEXT:    [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I20_I]], [[IF_THEN_I]] ], [ [[CALL_I22_I]], [[IF_THEN2_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ]
 // APPROX-NEXT:    ret double [[RETVAL_0_I]]
 //
+// NCRDIV-LABEL: @test_jn(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    switch i32 [[X:%.*]], label [[IF_END4_I:%.*]] [
+// NCRDIV-NEXT:      i32 0, label [[IF_THEN_I:%.*]]
+// NCRDIV-NEXT:      i32 1, label [[IF_THEN2_I:%.*]]
+// NCRDIV-NEXT:    ]
+// NCRDIV:       if.then.i:
+// NCRDIV-NEXT:    [[CALL_I20_I:%.*]] = tail call contract noundef double @__ocml_j0_f64(double noundef [[Y:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    br label [[_ZL2JNID_EXIT:%.*]]
+// NCRDIV:       if.then2.i:
+// NCRDIV-NEXT:    [[CALL_I22_I:%.*]] = tail call contract noundef double @__ocml_j1_f64(double noundef [[Y]]) #[[ATTR14]]
+// NCRDIV-NEXT:    br label [[_ZL2JNID_EXIT]]
+// NCRDIV:       if.end4.i:
+// NCRDIV-NEXT:    [[CALL_I_I:%.*]] = tail call contract noundef double @__ocml_j0_f64(double noundef [[Y]]) #[[ATTR14]]
+// NCRDIV-NEXT:    [[CALL_I21_I:%.*]] = tail call contract noundef double @__ocml_j1_f64(double noundef [[Y]]) #[[ATTR14]]
+// NCRDIV-NEXT:    [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1
+// NCRDIV-NEXT:    br i1 [[CMP7_I1]], label [[FOR_BODY_I:%.*]], label [[_ZL2JNID_EXIT]]
+// NCRDIV:       for.body.i:
+// NCRDIV-NEXT:    [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ]
+// NCRDIV-NEXT:    [[__X1_0_I3:%.*]] = phi double [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ]
+// NCRDIV-NEXT:    [[__X0_0_I2:%.*]] = phi double [ [[__X1_0_I3]], [[FOR_BODY_I]] ], [ [[CALL_I_I]], [[IF_END4_I]] ]
+// NCRDIV-NEXT:    [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1
+// NCRDIV-NEXT:    [[CONV_I:%.*]] = uitofp nneg i32 [[MUL_I]] to double
+// NCRDIV-NEXT:    [[DIV_I:%.*]] = fdiv contract double [[CONV_I]], [[Y]]
+// NCRDIV-NEXT:    [[MUL8_I:%.*]] = fmul contract double [[__X1_0_I3]], [[DIV_I]]
+// NCRDIV-NEXT:    [[SUB_I]] = fsub contract double [[MUL8_I]], [[__X0_0_I2]]
+// NCRDIV-NEXT:    [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1
+// NCRDIV-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]]
+// NCRDIV-NEXT:    br i1 [[EXITCOND_NOT]], label [[_ZL2JNID_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP16:![0-9]+]]
+// NCRDIV:       _ZL2jnid.exit:
+// NCRDIV-NEXT:    [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I20_I]], [[IF_THEN_I]] ], [ [[CALL_I22_I]], [[IF_THEN2_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ]
+// NCRDIV-NEXT:    ret double [[RETVAL_0_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_jn(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    switch i32 [[X:%.*]], label [[IF_END4_I:%.*]] [
@@ -2562,6 +3023,11 @@ extern "C" __device__ double test_jn(int x, double y) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.ldexp.f32.i32(float [[X:%.*]], i32 [[Y:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test_ldexpf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.ldexp.f32.i32(float [[X:%.*]], i32 [[Y:%.*]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_ldexpf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.ldexp.f32.i32(float [[X:%.*]], i32 [[Y:%.*]])
@@ -2586,6 +3052,11 @@ extern "C" __device__ float test_ldexpf(float x, int y) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.ldexp.f64.i32(double [[X:%.*]], i32 [[Y:%.*]])
 // APPROX-NEXT:    ret double [[TMP0]]
 //
+// NCRDIV-LABEL: @test_ldexp(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.ldexp.f64.i32(double [[X:%.*]], i32 [[Y:%.*]])
+// NCRDIV-NEXT:    ret double [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_ldexp(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) double @llvm.ldexp.f64.i32(double [[X:%.*]], i32 [[Y:%.*]])
@@ -2610,6 +3081,11 @@ extern "C" __device__ double test_ldexp(double x, int y) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_lgamma_f32(float noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_lgammaf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_lgamma_f32(float noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_lgammaf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_lgamma_f32(float noundef [[X:%.*]]) #[[ATTR14]]
@@ -2634,6 +3110,11 @@ extern "C" __device__ float test_lgammaf(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_lgamma_f64(double noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_lgamma(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_lgamma_f64(double noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_lgamma(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_lgamma_f64(double noundef [[X:%.*]]) #[[ATTR14]]
@@ -2661,6 +3142,12 @@ extern "C" __device__ double test_lgamma(double x) {
 // APPROX-NEXT:    [[CONV_I:%.*]] = fptosi float [[TMP0]] to i64
 // APPROX-NEXT:    ret i64 [[CONV_I]]
 //
+// NCRDIV-LABEL: @test_llrintf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract float @llvm.rint.f32(float [[X:%.*]])
+// NCRDIV-NEXT:    [[CONV_I:%.*]] = fptosi float [[TMP0]] to i64
+// NCRDIV-NEXT:    ret i64 [[CONV_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_llrintf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract addrspace(4) float @llvm.rint.f32(float [[X:%.*]])
@@ -2689,6 +3176,12 @@ extern "C" __device__ long long int test_llrintf(float x) {
 // APPROX-NEXT:    [[CONV_I:%.*]] = fptosi double [[TMP0]] to i64
 // APPROX-NEXT:    ret i64 [[CONV_I]]
 //
+// NCRDIV-LABEL: @test_llrint(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract double @llvm.rint.f64(double [[X:%.*]])
+// NCRDIV-NEXT:    [[CONV_I:%.*]] = fptosi double [[TMP0]] to i64
+// NCRDIV-NEXT:    ret i64 [[CONV_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_llrint(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract addrspace(4) double @llvm.rint.f64(double [[X:%.*]])
@@ -2717,6 +3210,12 @@ extern "C" __device__ long long int test_llrint(double x) {
 // APPROX-NEXT:    [[CONV_I:%.*]] = fptosi float [[TMP0]] to i64
 // APPROX-NEXT:    ret i64 [[CONV_I]]
 //
+// NCRDIV-LABEL: @test_llroundf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract float @llvm.round.f32(float [[X:%.*]])
+// NCRDIV-NEXT:    [[CONV_I:%.*]] = fptosi float [[TMP0]] to i64
+// NCRDIV-NEXT:    ret i64 [[CONV_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_llroundf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract addrspace(4) float @llvm.round.f32(float [[X:%.*]])
@@ -2745,6 +3244,12 @@ extern "C" __device__ long long int test_llroundf(float x) {
 // APPROX-NEXT:    [[CONV_I:%.*]] = fptosi double [[TMP0]] to i64
 // APPROX-NEXT:    ret i64 [[CONV_I]]
 //
+// NCRDIV-LABEL: @test_llround(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract double @llvm.round.f64(double [[X:%.*]])
+// NCRDIV-NEXT:    [[CONV_I:%.*]] = fptosi double [[TMP0]] to i64
+// NCRDIV-NEXT:    ret i64 [[CONV_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_llround(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract addrspace(4) double @llvm.round.f64(double [[X:%.*]])
@@ -2770,6 +3275,11 @@ extern "C" __device__ long long int test_llround(double x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.log10.f32(float [[X:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test_log10f(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.log10.f32(float [[X:%.*]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_log10f(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.log10.f32(float [[X:%.*]])
@@ -2794,6 +3304,11 @@ extern "C" __device__ float test_log10f(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_log10_f64(double noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_log10(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_log10_f64(double noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_log10(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_log10_f64(double noundef [[X:%.*]]) #[[ATTR13]]
@@ -2818,6 +3333,11 @@ extern "C" __device__ double test_log10(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_log1p_f32(float noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_log1pf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_log1p_f32(float noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_log1pf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_log1p_f32(float noundef [[X:%.*]]) #[[ATTR13]]
@@ -2842,6 +3362,11 @@ extern "C" __device__ float test_log1pf(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_log1p_f64(double noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_log1p(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_log1p_f64(double noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_log1p(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_log1p_f64(double noundef [[X:%.*]]) #[[ATTR13]]
@@ -2866,6 +3391,11 @@ extern "C" __device__ double test_log1p(double x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.amdgcn.log.f32(float [[X:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test_log2f(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.log2.f32(float [[X:%.*]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_log2f(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.log2.f32(float [[X:%.*]])
@@ -2890,6 +3420,11 @@ extern "C" __device__ float test_log2f(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_log2_f64(double noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_log2(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_log2_f64(double noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_log2(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_log2_f64(double noundef [[X:%.*]]) #[[ATTR13]]
@@ -2914,6 +3449,11 @@ extern "C" __device__ double test_log2(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_logb_f32(float noundef [[X:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_logbf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_logb_f32(float noundef [[X:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_logbf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_logb_f32(float noundef [[X:%.*]]) #[[ATTR12]]
@@ -2938,6 +3478,11 @@ extern "C" __device__ float test_logbf(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_logb_f64(double noundef [[X:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_logb(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_logb_f64(double noundef [[X:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_logb(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_logb_f64(double noundef [[X:%.*]]) #[[ATTR12]]
@@ -2962,6 +3507,11 @@ extern "C" __device__ double test_logb(double x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.log.f32(float [[X:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test_logf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.log.f32(float [[X:%.*]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_logf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.log.f32(float [[X:%.*]])
@@ -2989,6 +3539,12 @@ extern "C" __device__ float test_logf(float x) {
 // APPROX-NEXT:    [[CONV_I:%.*]] = fptosi float [[TMP0]] to i64
 // APPROX-NEXT:    ret i64 [[CONV_I]]
 //
+// NCRDIV-LABEL: @test_lrintf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract float @llvm.rint.f32(float [[X:%.*]])
+// NCRDIV-NEXT:    [[CONV_I:%.*]] = fptosi float [[TMP0]] to i64
+// NCRDIV-NEXT:    ret i64 [[CONV_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_lrintf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract addrspace(4) float @llvm.rint.f32(float [[X:%.*]])
@@ -3017,6 +3573,12 @@ extern "C" __device__ long int test_lrintf(float x) {
 // APPROX-NEXT:    [[CONV_I:%.*]] = fptosi double [[TMP0]] to i64
 // APPROX-NEXT:    ret i64 [[CONV_I]]
 //
+// NCRDIV-LABEL: @test_lrint(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract double @llvm.rint.f64(double [[X:%.*]])
+// NCRDIV-NEXT:    [[CONV_I:%.*]] = fptosi double [[TMP0]] to i64
+// NCRDIV-NEXT:    ret i64 [[CONV_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_lrint(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract addrspace(4) double @llvm.rint.f64(double [[X:%.*]])
@@ -3045,6 +3607,12 @@ extern "C" __device__ long int test_lrint(double x) {
 // APPROX-NEXT:    [[CONV_I:%.*]] = fptosi float [[TMP0]] to i64
 // APPROX-NEXT:    ret i64 [[CONV_I]]
 //
+// NCRDIV-LABEL: @test_lroundf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract float @llvm.round.f32(float [[X:%.*]])
+// NCRDIV-NEXT:    [[CONV_I:%.*]] = fptosi float [[TMP0]] to i64
+// NCRDIV-NEXT:    ret i64 [[CONV_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_lroundf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract addrspace(4) float @llvm.round.f32(float [[X:%.*]])
@@ -3073,6 +3641,12 @@ extern "C" __device__ long int test_lroundf(float x) {
 // APPROX-NEXT:    [[CONV_I:%.*]] = fptosi double [[TMP0]] to i64
 // APPROX-NEXT:    ret i64 [[CONV_I]]
 //
+// NCRDIV-LABEL: @test_lround(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract double @llvm.round.f64(double [[X:%.*]])
+// NCRDIV-NEXT:    [[CONV_I:%.*]] = fptosi double [[TMP0]] to i64
+// NCRDIV-NEXT:    ret i64 [[CONV_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_lround(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract addrspace(4) double @llvm.round.f64(double [[X:%.*]])
@@ -3113,6 +3687,16 @@ extern "C" __device__ long int test_lround(double x) {
 // APPROX-NEXT:    call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[__TMP_I]]) #[[ATTR15]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_modff(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[__TMP_I:%.*]] = alloca float, align 4, addrspace(5)
+// NCRDIV-NEXT:    call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[__TMP_I]]) #[[ATTR15:[0-9]+]]
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = call contract noundef float @__ocml_modf_f32(float noundef [[X:%.*]], ptr addrspace(5) noundef [[__TMP_I]]) #[[ATTR14]]
+// NCRDIV-NEXT:    [[TMP0:%.*]] = load float, ptr addrspace(5) [[__TMP_I]], align 4, !tbaa [[TBAA17:![0-9]+]]
+// NCRDIV-NEXT:    store float [[TMP0]], ptr [[Y:%.*]], align 4, !tbaa [[TBAA17]]
+// NCRDIV-NEXT:    call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[__TMP_I]]) #[[ATTR15]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_modff(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[__TMP_I:%.*]] = alloca float, align 4
@@ -3158,6 +3742,16 @@ extern "C" __device__ float test_modff(float x, float* y) {
 // APPROX-NEXT:    call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[__TMP_I]]) #[[ATTR15]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_modf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[__TMP_I:%.*]] = alloca double, align 8, addrspace(5)
+// NCRDIV-NEXT:    call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[__TMP_I]]) #[[ATTR15]]
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = call contract noundef double @__ocml_modf_f64(double noundef [[X:%.*]], ptr addrspace(5) noundef [[__TMP_I]]) #[[ATTR14]]
+// NCRDIV-NEXT:    [[TMP0:%.*]] = load double, ptr addrspace(5) [[__TMP_I]], align 8, !tbaa [[TBAA19:![0-9]+]]
+// NCRDIV-NEXT:    store double [[TMP0]], ptr [[Y:%.*]], align 8, !tbaa [[TBAA19]]
+// NCRDIV-NEXT:    call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[__TMP_I]]) #[[ATTR15]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_modf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[__TMP_I:%.*]] = alloca double, align 8
@@ -3367,6 +3961,101 @@ extern "C" __device__ double test_modf(double x, double* y) {
 // APPROX-NEXT:    [[TMP10:%.*]] = bitcast i32 [[BF_SET9_I]] to float
 // APPROX-NEXT:    ret float [[TMP10]]
 //
+// NCRDIV-LABEL: @test_nanf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = load i8, ptr [[TAG:%.*]], align 1, !tbaa [[TBAA4]]
+// NCRDIV-NEXT:    [[CMP_I_I:%.*]] = icmp eq i8 [[TMP0]], 48
+// NCRDIV-NEXT:    br i1 [[CMP_I_I]], label [[IF_THEN_I_I:%.*]], label [[WHILE_COND_I14_I_I:%.*]]
+// NCRDIV:       if.then.i.i:
+// NCRDIV-NEXT:    [[INCDEC_PTR_I_I:%.*]] = getelementptr inbounds nuw i8, ptr [[TAG]], i64 1
+// NCRDIV-NEXT:    [[TMP1:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[TBAA4]]
+// NCRDIV-NEXT:    switch i8 [[TMP1]], label [[WHILE_COND_I_I_I:%.*]] [
+// NCRDIV-NEXT:      i8 120, label [[WHILE_COND_I30_I_I_PREHEADER:%.*]]
+// NCRDIV-NEXT:      i8 88, label [[WHILE_COND_I30_I_I_PREHEADER]]
+// NCRDIV-NEXT:    ]
+// NCRDIV:       while.cond.i30.i.i.preheader:
+// NCRDIV-NEXT:    br label [[WHILE_COND_I30_I_I:%.*]]
+// NCRDIV:       while.cond.i30.i.i:
+// NCRDIV-NEXT:    [[__TAGP_ADDR_0_I31_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I37_I_I:%.*]], [[CLEANUP_I36_I_I:%.*]] ], [ [[INCDEC_PTR_I_I]], [[WHILE_COND_I30_I_I_PREHEADER]] ]
+// NCRDIV-NEXT:    [[__R_0_I32_I_I:%.*]] = phi i64 [ [[__R_2_I_I_I:%.*]], [[CLEANUP_I36_I_I]] ], [ 0, [[WHILE_COND_I30_I_I_PREHEADER]] ]
+// NCRDIV-NEXT:    [[TMP2:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I31_I_I]], align 1, !tbaa [[TBAA4]]
+// NCRDIV-NEXT:    [[CMP_NOT_I33_I_I:%.*]] = icmp eq i8 [[TMP2]], 0
+// NCRDIV-NEXT:    br i1 [[CMP_NOT_I33_I_I]], label [[_ZL4NANFPKC_EXIT:%.*]], label [[WHILE_BODY_I34_I_I:%.*]]
+// NCRDIV:       while.body.i34.i.i:
+// NCRDIV-NEXT:    [[TMP3:%.*]] = add i8 [[TMP2]], -48
+// NCRDIV-NEXT:    [[OR_COND_I35_I_I:%.*]] = icmp ult i8 [[TMP3]], 10
+// NCRDIV-NEXT:    br i1 [[OR_COND_I35_I_I]], label [[IF_END31_I_I_I:%.*]], label [[IF_ELSE_I_I_I:%.*]]
+// NCRDIV:       if.else.i.i.i:
+// NCRDIV-NEXT:    [[TMP4:%.*]] = add i8 [[TMP2]], -97
+// NCRDIV-NEXT:    [[OR_COND33_I_I_I:%.*]] = icmp ult i8 [[TMP4]], 6
+// NCRDIV-NEXT:    br i1 [[OR_COND33_I_I_I]], label [[IF_END31_I_I_I]], label [[IF_ELSE17_I_I_I:%.*]]
+// NCRDIV:       if.else17.i.i.i:
+// NCRDIV-NEXT:    [[TMP5:%.*]] = add i8 [[TMP2]], -65
+// NCRDIV-NEXT:    [[OR_COND34_I_I_I:%.*]] = icmp ult i8 [[TMP5]], 6
+// NCRDIV-NEXT:    br i1 [[OR_COND34_I_I_I]], label [[IF_END31_I_I_I]], label [[CLEANUP_I36_I_I]]
+// NCRDIV:       if.end31.i.i.i:
+// NCRDIV-NEXT:    [[DOTSINK:%.*]] = phi i64 [ -48, [[WHILE_BODY_I34_I_I]] ], [ -87, [[IF_ELSE_I_I_I]] ], [ -55, [[IF_ELSE17_I_I_I]] ]
+// NCRDIV-NEXT:    [[MUL24_I_I_I:%.*]] = shl i64 [[__R_0_I32_I_I]], 4
+// NCRDIV-NEXT:    [[CONV25_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64
+// NCRDIV-NEXT:    [[ADD26_I_I_I:%.*]] = add i64 [[MUL24_I_I_I]], [[DOTSINK]]
+// NCRDIV-NEXT:    [[ADD28_I_I_I:%.*]] = add i64 [[ADD26_I_I_I]], [[CONV25_I_I_I]]
+// NCRDIV-NEXT:    [[INCDEC_PTR_I40_I_I:%.*]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I31_I_I]], i64 1
+// NCRDIV-NEXT:    br label [[CLEANUP_I36_I_I]]
+// NCRDIV:       cleanup.i36.i.i:
+// NCRDIV-NEXT:    [[__TAGP_ADDR_1_I37_I_I]] = phi ptr [ [[INCDEC_PTR_I40_I_I]], [[IF_END31_I_I_I]] ], [ [[__TAGP_ADDR_0_I31_I_I]], [[IF_ELSE17_I_I_I]] ]
+// NCRDIV-NEXT:    [[__R_2_I_I_I]] = phi i64 [ [[ADD28_I_I_I]], [[IF_END31_I_I_I]] ], [ [[__R_0_I32_I_I]], [[IF_ELSE17_I_I_I]] ]
+// NCRDIV-NEXT:    [[COND_I_I_I:%.*]] = phi i1 [ true, [[IF_END31_I_I_I]] ], [ false, [[IF_ELSE17_I_I_I]] ]
+// NCRDIV-NEXT:    br i1 [[COND_I_I_I]], label [[WHILE_COND_I30_I_I]], label [[_ZL4NANFPKC_EXIT]], !llvm.loop [[LOOP11]]
+// NCRDIV:       while.cond.i.i.i:
+// NCRDIV-NEXT:    [[__TAGP_ADDR_0_I_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I_I_I:%.*]], [[CLEANUP_I_I_I:%.*]] ], [ [[INCDEC_PTR_I_I]], [[IF_THEN_I_I]] ]
+// NCRDIV-NEXT:    [[__R_0_I_I_I:%.*]] = phi i64 [ [[__R_1_I_I_I:%.*]], [[CLEANUP_I_I_I]] ], [ 0, [[IF_THEN_I_I]] ]
+// NCRDIV-NEXT:    [[TMP6:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I_I_I]], align 1, !tbaa [[TBAA4]]
+// NCRDIV-NEXT:    [[CMP_NOT_I_I_I:%.*]] = icmp eq i8 [[TMP6]], 0
+// NCRDIV-NEXT:    br i1 [[CMP_NOT_I_I_I]], label [[_ZL4NANFPKC_EXIT]], label [[WHILE_BODY_I_I_I:%.*]]
+// NCRDIV:       while.body.i.i.i:
+// NCRDIV-NEXT:    [[TMP7:%.*]] = and i8 [[TMP6]], -8
+// NCRDIV-NEXT:    [[OR_COND_I_I_I:%.*]] = icmp eq i8 [[TMP7]], 48
+// NCRDIV-NEXT:    br i1 [[OR_COND_I_I_I]], label [[IF_THEN_I_I_I:%.*]], label [[CLEANUP_I_I_I]]
+// NCRDIV:       if.then.i.i.i:
+// NCRDIV-NEXT:    [[MUL_I_I_I:%.*]] = shl i64 [[__R_0_I_I_I]], 3
+// NCRDIV-NEXT:    [[CONV5_I_I_I:%.*]] = zext nneg i8 [[TMP6]] to i64
+// NCRDIV-NEXT:    [[ADD_I_I_I:%.*]] = add i64 [[MUL_I_I_I]], -48
+// NCRDIV-NEXT:    [[SUB_I_I_I:%.*]] = add i64 [[ADD_I_I_I]], [[CONV5_I_I_I]]
+// NCRDIV-NEXT:    [[INCDEC_PTR_I_I_I:%.*]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I_I_I]], i64 1
+// NCRDIV-NEXT:    br label [[CLEANUP_I_I_I]]
+// NCRDIV:       cleanup.i.i.i:
+// NCRDIV-NEXT:    [[__TAGP_ADDR_1_I_I_I]] = phi ptr [ [[INCDEC_PTR_I_I_I]], [[IF_THEN_I_I_I]] ], [ [[__TAGP_ADDR_0_I_I_I]], [[WHILE_BODY_I_I_I]] ]
+// NCRDIV-NEXT:    [[__R_1_I_I_I]] = phi i64 [ [[SUB_I_I_I]], [[IF_THEN_I_I_I]] ], [ [[__R_0_I_I_I]], [[WHILE_BODY_I_I_I]] ]
+// NCRDIV-NEXT:    br i1 [[OR_COND_I_I_I]], label [[WHILE_COND_I_I_I]], label [[_ZL4NANFPKC_EXIT]], !llvm.loop [[LOOP7]]
+// NCRDIV:       while.cond.i14.i.i:
+// NCRDIV-NEXT:    [[__TAGP_ADDR_0_I15_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I21_I_I:%.*]], [[CLEANUP_I20_I_I:%.*]] ], [ [[TAG]], [[ENTRY:%.*]] ]
+// NCRDIV-NEXT:    [[__R_0_I16_I_I:%.*]] = phi i64 [ [[__R_1_I22_I_I:%.*]], [[CLEANUP_I20_I_I]] ], [ 0, [[ENTRY]] ]
+// NCRDIV-NEXT:    [[TMP8:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I15_I_I]], align 1, !tbaa [[TBAA4]]
+// NCRDIV-NEXT:    [[CMP_NOT_I17_I_I:%.*]] = icmp eq i8 [[TMP8]], 0
+// NCRDIV-NEXT:    br i1 [[CMP_NOT_I17_I_I]], label [[_ZL4NANFPKC_EXIT]], label [[WHILE_BODY_I18_I_I:%.*]]
+// NCRDIV:       while.body.i18.i.i:
+// NCRDIV-NEXT:    [[TMP9:%.*]] = add i8 [[TMP8]], -48
+// NCRDIV-NEXT:    [[OR_COND_I19_I_I:%.*]] = icmp ult i8 [[TMP9]], 10
+// NCRDIV-NEXT:    br i1 [[OR_COND_I19_I_I]], label [[IF_THEN_I24_I_I:%.*]], label [[CLEANUP_I20_I_I]]
+// NCRDIV:       if.then.i24.i.i:
+// NCRDIV-NEXT:    [[MUL_I25_I_I:%.*]] = mul i64 [[__R_0_I16_I_I]], 10
+// NCRDIV-NEXT:    [[CONV5_I26_I_I:%.*]] = zext nneg i8 [[TMP8]] to i64
+// NCRDIV-NEXT:    [[ADD_I27_I_I:%.*]] = add i64 [[MUL_I25_I_I]], -48
+// NCRDIV-NEXT:    [[SUB_I28_I_I:%.*]] = add i64 [[ADD_I27_I_I]], [[CONV5_I26_I_I]]
+// NCRDIV-NEXT:    [[INCDEC_PTR_I29_I_I:%.*]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I15_I_I]], i64 1
+// NCRDIV-NEXT:    br label [[CLEANUP_I20_I_I]]
+// NCRDIV:       cleanup.i20.i.i:
+// NCRDIV-NEXT:    [[__TAGP_ADDR_1_I21_I_I]] = phi ptr [ [[INCDEC_PTR_I29_I_I]], [[IF_THEN_I24_I_I]] ], [ [[__TAGP_ADDR_0_I15_I_I]], [[WHILE_BODY_I18_I_I]] ]
+// NCRDIV-NEXT:    [[__R_1_I22_I_I]] = phi i64 [ [[SUB_I28_I_I]], [[IF_THEN_I24_I_I]] ], [ [[__R_0_I16_I_I]], [[WHILE_BODY_I18_I_I]] ]
+// NCRDIV-NEXT:    br i1 [[OR_COND_I19_I_I]], label [[WHILE_COND_I14_I_I]], label [[_ZL4NANFPKC_EXIT]], !llvm.loop [[LOOP10]]
+// NCRDIV:       _ZL4nanfPKc.exit:
+// NCRDIV-NEXT:    [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, [[CLEANUP_I_I_I]] ], [ [[__R_0_I_I_I]], [[WHILE_COND_I_I_I]] ], [ 0, [[CLEANUP_I36_I_I]] ], [ [[__R_0_I32_I_I]], [[WHILE_COND_I30_I_I]] ], [ 0, [[CLEANUP_I20_I_I]] ], [ [[__R_0_I16_I_I]], [[WHILE_COND_I14_I_I]] ]
+// NCRDIV-NEXT:    [[CONV_I:%.*]] = trunc i64 [[RETVAL_0_I_I]] to i32
+// NCRDIV-NEXT:    [[BF_VALUE_I:%.*]] = and i32 [[CONV_I]], 4194303
+// NCRDIV-NEXT:    [[BF_SET9_I:%.*]] = or disjoint i32 [[BF_VALUE_I]], 2143289344
+// NCRDIV-NEXT:    [[TMP10:%.*]] = bitcast i32 [[BF_SET9_I]] to float
+// NCRDIV-NEXT:    ret float [[TMP10]]
+//
 // AMDGCNSPIRV-LABEL: @test_nanf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = load i8, ptr addrspace(4) [[TAG:%.*]], align 1, !tbaa [[TBAA5]]
@@ -3650,6 +4339,100 @@ extern "C" __device__ float test_nanf(const char *tag) {
 // APPROX-NEXT:    [[TMP10:%.*]] = bitcast i64 [[BF_SET9_I]] to double
 // APPROX-NEXT:    ret double [[TMP10]]
 //
+// NCRDIV-LABEL: @test_nan(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = load i8, ptr [[TAG:%.*]], align 1, !tbaa [[TBAA4]]
+// NCRDIV-NEXT:    [[CMP_I_I:%.*]] = icmp eq i8 [[TMP0]], 48
+// NCRDIV-NEXT:    br i1 [[CMP_I_I]], label [[IF_THEN_I_I:%.*]], label [[WHILE_COND_I14_I_I:%.*]]
+// NCRDIV:       if.then.i.i:
+// NCRDIV-NEXT:    [[INCDEC_PTR_I_I:%.*]] = getelementptr inbounds nuw i8, ptr [[TAG]], i64 1
+// NCRDIV-NEXT:    [[TMP1:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[TBAA4]]
+// NCRDIV-NEXT:    switch i8 [[TMP1]], label [[WHILE_COND_I_I_I:%.*]] [
+// NCRDIV-NEXT:      i8 120, label [[WHILE_COND_I30_I_I_PREHEADER:%.*]]
+// NCRDIV-NEXT:      i8 88, label [[WHILE_COND_I30_I_I_PREHEADER]]
+// NCRDIV-NEXT:    ]
+// NCRDIV:       while.cond.i30.i.i.preheader:
+// NCRDIV-NEXT:    br label [[WHILE_COND_I30_I_I:%.*]]
+// NCRDIV:       while.cond.i30.i.i:
+// NCRDIV-NEXT:    [[__TAGP_ADDR_0_I31_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I37_I_I:%.*]], [[CLEANUP_I36_I_I:%.*]] ], [ [[INCDEC_PTR_I_I]], [[WHILE_COND_I30_I_I_PREHEADER]] ]
+// NCRDIV-NEXT:    [[__R_0_I32_I_I:%.*]] = phi i64 [ [[__R_2_I_I_I:%.*]], [[CLEANUP_I36_I_I]] ], [ 0, [[WHILE_COND_I30_I_I_PREHEADER]] ]
+// NCRDIV-NEXT:    [[TMP2:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I31_I_I]], align 1, !tbaa [[TBAA4]]
+// NCRDIV-NEXT:    [[CMP_NOT_I33_I_I:%.*]] = icmp eq i8 [[TMP2]], 0
+// NCRDIV-NEXT:    br i1 [[CMP_NOT_I33_I_I]], label [[_ZL3NANPKC_EXIT:%.*]], label [[WHILE_BODY_I34_I_I:%.*]]
+// NCRDIV:       while.body.i34.i.i:
+// NCRDIV-NEXT:    [[TMP3:%.*]] = add i8 [[TMP2]], -48
+// NCRDIV-NEXT:    [[OR_COND_I35_I_I:%.*]] = icmp ult i8 [[TMP3]], 10
+// NCRDIV-NEXT:    br i1 [[OR_COND_I35_I_I]], label [[IF_END31_I_I_I:%.*]], label [[IF_ELSE_I_I_I:%.*]]
+// NCRDIV:       if.else.i.i.i:
+// NCRDIV-NEXT:    [[TMP4:%.*]] = add i8 [[TMP2]], -97
+// NCRDIV-NEXT:    [[OR_COND33_I_I_I:%.*]] = icmp ult i8 [[TMP4]], 6
+// NCRDIV-NEXT:    br i1 [[OR_COND33_I_I_I]], label [[IF_END31_I_I_I]], label [[IF_ELSE17_I_I_I:%.*]]
+// NCRDIV:       if.else17.i.i.i:
+// NCRDIV-NEXT:    [[TMP5:%.*]] = add i8 [[TMP2]], -65
+// NCRDIV-NEXT:    [[OR_COND34_I_I_I:%.*]] = icmp ult i8 [[TMP5]], 6
+// NCRDIV-NEXT:    br i1 [[OR_COND34_I_I_I]], label [[IF_END31_I_I_I]], label [[CLEANUP_I36_I_I]]
+// NCRDIV:       if.end31.i.i.i:
+// NCRDIV-NEXT:    [[DOTSINK:%.*]] = phi i64 [ -48, [[WHILE_BODY_I34_I_I]] ], [ -87, [[IF_ELSE_I_I_I]] ], [ -55, [[IF_ELSE17_I_I_I]] ]
+// NCRDIV-NEXT:    [[MUL24_I_I_I:%.*]] = shl i64 [[__R_0_I32_I_I]], 4
+// NCRDIV-NEXT:    [[CONV25_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64
+// NCRDIV-NEXT:    [[ADD26_I_I_I:%.*]] = add i64 [[MUL24_I_I_I]], [[DOTSINK]]
+// NCRDIV-NEXT:    [[ADD28_I_I_I:%.*]] = add i64 [[ADD26_I_I_I]], [[CONV25_I_I_I]]
+// NCRDIV-NEXT:    [[INCDEC_PTR_I40_I_I:%.*]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I31_I_I]], i64 1
+// NCRDIV-NEXT:    br label [[CLEANUP_I36_I_I]]
+// NCRDIV:       cleanup.i36.i.i:
+// NCRDIV-NEXT:    [[__TAGP_ADDR_1_I37_I_I]] = phi ptr [ [[INCDEC_PTR_I40_I_I]], [[IF_END31_I_I_I]] ], [ [[__TAGP_ADDR_0_I31_I_I]], [[IF_ELSE17_I_I_I]] ]
+// NCRDIV-NEXT:    [[__R_2_I_I_I]] = phi i64 [ [[ADD28_I_I_I]], [[IF_END31_I_I_I]] ], [ [[__R_0_I32_I_I]], [[IF_ELSE17_I_I_I]] ]
+// NCRDIV-NEXT:    [[COND_I_I_I:%.*]] = phi i1 [ true, [[IF_END31_I_I_I]] ], [ false, [[IF_ELSE17_I_I_I]] ]
+// NCRDIV-NEXT:    br i1 [[COND_I_I_I]], label [[WHILE_COND_I30_I_I]], label [[_ZL3NANPKC_EXIT]], !llvm.loop [[LOOP11]]
+// NCRDIV:       while.cond.i.i.i:
+// NCRDIV-NEXT:    [[__TAGP_ADDR_0_I_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I_I_I:%.*]], [[CLEANUP_I_I_I:%.*]] ], [ [[INCDEC_PTR_I_I]], [[IF_THEN_I_I]] ]
+// NCRDIV-NEXT:    [[__R_0_I_I_I:%.*]] = phi i64 [ [[__R_1_I_I_I:%.*]], [[CLEANUP_I_I_I]] ], [ 0, [[IF_THEN_I_I]] ]
+// NCRDIV-NEXT:    [[TMP6:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I_I_I]], align 1, !tbaa [[TBAA4]]
+// NCRDIV-NEXT:    [[CMP_NOT_I_I_I:%.*]] = icmp eq i8 [[TMP6]], 0
+// NCRDIV-NEXT:    br i1 [[CMP_NOT_I_I_I]], label [[_ZL3NANPKC_EXIT]], label [[WHILE_BODY_I_I_I:%.*]]
+// NCRDIV:       while.body.i.i.i:
+// NCRDIV-NEXT:    [[TMP7:%.*]] = and i8 [[TMP6]], -8
+// NCRDIV-NEXT:    [[OR_COND_I_I_I:%.*]] = icmp eq i8 [[TMP7]], 48
+// NCRDIV-NEXT:    br i1 [[OR_COND_I_I_I]], label [[IF_THEN_I_I_I:%.*]], label [[CLEANUP_I_I_I]]
+// NCRDIV:       if.then.i.i.i:
+// NCRDIV-NEXT:    [[MUL_I_I_I:%.*]] = shl i64 [[__R_0_I_I_I]], 3
+// NCRDIV-NEXT:    [[CONV5_I_I_I:%.*]] = zext nneg i8 [[TMP6]] to i64
+// NCRDIV-NEXT:    [[ADD_I_I_I:%.*]] = add i64 [[MUL_I_I_I]], -48
+// NCRDIV-NEXT:    [[SUB_I_I_I:%.*]] = add i64 [[ADD_I_I_I]], [[CONV5_I_I_I]]
+// NCRDIV-NEXT:    [[INCDEC_PTR_I_I_I:%.*]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I_I_I]], i64 1
+// NCRDIV-NEXT:    br label [[CLEANUP_I_I_I]]
+// NCRDIV:       cleanup.i.i.i:
+// NCRDIV-NEXT:    [[__TAGP_ADDR_1_I_I_I]] = phi ptr [ [[INCDEC_PTR_I_I_I]], [[IF_THEN_I_I_I]] ], [ [[__TAGP_ADDR_0_I_I_I]], [[WHILE_BODY_I_I_I]] ]
+// NCRDIV-NEXT:    [[__R_1_I_I_I]] = phi i64 [ [[SUB_I_I_I]], [[IF_THEN_I_I_I]] ], [ [[__R_0_I_I_I]], [[WHILE_BODY_I_I_I]] ]
+// NCRDIV-NEXT:    br i1 [[OR_COND_I_I_I]], label [[WHILE_COND_I_I_I]], label [[_ZL3NANPKC_EXIT]], !llvm.loop [[LOOP7]]
+// NCRDIV:       while.cond.i14.i.i:
+// NCRDIV-NEXT:    [[__TAGP_ADDR_0_I15_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I21_I_I:%.*]], [[CLEANUP_I20_I_I:%.*]] ], [ [[TAG]], [[ENTRY:%.*]] ]
+// NCRDIV-NEXT:    [[__R_0_I16_I_I:%.*]] = phi i64 [ [[__R_1_I22_I_I:%.*]], [[CLEANUP_I20_I_I]] ], [ 0, [[ENTRY]] ]
+// NCRDIV-NEXT:    [[TMP8:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I15_I_I]], align 1, !tbaa [[TBAA4]]
+// NCRDIV-NEXT:    [[CMP_NOT_I17_I_I:%.*]] = icmp eq i8 [[TMP8]], 0
+// NCRDIV-NEXT:    br i1 [[CMP_NOT_I17_I_I]], label [[_ZL3NANPKC_EXIT]], label [[WHILE_BODY_I18_I_I:%.*]]
+// NCRDIV:       while.body.i18.i.i:
+// NCRDIV-NEXT:    [[TMP9:%.*]] = add i8 [[TMP8]], -48
+// NCRDIV-NEXT:    [[OR_COND_I19_I_I:%.*]] = icmp ult i8 [[TMP9]], 10
+// NCRDIV-NEXT:    br i1 [[OR_COND_I19_I_I]], label [[IF_THEN_I24_I_I:%.*]], label [[CLEANUP_I20_I_I]]
+// NCRDIV:       if.then.i24.i.i:
+// NCRDIV-NEXT:    [[MUL_I25_I_I:%.*]] = mul i64 [[__R_0_I16_I_I]], 10
+// NCRDIV-NEXT:    [[CONV5_I26_I_I:%.*]] = zext nneg i8 [[TMP8]] to i64
+// NCRDIV-NEXT:    [[ADD_I27_I_I:%.*]] = add i64 [[MUL_I25_I_I]], -48
+// NCRDIV-NEXT:    [[SUB_I28_I_I:%.*]] = add i64 [[ADD_I27_I_I]], [[CONV5_I26_I_I]]
+// NCRDIV-NEXT:    [[INCDEC_PTR_I29_I_I:%.*]] = getelementptr inbounds nuw i8, ptr [[__TAGP_ADDR_0_I15_I_I]], i64 1
+// NCRDIV-NEXT:    br label [[CLEANUP_I20_I_I]]
+// NCRDIV:       cleanup.i20.i.i:
+// NCRDIV-NEXT:    [[__TAGP_ADDR_1_I21_I_I]] = phi ptr [ [[INCDEC_PTR_I29_I_I]], [[IF_THEN_I24_I_I]] ], [ [[__TAGP_ADDR_0_I15_I_I]], [[WHILE_BODY_I18_I_I]] ]
+// NCRDIV-NEXT:    [[__R_1_I22_I_I]] = phi i64 [ [[SUB_I28_I_I]], [[IF_THEN_I24_I_I]] ], [ [[__R_0_I16_I_I]], [[WHILE_BODY_I18_I_I]] ]
+// NCRDIV-NEXT:    br i1 [[OR_COND_I19_I_I]], label [[WHILE_COND_I14_I_I]], label [[_ZL3NANPKC_EXIT]], !llvm.loop [[LOOP10]]
+// NCRDIV:       _ZL3nanPKc.exit:
+// NCRDIV-NEXT:    [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, [[CLEANUP_I_I_I]] ], [ [[__R_0_I_I_I]], [[WHILE_COND_I_I_I]] ], [ 0, [[CLEANUP_I36_I_I]] ], [ [[__R_0_I32_I_I]], [[WHILE_COND_I30_I_I]] ], [ 0, [[CLEANUP_I20_I_I]] ], [ [[__R_0_I16_I_I]], [[WHILE_COND_I14_I_I]] ]
+// NCRDIV-NEXT:    [[BF_VALUE_I:%.*]] = and i64 [[RETVAL_0_I_I]], 2251799813685247
+// NCRDIV-NEXT:    [[BF_SET9_I:%.*]] = or disjoint i64 [[BF_VALUE_I]], 9221120237041090560
+// NCRDIV-NEXT:    [[TMP10:%.*]] = bitcast i64 [[BF_SET9_I]] to double
+// NCRDIV-NEXT:    ret double [[TMP10]]
+//
 // AMDGCNSPIRV-LABEL: @test_nan(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = load i8, ptr addrspace(4) [[TAG:%.*]], align 1, !tbaa [[TBAA5]]
@@ -3752,6 +4535,10 @@ extern "C" __device__ double test_nan(const char *tag) {
 // APPROX-NEXT:  entry:
 // APPROX-NEXT:    ret float 0x7FF8000000000000
 //
+// NCRDIV-LABEL: @test_nanf_emptystr(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    ret float 0x7FF8000000000000
+//
 // AMDGCNSPIRV-LABEL: @test_nanf_emptystr(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    ret float 0x7FF8000000000000
@@ -3772,6 +4559,10 @@ extern "C" __device__ float test_nanf_emptystr() {
 // APPROX-NEXT:  entry:
 // APPROX-NEXT:    ret double 0x7FF8000000000000
 //
+// NCRDIV-LABEL: @test_nan_emptystr(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    ret double 0x7FF8000000000000
+//
 // AMDGCNSPIRV-LABEL: @test_nan_emptystr(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    ret double 0x7FF8000000000000
@@ -3792,6 +4583,10 @@ extern "C" __device__ double test_nan_emptystr() {
 // APPROX-NEXT:  entry:
 // APPROX-NEXT:    ret float 0x7FF8000000000000
 //
+// NCRDIV-LABEL: @test_nanf_fill(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    ret float 0x7FF8000000000000
+//
 // AMDGCNSPIRV-LABEL: @test_nanf_fill(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    ret float 0x7FF8000000000000
@@ -3812,6 +4607,10 @@ extern "C" __device__ float test_nanf_fill() {
 // APPROX-NEXT:  entry:
 // APPROX-NEXT:    ret double 0x7FF8000000000000
 //
+// NCRDIV-LABEL: @test_nan_fill(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    ret double 0x7FF8000000000000
+//
 // AMDGCNSPIRV-LABEL: @test_nan_fill(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    ret double 0x7FF8000000000000
@@ -3835,6 +4634,11 @@ extern "C" __device__ double test_nan_fill() {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.nearbyint.f32(float [[X:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test_nearbyintf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.nearbyint.f32(float [[X:%.*]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_nearbyintf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.nearbyint.f32(float [[X:%.*]])
@@ -3859,6 +4663,11 @@ extern "C" __device__ float test_nearbyintf(float x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.nearbyint.f64(double [[X:%.*]])
 // APPROX-NEXT:    ret double [[TMP0]]
 //
+// NCRDIV-LABEL: @test_nearbyint(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.nearbyint.f64(double [[X:%.*]])
+// NCRDIV-NEXT:    ret double [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_nearbyint(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) double @llvm.nearbyint.f64(double [[X:%.*]])
@@ -3883,6 +4692,11 @@ extern "C" __device__ double test_nearbyint(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_nextafter_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_nextafterf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_nextafter_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_nextafterf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_nextafter_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR12]]
@@ -3907,6 +4721,11 @@ extern "C" __device__ float test_nextafterf(float x, float y) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_nextafter_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_nextafter(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_nextafter_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_nextafter(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_nextafter_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]]) #[[ATTR12]]
@@ -3931,6 +4750,11 @@ extern "C" __device__ double test_nextafter(double x, double y) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_len3_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]], float noundef [[Z:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_norm3df(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_len3_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]], float noundef [[Z:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_norm3df(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_len3_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]], float noundef [[Z:%.*]]) #[[ATTR12]]
@@ -3955,6 +4779,11 @@ extern "C" __device__ float test_norm3df(float x, float y, float z) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_len3_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]], double noundef [[Z:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_norm3d(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_len3_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]], double noundef [[Z:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_norm3d(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_len3_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]], double noundef [[Z:%.*]]) #[[ATTR12]]
@@ -3979,6 +4808,11 @@ extern "C" __device__ double test_norm3d(double x, double y, double z) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_len4_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]], float noundef [[Z:%.*]], float noundef [[W:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_norm4df(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_len4_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]], float noundef [[Z:%.*]], float noundef [[W:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_norm4df(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_len4_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]], float noundef [[Z:%.*]], float noundef [[W:%.*]]) #[[ATTR12]]
@@ -4003,6 +4837,11 @@ extern "C" __device__ float test_norm4df(float x, float y, float z, float w) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_len4_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]], double noundef [[Z:%.*]], double noundef [[W:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_norm4d(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_len4_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]], double noundef [[Z:%.*]], double noundef [[W:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_norm4d(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_len4_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]], double noundef [[Z:%.*]], double noundef [[W:%.*]]) #[[ATTR12]]
@@ -4027,6 +4866,11 @@ extern "C" __device__ double test_norm4d(double x, double y, double z, double w)
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_ncdf_f32(float noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_normcdff(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_ncdf_f32(float noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_normcdff(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_ncdf_f32(float noundef [[X:%.*]]) #[[ATTR13]]
@@ -4051,6 +4895,11 @@ extern "C" __device__ float test_normcdff(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_ncdf_f64(double noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_normcdf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_ncdf_f64(double noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_normcdf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_ncdf_f64(double noundef [[X:%.*]]) #[[ATTR13]]
@@ -4075,6 +4924,11 @@ extern "C" __device__ double test_normcdf(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_ncdfinv_f32(float noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_normcdfinvf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_ncdfinv_f32(float noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_normcdfinvf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_ncdfinv_f32(float noundef [[X:%.*]]) #[[ATTR13]]
@@ -4099,6 +4953,11 @@ extern "C" __device__ float test_normcdfinvf(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_ncdfinv_f64(double noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_normcdfinv(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_ncdfinv_f64(double noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_normcdfinv(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_ncdfinv_f64(double noundef [[X:%.*]]) #[[ATTR13]]
@@ -4168,6 +5027,26 @@ extern "C" __device__ double test_normcdfinv(double x) {
 // APPROX-NEXT:    [[TMP1:%.*]] = tail call contract noundef float @llvm.sqrt.f32(float [[__R_0_I_LCSSA]])
 // APPROX-NEXT:    ret float [[TMP1]]
 //
+// NCRDIV-LABEL: @test_normf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X:%.*]], 0
+// NCRDIV-NEXT:    br i1 [[TOBOOL_NOT_I1]], label [[_ZL5NORMFIPKF_EXIT:%.*]], label [[WHILE_BODY_I:%.*]]
+// NCRDIV:       while.body.i:
+// NCRDIV-NEXT:    [[__R_0_I4:%.*]] = phi float [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
+// NCRDIV-NEXT:    [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ]
+// NCRDIV-NEXT:    [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ]
+// NCRDIV-NEXT:    [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1
+// NCRDIV-NEXT:    [[TMP0:%.*]] = load float, ptr [[__A_ADDR_0_I3]], align 4, !tbaa [[TBAA17]]
+// NCRDIV-NEXT:    [[MUL_I:%.*]] = fmul contract float [[TMP0]], [[TMP0]]
+// NCRDIV-NEXT:    [[ADD_I]] = fadd contract float [[__R_0_I4]], [[MUL_I]]
+// NCRDIV-NEXT:    [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_0_I3]], i64 4
+// NCRDIV-NEXT:    [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0
+// NCRDIV-NEXT:    br i1 [[TOBOOL_NOT_I]], label [[_ZL5NORMFIPKF_EXIT]], label [[WHILE_BODY_I]], !llvm.loop [[LOOP21:![0-9]+]]
+// NCRDIV:       _ZL5normfiPKf.exit:
+// NCRDIV-NEXT:    [[__R_0_I_LCSSA:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ]
+// NCRDIV-NEXT:    [[TMP1:%.*]] = tail call contract noundef float @llvm.sqrt.f32(float [[__R_0_I_LCSSA]]), !fpmath [[META22:![0-9]+]]
+// NCRDIV-NEXT:    ret float [[TMP1]]
+//
 // AMDGCNSPIRV-LABEL: @test_normf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X:%.*]], 0
@@ -4252,6 +5131,26 @@ extern "C" __device__ float test_normf(int x, const float *y) {
 // APPROX-NEXT:    [[TMP1:%.*]] = tail call contract noundef double @llvm.sqrt.f64(double [[__R_0_I_LCSSA]])
 // APPROX-NEXT:    ret double [[TMP1]]
 //
+// NCRDIV-LABEL: @test_norm(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X:%.*]], 0
+// NCRDIV-NEXT:    br i1 [[TOBOOL_NOT_I1]], label [[_ZL4NORMIPKD_EXIT:%.*]], label [[WHILE_BODY_I:%.*]]
+// NCRDIV:       while.body.i:
+// NCRDIV-NEXT:    [[__R_0_I4:%.*]] = phi double [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
+// NCRDIV-NEXT:    [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ]
+// NCRDIV-NEXT:    [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ]
+// NCRDIV-NEXT:    [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1
+// NCRDIV-NEXT:    [[TMP0:%.*]] = load double, ptr [[__A_ADDR_0_I3]], align 8, !tbaa [[TBAA19]]
+// NCRDIV-NEXT:    [[MUL_I:%.*]] = fmul contract double [[TMP0]], [[TMP0]]
+// NCRDIV-NEXT:    [[ADD_I]] = fadd contract double [[__R_0_I4]], [[MUL_I]]
+// NCRDIV-NEXT:    [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_0_I3]], i64 8
+// NCRDIV-NEXT:    [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0
+// NCRDIV-NEXT:    br i1 [[TOBOOL_NOT_I]], label [[_ZL4NORMIPKD_EXIT]], label [[WHILE_BODY_I]], !llvm.loop [[LOOP23:![0-9]+]]
+// NCRDIV:       _ZL4normiPKd.exit:
+// NCRDIV-NEXT:    [[__R_0_I_LCSSA:%.*]] = phi double [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ]
+// NCRDIV-NEXT:    [[TMP1:%.*]] = tail call contract noundef double @llvm.sqrt.f64(double [[__R_0_I_LCSSA]])
+// NCRDIV-NEXT:    ret double [[TMP1]]
+//
 // AMDGCNSPIRV-LABEL: @test_norm(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X:%.*]], 0
@@ -4291,6 +5190,11 @@ extern "C" __device__ double test_norm(int x, const double *y) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_pow_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_powf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_pow_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_powf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_pow_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR13]]
@@ -4315,6 +5219,11 @@ extern "C" __device__ float test_powf(float x, float y) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_pow_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_pow(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_pow_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_pow(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_pow_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]]) #[[ATTR13]]
@@ -4339,6 +5248,11 @@ extern "C" __device__ double test_pow(double x, double y) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_pown_f32(float noundef [[X:%.*]], i32 noundef [[Y:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_powif(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_pown_f32(float noundef [[X:%.*]], i32 noundef [[Y:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_powif(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_pown_f32(float noundef [[X:%.*]], i32 noundef [[Y:%.*]]) #[[ATTR13]]
@@ -4363,6 +5277,11 @@ extern "C" __device__ float test_powif(float x, int y) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_pown_f64(double noundef [[X:%.*]], i32 noundef [[Y:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_powi(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_pown_f64(double noundef [[X:%.*]], i32 noundef [[Y:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_powi(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_pown_f64(double noundef [[X:%.*]], i32 noundef [[Y:%.*]]) #[[ATTR13]]
@@ -4387,6 +5306,11 @@ extern "C" __device__ double test_powi(double x, int y) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_rcbrt_f32(float noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_rcbrtf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_rcbrt_f32(float noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_rcbrtf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_rcbrt_f32(float noundef [[X:%.*]]) #[[ATTR13]]
@@ -4411,6 +5335,11 @@ extern "C" __device__ float test_rcbrtf(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_rcbrt_f64(double noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_rcbrt(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_rcbrt_f64(double noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_rcbrt(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_rcbrt_f64(double noundef [[X:%.*]]) #[[ATTR13]]
@@ -4435,6 +5364,11 @@ extern "C" __device__ double test_rcbrt(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_remainder_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_remainderf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_remainder_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_remainderf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_remainder_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR12]]
@@ -4459,6 +5393,11 @@ extern "C" __device__ float test_remainderf(float x, float y) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_remainder_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_remainder(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_remainder_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_remainder(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_remainder_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]]) #[[ATTR12]]
@@ -4498,6 +5437,16 @@ extern "C" __device__ double test_remainder(double x, double y) {
 // APPROX-NEXT:    call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[__TMP_I]]) #[[ATTR15]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_remquof(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[__TMP_I:%.*]] = alloca i32, align 4, addrspace(5)
+// NCRDIV-NEXT:    call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[__TMP_I]]) #[[ATTR15]]
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = call contract noundef float @__ocml_remquo_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]], ptr addrspace(5) noundef [[__TMP_I]]) #[[ATTR14]]
+// NCRDIV-NEXT:    [[TMP0:%.*]] = load i32, ptr addrspace(5) [[__TMP_I]], align 4, !tbaa [[TBAA13]]
+// NCRDIV-NEXT:    store i32 [[TMP0]], ptr [[Z:%.*]], align 4, !tbaa [[TBAA13]]
+// NCRDIV-NEXT:    call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[__TMP_I]]) #[[ATTR15]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_remquof(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[__TMP_I:%.*]] = alloca i32, align 4
@@ -4543,6 +5492,16 @@ extern "C" __device__ float test_remquof(float x, float y, int* z) {
 // APPROX-NEXT:    call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[__TMP_I]]) #[[ATTR15]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_remquo(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[__TMP_I:%.*]] = alloca i32, align 4, addrspace(5)
+// NCRDIV-NEXT:    call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[__TMP_I]]) #[[ATTR15]]
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = call contract noundef double @__ocml_remquo_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]], ptr addrspace(5) noundef [[__TMP_I]]) #[[ATTR14]]
+// NCRDIV-NEXT:    [[TMP0:%.*]] = load i32, ptr addrspace(5) [[__TMP_I]], align 4, !tbaa [[TBAA13]]
+// NCRDIV-NEXT:    store i32 [[TMP0]], ptr [[Z:%.*]], align 4, !tbaa [[TBAA13]]
+// NCRDIV-NEXT:    call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[__TMP_I]]) #[[ATTR15]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_remquo(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[__TMP_I:%.*]] = alloca i32, align 4
@@ -4573,6 +5532,11 @@ extern "C" __device__ double test_remquo(double x, double y, int* z) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_rhypot_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_rhypotf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_rhypot_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_rhypotf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_rhypot_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR12]]
@@ -4597,6 +5561,11 @@ extern "C" __device__ float test_rhypotf(float x, float y) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_rhypot_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_rhypot(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_rhypot_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_rhypot(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_rhypot_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]]) #[[ATTR12]]
@@ -4621,6 +5590,11 @@ extern "C" __device__ double test_rhypot(double x, double y) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.rint.f32(float [[X:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test_rintf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.rint.f32(float [[X:%.*]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_rintf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.rint.f32(float [[X:%.*]])
@@ -4645,6 +5619,11 @@ extern "C" __device__ float test_rintf(float x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.rint.f64(double [[X:%.*]])
 // APPROX-NEXT:    ret double [[TMP0]]
 //
+// NCRDIV-LABEL: @test_rint(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.rint.f64(double [[X:%.*]])
+// NCRDIV-NEXT:    ret double [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_rint(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) double @llvm.rint.f64(double [[X:%.*]])
@@ -4714,6 +5693,26 @@ extern "C" __device__ double test_rint(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_rsqrt_f32(float noundef [[__R_0_I_LCSSA]]) #[[ATTR13]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_rnormf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X:%.*]], 0
+// NCRDIV-NEXT:    br i1 [[TOBOOL_NOT_I1]], label [[_ZL6RNORMFIPKF_EXIT:%.*]], label [[WHILE_BODY_I:%.*]]
+// NCRDIV:       while.body.i:
+// NCRDIV-NEXT:    [[__R_0_I4:%.*]] = phi float [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
+// NCRDIV-NEXT:    [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ]
+// NCRDIV-NEXT:    [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ]
+// NCRDIV-NEXT:    [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1
+// NCRDIV-NEXT:    [[TMP0:%.*]] = load float, ptr [[__A_ADDR_0_I3]], align 4, !tbaa [[TBAA17]]
+// NCRDIV-NEXT:    [[MUL_I:%.*]] = fmul contract float [[TMP0]], [[TMP0]]
+// NCRDIV-NEXT:    [[ADD_I]] = fadd contract float [[__R_0_I4]], [[MUL_I]]
+// NCRDIV-NEXT:    [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_0_I3]], i64 4
+// NCRDIV-NEXT:    [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0
+// NCRDIV-NEXT:    br i1 [[TOBOOL_NOT_I]], label [[_ZL6RNORMFIPKF_EXIT]], label [[WHILE_BODY_I]], !llvm.loop [[LOOP24:![0-9]+]]
+// NCRDIV:       _ZL6rnormfiPKf.exit:
+// NCRDIV-NEXT:    [[__R_0_I_LCSSA:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ]
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_rsqrt_f32(float noundef [[__R_0_I_LCSSA]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_rnormf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X:%.*]], 0
@@ -4798,6 +5797,26 @@ extern "C" __device__ float test_rnormf(int x, const float* y) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_rsqrt_f64(double noundef [[__R_0_I_LCSSA]]) #[[ATTR13]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_rnorm(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X:%.*]], 0
+// NCRDIV-NEXT:    br i1 [[TOBOOL_NOT_I1]], label [[_ZL5RNORMIPKD_EXIT:%.*]], label [[WHILE_BODY_I:%.*]]
+// NCRDIV:       while.body.i:
+// NCRDIV-NEXT:    [[__R_0_I4:%.*]] = phi double [ [[ADD_I:%.*]], [[WHILE_BODY_I]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
+// NCRDIV-NEXT:    [[__A_ADDR_0_I3:%.*]] = phi ptr [ [[INCDEC_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[Y:%.*]], [[ENTRY]] ]
+// NCRDIV-NEXT:    [[__DIM_ADDR_0_I2:%.*]] = phi i32 [ [[DEC_I:%.*]], [[WHILE_BODY_I]] ], [ [[X]], [[ENTRY]] ]
+// NCRDIV-NEXT:    [[DEC_I]] = add nsw i32 [[__DIM_ADDR_0_I2]], -1
+// NCRDIV-NEXT:    [[TMP0:%.*]] = load double, ptr [[__A_ADDR_0_I3]], align 8, !tbaa [[TBAA19]]
+// NCRDIV-NEXT:    [[MUL_I:%.*]] = fmul contract double [[TMP0]], [[TMP0]]
+// NCRDIV-NEXT:    [[ADD_I]] = fadd contract double [[__R_0_I4]], [[MUL_I]]
+// NCRDIV-NEXT:    [[INCDEC_PTR_I]] = getelementptr inbounds nuw i8, ptr [[__A_ADDR_0_I3]], i64 8
+// NCRDIV-NEXT:    [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0
+// NCRDIV-NEXT:    br i1 [[TOBOOL_NOT_I]], label [[_ZL5RNORMIPKD_EXIT]], label [[WHILE_BODY_I]], !llvm.loop [[LOOP25:![0-9]+]]
+// NCRDIV:       _ZL5rnormiPKd.exit:
+// NCRDIV-NEXT:    [[__R_0_I_LCSSA:%.*]] = phi double [ 0.000000e+00, [[ENTRY]] ], [ [[ADD_I]], [[WHILE_BODY_I]] ]
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_rsqrt_f64(double noundef [[__R_0_I_LCSSA]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_rnorm(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TOBOOL_NOT_I1:%.*]] = icmp eq i32 [[X:%.*]], 0
@@ -4837,6 +5856,11 @@ extern "C" __device__ double test_rnorm(int x, const double* y) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_rlen3_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]], float noundef [[Z:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_rnorm3df(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_rlen3_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]], float noundef [[Z:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_rnorm3df(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_rlen3_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]], float noundef [[Z:%.*]]) #[[ATTR12]]
@@ -4861,6 +5885,11 @@ extern "C" __device__ float test_rnorm3df(float x, float y, float z) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_rlen3_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]], double noundef [[Z:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_rnorm3d(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_rlen3_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]], double noundef [[Z:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_rnorm3d(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_rlen3_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]], double noundef [[Z:%.*]]) #[[ATTR12]]
@@ -4885,6 +5914,11 @@ extern "C" __device__ double test_rnorm3d(double x, double y, double z) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_rlen4_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]], float noundef [[Z:%.*]], float noundef [[W:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_rnorm4df(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_rlen4_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]], float noundef [[Z:%.*]], float noundef [[W:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_rnorm4df(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_rlen4_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]], float noundef [[Z:%.*]], float noundef [[W:%.*]]) #[[ATTR12]]
@@ -4909,6 +5943,11 @@ extern "C" __device__ float test_rnorm4df(float x, float y, float z, float w) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_rlen4_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]], double noundef [[Z:%.*]], double noundef [[W:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_rnorm4d(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_rlen4_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]], double noundef [[Z:%.*]], double noundef [[W:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_rnorm4d(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_rlen4_f64(double noundef [[X:%.*]], double noundef [[Y:%.*]], double noundef [[Z:%.*]], double noundef [[W:%.*]]) #[[ATTR12]]
@@ -4933,6 +5972,11 @@ extern "C" __device__ double test_rnorm4d(double x, double y, double z, double w
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.round.f32(float [[X:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test_roundf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.round.f32(float [[X:%.*]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_roundf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.round.f32(float [[X:%.*]])
@@ -4957,6 +6001,11 @@ extern "C" __device__ float test_roundf(float x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.round.f64(double [[X:%.*]])
 // APPROX-NEXT:    ret double [[TMP0]]
 //
+// NCRDIV-LABEL: @test_round(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.round.f64(double [[X:%.*]])
+// NCRDIV-NEXT:    ret double [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_round(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) double @llvm.round.f64(double [[X:%.*]])
@@ -4981,6 +6030,11 @@ extern "C" __device__ double test_round(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_rsqrt_f32(float noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_rsqrtf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_rsqrt_f32(float noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_rsqrtf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_rsqrt_f32(float noundef [[X:%.*]]) #[[ATTR13]]
@@ -5005,6 +6059,11 @@ extern "C" __device__ float test_rsqrtf(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_rsqrt_f64(double noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_rsqrt(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_rsqrt_f64(double noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_rsqrt(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_rsqrt_f64(double noundef [[X:%.*]]) #[[ATTR13]]
@@ -5035,6 +6094,13 @@ extern "C" __device__ double test_rsqrt(double x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.ldexp.f32.i32(float [[X:%.*]], i32 [[CONV_I]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test_scalblnf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[SPEC_STORE_SELECT_I:%.*]] = tail call i64 @llvm.smax.i64(i64 [[Y:%.*]], i64 -2147483648)
+// NCRDIV-NEXT:    [[CONV_I:%.*]] = trunc i64 [[SPEC_STORE_SELECT_I]] to i32
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.ldexp.f32.i32(float [[X:%.*]], i32 [[CONV_I]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_scalblnf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[SPEC_STORE_SELECT_I:%.*]] = tail call addrspace(4) i64 @llvm.smax.i64(i64 [[Y:%.*]], i64 -2147483648)
@@ -5067,6 +6133,13 @@ extern "C" __device__ float test_scalblnf(float x, long int y) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.ldexp.f64.i32(double [[X:%.*]], i32 [[CONV_I]])
 // APPROX-NEXT:    ret double [[TMP0]]
 //
+// NCRDIV-LABEL: @test_scalbln(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[SPEC_STORE_SELECT_I:%.*]] = tail call i64 @llvm.smax.i64(i64 [[Y:%.*]], i64 -2147483648)
+// NCRDIV-NEXT:    [[CONV_I:%.*]] = trunc i64 [[SPEC_STORE_SELECT_I]] to i32
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.ldexp.f64.i32(double [[X:%.*]], i32 [[CONV_I]])
+// NCRDIV-NEXT:    ret double [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_scalbln(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[SPEC_STORE_SELECT_I:%.*]] = tail call addrspace(4) i64 @llvm.smax.i64(i64 [[Y:%.*]], i64 -2147483648)
@@ -5093,6 +6166,11 @@ extern "C" __device__ double test_scalbln(double x, long int y) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.ldexp.f32.i32(float [[X:%.*]], i32 [[Y:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test_scalbnf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.ldexp.f32.i32(float [[X:%.*]], i32 [[Y:%.*]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_scalbnf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.ldexp.f32.i32(float [[X:%.*]], i32 [[Y:%.*]])
@@ -5117,6 +6195,11 @@ extern "C" __device__ float test_scalbnf(float x, int y) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.ldexp.f64.i32(double [[X:%.*]], i32 [[Y:%.*]])
 // APPROX-NEXT:    ret double [[TMP0]]
 //
+// NCRDIV-LABEL: @test_scalbn(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.ldexp.f64.i32(double [[X:%.*]], i32 [[Y:%.*]])
+// NCRDIV-NEXT:    ret double [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_scalbn(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) double @llvm.ldexp.f64.i32(double [[X:%.*]], i32 [[Y:%.*]])
@@ -5193,6 +6276,17 @@ extern "C" __device__ BOOL_TYPE test___signbit(double x) {
 // APPROX-NEXT:    call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[__TMP_I]]) #[[ATTR15]]
 // APPROX-NEXT:    ret void
 //
+// NCRDIV-LABEL: @test_sincosf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[__TMP_I:%.*]] = alloca float, align 4, addrspace(5)
+// NCRDIV-NEXT:    call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[__TMP_I]]) #[[ATTR15]]
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = call contract float @__ocml_sincos_f32(float noundef [[X:%.*]], ptr addrspace(5) noundef [[__TMP_I]]) #[[ATTR14]]
+// NCRDIV-NEXT:    store float [[CALL_I]], ptr [[Y:%.*]], align 4, !tbaa [[TBAA17]]
+// NCRDIV-NEXT:    [[TMP0:%.*]] = load float, ptr addrspace(5) [[__TMP_I]], align 4, !tbaa [[TBAA17]]
+// NCRDIV-NEXT:    store float [[TMP0]], ptr [[Z:%.*]], align 4, !tbaa [[TBAA17]]
+// NCRDIV-NEXT:    call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[__TMP_I]]) #[[ATTR15]]
+// NCRDIV-NEXT:    ret void
+//
 // AMDGCNSPIRV-LABEL: @test_sincosf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[__TMP_I:%.*]] = alloca float, align 4
@@ -5242,6 +6336,17 @@ extern "C" __device__ void test_sincosf(float x, float *y, float *z) {
 // APPROX-NEXT:    call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[__TMP_I]]) #[[ATTR15]]
 // APPROX-NEXT:    ret void
 //
+// NCRDIV-LABEL: @test_sincos(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[__TMP_I:%.*]] = alloca double, align 8, addrspace(5)
+// NCRDIV-NEXT:    call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[__TMP_I]]) #[[ATTR15]]
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = call contract double @__ocml_sincos_f64(double noundef [[X:%.*]], ptr addrspace(5) noundef [[__TMP_I]]) #[[ATTR14]]
+// NCRDIV-NEXT:    store double [[CALL_I]], ptr [[Y:%.*]], align 8, !tbaa [[TBAA19]]
+// NCRDIV-NEXT:    [[TMP0:%.*]] = load double, ptr addrspace(5) [[__TMP_I]], align 8, !tbaa [[TBAA19]]
+// NCRDIV-NEXT:    store double [[TMP0]], ptr [[Z:%.*]], align 8, !tbaa [[TBAA19]]
+// NCRDIV-NEXT:    call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[__TMP_I]]) #[[ATTR15]]
+// NCRDIV-NEXT:    ret void
+//
 // AMDGCNSPIRV-LABEL: @test_sincos(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[__TMP_I:%.*]] = alloca double, align 8
@@ -5291,6 +6396,17 @@ extern "C" __device__ void test_sincos(double x, double *y, double *z) {
 // APPROX-NEXT:    call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[__TMP_I]]) #[[ATTR15]]
 // APPROX-NEXT:    ret void
 //
+// NCRDIV-LABEL: @test_sincospif(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[__TMP_I:%.*]] = alloca float, align 4, addrspace(5)
+// NCRDIV-NEXT:    call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[__TMP_I]]) #[[ATTR15]]
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = call contract float @__ocml_sincospi_f32(float noundef [[X:%.*]], ptr addrspace(5) noundef [[__TMP_I]]) #[[ATTR14]]
+// NCRDIV-NEXT:    store float [[CALL_I]], ptr [[Y:%.*]], align 4, !tbaa [[TBAA17]]
+// NCRDIV-NEXT:    [[TMP0:%.*]] = load float, ptr addrspace(5) [[__TMP_I]], align 4, !tbaa [[TBAA17]]
+// NCRDIV-NEXT:    store float [[TMP0]], ptr [[Z:%.*]], align 4, !tbaa [[TBAA17]]
+// NCRDIV-NEXT:    call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[__TMP_I]]) #[[ATTR15]]
+// NCRDIV-NEXT:    ret void
+//
 // AMDGCNSPIRV-LABEL: @test_sincospif(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[__TMP_I:%.*]] = alloca float, align 4
@@ -5340,6 +6456,17 @@ extern "C" __device__ void test_sincospif(float x, float *y, float *z) {
 // APPROX-NEXT:    call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[__TMP_I]]) #[[ATTR15]]
 // APPROX-NEXT:    ret void
 //
+// NCRDIV-LABEL: @test_sincospi(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[__TMP_I:%.*]] = alloca double, align 8, addrspace(5)
+// NCRDIV-NEXT:    call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[__TMP_I]]) #[[ATTR15]]
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = call contract double @__ocml_sincospi_f64(double noundef [[X:%.*]], ptr addrspace(5) noundef [[__TMP_I]]) #[[ATTR14]]
+// NCRDIV-NEXT:    store double [[CALL_I]], ptr [[Y:%.*]], align 8, !tbaa [[TBAA19]]
+// NCRDIV-NEXT:    [[TMP0:%.*]] = load double, ptr addrspace(5) [[__TMP_I]], align 8, !tbaa [[TBAA19]]
+// NCRDIV-NEXT:    store double [[TMP0]], ptr [[Z:%.*]], align 8, !tbaa [[TBAA19]]
+// NCRDIV-NEXT:    call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[__TMP_I]]) #[[ATTR15]]
+// NCRDIV-NEXT:    ret void
+//
 // AMDGCNSPIRV-LABEL: @test_sincospi(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[__TMP_I:%.*]] = alloca double, align 8
@@ -5371,6 +6498,11 @@ extern "C" __device__ void test_sincospi(double x, double *y, double *z) {
 // APPROX-NEXT:    [[CALL_I1:%.*]] = tail call contract noundef float @__ocml_native_sin_f32(float noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret float [[CALL_I1]]
 //
+// NCRDIV-LABEL: @test_sinf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_sin_f32(float noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_sinf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_sin_f32(float noundef [[X:%.*]]) #[[ATTR14]]
@@ -5395,6 +6527,11 @@ extern "C" __device__ float test_sinf(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_sin_f64(double noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_sin(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_sin_f64(double noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_sin(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_sin_f64(double noundef [[X:%.*]]) #[[ATTR14]]
@@ -5419,6 +6556,11 @@ extern "C" __device__ double test_sin(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_sinpi_f32(float noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_sinpif(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_sinpi_f32(float noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_sinpif(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_sinpi_f32(float noundef [[X:%.*]]) #[[ATTR14]]
@@ -5443,6 +6585,11 @@ extern "C" __device__ float test_sinpif(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_sinpi_f64(double noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_sinpi(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_sinpi_f64(double noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_sinpi(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_sinpi_f64(double noundef [[X:%.*]]) #[[ATTR14]]
@@ -5467,6 +6614,11 @@ extern "C" __device__ double test_sinpi(double x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.sqrt.f32(float [[X:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test_sqrtf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.sqrt.f32(float [[X:%.*]]), !fpmath [[META22]]
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_sqrtf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.sqrt.f32(float [[X:%.*]])
@@ -5491,6 +6643,11 @@ extern "C" __device__ float test_sqrtf(float x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.sqrt.f64(double [[X:%.*]])
 // APPROX-NEXT:    ret double [[TMP0]]
 //
+// NCRDIV-LABEL: @test_sqrt(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.sqrt.f64(double [[X:%.*]])
+// NCRDIV-NEXT:    ret double [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_sqrt(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) double @llvm.sqrt.f64(double [[X:%.*]])
@@ -5515,6 +6672,11 @@ extern "C" __device__ double test_sqrt(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_tan_f32(float noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_tanf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_tan_f32(float noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_tanf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_tan_f32(float noundef [[X:%.*]]) #[[ATTR14]]
@@ -5539,6 +6701,11 @@ extern "C" __device__ float test_tanf(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_tan_f64(double noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_tan(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_tan_f64(double noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_tan(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_tan_f64(double noundef [[X:%.*]]) #[[ATTR14]]
@@ -5563,6 +6730,11 @@ extern "C" __device__ double test_tan(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_tanh_f32(float noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_tanhf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_tanh_f32(float noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_tanhf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_tanh_f32(float noundef [[X:%.*]]) #[[ATTR13]]
@@ -5587,6 +6759,11 @@ extern "C" __device__ float test_tanhf(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_tanh_f64(double noundef [[X:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_tanh(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_tanh_f64(double noundef [[X:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_tanh(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_tanh_f64(double noundef [[X:%.*]]) #[[ATTR13]]
@@ -5611,6 +6788,11 @@ extern "C" __device__ double test_tanh(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_tgamma_f32(float noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_tgammaf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_tgamma_f32(float noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_tgammaf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_tgamma_f32(float noundef [[X:%.*]]) #[[ATTR14]]
@@ -5635,6 +6817,11 @@ extern "C" __device__ float test_tgammaf(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_tgamma_f64(double noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_tgamma(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_tgamma_f64(double noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_tgamma(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_tgamma_f64(double noundef [[X:%.*]]) #[[ATTR14]]
@@ -5659,6 +6846,11 @@ extern "C" __device__ double test_tgamma(double x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.trunc.f32(float [[X:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test_truncf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.trunc.f32(float [[X:%.*]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_truncf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.trunc.f32(float [[X:%.*]])
@@ -5683,6 +6875,11 @@ extern "C" __device__ float test_truncf(float x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.trunc.f64(double [[X:%.*]])
 // APPROX-NEXT:    ret double [[TMP0]]
 //
+// NCRDIV-LABEL: @test_trunc(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.trunc.f64(double [[X:%.*]])
+// NCRDIV-NEXT:    ret double [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_trunc(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) double @llvm.trunc.f64(double [[X:%.*]])
@@ -5707,6 +6904,11 @@ extern "C" __device__ double test_trunc(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_y0_f32(float noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_y0f(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_y0_f32(float noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_y0f(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_y0_f32(float noundef [[X:%.*]]) #[[ATTR14]]
@@ -5731,6 +6933,11 @@ extern "C" __device__ float test_y0f(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_y0_f64(double noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_y0(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_y0_f64(double noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_y0(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_y0_f64(double noundef [[X:%.*]]) #[[ATTR14]]
@@ -5755,6 +6962,11 @@ extern "C" __device__ double test_y0(double x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_y1_f32(float noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_y1f(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_y1_f32(float noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_y1f(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_y1_f32(float noundef [[X:%.*]]) #[[ATTR14]]
@@ -5779,6 +6991,11 @@ extern "C" __device__ float test_y1f(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_y1_f64(double noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret double [[CALL_I]]
 //
+// NCRDIV-LABEL: @test_y1(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef double @__ocml_y1_f64(double noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret double [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_y1(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) double @__ocml_y1_f64(double noundef [[X:%.*]]) #[[ATTR14]]
@@ -5887,6 +7104,39 @@ extern "C" __device__ double test_y1(double x) {
 // APPROX-NEXT:    [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I20_I]], [[IF_THEN_I]] ], [ [[CALL_I22_I]], [[IF_THEN2_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ]
 // APPROX-NEXT:    ret float [[RETVAL_0_I]]
 //
+// NCRDIV-LABEL: @test_ynf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    switch i32 [[X:%.*]], label [[IF_END4_I:%.*]] [
+// NCRDIV-NEXT:      i32 0, label [[IF_THEN_I:%.*]]
+// NCRDIV-NEXT:      i32 1, label [[IF_THEN2_I:%.*]]
+// NCRDIV-NEXT:    ]
+// NCRDIV:       if.then.i:
+// NCRDIV-NEXT:    [[CALL_I20_I:%.*]] = tail call contract noundef float @__ocml_y0_f32(float noundef [[Y:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    br label [[_ZL3YNFIF_EXIT:%.*]]
+// NCRDIV:       if.then2.i:
+// NCRDIV-NEXT:    [[CALL_I22_I:%.*]] = tail call contract noundef float @__ocml_y1_f32(float noundef [[Y]]) #[[ATTR14]]
+// NCRDIV-NEXT:    br label [[_ZL3YNFIF_EXIT]]
+// NCRDIV:       if.end4.i:
+// NCRDIV-NEXT:    [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_y0_f32(float noundef [[Y]]) #[[ATTR14]]
+// NCRDIV-NEXT:    [[CALL_I21_I:%.*]] = tail call contract noundef float @__ocml_y1_f32(float noundef [[Y]]) #[[ATTR14]]
+// NCRDIV-NEXT:    [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1
+// NCRDIV-NEXT:    br i1 [[CMP7_I1]], label [[FOR_BODY_I:%.*]], label [[_ZL3YNFIF_EXIT]]
+// NCRDIV:       for.body.i:
+// NCRDIV-NEXT:    [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ]
+// NCRDIV-NEXT:    [[__X1_0_I3:%.*]] = phi float [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ]
+// NCRDIV-NEXT:    [[__X0_0_I2:%.*]] = phi float [ [[__X1_0_I3]], [[FOR_BODY_I]] ], [ [[CALL_I_I]], [[IF_END4_I]] ]
+// NCRDIV-NEXT:    [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1
+// NCRDIV-NEXT:    [[CONV_I:%.*]] = uitofp nneg i32 [[MUL_I]] to float
+// NCRDIV-NEXT:    [[DIV_I:%.*]] = fdiv contract float [[CONV_I]], [[Y]], !fpmath [[META12]]
+// NCRDIV-NEXT:    [[MUL8_I:%.*]] = fmul contract float [[__X1_0_I3]], [[DIV_I]]
+// NCRDIV-NEXT:    [[SUB_I]] = fsub contract float [[MUL8_I]], [[__X0_0_I2]]
+// NCRDIV-NEXT:    [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1
+// NCRDIV-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]]
+// NCRDIV-NEXT:    br i1 [[EXITCOND_NOT]], label [[_ZL3YNFIF_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP26:![0-9]+]]
+// NCRDIV:       _ZL3ynfif.exit:
+// NCRDIV-NEXT:    [[RETVAL_0_I:%.*]] = phi float [ [[CALL_I20_I]], [[IF_THEN_I]] ], [ [[CALL_I22_I]], [[IF_THEN2_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ]
+// NCRDIV-NEXT:    ret float [[RETVAL_0_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_ynf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    switch i32 [[X:%.*]], label [[IF_END4_I:%.*]] [
@@ -6023,6 +7273,39 @@ extern "C" __device__ float test_ynf(int x, float y) {
 // APPROX-NEXT:    [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I20_I]], [[IF_THEN_I]] ], [ [[CALL_I22_I]], [[IF_THEN2_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ]
 // APPROX-NEXT:    ret double [[RETVAL_0_I]]
 //
+// NCRDIV-LABEL: @test_yn(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    switch i32 [[X:%.*]], label [[IF_END4_I:%.*]] [
+// NCRDIV-NEXT:      i32 0, label [[IF_THEN_I:%.*]]
+// NCRDIV-NEXT:      i32 1, label [[IF_THEN2_I:%.*]]
+// NCRDIV-NEXT:    ]
+// NCRDIV:       if.then.i:
+// NCRDIV-NEXT:    [[CALL_I20_I:%.*]] = tail call contract noundef double @__ocml_y0_f64(double noundef [[Y:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    br label [[_ZL2YNID_EXIT:%.*]]
+// NCRDIV:       if.then2.i:
+// NCRDIV-NEXT:    [[CALL_I22_I:%.*]] = tail call contract noundef double @__ocml_y1_f64(double noundef [[Y]]) #[[ATTR14]]
+// NCRDIV-NEXT:    br label [[_ZL2YNID_EXIT]]
+// NCRDIV:       if.end4.i:
+// NCRDIV-NEXT:    [[CALL_I_I:%.*]] = tail call contract noundef double @__ocml_y0_f64(double noundef [[Y]]) #[[ATTR14]]
+// NCRDIV-NEXT:    [[CALL_I21_I:%.*]] = tail call contract noundef double @__ocml_y1_f64(double noundef [[Y]]) #[[ATTR14]]
+// NCRDIV-NEXT:    [[CMP7_I1:%.*]] = icmp sgt i32 [[X]], 1
+// NCRDIV-NEXT:    br i1 [[CMP7_I1]], label [[FOR_BODY_I:%.*]], label [[_ZL2YNID_EXIT]]
+// NCRDIV:       for.body.i:
+// NCRDIV-NEXT:    [[__I_0_I4:%.*]] = phi i32 [ [[INC_I:%.*]], [[FOR_BODY_I]] ], [ 1, [[IF_END4_I]] ]
+// NCRDIV-NEXT:    [[__X1_0_I3:%.*]] = phi double [ [[SUB_I:%.*]], [[FOR_BODY_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ]
+// NCRDIV-NEXT:    [[__X0_0_I2:%.*]] = phi double [ [[__X1_0_I3]], [[FOR_BODY_I]] ], [ [[CALL_I_I]], [[IF_END4_I]] ]
+// NCRDIV-NEXT:    [[MUL_I:%.*]] = shl nuw nsw i32 [[__I_0_I4]], 1
+// NCRDIV-NEXT:    [[CONV_I:%.*]] = uitofp nneg i32 [[MUL_I]] to double
+// NCRDIV-NEXT:    [[DIV_I:%.*]] = fdiv contract double [[CONV_I]], [[Y]]
+// NCRDIV-NEXT:    [[MUL8_I:%.*]] = fmul contract double [[__X1_0_I3]], [[DIV_I]]
+// NCRDIV-NEXT:    [[SUB_I]] = fsub contract double [[MUL8_I]], [[__X0_0_I2]]
+// NCRDIV-NEXT:    [[INC_I]] = add nuw nsw i32 [[__I_0_I4]], 1
+// NCRDIV-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_I]], [[X]]
+// NCRDIV-NEXT:    br i1 [[EXITCOND_NOT]], label [[_ZL2YNID_EXIT]], label [[FOR_BODY_I]], !llvm.loop [[LOOP27:![0-9]+]]
+// NCRDIV:       _ZL2ynid.exit:
+// NCRDIV-NEXT:    [[RETVAL_0_I:%.*]] = phi double [ [[CALL_I20_I]], [[IF_THEN_I]] ], [ [[CALL_I22_I]], [[IF_THEN2_I]] ], [ [[CALL_I21_I]], [[IF_END4_I]] ], [ [[SUB_I]], [[FOR_BODY_I]] ]
+// NCRDIV-NEXT:    ret double [[RETVAL_0_I]]
+//
 // AMDGCNSPIRV-LABEL: @test_yn(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    switch i32 [[X:%.*]], label [[IF_END4_I:%.*]] [
@@ -6075,6 +7358,11 @@ extern "C" __device__ double test_yn(int x, double y) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_native_cos_f32(float noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test___cosf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_native_cos_f32(float noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test___cosf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_native_cos_f32(float noundef [[X:%.*]]) #[[ATTR14]]
@@ -6102,6 +7390,12 @@ extern "C" __device__ float test___cosf(float x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.amdgcn.exp2.f32(float [[MUL_I]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test___exp10f(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[MUL_I:%.*]] = fmul contract float [[X:%.*]], 0x400A934F00000000
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.amdgcn.exp2.f32(float [[MUL_I]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test___exp10f(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[MUL_I:%.*]] = fmul contract float [[X:%.*]], 0x400A934F00000000
@@ -6130,6 +7424,12 @@ extern "C" __device__ float test___exp10f(float x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.amdgcn.exp2.f32(float [[MUL_I]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test___expf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[MUL_I:%.*]] = fmul contract float [[X:%.*]], 0x3FF7154760000000
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.amdgcn.exp2.f32(float [[MUL_I]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test___expf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[MUL_I:%.*]] = fmul contract float [[X:%.*]], 0x3FF7154760000000
@@ -6155,6 +7455,11 @@ extern "C" __device__ float test___expf(float x) {
 // APPROX-NEXT:    [[ADD_I:%.*]] = fadd contract float [[X:%.*]], [[Y:%.*]]
 // APPROX-NEXT:    ret float [[ADD_I]]
 //
+// NCRDIV-LABEL: @test___fadd_rn(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[ADD_I:%.*]] = fadd contract float [[X:%.*]], [[Y:%.*]]
+// NCRDIV-NEXT:    ret float [[ADD_I]]
+//
 // AMDGCNSPIRV-LABEL: @test___fadd_rn(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[ADD_I:%.*]] = fadd contract float [[X:%.*]], [[Y:%.*]]
@@ -6179,6 +7484,11 @@ extern "C" __device__ float test___fadd_rn(float x, float y) {
 // APPROX-NEXT:    [[DIV_I:%.*]] = fdiv contract float [[X:%.*]], [[Y:%.*]]
 // APPROX-NEXT:    ret float [[DIV_I]]
 //
+// NCRDIV-LABEL: @test___fdividef(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[DIV_I:%.*]] = fdiv contract float [[X:%.*]], [[Y:%.*]], !fpmath [[META12]]
+// NCRDIV-NEXT:    ret float [[DIV_I]]
+//
 // AMDGCNSPIRV-LABEL: @test___fdividef(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[DIV_I:%.*]] = fdiv contract float [[X:%.*]], [[Y:%.*]]
@@ -6203,6 +7513,11 @@ extern "C" __device__ float test___fdividef(float x, float y) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.fma.f32(float [[X:%.*]], float [[Y:%.*]], float [[Z:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test__fmaf_rn(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.fma.f32(float [[X:%.*]], float [[Y:%.*]], float [[Z:%.*]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test__fmaf_rn(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.fma.f32(float [[X:%.*]], float [[Y:%.*]], float [[Z:%.*]])
@@ -6227,6 +7542,11 @@ extern "C" __device__ float test__fmaf_rn(float x, float y, float z) {
 // APPROX-NEXT:    [[MUL_I:%.*]] = fmul contract float [[X:%.*]], [[Y:%.*]]
 // APPROX-NEXT:    ret float [[MUL_I]]
 //
+// NCRDIV-LABEL: @test___fmul_rn(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[MUL_I:%.*]] = fmul contract float [[X:%.*]], [[Y:%.*]]
+// NCRDIV-NEXT:    ret float [[MUL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test___fmul_rn(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[MUL_I:%.*]] = fmul contract float [[X:%.*]], [[Y:%.*]]
@@ -6251,6 +7571,11 @@ extern "C" __device__ float test___fmul_rn(float x, float y) {
 // APPROX-NEXT:    [[DIV_I:%.*]] = fdiv contract float 1.000000e+00, [[X:%.*]]
 // APPROX-NEXT:    ret float [[DIV_I]]
 //
+// NCRDIV-LABEL: @test___frcp_rn(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[DIV_I:%.*]] = fdiv contract float 1.000000e+00, [[X:%.*]], !fpmath [[META12]]
+// NCRDIV-NEXT:    ret float [[DIV_I]]
+//
 // AMDGCNSPIRV-LABEL: @test___frcp_rn(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[DIV_I:%.*]] = fdiv contract float 1.000000e+00, [[X:%.*]]
@@ -6275,6 +7600,11 @@ extern "C" __device__ float test___frcp_rn(float x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.amdgcn.rsq.f32(float [[X:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test___frsqrt_rn(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.amdgcn.rsq.f32(float [[X:%.*]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test___frsqrt_rn(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.amdgcn.rsq.f32(float [[X:%.*]])
@@ -6299,6 +7629,11 @@ extern "C" __device__ float test___frsqrt_rn(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_native_sqrt_f32(float noundef [[X:%.*]]) #[[ATTR12]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test___fsqrt_rn(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_native_sqrt_f32(float noundef [[X:%.*]]) #[[ATTR12]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test___fsqrt_rn(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_native_sqrt_f32(float noundef [[X:%.*]]) #[[ATTR12]]
@@ -6323,6 +7658,11 @@ extern "C" __device__ float test___fsqrt_rn(float x) {
 // APPROX-NEXT:    [[SUB_I:%.*]] = fsub contract float [[X:%.*]], [[Y:%.*]]
 // APPROX-NEXT:    ret float [[SUB_I]]
 //
+// NCRDIV-LABEL: @test___fsub_rn(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[SUB_I:%.*]] = fsub contract float [[X:%.*]], [[Y:%.*]]
+// NCRDIV-NEXT:    ret float [[SUB_I]]
+//
 // AMDGCNSPIRV-LABEL: @test___fsub_rn(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[SUB_I:%.*]] = fsub contract float [[X:%.*]], [[Y:%.*]]
@@ -6347,6 +7687,11 @@ extern "C" __device__ float test___fsub_rn(float x, float y) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.log10.f32(float [[X:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test___log10f(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.log10.f32(float [[X:%.*]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test___log10f(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.log10.f32(float [[X:%.*]])
@@ -6371,6 +7716,11 @@ extern "C" __device__ float test___log10f(float x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.amdgcn.log.f32(float [[X:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test___log2f(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.amdgcn.log.f32(float [[X:%.*]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test___log2f(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.amdgcn.log.f32(float [[X:%.*]])
@@ -6395,6 +7745,11 @@ extern "C" __device__ float test___log2f(float x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.log.f32(float [[X:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test___logf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.log.f32(float [[X:%.*]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test___logf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.log.f32(float [[X:%.*]])
@@ -6419,6 +7774,11 @@ extern "C" __device__ float test___logf(float x) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_pow_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR13]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test___powf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_pow_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR13]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test___powf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_pow_f32(float noundef [[X:%.*]], float noundef [[Y:%.*]]) #[[ATTR13]]
@@ -6452,6 +7812,14 @@ extern "C" __device__ float test___powf(float x, float y) {
 // APPROX-NEXT:    [[COND5_I:%.*]] = select contract i1 [[CMP_I]], float 0.000000e+00, float [[COND_I]]
 // APPROX-NEXT:    ret float [[COND5_I]]
 //
+// NCRDIV-LABEL: @test___saturatef(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CMP_I:%.*]] = fcmp contract olt float [[X:%.*]], 0.000000e+00
+// NCRDIV-NEXT:    [[CMP1_I:%.*]] = fcmp contract ogt float [[X]], 1.000000e+00
+// NCRDIV-NEXT:    [[COND_I:%.*]] = select contract i1 [[CMP1_I]], float 1.000000e+00, float [[X]]
+// NCRDIV-NEXT:    [[COND5_I:%.*]] = select contract i1 [[CMP_I]], float 0.000000e+00, float [[COND_I]]
+// NCRDIV-NEXT:    ret float [[COND5_I]]
+//
 // AMDGCNSPIRV-LABEL: @test___saturatef(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CMP_I:%.*]] = fcmp contract olt float [[X:%.*]], 0.000000e+00
@@ -6488,6 +7856,14 @@ extern "C" __device__ float test___saturatef(float x) {
 // APPROX-NEXT:    store float [[CALL1_I]], ptr [[Z:%.*]], align 4, !tbaa [[TBAA16]]
 // APPROX-NEXT:    ret void
 //
+// NCRDIV-LABEL: @test___sincosf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract float @__ocml_native_sin_f32(float noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    store float [[CALL_I]], ptr [[Y:%.*]], align 4, !tbaa [[TBAA17]]
+// NCRDIV-NEXT:    [[CALL1_I:%.*]] = tail call contract float @__ocml_native_cos_f32(float noundef [[X]]) #[[ATTR14]]
+// NCRDIV-NEXT:    store float [[CALL1_I]], ptr [[Z:%.*]], align 4, !tbaa [[TBAA17]]
+// NCRDIV-NEXT:    ret void
+//
 // AMDGCNSPIRV-LABEL: @test___sincosf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func addrspace(4) float @__ocml_native_sin_f32(float noundef [[X:%.*]]) #[[ATTR14]]
@@ -6515,6 +7891,11 @@ extern "C" __device__ void test___sincosf(float x, float *y, float *z) {
 // APPROX-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_native_sin_f32(float noundef [[X:%.*]]) #[[ATTR14]]
 // APPROX-NEXT:    ret float [[CALL_I]]
 //
+// NCRDIV-LABEL: @test___sinf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I:%.*]] = tail call contract noundef float @__ocml_native_sin_f32(float noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    ret float [[CALL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test___sinf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_native_sin_f32(float noundef [[X:%.*]]) #[[ATTR14]]
@@ -6548,6 +7929,14 @@ extern "C" __device__ float test___sinf(float x) {
 // APPROX-NEXT:    [[MUL_I:%.*]] = fmul contract float [[CALL_I3_I]], [[TMP0]]
 // APPROX-NEXT:    ret float [[MUL_I]]
 //
+// NCRDIV-LABEL: @test___tanf(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[CALL_I3_I:%.*]] = tail call contract noundef float @__ocml_native_sin_f32(float noundef [[X:%.*]]) #[[ATTR14]]
+// NCRDIV-NEXT:    [[CALL_I_I:%.*]] = tail call contract noundef float @__ocml_native_cos_f32(float noundef [[X]]) #[[ATTR14]]
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract float @llvm.amdgcn.rcp.f32(float [[CALL_I_I]])
+// NCRDIV-NEXT:    [[MUL_I:%.*]] = fmul contract float [[CALL_I3_I]], [[TMP0]]
+// NCRDIV-NEXT:    ret float [[MUL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test___tanf(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[CALL_I3_I:%.*]] = tail call contract spir_func noundef addrspace(4) float @__ocml_native_sin_f32(float noundef [[X:%.*]]) #[[ATTR14]]
@@ -6575,6 +7964,11 @@ extern "C" __device__ float test___tanf(float x) {
 // APPROX-NEXT:    [[ADD_I:%.*]] = fadd contract double [[X:%.*]], [[Y:%.*]]
 // APPROX-NEXT:    ret double [[ADD_I]]
 //
+// NCRDIV-LABEL: @test___dadd_rn(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[ADD_I:%.*]] = fadd contract double [[X:%.*]], [[Y:%.*]]
+// NCRDIV-NEXT:    ret double [[ADD_I]]
+//
 // AMDGCNSPIRV-LABEL: @test___dadd_rn(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[ADD_I:%.*]] = fadd contract double [[X:%.*]], [[Y:%.*]]
@@ -6599,6 +7993,11 @@ extern "C" __device__ double test___dadd_rn(double x, double y) {
 // APPROX-NEXT:    [[DIV_I:%.*]] = fdiv contract double [[X:%.*]], [[Y:%.*]]
 // APPROX-NEXT:    ret double [[DIV_I]]
 //
+// NCRDIV-LABEL: @test___ddiv_rn(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[DIV_I:%.*]] = fdiv contract double [[X:%.*]], [[Y:%.*]]
+// NCRDIV-NEXT:    ret double [[DIV_I]]
+//
 // AMDGCNSPIRV-LABEL: @test___ddiv_rn(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[DIV_I:%.*]] = fdiv contract double [[X:%.*]], [[Y:%.*]]
@@ -6623,6 +8022,11 @@ extern "C" __device__ double test___ddiv_rn(double x, double y) {
 // APPROX-NEXT:    [[MUL_I:%.*]] = fmul contract double [[X:%.*]], [[Y:%.*]]
 // APPROX-NEXT:    ret double [[MUL_I]]
 //
+// NCRDIV-LABEL: @test___dmul_rn(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[MUL_I:%.*]] = fmul contract double [[X:%.*]], [[Y:%.*]]
+// NCRDIV-NEXT:    ret double [[MUL_I]]
+//
 // AMDGCNSPIRV-LABEL: @test___dmul_rn(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[MUL_I:%.*]] = fmul contract double [[X:%.*]], [[Y:%.*]]
@@ -6647,6 +8051,11 @@ extern "C" __device__ double test___dmul_rn(double x, double y) {
 // APPROX-NEXT:    [[DIV_I:%.*]] = fdiv contract double 1.000000e+00, [[X:%.*]]
 // APPROX-NEXT:    ret double [[DIV_I]]
 //
+// NCRDIV-LABEL: @test___drcp_rn(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[DIV_I:%.*]] = fdiv contract double 1.000000e+00, [[X:%.*]]
+// NCRDIV-NEXT:    ret double [[DIV_I]]
+//
 // AMDGCNSPIRV-LABEL: @test___drcp_rn(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[DIV_I:%.*]] = fdiv contract double 1.000000e+00, [[X:%.*]]
@@ -6671,6 +8080,11 @@ extern "C" __device__ double test___drcp_rn(double x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.sqrt.f64(double [[X:%.*]])
 // APPROX-NEXT:    ret double [[TMP0]]
 //
+// NCRDIV-LABEL: @test___dsqrt_rn(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.sqrt.f64(double [[X:%.*]])
+// NCRDIV-NEXT:    ret double [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test___dsqrt_rn(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) double @llvm.sqrt.f64(double [[X:%.*]])
@@ -6695,6 +8109,11 @@ extern "C" __device__ double test___dsqrt_rn(double x) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.fma.f64(double [[X:%.*]], double [[Y:%.*]], double [[Z:%.*]])
 // APPROX-NEXT:    ret double [[TMP0]]
 //
+// NCRDIV-LABEL: @test__fma_rn(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.fma.f64(double [[X:%.*]], double [[Y:%.*]], double [[Z:%.*]])
+// NCRDIV-NEXT:    ret double [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test__fma_rn(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) double @llvm.fma.f64(double [[X:%.*]], double [[Y:%.*]], double [[Z:%.*]])
@@ -6719,6 +8138,11 @@ extern "C" __device__ double test__fma_rn(double x, double y, double z) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.minnum.f32(float [[X:%.*]], float [[Y:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test_float_min(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.minnum.f32(float [[X:%.*]], float [[Y:%.*]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_float_min(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.minnum.f32(float [[X:%.*]], float [[Y:%.*]])
@@ -6743,6 +8167,11 @@ extern "C" __device__ float test_float_min(float x, float y) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.maxnum.f32(float [[X:%.*]], float [[Y:%.*]])
 // APPROX-NEXT:    ret float [[TMP0]]
 //
+// NCRDIV-LABEL: @test_float_max(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef float @llvm.maxnum.f32(float [[X:%.*]], float [[Y:%.*]])
+// NCRDIV-NEXT:    ret float [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_float_max(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) float @llvm.maxnum.f32(float [[X:%.*]], float [[Y:%.*]])
@@ -6767,6 +8196,11 @@ extern "C" __device__ float test_float_max(float x, float y) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.minnum.f64(double [[X:%.*]], double [[Y:%.*]])
 // APPROX-NEXT:    ret double [[TMP0]]
 //
+// NCRDIV-LABEL: @test_double_min(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.minnum.f64(double [[X:%.*]], double [[Y:%.*]])
+// NCRDIV-NEXT:    ret double [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_double_min(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) double @llvm.minnum.f64(double [[X:%.*]], double [[Y:%.*]])
@@ -6791,6 +8225,11 @@ extern "C" __device__ double test_double_min(double x, double y) {
 // APPROX-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.maxnum.f64(double [[X:%.*]], double [[Y:%.*]])
 // APPROX-NEXT:    ret double [[TMP0]]
 //
+// NCRDIV-LABEL: @test_double_max(
+// NCRDIV-NEXT:  entry:
+// NCRDIV-NEXT:    [[TMP0:%.*]] = tail call contract noundef double @llvm.maxnum.f64(double [[X:%.*]], double [[Y:%.*]])
+// NCRDIV-NEXT:    ret double [[TMP0]]
+//
 // AMDGCNSPIRV-LABEL: @test_double_max(
 // AMDGCNSPIRV-NEXT:  entry:
 // AMDGCNSPIRV-NEXT:    [[TMP0:%.*]] = tail call contract noundef addrspace(4) double @llvm.maxnum.f64(double [[X:%.*]], double [[Y:%.*]])
diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c
index 199916f70c14f..f0c4173e18022 100644
--- a/clang/test/Misc/target-invalid-cpu-note/riscv.c
+++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c
@@ -5,7 +5,9 @@
 // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32
 // RISCV32: error: unknown target CPU 'not-a-cpu'
 // RISCV32-NEXT: note: valid target CPU values are:
-// RISCV32-SAME: {{^}} generic-rv32
+// RISCV32-SAME: {{^}} andes-a45
+// RISCV32-SAME: {{^}}, andes-n45
+// RISCV32-SAME: {{^}}, generic-rv32
 // RISCV32-SAME: {{^}}, rocket-rv32
 // RISCV32-SAME: {{^}}, rp2350-hazard3
 // RISCV32-SAME: {{^}}, sifive-e20
@@ -24,7 +26,9 @@
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
 // RISCV64-NEXT: note: valid target CPU values are:
-// RISCV64-SAME: {{^}} generic-rv64
+// RISCV64-SAME: {{^}} andes-ax45
+// RISCV64-SAME: {{^}}, andes-nx45
+// RISCV64-SAME: {{^}}, generic-rv64
 // RISCV64-SAME: {{^}}, mips-p8700
 // RISCV64-SAME: {{^}}, rocket-rv64
 // RISCV64-SAME: {{^}}, sifive-p450
@@ -52,7 +56,9 @@
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
 // TUNE-RISCV32-NEXT: note: valid target CPU values are:
-// TUNE-RISCV32-SAME: {{^}} generic-rv32
+// TUNE-RISCV32-SAME: {{^}} andes-a45
+// TUNE-RISCV32-SAME: {{^}}, andes-n45
+// TUNE-RISCV32-SAME: {{^}}, generic-rv32
 // TUNE-RISCV32-SAME: {{^}}, rocket-rv32
 // TUNE-RISCV32-SAME: {{^}}, rp2350-hazard3
 // TUNE-RISCV32-SAME: {{^}}, sifive-e20
@@ -75,7 +81,9 @@
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
 // TUNE-RISCV64-NEXT: note: valid target CPU values are:
-// TUNE-RISCV64-SAME: {{^}} generic-rv64
+// TUNE-RISCV64-SAME: {{^}} andes-ax45
+// TUNE-RISCV64-SAME: {{^}}, andes-nx45
+// TUNE-RISCV64-SAME: {{^}}, generic-rv64
 // TUNE-RISCV64-SAME: {{^}}, mips-p8700
 // TUNE-RISCV64-SAME: {{^}}, rocket-rv64
 // TUNE-RISCV64-SAME: {{^}}, sifive-p450
diff --git a/clang/test/Modules/Inputs/PR137102/module.modulemap b/clang/test/Modules/Inputs/PR137102/module.modulemap
new file mode 100644
index 0000000000000..337aff5821e7f
--- /dev/null
+++ b/clang/test/Modules/Inputs/PR137102/module.modulemap
@@ -0,0 +1 @@
+module type_aware_destroying_new_delete { header "type_aware_destroying_new_delete.h" export * }
diff --git a/clang/test/Modules/Inputs/PR137102/type_aware_destroying_new_delete.h b/clang/test/Modules/Inputs/PR137102/type_aware_destroying_new_delete.h
new file mode 100644
index 0000000000000..f96a9ea0c8a41
--- /dev/null
+++ b/clang/test/Modules/Inputs/PR137102/type_aware_destroying_new_delete.h
@@ -0,0 +1,52 @@
+
+namespace std {
+    struct destroying_delete_t { };
+    template <class T> struct type_identity {
+        using type = T;
+    };
+    typedef __SIZE_TYPE__ size_t;
+    enum class align_val_t : size_t;
+};
+
+struct A {
+    A();
+   void *operator new(std::size_t);
+   void operator delete(A*, std::destroying_delete_t);
+};
+
+struct B {
+    B();
+    void *operator new(std::type_identity<B>, std::size_t, std::align_val_t);
+    void operator delete(std::type_identity<B>, void*, std::size_t, std::align_val_t);
+};
+
+struct C {
+    C();
+    template <class T> void *operator new(std::type_identity<T>, std::size_t, std::align_val_t);
+    template <class T> void operator delete(std::type_identity<T>, void*, std::size_t, std::align_val_t);
+};
+
+struct D {
+    D();
+};
+void *operator new(std::type_identity<D>, std::size_t, std::align_val_t);
+void operator delete(std::type_identity<D>, void*, std::size_t, std::align_val_t);
+
+struct E {
+    E();
+};
+template <class T> void *operator new(std::type_identity<T>, std::size_t, std::align_val_t);
+template <class T> void operator delete(std::type_identity<T>, void*, std::size_t, std::align_val_t);
+
+void in_module_tests() {
+  A* a = new A;
+  delete a;
+  B *b = new B;
+  delete b;
+  C *c = new C;
+  delete c;
+  D *d = new D;
+  delete d;
+  E *e = new E;
+  delete e;
+}
diff --git a/clang/test/Modules/explicit-build.cpp b/clang/test/Modules/explicit-build.cpp
index fb65508ccf091..50bba0d09966a 100644
--- a/clang/test/Modules/explicit-build.cpp
+++ b/clang/test/Modules/explicit-build.cpp
@@ -199,6 +199,6 @@
 // RUN:            -fmodule-file=%t/c.pcm \
 // RUN:            %s -DHAVE_A -DHAVE_B -DHAVE_C 2>&1 | FileCheck --check-prefix=CHECK-MISMATCHED-B %s
 //
-// CHECK-MISMATCHED-B:      fatal error: module file '{{.*}}b.pcm' is out of date and needs to be rebuilt: module file has a different size or mtime than expected
+// CHECK-MISMATCHED-B:      fatal error: module file '{{.*}}b.pcm' is out of date and needs to be rebuilt: module file has a different size than expected
 // CHECK-MISMATCHED-B-NEXT: note: imported by module 'c'
 // CHECK-MISMATCHED-B-NOT:  note:
diff --git a/clang/test/Modules/type-aware-destroying-new-and-delete-modules.cpp b/clang/test/Modules/type-aware-destroying-new-and-delete-modules.cpp
new file mode 100644
index 0000000000000..e88f8a8791147
--- /dev/null
+++ b/clang/test/Modules/type-aware-destroying-new-and-delete-modules.cpp
@@ -0,0 +1,23 @@
+// RUN: rm -rf %t
+// RUN: %clang_cc1 -fmodules -fimplicit-module-maps -x c++ -std=c++26 -fmodules-cache-path=%t -I %S/Inputs/PR137102 -emit-llvm-only %s
+// RUN: %clang_cc1 -fmodules -fimplicit-module-maps -x c++ -std=c++26 -fmodules-cache-path=%t -I %S/Inputs/PR137102 -emit-llvm-only %s -triple i686-windows
+
+#include "type_aware_destroying_new_delete.h"
+
+
+static void call_in_module_function(void) {
+    in_module_tests();
+}
+
+void out_of_module_tests() {
+    A* a = new A;
+    delete a;
+    B *b = new B;
+    delete b;
+    C *c = new C;
+    delete c;
+    D *d = new D;
+    delete d;
+    E *e = new E;
+    delete e;
+}
diff --git a/clang/test/PCH/Inputs/type_aware_destroying_new_delete.h b/clang/test/PCH/Inputs/type_aware_destroying_new_delete.h
new file mode 100644
index 0000000000000..42d609c0f5c26
--- /dev/null
+++ b/clang/test/PCH/Inputs/type_aware_destroying_new_delete.h
@@ -0,0 +1,52 @@
+
+namespace std {
+    struct destroying_delete_t { };
+    template <class T> struct type_identity {
+        using type = T;
+    };
+    typedef __SIZE_TYPE__ size_t;
+    enum class align_val_t : size_t;
+};
+
+struct A {
+    A();
+   void *operator new(std::size_t);
+   void operator delete(A*, std::destroying_delete_t);
+};
+
+struct B {
+    B();
+    void *operator new(std::type_identity<B>, std::size_t, std::align_val_t);
+    void operator delete(std::type_identity<B>, void*, std::size_t, std::align_val_t);
+};
+
+struct C {
+    C();
+    template <class T> void *operator new(std::type_identity<T>, std::size_t, std::align_val_t);
+    template <class T> void operator delete(std::type_identity<T>, void*, std::size_t, std::align_val_t);
+};
+
+struct D {
+    D();
+};
+void *operator new(std::type_identity<D>, std::size_t, std::align_val_t);
+void operator delete(std::type_identity<D>, void*, std::size_t, std::align_val_t);
+
+struct E {
+    E();
+};
+template <class T> void *operator new(std::type_identity<T>, std::size_t, std::align_val_t);
+template <class T> void operator delete(std::type_identity<T>, void*, std::size_t, std::align_val_t);
+
+void in_pch_tests() {
+  A* a = new A;
+  delete a;
+  B *b = new B;
+  delete b;
+  C *c = new C;
+  delete c;
+  D *d = new D;
+  delete d;
+  E *e = new E;
+  delete e;
+}
diff --git a/clang/test/PCH/type-aware-destroying-new-and-delete-pch.cpp b/clang/test/PCH/type-aware-destroying-new-and-delete-pch.cpp
new file mode 100644
index 0000000000000..d8f7f5dd50c78
--- /dev/null
+++ b/clang/test/PCH/type-aware-destroying-new-and-delete-pch.cpp
@@ -0,0 +1,27 @@
+// Test this without pch.
+// RUN: %clang_cc1 -x c++ -std=c++26 -include %S/Inputs/type_aware_destroying_new_delete.h -emit-llvm -o - %s
+
+// Test with pch.
+// RUN: %clang_cc1 -x c++ -std=c++26 -emit-pch -o %t %S/Inputs/type_aware_destroying_new_delete.h
+// RUN: %clang_cc1 -x c++ -std=c++26 -include-pch %t -emit-llvm -o - %s 
+
+// RUN: %clang_cc1 -x c++ -std=c++11 -emit-pch -fpch-instantiate-templates -o %t %S/Inputs/type_aware_destroying_new_delete.h
+// RUN: %clang_cc1 -x c++ -std=c++11 -include-pch %t -emit-llvm -o - %s
+
+
+static void call_in_pch_function(void) {
+    in_pch_tests();
+}
+
+void out_of_pch_tests() {
+    A* a = new A;
+    delete a;
+    B *b = new B;
+    delete b;
+    C *c = new C;
+    delete c;
+    D *d = new D;
+    delete d;
+    E *e = new E;
+    delete e;
+}
diff --git a/clang/test/Preprocessor/print-header-json.c b/clang/test/Preprocessor/print-header-json.c
index d0d5e6b6f7d9e..1ba63ddc7a249 100644
--- a/clang/test/Preprocessor/print-header-json.c
+++ b/clang/test/Preprocessor/print-header-json.c
@@ -1,11 +1,16 @@
 // RUN: %clang_cc1 -E -header-include-format=json -header-include-filtering=only-direct-system -header-include-file %t.txt -I %S/Inputs/print-header-json -isystem %S/Inputs/print-header-json/system %s
 // RUN: cat %t.txt | FileCheck %s --check-prefix=SUPPORTED
+
 // RUN: not %clang_cc1 -E -header-include-format=textual -header-include-filtering=only-direct-system -header-include-file %t.txt -I %S/Inputs/print-header-json -isystem %S/Inputs/print-header-json/system %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=UNSUPPORTED0
 // RUN: not %clang_cc1 -E -header-include-format=json -header-include-filtering=none -header-include-file %t.txt -I %S/Inputs/print-header-json -isystem %S/Inputs/print-header-json/system %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=UNSUPPORTED1
-// RUN: rm %t.txt
-// RUN: env CC_PRINT_HEADERS_FORMAT=json CC_PRINT_HEADERS_FILTERING=only-direct-system CC_PRINT_HEADERS_FILE=%t.txt %clang -fsyntax-only -I %S/Inputs/print-header-json -isystem %S/Inputs/print-header-json/system %s -o /dev/null
 // RUN: env CC_PRINT_HEADERS_FORMAT=textual CC_PRINT_HEADERS_FILTERING=only-direct-system CC_PRINT_HEADERS_FILE=%t.txt not %clang -fsyntax-only -I %S/Inputs/print-header-json -isystem %S/Inputs/print-header-json/system %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=UNSUPPORTED2
 // RUN: env CC_PRINT_HEADERS_FORMAT=json CC_PRINT_HEADERS_FILTERING=none CC_PRINT_HEADERS_FILE=%t.txt not %clang -fsyntax-only -I %S/Inputs/print-header-json -isystem %S/Inputs/print-header-json/system %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=UNSUPPORTED3
+// RUN: env CC_PRINT_HEADERS_FORMAT=json CC_PRINT_HEADERS_FILE=%t.txt not %clang -fsyntax-only -I %S/Inputs/print-header-json -isystem %S/Inputs/print-header-json/system %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=UNSUPPORTED4
+// RUN: not %clang_cc1 -E -header-include-filtering=only-direct-system -header-include-file %t.txt -I %S/Inputs/print-header-json -isystem %S/Inputs/print-header-json/system %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=UNSUPPORTED5
+// RUN: not %clang_cc1 -E -header-include-format=json -header-include-file %t.txt -I %S/Inputs/print-header-json -isystem %S/Inputs/print-header-json/system %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=UNSUPPORTED6
+
+// RUN: rm %t.txt
+// RUN: env CC_PRINT_HEADERS_FORMAT=json CC_PRINT_HEADERS_FILTERING=only-direct-system CC_PRINT_HEADERS_FILE=%t.txt %clang -fsyntax-only -I %S/Inputs/print-header-json -isystem %S/Inputs/print-header-json/system %s -o /dev/null
 // RUN: cat %t.txt | FileCheck %s --check-prefix=SUPPORTED
 
 #include "system0.h"
@@ -18,3 +23,6 @@
 // UNSUPPORTED1: error: unsupported combination: -header-include-format=json and -header-include-filtering=none
 // UNSUPPORTED2: error: unsupported combination: CC_PRINT_HEADERS_FORMAT=textual and CC_PRINT_HEADERS_FILTERING=only-direct-system
 // UNSUPPORTED3: error: unsupported combination: CC_PRINT_HEADERS_FORMAT=json and CC_PRINT_HEADERS_FILTERING=none
+// UNSUPPORTED4: error: environment variable CC_PRINT_HEADERS_FORMAT=json requires a compatible value for CC_PRINT_HEADERS_FILTERING
+// UNSUPPORTED5: error: -header-include-filtering=only-direct-system requires a compatible value for -header-include-format
+// UNSUPPORTED6: error: -header-include-format=json requires a compatible value for -header-include-filtering
diff --git a/clang/test/Sema/aarch64-sme2p2-instrinsics/acle_sme2p2_fp8_imm.cpp b/clang/test/Sema/aarch64-sme2p2-instrinsics/acle_sme2p2_fp8_imm.cpp
new file mode 100644
index 0000000000000..e031cfe9b3cb4
--- /dev/null
+++ b/clang/test/Sema/aarch64-sme2p2-instrinsics/acle_sme2p2_fp8_imm.cpp
@@ -0,0 +1,31 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu \
+// RUN:    -target-feature +sme -target-feature +sme2p2 -target-feature +sme-mop4 -target-feature +sme-f8f32 -target-feature +sme-f8f16 -fsyntax-only -verify %s
+
+// REQUIRES: aarch64-registered-target
+
+#include <arm_sme.h>
+
+void tests_mop4_imm_1x1(svmfloat8_t zn, svmfloat8_t zm, fpm_t fpmr) __arm_streaming __arm_inout("za") {
+  svmop4a_1x1_za16_mf8_mf8_fpm(-1, zn, zm, fpmr); // expected-error {{argument value 18446744073709551615 is outside the valid range [0, 1]}}
+  svmop4a_1x1_za32_mf8_mf8_fpm(-1, zn, zm, fpmr); // expected-error {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
+  return;
+}
+
+void tests_mop4_imm_1x2(svmfloat8_t zn, svmfloat8x2_t zm, fpm_t fpmr) __arm_streaming __arm_inout("za") {
+  svmop4a_1x2_za16_mf8_mf8_fpm(-1, zn, zm, fpmr); // expected-error {{argument value 18446744073709551615 is outside the valid range [0, 1]}}
+  svmop4a_1x2_za32_mf8_mf8_fpm(-1, zn, zm, fpmr); // expected-error {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
+  return;
+}
+
+void tests_mop4_imm_2x1(svmfloat8x2_t zn, svmfloat8_t zm, fpm_t fpmr) __arm_streaming __arm_inout("za") {
+  svmop4a_2x1_za16_mf8_mf8_fpm(-1, zn, zm, fpmr); // expected-error {{argument value 18446744073709551615 is outside the valid range [0, 1]}}
+  svmop4a_2x1_za32_mf8_mf8_fpm(-1, zn, zm, fpmr); // expected-error {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
+  return;
+}
+
+void tests_mop4_imm_2x2(svmfloat8x2_t zn, svmfloat8x2_t zm, fpm_t fpmr) __arm_streaming __arm_inout("za") {
+  svmop4a_2x2_za16_mf8_mf8_fpm(-1, zn, zm, fpmr); // expected-error {{argument value 18446744073709551615 is outside the valid range [0, 1]}}
+  svmop4a_2x2_za32_mf8_mf8_fpm(-1, zn, zm, fpmr); // expected-error {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
+  return;
+}
diff --git a/clang/test/Sema/implicit-void-ptr-cast.c b/clang/test/Sema/implicit-void-ptr-cast.c
new file mode 100644
index 0000000000000..df18eeebd9347
--- /dev/null
+++ b/clang/test/Sema/implicit-void-ptr-cast.c
@@ -0,0 +1,38 @@
+// RUN: %clang_cc1 -fsyntax-only -verify=c -Wimplicit-void-ptr-cast %s
+// RUN: %clang_cc1 -fsyntax-only -verify=c -Wc++-compat %s
+// RUN: %clang_cc1 -fsyntax-only -verify=cxx -x c++ %s
+// RUN: %clang_cc1 -fsyntax-only -verify=good %s
+// RUN: %clang_cc1 -fsyntax-only -verify=good -Wc++-compat -Wno-implicit-void-ptr-cast %s
+// good-no-diagnostics
+
+typedef __typeof__(sizeof(int)) size_t;
+extern void *malloc(size_t);
+
+void func(int *); // #func-param
+
+void test(void) {
+  int *x = malloc(sizeof(char)); // c-warning {{implicit conversion when initializing 'int *' with an expression of type 'void *' is not permitted in C++}} \
+                                    cxx-error {{cannot initialize a variable of type 'int *' with an rvalue of type 'void *'}}
+  x = malloc(sizeof(char));      // c-warning {{implicit conversion when assigning to 'int *' from type 'void *' is not permitted in C++}} \
+                                    cxx-error {{assigning to 'int *' from incompatible type 'void *'}}
+  func(malloc(sizeof(char)));    // c-warning {{implicit conversion when passing 'void *' to parameter of type 'int *' is not permitted in C++}} \
+                                    c-note@#func-param {{passing argument to parameter here}} \
+                                    cxx-error {{no matching function for call to 'func'}} \
+                                    cxx-note@#func-param {{candidate function not viable: cannot convert argument of incomplete type 'void *' to 'int *' for 1st argument}}
+  x = (int *)malloc(sizeof(char));
+
+  void *vp = 0;
+  x = vp; // c-warning {{implicit conversion when assigning to 'int *' from type 'void *' is not permitted in C++}} \
+             cxx-error {{assigning to 'int *' from incompatible type 'void *'}}
+  vp = vp;
+
+  x = (void *)malloc(sizeof(char)); // c-warning {{implicit conversion when assigning to 'int *' from type 'void *' is not permitted in C++}} \
+                                       cxx-error {{assigning to 'int *' from incompatible type 'void *'}}
+  const int *y = vp;                // c-warning {{implicit conversion when initializing 'const int *' with an expression of type 'void *' is not permitted in C++}} \
+                                       cxx-error {{cannot initialize a variable of type 'const int *' with an lvalue of type 'void *'}}
+}
+
+int *other_func(void *ptr) {
+  return ptr; // c-warning {{implicit conversion when returning 'void *' from a function with result type 'int *' is not permitted in C++}} \
+                 cxx-error {{cannot initialize return object of type 'int *' with an lvalue of type 'void *'}}
+}
diff --git a/clang/test/SemaCXX/constant-expression-cxx11.cpp b/clang/test/SemaCXX/constant-expression-cxx11.cpp
index 28016da925ef9..dc8f4bf1666ee 100644
--- a/clang/test/SemaCXX/constant-expression-cxx11.cpp
+++ b/clang/test/SemaCXX/constant-expression-cxx11.cpp
@@ -2203,6 +2203,8 @@ namespace BuiltinStrlen {
   static_assert(__builtin_strlen("foo") == 3, "");
   static_assert(__builtin_strlen("foo\0quux") == 3, "");
   static_assert(__builtin_strlen("foo\0quux" + 4) == 4, "");
+  static_assert(__builtin_strlen("foo") + 1 + "foo" == "foo", ""); // expected-error {{static assertion expression is not an integral constant expression}}
+  // expected-note@-1 {{comparison against pointer '&"foo"[4]' that points past the end of a complete object has unspecified value}}
 
   constexpr bool check(const char *p) {
     return __builtin_strlen(p) == 3 &&
diff --git a/clang/test/SemaCXX/constexpr-vectors-access-elements.cpp b/clang/test/SemaCXX/constexpr-vectors-access-elements.cpp
index 08223e15feb72..58efcde414af2 100644
--- a/clang/test/SemaCXX/constexpr-vectors-access-elements.cpp
+++ b/clang/test/SemaCXX/constexpr-vectors-access-elements.cpp
@@ -43,4 +43,6 @@ static_assert(b.lo.lo == 1); // expected-error {{not an integral constant expres
 // make sure clang rejects taking address of a vector element
 static_assert(&b[1]); // expected-error {{address of vector element requested}}
 
+constexpr const FourIntsExtVec *p = &b;
+static_assert(p->x == 1);
 }
diff --git a/clang/test/SemaOpenACC/data-construct-async-clause.c b/clang/test/SemaOpenACC/data-construct-async-clause.c
index 3c9fbae0d9875..6cb34b0fcebda 100644
--- a/clang/test/SemaOpenACC/data-construct-async-clause.c
+++ b/clang/test/SemaOpenACC/data-construct-async-clause.c
@@ -31,4 +31,41 @@ void Test() {
   // expected-error@+2{{expected ')'}}
   // expected-note@+1{{to match this '('}}
 #pragma acc enter data copyin(I) async(I, I)
+  //
+  // expected-error@+2{{OpenACC 'async' clause cannot appear more than once on a 'data' directive}}
+  // expected-note@+1{{previous clause is here}}
+#pragma acc data default(none) async async
+  while(1);
+
+  // expected-error@+2{{OpenACC 'async' clause cannot appear more than once on a 'data' directive}}
+  // expected-note@+1{{previous clause is here}}
+#pragma acc data default(none) async(1) async(2)
+  while(1);
+
+  // expected-error@+2{{OpenACC 'async' clause cannot appear more than once on a 'data' directive}}
+  // expected-note@+1{{previous clause is here}}
+#pragma acc data default(none) async(1) async(2)
+  while(1);
+
+  // expected-error@+3{{OpenACC 'async' clause cannot appear more than once in a 'device_type' region on a 'data' directive}}
+  // expected-note@+2{{previous clause is here}}
+  // expected-note@+1{{previous clause is here}}
+#pragma acc data default(none) async(1) device_type(*) async(1) async(2)
+  while(1);
+  // expected-error@+3{{OpenACC 'async' clause cannot appear more than once in a 'device_type' region on a 'data' directive}}
+  // expected-note@+2{{previous clause is here}}
+  // expected-note@+1{{previous clause is here}}
+#pragma acc data default(none) async device_type(*) async async
+  while(1);
+  // expected-error@+3{{OpenACC 'async' clause cannot appear more than once in a 'device_type' region on a 'data' directive}}
+  // expected-note@+2{{previous clause is here}}
+  // expected-note@+1{{previous clause is here}}
+#pragma acc data default(none) async(1) device_type(*) async async(2)
+  while(1);
+
+  // expected-error@+3{{OpenACC 'async' clause cannot appear more than once in a 'device_type' region on a 'data' directive}}
+  // expected-note@+2{{previous clause is here}}
+  // expected-note@+1{{previous clause is here}}
+#pragma acc data default(none) device_type(*) async async
+  while(1);
 }
diff --git a/clang/tools/driver/driver.cpp b/clang/tools/driver/driver.cpp
index 00c00cea16f47..db72b4a4526fe 100644
--- a/clang/tools/driver/driver.cpp
+++ b/clang/tools/driver/driver.cpp
@@ -156,6 +156,11 @@ static bool SetBackdoorDriverOutputsFromEnvVars(Driver &TheDriver) {
       }
 
       const char *FilteringStr = ::getenv("CC_PRINT_HEADERS_FILTERING");
+      if (!FilteringStr) {
+        TheDriver.Diag(clang::diag::err_drv_print_header_env_var_invalid_format)
+            << EnvVar;
+        return false;
+      }
       HeaderIncludeFilteringKind Filtering;
       if (!stringToHeaderIncludeFiltering(FilteringStr, Filtering)) {
         TheDriver.Diag(clang::diag::err_drv_print_header_env_var)
diff --git a/clang/tools/libclang/CIndex.cpp b/clang/tools/libclang/CIndex.cpp
index c8db6c92bb4d4..2910483152b17 100644
--- a/clang/tools/libclang/CIndex.cpp
+++ b/clang/tools/libclang/CIndex.cpp
@@ -5170,7 +5170,7 @@ int clang_File_isEqual(CXFile file1, CXFile file2) {
 
   FileEntryRef FEnt1 = *cxfile::getFileEntryRef(file1);
   FileEntryRef FEnt2 = *cxfile::getFileEntryRef(file2);
-  return FEnt1.getUniqueID() == FEnt2.getUniqueID();
+  return FEnt1 == FEnt2;
 }
 
 CXString clang_File_tryGetRealPathName(CXFile SFile) {
diff --git a/clang/unittests/Format/FormatTest.cpp b/clang/unittests/Format/FormatTest.cpp
index f1b3b7dd8c0c3..8543c1b565d6d 100644
--- a/clang/unittests/Format/FormatTest.cpp
+++ b/clang/unittests/Format/FormatTest.cpp
@@ -12645,9 +12645,6 @@ TEST_F(FormatTest, UnderstandsAttributes) {
   verifyFormat("aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa __attribute__((unused))\n"
                "aaaaaaaaaaaaaaaaaaaaaaa(int i);");
   verifyFormat("__attribute__((nodebug)) ::qualified_type f();");
-  verifyFormat(
-      "RenderWidgetHostViewCocoa *\n"
-      "    __attribute__((objc_precise_lifetime)) keepSelfAlive = self;");
   FormatStyle AfterType = getLLVMStyle();
   AfterType.BreakAfterReturnType = FormatStyle::RTBS_All;
   verifyFormat("__attribute__((nodebug)) void\n"
diff --git a/clang/unittests/Format/FormatTestJS.cpp b/clang/unittests/Format/FormatTestJS.cpp
index 1cfacc060d944..91577b9a49167 100644
--- a/clang/unittests/Format/FormatTestJS.cpp
+++ b/clang/unittests/Format/FormatTestJS.cpp
@@ -48,18 +48,22 @@ class FormatTestJS : public testing::Test {
   static void verifyFormat(
       StringRef Code,
       const FormatStyle &Style = getGoogleStyle(FormatStyle::LK_JavaScript)) {
-    EXPECT_EQ(Code.str(), format(Code, Style)) << "Expected code is not stable";
-    std::string Result = format(test::messUp(Code), Style);
-    EXPECT_EQ(Code.str(), Result) << "Formatted:\n" << Result;
+    auto Result = format(test::messUp(Code), Style);
+    EXPECT_EQ(Code, Result) << "Formatted:\n" << Result;
+    if (Code != Result)
+      return;
+    EXPECT_EQ(Code, format(Code, Style)) << "Expected code is not stable";
   }
 
   static void verifyFormat(
       StringRef Expected, StringRef Code,
       const FormatStyle &Style = getGoogleStyle(FormatStyle::LK_JavaScript)) {
-    EXPECT_EQ(Expected.str(), format(Expected, Style))
+    auto Result = format(Code, Style);
+    EXPECT_EQ(Expected, Result) << "Formatted:\n" << Result;
+    if (Expected != Result)
+      return;
+    EXPECT_EQ(Expected, format(Expected, Style))
         << "Expected code is not stable";
-    std::string Result = format(Code, Style);
-    EXPECT_EQ(Expected.str(), Result) << "Formatted:\n" << Result;
   }
 };
 
diff --git a/clang/unittests/Format/TokenAnnotatorTest.cpp b/clang/unittests/Format/TokenAnnotatorTest.cpp
index a6410f3c8fe53..87b2f329d57cf 100644
--- a/clang/unittests/Format/TokenAnnotatorTest.cpp
+++ b/clang/unittests/Format/TokenAnnotatorTest.cpp
@@ -1084,6 +1084,11 @@ TEST_F(TokenAnnotatorTest, UnderstandsOverloadedOperators) {
   ASSERT_EQ(Tokens.size(), 11u) << Tokens;
   EXPECT_TOKEN(Tokens[3], tok::identifier, TT_FunctionDeclarationName);
   EXPECT_TOKEN(Tokens[7], tok::l_paren, TT_OverloadedOperatorLParen);
+
+  Tokens = annotate("using std::operator==;");
+  ASSERT_EQ(Tokens.size(), 7u) << Tokens;
+  // Not TT_FunctionDeclarationName.
+  EXPECT_TOKEN(Tokens[3], tok::kw_operator, TT_Unknown);
 }
 
 TEST_F(TokenAnnotatorTest, OverloadedOperatorInTemplate) {
@@ -2165,6 +2170,16 @@ TEST_F(TokenAnnotatorTest, UnderstandsLambdas) {
   // FIXME:
   // EXPECT_TOKEN(Tokens[13], tok::l_paren, TT_LambdaDefinitionLParen);
   EXPECT_TOKEN(Tokens[17], tok::l_brace, TT_LambdaLBrace);
+
+  Tokens = annotate("auto foo{(std::function<int()>)[] { return 0; }};");
+  ASSERT_EQ(Tokens.size(), 23u) << Tokens;
+  EXPECT_TOKEN(Tokens[13], tok::l_square, TT_LambdaLSquare);
+  EXPECT_TOKEN(Tokens[15], tok::l_brace, TT_LambdaLBrace);
+
+  Tokens = annotate("auto foo{(int (*)())[] { return 0; }};");
+  ASSERT_EQ(Tokens.size(), 21u) << Tokens;
+  EXPECT_TOKEN(Tokens[11], tok::l_square, TT_LambdaLSquare);
+  EXPECT_TOKEN(Tokens[13], tok::l_brace, TT_LambdaLBrace);
 }
 
 TEST_F(TokenAnnotatorTest, UnderstandsFunctionAnnotations) {
@@ -3975,6 +3990,12 @@ TEST_F(TokenAnnotatorTest, IdentifierPackage) {
   EXPECT_FALSE(Tokens[0]->isObjCAccessSpecifier());
 }
 
+TEST_F(TokenAnnotatorTest, UserDefinedLiteral) {
+  auto Tokens = annotate("auto dollars = 2_$;");
+  ASSERT_EQ(Tokens.size(), 6u) << Tokens;
+  EXPECT_EQ(Tokens[3]->TokenText, "2_$");
+}
+
 } // namespace
 } // namespace format
 } // namespace clang
diff --git a/clang/unittests/Lex/PPDependencyDirectivesTest.cpp b/clang/unittests/Lex/PPDependencyDirectivesTest.cpp
index 03f1432d990cb..6ab80ba01677e 100644
--- a/clang/unittests/Lex/PPDependencyDirectivesTest.cpp
+++ b/clang/unittests/Lex/PPDependencyDirectivesTest.cpp
@@ -103,25 +103,33 @@ TEST_F(PPDependencyDirectivesTest, MacroGuard) {
     SmallVector<dependency_directives_scan::Token> Tokens;
     SmallVector<dependency_directives_scan::Directive> Directives;
   };
-  SmallVector<std::unique_ptr<DepDirectives>> DepDirectivesObjects;
-
-  auto getDependencyDirectives = [&](FileEntryRef File)
-      -> std::optional<ArrayRef<dependency_directives_scan::Directive>> {
-    DepDirectivesObjects.push_back(std::make_unique<DepDirectives>());
-    StringRef Input = (*FileMgr.getBufferForFile(File))->getBuffer();
-    bool Err = scanSourceForDependencyDirectives(
-        Input, DepDirectivesObjects.back()->Tokens,
-        DepDirectivesObjects.back()->Directives);
-    EXPECT_FALSE(Err);
-    return llvm::ArrayRef(DepDirectivesObjects.back()->Directives);
-  };
 
-  PreprocessorOptions PPOpts;
-  PPOpts.DependencyDirectivesForFile = [&](FileEntryRef File)
-      -> std::optional<ArrayRef<dependency_directives_scan::Directive>> {
-    return getDependencyDirectives(File);
+  class TestDependencyDirectivesGetter : public DependencyDirectivesGetter {
+    FileManager &FileMgr;
+    SmallVector<std::unique_ptr<DepDirectives>> DepDirectivesObjects;
+
+  public:
+    TestDependencyDirectivesGetter(FileManager &FileMgr) : FileMgr(FileMgr) {}
+
+    std::unique_ptr<DependencyDirectivesGetter>
+    cloneFor(FileManager &FileMgr) override {
+      return std::make_unique<TestDependencyDirectivesGetter>(FileMgr);
+    }
+
+    std::optional<ArrayRef<dependency_directives_scan::Directive>>
+    operator()(FileEntryRef File) override {
+      DepDirectivesObjects.push_back(std::make_unique<DepDirectives>());
+      StringRef Input = (*FileMgr.getBufferForFile(File))->getBuffer();
+      bool Err = scanSourceForDependencyDirectives(
+          Input, DepDirectivesObjects.back()->Tokens,
+          DepDirectivesObjects.back()->Directives);
+      EXPECT_FALSE(Err);
+      return DepDirectivesObjects.back()->Directives;
+    }
   };
+  TestDependencyDirectivesGetter GetDependencyDirectives(FileMgr);
 
+  PreprocessorOptions PPOpts;
   HeaderSearchOptions HSOpts;
   TrivialModuleLoader ModLoader;
   HeaderSearch HeaderInfo(HSOpts, SourceMgr, Diags, LangOpts, Target.get());
@@ -130,6 +138,8 @@ TEST_F(PPDependencyDirectivesTest, MacroGuard) {
                   /*OwnsHeaderSearch =*/false);
   PP.Initialize(*Target);
 
+  PP.setDependencyDirectivesGetter(GetDependencyDirectives);
+
   SmallVector<StringRef> IncludedFiles;
   PP.addPPCallbacks(std::make_unique<IncludeCollector>(PP, IncludedFiles));
   PP.EnterMainSourceFile();
diff --git a/clang/unittests/Parse/ParseHLSLRootSignatureTest.cpp b/clang/unittests/Parse/ParseHLSLRootSignatureTest.cpp
index 19d5b267f310a..e382a1b26d366 100644
--- a/clang/unittests/Parse/ParseHLSLRootSignatureTest.cpp
+++ b/clang/unittests/Parse/ParseHLSLRootSignatureTest.cpp
@@ -129,10 +129,10 @@ TEST_F(ParseHLSLRootSignatureTest, ValidParseEmptyTest) {
 TEST_F(ParseHLSLRootSignatureTest, ValidParseDTClausesTest) {
   const llvm::StringLiteral Source = R"cc(
     DescriptorTable(
-      CBV(),
-      SRV(),
-      Sampler(),
-      UAV()
+      CBV(b0),
+      SRV(space = 3, t42),
+      Sampler(s987, space = +2),
+      UAV(u4294967294)
     ),
     DescriptorTable()
   )cc";
@@ -154,18 +154,34 @@ TEST_F(ParseHLSLRootSignatureTest, ValidParseDTClausesTest) {
   RootElement Elem = Elements[0];
   ASSERT_TRUE(std::holds_alternative<DescriptorTableClause>(Elem));
   ASSERT_EQ(std::get<DescriptorTableClause>(Elem).Type, ClauseType::CBuffer);
+  ASSERT_EQ(std::get<DescriptorTableClause>(Elem).Reg.ViewType,
+            RegisterType::BReg);
+  ASSERT_EQ(std::get<DescriptorTableClause>(Elem).Reg.Number, 0u);
+  ASSERT_EQ(std::get<DescriptorTableClause>(Elem).Space, 0u);
 
   Elem = Elements[1];
   ASSERT_TRUE(std::holds_alternative<DescriptorTableClause>(Elem));
   ASSERT_EQ(std::get<DescriptorTableClause>(Elem).Type, ClauseType::SRV);
+  ASSERT_EQ(std::get<DescriptorTableClause>(Elem).Reg.ViewType,
+            RegisterType::TReg);
+  ASSERT_EQ(std::get<DescriptorTableClause>(Elem).Reg.Number, 42u);
+  ASSERT_EQ(std::get<DescriptorTableClause>(Elem).Space, 3u);
 
   Elem = Elements[2];
   ASSERT_TRUE(std::holds_alternative<DescriptorTableClause>(Elem));
   ASSERT_EQ(std::get<DescriptorTableClause>(Elem).Type, ClauseType::Sampler);
+  ASSERT_EQ(std::get<DescriptorTableClause>(Elem).Reg.ViewType,
+            RegisterType::SReg);
+  ASSERT_EQ(std::get<DescriptorTableClause>(Elem).Reg.Number, 987u);
+  ASSERT_EQ(std::get<DescriptorTableClause>(Elem).Space, 2u);
 
   Elem = Elements[3];
   ASSERT_TRUE(std::holds_alternative<DescriptorTableClause>(Elem));
   ASSERT_EQ(std::get<DescriptorTableClause>(Elem).Type, ClauseType::UAV);
+  ASSERT_EQ(std::get<DescriptorTableClause>(Elem).Reg.ViewType,
+            RegisterType::UReg);
+  ASSERT_EQ(std::get<DescriptorTableClause>(Elem).Reg.Number, 4294967294u);
+  ASSERT_EQ(std::get<DescriptorTableClause>(Elem).Space, 0u);
 
   Elem = Elements[4];
   ASSERT_TRUE(std::holds_alternative<DescriptorTable>(Elem));
@@ -175,6 +191,32 @@ TEST_F(ParseHLSLRootSignatureTest, ValidParseDTClausesTest) {
   Elem = Elements[5];
   ASSERT_TRUE(std::holds_alternative<DescriptorTable>(Elem));
   ASSERT_EQ(std::get<DescriptorTable>(Elem).NumClauses, 0u);
+
+  ASSERT_TRUE(Consumer->isSatisfied());
+}
+
+TEST_F(ParseHLSLRootSignatureTest, ValidTrailingCommaTest) {
+  // This test will checks we can handling trailing commas ','
+  const llvm::StringLiteral Source = R"cc(
+    DescriptorTable(
+      CBV(b0, ),
+      SRV(t42),
+    )
+  )cc";
+
+  TrivialModuleLoader ModLoader;
+  auto PP = createPP(Source, ModLoader);
+  auto TokLoc = SourceLocation();
+
+  hlsl::RootSignatureLexer Lexer(Source, TokLoc);
+  SmallVector<RootElement> Elements;
+  hlsl::RootSignatureParser Parser(Elements, Lexer, *PP);
+
+  // Test no diagnostics produced
+  Consumer->setNoDiag();
+
+  ASSERT_FALSE(Parser.parse());
+
   ASSERT_TRUE(Consumer->isSatisfied());
 }
 
@@ -236,6 +278,102 @@ TEST_F(ParseHLSLRootSignatureTest, InvalidParseUnexpectedEndOfStreamTest) {
 
   // Test correct diagnostic produced - end of stream
   Consumer->setExpected(diag::err_expected_after);
+
+  ASSERT_TRUE(Parser.parse());
+
+  ASSERT_TRUE(Consumer->isSatisfied());
+}
+
+TEST_F(ParseHLSLRootSignatureTest, InvalidMissingParameterTest) {
+  // This test will check that the parsing fails due a mandatory
+  // parameter (register) not being specified
+  const llvm::StringLiteral Source = R"cc(
+    DescriptorTable(
+      CBV()
+    )
+  )cc";
+
+  TrivialModuleLoader ModLoader;
+  auto PP = createPP(Source, ModLoader);
+  auto TokLoc = SourceLocation();
+
+  hlsl::RootSignatureLexer Lexer(Source, TokLoc);
+  SmallVector<RootElement> Elements;
+  hlsl::RootSignatureParser Parser(Elements, Lexer, *PP);
+
+  // Test correct diagnostic produced
+  Consumer->setExpected(diag::err_hlsl_rootsig_missing_param);
+  ASSERT_TRUE(Parser.parse());
+
+  ASSERT_TRUE(Consumer->isSatisfied());
+}
+
+TEST_F(ParseHLSLRootSignatureTest, InvalidRepeatedMandatoryParameterTest) {
+  // This test will check that the parsing fails due the same mandatory
+  // parameter being specified multiple times
+  const llvm::StringLiteral Source = R"cc(
+    DescriptorTable(
+      CBV(b32, b84)
+    )
+  )cc";
+
+  TrivialModuleLoader ModLoader;
+  auto PP = createPP(Source, ModLoader);
+  auto TokLoc = SourceLocation();
+
+  hlsl::RootSignatureLexer Lexer(Source, TokLoc);
+  SmallVector<RootElement> Elements;
+  hlsl::RootSignatureParser Parser(Elements, Lexer, *PP);
+
+  // Test correct diagnostic produced
+  Consumer->setExpected(diag::err_hlsl_rootsig_repeat_param);
+  ASSERT_TRUE(Parser.parse());
+
+  ASSERT_TRUE(Consumer->isSatisfied());
+}
+
+TEST_F(ParseHLSLRootSignatureTest, InvalidRepeatedOptionalParameterTest) {
+  // This test will check that the parsing fails due the same optional
+  // parameter being specified multiple times
+  const llvm::StringLiteral Source = R"cc(
+    DescriptorTable(
+      CBV(space = 2, space = 0)
+    )
+  )cc";
+
+  TrivialModuleLoader ModLoader;
+  auto PP = createPP(Source, ModLoader);
+  auto TokLoc = SourceLocation();
+
+  hlsl::RootSignatureLexer Lexer(Source, TokLoc);
+  SmallVector<RootElement> Elements;
+  hlsl::RootSignatureParser Parser(Elements, Lexer, *PP);
+
+  // Test correct diagnostic produced
+  Consumer->setExpected(diag::err_hlsl_rootsig_repeat_param);
+  ASSERT_TRUE(Parser.parse());
+
+  ASSERT_TRUE(Consumer->isSatisfied());
+}
+
+TEST_F(ParseHLSLRootSignatureTest, InvalidLexOverflowedNumberTest) {
+  // This test will check that the lexing fails due to an integer overflow
+  const llvm::StringLiteral Source = R"cc(
+    DescriptorTable(
+      CBV(b4294967296)
+    )
+  )cc";
+
+  TrivialModuleLoader ModLoader;
+  auto PP = createPP(Source, ModLoader);
+  auto TokLoc = SourceLocation();
+
+  hlsl::RootSignatureLexer Lexer(Source, TokLoc);
+  SmallVector<RootElement> Elements;
+  hlsl::RootSignatureParser Parser(Elements, Lexer, *PP);
+
+  // Test correct diagnostic produced
+  Consumer->setExpected(diag::err_hlsl_number_literal_overflow);
   ASSERT_TRUE(Parser.parse());
 
   ASSERT_TRUE(Consumer->isSatisfied());
diff --git a/clang/unittests/libclang/LibclangTest.cpp b/clang/unittests/libclang/LibclangTest.cpp
index 6de4d02bf74f4..b2a87d240e56e 100644
--- a/clang/unittests/libclang/LibclangTest.cpp
+++ b/clang/unittests/libclang/LibclangTest.cpp
@@ -1410,3 +1410,52 @@ TEST_F(LibclangRewriteTest, RewriteRemove) {
   ASSERT_EQ(clang_CXRewriter_overwriteChangedFiles(Rew), 0);
   EXPECT_EQ(getFileContent(Filename), "int () { return 0; }");
 }
+
+TEST_F(LibclangParseTest, FileEqual) {
+  std::string AInc = "a.inc", BInc = "b.inc", Main = "main.cpp";
+  WriteFile(Main, "int a[] = {\n"
+                  "    #include \"a.inc\"\n"
+                  "};\n"
+                  "int b[] = {\n"
+                  "    #include \"b.inc\"\n"
+                  "};");
+  WriteFile(AInc, "1,2,3");
+  WriteFile(BInc, "1,2,3");
+
+  ClangTU = clang_parseTranslationUnit(Index, Main.c_str(), nullptr, 0, nullptr,
+                                       0, TUFlags);
+
+  CXFile AFile = clang_getFile(ClangTU, AInc.c_str()),
+         AFile2 = clang_getFile(ClangTU, AInc.c_str()),
+         BFile = clang_getFile(ClangTU, BInc.c_str()),
+         MainFile = clang_getFile(ClangTU, Main.c_str());
+
+  ASSERT_FALSE(clang_File_isEqual(MainFile, AFile));
+  ASSERT_FALSE(clang_File_isEqual(AFile, BFile));
+  ASSERT_TRUE(clang_File_isEqual(AFile, AFile2));
+}
+
+TEST_F(LibclangParseTest, FileEqualInMemory) {
+  std::string AInc = "a.inc", BInc = "b.inc", Main = "main.cpp";
+  MapUnsavedFile(Main, "int a[] = {\n"
+                       "    #include \"a.inc\"\n"
+                       "};\n"
+                       "int b[] = {\n"
+                       "    #include \"b.inc\"\n"
+                       "};");
+  MapUnsavedFile(AInc, "1,2,3");
+  MapUnsavedFile(BInc, "1,2,3");
+
+  ClangTU = clang_parseTranslationUnit(Index, UnsavedFiles[0].Filename, nullptr,
+                                       0, &UnsavedFiles.front(),
+                                       UnsavedFiles.size(), TUFlags);
+
+  CXFile AFile = clang_getFile(ClangTU, UnsavedFiles[1].Filename),
+         AFile2 = clang_getFile(ClangTU, UnsavedFiles[1].Filename),
+         BFile = clang_getFile(ClangTU, UnsavedFiles[2].Filename),
+         MainFile = clang_getFile(ClangTU, UnsavedFiles[0].Filename);
+
+  ASSERT_FALSE(clang_File_isEqual(MainFile, AFile));
+  ASSERT_FALSE(clang_File_isEqual(AFile, BFile));
+  ASSERT_TRUE(clang_File_isEqual(AFile, AFile2));
+}
diff --git a/compiler-rt/lib/asan/asan_report.cpp b/compiler-rt/lib/asan/asan_report.cpp
index 8b22aebe7cafc..e049a21e4e16d 100644
--- a/compiler-rt/lib/asan/asan_report.cpp
+++ b/compiler-rt/lib/asan/asan_report.cpp
@@ -21,6 +21,7 @@
 #include "asan_scariness_score.h"
 #include "asan_stack.h"
 #include "asan_thread.h"
+#include "lsan/lsan_common.h"
 #include "sanitizer_common/sanitizer_common.h"
 #include "sanitizer_common/sanitizer_flags.h"
 #include "sanitizer_common/sanitizer_interface_internal.h"
@@ -149,7 +150,7 @@ class ScopedInErrorReport {
     // 2. Subsequent error reporting avoids nested lock acquisition patterns.
     // 3. Eliminates the lock order inversion risk between libdl and ASan's
     //    thread registry.
-#if !SANITIZER_SYMBOLIZER_MARKUP
+#if CAN_SANITIZE_LEAKS && (SANITIZER_LINUX || SANITIZER_NETBSD)
     Symbolizer::GetOrInit()->GetRefreshedListOfModules();
 #endif
 
diff --git a/compiler-rt/test/tsan/stack_race3.cpp b/compiler-rt/test/tsan/stack_race3.cpp
new file mode 100644
index 0000000000000..c50f4ad4c35cc
--- /dev/null
+++ b/compiler-rt/test/tsan/stack_race3.cpp
@@ -0,0 +1,21 @@
+// RUN: %clangxx_tsan -O1 %s -o %t && %deflake %run %t | FileCheck %s
+#include "test.h"
+
+void *Thread(void *a) {
+  barrier_wait(&barrier);
+  ((int *)a)[1] = 43;
+  return 0;
+}
+
+int main() {
+  barrier_init(&barrier, 2);
+  int Arr[2] = {41, 42};
+  pthread_t t;
+  pthread_create(&t, 0, Thread, &Arr[0]);
+  Arr[1] = 43;
+  barrier_wait(&barrier);
+  pthread_join(t, 0);
+}
+
+// CHECK: WARNING: ThreadSanitizer: data race
+// CHECK:   Location is stack of main thread.
diff --git a/flang-rt/lib/cuda/allocator.cpp b/flang-rt/lib/cuda/allocator.cpp
index a1c3a2c1b2ea8..51119ab251168 100644
--- a/flang-rt/lib/cuda/allocator.cpp
+++ b/flang-rt/lib/cuda/allocator.cpp
@@ -11,6 +11,7 @@
 #include "flang-rt/runtime/derived.h"
 #include "flang-rt/runtime/descriptor.h"
 #include "flang-rt/runtime/environment.h"
+#include "flang-rt/runtime/lock.h"
 #include "flang-rt/runtime/stat.h"
 #include "flang-rt/runtime/terminator.h"
 #include "flang-rt/runtime/type-info.h"
@@ -21,6 +22,105 @@
 #include "cuda_runtime.h"
 
 namespace Fortran::runtime::cuda {
+
+struct DeviceAllocation {
+  void *ptr;
+  std::size_t size;
+  cudaStream_t stream;
+};
+
+// Compare address values. nullptr will be sorted at the end of the array.
+int compareDeviceAlloc(const void *a, const void *b) {
+  const DeviceAllocation *deva = (const DeviceAllocation *)a;
+  const DeviceAllocation *devb = (const DeviceAllocation *)b;
+  if (deva->ptr == nullptr && devb->ptr == nullptr)
+    return 0;
+  if (deva->ptr == nullptr)
+    return 1;
+  if (devb->ptr == nullptr)
+    return -1;
+  return deva->ptr < devb->ptr ? -1 : (deva->ptr > devb->ptr ? 1 : 0);
+}
+
+// Dynamic array for tracking asynchronous allocations.
+static DeviceAllocation *deviceAllocations = nullptr;
+Lock lock;
+static int maxDeviceAllocations{512}; // Initial size
+static int numDeviceAllocations{0};
+static constexpr int allocNotFound{-1};
+
+static void initAllocations() {
+  if (!deviceAllocations) {
+    deviceAllocations = static_cast<DeviceAllocation *>(
+        malloc(maxDeviceAllocations * sizeof(DeviceAllocation)));
+    if (!deviceAllocations) {
+      Terminator terminator{__FILE__, __LINE__};
+      terminator.Crash("Failed to allocate tracking array");
+    }
+  }
+}
+
+static void doubleAllocationArray() {
+  unsigned newSize = maxDeviceAllocations * 2;
+  DeviceAllocation *newArray = static_cast<DeviceAllocation *>(
+      realloc(deviceAllocations, newSize * sizeof(DeviceAllocation)));
+  if (!newArray) {
+    Terminator terminator{__FILE__, __LINE__};
+    terminator.Crash("Failed to reallocate tracking array");
+  }
+  deviceAllocations = newArray;
+  maxDeviceAllocations = newSize;
+}
+
+static unsigned findAllocation(void *ptr) {
+  if (numDeviceAllocations == 0) {
+    return allocNotFound;
+  }
+
+  int left{0};
+  int right{numDeviceAllocations - 1};
+
+  if (left == right) {
+    return left;
+  }
+
+  while (left <= right) {
+    int mid = left + (right - left) / 2;
+    if (deviceAllocations[mid].ptr == ptr) {
+      return mid;
+    }
+    if (deviceAllocations[mid].ptr < ptr) {
+      left = mid + 1;
+    } else {
+      right = mid - 1;
+    }
+  }
+  return allocNotFound;
+}
+
+static void insertAllocation(void *ptr, std::size_t size, std::int64_t stream) {
+  CriticalSection critical{lock};
+  initAllocations();
+  if (numDeviceAllocations >= maxDeviceAllocations) {
+    doubleAllocationArray();
+  }
+  deviceAllocations[numDeviceAllocations].ptr = ptr;
+  deviceAllocations[numDeviceAllocations].size = size;
+  deviceAllocations[numDeviceAllocations].stream = (cudaStream_t)stream;
+  ++numDeviceAllocations;
+  qsort(deviceAllocations, numDeviceAllocations, sizeof(DeviceAllocation),
+      compareDeviceAlloc);
+}
+
+static void eraseAllocation(int pos) {
+  deviceAllocations[pos].ptr = nullptr;
+  deviceAllocations[pos].size = 0;
+  deviceAllocations[pos].stream = (cudaStream_t)0;
+  qsort(deviceAllocations, numDeviceAllocations, sizeof(DeviceAllocation),
+      compareDeviceAlloc);
+  --numDeviceAllocations;
+}
+
 extern "C" {
 
 void RTDEF(CUFRegisterAllocator)() {
@@ -55,12 +155,23 @@ void *CUFAllocDevice(std::size_t sizeInBytes, std::int64_t asyncId) {
     } else {
       CUDA_REPORT_IF_ERROR(
           cudaMallocAsync(&p, sizeInBytes, (cudaStream_t)asyncId));
+      insertAllocation(p, sizeInBytes, asyncId);
     }
   }
   return p;
 }
 
-void CUFFreeDevice(void *p) { CUDA_REPORT_IF_ERROR(cudaFree(p)); }
+void CUFFreeDevice(void *p) {
+  CriticalSection critical{lock};
+  int pos = findAllocation(p);
+  if (pos >= 0) {
+    cudaStream_t stream = deviceAllocations[pos].stream;
+    eraseAllocation(pos);
+    CUDA_REPORT_IF_ERROR(cudaFreeAsync(p, stream));
+  } else {
+    CUDA_REPORT_IF_ERROR(cudaFree(p));
+  }
+}
 
 void *CUFAllocManaged(
     std::size_t sizeInBytes, [[maybe_unused]] std::int64_t asyncId) {
diff --git a/flang-rt/unittests/Runtime/CUDA/Allocatable.cpp b/flang-rt/unittests/Runtime/CUDA/Allocatable.cpp
index 1c8ded0f87d4e..89649aa95ad93 100644
--- a/flang-rt/unittests/Runtime/CUDA/Allocatable.cpp
+++ b/flang-rt/unittests/Runtime/CUDA/Allocatable.cpp
@@ -58,3 +58,62 @@ TEST(AllocatableCUFTest, SimpleDeviceAllocatable) {
 
   EXPECT_EQ(cudaSuccess, cudaGetLastError());
 }
+
+TEST(AllocatableCUFTest, StreamDeviceAllocatable) {
+  using Fortran::common::TypeCategory;
+  RTNAME(CUFRegisterAllocator)();
+  // REAL(4), DEVICE, ALLOCATABLE :: a(:)
+  auto a{createAllocatable(TypeCategory::Real, 4)};
+  a->SetAllocIdx(kDeviceAllocatorPos);
+  EXPECT_EQ((int)kDeviceAllocatorPos, a->GetAllocIdx());
+  EXPECT_FALSE(a->HasAddendum());
+  RTNAME(AllocatableSetBounds)(*a, 0, 1, 10);
+
+  auto b{createAllocatable(TypeCategory::Real, 4)};
+  b->SetAllocIdx(kDeviceAllocatorPos);
+  EXPECT_EQ((int)kDeviceAllocatorPos, b->GetAllocIdx());
+  EXPECT_FALSE(b->HasAddendum());
+  RTNAME(AllocatableSetBounds)(*b, 0, 1, 20);
+
+  auto c{createAllocatable(TypeCategory::Real, 4)};
+  c->SetAllocIdx(kDeviceAllocatorPos);
+  EXPECT_EQ((int)kDeviceAllocatorPos, c->GetAllocIdx());
+  EXPECT_FALSE(b->HasAddendum());
+  RTNAME(AllocatableSetBounds)(*c, 0, 1, 100);
+
+  RTNAME(AllocatableAllocate)
+  (*a, 1, /*hasStat=*/false, /*errMsg=*/nullptr, __FILE__, __LINE__);
+  EXPECT_TRUE(a->IsAllocated());
+  cudaDeviceSynchronize();
+  EXPECT_EQ(cudaSuccess, cudaGetLastError());
+
+  RTNAME(AllocatableAllocate)
+  (*b, 1, /*hasStat=*/false, /*errMsg=*/nullptr, __FILE__, __LINE__);
+  EXPECT_TRUE(b->IsAllocated());
+  cudaDeviceSynchronize();
+  EXPECT_EQ(cudaSuccess, cudaGetLastError());
+
+  RTNAME(AllocatableAllocate)
+  (*c, 1, /*hasStat=*/false, /*errMsg=*/nullptr, __FILE__, __LINE__);
+  EXPECT_TRUE(c->IsAllocated());
+  cudaDeviceSynchronize();
+  EXPECT_EQ(cudaSuccess, cudaGetLastError());
+
+  RTNAME(AllocatableDeallocate)
+  (*b, /*hasStat=*/false, /*errMsg=*/nullptr, __FILE__, __LINE__);
+  EXPECT_FALSE(b->IsAllocated());
+  cudaDeviceSynchronize();
+  EXPECT_EQ(cudaSuccess, cudaGetLastError());
+
+  RTNAME(AllocatableDeallocate)
+  (*a, /*hasStat=*/false, /*errMsg=*/nullptr, __FILE__, __LINE__);
+  EXPECT_FALSE(a->IsAllocated());
+  cudaDeviceSynchronize();
+  EXPECT_EQ(cudaSuccess, cudaGetLastError());
+
+  RTNAME(AllocatableDeallocate)
+  (*c, /*hasStat=*/false, /*errMsg=*/nullptr, __FILE__, __LINE__);
+  EXPECT_FALSE(c->IsAllocated());
+  cudaDeviceSynchronize();
+  EXPECT_EQ(cudaSuccess, cudaGetLastError());
+}
diff --git a/flang/CMakeLists.txt b/flang/CMakeLists.txt
index 76eb13295eb07..ed02fad6a6e66 100644
--- a/flang/CMakeLists.txt
+++ b/flang/CMakeLists.txt
@@ -452,6 +452,10 @@ if (LLVM_COMPILER_IS_GCC_COMPATIBLE)
    set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} -fno-semantic-interposition")
   endif()
 
+  # GCC requires this flag in order for precompiled headers to work with ccache
+  if (CMAKE_CXX_COMPILER_ID STREQUAL "GNU" AND NOT CMAKE_DISABLE_PRECOMPILE_HEADERS)
+    set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fpch-preprocess")
+  endif()
 endif()
 
 # Clang on Darwin enables non-POSIX extensions by default, which allows the
@@ -462,6 +466,11 @@ if (APPLE)
   set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -D_POSIX_C_SOURCE=200809")
 endif()
 
+# Clang requires this flag in order for precompiled headers to work with ccache
+if (CMAKE_CXX_COMPILER_ID MATCHES "Clang" AND NOT CMAKE_DISABLE_PRECOMPILE_HEADERS)
+  set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Xclang -fno-pch-timestamp")
+endif()
+
 list(REMOVE_DUPLICATES CMAKE_CXX_FLAGS)
 
 # Determine HOST_LINK_VERSION on Darwin.
diff --git a/flang/docs/FortranStandardsSupport.md b/flang/docs/FortranStandardsSupport.md
new file mode 100644
index 0000000000000..78f5aa4f5dd8d
--- /dev/null
+++ b/flang/docs/FortranStandardsSupport.md
@@ -0,0 +1,118 @@
+<!--===- docs/FortranStandardsSupport.md
+
+   Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+   See https://llvm.org/LICENSE.txt for license information.
+   SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+-->
+
+# Flang Fortran Standards Support
+
+```{contents}
+---
+local:
+---
+```
+
+This document summarizes Fortran standards support in Flang. The information is only provided as a guideline. The
+TODOs/Not Yet Implemented messages emitted by the compiler for unimplemented features should be treated as authoritative.
+
+The standards support information is provided as a table with three columns that are self explanatory.
+The Status column uses the letters **Y**, **P**, **N** for the implementation status:
+- **Y** : Yes. When the implementation is complete
+- **P** : Partial. When the implementation is incomplete for a few cases
+- **N** : No. When the implementation is absent
+
+There is no distinction made between support in the Parser/Semantics and the MLIR or Lowering stages.
+
+Note: The two major missing features in Flang at present are coarrays and parameterized derived types (PDTs) with length type parameters.
+
+
+## Fortran 2023
+See [document](F202X.md) for a brief discussion about the new features in Fortran 2023. The following table summarizes the
+status of all important Fortran 2023 features. The table entries are based on the document [The new features in Fortran 2023](https://wg5-fortran.org/N2201-N2250/N2212.pdf).
+
+| Feature                                                    | Status | Comments                                                |
+|------------------------------------------------------------|--------|---------------------------------------------------------|
+| Allow longer statement lines and overall statement length  | Y      | |
+| Automatic allocation of lengths of character variables     | N      | |
+| The specifiers typeof and classof                          | N      | |
+| Conditional expressions and arguments                      | N      | |
+| More use of boz constants                                  | P      | All usages other than enum are supported |
+| Intrinsics for extracting tokens from a string             | N      | |
+| Intrinsics for Trig functions that work in degrees         | N      | |
+| Intrinsics for Trig functions that work in half revolutions| N      | |
+| Changes to system_clock                                    | N      | |
+| Changes for conformance with the new IEEE standard         | Y      | |
+| Additional named constants to specify kinds                | Y      | |
+| Extensions for c_f_pointer intrinsic                       | N      | |
+| Procedures for converting between fortran and c strings    | N      | |
+| The at edit descriptor                                     | N      | |
+| Control over leading zeros in output of real values        | N      | |
+| Extensions for Namelist                                    | N      | |
+| Allow an object of a type with a coarray ultimate component to be an array or allocatable | N | |
+| Put with Notify                                            | N      | |
+| Error conditions in collectives                            | N      | |
+| Simple procedures                                          | N      | |
+| Using integer arrays to specify subscripts                 | N      | |
+| Using integer arrays to specify rank and bound of an array | N      | |
+| Using an integer constant to specify rank                  | N      | |
+| Reduction specifier for do concurrent                      | P      | Syntax is accepted |
+| Enumerations                                               | N      | |
+
+## Fortran 2018
+All features except those listed in the following table are supported. Almost all of the unsupported features are related to
+the multi-image execution. The table entries are based on the document [The new features in Fortran 2018](https://wg5-fortran.org/N2151-N2200/ISO-IECJTC1-SC22-WG5_N2161_The_New_Features_of_Fortran_2018.pdf).
+
+| Feature                                                    | Status | Comments                                                |
+|------------------------------------------------------------|--------|---------------------------------------------------------|
+| Asynchronous communication                                 | P      | Syntax is accepted |
+| Teams                                                      | N      | Multi-image/Coarray feature |
+| Image failure                                              | P      | Multi-image/Coarray feature. stat_failed_image is added |
+| Form team statement                                        | N      | Multi-image/Coarray feature |
+| Change team construct                                      | N      | Multi-image/Coarray feature |
+| Coarrays allocated in teams                                | N      | Multi-image/Coarray feature |
+| Critical construct                                         | N      | Multi-image/Coarray feature |
+| Lock and unlock statements                                 | N      | Multi-image/Coarray feature |
+| Events                                                     | N      | Multi-image/Coarray feature |
+| Sync team construct                                        | N      | Multi-image/Coarray feature |
+| Image selectors                                            | N      | Multi-image/Coarray feature |
+| Intrinsic functions get_team 	and team_number              | N      | Multi-image/Coarray feature |
+| Intrinsic function image_index                             | N      | Multi-image/Coarray feature |
+| Intrinsic function num_images                              | N      | Multi-image/Coarray feature |
+| Intrinsic function this_image                              | N      | Multi-image/Coarray feature |
+| Intrinsic move_alloc extensions                            | P      | Multi-image/Coarray feature |
+| Detecting failed and stopped images                        | N      | Multi-image/Coarray feature |
+| Collective subroutines                                     | N      | Multi-image/Coarray feature |
+| New and enhanced atomic subroutines                        | N      | Multi-image/Coarray feature |
+| Failed images and stat= specifiers                         | N      | Multi-image/Coarray feature |
+| Intrinsic function coshape                                 | N      | Multi-image/Coarray feature |
+
+## Fortran 2008
+All features except those listed in the following table are supported.
+
+| Feature                                                    | Status | Comments                                                |
+|------------------------------------------------------------|--------|---------------------------------------------------------|
+| Coarrays                                                   | N      | Lowering and runtime support is not implemented         |
+| do concurrent                                              | P      | Sequential execution works. Parallel support in progress|
+| Internal procedure as an actual argument or pointer target | Y      | Current implementation requires stack to be executable. See [Proposal](InternalProcedureTrampolines.md) |
+
+## Fortran 2003
+All features except those listed in the following table are supported.
+
+| Feature                                                    | Status | Comments                                                |
+|------------------------------------------------------------|--------|---------------------------------------------------------|
+| Parameterized Derived Types                                | P      | PDT with length type parameters is not supported. See [Proposal](ParameterizedDerivedTypes.md) |
+| Assignment to allocatable                                  | P      | Assignment to whole allocatable in FORALL is not implemented       |
+| The VOLATILE attribute                                     | P      | VOLATILE in procedure interfaces is not implemented     |
+| Asynchronous input/output                                  | P      | IO will happen synchronously                            |
+| MIN/MAX extensions for CHARACTER                           | P      | Some variants are not supported                         |
+
+## Fortran 95
+All features are supported.
+
+## Fortran 90
+All features are supported.
+
+## FORTRAN 77
+All features are supported.
diff --git a/flang/docs/index.md b/flang/docs/index.md
index aedd3a6a45d6f..2568ad70c5d09 100644
--- a/flang/docs/index.md
+++ b/flang/docs/index.md
@@ -26,6 +26,7 @@ on how to get in touch with us and to learn more about the current status.
    C++style
    DesignGuideline
    FortranForCProgrammers
+   FortranStandardsSupport
    GettingInvolved
    GettingStarted
    ImplementingASemanticCheck
diff --git a/flang/examples/FeatureList/FeatureList.cpp b/flang/examples/FeatureList/FeatureList.cpp
index 94fdfa3e4dea9..d1407cf0ef239 100644
--- a/flang/examples/FeatureList/FeatureList.cpp
+++ b/flang/examples/FeatureList/FeatureList.cpp
@@ -564,11 +564,11 @@ struct NodeVisitor {
   READ_FEATURE(OpenMPDeclareReductionConstruct)
   READ_FEATURE(OpenMPDeclareSimdConstruct)
   READ_FEATURE(OpenMPDeclareTargetConstruct)
+  READ_FEATURE(OmpMemoryOrderType)
   READ_FEATURE(OmpMemoryOrderClause)
   READ_FEATURE(OmpAtomicClause)
   READ_FEATURE(OmpAtomicClauseList)
   READ_FEATURE(OmpAtomicDefaultMemOrderClause)
-  READ_FEATURE(OmpAtomicDefaultMemOrderType)
   READ_FEATURE(OpenMPFlushConstruct)
   READ_FEATURE(OpenMPLoopConstruct)
   READ_FEATURE(OpenMPExecutableAllocate)
diff --git a/flang/include/flang/Lower/DirectivesCommon.h b/flang/include/flang/Lower/DirectivesCommon.h
index 688d37709f88b..d1dbaefcd81d0 100644
--- a/flang/include/flang/Lower/DirectivesCommon.h
+++ b/flang/include/flang/Lower/DirectivesCommon.h
@@ -55,36 +55,42 @@ static inline void genOmpAtomicHintAndMemoryOrderClauses(
     mlir::omp::ClauseMemoryOrderKindAttr &memoryOrder) {
   fir::FirOpBuilder &firOpBuilder = converter.getFirOpBuilder();
   for (const Fortran::parser::OmpAtomicClause &clause : clauseList.v) {
-    if (const auto *hintClause =
-            std::get_if<Fortran::parser::OmpHintClause>(&clause.u)) {
-      const auto *expr = Fortran::semantics::GetExpr(hintClause->v);
-      uint64_t hintExprValue = *Fortran::evaluate::ToInt64(*expr);
-      hint = firOpBuilder.getI64IntegerAttr(hintExprValue);
-    } else if (const auto *ompMemoryOrderClause =
-                   std::get_if<Fortran::parser::OmpMemoryOrderClause>(
-                       &clause.u)) {
-      if (std::get_if<Fortran::parser::OmpClause::Acquire>(
-              &ompMemoryOrderClause->v.u)) {
-        memoryOrder = mlir::omp::ClauseMemoryOrderKindAttr::get(
-            firOpBuilder.getContext(),
-            mlir::omp::ClauseMemoryOrderKind::Acquire);
-      } else if (std::get_if<Fortran::parser::OmpClause::Relaxed>(
-                     &ompMemoryOrderClause->v.u)) {
-        memoryOrder = mlir::omp::ClauseMemoryOrderKindAttr::get(
-            firOpBuilder.getContext(),
-            mlir::omp::ClauseMemoryOrderKind::Relaxed);
-      } else if (std::get_if<Fortran::parser::OmpClause::SeqCst>(
-                     &ompMemoryOrderClause->v.u)) {
-        memoryOrder = mlir::omp::ClauseMemoryOrderKindAttr::get(
-            firOpBuilder.getContext(),
-            mlir::omp::ClauseMemoryOrderKind::Seq_cst);
-      } else if (std::get_if<Fortran::parser::OmpClause::Release>(
-                     &ompMemoryOrderClause->v.u)) {
-        memoryOrder = mlir::omp::ClauseMemoryOrderKindAttr::get(
-            firOpBuilder.getContext(),
-            mlir::omp::ClauseMemoryOrderKind::Release);
-      }
-    }
+    common::visit(
+        common::visitors{
+            [&](const parser::OmpMemoryOrderClause &s) {
+              auto kind = common::visit(
+                  common::visitors{
+                      [&](const parser::OmpClause::AcqRel &) {
+                        return mlir::omp::ClauseMemoryOrderKind::Acq_rel;
+                      },
+                      [&](const parser::OmpClause::Acquire &) {
+                        return mlir::omp::ClauseMemoryOrderKind::Acquire;
+                      },
+                      [&](const parser::OmpClause::Relaxed &) {
+                        return mlir::omp::ClauseMemoryOrderKind::Relaxed;
+                      },
+                      [&](const parser::OmpClause::Release &) {
+                        return mlir::omp::ClauseMemoryOrderKind::Release;
+                      },
+                      [&](const parser::OmpClause::SeqCst &) {
+                        return mlir::omp::ClauseMemoryOrderKind::Seq_cst;
+                      },
+                      [&](auto &&) -> mlir::omp::ClauseMemoryOrderKind {
+                        llvm_unreachable("Unexpected clause");
+                      },
+                  },
+                  s.v.u);
+              memoryOrder = mlir::omp::ClauseMemoryOrderKindAttr::get(
+                  firOpBuilder.getContext(), kind);
+            },
+            [&](const parser::OmpHintClause &s) {
+              const auto *expr = Fortran::semantics::GetExpr(s.v);
+              uint64_t hintExprValue = *Fortran::evaluate::ToInt64(*expr);
+              hint = firOpBuilder.getI64IntegerAttr(hintExprValue);
+            },
+            [&](const parser::OmpFailClause &) {},
+        },
+        clause.u);
   }
 }
 
diff --git a/flang/include/flang/Parser/dump-parse-tree.h b/flang/include/flang/Parser/dump-parse-tree.h
index 42f2ff376c650..c0cf90c4696b6 100644
--- a/flang/include/flang/Parser/dump-parse-tree.h
+++ b/flang/include/flang/Parser/dump-parse-tree.h
@@ -707,11 +707,11 @@ class ParseTreeDumper {
   NODE(parser, OpenMPDeclareSimdConstruct)
   NODE(parser, OpenMPDeclareTargetConstruct)
   NODE(parser, OpenMPDeclareMapperConstruct)
+  NODE_ENUM(common, OmpMemoryOrderType)
   NODE(parser, OmpMemoryOrderClause)
   NODE(parser, OmpAtomicClause)
   NODE(parser, OmpAtomicClauseList)
   NODE(parser, OmpAtomicDefaultMemOrderClause)
-  NODE_ENUM(common, OmpAtomicDefaultMemOrderType)
   NODE(parser, OpenMPDepobjConstruct)
   NODE(parser, OpenMPUtilityConstruct)
   NODE(parser, OpenMPDispatchConstruct)
diff --git a/flang/include/flang/Parser/parse-tree.h b/flang/include/flang/Parser/parse-tree.h
index 2f45faec42c8f..ca8473c6f9674 100644
--- a/flang/include/flang/Parser/parse-tree.h
+++ b/flang/include/flang/Parser/parse-tree.h
@@ -4071,7 +4071,7 @@ struct OmpAtClause {
 //    SEQ_CST | ACQ_REL | RELAXED |                 // since 5.0
 //    ACQUIRE | RELEASE                             // since 5.2
 struct OmpAtomicDefaultMemOrderClause {
-  using MemoryOrder = common::OmpAtomicDefaultMemOrderType;
+  using MemoryOrder = common::OmpMemoryOrderType;
   WRAPPER_CLASS_BOILERPLATE(OmpAtomicDefaultMemOrderClause, MemoryOrder);
 };
 
@@ -4242,9 +4242,8 @@ struct OmpDeviceTypeClause {
 // OMP 5.2 15.8.3 extended-atomic, fail-clause ->
 //    FAIL(memory-order)
 struct OmpFailClause {
-  WRAPPER_CLASS_BOILERPLATE(
-      OmpFailClause, common::Indirection<OmpMemoryOrderClause>);
-  CharBlock source;
+  using MemoryOrder = common::OmpMemoryOrderType;
+  WRAPPER_CLASS_BOILERPLATE(OmpFailClause, MemoryOrder);
 };
 
 // Ref: [4.5:107-109], [5.0:176-180], [5.1:205-210], [5.2:167-168]
@@ -4822,10 +4821,10 @@ struct OpenMPAllocatorsConstruct {
 
 // 2.17.7 Atomic construct/2.17.8 Flush construct [OpenMP 5.0]
 //        memory-order-clause -> acq_rel
-//                               release
 //                               acquire
-//                               seq_cst
+//                               release
 //                               relaxed
+//                               seq_cst
 struct OmpMemoryOrderClause {
   WRAPPER_CLASS_BOILERPLATE(OmpMemoryOrderClause, OmpClause);
   CharBlock source;
diff --git a/flang/include/flang/Semantics/symbol.h b/flang/include/flang/Semantics/symbol.h
index 715811885c219..36d926a8a4bc5 100644
--- a/flang/include/flang/Semantics/symbol.h
+++ b/flang/include/flang/Semantics/symbol.h
@@ -48,7 +48,7 @@ using MutableSymbolVector = std::vector<MutableSymbolRef>;
 
 // Mixin for details with OpenMP declarative constructs.
 class WithOmpDeclarative {
-  using OmpAtomicOrderType = common::OmpAtomicDefaultMemOrderType;
+  using OmpAtomicOrderType = common::OmpMemoryOrderType;
 
 public:
   ENUM_CLASS(RequiresFlag, ReverseOffload, UnifiedAddress, UnifiedSharedMemory,
diff --git a/flang/include/flang/Support/Fortran.h b/flang/include/flang/Support/Fortran.h
index 6ce053926c1e7..0b4fc1a608e9e 100644
--- a/flang/include/flang/Support/Fortran.h
+++ b/flang/include/flang/Support/Fortran.h
@@ -72,8 +72,8 @@ ENUM_CLASS(
 ENUM_CLASS(
     OpenACCDeviceType, Star, Default, Nvidia, Radeon, Host, Multicore, None)
 
-// OpenMP atomic_default_mem_order clause allowed values
-ENUM_CLASS(OmpAtomicDefaultMemOrderType, SeqCst, AcqRel, Relaxed)
+// OpenMP memory-order types
+ENUM_CLASS(OmpMemoryOrderType, Acq_Rel, Acquire, Relaxed, Release, Seq_Cst)
 
 // Fortran names may have up to 63 characters (See Fortran 2018 C601).
 static constexpr int maxNameLen{63};
diff --git a/flang/lib/Lower/OpenMP/Clauses.cpp b/flang/lib/Lower/OpenMP/Clauses.cpp
index 3f0748382116b..f1330b8d1909f 100644
--- a/flang/lib/Lower/OpenMP/Clauses.cpp
+++ b/flang/lib/Lower/OpenMP/Clauses.cpp
@@ -494,12 +494,13 @@ AtomicDefaultMemOrder make(const parser::OmpClause::AtomicDefaultMemOrder &inp,
                            semantics::SemanticsContext &semaCtx) {
   // inp.v -> parser::OmpAtomicDefaultMemOrderClause
   CLAUSET_ENUM_CONVERT( //
-      convert, common::OmpAtomicDefaultMemOrderType,
-      AtomicDefaultMemOrder::MemoryOrder,
+      convert, common::OmpMemoryOrderType, AtomicDefaultMemOrder::MemoryOrder,
       // clang-format off
-      MS(AcqRel,   AcqRel)
+      MS(Acq_Rel,  AcqRel)
+      MS(Acquire,  Acquire)
       MS(Relaxed,  Relaxed)
-      MS(SeqCst,   SeqCst)
+      MS(Release,  Release)
+      MS(Seq_Cst,  SeqCst)
       // clang-format on
   );
 
@@ -784,8 +785,19 @@ Exclusive make(const parser::OmpClause::Exclusive &inp,
 
 Fail make(const parser::OmpClause::Fail &inp,
           semantics::SemanticsContext &semaCtx) {
-  // inp -> empty
-  llvm_unreachable("Empty: fail");
+  // inp.v -> parser::OmpFalClause
+  CLAUSET_ENUM_CONVERT( //
+      convert, common::OmpMemoryOrderType, Fail::MemoryOrder,
+      // clang-format off
+      MS(Acq_Rel,  AcqRel)
+      MS(Acquire,  Acquire)
+      MS(Relaxed,  Relaxed)
+      MS(Release,  Release)
+      MS(Seq_Cst,  SeqCst)
+      // clang-format on
+  );
+
+  return Fail{/*MemoryOrder=*/convert(inp.v.v)};
 }
 
 Filter make(const parser::OmpClause::Filter &inp,
diff --git a/flang/lib/Optimizer/CodeGen/LowerRepackArrays.cpp b/flang/lib/Optimizer/CodeGen/LowerRepackArrays.cpp
index 7deed3d44ae5b..7fb713ff1a6c7 100644
--- a/flang/lib/Optimizer/CodeGen/LowerRepackArrays.cpp
+++ b/flang/lib/Optimizer/CodeGen/LowerRepackArrays.cpp
@@ -357,8 +357,8 @@ class LowerRepackArraysPass
     patterns.insert<PackArrayConversion>(context);
     patterns.insert<UnpackArrayConversion>(context);
     mlir::GreedyRewriteConfig config;
-    config.enableRegionSimplification =
-        mlir::GreedySimplifyRegionLevel::Disabled;
+    config.setRegionSimplificationLevel(
+        mlir::GreedySimplifyRegionLevel::Disabled);
     (void)applyPatternsGreedily(module, std::move(patterns), config);
   }
 
diff --git a/flang/lib/Optimizer/CodeGen/TargetRewrite.cpp b/flang/lib/Optimizer/CodeGen/TargetRewrite.cpp
index 6f5e01612fc97..05ebc46cab1b2 100644
--- a/flang/lib/Optimizer/CodeGen/TargetRewrite.cpp
+++ b/flang/lib/Optimizer/CodeGen/TargetRewrite.cpp
@@ -531,6 +531,11 @@ class TargetRewrite : public fir::impl::TargetRewritePassBase<TargetRewrite> {
       if (callOp.getClusterSizeZ())
         newCall.getClusterSizeZMutable().assign(callOp.getClusterSizeZ());
       newCallResults.append(newCall.result_begin(), newCall.result_end());
+      if (auto cudaProcAttr =
+              callOp->template getAttrOfType<cuf::ProcAttributeAttr>(
+                  cuf::getProcAttrName())) {
+        newCall->setAttr(cuf::getProcAttrName(), cudaProcAttr);
+      }
     } else if constexpr (std::is_same_v<std::decay_t<A>, fir::CallOp>) {
       fir::CallOp newCall;
       if (callOp.getCallee()) {
diff --git a/flang/lib/Optimizer/Dialect/CUF/CUFToLLVMIRTranslation.cpp b/flang/lib/Optimizer/Dialect/CUF/CUFToLLVMIRTranslation.cpp
index 7ed7f35595968..5c4e4179d2dee 100644
--- a/flang/lib/Optimizer/Dialect/CUF/CUFToLLVMIRTranslation.cpp
+++ b/flang/lib/Optimizer/Dialect/CUF/CUFToLLVMIRTranslation.cpp
@@ -28,7 +28,7 @@ LogicalResult registerModule(cuf::RegisterModuleOp op,
                              llvm::IRBuilderBase &builder,
                              LLVM::ModuleTranslation &moduleTranslation) {
   std::string binaryIdentifier =
-      op.getName().getLeafReference().str() + "_bin_cst";
+      op.getName().getLeafReference().str() + "_binary";
   llvm::Module *module = moduleTranslation.getLLVMModule();
   llvm::Value *binary = module->getGlobalVariable(binaryIdentifier, true);
   if (!binary)
diff --git a/flang/lib/Optimizer/HLFIR/Transforms/InlineElementals.cpp b/flang/lib/Optimizer/HLFIR/Transforms/InlineElementals.cpp
index b68fe6ee0c747..c42b895946d19 100644
--- a/flang/lib/Optimizer/HLFIR/Transforms/InlineElementals.cpp
+++ b/flang/lib/Optimizer/HLFIR/Transforms/InlineElementals.cpp
@@ -119,8 +119,8 @@ class InlineElementalsPass
 
     mlir::GreedyRewriteConfig config;
     // Prevent the pattern driver from merging blocks.
-    config.enableRegionSimplification =
-        mlir::GreedySimplifyRegionLevel::Disabled;
+    config.setRegionSimplificationLevel(
+        mlir::GreedySimplifyRegionLevel::Disabled);
 
     mlir::RewritePatternSet patterns(context);
     patterns.insert<InlineElementalConversion>(context);
diff --git a/flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRAssign.cpp b/flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRAssign.cpp
index 249976d5509b0..6e209cce07ad4 100644
--- a/flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRAssign.cpp
+++ b/flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRAssign.cpp
@@ -135,8 +135,8 @@ class InlineHLFIRAssignPass
 
     mlir::GreedyRewriteConfig config;
     // Prevent the pattern driver from merging blocks.
-    config.enableRegionSimplification =
-        mlir::GreedySimplifyRegionLevel::Disabled;
+    config.setRegionSimplificationLevel(
+        mlir::GreedySimplifyRegionLevel::Disabled);
 
     mlir::RewritePatternSet patterns(context);
     patterns.insert<InlineHLFIRAssignConversion>(context);
diff --git a/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp b/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp
index 7c0fcba806869..31e5bc1193e22 100644
--- a/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp
+++ b/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp
@@ -557,8 +557,8 @@ class LowerHLFIRIntrinsics
     // Pattern rewriting only requires that the resulting IR is still valid
     mlir::GreedyRewriteConfig config;
     // Prevent the pattern driver from merging blocks
-    config.enableRegionSimplification =
-        mlir::GreedySimplifyRegionLevel::Disabled;
+    config.setRegionSimplificationLevel(
+        mlir::GreedySimplifyRegionLevel::Disabled);
 
     if (mlir::failed(
             mlir::applyPatternsGreedily(module, std::move(patterns), config))) {
diff --git a/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp b/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
index 79aabd2981e1a..2f6ee2592a84f 100644
--- a/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
+++ b/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
@@ -875,8 +875,8 @@ class OptimizedBufferizationPass
 
     mlir::GreedyRewriteConfig config;
     // Prevent the pattern driver from merging blocks
-    config.enableRegionSimplification =
-        mlir::GreedySimplifyRegionLevel::Disabled;
+    config.setRegionSimplificationLevel(
+        mlir::GreedySimplifyRegionLevel::Disabled);
 
     mlir::RewritePatternSet patterns(context);
     // TODO: right now the patterns are non-conflicting,
diff --git a/flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp b/flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
index e9d820adbd22b..1dea7d89e180d 100644
--- a/flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
+++ b/flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
@@ -2132,8 +2132,8 @@ class SimplifyHLFIRIntrinsics
 
     mlir::GreedyRewriteConfig config;
     // Prevent the pattern driver from merging blocks
-    config.enableRegionSimplification =
-        mlir::GreedySimplifyRegionLevel::Disabled;
+    config.setRegionSimplificationLevel(
+        mlir::GreedySimplifyRegionLevel::Disabled);
 
     mlir::RewritePatternSet patterns(context);
     patterns.insert<TransposeAsElementalConversion>(context);
diff --git a/flang/lib/Optimizer/Passes/Pipelines.cpp b/flang/lib/Optimizer/Passes/Pipelines.cpp
index 81ff6bf9b2c6a..7a06a27748ebd 100644
--- a/flang/lib/Optimizer/Passes/Pipelines.cpp
+++ b/flang/lib/Optimizer/Passes/Pipelines.cpp
@@ -35,7 +35,8 @@ void addNestedPassToAllTopLevelOperationsConditionally(
 
 void addCanonicalizerPassWithoutRegionSimplification(mlir::OpPassManager &pm) {
   mlir::GreedyRewriteConfig config;
-  config.enableRegionSimplification = mlir::GreedySimplifyRegionLevel::Disabled;
+  config.setRegionSimplificationLevel(
+      mlir::GreedySimplifyRegionLevel::Disabled);
   pm.addPass(mlir::createCanonicalizerPass(config));
 }
 
@@ -163,7 +164,8 @@ void createDefaultFIROptimizerPassPipeline(mlir::PassManager &pm,
 
   // simplify the IR
   mlir::GreedyRewriteConfig config;
-  config.enableRegionSimplification = mlir::GreedySimplifyRegionLevel::Disabled;
+  config.setRegionSimplificationLevel(
+      mlir::GreedySimplifyRegionLevel::Disabled);
   pm.addPass(mlir::createCSEPass());
   fir::addAVC(pm, pc.OptLevel);
   addNestedPassToAllTopLevelOperations<PassConstructor>(
diff --git a/flang/lib/Optimizer/Transforms/AssumedRankOpConversion.cpp b/flang/lib/Optimizer/Transforms/AssumedRankOpConversion.cpp
index d0bd67a236419..6af1cb988a4c1 100644
--- a/flang/lib/Optimizer/Transforms/AssumedRankOpConversion.cpp
+++ b/flang/lib/Optimizer/Transforms/AssumedRankOpConversion.cpp
@@ -152,8 +152,8 @@ class AssumedRankOpConversion
     patterns.insert<ReboxAssumedRankConv>(context, &symbolTable, kindMap);
     patterns.insert<IsAssumedSizeConv>(context, &symbolTable, kindMap);
     mlir::GreedyRewriteConfig config;
-    config.enableRegionSimplification =
-        mlir::GreedySimplifyRegionLevel::Disabled;
+    config.setRegionSimplificationLevel(
+        mlir::GreedySimplifyRegionLevel::Disabled);
     (void)applyPatternsGreedily(mod, std::move(patterns), config);
   }
 };
diff --git a/flang/lib/Optimizer/Transforms/ConstantArgumentGlobalisation.cpp b/flang/lib/Optimizer/Transforms/ConstantArgumentGlobalisation.cpp
index 562f3058f20f3..239a7cdaa4cf2 100644
--- a/flang/lib/Optimizer/Transforms/ConstantArgumentGlobalisation.cpp
+++ b/flang/lib/Optimizer/Transforms/ConstantArgumentGlobalisation.cpp
@@ -168,9 +168,9 @@ class ConstantArgumentGlobalisationOpt
     auto *context = &getContext();
     mlir::RewritePatternSet patterns(context);
     mlir::GreedyRewriteConfig config;
-    config.enableRegionSimplification =
-        mlir::GreedySimplifyRegionLevel::Disabled;
-    config.strictMode = mlir::GreedyRewriteStrictness::ExistingOps;
+    config.setRegionSimplificationLevel(
+        mlir::GreedySimplifyRegionLevel::Disabled);
+    config.setStrictness(mlir::GreedyRewriteStrictness::ExistingOps);
 
     patterns.insert<CallOpRewriter>(context, *di);
     if (mlir::failed(
diff --git a/flang/lib/Optimizer/Transforms/SimplifyFIROperations.cpp b/flang/lib/Optimizer/Transforms/SimplifyFIROperations.cpp
index 212de2f2286db..6d106046b70f2 100644
--- a/flang/lib/Optimizer/Transforms/SimplifyFIROperations.cpp
+++ b/flang/lib/Optimizer/Transforms/SimplifyFIROperations.cpp
@@ -205,7 +205,8 @@ void SimplifyFIROperationsPass::runOnOperation() {
   fir::populateSimplifyFIROperationsPatterns(patterns,
                                              preferInlineImplementation);
   mlir::GreedyRewriteConfig config;
-  config.enableRegionSimplification = mlir::GreedySimplifyRegionLevel::Disabled;
+  config.setRegionSimplificationLevel(
+      mlir::GreedySimplifyRegionLevel::Disabled);
 
   if (mlir::failed(
           mlir::applyPatternsGreedily(module, std::move(patterns), config))) {
diff --git a/flang/lib/Optimizer/Transforms/StackArrays.cpp b/flang/lib/Optimizer/Transforms/StackArrays.cpp
index 9a6566bef50f1..f9b9b4f4ff385 100644
--- a/flang/lib/Optimizer/Transforms/StackArrays.cpp
+++ b/flang/lib/Optimizer/Transforms/StackArrays.cpp
@@ -806,7 +806,8 @@ void StackArraysPass::runOnOperation() {
   mlir::RewritePatternSet patterns(&context);
   mlir::GreedyRewriteConfig config;
   // prevent the pattern driver form merging blocks
-  config.enableRegionSimplification = mlir::GreedySimplifyRegionLevel::Disabled;
+  config.setRegionSimplificationLevel(
+      mlir::GreedySimplifyRegionLevel::Disabled);
 
   patterns.insert<AllocMemConversion>(&context, *candidateOps);
   if (mlir::failed(mlir::applyOpPatternsGreedily(
diff --git a/flang/lib/Parser/openmp-parsers.cpp b/flang/lib/Parser/openmp-parsers.cpp
index 57324810eac1e..e631922a354c4 100644
--- a/flang/lib/Parser/openmp-parsers.cpp
+++ b/flang/lib/Parser/openmp-parsers.cpp
@@ -636,6 +636,20 @@ TYPE_PARSER(construct<OmpAffinityClause>(
     maybe(nonemptyList(Parser<OmpAffinityClause::Modifier>{}) / ":"),
     Parser<OmpObjectList>{}))
 
+// 2.4 Requires construct [OpenMP 5.0]
+//        atomic-default-mem-order-clause ->
+//                               acq_rel
+//                               acquire
+//                               relaxed
+//                               release
+//                               seq_cst
+TYPE_PARSER(construct<OmpAtomicDefaultMemOrderClause>(
+    "ACQ_REL" >> pure(common::OmpMemoryOrderType::Acq_Rel) ||
+    "ACQUIRE" >> pure(common::OmpMemoryOrderType::Acquire) ||
+    "RELAXED" >> pure(common::OmpMemoryOrderType::Relaxed) ||
+    "RELEASE" >> pure(common::OmpMemoryOrderType::Release) ||
+    "SEQ_CST" >> pure(common::OmpMemoryOrderType::Seq_Cst)))
+
 TYPE_PARSER(construct<OmpCancellationConstructTypeClause>(
     OmpDirectiveNameParser{}, maybe(parenthesized(scalarLogicalExpr))))
 
@@ -652,6 +666,13 @@ TYPE_PARSER(construct<OmpDefaultClause>(
         Parser<OmpDefaultClause::DataSharingAttribute>{}) ||
     construct<OmpDefaultClause>(indirect(Parser<OmpDirectiveSpecification>{}))))
 
+TYPE_PARSER(construct<OmpFailClause>(
+    "ACQ_REL" >> pure(common::OmpMemoryOrderType::Acq_Rel) ||
+    "ACQUIRE" >> pure(common::OmpMemoryOrderType::Acquire) ||
+    "RELAXED" >> pure(common::OmpMemoryOrderType::Relaxed) ||
+    "RELEASE" >> pure(common::OmpMemoryOrderType::Release) ||
+    "SEQ_CST" >> pure(common::OmpMemoryOrderType::Seq_Cst)))
+
 // 2.5 PROC_BIND (MASTER | CLOSE | PRIMARY | SPREAD)
 TYPE_PARSER(construct<OmpProcBindClause>(
     "CLOSE" >> pure(OmpProcBindClause::AffinityPolicy::Close) ||
@@ -929,6 +950,8 @@ TYPE_PARSER( //
                    parenthesized(Parser<OmpObjectList>{}))) ||
     "EXCLUSIVE" >> construct<OmpClause>(construct<OmpClause::Exclusive>(
                        parenthesized(Parser<OmpObjectList>{}))) ||
+    "FAIL" >> construct<OmpClause>(construct<OmpClause::Fail>(
+                  parenthesized(Parser<OmpFailClause>{}))) ||
     "FILTER" >> construct<OmpClause>(construct<OmpClause::Filter>(
                     parenthesized(scalarIntExpr))) ||
     "FINAL" >> construct<OmpClause>(construct<OmpClause::Final>(
@@ -1187,38 +1210,26 @@ TYPE_PARSER(sourced(construct<OmpLoopDirective>(first(
 TYPE_PARSER(sourced(construct<OmpBeginLoopDirective>(
     sourced(Parser<OmpLoopDirective>{}), Parser<OmpClauseList>{})))
 
-TYPE_PARSER(sourced(construct<OmpFailClause>(
-    parenthesized(indirect(Parser<OmpMemoryOrderClause>{})))))
-
 // 2.17.7 Atomic construct/2.17.8 Flush construct [OpenMP 5.0]
 //        memory-order-clause ->
-//                               seq_cst
 //                               acq_rel
-//                               release
 //                               acquire
 //                               relaxed
+//                               release
+//                               seq_cst
 TYPE_PARSER(sourced(construct<OmpMemoryOrderClause>(
-    sourced("SEQ_CST" >> construct<OmpClause>(construct<OmpClause::SeqCst>()) ||
-        "ACQ_REL" >> construct<OmpClause>(construct<OmpClause::AcqRel>()) ||
-        "RELEASE" >> construct<OmpClause>(construct<OmpClause::Release>()) ||
+    sourced("ACQ_REL" >> construct<OmpClause>(construct<OmpClause::AcqRel>()) ||
         "ACQUIRE" >> construct<OmpClause>(construct<OmpClause::Acquire>()) ||
-        "RELAXED" >> construct<OmpClause>(construct<OmpClause::Relaxed>())))))
-
-// 2.4 Requires construct [OpenMP 5.0]
-//        atomic-default-mem-order-clause ->
-//                               seq_cst
-//                               acq_rel
-//                               relaxed
-TYPE_PARSER(construct<OmpAtomicDefaultMemOrderClause>(
-    "SEQ_CST" >> pure(common::OmpAtomicDefaultMemOrderType::SeqCst) ||
-    "ACQ_REL" >> pure(common::OmpAtomicDefaultMemOrderType::AcqRel) ||
-    "RELAXED" >> pure(common::OmpAtomicDefaultMemOrderType::Relaxed)))
+        "RELAXED" >> construct<OmpClause>(construct<OmpClause::Relaxed>()) ||
+        "RELEASE" >> construct<OmpClause>(construct<OmpClause::Release>()) ||
+        "SEQ_CST" >> construct<OmpClause>(construct<OmpClause::SeqCst>())))))
 
 // 2.17.7 Atomic construct
 //        atomic-clause -> memory-order-clause | HINT(hint-expression)
 TYPE_PARSER(sourced(construct<OmpAtomicClause>(
     construct<OmpAtomicClause>(Parser<OmpMemoryOrderClause>{}) ||
-    construct<OmpAtomicClause>("FAIL" >> Parser<OmpFailClause>{}) ||
+    construct<OmpAtomicClause>(
+        "FAIL" >> parenthesized(Parser<OmpFailClause>{})) ||
     construct<OmpAtomicClause>(
         "HINT" >> parenthesized(Parser<OmpHintClause>{})))))
 
diff --git a/flang/lib/Parser/unparse.cpp b/flang/lib/Parser/unparse.cpp
index 3134d35fe7fbe..5ac598265ec87 100644
--- a/flang/lib/Parser/unparse.cpp
+++ b/flang/lib/Parser/unparse.cpp
@@ -2558,8 +2558,8 @@ class UnparseVisitor {
     }
   }
 
-  void Unparse(const OmpAtomicDefaultMemOrderClause &x) {
-    Word(ToUpperCaseLetters(common::EnumToString(x.v)));
+  void Unparse(const common::OmpMemoryOrderType &x) {
+    Word(ToUpperCaseLetters(common::EnumToString(x)));
   }
 
   void Unparse(const OmpAtomicClauseList &x) { Walk(" ", x.v, " "); }
@@ -2889,22 +2889,20 @@ class UnparseVisitor {
     Put("\n");
     EndOpenMP();
   }
-  void Unparse(const OmpFailClause &x) {
-    Word("FAIL(");
-    Walk(x.v);
-    Put(")");
-  }
-  void Unparse(const OmpHintClause &x) {
-    Word("HINT(");
-    Walk(x.v);
-    Put(")");
-  }
   void Unparse(const OmpMemoryOrderClause &x) { Walk(x.v); }
   void Unparse(const OmpAtomicClause &x) {
     common::visit(common::visitors{
                       [&](const OmpMemoryOrderClause &y) { Walk(y); },
-                      [&](const OmpFailClause &y) { Walk(y); },
-                      [&](const OmpHintClause &y) { Walk(y); },
+                      [&](const OmpFailClause &y) {
+                        Word("FAIL(");
+                        Walk(y.v);
+                        Put(")");
+                      },
+                      [&](const OmpHintClause &y) {
+                        Word("HINT(");
+                        Walk(y.v);
+                        Put(")");
+                      },
                   },
         x.u);
   }
diff --git a/flang/lib/Semantics/check-omp-structure.cpp b/flang/lib/Semantics/check-omp-structure.cpp
index c8a905451cd03..ee7959be0322c 100644
--- a/flang/lib/Semantics/check-omp-structure.cpp
+++ b/flang/lib/Semantics/check-omp-structure.cpp
@@ -3262,6 +3262,12 @@ CHECK_SIMPLE_CLAUSE(Align, OMPC_align)
 CHECK_SIMPLE_CLAUSE(Compare, OMPC_compare)
 CHECK_SIMPLE_CLAUSE(OmpxAttribute, OMPC_ompx_attribute)
 CHECK_SIMPLE_CLAUSE(Weak, OMPC_weak)
+CHECK_SIMPLE_CLAUSE(AcqRel, OMPC_acq_rel)
+CHECK_SIMPLE_CLAUSE(Acquire, OMPC_acquire)
+CHECK_SIMPLE_CLAUSE(Relaxed, OMPC_relaxed)
+CHECK_SIMPLE_CLAUSE(Release, OMPC_release)
+CHECK_SIMPLE_CLAUSE(SeqCst, OMPC_seq_cst)
+CHECK_SIMPLE_CLAUSE(Fail, OMPC_fail)
 
 CHECK_REQ_SCALAR_INT_CLAUSE(NumTeams, OMPC_num_teams)
 CHECK_REQ_SCALAR_INT_CLAUSE(NumThreads, OMPC_num_threads)
@@ -3273,53 +3279,6 @@ CHECK_REQ_CONSTANT_SCALAR_INT_CLAUSE(Collapse, OMPC_collapse)
 CHECK_REQ_CONSTANT_SCALAR_INT_CLAUSE(Safelen, OMPC_safelen)
 CHECK_REQ_CONSTANT_SCALAR_INT_CLAUSE(Simdlen, OMPC_simdlen)
 
-void OmpStructureChecker::Enter(const parser::OmpClause::AcqRel &) {
-  if (!isFailClause)
-    CheckAllowedClause(llvm::omp::Clause::OMPC_acq_rel);
-}
-
-void OmpStructureChecker::Enter(const parser::OmpClause::Acquire &) {
-  if (!isFailClause)
-    CheckAllowedClause(llvm::omp::Clause::OMPC_acquire);
-}
-
-void OmpStructureChecker::Enter(const parser::OmpClause::Release &) {
-  if (!isFailClause)
-    CheckAllowedClause(llvm::omp::Clause::OMPC_release);
-}
-
-void OmpStructureChecker::Enter(const parser::OmpClause::Relaxed &) {
-  if (!isFailClause)
-    CheckAllowedClause(llvm::omp::Clause::OMPC_relaxed);
-}
-
-void OmpStructureChecker::Enter(const parser::OmpClause::SeqCst &) {
-  if (!isFailClause)
-    CheckAllowedClause(llvm::omp::Clause::OMPC_seq_cst);
-}
-
-void OmpStructureChecker::Enter(const parser::OmpClause::Fail &) {
-  assert(!isFailClause && "Unexpected FAIL clause inside a FAIL clause?");
-  isFailClause = true;
-  CheckAllowedClause(llvm::omp::Clause::OMPC_fail);
-}
-
-void OmpStructureChecker::Leave(const parser::OmpClause::Fail &) {
-  assert(isFailClause && "Expected to be inside a FAIL clause here");
-  isFailClause = false;
-}
-
-void OmpStructureChecker::Enter(const parser::OmpFailClause &) {
-  assert(!isFailClause && "Unexpected FAIL clause inside a FAIL clause?");
-  isFailClause = true;
-  CheckAllowedClause(llvm::omp::Clause::OMPC_fail);
-}
-
-void OmpStructureChecker::Leave(const parser::OmpFailClause &) {
-  assert(isFailClause && "Expected to be inside a FAIL clause here");
-  isFailClause = false;
-}
-
 // Restrictions specific to each clause are implemented apart from the
 // generalized restrictions.
 
diff --git a/flang/lib/Semantics/check-omp-structure.h b/flang/lib/Semantics/check-omp-structure.h
index 87130f51b85f6..5ea2039a83c3f 100644
--- a/flang/lib/Semantics/check-omp-structure.h
+++ b/flang/lib/Semantics/check-omp-structure.h
@@ -166,10 +166,6 @@ class OmpStructureChecker
 #define GEN_FLANG_CLAUSE_CHECK_ENTER
 #include "llvm/Frontend/OpenMP/OMP.inc"
 
-  void Leave(const parser::OmpClause::Fail &);
-  void Enter(const parser::OmpFailClause &);
-  void Leave(const parser::OmpFailClause &);
-
 private:
   bool CheckAllowedClause(llvmOmpClause clause);
   bool IsVariableListItem(const Symbol &sym);
@@ -345,7 +341,6 @@ class OmpStructureChecker
   using LoopConstruct = std::variant<const parser::DoConstruct *,
       const parser::OpenMPLoopConstruct *>;
   std::vector<LoopConstruct> loopStack_;
-  bool isFailClause{false};
 };
 
 /// Find a duplicate entry in the range, and return an iterator to it.
diff --git a/flang/lib/Semantics/resolve-directives.cpp b/flang/lib/Semantics/resolve-directives.cpp
index c50724fe9d35d..620a37cb40231 100644
--- a/flang/lib/Semantics/resolve-directives.cpp
+++ b/flang/lib/Semantics/resolve-directives.cpp
@@ -416,7 +416,7 @@ class OmpAttributeVisitor : DirectiveAttributeVisitor<llvm::omp::Directive> {
 
     // Gather information from the clauses.
     Flags flags;
-    std::optional<common::OmpAtomicDefaultMemOrderType> memOrder;
+    std::optional<common::OmpMemoryOrderType> memOrder;
     for (const auto &clause : std::get<parser::OmpClauseList>(x.t).v) {
       flags |= common::visit(
           common::visitors{
@@ -799,7 +799,7 @@ class OmpAttributeVisitor : DirectiveAttributeVisitor<llvm::omp::Directive> {
   std::int64_t ordCollapseLevel{0};
 
   void AddOmpRequiresToScope(Scope &, WithOmpDeclarative::RequiresFlags,
-      std::optional<common::OmpAtomicDefaultMemOrderType>);
+      std::optional<common::OmpMemoryOrderType>);
   void IssueNonConformanceWarning(
       llvm::omp::Directive D, parser::CharBlock source);
 
@@ -2721,7 +2721,7 @@ void ResolveOmpTopLevelParts(
   // program units. Modules are skipped because their REQUIRES clauses should be
   // propagated via USE statements instead.
   WithOmpDeclarative::RequiresFlags combinedFlags;
-  std::optional<common::OmpAtomicDefaultMemOrderType> combinedMemOrder;
+  std::optional<common::OmpMemoryOrderType> combinedMemOrder;
 
   // Function to go through non-module top level program units and extract
   // REQUIRES information to be processed by a function-like argument.
@@ -2764,7 +2764,7 @@ void ResolveOmpTopLevelParts(
         flags{details.ompRequires()}) {
       combinedFlags |= *flags;
     }
-    if (const common::OmpAtomicDefaultMemOrderType *
+    if (const common::OmpMemoryOrderType *
         memOrder{details.ompAtomicDefaultMemOrder()}) {
       if (combinedMemOrder && *combinedMemOrder != *memOrder) {
         context.Say(symbol.scope()->sourceRange(),
@@ -2983,7 +2983,7 @@ void OmpAttributeVisitor::CheckNameInAllocateStmt(
 
 void OmpAttributeVisitor::AddOmpRequiresToScope(Scope &scope,
     WithOmpDeclarative::RequiresFlags flags,
-    std::optional<common::OmpAtomicDefaultMemOrderType> memOrder) {
+    std::optional<common::OmpMemoryOrderType> memOrder) {
   Scope *scopeIter = &scope;
   do {
     if (Symbol * symbol{scopeIter->symbol()}) {
diff --git a/flang/lib/Semantics/rewrite-directives.cpp b/flang/lib/Semantics/rewrite-directives.cpp
index c94d0f3855bee..104a77885d276 100644
--- a/flang/lib/Semantics/rewrite-directives.cpp
+++ b/flang/lib/Semantics/rewrite-directives.cpp
@@ -70,7 +70,7 @@ bool OmpRewriteMutator::Pre(parser::OpenMPAtomicConstruct &x) {
       x.u)};
 
   // Get the `atomic_default_mem_order` clause from the top-level parent.
-  std::optional<common::OmpAtomicDefaultMemOrderType> defaultMemOrder;
+  std::optional<common::OmpMemoryOrderType> defaultMemOrder;
   common::visit(
       [&](auto &details) {
         if constexpr (std::is_convertible_v<decltype(&details),
@@ -119,7 +119,7 @@ bool OmpRewriteMutator::Pre(parser::OpenMPAtomicConstruct &x) {
   if (clauseList) {
     atomicDirectiveDefaultOrderFound_ = true;
     switch (*defaultMemOrder) {
-    case common::OmpAtomicDefaultMemOrderType::AcqRel:
+    case common::OmpMemoryOrderType::Acq_Rel:
       clauseList->emplace_back<parser::OmpMemoryOrderClause>(common::visit(
           common::visitors{[](parser::OmpAtomicRead &) -> parser::OmpClause {
                              return parser::OmpClause::Acquire{};
@@ -133,14 +133,18 @@ bool OmpRewriteMutator::Pre(parser::OpenMPAtomicConstruct &x) {
               }},
           x.u));
       break;
-    case common::OmpAtomicDefaultMemOrderType::Relaxed:
+    case common::OmpMemoryOrderType::Relaxed:
       clauseList->emplace_back<parser::OmpMemoryOrderClause>(
           parser::OmpClause{parser::OmpClause::Relaxed{}});
       break;
-    case common::OmpAtomicDefaultMemOrderType::SeqCst:
+    case common::OmpMemoryOrderType::Seq_Cst:
       clauseList->emplace_back<parser::OmpMemoryOrderClause>(
           parser::OmpClause{parser::OmpClause::SeqCst{}});
       break;
+    default:
+      // FIXME: Don't process other values at the moment since their validity
+      // depends on the OpenMP version (which is unavailable here).
+      break;
     }
   }
 
diff --git a/flang/test/Fir/CUDA/cuda-target-rewrite.mlir b/flang/test/Fir/CUDA/cuda-target-rewrite.mlir
index 10e8b8902aa63..a334934f31723 100644
--- a/flang/test/Fir/CUDA/cuda-target-rewrite.mlir
+++ b/flang/test/Fir/CUDA/cuda-target-rewrite.mlir
@@ -45,7 +45,7 @@ gpu.module @testmod {
 func.func @main(%arg0: complex<f64>) {
   %0 = llvm.mlir.constant(0 : i64) : i64
   %1 = llvm.mlir.constant(0 : i32) : i32
-  gpu.launch_func  @testmod::@_QPtest blocks in (%0, %0, %0) threads in (%0, %0, %0) : i64 dynamic_shared_memory_size %1 args(%arg0 : complex<f64>)
+  gpu.launch_func  @testmod::@_QPtest blocks in (%0, %0, %0) threads in (%0, %0, %0) : i64 dynamic_shared_memory_size %1 args(%arg0 : complex<f64>) {cuf.proc_attr = #cuf.cuda_proc<global>}
   return
 }
 
@@ -54,4 +54,4 @@ func.func @main(%arg0: complex<f64>) {
 // CHECK-LABEL: gpu.func @_QPtest
 // CHECK-SAME: (%arg0: f64, %arg1: f64) kernel {
 // CHECK: gpu.return
-// CHECK: gpu.launch_func  @testmod::@_QPtest blocks in (%{{.*}}, %{{.*}}, %{{.*}}) threads in (%{{.*}}, %{{.*}}, %{{.*}}) : i64 dynamic_shared_memory_size %{{.*}} args(%{{.*}} : f64, %{{.*}} : f64)
+// CHECK: gpu.launch_func  @testmod::@_QPtest blocks in (%{{.*}}, %{{.*}}, %{{.*}}) threads in (%{{.*}}, %{{.*}}, %{{.*}}) : i64 dynamic_shared_memory_size %{{.*}} args(%{{.*}} : f64, %{{.*}} : f64) {cuf.proc_attr = #cuf.cuda_proc<global>}
diff --git a/flang/test/Semantics/OpenACC/acc-data.f90 b/flang/test/Semantics/OpenACC/acc-data.f90
index ac49532c495d5..473b91d555cea 100644
--- a/flang/test/Semantics/OpenACC/acc-data.f90
+++ b/flang/test/Semantics/OpenACC/acc-data.f90
@@ -187,6 +187,17 @@ program openacc_data_validity
   !$acc data copy(aa) device_type(default) wait
   !$acc end data
 
+  !ERROR: At most one ASYNC clause can appear on the DATA directive or in group separated by the DEVICE_TYPE clause
+  !$acc data copy(aa) async(async1) async(2)
+  !$acc end data
+
+  !$acc data copy(aa) async(async1) device_type(multicore) async(2) ! ok
+  !$acc end data
+
+  !ERROR: At most one ASYNC clause can appear on the DATA directive or in group separated by the DEVICE_TYPE clause
+  !$acc data copy(aa) async(async1) device_type(multicore) async(2) async(3)
+  !$acc end data
+
   do i = 1, 100
     !$acc data copy(aa)
     !ERROR: CYCLE to construct outside of DATA construct is not allowed
diff --git a/libc/src/math/generic/expm1f.cpp b/libc/src/math/generic/expm1f.cpp
index 1e44e943d9258..b2967e2516197 100644
--- a/libc/src/math/generic/expm1f.cpp
+++ b/libc/src/math/generic/expm1f.cpp
@@ -30,6 +30,7 @@ LLVM_LIBC_FUNCTION(float, expm1f, (float x)) {
   uint32_t x_u = xbits.uintval();
   uint32_t x_abs = x_u & 0x7fff'ffffU;
 
+#ifndef LIBC_MATH_HAS_SKIP_ACCURATE_PASS
   // Exceptional value
   if (LIBC_UNLIKELY(x_u == 0x3e35'bec5U)) { // x = 0x1.6b7d8ap-3f
     int round_mode = fputil::quick_get_round();
@@ -37,7 +38,6 @@ LLVM_LIBC_FUNCTION(float, expm1f, (float x)) {
       return 0x1.8dbe64p-3f;
     return 0x1.8dbe62p-3f;
   }
-
 #if !defined(LIBC_TARGET_CPU_HAS_FMA_DOUBLE)
   if (LIBC_UNLIKELY(x_u == 0xbdc1'c6cbU)) { // x = -0x1.838d96p-4f
     int round_mode = fputil::quick_get_round();
@@ -46,6 +46,7 @@ LLVM_LIBC_FUNCTION(float, expm1f, (float x)) {
     return -0x1.71c882p-4f;
   }
 #endif // LIBC_TARGET_CPU_HAS_FMA_DOUBLE
+#endif // !LIBC_MATH_HAS_SKIP_ACCURATE_PASS
 
   // When |x| > 25*log(2), or nan
   if (LIBC_UNLIKELY(x_abs >= 0x418a'a123U)) {
diff --git a/libc/src/stdio/printf_core/core_structs.h b/libc/src/stdio/printf_core/core_structs.h
index 4c3b81ff018ab..bab4fe75058a0 100644
--- a/libc/src/stdio/printf_core/core_structs.h
+++ b/libc/src/stdio/printf_core/core_structs.h
@@ -55,8 +55,13 @@ struct FormatSection {
   int min_width = 0;
   int precision = -1;
 
-  // Needs to be large enough to hold a long double.
+  // Needs to be large enough to hold a long double. Special case handling for
+  // the PowerPC double double type because it has no FPBits interface.
+#ifdef LIBC_TYPES_LONG_DOUBLE_IS_DOUBLE_DOUBLE
+  Uint128 conv_val_raw;
+#else
   fputil::FPBits<long double>::StorageType conv_val_raw;
+#endif // LIBC_TYPES_LONG_DOUBLE_IS_DOUBLE_DOUBLE
   void *conv_val_ptr;
 
   char conv_name;
diff --git a/libc/test/src/math/performance_testing/BinaryOpSingleOutputPerf.h b/libc/test/src/math/performance_testing/BinaryOpSingleOutputPerf.h
deleted file mode 100644
index 98a1813bd7b54..0000000000000
--- a/libc/test/src/math/performance_testing/BinaryOpSingleOutputPerf.h
+++ /dev/null
@@ -1,148 +0,0 @@
-//===-- Common utility class for differential analysis --------------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#include "src/__support/CPP/algorithm.h"
-#include "src/__support/FPUtil/FPBits.h"
-#include "src/__support/macros/config.h"
-#include "test/src/math/performance_testing/Timer.h"
-
-#include <cstddef>
-#include <fstream>
-
-namespace LIBC_NAMESPACE_DECL {
-namespace testing {
-template <typename OutputType, typename InputType>
-class BinaryOpSingleOutputPerf {
-  using FPBits = fputil::FPBits<OutputType>;
-  using StorageType = typename FPBits::StorageType;
-  static constexpr StorageType UIntMax =
-      cpp::numeric_limits<StorageType>::max();
-
-public:
-  typedef OutputType Func(InputType, InputType);
-
-  static void run_perf_in_range(Func myFunc, Func otherFunc,
-                                StorageType startingBit, StorageType endingBit,
-                                size_t N, size_t rounds, std::ofstream &log) {
-    if (sizeof(StorageType) <= sizeof(size_t))
-      N = cpp::min(N, static_cast<size_t>(endingBit - startingBit));
-
-    auto runner = [=](Func func) {
-      [[maybe_unused]] volatile OutputType result;
-      if (endingBit < startingBit) {
-        return;
-      }
-
-      StorageType step = (endingBit - startingBit) / N;
-      for (size_t i = 0; i < rounds; i++) {
-        for (StorageType bitsX = startingBit, bitsY = endingBit;;
-             bitsX += step, bitsY -= step) {
-          InputType x = FPBits(bitsX).get_val();
-          InputType y = FPBits(bitsY).get_val();
-          result = func(x, y);
-          if (endingBit - bitsX < step) {
-            break;
-          }
-        }
-      }
-    };
-
-    Timer timer;
-    timer.start();
-    runner(myFunc);
-    timer.stop();
-
-    double my_average = static_cast<double>(timer.nanoseconds()) / N / rounds;
-    log << "-- My function --\n";
-    log << "     Total time      : " << timer.nanoseconds() << " ns \n";
-    log << "     Average runtime : " << my_average << " ns/op \n";
-    log << "     Ops per second  : "
-        << static_cast<uint64_t>(1'000'000'000.0 / my_average) << " op/s \n";
-
-    timer.start();
-    runner(otherFunc);
-    timer.stop();
-
-    double other_average =
-        static_cast<double>(timer.nanoseconds()) / N / rounds;
-    log << "-- Other function --\n";
-    log << "     Total time      : " << timer.nanoseconds() << " ns \n";
-    log << "     Average runtime : " << other_average << " ns/op \n";
-    log << "     Ops per second  : "
-        << static_cast<uint64_t>(1'000'000'000.0 / other_average) << " op/s \n";
-
-    log << "-- Average runtime ratio --\n";
-    log << "     Mine / Other's  : " << my_average / other_average << " \n";
-  }
-
-  static void run_perf(Func myFunc, Func otherFunc, int rounds,
-                       const char *logFile) {
-    std::ofstream log(logFile);
-    log << " Performance tests with inputs in denormal range:\n";
-    run_perf_in_range(myFunc, otherFunc, /* startingBit= */ StorageType(0),
-                      /* endingBit= */ FPBits::max_subnormal().uintval(),
-                      1'000'001, rounds, log);
-    log << "\n Performance tests with inputs in normal range:\n";
-    run_perf_in_range(myFunc, otherFunc,
-                      /* startingBit= */ FPBits::min_normal().uintval(),
-                      /* endingBit= */ FPBits::max_normal().uintval(),
-                      1'000'001, rounds, log);
-    log << "\n Performance tests with inputs in normal range with exponents "
-           "close to each other:\n";
-    run_perf_in_range(
-        myFunc, otherFunc,
-        /* startingBit= */ FPBits(OutputType(0x1.0p-10)).uintval(),
-        /* endingBit= */ FPBits(OutputType(0x1.0p+10)).uintval(), 1'000'001,
-        rounds, log);
-  }
-
-  static void run_diff(Func myFunc, Func otherFunc, const char *logFile) {
-    uint64_t diffCount = 0;
-    std::ofstream log(logFile);
-    log << " Diff tests with inputs in denormal range:\n";
-    diffCount += run_diff_in_range(
-        myFunc, otherFunc, /* startingBit= */ StorageType(0),
-        /* endingBit= */ FPBits::max_subnormal().uintval(), 1'000'001, log);
-    log << "\n Diff tests with inputs in normal range:\n";
-    diffCount += run_diff_in_range(
-        myFunc, otherFunc,
-        /* startingBit= */ FPBits::min_normal().uintval(),
-        /* endingBit= */ FPBits::max_normal().uintval(), 100'000'001, log);
-    log << "\n Diff tests with inputs in normal range with exponents "
-           "close to each other:\n";
-    diffCount += run_diff_in_range(
-        myFunc, otherFunc,
-        /* startingBit= */ FPBits(OutputType(0x1.0p-10)).uintval(),
-        /* endingBit= */ FPBits(OutputType(0x1.0p+10)).uintval(), 10'000'001,
-        log);
-
-    log << "Total number of differing results: " << diffCount << '\n';
-  }
-};
-
-} // namespace testing
-} // namespace LIBC_NAMESPACE_DECL
-
-#define BINARY_OP_SINGLE_OUTPUT_PERF(OutputType, InputType, myFunc, otherFunc, \
-                                     filename)                                 \
-  int main() {                                                                 \
-    LIBC_NAMESPACE::testing::BinaryOpSingleOutputPerf<                         \
-        OutputType, InputType>::run_perf(&myFunc, &otherFunc, 1, filename);    \
-    return 0;                                                                  \
-  }
-
-#define BINARY_OP_SINGLE_OUTPUT_PERF_EX(OutputType, InputType, myFunc,         \
-                                        otherFunc, rounds, filename)           \
-  {                                                                            \
-    LIBC_NAMESPACE::testing::BinaryOpSingleOutputPerf<                         \
-        OutputType, InputType>::run_perf(&myFunc, &otherFunc, rounds,          \
-                                         filename);                            \
-    LIBC_NAMESPACE::testing::BinaryOpSingleOutputPerf<                         \
-        OutputType, InputType>::run_perf(&myFunc, &otherFunc, rounds,          \
-                                         filename);                            \
-  }
diff --git a/libc/test/src/math/performance_testing/CMakeLists.txt b/libc/test/src/math/performance_testing/CMakeLists.txt
index d8f87e04c15d8..618a6d037a63f 100644
--- a/libc/test/src/math/performance_testing/CMakeLists.txt
+++ b/libc/test/src/math/performance_testing/CMakeLists.txt
@@ -92,18 +92,9 @@ function(add_perf_binary target_name)
 endfunction()
 
 add_header_library(
-  single_input_single_output_diff
+  perf_test
   HDRS
-    SingleInputSingleOutputPerf.h
-  DEPENDS
-    libc.src.__support.CPP.algorithm
-    libc.src.__support.FPUtil.fp_bits
-)
-
-add_header_library(
-  binary_op_single_output_diff
-  HDRS
-    BinaryOpSingleOutputPerf.h
+    PerfTest.h
   DEPENDS
     libc.src.__support.CPP.algorithm
     libc.src.__support.FPUtil.fp_bits
@@ -114,7 +105,7 @@ add_perf_binary(
   SRCS
     sinf_perf.cpp
   DEPENDS
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.sinf
   COMPILE_OPTIONS
     -fno-builtin
@@ -125,7 +116,7 @@ add_perf_binary(
   SRCS
     cosf_perf.cpp
   DEPENDS
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.cosf
   COMPILE_OPTIONS
     -fno-builtin
@@ -136,7 +127,7 @@ add_perf_binary(
   SRCS
     expm1f_perf.cpp
   DEPENDS
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.expm1f
   COMPILE_OPTIONS
     -fno-builtin
@@ -147,7 +138,7 @@ add_perf_binary(
   SRCS
     ceilf_perf.cpp
   DEPENDS
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.ceilf
   COMPILE_OPTIONS
     -fno-builtin
@@ -158,7 +149,7 @@ add_perf_binary(
   SRCS
     exp10f16_perf.cpp
   DEPENDS
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.exp10f16
   COMPILE_OPTIONS
     -fno-builtin
@@ -169,7 +160,7 @@ add_perf_binary(
   SRCS
     exp2f_perf.cpp
   DEPENDS
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.exp2f
   COMPILE_OPTIONS
     -fno-builtin
@@ -180,7 +171,7 @@ add_perf_binary(
   SRCS
     exp2f16_perf.cpp
   DEPENDS
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.exp2f16
   COMPILE_OPTIONS
     -fno-builtin
@@ -191,7 +182,7 @@ add_perf_binary(
   SRCS
     expf_perf.cpp
   DEPENDS
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.expf
   COMPILE_OPTIONS
     -fno-builtin
@@ -202,7 +193,7 @@ add_perf_binary(
   SRCS
     expf16_perf.cpp
   DEPENDS
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.expf16
   COMPILE_OPTIONS
     -fno-builtin
@@ -213,7 +204,7 @@ add_perf_binary(
   SRCS
     fabsf_perf.cpp
   DEPENDS
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.fabsf
   COMPILE_OPTIONS
     -fno-builtin
@@ -224,7 +215,7 @@ add_perf_binary(
   SRCS
     floorf_perf.cpp
   DEPENDS
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.floorf
   COMPILE_OPTIONS
     -fno-builtin
@@ -235,7 +226,7 @@ add_perf_binary(
   SRCS
     log10f_perf.cpp
   DEPENDS
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.log10f
   COMPILE_OPTIONS
     -fno-builtin
@@ -246,7 +237,7 @@ add_perf_binary(
   SRCS
     log1pf_perf.cpp
   DEPENDS
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.log1pf
   COMPILE_OPTIONS
     -fno-builtin
@@ -257,7 +248,7 @@ add_perf_binary(
   SRCS
     log2f_perf.cpp
   DEPENDS
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.log2f
   COMPILE_OPTIONS
     -fno-builtin
@@ -268,7 +259,7 @@ add_perf_binary(
   SRCS
     logf_perf.cpp
   DEPENDS
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.logf
   COMPILE_OPTIONS
     -fno-builtin
@@ -279,7 +270,7 @@ add_perf_binary(
   SRCS
     logbf_perf.cpp
   DEPENDS
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.logbf
   COMPILE_OPTIONS
     -fno-builtin
@@ -290,7 +281,7 @@ add_perf_binary(
   SRCS
     nearbyintf_perf.cpp
   DEPENDS
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.nearbyintf
   COMPILE_OPTIONS
     -fno-builtin
@@ -301,7 +292,7 @@ add_perf_binary(
   SRCS
     rintf_perf.cpp
   DEPENDS
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.rintf
   COMPILE_OPTIONS
     -fno-builtin
@@ -312,7 +303,7 @@ add_perf_binary(
   SRCS
     roundf_perf.cpp
   DEPENDS
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.roundf
   COMPILE_OPTIONS
     -fno-builtin
@@ -323,7 +314,7 @@ add_perf_binary(
   SRCS
     sqrtf_perf.cpp
   DEPENDS
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.sqrtf
   COMPILE_OPTIONS
     -fno-builtin
@@ -334,7 +325,7 @@ add_perf_binary(
   SRCS
     truncf_perf.cpp
   DEPENDS
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.truncf
   COMPILE_OPTIONS
     -fno-builtin
@@ -345,7 +336,7 @@ add_perf_binary(
   SRCS
     hypotf16_perf.cpp
   DEPENDS
-    .binary_op_single_output_diff
+    .perf_test
     libc.src.math.hypotf16
     libc.src.__support.FPUtil.fp_bits
   COMPILE_OPTIONS
@@ -357,7 +348,7 @@ add_perf_binary(
   SRCS
     hypotf_perf.cpp
   DEPENDS
-    .binary_op_single_output_diff
+    .perf_test
     libc.src.math.hypotf
   COMPILE_OPTIONS
     -fno-builtin
@@ -368,7 +359,7 @@ add_perf_binary(
   SRCS
     hypot_perf.cpp
   DEPENDS
-    .binary_op_single_output_diff
+    .perf_test
     libc.src.math.hypot
   COMPILE_OPTIONS
     -fno-builtin
@@ -379,7 +370,7 @@ add_perf_binary(
   SRCS
     fmodf_perf.cpp
   DEPENDS
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.fmodf
   COMPILE_OPTIONS
     -fno-builtin
@@ -390,7 +381,7 @@ add_perf_binary(
   SRCS
     fmod_perf.cpp
   DEPENDS
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.fmod
   COMPILE_OPTIONS
     -fno-builtin
@@ -401,7 +392,7 @@ add_perf_binary(
   SRCS
     fmodl_perf.cpp
   DEPENDS
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.fmodl
   COMPILE_OPTIONS
     -fno-builtin
@@ -412,7 +403,7 @@ add_perf_binary(
   SRCS
     fmodf16_perf.cpp
   DEPENDS
-    .binary_op_single_output_diff
+    .perf_test
     libc.src.math.fmodf16
     libc.src.__support.FPUtil.generic.fmod
     libc.src.__support.macros.properties.types
@@ -423,8 +414,9 @@ add_perf_binary(
   SRCS
     fmodf128_perf.cpp
   DEPENDS
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.fmodf128
+    libc.src.__support.macros.properties.types
   COMPILE_OPTIONS
     -fno-builtin
 )
@@ -457,8 +449,7 @@ add_perf_binary(
   SRCS
     misc_basic_ops_perf.cpp
   DEPENDS
-    .binary_op_single_output_diff
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.copysignf
     libc.src.math.copysignf16
     libc.src.math.fabsf
@@ -472,7 +463,7 @@ add_perf_binary(
   SRCS
     max_min_funcs_perf.cpp
   DEPENDS
-    .binary_op_single_output_diff
+    .perf_test
     libc.src.math.fmaxf
     libc.src.math.fmaxf16
     libc.src.math.fmaximumf
@@ -494,7 +485,7 @@ add_perf_binary(
   SRCS
     fmul_perf.cpp
   DEPENDS
-    .binary_op_single_output_diff
+    .perf_test
     libc.src.math.fmul
     libc.src.__support.FPUtil.generic.mul
     libc.src.__support.FPUtil.fp_bits
@@ -507,7 +498,7 @@ add_perf_binary(
   SRCS
     fmull_perf.cpp
   DEPENDS
-    .binary_op_single_output_diff
+    .perf_test
     libc.src.math.fmull
   COMPILE_OPTIONS
     -fno-builtin
@@ -518,6 +509,6 @@ add_perf_binary(
   SRCS
     sqrtf128_perf.cpp
   DEPENDS
-    .single_input_single_output_diff
+    .perf_test
     libc.src.math.sqrtf128
 )
diff --git a/libc/test/src/math/performance_testing/PerfTest.h b/libc/test/src/math/performance_testing/PerfTest.h
new file mode 100644
index 0000000000000..3cc6b2411aeab
--- /dev/null
+++ b/libc/test/src/math/performance_testing/PerfTest.h
@@ -0,0 +1,159 @@
+//===-- Common utility class for differential analysis --------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "src/__support/CPP/algorithm.h"
+#include "src/__support/FPUtil/FPBits.h"
+#include "src/__support/macros/config.h"
+#include "test/src/math/performance_testing/Timer.h"
+
+#include <cstddef>
+#include <fstream>
+
+namespace LIBC_NAMESPACE_DECL {
+namespace testing {
+template <typename OutputType, typename InputType> class PerfTest {
+  using FPBits = fputil::FPBits<OutputType>;
+  using StorageType = typename FPBits::StorageType;
+  static constexpr StorageType U_INT_MAX =
+      cpp::numeric_limits<StorageType>::max();
+
+public:
+  using BinaryFuncPtr = OutputType (*)(InputType, InputType);
+  using UnaryFuncPtr = OutputType (*)(InputType);
+
+  template <bool binary, typename Func>
+  static void run_perf_in_range(Func FuncA, Func FuncB, StorageType startingBit,
+                                StorageType endingBit, size_t N, size_t rounds,
+                                const char *name_a, const char *name_b,
+                                std::ofstream &log) {
+    if (sizeof(StorageType) <= sizeof(size_t))
+      N = cpp::min(N, static_cast<size_t>(endingBit - startingBit));
+
+    auto runner = [=](Func func) {
+      [[maybe_unused]] volatile OutputType result;
+      if (endingBit < startingBit) {
+        return;
+      }
+
+      StorageType step = (endingBit - startingBit) / N;
+      if (step == 0)
+        step = 1;
+      for (size_t i = 0; i < rounds; i++) {
+        for (StorageType bits_x = startingBit, bits_y = endingBit;;
+             bits_x += step, bits_y -= step) {
+          InputType x = FPBits(bits_x).get_val();
+          if constexpr (binary) {
+            InputType y = FPBits(bits_y).get_val();
+            result = func(x, y);
+          } else {
+            result = func(x);
+          }
+          if (endingBit - bits_x < step) {
+            break;
+          }
+        }
+      }
+    };
+
+    Timer timer;
+    timer.start();
+    runner(FuncA);
+    timer.stop();
+
+    double a_average = static_cast<double>(timer.nanoseconds()) / N / rounds;
+    log << "-- Function A: " << name_a << " --\n";
+    log << "     Total time      : " << timer.nanoseconds() << " ns \n";
+    log << "     Average runtime : " << a_average << " ns/op \n";
+    log << "     Ops per second  : "
+        << static_cast<uint64_t>(1'000'000'000.0 / a_average) << " op/s \n";
+
+    timer.start();
+    runner(FuncB);
+    timer.stop();
+
+    double b_average = static_cast<double>(timer.nanoseconds()) / N / rounds;
+    log << "-- Function B: " << name_b << " --\n";
+    log << "     Total time      : " << timer.nanoseconds() << " ns \n";
+    log << "     Average runtime : " << b_average << " ns/op \n";
+    log << "     Ops per second  : "
+        << static_cast<uint64_t>(1'000'000'000.0 / b_average) << " op/s \n";
+
+    log << "-- Average ops per second ratio --\n";
+    log << "     A / B  : " << b_average / a_average << " \n";
+  }
+
+  template <bool binary, typename Func>
+  static void run_perf(Func FuncA, Func FuncB, int rounds, const char *name_a,
+                       const char *name_b, const char *logFile) {
+    std::ofstream log(logFile);
+    log << " Performance tests with inputs in denormal range:\n";
+    run_perf_in_range<binary>(
+        FuncA, FuncB, /* startingBit= */ StorageType(0),
+        /* endingBit= */ FPBits::max_subnormal().uintval(), 1'000'001, rounds,
+        name_a, name_b, log);
+    log << "\n Performance tests with inputs in normal range:\n";
+    run_perf_in_range<binary>(FuncA, FuncB,
+                              /* startingBit= */ FPBits::min_normal().uintval(),
+                              /* endingBit= */ FPBits::max_normal().uintval(),
+                              1'000'001, rounds, name_a, name_b, log);
+    log << "\n Performance tests with inputs in normal range with exponents "
+           "close to each other:\n";
+    run_perf_in_range<binary>(
+        FuncA, FuncB,
+        /* startingBit= */ FPBits(OutputType(0x1.0p-10)).uintval(),
+        /* endingBit= */ FPBits(OutputType(0x1.0p+10)).uintval(), 1'000'001,
+        rounds, name_a, name_b, log);
+  }
+};
+
+} // namespace testing
+} // namespace LIBC_NAMESPACE_DECL
+
+#define BINARY_INPUT_SINGLE_OUTPUT_PERF(OutputType, InputType, FuncA, FuncB,   \
+                                        filename)                              \
+  {                                                                            \
+    using TargetFuncPtr =                                                      \
+        typename LIBC_NAMESPACE::testing::PerfTest<OutputType,                 \
+                                                   InputType>::BinaryFuncPtr;  \
+    LIBC_NAMESPACE::testing::PerfTest<OutputType, InputType>::run_perf<true>(  \
+        static_cast<TargetFuncPtr>(&FuncA),                                    \
+        static_cast<TargetFuncPtr>(&FuncB), 1, #FuncA, #FuncB, filename);      \
+    return 0;                                                                  \
+  }
+
+#define BINARY_INPUT_SINGLE_OUTPUT_PERF_EX(OutputType, InputType, FuncA,       \
+                                           FuncB, rounds, filename)            \
+  {                                                                            \
+    using TargetFuncPtr =                                                      \
+        typename LIBC_NAMESPACE::testing::PerfTest<OutputType,                 \
+                                                   InputType>::BinaryFuncPtr;  \
+    LIBC_NAMESPACE::testing::PerfTest<OutputType, InputType>::run_perf<true>(  \
+        static_cast<TargetFuncPtr>(&FuncA),                                    \
+        static_cast<TargetFuncPtr>(&FuncB), rounds, #FuncA, #FuncB, filename); \
+    return 0;                                                                  \
+  }
+
+#define SINGLE_INPUT_SINGLE_OUTPUT_PERF(T, FuncA, FuncB, filename)             \
+  {                                                                            \
+    using TargetFuncPtr =                                                      \
+        typename LIBC_NAMESPACE::testing::PerfTest<T, T>::UnaryFuncPtr;        \
+    LIBC_NAMESPACE::testing::PerfTest<T, T>::run_perf<false>(                  \
+        static_cast<TargetFuncPtr>(&FuncA),                                    \
+        static_cast<TargetFuncPtr>(&FuncB), 1, #FuncA, #FuncB, filename);      \
+    return 0;                                                                  \
+  }
+
+#define SINGLE_INPUT_SINGLE_OUTPUT_PERF_EX(T, FuncA, FuncB, rounds, filename)  \
+  {                                                                            \
+    using TargetFuncPtr =                                                      \
+        typename LIBC_NAMESPACE::testing::PerfTest<T, T>::UnaryFuncPtr;        \
+    LIBC_NAMESPACE::testing::PerfTest<T, T>::run_perf<false>(                  \
+        static_cast<TargetFuncPtr>(&FuncA),                                    \
+        static_cast<TargetFuncPtr>(&FuncB), rounds, #FuncA, #FuncB, filename); \
+    return 0;                                                                  \
+  }
diff --git a/libc/test/src/math/performance_testing/SingleInputSingleOutputPerf.h b/libc/test/src/math/performance_testing/SingleInputSingleOutputPerf.h
deleted file mode 100644
index efad1259d6bf1..0000000000000
--- a/libc/test/src/math/performance_testing/SingleInputSingleOutputPerf.h
+++ /dev/null
@@ -1,105 +0,0 @@
-//===-- Common utility class for differential analysis --------------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#include "src/__support/CPP/algorithm.h"
-#include "src/__support/FPUtil/FPBits.h"
-#include "src/__support/macros/config.h"
-#include "test/src/math/performance_testing/Timer.h"
-
-#include <fstream>
-
-namespace LIBC_NAMESPACE_DECL {
-namespace testing {
-
-template <typename T> class SingleInputSingleOutputPerf {
-  using FPBits = fputil::FPBits<T>;
-  using StorageType = typename FPBits::StorageType;
-  static constexpr StorageType UIntMax =
-      cpp::numeric_limits<StorageType>::max();
-
-public:
-  typedef T Func(T);
-
-  static void runPerfInRange(Func myFunc, Func otherFunc,
-                             StorageType startingBit, StorageType endingBit,
-                             size_t rounds, std::ofstream &log) {
-    size_t n = 10'010'001;
-    if (sizeof(StorageType) <= sizeof(size_t))
-      n = cpp::min(n, static_cast<size_t>(endingBit - startingBit));
-
-    auto runner = [=](Func func) {
-      StorageType step = (endingBit - startingBit) / n;
-      if (step == 0)
-        step = 1;
-      [[maybe_unused]] volatile T result;
-      for (size_t i = 0; i < rounds; i++) {
-        for (StorageType bits = startingBit; bits < endingBit; bits += step) {
-          T x = FPBits(bits).get_val();
-          result = func(x);
-        }
-      }
-    };
-
-    Timer timer;
-    timer.start();
-    runner(myFunc);
-    timer.stop();
-
-    double myAverage = static_cast<double>(timer.nanoseconds()) / n / rounds;
-    log << "-- My function --\n";
-    log << "     Total time      : " << timer.nanoseconds() << " ns \n";
-    log << "     Average runtime : " << myAverage << " ns/op \n";
-    log << "     Ops per second  : "
-        << static_cast<uint64_t>(1'000'000'000.0 / myAverage) << " op/s \n";
-
-    timer.start();
-    runner(otherFunc);
-    timer.stop();
-
-    double otherAverage = static_cast<double>(timer.nanoseconds()) / n / rounds;
-    log << "-- Other function --\n";
-    log << "     Total time      : " << timer.nanoseconds() << " ns \n";
-    log << "     Average runtime : " << otherAverage << " ns/op \n";
-    log << "     Ops per second  : "
-        << static_cast<uint64_t>(1'000'000'000.0 / otherAverage) << " op/s \n";
-
-    log << "-- Average runtime ratio --\n";
-    log << "     Mine / Other's  : " << myAverage / otherAverage << " \n";
-  }
-
-  static void runPerf(Func myFunc, Func otherFunc, size_t rounds,
-                      const char *logFile) {
-    std::ofstream log(logFile);
-    log << " Performance tests with inputs in denormal range:\n";
-    runPerfInRange(myFunc, otherFunc, /* startingBit= */ StorageType(0),
-                   /* endingBit= */ FPBits::max_subnormal().uintval(), rounds,
-                   log);
-    log << "\n Performance tests with inputs in normal range:\n";
-    runPerfInRange(myFunc, otherFunc,
-                   /* startingBit= */ FPBits::min_normal().uintval(),
-                   /* endingBit= */ FPBits::max_normal().uintval(), rounds,
-                   log);
-  }
-};
-
-} // namespace testing
-} // namespace LIBC_NAMESPACE_DECL
-
-#define SINGLE_INPUT_SINGLE_OUTPUT_PERF(T, myFunc, otherFunc, filename)        \
-  int main() {                                                                 \
-    LIBC_NAMESPACE::testing::SingleInputSingleOutputPerf<T>::runPerf(          \
-        &myFunc, &otherFunc, 1, filename);                                     \
-    return 0;                                                                  \
-  }
-
-#define SINGLE_INPUT_SINGLE_OUTPUT_PERF_EX(T, myFunc, otherFunc, rounds,       \
-                                           filename)                           \
-  {                                                                            \
-    LIBC_NAMESPACE::testing::SingleInputSingleOutputPerf<T>::runPerf(          \
-        &myFunc, &otherFunc, rounds, filename);                                \
-  }
diff --git a/libc/test/src/math/performance_testing/ceilf_perf.cpp b/libc/test/src/math/performance_testing/ceilf_perf.cpp
index 04e96f6fb2dcc..37c5d31a3a393 100644
--- a/libc/test/src/math/performance_testing/ceilf_perf.cpp
+++ b/libc/test/src/math/performance_testing/ceilf_perf.cpp
@@ -6,11 +6,13 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "SingleInputSingleOutputPerf.h"
-
+#include "PerfTest.h"
 #include "src/math/ceilf.h"
 
 #include <math.h>
 
-SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::ceilf, ::ceilf,
-                                "ceilf_perf.log")
+int main() {
+  SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::ceilf, ::ceilf,
+                                  "ceilf_perf.log")
+  return 0;
+}
diff --git a/libc/test/src/math/performance_testing/cosf_perf.cpp b/libc/test/src/math/performance_testing/cosf_perf.cpp
index 1501b8bf25404..b189c554265e1 100644
--- a/libc/test/src/math/performance_testing/cosf_perf.cpp
+++ b/libc/test/src/math/performance_testing/cosf_perf.cpp
@@ -6,11 +6,13 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "SingleInputSingleOutputPerf.h"
-
+#include "PerfTest.h"
 #include "src/math/cosf.h"
 
 #include <math.h>
 
-SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::cosf, ::cosf,
-                                "cosf_perf.log")
+int main() {
+  SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::cosf, ::cosf,
+                                  "cosf_perf.log")
+  return 0;
+}
diff --git a/libc/test/src/math/performance_testing/exp10f16_perf.cpp b/libc/test/src/math/performance_testing/exp10f16_perf.cpp
index b9e76d420afce..8d7bb7b6b1aa8 100644
--- a/libc/test/src/math/performance_testing/exp10f16_perf.cpp
+++ b/libc/test/src/math/performance_testing/exp10f16_perf.cpp
@@ -6,8 +6,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "SingleInputSingleOutputPerf.h"
-
+#include "PerfTest.h"
 #include "src/math/exp10f16.h"
 
 // LLVM libc might be the only libc implementation with support for float16 math
diff --git a/libc/test/src/math/performance_testing/exp2f16_perf.cpp b/libc/test/src/math/performance_testing/exp2f16_perf.cpp
index aa58de2476f1a..c564fa17bb1fe 100644
--- a/libc/test/src/math/performance_testing/exp2f16_perf.cpp
+++ b/libc/test/src/math/performance_testing/exp2f16_perf.cpp
@@ -6,8 +6,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "SingleInputSingleOutputPerf.h"
-
+#include "PerfTest.h"
 #include "src/math/exp2f16.h"
 
 // LLVM libc might be the only libc implementation with support for float16 math
diff --git a/libc/test/src/math/performance_testing/exp2f_perf.cpp b/libc/test/src/math/performance_testing/exp2f_perf.cpp
index 19a70ac6569aa..fa5a6ad452e94 100644
--- a/libc/test/src/math/performance_testing/exp2f_perf.cpp
+++ b/libc/test/src/math/performance_testing/exp2f_perf.cpp
@@ -6,11 +6,13 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "SingleInputSingleOutputPerf.h"
-
+#include "PerfTest.h"
 #include "src/math/exp2f.h"
 
 #include <math.h>
 
-SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::exp2f, ::exp2f,
-                                "exp2f_perf.log")
+int main() {
+  SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::exp2f, ::exp2f,
+                                  "exp2f_perf.log")
+  return 0;
+}
diff --git a/libc/test/src/math/performance_testing/expf16_perf.cpp b/libc/test/src/math/performance_testing/expf16_perf.cpp
index bc9d9f05559a3..7fe567c1e3951 100644
--- a/libc/test/src/math/performance_testing/expf16_perf.cpp
+++ b/libc/test/src/math/performance_testing/expf16_perf.cpp
@@ -6,8 +6,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "SingleInputSingleOutputPerf.h"
-
+#include "PerfTest.h"
 #include "src/math/expf16.h"
 
 // LLVM libc might be the only libc implementation with support for float16 math
diff --git a/libc/test/src/math/performance_testing/expf_perf.cpp b/libc/test/src/math/performance_testing/expf_perf.cpp
index 4b743514023d1..33306d181be20 100644
--- a/libc/test/src/math/performance_testing/expf_perf.cpp
+++ b/libc/test/src/math/performance_testing/expf_perf.cpp
@@ -6,11 +6,13 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "SingleInputSingleOutputPerf.h"
-
+#include "PerfTest.h"
 #include "src/math/expf.h"
 
 #include <math.h>
 
-SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::expf, ::expf,
-                                "expf_perf.log")
+int main() {
+  SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::expf, ::expf,
+                                  "expf_perf.log")
+  return 0;
+}
diff --git a/libc/test/src/math/performance_testing/expm1f_perf.cpp b/libc/test/src/math/performance_testing/expm1f_perf.cpp
index 128ab351d86db..a64f3039f8a5e 100644
--- a/libc/test/src/math/performance_testing/expm1f_perf.cpp
+++ b/libc/test/src/math/performance_testing/expm1f_perf.cpp
@@ -6,11 +6,13 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "SingleInputSingleOutputPerf.h"
-
+#include "PerfTest.h"
 #include "src/math/expm1f.h"
 
 #include <math.h>
 
-SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::expm1f, ::expm1f,
-                                "expm1f_perf.log")
+int main() {
+  SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::expm1f, ::expm1f,
+                                  "expm1f_perf.log")
+  return 0;
+}
diff --git a/libc/test/src/math/performance_testing/fabsf_perf.cpp b/libc/test/src/math/performance_testing/fabsf_perf.cpp
index b6c6add75d230..7a8bd1648f81b 100644
--- a/libc/test/src/math/performance_testing/fabsf_perf.cpp
+++ b/libc/test/src/math/performance_testing/fabsf_perf.cpp
@@ -6,11 +6,13 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "SingleInputSingleOutputPerf.h"
-
+#include "PerfTest.h"
 #include "src/math/fabsf.h"
 
 #include <math.h>
 
-SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::fabsf, ::fabsf,
-                                "fabsf_perf.log")
+int main() {
+  SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::fabsf, ::fabsf,
+                                  "fabsf_perf.log")
+  return 0;
+}
diff --git a/libc/test/src/math/performance_testing/floorf_perf.cpp b/libc/test/src/math/performance_testing/floorf_perf.cpp
index 0f1087b3c8236..85fa7391d0d37 100644
--- a/libc/test/src/math/performance_testing/floorf_perf.cpp
+++ b/libc/test/src/math/performance_testing/floorf_perf.cpp
@@ -6,11 +6,13 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "SingleInputSingleOutputPerf.h"
-
+#include "PerfTest.h"
 #include "src/math/floorf.h"
 
 #include <math.h>
 
-SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::floorf, ::floorf,
-                                "floorf_perf.log")
+int main() {
+  SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::floorf, ::floorf,
+                                  "floorf_perf.log")
+  return 0;
+}
diff --git a/libc/test/src/math/performance_testing/fmod_perf.cpp b/libc/test/src/math/performance_testing/fmod_perf.cpp
index 75a4242034226..a99a61f6f9054 100644
--- a/libc/test/src/math/performance_testing/fmod_perf.cpp
+++ b/libc/test/src/math/performance_testing/fmod_perf.cpp
@@ -6,11 +6,13 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "BinaryOpSingleOutputPerf.h"
-
+#include "PerfTest.h"
 #include "src/math/fmod.h"
 
 #include <math.h>
 
-BINARY_OP_SINGLE_OUTPUT_PERF(double, double, LIBC_NAMESPACE::fmod, ::fmod,
-                             "fmod_perf.log")
+int main() {
+  BINARY_INPUT_SINGLE_OUTPUT_PERF(double, double, LIBC_NAMESPACE::fmod, ::fmod,
+                                  "fmod_perf.log")
+  return 0;
+}
diff --git a/libc/test/src/math/performance_testing/fmodf128_perf.cpp b/libc/test/src/math/performance_testing/fmodf128_perf.cpp
index 8165e9254dd56..93212686c2abd 100644
--- a/libc/test/src/math/performance_testing/fmodf128_perf.cpp
+++ b/libc/test/src/math/performance_testing/fmodf128_perf.cpp
@@ -6,11 +6,14 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "BinaryOpSingleOutputDiff.h"
-
+#include "PerfTest.h"
+#include "src/__support/macros/properties/types.h"
 #include "src/math/fmodf128.h"
 
 #include <math.h>
 
-BINARY_OP_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::fmodf128, ::fmodf128,
-                             "fmodf128_perf.log")
+int main() {
+  BINARY_INPUT_SINGLE_OUTPUT_PERF(float128, float128, LIBC_NAMESPACE::fmodf128,
+                                  ::fmodf128, "fmodf128_perf.log")
+  return 0;
+}
diff --git a/libc/test/src/math/performance_testing/fmodf16_perf.cpp b/libc/test/src/math/performance_testing/fmodf16_perf.cpp
index 062bc2da05adf..f7c492cb77796 100644
--- a/libc/test/src/math/performance_testing/fmodf16_perf.cpp
+++ b/libc/test/src/math/performance_testing/fmodf16_perf.cpp
@@ -6,7 +6,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "BinaryOpSingleOutputPerf.h"
+#include "PerfTest.h"
 
 #include "src/__support/FPUtil/generic/FMod.h"
 #include "src/__support/macros/properties/types.h"
@@ -16,12 +16,12 @@
 #define FMOD_FUNC(U) (LIBC_NAMESPACE::fputil::generic::FMod<float16, U>::eval)
 
 int main() {
-  BINARY_OP_SINGLE_OUTPUT_PERF_EX(float16, float16, FMOD_FUNC(uint16_t),
-                                  FMOD_FUNC(uint32_t), 5000,
-                                  "fmodf16_u16_vs_u32_perf.log")
+  BINARY_INPUT_SINGLE_OUTPUT_PERF_EX(float16, float16, FMOD_FUNC(uint16_t),
+                                     FMOD_FUNC(uint32_t), 5000,
+                                     "fmodf16_u16_vs_u32_perf.log")
 
-  BINARY_OP_SINGLE_OUTPUT_PERF_EX(float16, float16, FMOD_FUNC(uint16_t),
-                                  FMOD_FUNC(uint64_t), 5000,
-                                  "fmodf16_u16_vs_u64_perf.log")
+  BINARY_INPUT_SINGLE_OUTPUT_PERF_EX(float16, float16, FMOD_FUNC(uint16_t),
+                                     FMOD_FUNC(uint64_t), 5000,
+                                     "fmodf16_u16_vs_u64_perf.log")
   return 0;
 }
diff --git a/libc/test/src/math/performance_testing/fmodf_perf.cpp b/libc/test/src/math/performance_testing/fmodf_perf.cpp
index b4f37ef25e676..27cc7eda6a892 100644
--- a/libc/test/src/math/performance_testing/fmodf_perf.cpp
+++ b/libc/test/src/math/performance_testing/fmodf_perf.cpp
@@ -6,11 +6,13 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "BinaryOpSingleOutputPerf.h"
-
+#include "PerfTest.h"
 #include "src/math/fmodf.h"
 
 #include <math.h>
 
-BINARY_OP_SINGLE_OUTPUT_PERF(float, float, LIBC_NAMESPACE::fmodf, ::fmodf,
-                             "fmodf_perf.log")
+int main() {
+  BINARY_INPUT_SINGLE_OUTPUT_PERF(float, float, LIBC_NAMESPACE::fmodf, ::fmodf,
+                                  "fmodf_perf.log")
+  return 0;
+}
diff --git a/libc/test/src/math/performance_testing/fmodl_perf.cpp b/libc/test/src/math/performance_testing/fmodl_perf.cpp
index aefdf2d6b42fc..bb5a1d83fa9f1 100644
--- a/libc/test/src/math/performance_testing/fmodl_perf.cpp
+++ b/libc/test/src/math/performance_testing/fmodl_perf.cpp
@@ -6,11 +6,14 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "BinaryOpSingleOutputDiff.h"
-
+#include "PerfTest.h"
 #include "src/math/fmodl.h"
 
 #include <math.h>
 
-BINARY_OP_SINGLE_OUTPUT_PERF(long double, LIBC_NAMESPACE::fmodl, ::fmodl,
-                             "fmodl_perf.log")
+int main() {
+  BINARY_INPUT_SINGLE_OUTPUT_PERF(long double, long double,
+                                  LIBC_NAMESPACE::fmodl, ::fmodl,
+                                  "fmodl_perf.log")
+  return 0;
+}
diff --git a/libc/test/src/math/performance_testing/fmul_perf.cpp b/libc/test/src/math/performance_testing/fmul_perf.cpp
index f15cfafbf2945..0a8dcfea121e8 100644
--- a/libc/test/src/math/performance_testing/fmul_perf.cpp
+++ b/libc/test/src/math/performance_testing/fmul_perf.cpp
@@ -6,7 +6,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "BinaryOpSingleOutputPerf.h"
+#include "PerfTest.h"
 #include "src/__support/FPUtil/generic/mul.h"
 #include "src/math/fmul.h"
 
@@ -17,8 +17,8 @@ float fmul_placeholder_binary(double x, double y) {
 }
 
 int main() {
-  BINARY_OP_SINGLE_OUTPUT_PERF_EX(float, double, LIBC_NAMESPACE::fmul,
-                                  fmul_placeholder_binary, DOUBLE_ROUNDS,
-                                  "fmul_perf.log")
+  BINARY_INPUT_SINGLE_OUTPUT_PERF_EX(float, double, LIBC_NAMESPACE::fmul,
+                                     fmul_placeholder_binary, DOUBLE_ROUNDS,
+                                     "fmul_perf.log")
   return 0;
 }
diff --git a/libc/test/src/math/performance_testing/fmull_perf.cpp b/libc/test/src/math/performance_testing/fmull_perf.cpp
index 058e10288dbde..16ea375b8ee12 100644
--- a/libc/test/src/math/performance_testing/fmull_perf.cpp
+++ b/libc/test/src/math/performance_testing/fmull_perf.cpp
@@ -6,7 +6,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "BinaryOpSingleOutputPerf.h"
+#include "PerfTest.h"
 #include "src/math/fmull.h"
 
 static constexpr size_t LONG_DOUBLE_ROUNDS = 40;
@@ -16,8 +16,8 @@ float fmull_placeholder_binary(long double x, long double y) {
 }
 
 int main() {
-  BINARY_OP_SINGLE_OUTPUT_PERF_EX(float, long double, LIBC_NAMESPACE::fmull,
-                                  fmull_placeholder_binary, LONG_DOUBLE_ROUNDS,
-                                  "fmull_perf.log")
+  BINARY_INPUT_SINGLE_OUTPUT_PERF_EX(float, long double, LIBC_NAMESPACE::fmull,
+                                     fmull_placeholder_binary,
+                                     LONG_DOUBLE_ROUNDS, "fmull_perf.log")
   return 0;
 }
diff --git a/libc/test/src/math/performance_testing/hypot_perf.cpp b/libc/test/src/math/performance_testing/hypot_perf.cpp
index 04a493ff0e025..f7a310736d56a 100644
--- a/libc/test/src/math/performance_testing/hypot_perf.cpp
+++ b/libc/test/src/math/performance_testing/hypot_perf.cpp
@@ -6,11 +6,13 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "BinaryOpSingleOutputPerf.h"
-
+#include "PerfTest.h"
 #include "src/math/hypot.h"
 
 #include <math.h>
 
-BINARY_OP_SINGLE_OUTPUT_PERF(double, double, LIBC_NAMESPACE::hypot, ::hypot,
-                             "hypot_perf.log")
+int main() {
+  BINARY_INPUT_SINGLE_OUTPUT_PERF(double, double, LIBC_NAMESPACE::hypot,
+                                  ::hypot, "hypot_perf.log")
+  return 0;
+}
diff --git a/libc/test/src/math/performance_testing/hypotf16_perf.cpp b/libc/test/src/math/performance_testing/hypotf16_perf.cpp
index b53a9042171a6..883331ad4db18 100644
--- a/libc/test/src/math/performance_testing/hypotf16_perf.cpp
+++ b/libc/test/src/math/performance_testing/hypotf16_perf.cpp
@@ -6,11 +6,14 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "BinaryOpSingleOutputPerf.h"
+#include "PerfTest.h"
 
 #include "src/__support/FPUtil/Hypot.h"
 #include "src/math/hypotf16.h"
 
-BINARY_OP_SINGLE_OUTPUT_PERF(float16, float16, LIBC_NAMESPACE::hypotf16,
-                             LIBC_NAMESPACE::fputil::hypot<float16>,
-                             "hypotf16_perf.log")
+int main() {
+  BINARY_INPUT_SINGLE_OUTPUT_PERF(float16, float16, LIBC_NAMESPACE::hypotf16,
+                                  LIBC_NAMESPACE::fputil::hypot<float16>,
+                                  "hypotf16_perf.log")
+  return 0;
+}
diff --git a/libc/test/src/math/performance_testing/hypotf_perf.cpp b/libc/test/src/math/performance_testing/hypotf_perf.cpp
index 8a42f792263c9..00f22335b70a9 100644
--- a/libc/test/src/math/performance_testing/hypotf_perf.cpp
+++ b/libc/test/src/math/performance_testing/hypotf_perf.cpp
@@ -6,11 +6,14 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "BinaryOpSingleOutputPerf.h"
+#include "PerfTest.h"
 
 #include "src/math/hypotf.h"
 
 #include <math.h>
 
-BINARY_OP_SINGLE_OUTPUT_PERF(float, float, LIBC_NAMESPACE::hypotf, ::hypotf,
-                             "hypotf_perf.log")
+int main() {
+  BINARY_INPUT_SINGLE_OUTPUT_PERF(float, float, LIBC_NAMESPACE::hypotf,
+                                  ::hypotf, "hypotf_perf.log")
+  return 0;
+}
diff --git a/libc/test/src/math/performance_testing/log10f_perf.cpp b/libc/test/src/math/performance_testing/log10f_perf.cpp
index 32a31b9325285..87e191e72d3a6 100644
--- a/libc/test/src/math/performance_testing/log10f_perf.cpp
+++ b/libc/test/src/math/performance_testing/log10f_perf.cpp
@@ -6,11 +6,13 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "SingleInputSingleOutputPerf.h"
-
+#include "PerfTest.h"
 #include "src/math/log10f.h"
 
 #include <math.h>
 
-SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::log10f, ::log10f,
-                                "log10f_perf.log")
+int main() {
+  SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::log10f, ::log10f,
+                                  "log10f_perf.log")
+  return 0;
+}
diff --git a/libc/test/src/math/performance_testing/log1pf_perf.cpp b/libc/test/src/math/performance_testing/log1pf_perf.cpp
index 18c168423b87d..2484b03efc103 100644
--- a/libc/test/src/math/performance_testing/log1pf_perf.cpp
+++ b/libc/test/src/math/performance_testing/log1pf_perf.cpp
@@ -6,11 +6,13 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "SingleInputSingleOutputPerf.h"
-
+#include "PerfTest.h"
 #include "src/math/log1pf.h"
 
 #include <math.h>
 
-SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::log1pf, ::log1pf,
-                                "log1pf_perf.log")
+int main() {
+  SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::log1pf, ::log1pf,
+                                  "log1pf_perf.log")
+  return 0;
+}
diff --git a/libc/test/src/math/performance_testing/log2f_perf.cpp b/libc/test/src/math/performance_testing/log2f_perf.cpp
index c4c4dbf4d9f55..9d0e6e5858d37 100644
--- a/libc/test/src/math/performance_testing/log2f_perf.cpp
+++ b/libc/test/src/math/performance_testing/log2f_perf.cpp
@@ -6,11 +6,13 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "SingleInputSingleOutputPerf.h"
-
+#include "PerfTest.h"
 #include "src/math/log2f.h"
 
 #include <math.h>
 
-SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::log2f, ::log2f,
-                                "log2f_perf.log")
+int main() {
+  SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::log2f, ::log2f,
+                                  "log2f_perf.log")
+  return 0;
+}
diff --git a/libc/test/src/math/performance_testing/logbf_perf.cpp b/libc/test/src/math/performance_testing/logbf_perf.cpp
index eefd64b8ae913..b5e6d1ffeb609 100644
--- a/libc/test/src/math/performance_testing/logbf_perf.cpp
+++ b/libc/test/src/math/performance_testing/logbf_perf.cpp
@@ -6,11 +6,13 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "SingleInputSingleOutputPerf.h"
-
+#include "PerfTest.h"
 #include "src/math/logbf.h"
 
 #include <math.h>
 
-SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::logbf, ::logbf,
-                                "logbf_perf.log")
+int main() {
+  SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::logbf, ::logbf,
+                                  "logbf_perf.log")
+  return 0;
+}
diff --git a/libc/test/src/math/performance_testing/logf_perf.cpp b/libc/test/src/math/performance_testing/logf_perf.cpp
index 53f4f50e09efe..b078d9f478442 100644
--- a/libc/test/src/math/performance_testing/logf_perf.cpp
+++ b/libc/test/src/math/performance_testing/logf_perf.cpp
@@ -6,11 +6,13 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "SingleInputSingleOutputPerf.h"
-
+#include "PerfTest.h"
 #include "src/math/logf.h"
 
 #include <math.h>
 
-SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::logf, ::logf,
-                                "logf_perf.log")
+int main() {
+  SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::logf, ::logf,
+                                  "logf_perf.log")
+  return 0;
+}
diff --git a/libc/test/src/math/performance_testing/max_min_funcs_perf.cpp b/libc/test/src/math/performance_testing/max_min_funcs_perf.cpp
index b77268d107c58..7bf9a8621f2b7 100644
--- a/libc/test/src/math/performance_testing/max_min_funcs_perf.cpp
+++ b/libc/test/src/math/performance_testing/max_min_funcs_perf.cpp
@@ -6,7 +6,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "BinaryOpSingleOutputPerf.h"
+#include "PerfTest.h"
 #include "src/math/fmaxf.h"
 #include "src/math/fmaxf16.h"
 #include "src/math/fmaximum_numf.h"
@@ -35,41 +35,40 @@ float16 placeholder_binaryf16(float16 x, float16 y) { return x; }
 float placeholder_binaryf(float x, float y) { return x; }
 
 int main() {
-  BINARY_OP_SINGLE_OUTPUT_PERF_EX(float16, float16, LIBC_NAMESPACE::fmaxf16,
-                                  placeholder_binaryf16, FLOAT16_ROUNDS,
-                                  "fmaxf16_perf.log")
-  BINARY_OP_SINGLE_OUTPUT_PERF_EX(float16, float16, LIBC_NAMESPACE::fminf16,
-                                  placeholder_binaryf16, FLOAT16_ROUNDS,
-                                  "fminf16_perf.log")
-  BINARY_OP_SINGLE_OUTPUT_PERF_EX(float16, float16, LIBC_NAMESPACE::fmaximumf16,
-                                  placeholder_binaryf16, FLOAT16_ROUNDS,
-                                  "fmaximumf16_perf.log")
-  BINARY_OP_SINGLE_OUTPUT_PERF_EX(float16, float16, LIBC_NAMESPACE::fminimumf16,
-                                  placeholder_binaryf16, FLOAT16_ROUNDS,
-                                  "fminimumf16_perf.log")
-  BINARY_OP_SINGLE_OUTPUT_PERF_EX(
+  BINARY_INPUT_SINGLE_OUTPUT_PERF_EX(float16, float16, LIBC_NAMESPACE::fmaxf16,
+                                     placeholder_binaryf16, FLOAT16_ROUNDS,
+                                     "fmaxf16_perf.log")
+  BINARY_INPUT_SINGLE_OUTPUT_PERF_EX(float16, float16, LIBC_NAMESPACE::fminf16,
+                                     placeholder_binaryf16, FLOAT16_ROUNDS,
+                                     "fminf16_perf.log")
+  BINARY_INPUT_SINGLE_OUTPUT_PERF_EX(
+      float16, float16, LIBC_NAMESPACE::fmaximumf16, placeholder_binaryf16,
+      FLOAT16_ROUNDS, "fmaximumf16_perf.log")
+  BINARY_INPUT_SINGLE_OUTPUT_PERF_EX(
+      float16, float16, LIBC_NAMESPACE::fminimumf16, placeholder_binaryf16,
+      FLOAT16_ROUNDS, "fminimumf16_perf.log")
+  BINARY_INPUT_SINGLE_OUTPUT_PERF_EX(
       float16, float16, LIBC_NAMESPACE::fmaximum_numf16, placeholder_binaryf16,
       FLOAT16_ROUNDS, "fmaximum_numf16_perf.log")
-  BINARY_OP_SINGLE_OUTPUT_PERF_EX(
+  BINARY_INPUT_SINGLE_OUTPUT_PERF_EX(
       float16, float16, LIBC_NAMESPACE::fminimum_numf16, placeholder_binaryf16,
       FLOAT16_ROUNDS, "fminimum_numf16_perf.log")
 
-  BINARY_OP_SINGLE_OUTPUT_PERF_EX(float, float, LIBC_NAMESPACE::fmaxf, ::fmaxf,
-                                  FLOAT_ROUNDS, "fmaxf_perf.log")
-  BINARY_OP_SINGLE_OUTPUT_PERF_EX(float, float, LIBC_NAMESPACE::fminf, ::fminf,
-                                  FLOAT_ROUNDS, "fminf_perf.log")
-  BINARY_OP_SINGLE_OUTPUT_PERF_EX(float, float, LIBC_NAMESPACE::fmaximumf,
-                                  placeholder_binaryf, FLOAT_ROUNDS,
-                                  "fmaximumf_perf.log")
-  BINARY_OP_SINGLE_OUTPUT_PERF_EX(float, float, LIBC_NAMESPACE::fminimumf,
-                                  placeholder_binaryf, FLOAT_ROUNDS,
-                                  "fminimumf_perf.log")
-  BINARY_OP_SINGLE_OUTPUT_PERF_EX(float, float, LIBC_NAMESPACE::fmaximum_numf,
-                                  placeholder_binaryf, FLOAT_ROUNDS,
-                                  "fmaximum_numf_perf.log")
-  BINARY_OP_SINGLE_OUTPUT_PERF_EX(float, float, LIBC_NAMESPACE::fminimum_numf,
-                                  placeholder_binaryf, FLOAT_ROUNDS,
-                                  "fminimum_numf_perf.log")
-
+  BINARY_INPUT_SINGLE_OUTPUT_PERF_EX(float, float, LIBC_NAMESPACE::fmaxf,
+                                     ::fmaxf, FLOAT_ROUNDS, "fmaxf_perf.log")
+  BINARY_INPUT_SINGLE_OUTPUT_PERF_EX(float, float, LIBC_NAMESPACE::fminf,
+                                     ::fminf, FLOAT_ROUNDS, "fminf_perf.log")
+  BINARY_INPUT_SINGLE_OUTPUT_PERF_EX(float, float, LIBC_NAMESPACE::fmaximumf,
+                                     placeholder_binaryf, FLOAT_ROUNDS,
+                                     "fmaximumf_perf.log")
+  BINARY_INPUT_SINGLE_OUTPUT_PERF_EX(float, float, LIBC_NAMESPACE::fminimumf,
+                                     placeholder_binaryf, FLOAT_ROUNDS,
+                                     "fminimumf_perf.log")
+  BINARY_INPUT_SINGLE_OUTPUT_PERF_EX(
+      float, float, LIBC_NAMESPACE::fmaximum_numf, placeholder_binaryf,
+      FLOAT_ROUNDS, "fmaximum_numf_perf.log")
+  BINARY_INPUT_SINGLE_OUTPUT_PERF_EX(
+      float, float, LIBC_NAMESPACE::fminimum_numf, placeholder_binaryf,
+      FLOAT_ROUNDS, "fminimum_numf_perf.log")
   return 0;
 }
diff --git a/libc/test/src/math/performance_testing/misc_basic_ops_perf.cpp b/libc/test/src/math/performance_testing/misc_basic_ops_perf.cpp
index 9a4522c307ac7..6f7864e5eabae 100644
--- a/libc/test/src/math/performance_testing/misc_basic_ops_perf.cpp
+++ b/libc/test/src/math/performance_testing/misc_basic_ops_perf.cpp
@@ -6,8 +6,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "BinaryOpSingleOutputPerf.h"
-#include "SingleInputSingleOutputPerf.h"
+#include "PerfTest.h"
 #include "src/math/copysignf.h"
 #include "src/math/copysignf16.h"
 #include "src/math/fabsf.h"
@@ -28,14 +27,15 @@ int main() {
   SINGLE_INPUT_SINGLE_OUTPUT_PERF_EX(float16, LIBC_NAMESPACE::fabsf16,
                                      placeholder_unaryf16, FLOAT16_ROUNDS,
                                      "fabsf16_perf.log")
-  BINARY_OP_SINGLE_OUTPUT_PERF_EX(float16, float16, LIBC_NAMESPACE::copysignf16,
-                                  placeholder_binaryf16, FLOAT16_ROUNDS,
-                                  "copysignf16_perf.log")
+  BINARY_INPUT_SINGLE_OUTPUT_PERF_EX(
+      float16, float16, LIBC_NAMESPACE::copysignf16, placeholder_binaryf16,
+      FLOAT16_ROUNDS, "copysignf16_perf.log")
 
   SINGLE_INPUT_SINGLE_OUTPUT_PERF_EX(float, LIBC_NAMESPACE::fabsf, fabsf,
                                      FLOAT_ROUNDS, "fabsf_perf.log")
-  BINARY_OP_SINGLE_OUTPUT_PERF_EX(float, float, LIBC_NAMESPACE::copysignf,
-                                  copysignf, FLOAT_ROUNDS, "copysignf_perf.log")
+  BINARY_INPUT_SINGLE_OUTPUT_PERF_EX(float, float, LIBC_NAMESPACE::copysignf,
+                                     copysignf, FLOAT_ROUNDS,
+                                     "copysignf_perf.log")
 
   return 0;
 }
diff --git a/libc/test/src/math/performance_testing/nearbyintf_perf.cpp b/libc/test/src/math/performance_testing/nearbyintf_perf.cpp
index ae708dd213243..3fa844dfbed96 100644
--- a/libc/test/src/math/performance_testing/nearbyintf_perf.cpp
+++ b/libc/test/src/math/performance_testing/nearbyintf_perf.cpp
@@ -6,11 +6,13 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "SingleInputSingleOutputPerf.h"
-
+#include "PerfTest.h"
 #include "src/math/nearbyintf.h"
 
 #include <math.h>
 
-SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::nearbyintf, ::nearbyintf,
-                                "nearbyintf_perf.log")
+int main() {
+  SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::nearbyintf,
+                                  ::nearbyintf, "nearbyintf_perf.log")
+  return 0;
+}
diff --git a/libc/test/src/math/performance_testing/nearest_integer_funcs_perf.cpp b/libc/test/src/math/performance_testing/nearest_integer_funcs_perf.cpp
index b7bd6636a72e1..fa5f80fdba9f0 100644
--- a/libc/test/src/math/performance_testing/nearest_integer_funcs_perf.cpp
+++ b/libc/test/src/math/performance_testing/nearest_integer_funcs_perf.cpp
@@ -40,7 +40,8 @@ template <typename T> class NearestIntegerPerf {
   static void run_perf_in_range(Func my_func, Func other_func,
                                 StorageType starting_bit,
                                 StorageType ending_bit, StorageType step,
-                                size_t rounds, std::ofstream &log) {
+                                size_t rounds, const char *name_a,
+                                const char *name_b, std::ofstream &log) {
     auto runner = [=](Func func) {
       [[maybe_unused]] volatile T result;
       for (size_t i = 0; i < rounds; i++) {
@@ -60,7 +61,7 @@ template <typename T> class NearestIntegerPerf {
     size_t number_of_runs = (ending_bit - starting_bit) / step + 1;
     double my_average =
         static_cast<double>(timer.nanoseconds()) / number_of_runs / rounds;
-    log << "-- My function --\n";
+    log << "-- Function A: " << name_a << " --\n";
     log << "     Total time      : " << timer.nanoseconds() << " ns \n";
     log << "     Average runtime : " << my_average << " ns/op \n";
     log << "     Ops per second  : "
@@ -72,17 +73,18 @@ template <typename T> class NearestIntegerPerf {
 
     double other_average =
         static_cast<double>(timer.nanoseconds()) / number_of_runs / rounds;
-    log << "-- Other function --\n";
+    log << "-- Function B: " << name_b << " --\n";
     log << "     Total time      : " << timer.nanoseconds() << " ns \n";
     log << "     Average runtime : " << other_average << " ns/op \n";
     log << "     Ops per second  : "
         << static_cast<uint64_t>(1'000'000'000.0 / other_average) << " op/s \n";
 
-    log << "-- Average runtime ratio --\n";
-    log << "     Mine / Other's  : " << my_average / other_average << " \n";
+    log << "-- Average ops per second ratio --\n";
+    log << "     A / B  : " << other_average / my_average << " \n";
   }
 
   static void run_perf(Func my_func, Func other_func, size_t rounds,
+                       const char *name_a, const char *name_b,
                        const char *log_file) {
     std::ofstream log(log_file);
     log << "Performance tests with inputs in normal integral range:\n";
@@ -93,14 +95,14 @@ template <typename T> class NearestIntegerPerf {
         StorageType((FPBits::EXP_BIAS + FPBits::FRACTION_LEN - 1)
                     << FPBits::SIG_LEN),
         /*step=*/StorageType(1 << FPBits::SIG_LEN),
-        rounds * FPBits::EXP_BIAS * FPBits::EXP_BIAS * 2, log);
+        rounds * FPBits::EXP_BIAS * FPBits::EXP_BIAS * 2, name_a, name_b, log);
     log << "\n Performance tests with inputs in low integral range:\n";
     run_perf_in_range(
         my_func, other_func,
         /*starting_bit=*/StorageType(1 << FPBits::SIG_LEN),
         /*ending_bit=*/StorageType((FPBits::EXP_BIAS - 1) << FPBits::SIG_LEN),
         /*step_bit=*/StorageType(1 << FPBits::SIG_LEN),
-        rounds * FPBits::EXP_BIAS * FPBits::EXP_BIAS * 2, log);
+        rounds * FPBits::EXP_BIAS * FPBits::EXP_BIAS * 2, name_a, name_b, log);
     log << "\n Performance tests with inputs in high integral range:\n";
     run_perf_in_range(
         my_func, other_func,
@@ -110,7 +112,7 @@ template <typename T> class NearestIntegerPerf {
         /*ending_bit=*/
         StorageType(FPBits::MAX_BIASED_EXPONENT << FPBits::SIG_LEN),
         /*step=*/StorageType(1 << FPBits::SIG_LEN),
-        rounds * FPBits::EXP_BIAS * FPBits::EXP_BIAS * 2, log);
+        rounds * FPBits::EXP_BIAS * FPBits::EXP_BIAS * 2, name_a, name_b, log);
     log << "\n Performance tests with inputs in normal fractional range:\n";
     run_perf_in_range(
         my_func, other_func,
@@ -118,11 +120,11 @@ template <typename T> class NearestIntegerPerf {
         StorageType(((FPBits::EXP_BIAS + 1) << FPBits::SIG_LEN) + 1),
         /*ending_bit=*/
         StorageType(((FPBits::EXP_BIAS + 2) << FPBits::SIG_LEN) - 1),
-        /*step=*/StorageType(1), rounds * 2, log);
+        /*step=*/StorageType(1), rounds * 2, name_a, name_b, log);
     log << "\n Performance tests with inputs in subnormal fractional range:\n";
     run_perf_in_range(my_func, other_func, /*starting_bit=*/StorageType(1),
                       /*ending_bit=*/StorageType(FPBits::SIG_MASK),
-                      /*step=*/StorageType(1), rounds, log);
+                      /*step=*/StorageType(1), rounds, name_a, name_b, log);
   }
 };
 
@@ -131,9 +133,7 @@ template <typename T> class NearestIntegerPerf {
 #define NEAREST_INTEGER_PERF(T, my_func, other_func, rounds, filename)         \
   {                                                                            \
     LIBC_NAMESPACE::testing::NearestIntegerPerf<T>::run_perf(                  \
-        &my_func, &other_func, rounds, filename);                              \
-    LIBC_NAMESPACE::testing::NearestIntegerPerf<T>::run_perf(                  \
-        &my_func, &other_func, rounds, filename);                              \
+        &my_func, &other_func, rounds, #my_func, #other_func, filename);       \
   }
 
 static constexpr size_t FLOAT16_ROUNDS = 20'000;
diff --git a/libc/test/src/math/performance_testing/rintf_perf.cpp b/libc/test/src/math/performance_testing/rintf_perf.cpp
index 6347ac9149af6..f54b19c4dd157 100644
--- a/libc/test/src/math/performance_testing/rintf_perf.cpp
+++ b/libc/test/src/math/performance_testing/rintf_perf.cpp
@@ -6,11 +6,13 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "SingleInputSingleOutputPerf.h"
-
+#include "PerfTest.h"
 #include "src/math/rintf.h"
 
 #include <math.h>
 
-SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::rintf, ::rintf,
-                                "rintf_perf.log")
+int main() {
+  SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::rintf, ::rintf,
+                                  "rintf_perf.log")
+  return 0;
+}
diff --git a/libc/test/src/math/performance_testing/roundf_perf.cpp b/libc/test/src/math/performance_testing/roundf_perf.cpp
index 36becacba07cb..fb2a6309c89ed 100644
--- a/libc/test/src/math/performance_testing/roundf_perf.cpp
+++ b/libc/test/src/math/performance_testing/roundf_perf.cpp
@@ -6,11 +6,13 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "SingleInputSingleOutputPerf.h"
-
+#include "PerfTest.h"
 #include "src/math/roundf.h"
 
 #include <math.h>
 
-SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::roundf, ::roundf,
-                                "roundf_perf.log")
+int main() {
+  SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::roundf, ::roundf,
+                                  "roundf_perf.log")
+  return 0;
+}
diff --git a/libc/test/src/math/performance_testing/sinf_perf.cpp b/libc/test/src/math/performance_testing/sinf_perf.cpp
index 43ba60e1ef76a..e12a4b1dbb3ff 100644
--- a/libc/test/src/math/performance_testing/sinf_perf.cpp
+++ b/libc/test/src/math/performance_testing/sinf_perf.cpp
@@ -6,11 +6,13 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "SingleInputSingleOutputPerf.h"
-
+#include "PerfTest.h"
 #include "src/math/sinf.h"
 
 #include <math.h>
 
-SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::sinf, ::sinf,
-                                "sinf_perf.log")
+int main() {
+  SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::sinf, ::sinf,
+                                  "sinf_perf.log")
+  return 0;
+}
diff --git a/libc/test/src/math/performance_testing/sqrtf128_perf.cpp b/libc/test/src/math/performance_testing/sqrtf128_perf.cpp
index bc04e698b2439..e6a30aff7d463 100644
--- a/libc/test/src/math/performance_testing/sqrtf128_perf.cpp
+++ b/libc/test/src/math/performance_testing/sqrtf128_perf.cpp
@@ -7,8 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "SingleInputSingleOutputPerf.h"
-
+#include "PerfTest.h"
 #include "src/__support/FPUtil/sqrt.h"
 #include "src/math/sqrtf128.h"
 
@@ -16,5 +15,8 @@ float128 sqrtf128_placeholder(float128 x) {
   return LIBC_NAMESPACE::fputil::sqrt<float128>(x);
 }
 
-SINGLE_INPUT_SINGLE_OUTPUT_PERF(float128, LIBC_NAMESPACE::sqrtf128,
-                                ::sqrtf128_placeholder, "sqrtf128_perf.log")
+int main() {
+  SINGLE_INPUT_SINGLE_OUTPUT_PERF(float128, LIBC_NAMESPACE::sqrtf128,
+                                  ::sqrtf128_placeholder, "sqrtf128_perf.log")
+  return 0;
+}
diff --git a/libc/test/src/math/performance_testing/sqrtf_perf.cpp b/libc/test/src/math/performance_testing/sqrtf_perf.cpp
index 71325518533b6..a244e3c567567 100644
--- a/libc/test/src/math/performance_testing/sqrtf_perf.cpp
+++ b/libc/test/src/math/performance_testing/sqrtf_perf.cpp
@@ -6,11 +6,13 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "SingleInputSingleOutputPerf.h"
-
+#include "PerfTest.h"
 #include "src/math/sqrtf.h"
 
 #include <math.h>
 
-SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::sqrtf, ::sqrtf,
-                                "sqrtf_perf.log")
+int main() {
+  SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::sqrtf, ::sqrtf,
+                                  "sqrtf_perf.log")
+  return 0;
+}
diff --git a/libc/test/src/math/performance_testing/truncf_perf.cpp b/libc/test/src/math/performance_testing/truncf_perf.cpp
index ff74c6b4eb64d..11c7d23b92800 100644
--- a/libc/test/src/math/performance_testing/truncf_perf.cpp
+++ b/libc/test/src/math/performance_testing/truncf_perf.cpp
@@ -6,11 +6,13 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "SingleInputSingleOutputPerf.h"
-
+#include "PerfTest.h"
 #include "src/math/truncf.h"
 
 #include <math.h>
 
-SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::truncf, ::truncf,
-                                "truncf_perf.log")
+int main() {
+  SINGLE_INPUT_SINGLE_OUTPUT_PERF(float, LIBC_NAMESPACE::truncf, ::truncf,
+                                  "truncf_perf.log")
+  return 0;
+}
diff --git a/libclc/CMakeLists.txt b/libclc/CMakeLists.txt
index dbbc29261d3b5..50ddfc3930cd3 100644
--- a/libclc/CMakeLists.txt
+++ b/libclc/CMakeLists.txt
@@ -411,6 +411,9 @@ foreach( t ${LIBCLC_TARGETS_TO_BUILD} )
     set( LIBCLC_ARCH_OBJFILE_DIR "${LIBCLC_OBJFILE_DIR}/${arch_suffix}" )
     file( MAKE_DIRECTORY ${LIBCLC_ARCH_OBJFILE_DIR} )
 
+    # Build for OpenCL 3.0 independently of the target or device.
+    list( APPEND build_flags -cl-std=CL3.0 )
+
     string( TOUPPER "CLC_${MACRO_ARCH}" CLC_TARGET_DEFINE )
 
     list( APPEND build_flags
@@ -438,8 +441,6 @@ foreach( t ${LIBCLC_TARGETS_TO_BUILD} )
 
     list( APPEND build_flags
       -I${CMAKE_CURRENT_SOURCE_DIR}/generic/include
-      # FIXME: Fix libclc to not require disabling this noisy warning
-      -Wno-bitwise-conditional-parentheses
     )
 
     add_libclc_builtin_set(
diff --git a/libclc/amdgpu/lib/SOURCES_3.9 b/libclc/amdgpu/lib/SOURCES_3.9
deleted file mode 100644
index 69c5e5ce9fbac..0000000000000
--- a/libclc/amdgpu/lib/SOURCES_3.9
+++ /dev/null
@@ -1,2 +0,0 @@
-shared/vload_half_helpers.ll
-shared/vstore_half_helpers.ll
diff --git a/libclc/amdgpu/lib/SOURCES_4.0 b/libclc/amdgpu/lib/SOURCES_4.0
deleted file mode 100644
index 69c5e5ce9fbac..0000000000000
--- a/libclc/amdgpu/lib/SOURCES_4.0
+++ /dev/null
@@ -1,2 +0,0 @@
-shared/vload_half_helpers.ll
-shared/vstore_half_helpers.ll
diff --git a/libclc/amdgpu/lib/SOURCES_5.0 b/libclc/amdgpu/lib/SOURCES_5.0
deleted file mode 100644
index 69c5e5ce9fbac..0000000000000
--- a/libclc/amdgpu/lib/SOURCES_5.0
+++ /dev/null
@@ -1,2 +0,0 @@
-shared/vload_half_helpers.ll
-shared/vstore_half_helpers.ll
diff --git a/libclc/amdgpu/lib/shared/vload_half_helpers.ll b/libclc/amdgpu/lib/shared/vload_half_helpers.ll
deleted file mode 100644
index bf7d544afbf55..0000000000000
--- a/libclc/amdgpu/lib/shared/vload_half_helpers.ll
+++ /dev/null
@@ -1,31 +0,0 @@
-;;===----------------------------------------------------------------------===;;
-;
-; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-; See https://llvm.org/LICENSE.txt for license information.
-; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-;
-;;===----------------------------------------------------------------------===;;
-
-define float @__clc_vload_half_float_helper__private(half addrspace(0)* nocapture %ptr) nounwind alwaysinline {
-  %data = load half, half addrspace(0)* %ptr
-  %res = fpext half %data to float
-  ret float %res
-}
-
-define float @__clc_vload_half_float_helper__global(half addrspace(1)* nocapture %ptr) nounwind alwaysinline {
-  %data = load half, half addrspace(1)* %ptr
-  %res = fpext half %data to float
-  ret float %res
-}
-
-define float @__clc_vload_half_float_helper__local(half addrspace(3)* nocapture %ptr) nounwind alwaysinline {
-  %data = load half, half addrspace(3)* %ptr
-  %res = fpext half %data to float
-  ret float %res
-}
-
-define float @__clc_vload_half_float_helper__constant(half addrspace(2)* nocapture %ptr) nounwind alwaysinline {
-  %data = load half, half addrspace(2)* %ptr
-  %res = fpext half %data to float
-  ret float %res
-}
diff --git a/libclc/amdgpu/lib/shared/vstore_half_helpers.ll b/libclc/amdgpu/lib/shared/vstore_half_helpers.ll
deleted file mode 100644
index 5ec193d6d40a0..0000000000000
--- a/libclc/amdgpu/lib/shared/vstore_half_helpers.ll
+++ /dev/null
@@ -1,43 +0,0 @@
-;;===----------------------------------------------------------------------===;;
-;
-; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-; See https://llvm.org/LICENSE.txt for license information.
-; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-;
-;;===----------------------------------------------------------------------===;;
-
-define void @__clc_vstore_half_float_helper__private(float %data, half addrspace(0)* nocapture %ptr) nounwind alwaysinline {
-  %res = fptrunc float %data to half
-  store half %res, half addrspace(0)* %ptr
-  ret void
-}
-
-define void @__clc_vstore_half_float_helper__global(float %data, half addrspace(1)* nocapture %ptr) nounwind alwaysinline {
-  %res = fptrunc float %data to half
-  store half %res, half addrspace(1)* %ptr
-  ret void
-}
-
-define void @__clc_vstore_half_float_helper__local(float %data, half addrspace(3)* nocapture %ptr) nounwind alwaysinline {
-  %res = fptrunc float %data to half
-  store half %res, half addrspace(3)* %ptr
-  ret void
-}
-
-define void @__clc_vstore_half_double_helper__private(double %data, half addrspace(0)* nocapture %ptr) nounwind alwaysinline {
-  %res = fptrunc double %data to half
-  store half %res, half addrspace(0)* %ptr
-  ret void
-}
-
-define void @__clc_vstore_half_double_helper__global(double %data, half addrspace(1)* nocapture %ptr) nounwind alwaysinline {
-  %res = fptrunc double %data to half
-  store half %res, half addrspace(1)* %ptr
-  ret void
-}
-
-define void @__clc_vstore_half_double_helper__local(double %data, half addrspace(3)* nocapture %ptr) nounwind alwaysinline {
-  %res = fptrunc double %data to half
-  store half %res, half addrspace(3)* %ptr
-  ret void
-}
diff --git a/libclc/cmake/modules/AddLibclc.cmake b/libclc/cmake/modules/AddLibclc.cmake
index 154f4ea8f6cf5..3be2bf231eb30 100644
--- a/libclc/cmake/modules/AddLibclc.cmake
+++ b/libclc/cmake/modules/AddLibclc.cmake
@@ -466,16 +466,22 @@ function(libclc_configure_lib_source LIB_FILE_LIST)
   ## Add the generated convert files here to prevent adding the ones listed in
   ## SOURCES
   set( rel_files ${${LIB_FILE_LIST}} ) # Source directory input files, relative to the root dir
-  set( objects ${${LIB_FILE_LIST}} )   # A "set" of already-added input files
+  # A "set" of already-added input files
+  set( objects )
+  foreach( f ${${LIB_FILE_LIST}} )
+    get_filename_component( name ${f} NAME )
+    list( APPEND objects ${name} )
+  endforeach()
 
   foreach( l ${source_list} )
     file( READ ${l} file_list )
     string( REPLACE "\n" ";" file_list ${file_list} )
     get_filename_component( dir ${l} DIRECTORY )
     foreach( f ${file_list} )
+      get_filename_component( name ${f} NAME )
       # Only add each file once, so that targets can 'specialize' builtins
-      if( NOT ${f} IN_LIST objects )
-        list( APPEND objects ${f} )
+      if( NOT ${name} IN_LIST objects )
+        list( APPEND objects ${name} )
         list( APPEND rel_files ${dir}/${f} )
       endif()
     endforeach()
diff --git a/libclc/generic/include/clc/clc.h b/libclc/generic/include/clc/clc.h
index b1e851184d7e1..f4c0dc7c0bee4 100644
--- a/libclc/generic/include/clc/clc.h
+++ b/libclc/generic/include/clc/clc.h
@@ -35,9 +35,6 @@
 /* 6.2.4.2 Reinterpreting Types Using as_type() and as_typen() */
 #include <clc/as_type.h>
 
-/* 6.9 Preprocessor Directives and Macros */
-#include <clc/clcmacros.h>
-
 /* 6.11.1 Work-Item Functions */
 #include <clc/workitem/get_global_size.h>
 #include <clc/workitem/get_global_id.h>
diff --git a/libclc/generic/include/clc/clcmacros.h b/libclc/generic/include/clc/clcmacros.h
deleted file mode 100644
index dd96f459643f1..0000000000000
--- a/libclc/generic/include/clc/clcmacros.h
+++ /dev/null
@@ -1,31 +0,0 @@
-//===----------------------------------------------------------------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef __CLC_CLCMACROS_H__
-#define __CLC_CLCMACROS_H__
-
-/* 6.9 Preprocessor Directives and Macros
- * Some of these are handled by clang or passed by clover */
-#if __OPENCL_VERSION__ >= 110
-#define CLC_VERSION_1_0 100
-#define CLC_VERSION_1_1 110
-#endif
-
-#if __OPENCL_VERSION__ >= 120
-#define CLC_VERSION_1_2 120
-#endif
-
-#define NULL ((void *)0)
-
-#define __kernel_exec(X, typen)                                                \
-  __kernel __attribute__((work_group_size_hint(X, 1, 1)))                      \
-  __attribute__((vec_type_hint(typen)))
-
-#define kernel_exec(X, typen) __kernel_exec(X, typen)
-
-#endif // __CLC_CLCMACROS_H__
diff --git a/libclc/generic/include/clc/image/image.h b/libclc/generic/include/clc/image/image.h
index 8a7f7a38aa3e7..555ec3904c1f8 100644
--- a/libclc/generic/include/clc/image/image.h
+++ b/libclc/generic/include/clc/image/image.h
@@ -6,6 +6,8 @@
 //
 //===----------------------------------------------------------------------===//
 
+#if defined(__opencl_c_images)
+
 _CLC_OVERLOAD _CLC_DECL int get_image_width (image2d_t image);
 _CLC_OVERLOAD _CLC_DECL int get_image_width (image3d_t image);
 
@@ -42,3 +44,5 @@ _CLC_OVERLOAD _CLC_DECL uint4
 read_imageui(image2d_t image, sampler_t sampler, int2 coord);
 _CLC_OVERLOAD _CLC_DECL uint4
 read_imageui(image2d_t image, sampler_t sampler, float2 coord);
+
+#endif
diff --git a/libclc/generic/include/clc/shared/vload.h b/libclc/generic/include/clc/shared/vload.h
index b2db5551d0903..a343d652933fd 100644
--- a/libclc/generic/include/clc/shared/vload.h
+++ b/libclc/generic/include/clc/shared/vload.h
@@ -6,23 +6,24 @@
 //
 //===----------------------------------------------------------------------===//
 
-#define _CLC_VLOAD_DECL(SUFFIX, MEM_TYPE, VEC_TYPE, WIDTH, ADDR_SPACE) \
-  _CLC_OVERLOAD _CLC_DECL VEC_TYPE vload##SUFFIX##WIDTH(size_t offset, const ADDR_SPACE MEM_TYPE *x);
+#define _CLC_VLOAD_DECL(SUFFIX, MEM_TYPE, VEC_TYPE, WIDTH, ADDR_SPACE)         \
+  _CLC_OVERLOAD _CLC_DECL VEC_TYPE vload##SUFFIX##WIDTH(                       \
+      size_t offset, const ADDR_SPACE MEM_TYPE *x);
 
-#define _CLC_VECTOR_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE, ADDR_SPACE) \
-  _CLC_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##2, 2, ADDR_SPACE) \
-  _CLC_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##3, 3, ADDR_SPACE) \
-  _CLC_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##4, 4, ADDR_SPACE) \
-  _CLC_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##8, 8, ADDR_SPACE) \
+#define _CLC_VECTOR_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE, ADDR_SPACE)        \
+  _CLC_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##2, 2, ADDR_SPACE)               \
+  _CLC_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##3, 3, ADDR_SPACE)               \
+  _CLC_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##4, 4, ADDR_SPACE)               \
+  _CLC_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##8, 8, ADDR_SPACE)               \
   _CLC_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##16, 16, ADDR_SPACE)
 
-#define _CLC_VECTOR_VLOAD_PRIM3(SUFFIX, MEM_TYPE, PRIM_TYPE) \
-  _CLC_VECTOR_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE, __private) \
-  _CLC_VECTOR_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE, __local) \
-  _CLC_VECTOR_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE, __constant) \
+#define _CLC_VECTOR_VLOAD_PRIM3(SUFFIX, MEM_TYPE, PRIM_TYPE)                   \
+  _CLC_VECTOR_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE, __private)               \
+  _CLC_VECTOR_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE, __local)                 \
+  _CLC_VECTOR_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE, __constant)              \
   _CLC_VECTOR_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE, __global)
 
-#define _CLC_VECTOR_VLOAD_PRIM1(PRIM_TYPE) \
+#define _CLC_VECTOR_VLOAD_PRIM1(PRIM_TYPE)                                     \
   _CLC_VECTOR_VLOAD_PRIM3(, PRIM_TYPE, PRIM_TYPE)
 
 // Declare vector load prototypes
@@ -40,12 +41,12 @@ _CLC_VECTOR_VLOAD_PRIM3(_half, half, float)
 _CLC_VECTOR_VLOAD_PRIM3(a_half, half, float)
 
 #ifdef cl_khr_fp64
-#pragma OPENCL EXTENSION cl_khr_fp64: enable
-  _CLC_VECTOR_VLOAD_PRIM1(double)
+#pragma OPENCL EXTENSION cl_khr_fp64 : enable
+_CLC_VECTOR_VLOAD_PRIM1(double)
 #endif
 #ifdef cl_khr_fp16
-#pragma OPENCL EXTENSION cl_khr_fp16: enable
-  _CLC_VECTOR_VLOAD_PRIM1(half)
+#pragma OPENCL EXTENSION cl_khr_fp16 : enable
+_CLC_VECTOR_VLOAD_PRIM1(half)
 #endif
 
 // Scalar vload_half also needs to be declared
diff --git a/libclc/generic/include/clc/shared/vstore.h b/libclc/generic/include/clc/shared/vstore.h
index 93687e030eb41..6e98f0368c5c1 100644
--- a/libclc/generic/include/clc/shared/vstore.h
+++ b/libclc/generic/include/clc/shared/vstore.h
@@ -6,33 +6,34 @@
 //
 //===----------------------------------------------------------------------===//
 
-#define _CLC_VSTORE_DECL(SUFFIX, PRIM_TYPE, VEC_TYPE, WIDTH, ADDR_SPACE, RND) \
-  _CLC_OVERLOAD _CLC_DECL void vstore##SUFFIX##WIDTH##RND(VEC_TYPE vec, size_t offset, ADDR_SPACE PRIM_TYPE *out);
+#define _CLC_VSTORE_DECL(SUFFIX, PRIM_TYPE, VEC_TYPE, WIDTH, ADDR_SPACE, RND)  \
+  _CLC_OVERLOAD _CLC_DECL void vstore##SUFFIX##WIDTH##RND(                     \
+      VEC_TYPE vec, size_t offset, ADDR_SPACE PRIM_TYPE *out);
 
-#define _CLC_VECTOR_VSTORE_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE, ADDR_SPACE, RND) \
-  _CLC_VSTORE_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##2, 2, ADDR_SPACE, RND) \
-  _CLC_VSTORE_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##3, 3, ADDR_SPACE, RND) \
-  _CLC_VSTORE_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##4, 4, ADDR_SPACE, RND) \
-  _CLC_VSTORE_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##8, 8, ADDR_SPACE, RND) \
+#define _CLC_VECTOR_VSTORE_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE, ADDR_SPACE, RND)  \
+  _CLC_VSTORE_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##2, 2, ADDR_SPACE, RND)         \
+  _CLC_VSTORE_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##3, 3, ADDR_SPACE, RND)         \
+  _CLC_VSTORE_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##4, 4, ADDR_SPACE, RND)         \
+  _CLC_VSTORE_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##8, 8, ADDR_SPACE, RND)         \
   _CLC_VSTORE_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##16, 16, ADDR_SPACE, RND)
 
-#define _CLC_VECTOR_VSTORE_PRIM3(SUFFIX, MEM_TYPE, PRIM_TYPE, RND) \
-  _CLC_VECTOR_VSTORE_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE, __private, RND) \
-  _CLC_VECTOR_VSTORE_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE, __local, RND) \
+#define _CLC_VECTOR_VSTORE_PRIM3(SUFFIX, MEM_TYPE, PRIM_TYPE, RND)             \
+  _CLC_VECTOR_VSTORE_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE, __private, RND)         \
+  _CLC_VECTOR_VSTORE_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE, __local, RND)           \
   _CLC_VECTOR_VSTORE_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE, __global, RND)
 
-#define _CLC_VECTOR_VSTORE_PRIM1(PRIM_TYPE) \
-  _CLC_VECTOR_VSTORE_PRIM3(,PRIM_TYPE, PRIM_TYPE, )
+#define _CLC_VECTOR_VSTORE_PRIM1(PRIM_TYPE)                                    \
+  _CLC_VECTOR_VSTORE_PRIM3(, PRIM_TYPE, PRIM_TYPE, )
 
-#define _CLC_VECTOR_VSTORE_HALF_PRIM1(PRIM_TYPE, RND) \
-	_CLC_VSTORE_DECL(_half, half, PRIM_TYPE, , __private, RND) \
-	_CLC_VSTORE_DECL(_half, half, PRIM_TYPE, , __local, RND) \
-	_CLC_VSTORE_DECL(_half, half, PRIM_TYPE, , __global, RND) \
-	_CLC_VECTOR_VSTORE_PRIM3(_half, half, PRIM_TYPE, RND) \
-	_CLC_VSTORE_DECL(a_half, half, PRIM_TYPE, , __private, RND) \
-	_CLC_VSTORE_DECL(a_half, half, PRIM_TYPE, , __local, RND) \
-	_CLC_VSTORE_DECL(a_half, half, PRIM_TYPE, , __global, RND) \
-	_CLC_VECTOR_VSTORE_PRIM3(a_half, half, PRIM_TYPE, RND)
+#define _CLC_VECTOR_VSTORE_HALF_PRIM1(PRIM_TYPE, RND)                          \
+  _CLC_VSTORE_DECL(_half, half, PRIM_TYPE, , __private, RND)                   \
+  _CLC_VSTORE_DECL(_half, half, PRIM_TYPE, , __local, RND)                     \
+  _CLC_VSTORE_DECL(_half, half, PRIM_TYPE, , __global, RND)                    \
+  _CLC_VECTOR_VSTORE_PRIM3(_half, half, PRIM_TYPE, RND)                        \
+  _CLC_VSTORE_DECL(a_half, half, PRIM_TYPE, , __private, RND)                  \
+  _CLC_VSTORE_DECL(a_half, half, PRIM_TYPE, , __local, RND)                    \
+  _CLC_VSTORE_DECL(a_half, half, PRIM_TYPE, , __global, RND)                   \
+  _CLC_VECTOR_VSTORE_PRIM3(a_half, half, PRIM_TYPE, RND)
 
 _CLC_VECTOR_VSTORE_PRIM1(char)
 _CLC_VECTOR_VSTORE_PRIM1(uchar)
@@ -44,26 +45,25 @@ _CLC_VECTOR_VSTORE_PRIM1(long)
 _CLC_VECTOR_VSTORE_PRIM1(ulong)
 _CLC_VECTOR_VSTORE_PRIM1(float)
 
-_CLC_VECTOR_VSTORE_HALF_PRIM1(float,)
+_CLC_VECTOR_VSTORE_HALF_PRIM1(float, )
 _CLC_VECTOR_VSTORE_HALF_PRIM1(float, _rtz)
 _CLC_VECTOR_VSTORE_HALF_PRIM1(float, _rtn)
 _CLC_VECTOR_VSTORE_HALF_PRIM1(float, _rtp)
 _CLC_VECTOR_VSTORE_HALF_PRIM1(float, _rte)
 
 #ifdef cl_khr_fp64
-  _CLC_VECTOR_VSTORE_PRIM1(double)
-  _CLC_VECTOR_VSTORE_HALF_PRIM1(double,)
-  _CLC_VECTOR_VSTORE_HALF_PRIM1(double, _rtz)
-  _CLC_VECTOR_VSTORE_HALF_PRIM1(double, _rtn)
-  _CLC_VECTOR_VSTORE_HALF_PRIM1(double, _rtp)
-  _CLC_VECTOR_VSTORE_HALF_PRIM1(double, _rte)
+_CLC_VECTOR_VSTORE_PRIM1(double)
+_CLC_VECTOR_VSTORE_HALF_PRIM1(double, )
+_CLC_VECTOR_VSTORE_HALF_PRIM1(double, _rtz)
+_CLC_VECTOR_VSTORE_HALF_PRIM1(double, _rtn)
+_CLC_VECTOR_VSTORE_HALF_PRIM1(double, _rtp)
+_CLC_VECTOR_VSTORE_HALF_PRIM1(double, _rte)
 #endif
 
 #ifdef cl_khr_fp16
-  _CLC_VECTOR_VSTORE_PRIM1(half)
+_CLC_VECTOR_VSTORE_PRIM1(half)
 #endif
 
-
 #undef _CLC_VSTORE_DECL
 #undef _CLC_VECTOR_VSTORE_DECL
 #undef _CLC_VECTOR_VSTORE_PRIM3
diff --git a/libclc/generic/lib/shared/vload.cl b/libclc/generic/lib/shared/vload.cl
index dcbae4f20929f..05737aaa88b71 100644
--- a/libclc/generic/lib/shared/vload.cl
+++ b/libclc/generic/lib/shared/vload.cl
@@ -8,106 +8,113 @@
 
 #include <clc/clc.h>
 
-#define VLOAD_VECTORIZE(PRIM_TYPE, ADDR_SPACE) \
-  typedef PRIM_TYPE##2 less_aligned_##ADDR_SPACE##PRIM_TYPE##2 __attribute__ ((aligned (sizeof(PRIM_TYPE))));\
-  _CLC_OVERLOAD _CLC_DEF PRIM_TYPE##2 vload2(size_t offset, const ADDR_SPACE PRIM_TYPE *x) { \
-    return *((const ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##2*) (&x[2*offset])); \
-  } \
-\
-  typedef PRIM_TYPE##3 less_aligned_##ADDR_SPACE##PRIM_TYPE##3 __attribute__ ((aligned (sizeof(PRIM_TYPE))));\
-  _CLC_OVERLOAD _CLC_DEF PRIM_TYPE##3 vload3(size_t offset, const ADDR_SPACE PRIM_TYPE *x) { \
-    PRIM_TYPE##2 vec = *((const ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##2*) (&x[3*offset])); \
-    return (PRIM_TYPE##3)(vec.s0, vec.s1, x[offset*3+2]); \
-  } \
-\
-  typedef PRIM_TYPE##4 less_aligned_##ADDR_SPACE##PRIM_TYPE##4 __attribute__ ((aligned (sizeof(PRIM_TYPE))));\
-  _CLC_OVERLOAD _CLC_DEF PRIM_TYPE##4 vload4(size_t offset, const ADDR_SPACE PRIM_TYPE *x) { \
-    return *((const ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##4*) (&x[4*offset])); \
-  } \
-\
-  typedef PRIM_TYPE##8 less_aligned_##ADDR_SPACE##PRIM_TYPE##8 __attribute__ ((aligned (sizeof(PRIM_TYPE))));\
-  _CLC_OVERLOAD _CLC_DEF PRIM_TYPE##8 vload8(size_t offset, const ADDR_SPACE PRIM_TYPE *x) { \
-    return *((const ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##8*) (&x[8*offset])); \
-  } \
-\
-  typedef PRIM_TYPE##16 less_aligned_##ADDR_SPACE##PRIM_TYPE##16 __attribute__ ((aligned (sizeof(PRIM_TYPE))));\
-  _CLC_OVERLOAD _CLC_DEF PRIM_TYPE##16 vload16(size_t offset, const ADDR_SPACE PRIM_TYPE *x) { \
-    return *((const ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##16*) (&x[16*offset])); \
-  } \
+#define VLOAD_VECTORIZE(PRIM_TYPE, ADDR_SPACE)                                 \
+  typedef PRIM_TYPE##2 less_aligned_##ADDR_SPACE##PRIM_TYPE##2                 \
+      __attribute__((aligned(sizeof(PRIM_TYPE))));                             \
+  _CLC_OVERLOAD _CLC_DEF PRIM_TYPE##2 vload2(size_t offset,                    \
+                                             const ADDR_SPACE PRIM_TYPE *x) {  \
+    return *((const ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##2         \
+                  *)(&x[2 * offset]));                                         \
+  }                                                                            \
+                                                                               \
+  typedef PRIM_TYPE##3 less_aligned_##ADDR_SPACE##PRIM_TYPE##3                 \
+      __attribute__((aligned(sizeof(PRIM_TYPE))));                             \
+  _CLC_OVERLOAD _CLC_DEF PRIM_TYPE##3 vload3(size_t offset,                    \
+                                             const ADDR_SPACE PRIM_TYPE *x) {  \
+    PRIM_TYPE##2 vec =                                                         \
+        *((const ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##2            \
+               *)(&x[3 * offset]));                                            \
+    return (PRIM_TYPE##3)(vec.s0, vec.s1, x[offset * 3 + 2]);                  \
+  }                                                                            \
+                                                                               \
+  typedef PRIM_TYPE##4 less_aligned_##ADDR_SPACE##PRIM_TYPE##4                 \
+      __attribute__((aligned(sizeof(PRIM_TYPE))));                             \
+  _CLC_OVERLOAD _CLC_DEF PRIM_TYPE##4 vload4(size_t offset,                    \
+                                             const ADDR_SPACE PRIM_TYPE *x) {  \
+    return *((const ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##4         \
+                  *)(&x[4 * offset]));                                         \
+  }                                                                            \
+                                                                               \
+  typedef PRIM_TYPE##8 less_aligned_##ADDR_SPACE##PRIM_TYPE##8                 \
+      __attribute__((aligned(sizeof(PRIM_TYPE))));                             \
+  _CLC_OVERLOAD _CLC_DEF PRIM_TYPE##8 vload8(size_t offset,                    \
+                                             const ADDR_SPACE PRIM_TYPE *x) {  \
+    return *((const ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##8         \
+                  *)(&x[8 * offset]));                                         \
+  }                                                                            \
+                                                                               \
+  typedef PRIM_TYPE##16 less_aligned_##ADDR_SPACE##PRIM_TYPE##16               \
+      __attribute__((aligned(sizeof(PRIM_TYPE))));                             \
+  _CLC_OVERLOAD _CLC_DEF PRIM_TYPE##16 vload16(                                \
+      size_t offset, const ADDR_SPACE PRIM_TYPE *x) {                          \
+    return *((const ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##16        \
+                  *)(&x[16 * offset]));                                        \
+  }
 
-#define VLOAD_ADDR_SPACES(__CLC_SCALAR_GENTYPE) \
-    VLOAD_VECTORIZE(__CLC_SCALAR_GENTYPE, __private) \
-    VLOAD_VECTORIZE(__CLC_SCALAR_GENTYPE, __local) \
-    VLOAD_VECTORIZE(__CLC_SCALAR_GENTYPE, __constant) \
-    VLOAD_VECTORIZE(__CLC_SCALAR_GENTYPE, __global) \
+#define VLOAD_ADDR_SPACES(__CLC_SCALAR_GENTYPE)                                \
+  VLOAD_VECTORIZE(__CLC_SCALAR_GENTYPE, __private)                             \
+  VLOAD_VECTORIZE(__CLC_SCALAR_GENTYPE, __local)                               \
+  VLOAD_VECTORIZE(__CLC_SCALAR_GENTYPE, __constant)                            \
+  VLOAD_VECTORIZE(__CLC_SCALAR_GENTYPE, __global)
 
-#define VLOAD_TYPES() \
-    VLOAD_ADDR_SPACES(char) \
-    VLOAD_ADDR_SPACES(uchar) \
-    VLOAD_ADDR_SPACES(short) \
-    VLOAD_ADDR_SPACES(ushort) \
-    VLOAD_ADDR_SPACES(int) \
-    VLOAD_ADDR_SPACES(uint) \
-    VLOAD_ADDR_SPACES(long) \
-    VLOAD_ADDR_SPACES(ulong) \
-    VLOAD_ADDR_SPACES(float) \
+#define VLOAD_TYPES()                                                          \
+  VLOAD_ADDR_SPACES(char)                                                      \
+  VLOAD_ADDR_SPACES(uchar)                                                     \
+  VLOAD_ADDR_SPACES(short)                                                     \
+  VLOAD_ADDR_SPACES(ushort)                                                    \
+  VLOAD_ADDR_SPACES(int)                                                       \
+  VLOAD_ADDR_SPACES(uint)                                                      \
+  VLOAD_ADDR_SPACES(long)                                                      \
+  VLOAD_ADDR_SPACES(ulong)                                                     \
+  VLOAD_ADDR_SPACES(float)
 
 VLOAD_TYPES()
 
 #ifdef cl_khr_fp64
 #pragma OPENCL EXTENSION cl_khr_fp64 : enable
-    VLOAD_ADDR_SPACES(double)
+VLOAD_ADDR_SPACES(double)
 #endif
 #ifdef cl_khr_fp16
 #pragma OPENCL EXTENSION cl_khr_fp16 : enable
-    VLOAD_ADDR_SPACES(half)
+VLOAD_ADDR_SPACES(half)
 #endif
 
 /* vload_half are legal even without cl_khr_fp16 */
 /* no vload_half for double */
-#if __clang_major__ < 6
-float __clc_vload_half_float_helper__constant(const __constant half *);
-float __clc_vload_half_float_helper__global(const __global half *);
-float __clc_vload_half_float_helper__local(const __local half *);
-float __clc_vload_half_float_helper__private(const __private half *);
-
-#define VEC_LOAD1(val, AS) val = __clc_vload_half_float_helper##AS (&mem[offset++]);
-#else
 #define VEC_LOAD1(val, AS) val = __builtin_load_halff(&mem[offset++]);
-#endif
-
-#define VEC_LOAD2(val, AS) \
-	VEC_LOAD1(val.lo, AS) \
-	VEC_LOAD1(val.hi, AS)
-#define VEC_LOAD3(val, AS) \
-	VEC_LOAD1(val.s0, AS) \
-	VEC_LOAD1(val.s1, AS) \
-	VEC_LOAD1(val.s2, AS)
-#define VEC_LOAD4(val, AS) \
-	VEC_LOAD2(val.lo, AS) \
-	VEC_LOAD2(val.hi, AS)
-#define VEC_LOAD8(val, AS) \
-	VEC_LOAD4(val.lo, AS) \
-	VEC_LOAD4(val.hi, AS)
-#define VEC_LOAD16(val, AS) \
-	VEC_LOAD8(val.lo, AS) \
-	VEC_LOAD8(val.hi, AS)
+#define VEC_LOAD2(val, AS)                                                     \
+  VEC_LOAD1(val.lo, AS)                                                        \
+  VEC_LOAD1(val.hi, AS)
+#define VEC_LOAD3(val, AS)                                                     \
+  VEC_LOAD1(val.s0, AS)                                                        \
+  VEC_LOAD1(val.s1, AS)                                                        \
+  VEC_LOAD1(val.s2, AS)
+#define VEC_LOAD4(val, AS)                                                     \
+  VEC_LOAD2(val.lo, AS)                                                        \
+  VEC_LOAD2(val.hi, AS)
+#define VEC_LOAD8(val, AS)                                                     \
+  VEC_LOAD4(val.lo, AS)                                                        \
+  VEC_LOAD4(val.hi, AS)
+#define VEC_LOAD16(val, AS)                                                    \
+  VEC_LOAD8(val.lo, AS)                                                        \
+  VEC_LOAD8(val.hi, AS)
 
-#define __FUNC(SUFFIX, VEC_SIZE, OFFSET_SIZE, TYPE, AS) \
-  _CLC_OVERLOAD _CLC_DEF TYPE vload_half##SUFFIX(size_t offset, const AS half *mem) { \
-    offset *= VEC_SIZE; \
-    TYPE __tmp; \
-    VEC_LOAD##VEC_SIZE(__tmp, AS) \
-    return __tmp; \
-  } \
-  _CLC_OVERLOAD _CLC_DEF TYPE vloada_half##SUFFIX(size_t offset, const AS half *mem) { \
-    offset *= OFFSET_SIZE; \
-    TYPE __tmp; \
-    VEC_LOAD##VEC_SIZE(__tmp, AS) \
-    return __tmp; \
+#define __FUNC(SUFFIX, VEC_SIZE, OFFSET_SIZE, TYPE, AS)                        \
+  _CLC_OVERLOAD _CLC_DEF TYPE vload_half##SUFFIX(size_t offset,                \
+                                                 const AS half *mem) {         \
+    offset *= VEC_SIZE;                                                        \
+    TYPE __tmp;                                                                \
+    VEC_LOAD##VEC_SIZE(__tmp, AS) return __tmp;                                \
+  }                                                                            \
+  _CLC_OVERLOAD _CLC_DEF TYPE vloada_half##SUFFIX(size_t offset,               \
+                                                  const AS half *mem) {        \
+    offset *= OFFSET_SIZE;                                                     \
+    TYPE __tmp;                                                                \
+    VEC_LOAD##VEC_SIZE(__tmp, AS) return __tmp;                                \
   }
 
-#define FUNC(SUFFIX, VEC_SIZE, OFFSET_SIZE, TYPE, AS) __FUNC(SUFFIX, VEC_SIZE, OFFSET_SIZE, TYPE, AS)
+#define FUNC(SUFFIX, VEC_SIZE, OFFSET_SIZE, TYPE, AS)                          \
+  __FUNC(SUFFIX, VEC_SIZE, OFFSET_SIZE, TYPE, AS)
 
 #define __CLC_BODY "vload_half.inc"
 #include <clc/math/gentype.inc>
diff --git a/libclc/generic/lib/shared/vload_half.inc b/libclc/generic/lib/shared/vload_half.inc
index ff47969327bab..26716b9960018 100644
--- a/libclc/generic/lib/shared/vload_half.inc
+++ b/libclc/generic/lib/shared/vload_half.inc
@@ -11,21 +11,21 @@
 #ifndef __CLC_SCALAR
 
 #if __CLC_VECSIZE == 3
-#  define __CLC_OFFSET 4
+#define __CLC_OFFSET 4
 #else
-#  define __CLC_OFFSET __CLC_VECSIZE
+#define __CLC_OFFSET __CLC_VECSIZE
 #endif
 
-  FUNC(__CLC_VECSIZE, __CLC_VECSIZE, __CLC_OFFSET, __CLC_GENTYPE, __private);
-  FUNC(__CLC_VECSIZE, __CLC_VECSIZE, __CLC_OFFSET, __CLC_GENTYPE, __local);
-  FUNC(__CLC_VECSIZE, __CLC_VECSIZE, __CLC_OFFSET, __CLC_GENTYPE, __global);
-  FUNC(__CLC_VECSIZE, __CLC_VECSIZE, __CLC_OFFSET, __CLC_GENTYPE, __constant);
+FUNC(__CLC_VECSIZE, __CLC_VECSIZE, __CLC_OFFSET, __CLC_GENTYPE, __private);
+FUNC(__CLC_VECSIZE, __CLC_VECSIZE, __CLC_OFFSET, __CLC_GENTYPE, __local);
+FUNC(__CLC_VECSIZE, __CLC_VECSIZE, __CLC_OFFSET, __CLC_GENTYPE, __global);
+FUNC(__CLC_VECSIZE, __CLC_VECSIZE, __CLC_OFFSET, __CLC_GENTYPE, __constant);
 
 #undef __CLC_OFFSET
 #else
-  FUNC(, 1, 1, __CLC_GENTYPE, __private);
-  FUNC(, 1, 1, __CLC_GENTYPE, __local);
-  FUNC(, 1, 1, __CLC_GENTYPE, __global);
-  FUNC(, 1, 1, __CLC_GENTYPE, __constant);
+FUNC(, 1, 1, __CLC_GENTYPE, __private);
+FUNC(, 1, 1, __CLC_GENTYPE, __local);
+FUNC(, 1, 1, __CLC_GENTYPE, __global);
+FUNC(, 1, 1, __CLC_GENTYPE, __constant);
 #endif
 #endif
diff --git a/libclc/generic/lib/shared/vstore.cl b/libclc/generic/lib/shared/vstore.cl
index 0a105f5cd8c86..0c0513f08a778 100644
--- a/libclc/generic/lib/shared/vstore.cl
+++ b/libclc/generic/lib/shared/vstore.cl
@@ -10,36 +10,50 @@
 
 #pragma OPENCL EXTENSION cl_khr_byte_addressable_store : enable
 
-#define VSTORE_VECTORIZE(PRIM_TYPE, ADDR_SPACE) \
-  typedef PRIM_TYPE##2 less_aligned_##ADDR_SPACE##PRIM_TYPE##2 __attribute__ ((aligned (sizeof(PRIM_TYPE))));\
-  _CLC_OVERLOAD _CLC_DEF void vstore2(PRIM_TYPE##2 vec, size_t offset, ADDR_SPACE PRIM_TYPE *mem) { \
-    *((ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##2*) (&mem[2*offset])) = vec; \
-  } \
-\
-  _CLC_OVERLOAD _CLC_DEF void vstore3(PRIM_TYPE##3 vec, size_t offset, ADDR_SPACE PRIM_TYPE *mem) { \
-    *((ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##2*) (&mem[3*offset])) = (PRIM_TYPE##2)(vec.s0, vec.s1); \
-    mem[3 * offset + 2] = vec.s2;\
-  } \
-\
-  typedef PRIM_TYPE##4 less_aligned_##ADDR_SPACE##PRIM_TYPE##4 __attribute__ ((aligned (sizeof(PRIM_TYPE))));\
-  _CLC_OVERLOAD _CLC_DEF void vstore4(PRIM_TYPE##4 vec, size_t offset, ADDR_SPACE PRIM_TYPE *mem) { \
-    *((ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##4*) (&mem[4*offset])) = vec; \
-  } \
-\
-  typedef PRIM_TYPE##8 less_aligned_##ADDR_SPACE##PRIM_TYPE##8 __attribute__ ((aligned (sizeof(PRIM_TYPE))));\
-  _CLC_OVERLOAD _CLC_DEF void vstore8(PRIM_TYPE##8 vec, size_t offset, ADDR_SPACE PRIM_TYPE *mem) { \
-    *((ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##8*) (&mem[8*offset])) = vec; \
-  } \
-\
-  typedef PRIM_TYPE##16 less_aligned_##ADDR_SPACE##PRIM_TYPE##16 __attribute__ ((aligned (sizeof(PRIM_TYPE))));\
-  _CLC_OVERLOAD _CLC_DEF void vstore16(PRIM_TYPE##16 vec, size_t offset, ADDR_SPACE PRIM_TYPE *mem) { \
-    *((ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##16*) (&mem[16*offset])) = vec; \
-  } \
+#define VSTORE_VECTORIZE(PRIM_TYPE, ADDR_SPACE)                                \
+  typedef PRIM_TYPE##2 less_aligned_##ADDR_SPACE##PRIM_TYPE##2                 \
+      __attribute__((aligned(sizeof(PRIM_TYPE))));                             \
+  _CLC_OVERLOAD _CLC_DEF void vstore2(PRIM_TYPE##2 vec, size_t offset,         \
+                                      ADDR_SPACE PRIM_TYPE *mem) {             \
+    *((ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##2                      \
+           *)(&mem[2 * offset])) = vec;                                        \
+  }                                                                            \
+                                                                               \
+  _CLC_OVERLOAD _CLC_DEF void vstore3(PRIM_TYPE##3 vec, size_t offset,         \
+                                      ADDR_SPACE PRIM_TYPE *mem) {             \
+    *((ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##2                      \
+           *)(&mem[3 * offset])) = (PRIM_TYPE##2)(vec.s0, vec.s1);             \
+    mem[3 * offset + 2] = vec.s2;                                              \
+  }                                                                            \
+                                                                               \
+  typedef PRIM_TYPE##4 less_aligned_##ADDR_SPACE##PRIM_TYPE##4                 \
+      __attribute__((aligned(sizeof(PRIM_TYPE))));                             \
+  _CLC_OVERLOAD _CLC_DEF void vstore4(PRIM_TYPE##4 vec, size_t offset,         \
+                                      ADDR_SPACE PRIM_TYPE *mem) {             \
+    *((ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##4                      \
+           *)(&mem[4 * offset])) = vec;                                        \
+  }                                                                            \
+                                                                               \
+  typedef PRIM_TYPE##8 less_aligned_##ADDR_SPACE##PRIM_TYPE##8                 \
+      __attribute__((aligned(sizeof(PRIM_TYPE))));                             \
+  _CLC_OVERLOAD _CLC_DEF void vstore8(PRIM_TYPE##8 vec, size_t offset,         \
+                                      ADDR_SPACE PRIM_TYPE *mem) {             \
+    *((ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##8                      \
+           *)(&mem[8 * offset])) = vec;                                        \
+  }                                                                            \
+                                                                               \
+  typedef PRIM_TYPE##16 less_aligned_##ADDR_SPACE##PRIM_TYPE##16               \
+      __attribute__((aligned(sizeof(PRIM_TYPE))));                             \
+  _CLC_OVERLOAD _CLC_DEF void vstore16(PRIM_TYPE##16 vec, size_t offset,       \
+                                       ADDR_SPACE PRIM_TYPE *mem) {            \
+    *((ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##16                     \
+           *)(&mem[16 * offset])) = vec;                                       \
+  }
 
-#define VSTORE_ADDR_SPACES(__CLC_SCALAR___CLC_GENTYPE) \
-    VSTORE_VECTORIZE(__CLC_SCALAR___CLC_GENTYPE, __private) \
-    VSTORE_VECTORIZE(__CLC_SCALAR___CLC_GENTYPE, __local) \
-    VSTORE_VECTORIZE(__CLC_SCALAR___CLC_GENTYPE, __global) \
+#define VSTORE_ADDR_SPACES(__CLC_SCALAR___CLC_GENTYPE)                         \
+  VSTORE_VECTORIZE(__CLC_SCALAR___CLC_GENTYPE, __private)                      \
+  VSTORE_VECTORIZE(__CLC_SCALAR___CLC_GENTYPE, __local)                        \
+  VSTORE_VECTORIZE(__CLC_SCALAR___CLC_GENTYPE, __global)
 
 VSTORE_ADDR_SPACES(char)
 VSTORE_ADDR_SPACES(uchar)
@@ -51,208 +65,174 @@ VSTORE_ADDR_SPACES(long)
 VSTORE_ADDR_SPACES(ulong)
 VSTORE_ADDR_SPACES(float)
 
-
 #ifdef cl_khr_fp64
 #pragma OPENCL EXTENSION cl_khr_fp64 : enable
-    VSTORE_ADDR_SPACES(double)
+VSTORE_ADDR_SPACES(double)
 #endif
 
 #ifdef cl_khr_fp16
 #pragma OPENCL EXTENSION cl_khr_fp16 : enable
-    VSTORE_ADDR_SPACES(half)
-#endif
-
-/* vstore_half are legal even without cl_khr_fp16 */
-#if __clang_major__ < 6
-#define DECLARE_HELPER(STYPE, AS, builtin) void __clc_vstore_half_##STYPE##_helper##AS(STYPE, AS half *);
-#else
-#define DECLARE_HELPER(STYPE, AS, __builtin) \
-_CLC_DEF void __clc_vstore_half_##STYPE##_helper##AS(STYPE s, AS half *d) \
-{ \
-	__builtin(s, d); \
-}
+VSTORE_ADDR_SPACES(half)
 #endif
 
-DECLARE_HELPER(float, __private, __builtin_store_halff);
-DECLARE_HELPER(float, __global, __builtin_store_halff);
-DECLARE_HELPER(float, __local, __builtin_store_halff);
-
-#ifdef cl_khr_fp64
-DECLARE_HELPER(double, __private, __builtin_store_half);
-DECLARE_HELPER(double, __global, __builtin_store_half);
-DECLARE_HELPER(double, __local, __builtin_store_half);
-#endif
-
-#define VEC_STORE1(STYPE, AS, val, ROUNDF) __clc_vstore_half_##STYPE##_helper##AS (ROUNDF(val), &mem[offset++]);
-
-#define VEC_STORE2(STYPE, AS, val, ROUNDF) \
-	VEC_STORE1(STYPE, AS, val.lo, ROUNDF) \
-	VEC_STORE1(STYPE, AS, val.hi, ROUNDF)
-#define VEC_STORE3(STYPE, AS, val, ROUNDF) \
-	VEC_STORE1(STYPE, AS, val.s0, ROUNDF) \
-	VEC_STORE1(STYPE, AS, val.s1, ROUNDF) \
-	VEC_STORE1(STYPE, AS, val.s2, ROUNDF)
-#define VEC_STORE4(STYPE, AS, val, ROUNDF) \
-	VEC_STORE2(STYPE, AS, val.lo, ROUNDF) \
-	VEC_STORE2(STYPE, AS, val.hi, ROUNDF)
-#define VEC_STORE8(STYPE, AS, val, ROUNDF) \
-	VEC_STORE4(STYPE, AS, val.lo, ROUNDF) \
-	VEC_STORE4(STYPE, AS, val.hi, ROUNDF)
-#define VEC_STORE16(STYPE, AS, val, ROUNDF) \
-	VEC_STORE8(STYPE, AS, val.lo, ROUNDF) \
-	VEC_STORE8(STYPE, AS, val.hi, ROUNDF)
-
-#define __FUNC(SUFFIX, VEC_SIZE, OFFSET, TYPE, STYPE, AS, ROUNDF) \
-  _CLC_OVERLOAD _CLC_DEF void vstore_half##SUFFIX(TYPE vec, size_t offset, AS half *mem) { \
-    offset *= VEC_SIZE; \
-    VEC_STORE##VEC_SIZE(STYPE, AS, vec, ROUNDF) \
-  } \
-  _CLC_OVERLOAD _CLC_DEF void vstorea_half##SUFFIX(TYPE vec, size_t offset, AS half *mem) { \
-    offset *= OFFSET; \
-    VEC_STORE##VEC_SIZE(STYPE, AS, vec, ROUNDF) \
+#define VEC_STORE1(val, ROUNDF, BUILTIN) BUILTIN(ROUNDF(val), &mem[offset++]);
+
+#define VEC_STORE2(val, ROUNDF, BUILTIN)                                       \
+  VEC_STORE1(val.lo, ROUNDF, BUILTIN)                                          \
+  VEC_STORE1(val.hi, ROUNDF, BUILTIN)
+#define VEC_STORE3(val, ROUNDF, BUILTIN)                                       \
+  VEC_STORE1(val.s0, ROUNDF, BUILTIN)                                          \
+  VEC_STORE1(val.s1, ROUNDF, BUILTIN)                                          \
+  VEC_STORE1(val.s2, ROUNDF, BUILTIN)
+#define VEC_STORE4(val, ROUNDF, BUILTIN)                                       \
+  VEC_STORE2(val.lo, ROUNDF, BUILTIN)                                          \
+  VEC_STORE2(val.hi, ROUNDF, BUILTIN)
+#define VEC_STORE8(val, ROUNDF, BUILTIN)                                       \
+  VEC_STORE4(val.lo, ROUNDF, BUILTIN)                                          \
+  VEC_STORE4(val.hi, ROUNDF, BUILTIN)
+#define VEC_STORE16(val, ROUNDF, BUILTIN)                                      \
+  VEC_STORE8(val.lo, ROUNDF, BUILTIN)                                          \
+  VEC_STORE8(val.hi, ROUNDF, BUILTIN)
+
+#define __FUNC(SUFFIX, VEC_SIZE, OFFSET, TYPE, AS, ROUNDF, BUILTIN)            \
+  _CLC_OVERLOAD _CLC_DEF void vstore_half##SUFFIX(TYPE vec, size_t offset,     \
+                                                  AS half *mem) {              \
+    offset *= VEC_SIZE;                                                        \
+    VEC_STORE##VEC_SIZE(vec, ROUNDF, BUILTIN)                                  \
+  }                                                                            \
+  _CLC_OVERLOAD _CLC_DEF void vstorea_half##SUFFIX(TYPE vec, size_t offset,    \
+                                                   AS half *mem) {             \
+    offset *= OFFSET;                                                          \
+    VEC_STORE##VEC_SIZE(vec, ROUNDF, BUILTIN)                                  \
   }
 
-_CLC_DEF _CLC_OVERLOAD float __clc_noop(float x)
-{
-	return x;
-}
-_CLC_DEF _CLC_OVERLOAD float __clc_rtz(float x)
-{
-	/* Remove lower 13 bits to make sure the number is rounded down */
-	int mask = 0xffffe000;
-	const int exp = (as_uint(x) >> 23 & 0xff) - 127;
-	/* Denormals cannot be flushed, and they use different bit for rounding */
-	if (exp < -14)
-		mask <<= min(-(exp + 14), 10);
-	/* RTZ does not produce Inf for large numbers */
-	if (fabs(x) > 65504.0f && !isinf(x))
-		return copysign(65504.0f, x);
-	/* Handle nan corner case */
-	if (isnan(x))
-		return x;
-	return as_float(as_uint(x) & mask);
+_CLC_DEF _CLC_OVERLOAD float __clc_noop(float x) { return x; }
+_CLC_DEF _CLC_OVERLOAD float __clc_rtz(float x) {
+  /* Remove lower 13 bits to make sure the number is rounded down */
+  int mask = 0xffffe000;
+  const int exp = (as_uint(x) >> 23 & 0xff) - 127;
+  /* Denormals cannot be flushed, and they use different bit for rounding */
+  if (exp < -14)
+    mask <<= min(-(exp + 14), 10);
+  /* RTZ does not produce Inf for large numbers */
+  if (fabs(x) > 65504.0f && !isinf(x))
+    return copysign(65504.0f, x);
+  /* Handle nan corner case */
+  if (isnan(x))
+    return x;
+  return as_float(as_uint(x) & mask);
 }
-_CLC_DEF _CLC_OVERLOAD float __clc_rti(float x)
-{
-	const float inf = copysign(INFINITY, x);
-	/* Set lower 13 bits */
-	int mask = (1 << 13) - 1;
-	const int exp = (as_uint(x) >> 23 & 0xff) - 127;
-	/* Denormals cannot be flushed, and they use different bit for rounding */
-	if (exp < -14)
-		mask = (1 << (13 + min(-(exp + 14), 10))) - 1;
-	/* Handle nan corner case */
-	if (isnan(x))
-		return x;
-	const float next = nextafter(as_float(as_uint(x) | mask), inf);
-	return ((as_uint(x) & mask) == 0) ? x : next;
+_CLC_DEF _CLC_OVERLOAD float __clc_rti(float x) {
+  const float inf = copysign(INFINITY, x);
+  /* Set lower 13 bits */
+  int mask = (1 << 13) - 1;
+  const int exp = (as_uint(x) >> 23 & 0xff) - 127;
+  /* Denormals cannot be flushed, and they use different bit for rounding */
+  if (exp < -14)
+    mask = (1 << (13 + min(-(exp + 14), 10))) - 1;
+  /* Handle nan corner case */
+  if (isnan(x))
+    return x;
+  const float next = nextafter(as_float(as_uint(x) | mask), inf);
+  return ((as_uint(x) & mask) == 0) ? x : next;
 }
-_CLC_DEF _CLC_OVERLOAD float __clc_rtn(float x)
-{
-	return ((as_uint(x) & 0x80000000) == 0) ? __clc_rtz(x) : __clc_rti(x);
+_CLC_DEF _CLC_OVERLOAD float __clc_rtn(float x) {
+  return ((as_uint(x) & 0x80000000) == 0) ? __clc_rtz(x) : __clc_rti(x);
 }
-_CLC_DEF _CLC_OVERLOAD float __clc_rtp(float x)
-{
-	return ((as_uint(x) & 0x80000000) == 0) ? __clc_rti(x) : __clc_rtz(x);
+_CLC_DEF _CLC_OVERLOAD float __clc_rtp(float x) {
+  return ((as_uint(x) & 0x80000000) == 0) ? __clc_rti(x) : __clc_rtz(x);
 }
-_CLC_DEF _CLC_OVERLOAD float __clc_rte(float x)
-{
-	/* Mantisa + implicit bit */
-	const uint mantissa = (as_uint(x) & 0x7fffff) | (1u << 23);
-	const int exp = (as_uint(x) >> 23 & 0xff) - 127;
-	int shift = 13;
-	if (exp < -14) {
-		/* The default assumes lower 13 bits are rounded,
-		 * but it might be more for denormals.
-		 * Shifting beyond last == 0b, and qr == 00b is not necessary */
-		shift += min(-(exp + 14), 15);
-	}
-	int mask = (1 << shift) - 1;
-	const uint grs = mantissa & mask;
-	const uint last = mantissa & (1 << shift);
-	/* IEEE round up rule is: grs > 101b or grs == 100b and last == 1.
-	 * exp > 15 should round to inf. */
-	bool roundup = (grs > (1 << (shift - 1))) ||
-		(grs == (1 << (shift - 1)) && last != 0) || (exp > 15);
-	return roundup ? __clc_rti(x) : __clc_rtz(x);
+_CLC_DEF _CLC_OVERLOAD float __clc_rte(float x) {
+  /* Mantisa + implicit bit */
+  const uint mantissa = (as_uint(x) & 0x7fffff) | (1u << 23);
+  const int exp = (as_uint(x) >> 23 & 0xff) - 127;
+  int shift = 13;
+  if (exp < -14) {
+    /* The default assumes lower 13 bits are rounded,
+     * but it might be more for denormals.
+     * Shifting beyond last == 0b, and qr == 00b is not necessary */
+    shift += min(-(exp + 14), 15);
+  }
+  int mask = (1 << shift) - 1;
+  const uint grs = mantissa & mask;
+  const uint last = mantissa & (1 << shift);
+  /* IEEE round up rule is: grs > 101b or grs == 100b and last == 1.
+   * exp > 15 should round to inf. */
+  bool roundup = (grs > (1 << (shift - 1))) ||
+                 (grs == (1 << (shift - 1)) && last != 0) || (exp > 15);
+  return roundup ? __clc_rti(x) : __clc_rtz(x);
 }
 
 #ifdef cl_khr_fp64
-_CLC_DEF _CLC_OVERLOAD double __clc_noop(double x)
-{
-	return x;
-}
-_CLC_DEF _CLC_OVERLOAD double __clc_rtz(double x)
-{
-	/* Remove lower 42 bits to make sure the number is rounded down */
-	ulong mask = 0xfffffc0000000000UL;
-	const int exp = (as_ulong(x) >> 52 & 0x7ff) - 1023;
-	/* Denormals cannot be flushed, and they use different bit for rounding */
-	if (exp < -14)
-		mask <<= min(-(exp + 14), 10);
-	/* RTZ does not produce Inf for large numbers */
-	if (fabs(x) > 65504.0 && !isinf(x))
-		return copysign(65504.0, x);
-	/* Handle nan corner case */
-	if (isnan(x))
-		return x;
-	return as_double(as_ulong(x) & mask);
+_CLC_DEF _CLC_OVERLOAD double __clc_noop(double x) { return x; }
+_CLC_DEF _CLC_OVERLOAD double __clc_rtz(double x) {
+  /* Remove lower 42 bits to make sure the number is rounded down */
+  ulong mask = 0xfffffc0000000000UL;
+  const int exp = (as_ulong(x) >> 52 & 0x7ff) - 1023;
+  /* Denormals cannot be flushed, and they use different bit for rounding */
+  if (exp < -14)
+    mask <<= min(-(exp + 14), 10);
+  /* RTZ does not produce Inf for large numbers */
+  if (fabs(x) > 65504.0 && !isinf(x))
+    return copysign(65504.0, x);
+  /* Handle nan corner case */
+  if (isnan(x))
+    return x;
+  return as_double(as_ulong(x) & mask);
 }
-_CLC_DEF _CLC_OVERLOAD double __clc_rti(double x)
-{
-	const double inf = copysign((double)INFINITY, x);
-	/* Set lower 42 bits */
-	long mask = (1UL << 42UL) - 1UL;
-	const int exp = (as_ulong(x) >> 52 & 0x7ff) - 1023;
-	/* Denormals cannot be flushed, and they use different bit for rounding */
-	if (exp < -14)
-		mask = (1UL << (42UL + min(-(exp + 14), 10))) - 1;
-	/* Handle nan corner case */
-	if (isnan(x))
-		return x;
-	const double next = nextafter(as_double(as_ulong(x) | mask), inf);
-	return ((as_ulong(x) & mask) == 0) ? x : next;
+_CLC_DEF _CLC_OVERLOAD double __clc_rti(double x) {
+  const double inf = copysign((double)INFINITY, x);
+  /* Set lower 42 bits */
+  long mask = (1UL << 42UL) - 1UL;
+  const int exp = (as_ulong(x) >> 52 & 0x7ff) - 1023;
+  /* Denormals cannot be flushed, and they use different bit for rounding */
+  if (exp < -14)
+    mask = (1UL << (42UL + min(-(exp + 14), 10))) - 1;
+  /* Handle nan corner case */
+  if (isnan(x))
+    return x;
+  const double next = nextafter(as_double(as_ulong(x) | mask), inf);
+  return ((as_ulong(x) & mask) == 0) ? x : next;
 }
-_CLC_DEF _CLC_OVERLOAD double __clc_rtn(double x)
-{
-	return ((as_ulong(x) & 0x8000000000000000UL) == 0) ? __clc_rtz(x) : __clc_rti(x);
+_CLC_DEF _CLC_OVERLOAD double __clc_rtn(double x) {
+  return ((as_ulong(x) & 0x8000000000000000UL) == 0) ? __clc_rtz(x)
+                                                     : __clc_rti(x);
 }
-_CLC_DEF _CLC_OVERLOAD double __clc_rtp(double x)
-{
-	return ((as_ulong(x) & 0x8000000000000000UL) == 0) ? __clc_rti(x) : __clc_rtz(x);
+_CLC_DEF _CLC_OVERLOAD double __clc_rtp(double x) {
+  return ((as_ulong(x) & 0x8000000000000000UL) == 0) ? __clc_rti(x)
+                                                     : __clc_rtz(x);
 }
-_CLC_DEF _CLC_OVERLOAD double __clc_rte(double x)
-{
-	/* Mantisa + implicit bit */
-	const ulong mantissa = (as_ulong(x) & 0xfffffffffffff) | (1UL << 52);
-	const int exp = (as_ulong(x) >> 52 & 0x7ff) - 1023;
-	int shift = 42;
-	if (exp < -14) {
-		/* The default assumes lower 13 bits are rounded,
-		 * but it might be more for denormals.
-		 * Shifting beyond last == 0b, and qr == 00b is not necessary */
-		shift += min(-(exp + 14), 15);
-	}
-	ulong mask = (1UL << shift) - 1UL;
-	const ulong grs = mantissa & mask;
-	const ulong last = mantissa & (1UL << shift);
-	/* IEEE round up rule is: grs > 101b or grs == 100b and last == 1.
-	 * exp > 15 should round to inf. */
-	bool roundup = (grs > (1UL << (shift - 1UL))) ||
-		(grs == (1UL << (shift - 1UL)) && last != 0) || (exp > 15);
-	return roundup ? __clc_rti(x) : __clc_rtz(x);
+_CLC_DEF _CLC_OVERLOAD double __clc_rte(double x) {
+  /* Mantisa + implicit bit */
+  const ulong mantissa = (as_ulong(x) & 0xfffffffffffff) | (1UL << 52);
+  const int exp = (as_ulong(x) >> 52 & 0x7ff) - 1023;
+  int shift = 42;
+  if (exp < -14) {
+    /* The default assumes lower 13 bits are rounded,
+     * but it might be more for denormals.
+     * Shifting beyond last == 0b, and qr == 00b is not necessary */
+    shift += min(-(exp + 14), 15);
+  }
+  ulong mask = (1UL << shift) - 1UL;
+  const ulong grs = mantissa & mask;
+  const ulong last = mantissa & (1UL << shift);
+  /* IEEE round up rule is: grs > 101b or grs == 100b and last == 1.
+   * exp > 15 should round to inf. */
+  bool roundup = (grs > (1UL << (shift - 1UL))) ||
+                 (grs == (1UL << (shift - 1UL)) && last != 0) || (exp > 15);
+  return roundup ? __clc_rti(x) : __clc_rtz(x);
 }
 #endif
 
-#define __XFUNC(SUFFIX, VEC_SIZE, OFFSET, TYPE, STYPE, AS) \
-	__FUNC(SUFFIX, VEC_SIZE, OFFSET, TYPE, STYPE, AS, __clc_noop) \
-	__FUNC(SUFFIX ## _rtz, VEC_SIZE, OFFSET, TYPE, STYPE, AS, __clc_rtz) \
-	__FUNC(SUFFIX ## _rtn, VEC_SIZE, OFFSET, TYPE, STYPE, AS, __clc_rtn) \
-	__FUNC(SUFFIX ## _rtp, VEC_SIZE, OFFSET, TYPE, STYPE, AS, __clc_rtp) \
-	__FUNC(SUFFIX ## _rte, VEC_SIZE, OFFSET, TYPE, STYPE, AS, __clc_rte)
+#define __XFUNC(SUFFIX, VEC_SIZE, OFFSET, TYPE, AS, BUILTIN)                   \
+  __FUNC(SUFFIX, VEC_SIZE, OFFSET, TYPE, AS, __clc_noop, BUILTIN)              \
+  __FUNC(SUFFIX##_rtz, VEC_SIZE, OFFSET, TYPE, AS, __clc_rtz, BUILTIN)         \
+  __FUNC(SUFFIX##_rtn, VEC_SIZE, OFFSET, TYPE, AS, __clc_rtn, BUILTIN)         \
+  __FUNC(SUFFIX##_rtp, VEC_SIZE, OFFSET, TYPE, AS, __clc_rtp, BUILTIN)         \
+  __FUNC(SUFFIX##_rte, VEC_SIZE, OFFSET, TYPE, AS, __clc_rte, BUILTIN)
 
-#define FUNC(SUFFIX, VEC_SIZE, OFFSET, TYPE, STYPE, AS) \
-	__XFUNC(SUFFIX, VEC_SIZE, OFFSET, TYPE, STYPE, AS)
+#define FUNC(SUFFIX, VEC_SIZE, OFFSET, TYPE, AS, BUILTIN)                      \
+  __XFUNC(SUFFIX, VEC_SIZE, OFFSET, TYPE, AS, BUILTIN)
 
 #define __CLC_BODY "vstore_half.inc"
 #include <clc/math/gentype.inc>
diff --git a/libclc/generic/lib/shared/vstore_half.inc b/libclc/generic/lib/shared/vstore_half.inc
index 7c3472804b861..78f137f76e832 100644
--- a/libclc/generic/lib/shared/vstore_half.inc
+++ b/libclc/generic/lib/shared/vstore_half.inc
@@ -8,22 +8,37 @@
 
 // This does not exist for fp16
 #if __CLC_FPSIZE > 16
+
+#if __CLC_FPSIZE == 32
+#define STORE_HALF_BUILTIN __builtin_store_halff
+#elif __CLC_FPSIZE == 64
+#define STORE_HALF_BUILTIN __builtin_store_half
+#else
+#error "Invalid FP size"
+#endif
+
 #ifndef __CLC_SCALAR
 
 #if __CLC_VECSIZE == 3
-#  define __CLC_OFFSET 4
+#define __CLC_OFFSET 4
 #else
-#  define __CLC_OFFSET __CLC_VECSIZE
+#define __CLC_OFFSET __CLC_VECSIZE
 #endif
 
-  FUNC(__CLC_VECSIZE, __CLC_VECSIZE, __CLC_OFFSET, __CLC_GENTYPE, __CLC_SCALAR_GENTYPE, __private);
-  FUNC(__CLC_VECSIZE, __CLC_VECSIZE, __CLC_OFFSET, __CLC_GENTYPE, __CLC_SCALAR_GENTYPE, __local);
-  FUNC(__CLC_VECSIZE, __CLC_VECSIZE, __CLC_OFFSET, __CLC_GENTYPE, __CLC_SCALAR_GENTYPE, __global);
+FUNC(__CLC_VECSIZE, __CLC_VECSIZE, __CLC_OFFSET, __CLC_GENTYPE, __private,
+     STORE_HALF_BUILTIN);
+FUNC(__CLC_VECSIZE, __CLC_VECSIZE, __CLC_OFFSET, __CLC_GENTYPE, __local,
+     STORE_HALF_BUILTIN);
+FUNC(__CLC_VECSIZE, __CLC_VECSIZE, __CLC_OFFSET, __CLC_GENTYPE, __global,
+     STORE_HALF_BUILTIN);
 
 #undef __CLC_OFFSET
 #else
-  FUNC(, 1, 1, __CLC_GENTYPE, __CLC_SCALAR_GENTYPE, __private);
-  FUNC(, 1, 1, __CLC_GENTYPE, __CLC_SCALAR_GENTYPE, __local);
-  FUNC(, 1, 1, __CLC_GENTYPE, __CLC_SCALAR_GENTYPE, __global);
+FUNC(, 1, 1, __CLC_GENTYPE, __private, STORE_HALF_BUILTIN);
+FUNC(, 1, 1, __CLC_GENTYPE, __local, STORE_HALF_BUILTIN);
+FUNC(, 1, 1, __CLC_GENTYPE, __global, STORE_HALF_BUILTIN);
 #endif
+
+#undef STORE_HALF_BUILTIN
+
 #endif
diff --git a/libclc/ptx/lib/SOURCES_3.9 b/libclc/ptx/lib/SOURCES_3.9
deleted file mode 100644
index 69c5e5ce9fbac..0000000000000
--- a/libclc/ptx/lib/SOURCES_3.9
+++ /dev/null
@@ -1,2 +0,0 @@
-shared/vload_half_helpers.ll
-shared/vstore_half_helpers.ll
diff --git a/libclc/ptx/lib/SOURCES_4.0 b/libclc/ptx/lib/SOURCES_4.0
deleted file mode 100644
index 69c5e5ce9fbac..0000000000000
--- a/libclc/ptx/lib/SOURCES_4.0
+++ /dev/null
@@ -1,2 +0,0 @@
-shared/vload_half_helpers.ll
-shared/vstore_half_helpers.ll
diff --git a/libclc/ptx/lib/SOURCES_5.0 b/libclc/ptx/lib/SOURCES_5.0
deleted file mode 100644
index 69c5e5ce9fbac..0000000000000
--- a/libclc/ptx/lib/SOURCES_5.0
+++ /dev/null
@@ -1,2 +0,0 @@
-shared/vload_half_helpers.ll
-shared/vstore_half_helpers.ll
diff --git a/libclc/ptx/lib/shared/vload_half_helpers.ll b/libclc/ptx/lib/shared/vload_half_helpers.ll
deleted file mode 100644
index 5fbae19fde287..0000000000000
--- a/libclc/ptx/lib/shared/vload_half_helpers.ll
+++ /dev/null
@@ -1,31 +0,0 @@
-;;===----------------------------------------------------------------------===;;
-;
-; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-; See https://llvm.org/LICENSE.txt for license information.
-; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-;
-;;===----------------------------------------------------------------------===;;
-
-define float @__clc_vload_half_float_helper__private(half addrspace(0)* nocapture %ptr) nounwind alwaysinline {
-  %data = load half, half addrspace(0)* %ptr
-  %res = fpext half %data to float
-  ret float %res
-}
-
-define float @__clc_vload_half_float_helper__global(half addrspace(1)* nocapture %ptr) nounwind alwaysinline {
-  %data = load half, half addrspace(1)* %ptr
-  %res = fpext half %data to float
-  ret float %res
-}
-
-define float @__clc_vload_half_float_helper__local(half addrspace(3)* nocapture %ptr) nounwind alwaysinline {
-  %data = load half, half addrspace(3)* %ptr
-  %res = fpext half %data to float
-  ret float %res
-}
-
-define float @__clc_vload_half_float_helper__constant(half addrspace(4)* nocapture %ptr) nounwind alwaysinline {
-  %data = load half, half addrspace(4)* %ptr
-  %res = fpext half %data to float
-  ret float %res
-}
diff --git a/libclc/ptx/lib/shared/vstore_half_helpers.ll b/libclc/ptx/lib/shared/vstore_half_helpers.ll
deleted file mode 100644
index 5ec193d6d40a0..0000000000000
--- a/libclc/ptx/lib/shared/vstore_half_helpers.ll
+++ /dev/null
@@ -1,43 +0,0 @@
-;;===----------------------------------------------------------------------===;;
-;
-; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-; See https://llvm.org/LICENSE.txt for license information.
-; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-;
-;;===----------------------------------------------------------------------===;;
-
-define void @__clc_vstore_half_float_helper__private(float %data, half addrspace(0)* nocapture %ptr) nounwind alwaysinline {
-  %res = fptrunc float %data to half
-  store half %res, half addrspace(0)* %ptr
-  ret void
-}
-
-define void @__clc_vstore_half_float_helper__global(float %data, half addrspace(1)* nocapture %ptr) nounwind alwaysinline {
-  %res = fptrunc float %data to half
-  store half %res, half addrspace(1)* %ptr
-  ret void
-}
-
-define void @__clc_vstore_half_float_helper__local(float %data, half addrspace(3)* nocapture %ptr) nounwind alwaysinline {
-  %res = fptrunc float %data to half
-  store half %res, half addrspace(3)* %ptr
-  ret void
-}
-
-define void @__clc_vstore_half_double_helper__private(double %data, half addrspace(0)* nocapture %ptr) nounwind alwaysinline {
-  %res = fptrunc double %data to half
-  store half %res, half addrspace(0)* %ptr
-  ret void
-}
-
-define void @__clc_vstore_half_double_helper__global(double %data, half addrspace(1)* nocapture %ptr) nounwind alwaysinline {
-  %res = fptrunc double %data to half
-  store half %res, half addrspace(1)* %ptr
-  ret void
-}
-
-define void @__clc_vstore_half_double_helper__local(double %data, half addrspace(3)* nocapture %ptr) nounwind alwaysinline {
-  %res = fptrunc double %data to half
-  store half %res, half addrspace(3)* %ptr
-  ret void
-}
diff --git a/libcxx/include/__ranges/to.h b/libcxx/include/__ranges/to.h
index c937b0656de87..3a2bc42969f7b 100644
--- a/libcxx/include/__ranges/to.h
+++ b/libcxx/include/__ranges/to.h
@@ -26,7 +26,9 @@
 #include <__ranges/size.h>
 #include <__ranges/transform_view.h>
 #include <__type_traits/add_pointer.h>
+#include <__type_traits/is_class.h>
 #include <__type_traits/is_const.h>
+#include <__type_traits/is_union.h>
 #include <__type_traits/is_volatile.h>
 #include <__type_traits/type_identity.h>
 #include <__utility/declval.h>
@@ -81,7 +83,7 @@ template <class _Container, input_range _Range, class... _Args>
   static_assert(!is_const_v<_Container>, "The target container cannot be const-qualified, please remove the const");
   static_assert(
       !is_volatile_v<_Container>, "The target container cannot be volatile-qualified, please remove the volatile");
-
+  static_assert(is_class_v<_Container> || is_union_v<_Container>, "The target must be a class type or union type");
   // First see if the non-recursive case applies -- the conversion target is either:
   // - a range with a convertible value type;
   // - a non-range type which might support being created from the input argument(s) (e.g. an `optional`).
@@ -208,7 +210,7 @@ template <class _Container, class... _Args>
   static_assert(!is_const_v<_Container>, "The target container cannot be const-qualified, please remove the const");
   static_assert(
       !is_volatile_v<_Container>, "The target container cannot be volatile-qualified, please remove the volatile");
-
+  static_assert(is_class_v<_Container> || is_union_v<_Container>, "The target must be a class type or union type");
   auto __to_func = []<input_range _Range, class... _Tail>(_Range&& __range, _Tail&&... __tail) static
     requires requires { //
       /**/ ranges::to<_Container>(std::forward<_Range>(__range), std::forward<_Tail>(__tail)...);
diff --git a/libcxx/test/libcxx/ranges/range.utility/range.utility.conv/to.static_assert.verify.cpp b/libcxx/test/libcxx/ranges/range.utility/range.utility.conv/to.static_assert.verify.cpp
index c3ab002558a03..0800ee8cf7bae 100644
--- a/libcxx/test/libcxx/ranges/range.utility/range.utility.conv/to.static_assert.verify.cpp
+++ b/libcxx/test/libcxx/ranges/range.utility/range.utility.conv/to.static_assert.verify.cpp
@@ -14,12 +14,79 @@
 #include <ranges>
 #include <vector>
 
-void test() {
+void test_cv_qualifications() {
   using R = std::vector<int>;
-  R in = {1, 2, 3};
+  R in    = {1, 2, 3};
 
-  (void)std::ranges::to<const R>(in); //expected-error-re@*:* {{static assertion failed{{.*}}The target container cannot be const-qualified, please remove the const}}
-  (void)(in | std::ranges::to<const R>()); //expected-error-re@*:* {{static assertion failed{{.*}}The target container cannot be const-qualified, please remove the const}}
-  (void)std::ranges::to<volatile R>(in); //expected-error-re@*:* {{static assertion failed{{.*}}The target container cannot be volatile-qualified, please remove the volatile}}
-  (void)(in | std::ranges::to<volatile R>()); //expected-error-re@*:* {{static assertion failed{{.*}}The target container cannot be volatile-qualified, please remove the volatile}}
+  //expected-error-re@*:* {{static assertion failed{{.*}}The target container cannot be const-qualified, please remove the const}}
+  (void)std::ranges::to<const R>(in);
+  //expected-error-re@*:* {{static assertion failed{{.*}}The target container cannot be const-qualified, please remove the const}}
+  (void)(in | std::ranges::to<const R>());
+
+  //expected-error-re@*:* {{static assertion failed{{.*}}The target container cannot be volatile-qualified, please remove the volatile}}
+  (void)std::ranges::to<volatile R>(in);
+
+  //expected-error-re@*:* {{static assertion failed{{.*}}The target container cannot be volatile-qualified, please remove the volatile}}
+  (void)(in | std::ranges::to<volatile R>());
+}
+//unexpected_types
+void ff();
+void test_unexpected_types() {
+  struct C {
+    int member;
+    int f();
+  };
+
+  enum color { red, green, blue };
+  using member_func_ptr = decltype(&C::f);
+  using member_ptr      = decltype(&C::member);
+  using func_ptr        = decltype(&ff);
+  using func_t          = decltype(ff);
+
+  struct R {
+    int* begin() const { return nullptr; };
+    int* end() const { return nullptr; };
+
+    operator int() const;
+    operator int*() const;
+    operator func_ptr() const;
+    operator member_func_ptr() const;
+    operator member_ptr() const;
+    operator color() const;
+  };
+  //expected-error-re@*:* {{static assertion failed{{.*}}The target must be a class type}}
+  (void)std::ranges::to<int>(R{});
+  //expected-error-re@*:* {{static assertion failed{{.*}}The target must be a class type}}
+  (void)(R{} | std::ranges::to<int>());
+
+  //expected-error-re@*:* {{static assertion failed{{.*}}The target must be a class type}}
+  (void)std::ranges::to<int*>(R{});
+  //expected-error-re@*:* {{static assertion failed{{.*}}The target must be a class type}}
+  (void)(R{} | std::ranges::to<int*>());
+
+  //expected-error-re@*:* {{static assertion failed{{.*}}The target must be a class type}}
+  (void)std::ranges::to<func_ptr>(R{});
+  //expected-error-re@*:* {{static assertion failed{{.*}}The target must be a class type}}
+  (void)(R{} | std::ranges::to<func_ptr>());
+
+  //expected-error-re@*:* {{static assertion failed{{.*}}The target must be a class type}}
+  (void)std::ranges::to<member_ptr>(R{});
+  //expected-error-re@*:* {{static assertion failed{{.*}}The target must be a class type}}
+  (void)(R{} | std::ranges::to<member_ptr>());
+
+  //expected-error-re@*:* {{static assertion failed{{.*}}The target must be a class type}}
+  (void)std::ranges::to<func_t>(R{});
+  //expected-error-re@*:* {{static assertion failed{{.*}}The target must be a class type}}
+  (void)(R{} | std::ranges::to<func_t>());
+
+  //expected-error-re@*:* {{static assertion failed{{.*}}The target must be a class type}}
+  (void)std::ranges::to<void>(R{});
+  //expected-error-re@*:* {{static assertion failed{{.*}}The target must be a class type}}
+  //expected-error-re@*:* {{static assertion failed{{.*}}ranges::to: unable to convert to the given container type.}}
+  (void)(R{} | std::ranges::to<void>());
+
+  //expected-error-re@*:* {{static assertion failed{{.*}}The target must be a class type}}
+  (void)std::ranges::to<color>(R{});
+  //expected-error-re@*:* {{static assertion failed{{.*}}The target must be a class type}}
+  (void)(R{} | std::ranges::to<color>());
 }
diff --git a/libcxxabi/test/test_demangle.pass.cpp b/libcxxabi/test/test_demangle.pass.cpp
index 53da1bf6765e7..343885da3017a 100644
--- a/libcxxabi/test/test_demangle.pass.cpp
+++ b/libcxxabi/test/test_demangle.pass.cpp
@@ -29659,6 +29659,8 @@ const char* cases[][2] = {
     {"_ZNKO1X1hEv", "X::h() const &&"},
 //    {"_Z1fM1XVKFivEMS_VFivEMS_KOFivE", "f(int (X::*)() const volatile, int (X::*)() volatile, int (X::*)() const &&)"},
 //    {"_Z1fM1XRFivEMS_OFivEMS_KOFivE", "f(int (X::*)() &, int (X::*)() &&, int (X::*)() const &&)"},
+    {"_Z1fM1XKFivOE", "f(int (X::*)() const &&)"},
+    {"_Z1fM1XKFivOEMS_FOKivEMS_VFS3_RS2_E", "f(int (X::*)() const &&, int const&& (X::*)(), int const&& (X::*)(int const&) volatile)"},
     {"_ZN5test12f0ENS_1TILZNS_1xEEEE", "test1::f0(test1::T<test1::x>)"},
     {"_ZN5test12f1ENS_2t1ILZNS_2f0EfEEE", "test1::f1(test1::t1<test1::f0(float)>)"},
     {"_ZN5test22f1ENS_2t1IXadL_ZNS_2f0EfEEEE", "test2::f1(test2::t1<&test2::f0(float)>)"},
diff --git a/lldb/include/lldb/API/SBExecutionContext.h b/lldb/include/lldb/API/SBExecutionContext.h
index e1e08fe3f4aae..20584271ff36c 100644
--- a/lldb/include/lldb/API/SBExecutionContext.h
+++ b/lldb/include/lldb/API/SBExecutionContext.h
@@ -55,6 +55,7 @@ class LLDB_API SBExecutionContext {
   SBFrame GetFrame() const;
 
 protected:
+  friend class SBInstructionList;
   friend class lldb_private::python::SWIGBridge;
   friend class lldb_private::ScriptInterpreter;
 
diff --git a/lldb/include/lldb/API/SBInstructionList.h b/lldb/include/lldb/API/SBInstructionList.h
index 4c26ec9a294e0..4c6bab9c8ccc7 100644
--- a/lldb/include/lldb/API/SBInstructionList.h
+++ b/lldb/include/lldb/API/SBInstructionList.h
@@ -54,6 +54,11 @@ class LLDB_API SBInstructionList {
 
   bool GetDescription(lldb::SBStream &description);
 
+  // Writes assembly instructions to `description` with load addresses using
+  // `exe_ctx`.
+  bool GetDescription(lldb::SBStream &description,
+                      lldb::SBExecutionContext &exe_ctx);
+
   bool DumpEmulationForAllInstructions(const char *triple);
 
 protected:
@@ -62,8 +67,8 @@ class LLDB_API SBInstructionList {
   friend class SBTarget;
 
   void SetDisassembler(const lldb::DisassemblerSP &opaque_sp);
-  bool GetDescription(lldb_private::Stream &description);
-
+  bool GetDescription(lldb_private::Stream &description,
+                      lldb_private::ExecutionContext *exe_ctx = nullptr);
 
 private:
   lldb::DisassemblerSP m_opaque_sp;
diff --git a/lldb/include/lldb/Interpreter/CommandObject.h b/lldb/include/lldb/Interpreter/CommandObject.h
index e6fea9e022c43..8e33edbc4c794 100644
--- a/lldb/include/lldb/Interpreter/CommandObject.h
+++ b/lldb/include/lldb/Interpreter/CommandObject.h
@@ -40,14 +40,13 @@ int AddNamesMatchingPartialString(
     StringList *descriptions = nullptr) {
   int number_added = 0;
 
-  const bool add_all = cmd_str.empty();
-
-  for (auto iter = in_map.begin(), end = in_map.end(); iter != end; iter++) {
-    if (add_all || (iter->first.find(std::string(cmd_str), 0) == 0)) {
+  for (const auto &[name, cmd] : in_map) {
+    llvm::StringRef cmd_name = name;
+    if (cmd_name.starts_with(cmd_str)) {
       ++number_added;
-      matches.AppendString(iter->first.c_str());
+      matches.AppendString(name);
       if (descriptions)
-        descriptions->AppendString(iter->second->GetHelp());
+        descriptions->AppendString(cmd->GetHelp());
     }
   }
 
diff --git a/lldb/include/lldb/Interpreter/OptionValueEnumeration.h b/lldb/include/lldb/Interpreter/OptionValueEnumeration.h
index 7dc6eea4e69de..924fcc10cbb00 100644
--- a/lldb/include/lldb/Interpreter/OptionValueEnumeration.h
+++ b/lldb/include/lldb/Interpreter/OptionValueEnumeration.h
@@ -41,6 +41,8 @@ class OptionValueEnumeration
   void DumpValue(const ExecutionContext *exe_ctx, Stream &strm,
                  uint32_t dump_mask) override;
 
+  llvm::json::Value ToJSON(const ExecutionContext *exe_ctx) override;
+
   Status
   SetValueFromString(llvm::StringRef value,
                      VarSetOperationType op = eVarSetOperationAssign) override;
diff --git a/lldb/include/lldb/Utility/CompletionRequest.h b/lldb/include/lldb/Utility/CompletionRequest.h
index 865d6db576298..4d3d44054982e 100644
--- a/lldb/include/lldb/Utility/CompletionRequest.h
+++ b/lldb/include/lldb/Utility/CompletionRequest.h
@@ -115,6 +115,11 @@ class CompletionRequest {
   CompletionRequest(llvm::StringRef command_line, unsigned raw_cursor_pos,
                     CompletionResult &result);
 
+  /// Sets the maximum number of completions that should be returned.
+  void SetMaxReturnElements(size_t max_return_elements) {
+    m_max_return_elements = max_return_elements;
+  }
+
   /// Returns the raw user input used to create this CompletionRequest cut off
   /// at the cursor position. The cursor will be at the end of the raw line.
   llvm::StringRef GetRawLine() const {
@@ -157,6 +162,23 @@ class CompletionRequest {
 
   size_t GetCursorIndex() const { return m_cursor_index; }
 
+  size_t GetMaxReturnElements() const { return m_max_return_elements; }
+
+  /// Returns true if the maximum number of completions has not been reached
+  /// yet, hence we should keep adding completions.
+  bool ShouldAddCompletions() const {
+    return GetMaxNumberOfCompletionsToAdd() > 0;
+  }
+
+  /// Returns the maximum number of completions that need to be added
+  /// until reaching the maximum
+  size_t GetMaxNumberOfCompletionsToAdd() const {
+    const size_t number_of_results = m_result.GetNumberOfResults();
+    if (number_of_results >= m_max_return_elements)
+      return 0;
+    return m_max_return_elements - number_of_results;
+  }
+
   /// Adds a possible completion string. If the completion was already
   /// suggested before, it will not be added to the list of results. A copy of
   /// the suggested completion is stored, so the given string can be free'd
@@ -231,6 +253,8 @@ class CompletionRequest {
   size_t m_cursor_index;
   /// The cursor position in the argument indexed by m_cursor_index.
   size_t m_cursor_char_position;
+  /// The maximum number of completions that should be returned.
+  size_t m_max_return_elements = std::numeric_limits<size_t>::max();
 
   /// The result this request is supposed to fill out.
   /// We keep this object private to ensure that no backend can in any way
diff --git a/lldb/packages/Python/lldbsuite/test/lldbtest.py b/lldb/packages/Python/lldbsuite/test/lldbtest.py
index db15a1d851677..763e0619fed58 100644
--- a/lldb/packages/Python/lldbsuite/test/lldbtest.py
+++ b/lldb/packages/Python/lldbsuite/test/lldbtest.py
@@ -2257,12 +2257,12 @@ def complete_from_to(self, str_input, patterns):
                 substrs=[p],
             )
 
-    def completions_match(self, command, completions):
+    def completions_match(self, command, completions, max_completions=-1):
         """Checks that the completions for the given command are equal to the
         given list of completions"""
         interp = self.dbg.GetCommandInterpreter()
         match_strings = lldb.SBStringList()
-        interp.HandleCompletion(command, len(command), 0, -1, match_strings)
+        interp.HandleCompletion(command, len(command), 0, max_completions, match_strings)
         # match_strings is a 1-indexed list, so we have to slice...
         self.assertCountEqual(
             completions, list(match_strings)[1:], "List of returned completion is wrong"
diff --git a/lldb/source/API/SBCommandInterpreter.cpp b/lldb/source/API/SBCommandInterpreter.cpp
index de22a9dd96bd8..4ea79d336e08d 100644
--- a/lldb/source/API/SBCommandInterpreter.cpp
+++ b/lldb/source/API/SBCommandInterpreter.cpp
@@ -263,13 +263,26 @@ int SBCommandInterpreter::HandleCompletionWithDescriptions(
   if (!IsValid())
     return 0;
 
+  if (max_return_elements == 0)
+    return 0;
+
   lldb_private::StringList lldb_matches, lldb_descriptions;
   CompletionResult result;
   CompletionRequest request(current_line, cursor - current_line, result);
+  if (max_return_elements > 0)
+    request.SetMaxReturnElements(max_return_elements);
   m_opaque_ptr->HandleCompletion(request);
   result.GetMatches(lldb_matches);
   result.GetDescriptions(lldb_descriptions);
 
+  // limit the matches to the max_return_elements if necessary
+  if (max_return_elements > 0 &&
+      lldb_matches.GetSize() > static_cast<size_t>(max_return_elements)) {
+    lldb_matches.SetSize(max_return_elements);
+    lldb_descriptions.SetSize(max_return_elements);
+  }
+  int number_of_matches = lldb_matches.GetSize();
+
   // Make the result array indexed from 1 again by adding the 'common prefix'
   // of all completions as element 0. This is done to emulate the old API.
   if (request.GetParsedLine().GetArgumentCount() == 0) {
@@ -303,7 +316,7 @@ int SBCommandInterpreter::HandleCompletionWithDescriptions(
   matches.AppendList(temp_matches_list);
   SBStringList temp_descriptions_list(&lldb_descriptions);
   descriptions.AppendList(temp_descriptions_list);
-  return result.GetNumberOfResults();
+  return number_of_matches;
 }
 
 int SBCommandInterpreter::HandleCompletionWithDescriptions(
diff --git a/lldb/source/API/SBInstructionList.cpp b/lldb/source/API/SBInstructionList.cpp
index c18204375dff1..0d958c6ae93ef 100644
--- a/lldb/source/API/SBInstructionList.cpp
+++ b/lldb/source/API/SBInstructionList.cpp
@@ -8,6 +8,7 @@
 
 #include "lldb/API/SBInstructionList.h"
 #include "lldb/API/SBAddress.h"
+#include "lldb/API/SBExecutionContext.h"
 #include "lldb/API/SBFile.h"
 #include "lldb/API/SBInstruction.h"
 #include "lldb/API/SBStream.h"
@@ -15,6 +16,7 @@
 #include "lldb/Core/Module.h"
 #include "lldb/Host/StreamFile.h"
 #include "lldb/Symbol/SymbolContext.h"
+#include "lldb/Target/ExecutionContext.h"
 #include "lldb/Utility/Instrumentation.h"
 #include "lldb/Utility/Stream.h"
 
@@ -138,7 +140,15 @@ bool SBInstructionList::GetDescription(lldb::SBStream &stream) {
   return GetDescription(stream.ref());
 }
 
-bool SBInstructionList::GetDescription(Stream &sref) {
+bool SBInstructionList::GetDescription(lldb::SBStream &stream,
+                                       lldb::SBExecutionContext &exe_ctx) {
+  LLDB_INSTRUMENT_VA(this, stream);
+  ExecutionContext exe_ctx_wrapper(exe_ctx.get());
+  return GetDescription(stream.ref(), &exe_ctx_wrapper);
+}
+
+bool SBInstructionList::GetDescription(
+    Stream &sref, lldb_private::ExecutionContext *exe_ctx) {
 
   if (m_opaque_sp) {
     size_t num_instructions = GetSize();
@@ -148,7 +158,7 @@ bool SBInstructionList::GetDescription(Stream &sref) {
       const uint32_t max_opcode_byte_size =
           m_opaque_sp->GetInstructionList().GetMaxOpcocdeByteSize();
       FormatEntity::Entry format;
-      FormatEntity::Parse("${addr}: ", format);
+      FormatEntity::Parse("${addr-file-or-load}: ", format);
       SymbolContext sc;
       SymbolContext prev_sc;
 
@@ -172,7 +182,7 @@ bool SBInstructionList::GetDescription(Stream &sref) {
         if (next_addr && *next_addr != addr)
           sref.EOL();
         inst->Dump(&sref, max_opcode_byte_size, true, false,
-                   /*show_control_flow_kind=*/false, nullptr, &sc, &prev_sc,
+                   /*show_control_flow_kind=*/false, exe_ctx, &sc, &prev_sc,
                    &format, 0);
         sref.EOL();
         next_addr = addr;
diff --git a/lldb/source/Commands/CommandCompletions.cpp b/lldb/source/Commands/CommandCompletions.cpp
index 216aaf9abce6c..38231a8e993c7 100644
--- a/lldb/source/Commands/CommandCompletions.cpp
+++ b/lldb/source/Commands/CommandCompletions.cpp
@@ -91,7 +91,7 @@ bool CommandCompletions::InvokeCommonCompletionCallbacks(
        nullptr} // This one has to be last in the list.
   };
 
-  for (int i = 0;; i++) {
+  for (int i = 0; request.ShouldAddCompletions(); i++) {
     if (common_completions[i].type == lldb::eTerminatorCompletion)
       break;
     else if ((common_completions[i].type & completion_mask) ==
@@ -167,7 +167,9 @@ class SourceFileCompleter : public Completer {
         m_matching_files.AppendIfUnique(context.comp_unit->GetPrimaryFile());
       }
     }
-    return Searcher::eCallbackReturnContinue;
+    return m_matching_files.GetSize() >= m_request.GetMaxNumberOfCompletionsToAdd()
+               ? Searcher::eCallbackReturnStop
+               : Searcher::eCallbackReturnContinue;
   }
 
   void DoCompletion(SearchFilter *filter) override {
@@ -230,6 +232,9 @@ class SymbolCompleter : public Completer {
 
       // Now add the functions & symbols to the list - only add if unique:
       for (const SymbolContext &sc : sc_list) {
+        if (m_match_set.size() >= m_request.GetMaxNumberOfCompletionsToAdd())
+          break;
+
         ConstString func_name = sc.GetFunctionName(Mangled::ePreferDemangled);
         // Ensure that the function name matches the regex. This is more than
         // a sanity check. It is possible that the demangled function name
@@ -239,7 +244,9 @@ class SymbolCompleter : public Completer {
           m_match_set.insert(func_name);
       }
     }
-    return Searcher::eCallbackReturnContinue;
+    return m_match_set.size() >= m_request.GetMaxNumberOfCompletionsToAdd()
+               ? Searcher::eCallbackReturnStop
+               : Searcher::eCallbackReturnContinue;
   }
 
   void DoCompletion(SearchFilter *filter) override {
@@ -305,7 +312,8 @@ class ModuleCompleter : public Completer {
           m_request.AddCompletion(cur_file_name);
       }
     }
-    return Searcher::eCallbackReturnContinue;
+    return m_request.ShouldAddCompletions() ? Searcher::eCallbackReturnContinue
+                                            : Searcher::eCallbackReturnStop;
   }
 
   void DoCompletion(SearchFilter *filter) override { filter->Search(*this); }
@@ -429,7 +437,8 @@ static void DiskFilesOrDirectories(const llvm::Twine &partial_name,
   std::error_code EC;
   llvm::vfs::directory_iterator Iter = fs.DirBegin(SearchDir, EC);
   llvm::vfs::directory_iterator End;
-  for (; Iter != End && !EC; Iter.increment(EC)) {
+  for (; Iter != End && !EC && request.ShouldAddCompletions();
+       Iter.increment(EC)) {
     auto &Entry = *Iter;
     llvm::ErrorOr<llvm::vfs::Status> Status = fs.GetStatus(Entry.path());
 
diff --git a/lldb/source/Commands/CommandObjectProcess.cpp b/lldb/source/Commands/CommandObjectProcess.cpp
index 654dfa83ea444..ed80c854ed66e 100644
--- a/lldb/source/Commands/CommandObjectProcess.cpp
+++ b/lldb/source/Commands/CommandObjectProcess.cpp
@@ -468,7 +468,13 @@ class CommandObjectProcessContinue : public CommandObjectParsed {
       case 'b':
         m_run_to_bkpt_args.AppendArgument(option_arg);
         m_any_bkpts_specified = true;
-      break;
+        break;
+      case 'F':
+        m_base_direction = lldb::RunDirection::eRunForward;
+        break;
+      case 'R':
+        m_base_direction = lldb::RunDirection::eRunReverse;
+        break;
       default:
         llvm_unreachable("Unimplemented option");
       }
@@ -479,6 +485,7 @@ class CommandObjectProcessContinue : public CommandObjectParsed {
       m_ignore = 0;
       m_run_to_bkpt_args.Clear();
       m_any_bkpts_specified = false;
+      m_base_direction = std::nullopt;
     }
 
     llvm::ArrayRef<OptionDefinition> GetDefinitions() override {
@@ -488,6 +495,7 @@ class CommandObjectProcessContinue : public CommandObjectParsed {
     uint32_t m_ignore = 0;
     Args m_run_to_bkpt_args;
     bool m_any_bkpts_specified = false;
+    std::optional<lldb::RunDirection> m_base_direction;
   };
 
   void DoExecute(Args &command, CommandReturnObject &result) override {
@@ -654,6 +662,9 @@ class CommandObjectProcessContinue : public CommandObjectParsed {
         }
       }
 
+      if (m_options.m_base_direction.has_value())
+        process->SetBaseDirection(*m_options.m_base_direction);
+
       const uint32_t iohandler_id = process->GetIOHandlerID();
 
       StreamString stream;
diff --git a/lldb/source/Commands/Options.td b/lldb/source/Commands/Options.td
index cc579d767eb06..53864ff29327d 100644
--- a/lldb/source/Commands/Options.td
+++ b/lldb/source/Commands/Options.td
@@ -737,13 +737,17 @@ let Command = "process attach" in {
 }
 
 let Command = "process continue" in {
-  def process_continue_ignore_count : Option<"ignore-count", "i">, Group<1>,
+  def process_continue_ignore_count : Option<"ignore-count", "i">, Groups<[1,2]>,
     Arg<"UnsignedInteger">, Desc<"Ignore <N> crossings of the breakpoint (if it"
     " exists) for the currently selected thread.">;
-  def process_continue_run_to_bkpt : Option<"continue-to-bkpt", "b">, Group<2>,
+  def process_continue_run_to_bkpt : Option<"continue-to-bkpt", "b">, Groups<[3,4]>,
     Arg<"BreakpointIDRange">, Desc<"Specify a breakpoint to continue to, temporarily "
     "ignoring other breakpoints.  Can be specified more than once.  "
     "The continue action will be done synchronously if this option is specified.">;
+  def thread_continue_forward : Option<"forward", "F">, Groups<[1,3]>,
+    Desc<"Set the direction to forward before continuing.">;
+  def thread_continue_reverse : Option<"reverse", "R">, Groups<[2,4]>,
+    Desc<"Set the direction to reverse before continuing.">;
 }
 
 let Command = "process detach" in {
diff --git a/lldb/source/Core/Debugger.cpp b/lldb/source/Core/Debugger.cpp
index b572210f25603..cd8726eeba632 100644
--- a/lldb/source/Core/Debugger.cpp
+++ b/lldb/source/Core/Debugger.cpp
@@ -257,7 +257,9 @@ Status Debugger::SetPropertyValue(const ExecutionContext *exe_ctx,
       else
         m_statusline.reset();
     } else if (property_path ==
-               g_debugger_properties[ePropertyStatuslineFormat].name) {
+                   g_debugger_properties[ePropertyStatuslineFormat].name ||
+               property_path ==
+                   g_debugger_properties[ePropertySeparator].name) {
       // Statusline format changed. Redraw the statusline.
       RedrawStatusline();
     } else if (property_path ==
diff --git a/lldb/source/Interpreter/OptionValueEnumeration.cpp b/lldb/source/Interpreter/OptionValueEnumeration.cpp
index 8088695243545..dd231f43e0d96 100644
--- a/lldb/source/Interpreter/OptionValueEnumeration.cpp
+++ b/lldb/source/Interpreter/OptionValueEnumeration.cpp
@@ -37,6 +37,16 @@ void OptionValueEnumeration::DumpValue(const ExecutionContext *exe_ctx,
   }
 }
 
+llvm::json::Value
+OptionValueEnumeration::ToJSON(const ExecutionContext *exe_ctx) {
+  for (const auto &enums : m_enumerations) {
+    if (enums.value.value == m_current_value)
+      return enums.cstring.GetStringRef();
+  }
+
+  return std::to_string(static_cast<uint64_t>(m_current_value));
+}
+
 Status OptionValueEnumeration::SetValueFromString(llvm::StringRef value,
                                                   VarSetOperationType op) {
   Status error;
@@ -105,6 +115,6 @@ void OptionValueEnumeration::AutoComplete(CommandInterpreter &interpreter,
     }
     return;
   }
-    for (size_t i = 0; i < num_enumerators; ++i)
-      request.AddCompletion(m_enumerations.GetCStringAtIndex(i).GetStringRef());
+  for (size_t i = 0; i < num_enumerators; ++i)
+    request.AddCompletion(m_enumerations.GetCStringAtIndex(i).GetStringRef());
 }
diff --git a/lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp b/lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
index 5b1353454a1c6..3eb5c3b2101b5 100644
--- a/lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
+++ b/lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
@@ -330,7 +330,7 @@ bool ClangModulesDeclVendorImpl::AddModule(const SourceModule &module,
     }
   }
   if (!HS.lookupModule(module.path.front().GetStringRef())) {
-    error_stream.Printf("error: Header search couldn't locate module %s\n",
+    error_stream.Printf("error: Header search couldn't locate module '%s'\n",
                         module.path.front().AsCString());
     return false;
   }
diff --git a/lldb/source/Plugins/Language/CPlusPlus/LibCxxInitializerList.cpp b/lldb/source/Plugins/Language/CPlusPlus/LibCxxInitializerList.cpp
index ffc894256626c..f0675da1eac9f 100644
--- a/lldb/source/Plugins/Language/CPlusPlus/LibCxxInitializerList.cpp
+++ b/lldb/source/Plugins/Language/CPlusPlus/LibCxxInitializerList.cpp
@@ -90,7 +90,8 @@ lldb_private::formatters::LibcxxInitializerListSyntheticFrontEnd::Update() {
 
   llvm::Expected<uint64_t> size_or_err = m_element_type.GetByteSize(nullptr);
   if (!size_or_err)
-    LLDB_LOG_ERRORV(GetLog(LLDBLog::Types), size_or_err.takeError(), "{0}");
+    LLDB_LOG_ERRORV(GetLog(LLDBLog::DataFormatters), size_or_err.takeError(),
+                    "{0}");
   else {
     m_element_size = *size_or_err;
     // Store raw pointers or end up with a circular dependency.
diff --git a/lldb/source/Plugins/Language/CPlusPlus/LibCxxSpan.cpp b/lldb/source/Plugins/Language/CPlusPlus/LibCxxSpan.cpp
index acda41024cf03..cfb42e283f828 100644
--- a/lldb/source/Plugins/Language/CPlusPlus/LibCxxSpan.cpp
+++ b/lldb/source/Plugins/Language/CPlusPlus/LibCxxSpan.cpp
@@ -104,7 +104,8 @@ lldb_private::formatters::LibcxxStdSpanSyntheticFrontEnd::Update() {
   // Get element size.
   llvm::Expected<uint64_t> size_or_err = m_element_type.GetByteSize(nullptr);
   if (!size_or_err)
-    LLDB_LOG_ERRORV(GetLog(LLDBLog::Types), size_or_err.takeError(), "{0}");
+    LLDB_LOG_ERRORV(GetLog(LLDBLog::DataFormatters), size_or_err.takeError(),
+                    "{0}");
   else {
     m_element_size = *size_or_err;
 
diff --git a/lldb/source/Plugins/Language/CPlusPlus/LibCxxVariant.cpp b/lldb/source/Plugins/Language/CPlusPlus/LibCxxVariant.cpp
index 701946d44cb40..82b34584e35a6 100644
--- a/lldb/source/Plugins/Language/CPlusPlus/LibCxxVariant.cpp
+++ b/lldb/source/Plugins/Language/CPlusPlus/LibCxxVariant.cpp
@@ -99,8 +99,8 @@ LibcxxVariantGetIndexValidity(ValueObjectSP &impl_sp) {
 
   llvm::Expected<uint64_t> index_type_bytes = index_type.GetByteSize(nullptr);
   if (!index_type_bytes) {
-    LLDB_LOG_ERRORV(GetLog(LLDBLog::Types), index_type_bytes.takeError(),
-                    "{0}");
+    LLDB_LOG_ERRORV(GetLog(LLDBLog::DataFormatters),
+                    index_type_bytes.takeError(), "{0}");
     if (!index_type_bytes)
       return LibcxxVariantIndexValidity::Invalid;
   }
diff --git a/lldb/source/Plugins/Language/CPlusPlus/LibCxxVector.cpp b/lldb/source/Plugins/Language/CPlusPlus/LibCxxVector.cpp
index ce2261b6f03c3..900d8d4dce0b5 100644
--- a/lldb/source/Plugins/Language/CPlusPlus/LibCxxVector.cpp
+++ b/lldb/source/Plugins/Language/CPlusPlus/LibCxxVector.cpp
@@ -150,7 +150,8 @@ lldb_private::formatters::LibcxxStdVectorSyntheticFrontEnd::Update() {
   m_element_type = data_sp->GetCompilerType().GetPointeeType();
   llvm::Expected<uint64_t> size_or_err = m_element_type.GetByteSize(nullptr);
   if (!size_or_err)
-    LLDB_LOG_ERRORV(GetLog(LLDBLog::Types), size_or_err.takeError(), "{0}");
+    LLDB_LOG_ERRORV(GetLog(LLDBLog::DataFormatters), size_or_err.takeError(),
+                    "{0}");
   else {
     m_element_size = *size_or_err;
 
diff --git a/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp b/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
index 2338367302387..f458357d948da 100644
--- a/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
+++ b/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
@@ -1112,7 +1112,7 @@ class CommandObjectMultiwordObjC_TaggedPointer : public CommandObjectMultiword {
       : CommandObjectMultiword(
             interpreter, "tagged-pointer",
             "Commands for operating on Objective-C tagged pointers.",
-            "class-table <subcommand> [<subcommand-options>]") {
+            "tagged-pointer <subcommand> [<subcommand-options>]") {
     LoadSubCommand(
         "info",
         CommandObjectSP(
diff --git a/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTypeEncodingParser.cpp b/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTypeEncodingParser.cpp
index ddaa7a8a597b4..f29a876ba2f24 100644
--- a/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTypeEncodingParser.cpp
+++ b/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTypeEncodingParser.cpp
@@ -19,6 +19,7 @@
 
 #include "clang/Basic/TargetInfo.h"
 
+#include <optional>
 #include <vector>
 
 using namespace lldb_private;
@@ -41,13 +42,17 @@ std::string AppleObjCTypeEncodingParser::ReadStructName(StringLexer &type) {
   return std::string(buffer.GetString());
 }
 
-std::string AppleObjCTypeEncodingParser::ReadQuotedString(StringLexer &type) {
+std::optional<std::string>
+AppleObjCTypeEncodingParser::ReadQuotedString(StringLexer &type) {
+  if (!type.HasAtLeast(1))
+    return std::nullopt;
+
   StreamString buffer;
-  while (type.HasAtLeast(1) && type.Peek() != '"')
+  while (type.Peek() != '"') {
     buffer.Printf("%c", type.Next());
-  StringLexer::Character next = type.Next();
-  UNUSED_IF_ASSERT_DISABLED(next);
-  assert(next == '"');
+    if (!type.HasAtLeast(1))
+      return std::nullopt;
+  }
   return std::string(buffer.GetString());
 }
 
@@ -70,10 +75,12 @@ AppleObjCTypeEncodingParser::ReadStructElement(TypeSystemClang &ast_ctx,
                                                StringLexer &type,
                                                bool for_expression) {
   StructElement retval;
-  if (type.NextIf('"'))
-    retval.name = ReadQuotedString(type);
-  if (!type.NextIf('"'))
-    return retval;
+  if (type.NextIf('"')) {
+    if (auto maybe_name = ReadQuotedString(type))
+      retval.name = *maybe_name;
+    else
+      return retval;
+  }
   uint32_t bitfield_size = 0;
   retval.type = BuildType(ast_ctx, type, for_expression, &bitfield_size);
   retval.bitfield = bitfield_size;
@@ -198,7 +205,10 @@ clang::QualType AppleObjCTypeEncodingParser::BuildObjCObjectPointerType(
     // quoted string is a class name. - If we see anything else, the quoted
     // string is a field name and we push it back onto type.
 
-    name = ReadQuotedString(type);
+    if (auto maybe_name = ReadQuotedString(type))
+      name = *maybe_name;
+    else
+      return clang::QualType();
 
     if (type.HasAtLeast(1)) {
       switch (type.Peek()) {
diff --git a/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTypeEncodingParser.h b/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTypeEncodingParser.h
index 57ed9c21fabad..3058514f38ba1 100644
--- a/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTypeEncodingParser.h
+++ b/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTypeEncodingParser.h
@@ -63,7 +63,7 @@ class AppleObjCTypeEncodingParser : public ObjCLanguageRuntime::EncodingToType {
 
   uint32_t ReadNumber(StringLexer &type);
 
-  std::string ReadQuotedString(StringLexer &type);
+  std::optional<std::string> ReadQuotedString(StringLexer &type);
 
   ObjCLanguageRuntime &m_runtime;
 };
diff --git a/lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp b/lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
index f31b56b9f81e6..9d5e0f886a4a5 100644
--- a/lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
+++ b/lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
@@ -12,6 +12,7 @@
 #include "Plugins/Process/Utility/RegisterContextDarwin_arm.h"
 #include "Plugins/Process/Utility/RegisterContextDarwin_arm64.h"
 #include "Plugins/Process/Utility/RegisterContextDarwin_i386.h"
+#include "Plugins/Process/Utility/RegisterContextDarwin_riscv32.h"
 #include "Plugins/Process/Utility/RegisterContextDarwin_x86_64.h"
 #include "lldb/Core/Debugger.h"
 #include "lldb/Core/Module.h"
@@ -769,6 +770,147 @@ class RegisterContextDarwin_arm64_Mach : public RegisterContextDarwin_arm64 {
   }
 };
 
+class RegisterContextDarwin_riscv32_Mach
+    : public RegisterContextDarwin_riscv32 {
+public:
+  RegisterContextDarwin_riscv32_Mach(lldb_private::Thread &thread,
+                                     const DataExtractor &data)
+      : RegisterContextDarwin_riscv32(thread, 0) {
+    SetRegisterDataFrom_LC_THREAD(data);
+  }
+
+  void InvalidateAllRegisters() override {
+    // Do nothing... registers are always valid...
+  }
+
+  void SetRegisterDataFrom_LC_THREAD(const DataExtractor &data) {
+    lldb::offset_t offset = 0;
+    SetError(GPRRegSet, Read, -1);
+    SetError(FPURegSet, Read, -1);
+    SetError(EXCRegSet, Read, -1);
+    SetError(CSRRegSet, Read, -1);
+    bool done = false;
+    while (!done) {
+      int flavor = data.GetU32(&offset);
+      uint32_t count = data.GetU32(&offset);
+      lldb::offset_t next_thread_state = offset + (count * 4);
+      switch (flavor) {
+      case GPRRegSet:
+        // x0-x31 + pc
+        if (count >= 32) {
+          for (uint32_t i = 0; i < 32; ++i)
+            ((uint32_t *)&gpr.x0)[i] = data.GetU32(&offset);
+          gpr.pc = data.GetU32(&offset);
+          SetError(GPRRegSet, Read, 0);
+        }
+        offset = next_thread_state;
+        break;
+      case FPURegSet: {
+        // f0-f31 + fcsr
+        if (count >= 32) {
+          for (uint32_t i = 0; i < 32; ++i)
+            ((uint32_t *)&fpr.f0)[i] = data.GetU32(&offset);
+          fpr.fcsr = data.GetU32(&offset);
+          SetError(FPURegSet, Read, 0);
+        }
+      }
+        offset = next_thread_state;
+        break;
+      case EXCRegSet:
+        if (count == 3) {
+          exc.exception = data.GetU32(&offset);
+          exc.fsr = data.GetU32(&offset);
+          exc.far = data.GetU32(&offset);
+          SetError(EXCRegSet, Read, 0);
+        }
+        offset = next_thread_state;
+        break;
+      default:
+        done = true;
+        break;
+      }
+    }
+  }
+
+  static bool Create_LC_THREAD(Thread *thread, Stream &data) {
+    RegisterContextSP reg_ctx_sp(thread->GetRegisterContext());
+    if (reg_ctx_sp) {
+      RegisterContext *reg_ctx = reg_ctx_sp.get();
+
+      data.PutHex32(GPRRegSet); // Flavor
+      data.PutHex32(GPRWordCount);
+      PrintRegisterValue(reg_ctx, "x0", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x1", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x2", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x3", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x4", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x5", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x6", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x7", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x8", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x9", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x10", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x11", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x12", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x13", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x14", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x15", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x16", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x17", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x18", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x19", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x20", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x21", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x22", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x23", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x24", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x25", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x26", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x27", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x28", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x29", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x30", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "x31", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "pc", nullptr, 4, data);
+      data.PutHex32(0); // uint32_t pad at the end
+
+      // Write out the EXC registers
+      data.PutHex32(EXCRegSet);
+      data.PutHex32(EXCWordCount);
+      PrintRegisterValue(reg_ctx, "exception", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "fsr", nullptr, 4, data);
+      PrintRegisterValue(reg_ctx, "far", nullptr, 4, data);
+      return true;
+    }
+    return false;
+  }
+
+protected:
+  int DoReadGPR(lldb::tid_t tid, int flavor, GPR &gpr) override { return -1; }
+
+  int DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpu) override { return -1; }
+
+  int DoReadEXC(lldb::tid_t tid, int flavor, EXC &exc) override { return -1; }
+
+  int DoReadCSR(lldb::tid_t tid, int flavor, CSR &csr) override { return -1; }
+
+  int DoWriteGPR(lldb::tid_t tid, int flavor, const GPR &gpr) override {
+    return 0;
+  }
+
+  int DoWriteFPU(lldb::tid_t tid, int flavor, const FPU &fpu) override {
+    return 0;
+  }
+
+  int DoWriteEXC(lldb::tid_t tid, int flavor, const EXC &exc) override {
+    return 0;
+  }
+
+  int DoWriteCSR(lldb::tid_t tid, int flavor, const CSR &csr) override {
+    return 0;
+  }
+};
+
 static uint32_t MachHeaderSizeFromMagic(uint32_t magic) {
   switch (magic) {
   case MH_MAGIC:
@@ -5827,6 +5969,11 @@ ObjectFileMachO::GetThreadContextAtIndex(uint32_t idx,
         reg_ctx_sp =
             std::make_shared<RegisterContextDarwin_x86_64_Mach>(thread, data);
         break;
+
+      case llvm::MachO::CPU_TYPE_RISCV:
+        reg_ctx_sp =
+            std::make_shared<RegisterContextDarwin_riscv32_Mach>(thread, data);
+        break;
       }
     }
   }
@@ -6695,6 +6842,11 @@ bool ObjectFileMachO::SaveCore(const lldb::ProcessSP &process_sp,
               RegisterContextDarwin_x86_64_Mach::Create_LC_THREAD(
                   thread_sp.get(), LC_THREAD_datas[thread_idx]);
               break;
+
+            case llvm::MachO::CPU_TYPE_RISCV:
+              RegisterContextDarwin_riscv32_Mach::Create_LC_THREAD(
+                  thread_sp.get(), LC_THREAD_datas[thread_idx]);
+              break;
             }
           }
         }
diff --git a/lldb/source/Plugins/Process/Utility/CMakeLists.txt b/lldb/source/Plugins/Process/Utility/CMakeLists.txt
index f269f5d7d4d74..d29605fddd5cb 100644
--- a/lldb/source/Plugins/Process/Utility/CMakeLists.txt
+++ b/lldb/source/Plugins/Process/Utility/CMakeLists.txt
@@ -20,6 +20,7 @@ add_lldb_library(lldbPluginProcessUtility
   RegisterContextDarwin_arm.cpp
   RegisterContextDarwin_arm64.cpp
   RegisterContextDarwin_i386.cpp
+  RegisterContextDarwin_riscv32.cpp
   RegisterContextDarwin_x86_64.cpp
   RegisterContextDummy.cpp
   RegisterContextFreeBSD_i386.cpp
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_riscv32.cpp b/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_riscv32.cpp
new file mode 100644
index 0000000000000..14f5bc3ea8c49
--- /dev/null
+++ b/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_riscv32.cpp
@@ -0,0 +1,1313 @@
+//===-- RegisterContextDarwin_riscv32.cpp
+//------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "lldb/Utility/DataBufferHeap.h"
+#include "lldb/Utility/DataExtractor.h"
+#include "lldb/Utility/Endian.h"
+#include "lldb/Utility/Log.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/Utility/Scalar.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/Support/Compiler.h"
+
+#include <cstddef>
+
+#include <memory>
+
+#include "RegisterContextDarwin_riscv32.h"
+#include "Utility/RISCV_DWARF_Registers.h"
+
+using namespace lldb;
+using namespace lldb_private;
+
+enum {
+  gpr_x0 = 0,
+  gpr_x1,
+  gpr_x2,
+  gpr_x3,
+  gpr_x4,
+  gpr_x5,
+  gpr_x6,
+  gpr_x7,
+  gpr_x8,
+  gpr_x9,
+  gpr_x10,
+  gpr_x11,
+  gpr_x12,
+  gpr_x13,
+  gpr_x14,
+  gpr_x15,
+  gpr_x16,
+  gpr_x17,
+  gpr_x18,
+  gpr_x19,
+  gpr_x20,
+  gpr_x21,
+  gpr_x22,
+  gpr_x23,
+  gpr_x24,
+  gpr_x25,
+  gpr_x26,
+  gpr_x27,
+  gpr_x28,
+  gpr_x29,
+  gpr_x30,
+  gpr_x31,
+  gpr_pc,
+
+  fpr_f0,
+  fpr_f1,
+  fpr_f2,
+  fpr_f3,
+  fpr_f4,
+  fpr_f5,
+  fpr_f6,
+  fpr_f7,
+  fpr_f8,
+  fpr_f9,
+  fpr_f10,
+  fpr_f11,
+  fpr_f12,
+  fpr_f13,
+  fpr_f14,
+  fpr_f15,
+  fpr_f16,
+  fpr_f17,
+  fpr_f18,
+  fpr_f19,
+  fpr_f20,
+  fpr_f21,
+  fpr_f22,
+  fpr_f23,
+  fpr_f24,
+  fpr_f25,
+  fpr_f26,
+  fpr_f27,
+  fpr_f28,
+  fpr_f29,
+  fpr_f30,
+  fpr_f31,
+  fpr_fcsr,
+
+  exc_exception,
+  exc_fsr,
+  exc_far,
+
+  csr_bank,
+
+  k_num_registers
+};
+
+/* clang-format off */
+#define GPR_OFFSET(reg)                                                        \
+  (LLVM_EXTENSION offsetof(RegisterContextDarwin_riscv32::GPR, reg))
+#define FPU_OFFSET(reg)                                                        \
+  (LLVM_EXTENSION offsetof(RegisterContextDarwin_riscv32::FPU, reg) +          \
+   sizeof(RegisterContextDarwin_riscv32::GPR))
+#define EXC_OFFSET(reg)                                                        \
+  (LLVM_EXTENSION offsetof(RegisterContextDarwin_riscv32::EXC, reg) +          \
+   sizeof(RegisterContextDarwin_riscv32::GPR) +                                \
+   sizeof(RegisterContextDarwin_riscv32::FPU))
+
+// These macros will auto define the register name, alt name, register size,
+// register offset, encoding, format and native register. This ensures that the
+// register state structures are defined correctly and have the correct sizes
+// and offsets.
+#define DEFINE_GPR_ABI(reg, canon)                                             \
+      #reg, #canon,                                                            \
+      sizeof(((RegisterContextDarwin_riscv32::GPR *)nullptr)->canon),          \
+      GPR_OFFSET(canon), eEncodingUint, eFormatHex
+#define DEFINE_GPR(reg)                                                        \
+      #reg, nullptr,                                                           \
+      sizeof(((RegisterContextDarwin_riscv32::GPR *)nullptr)->reg),            \
+      GPR_OFFSET(reg), eEncodingUint, eFormatHex
+#define DEFINE_FPU_ABI(reg, canon)                                             \
+      #reg, #canon,                                                            \
+      sizeof(((RegisterContextDarwin_riscv32::FPU *)nullptr)->canon),          \
+      FPU_OFFSET(canon), eEncodingUint, eFormatHex
+#define DEFINE_FPU(reg)                                                        \
+      #reg, nullptr,                                                           \
+      sizeof(((RegisterContextDarwin_riscv32::FPU *)nullptr)->reg),            \
+      FPU_OFFSET(reg), eEncodingUint, eFormatHex
+#define DEFINE_EXC(reg)                                                        \
+      #reg, nullptr,                                                           \
+      sizeof(((RegisterContextDarwin_riscv32::EXC *)nullptr)->reg),            \
+      EXC_OFFSET(reg), eEncodingUint, eFormatHex
+#define REG_CONTEXT_SIZE                                                       \
+  (sizeof(RegisterContextDarwin_riscv32::GPR) +                                \
+   sizeof(RegisterContextDarwin_riscv32::FPU) +                                \
+   sizeof(RegisterContextDarwin_riscv32::EXC) +                                \
+   sizeof(RegisterContextDarwin_riscv32::CSR))
+/* clang-format on */
+
+static RegisterInfo g_register_infos[] = {
+    {
+        DEFINE_GPR_ABI(zero, x0),
+        {riscv_dwarf::dwarf_gpr_x0, riscv_dwarf::dwarf_gpr_x0,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x0},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(ra, x1),
+        {riscv_dwarf::dwarf_gpr_x1, riscv_dwarf::dwarf_gpr_x1,
+         LLDB_REGNUM_GENERIC_RA, LLDB_INVALID_REGNUM, gpr_x1},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(sp, x2),
+        {riscv_dwarf::dwarf_gpr_x2, riscv_dwarf::dwarf_gpr_x2,
+         LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM, gpr_x2},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(gp, x3),
+        {riscv_dwarf::dwarf_gpr_x3, riscv_dwarf::dwarf_gpr_x3,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x3},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(tp, x4),
+        {riscv_dwarf::dwarf_gpr_x4, riscv_dwarf::dwarf_gpr_x4,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x4},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(t0, x5),
+        {riscv_dwarf::dwarf_gpr_x5, riscv_dwarf::dwarf_gpr_x5,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x5},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(t1, x6),
+        {riscv_dwarf::dwarf_gpr_x6, riscv_dwarf::dwarf_gpr_x6,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x6},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(t2, x7),
+        {riscv_dwarf::dwarf_gpr_x7, riscv_dwarf::dwarf_gpr_x7,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x7},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(fp, x8),
+        {riscv_dwarf::dwarf_gpr_x8, riscv_dwarf::dwarf_gpr_x8,
+         LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM, gpr_x8},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(s1, x9),
+        {riscv_dwarf::dwarf_gpr_x9, riscv_dwarf::dwarf_gpr_x9,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x9},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(a0, x10),
+        {riscv_dwarf::dwarf_gpr_x10, riscv_dwarf::dwarf_gpr_x10,
+         LLDB_REGNUM_GENERIC_ARG1, LLDB_INVALID_REGNUM, gpr_x10},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(a1, x11),
+        {riscv_dwarf::dwarf_gpr_x11, riscv_dwarf::dwarf_gpr_x11,
+         LLDB_REGNUM_GENERIC_ARG2, LLDB_INVALID_REGNUM, gpr_x11},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(a2, x12),
+        {riscv_dwarf::dwarf_gpr_x12, riscv_dwarf::dwarf_gpr_x12,
+         LLDB_REGNUM_GENERIC_ARG3, LLDB_INVALID_REGNUM, gpr_x12},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(a3, x13),
+        {riscv_dwarf::dwarf_gpr_x13, riscv_dwarf::dwarf_gpr_x13,
+         LLDB_REGNUM_GENERIC_ARG4, LLDB_INVALID_REGNUM, gpr_x13},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(a4, x14),
+        {riscv_dwarf::dwarf_gpr_x14, riscv_dwarf::dwarf_gpr_x14,
+         LLDB_REGNUM_GENERIC_ARG5, LLDB_INVALID_REGNUM, gpr_x14},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(a5, x15),
+        {riscv_dwarf::dwarf_gpr_x15, riscv_dwarf::dwarf_gpr_x15,
+         LLDB_REGNUM_GENERIC_ARG6, LLDB_INVALID_REGNUM, gpr_x15},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(a6, x16),
+        {riscv_dwarf::dwarf_gpr_x16, riscv_dwarf::dwarf_gpr_x16,
+         LLDB_REGNUM_GENERIC_ARG7, LLDB_INVALID_REGNUM, gpr_x16},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(a7, x17),
+        {riscv_dwarf::dwarf_gpr_x17, riscv_dwarf::dwarf_gpr_x17,
+         LLDB_REGNUM_GENERIC_ARG8, LLDB_INVALID_REGNUM, gpr_x17},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(s2, x18),
+        {riscv_dwarf::dwarf_gpr_x18, riscv_dwarf::dwarf_gpr_x18,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x18},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(s3, x19),
+        {riscv_dwarf::dwarf_gpr_x19, riscv_dwarf::dwarf_gpr_x19,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x19},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(s4, x20),
+        {riscv_dwarf::dwarf_gpr_x20, riscv_dwarf::dwarf_gpr_x20,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x20},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(s5, x21),
+        {riscv_dwarf::dwarf_gpr_x21, riscv_dwarf::dwarf_gpr_x21,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x21},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(s6, x22),
+        {riscv_dwarf::dwarf_gpr_x22, riscv_dwarf::dwarf_gpr_x22,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x22},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(s7, x23),
+        {riscv_dwarf::dwarf_gpr_x23, riscv_dwarf::dwarf_gpr_x23,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x23},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(s8, x24),
+        {riscv_dwarf::dwarf_gpr_x24, riscv_dwarf::dwarf_gpr_x24,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x24},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(s9, x25),
+        {riscv_dwarf::dwarf_gpr_x25, riscv_dwarf::dwarf_gpr_x25,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x25},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(s10, x26),
+        {riscv_dwarf::dwarf_gpr_x26, riscv_dwarf::dwarf_gpr_x26,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x26},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(s11, x27),
+        {riscv_dwarf::dwarf_gpr_x27, riscv_dwarf::dwarf_gpr_x27,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x27},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(t3, x28),
+        {riscv_dwarf::dwarf_gpr_x28, riscv_dwarf::dwarf_gpr_x28,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x28},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(t4, x29),
+        {riscv_dwarf::dwarf_gpr_x29, riscv_dwarf::dwarf_gpr_x29,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x29},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(t5, x30),
+        {riscv_dwarf::dwarf_gpr_x30, riscv_dwarf::dwarf_gpr_x30,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x30},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR_ABI(t6, x31),
+        {riscv_dwarf::dwarf_gpr_x31, riscv_dwarf::dwarf_gpr_x31,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_x31},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_GPR(pc),
+        {riscv_dwarf::dwarf_gpr_pc, riscv_dwarf::dwarf_gpr_pc,
+         LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM, gpr_pc},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+
+    {
+        DEFINE_FPU_ABI(ft0, f0),
+        {riscv_dwarf::dwarf_fpr_f0, riscv_dwarf::dwarf_fpr_f0,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f0},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(ft1, f1),
+        {riscv_dwarf::dwarf_fpr_f1, riscv_dwarf::dwarf_fpr_f1,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f1},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(ft2, f2),
+        {riscv_dwarf::dwarf_fpr_f2, riscv_dwarf::dwarf_fpr_f2,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f2},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(ft3, f3),
+        {riscv_dwarf::dwarf_fpr_f3, riscv_dwarf::dwarf_fpr_f3,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f3},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(ft4, f4),
+        {riscv_dwarf::dwarf_fpr_f4, riscv_dwarf::dwarf_fpr_f4,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f4},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(ft5, f5),
+        {riscv_dwarf::dwarf_fpr_f5, riscv_dwarf::dwarf_fpr_f5,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f5},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(ft6, f6),
+        {riscv_dwarf::dwarf_fpr_f6, riscv_dwarf::dwarf_fpr_f6,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f6},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(ft7, f7),
+        {riscv_dwarf::dwarf_fpr_f7, riscv_dwarf::dwarf_fpr_f7,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f7},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(fs0, f8),
+        {riscv_dwarf::dwarf_fpr_f8, riscv_dwarf::dwarf_fpr_f8,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f8},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(fs1, f9),
+        {riscv_dwarf::dwarf_fpr_f9, riscv_dwarf::dwarf_fpr_f9,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f9},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(fa0, f10),
+        {riscv_dwarf::dwarf_fpr_f10, riscv_dwarf::dwarf_fpr_f10,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f10},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(fa1, f11),
+        {riscv_dwarf::dwarf_fpr_f11, riscv_dwarf::dwarf_fpr_f11,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f11},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(fa2, f12),
+        {riscv_dwarf::dwarf_fpr_f12, riscv_dwarf::dwarf_fpr_f12,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f12},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(fa3, f13),
+        {riscv_dwarf::dwarf_fpr_f13, riscv_dwarf::dwarf_fpr_f13,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f13},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(fa4, f14),
+        {riscv_dwarf::dwarf_fpr_f14, riscv_dwarf::dwarf_fpr_f14,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f14},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(fa5, f15),
+        {riscv_dwarf::dwarf_fpr_f15, riscv_dwarf::dwarf_fpr_f15,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f15},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(fa6, f16),
+        {riscv_dwarf::dwarf_fpr_f16, riscv_dwarf::dwarf_fpr_f16,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f16},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(fa7, f17),
+        {riscv_dwarf::dwarf_fpr_f17, riscv_dwarf::dwarf_fpr_f17,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f17},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(fs2, f18),
+        {riscv_dwarf::dwarf_fpr_f18, riscv_dwarf::dwarf_fpr_f18,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f18},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(fs3, f19),
+        {riscv_dwarf::dwarf_fpr_f19, riscv_dwarf::dwarf_fpr_f19,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f19},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(fs4, f20),
+        {riscv_dwarf::dwarf_fpr_f20, riscv_dwarf::dwarf_fpr_f20,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f20},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(fs5, f21),
+        {riscv_dwarf::dwarf_fpr_f21, riscv_dwarf::dwarf_fpr_f21,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f21},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(fs6, f22),
+        {riscv_dwarf::dwarf_fpr_f22, riscv_dwarf::dwarf_fpr_f22,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f22},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(fs7, f23),
+        {riscv_dwarf::dwarf_fpr_f23, riscv_dwarf::dwarf_fpr_f23,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f23},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(fs8, f24),
+        {riscv_dwarf::dwarf_fpr_f24, riscv_dwarf::dwarf_fpr_f24,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f24},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(fs9, f25),
+        {riscv_dwarf::dwarf_fpr_f25, riscv_dwarf::dwarf_fpr_f25,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f25},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(fs10, f26),
+        {riscv_dwarf::dwarf_fpr_f26, riscv_dwarf::dwarf_fpr_f26,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f26},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(fs11, f27),
+        {riscv_dwarf::dwarf_fpr_f27, riscv_dwarf::dwarf_fpr_f27,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f27},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(ft8, f28),
+        {riscv_dwarf::dwarf_fpr_f28, riscv_dwarf::dwarf_fpr_f28,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f28},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(ft9, f29),
+        {riscv_dwarf::dwarf_fpr_f29, riscv_dwarf::dwarf_fpr_f29,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f29},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(ft10, f30),
+        {riscv_dwarf::dwarf_fpr_f30, riscv_dwarf::dwarf_fpr_f30,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f30},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU_ABI(ft11, f31),
+        {riscv_dwarf::dwarf_fpr_f31, riscv_dwarf::dwarf_fpr_f31,
+         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, fpr_f31},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_FPU(fcsr),
+        {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+         LLDB_INVALID_REGNUM, fpr_fcsr},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+
+    {
+        DEFINE_EXC(exception),
+        {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+         LLDB_INVALID_REGNUM, exc_exception},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_EXC(fsr),
+        {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+         LLDB_INVALID_REGNUM, exc_fsr},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {
+        DEFINE_EXC(far),
+        {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+         LLDB_INVALID_REGNUM, exc_far},
+        nullptr,
+        nullptr,
+        nullptr,
+    },
+    {"csr",
+     nullptr,
+     1024 * sizeof(uint32_t),
+     0,
+     eEncodingVector,
+     eFormatVectorOfUInt32,
+     {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+      LLDB_INVALID_REGNUM, csr_bank},
+     nullptr,
+     nullptr,
+     nullptr}};
+
+static size_t k_num_register_infos = std::size(g_register_infos);
+
+RegisterContextDarwin_riscv32::RegisterContextDarwin_riscv32(
+    Thread &thread, uint32_t concrete_frame_idx)
+    : RegisterContext(thread, concrete_frame_idx), gpr(), fpr(), exc() {
+  uint32_t i;
+  for (i = 0; i < kNumErrors; i++) {
+    gpr_errs[i] = -1;
+    fpr_errs[i] = -1;
+    exc_errs[i] = -1;
+    csr_errs[i] = -1;
+  }
+}
+
+RegisterContextDarwin_riscv32::~RegisterContextDarwin_riscv32() = default;
+
+void RegisterContextDarwin_riscv32::InvalidateAllRegisters() {
+  InvalidateAllRegisterStates();
+}
+
+size_t RegisterContextDarwin_riscv32::GetRegisterCount() {
+  assert(k_num_register_infos == k_num_registers);
+  return k_num_registers;
+}
+
+const RegisterInfo *
+RegisterContextDarwin_riscv32::GetRegisterInfoAtIndex(size_t reg) {
+  assert(k_num_register_infos == k_num_registers);
+  if (reg < k_num_registers)
+    return &g_register_infos[reg];
+  return nullptr;
+}
+
+size_t RegisterContextDarwin_riscv32::GetRegisterInfosCount() {
+  return k_num_register_infos;
+}
+
+const RegisterInfo *RegisterContextDarwin_riscv32::GetRegisterInfos() {
+  return g_register_infos;
+}
+
+// General purpose registers
+static uint32_t g_gpr_regnums[] = {
+    gpr_x0,  gpr_x1,  gpr_x2,  gpr_x3,  gpr_x4,  gpr_x5,  gpr_x6,
+    gpr_x7,  gpr_x8,  gpr_x9,  gpr_x10, gpr_x11, gpr_x12, gpr_x13,
+    gpr_x14, gpr_x15, gpr_x16, gpr_x17, gpr_x18, gpr_x19, gpr_x20,
+    gpr_x21, gpr_x22, gpr_x23, gpr_x24, gpr_x25, gpr_x26, gpr_x27,
+    gpr_x28, gpr_x29, gpr_x30, gpr_x31, gpr_pc};
+
+// Floating point registers
+static uint32_t g_fpr_regnums[] = {
+    fpr_f0,  fpr_f1,  fpr_f2,  fpr_f3,  fpr_f4,  fpr_f5,  fpr_f6,
+    fpr_f7,  fpr_f8,  fpr_f9,  fpr_f10, fpr_f11, fpr_f12, fpr_f13,
+    fpr_f14, fpr_f15, fpr_f16, fpr_f17, fpr_f18, fpr_f19, fpr_f20,
+    fpr_f21, fpr_f22, fpr_f23, fpr_f24, fpr_f25, fpr_f26, fpr_f27,
+    fpr_f28, fpr_f29, fpr_f30, fpr_f31, fpr_fcsr};
+
+// Exception registers
+
+static uint32_t g_exc_regnums[] = {exc_exception, exc_fsr, exc_far};
+
+// CSR bank registers
+static uint32_t g_csr_regnums[] = {csr_bank};
+
+// Number of registers in each register set
+const size_t k_num_gpr_registers = std::size(g_gpr_regnums);
+const size_t k_num_fpr_registers = std::size(g_fpr_regnums);
+const size_t k_num_exc_registers = std::size(g_exc_regnums);
+const size_t k_num_csr_registers = std::size(g_csr_regnums);
+
+// Register set definitions. The first definitions at register set index of
+// zero is for all registers, followed by other registers sets. The register
+// information for the all register set need not be filled in.
+static const RegisterSet g_reg_sets[] = {
+    {
+        "General Purpose Registers",
+        "gpr",
+        k_num_gpr_registers,
+        g_gpr_regnums,
+    },
+    {"Floating Point Registers", "fpr", k_num_fpr_registers, g_fpr_regnums},
+    {"Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums},
+    {"CSR register bank", "csr", k_num_csr_registers, g_csr_regnums}};
+
+const size_t k_num_regsets = std::size(g_reg_sets);
+
+size_t RegisterContextDarwin_riscv32::GetRegisterSetCount() {
+  return k_num_regsets;
+}
+
+const RegisterSet *
+RegisterContextDarwin_riscv32::GetRegisterSet(size_t reg_set) {
+  if (reg_set < k_num_regsets)
+    return &g_reg_sets[reg_set];
+  return nullptr;
+}
+
+// Register information definitions for 32 bit riscv32.
+int RegisterContextDarwin_riscv32::GetSetForNativeRegNum(int reg_num) {
+  if (reg_num < fpr_f0)
+    return GPRRegSet;
+  else if (reg_num < exc_exception)
+    return FPURegSet;
+  else if (reg_num < csr_bank)
+    return EXCRegSet;
+  else if (reg_num < k_num_registers)
+    return CSRRegSet;
+  return -1;
+}
+
+void RegisterContextDarwin_riscv32::LogGPR(Log *log, const char *title) {
+  if (log) {
+    if (title)
+      LLDB_LOGF(log, "%s", title);
+    for (uint32_t i = 0; i < k_num_gpr_registers; i++) {
+      uint32_t reg = gpr_x0 + i;
+      LLDB_LOGF(log, "%12s = 0x%4.4x", g_register_infos[reg].name,
+                (&gpr.x0)[reg]);
+    }
+  }
+}
+
+int RegisterContextDarwin_riscv32::ReadGPR(bool force) {
+  int set = GPRRegSet;
+  if (force || !RegisterSetIsCached(set)) {
+    SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr));
+  }
+  return GetError(set, Read);
+}
+
+int RegisterContextDarwin_riscv32::ReadFPU(bool force) {
+  int set = FPURegSet;
+  if (force || !RegisterSetIsCached(set)) {
+    SetError(set, Read, DoReadFPU(GetThreadID(), set, fpr));
+  }
+  return GetError(set, Read);
+}
+
+int RegisterContextDarwin_riscv32::ReadEXC(bool force) {
+  int set = EXCRegSet;
+  if (force || !RegisterSetIsCached(set)) {
+    SetError(set, Read, DoReadEXC(GetThreadID(), set, exc));
+  }
+  return GetError(set, Read);
+}
+
+int RegisterContextDarwin_riscv32::ReadCSR(bool force) {
+  int set = CSRRegSet;
+  if (force || !RegisterSetIsCached(set)) {
+    SetError(set, Read, DoReadCSR(GetThreadID(), set, csr));
+  }
+  return GetError(set, Read);
+}
+
+int RegisterContextDarwin_riscv32::WriteGPR() {
+  int set = GPRRegSet;
+  if (!RegisterSetIsCached(set)) {
+    SetError(set, Write, -1);
+    return -1;
+  }
+  SetError(set, Write, DoWriteGPR(GetThreadID(), set, gpr));
+  SetError(set, Read, -1);
+  return GetError(set, Write);
+}
+
+int RegisterContextDarwin_riscv32::WriteFPU() {
+  int set = FPURegSet;
+  if (!RegisterSetIsCached(set)) {
+    SetError(set, Write, -1);
+    return -1;
+  }
+  SetError(set, Write, DoWriteFPU(GetThreadID(), set, fpr));
+  SetError(set, Read, -1);
+  return GetError(set, Write);
+}
+
+int RegisterContextDarwin_riscv32::WriteEXC() {
+  int set = EXCRegSet;
+  if (!RegisterSetIsCached(set)) {
+    SetError(set, Write, -1);
+    return -1;
+  }
+  SetError(set, Write, DoWriteEXC(GetThreadID(), set, exc));
+  SetError(set, Read, -1);
+  return GetError(set, Write);
+}
+
+int RegisterContextDarwin_riscv32::WriteCSR() {
+  int set = CSRRegSet;
+  if (!RegisterSetIsCached(set)) {
+    SetError(set, Write, -1);
+    return -1;
+  }
+  SetError(set, Write, DoWriteCSR(GetThreadID(), set, csr));
+  SetError(set, Read, -1);
+  return GetError(set, Write);
+}
+
+int RegisterContextDarwin_riscv32::ReadRegisterSet(uint32_t set, bool force) {
+  switch (set) {
+  case GPRRegSet:
+    return ReadGPR(force);
+  case FPURegSet:
+    return ReadFPU(force);
+  case EXCRegSet:
+    return ReadEXC(force);
+  case CSRRegSet:
+    return ReadCSR(force);
+  default:
+    break;
+  }
+  return -1;
+}
+
+int RegisterContextDarwin_riscv32::WriteRegisterSet(uint32_t set) {
+  // Make sure we have a valid context to set.
+  if (RegisterSetIsCached(set)) {
+    switch (set) {
+    case GPRRegSet:
+      return WriteGPR();
+    case FPURegSet:
+      return WriteFPU();
+    case EXCRegSet:
+      return WriteEXC();
+    case CSRRegSet:
+      return WriteCSR();
+    default:
+      break;
+    }
+  }
+  return -1;
+}
+
+bool RegisterContextDarwin_riscv32::ReadRegister(const RegisterInfo *reg_info,
+                                                 RegisterValue &value) {
+  const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
+  int set = RegisterContextDarwin_riscv32::GetSetForNativeRegNum(reg);
+
+  if (set == -1)
+    return false;
+
+  if (ReadRegisterSet(set, false) != 0)
+    return false;
+
+  switch (reg) {
+  case gpr_x0:
+  case gpr_x1:
+  case gpr_x2:
+  case gpr_x3:
+  case gpr_x4:
+  case gpr_x5:
+  case gpr_x6:
+  case gpr_x7:
+  case gpr_x8:
+  case gpr_x9:
+  case gpr_x10:
+  case gpr_x11:
+  case gpr_x12:
+  case gpr_x13:
+  case gpr_x14:
+  case gpr_x15:
+  case gpr_x16:
+  case gpr_x17:
+  case gpr_x18:
+  case gpr_x19:
+  case gpr_x20:
+  case gpr_x21:
+  case gpr_x22:
+  case gpr_x23:
+  case gpr_x24:
+  case gpr_x25:
+  case gpr_x26:
+  case gpr_x27:
+  case gpr_x28:
+  case gpr_x29:
+  case gpr_x30:
+  case gpr_x31:
+  case gpr_pc:
+    value = (&gpr.x0)[reg - gpr_x0];
+    break;
+
+  case fpr_f0:
+  case fpr_f1:
+  case fpr_f2:
+  case fpr_f3:
+  case fpr_f4:
+  case fpr_f5:
+  case fpr_f6:
+  case fpr_f7:
+  case fpr_f8:
+  case fpr_f9:
+  case fpr_f10:
+  case fpr_f11:
+  case fpr_f12:
+  case fpr_f13:
+  case fpr_f14:
+  case fpr_f15:
+  case fpr_f16:
+  case fpr_f17:
+  case fpr_f18:
+  case fpr_f19:
+  case fpr_f20:
+  case fpr_f21:
+  case fpr_f22:
+  case fpr_f23:
+  case fpr_f24:
+  case fpr_f25:
+  case fpr_f26:
+  case fpr_f27:
+  case fpr_f28:
+  case fpr_f29:
+  case fpr_f30:
+  case fpr_f31:
+  case fpr_fcsr:
+    value = (&fpr.f0)[reg - fpr_f0];
+    break;
+
+  case exc_exception:
+    value = exc.exception;
+    break;
+
+  case exc_fsr:
+    value = exc.fsr;
+    break;
+
+  case exc_far:
+    value = exc.far;
+    break;
+
+  case csr_bank:
+    // These values don't fit into scalar types,
+    // RegisterContext::ReadRegisterBytes() must be used for these registers
+    //::memcpy (reg_value.value.vector.uint8, fpu.stmm[reg - fpu_stmm0].bytes,
+    // 10);
+
+    // AArch64 copies NEON registers with
+    // value.SetBytes(csr.bytes, reg_info->byte_size,
+    //                endian::InlHostByteOrder());
+    return false;
+
+  default:
+    return false;
+  }
+  return true;
+}
+
+bool RegisterContextDarwin_riscv32::WriteRegister(const RegisterInfo *reg_info,
+                                                  const RegisterValue &value) {
+  const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
+  int set = GetSetForNativeRegNum(reg);
+
+  if (set == -1)
+    return false;
+
+  if (ReadRegisterSet(set, false) != 0)
+    return false;
+
+  switch (reg) {
+  case gpr_x0:
+  case gpr_x1:
+  case gpr_x2:
+  case gpr_x3:
+  case gpr_x4:
+  case gpr_x5:
+  case gpr_x6:
+  case gpr_x7:
+  case gpr_x8:
+  case gpr_x9:
+  case gpr_x10:
+  case gpr_x11:
+  case gpr_x12:
+  case gpr_x13:
+  case gpr_x14:
+  case gpr_x15:
+  case gpr_x16:
+  case gpr_x17:
+  case gpr_x18:
+  case gpr_x19:
+  case gpr_x20:
+  case gpr_x21:
+  case gpr_x22:
+  case gpr_x23:
+  case gpr_x24:
+  case gpr_x25:
+  case gpr_x26:
+  case gpr_x27:
+  case gpr_x28:
+  case gpr_x29:
+  case gpr_x30:
+  case gpr_x31:
+  case gpr_pc:
+    (&gpr.x0)[reg - gpr_x0] = value.GetAsUInt32();
+    break;
+
+  case fpr_f0:
+  case fpr_f1:
+  case fpr_f2:
+  case fpr_f3:
+  case fpr_f4:
+  case fpr_f5:
+  case fpr_f6:
+  case fpr_f7:
+  case fpr_f8:
+  case fpr_f9:
+  case fpr_f10:
+  case fpr_f11:
+  case fpr_f12:
+  case fpr_f13:
+  case fpr_f14:
+  case fpr_f15:
+  case fpr_f16:
+  case fpr_f17:
+  case fpr_f18:
+  case fpr_f19:
+  case fpr_f20:
+  case fpr_f21:
+  case fpr_f22:
+  case fpr_f23:
+  case fpr_f24:
+  case fpr_f25:
+  case fpr_f26:
+  case fpr_f27:
+  case fpr_f28:
+  case fpr_f29:
+  case fpr_f30:
+  case fpr_f31:
+  case fpr_fcsr:
+    (&fpr.f0)[reg - fpr_f0] = value.GetAsUInt32();
+    break;
+
+  case exc_exception:
+    exc.exception = value.GetAsUInt32();
+    break;
+
+  case exc_fsr:
+    exc.fsr = value.GetAsUInt32();
+    break;
+
+  case exc_far:
+    exc.far = value.GetAsUInt32();
+    break;
+
+  case csr_bank:
+    // These values don't fit into scalar types,
+    // RegisterContext::ReadRegisterBytes() must be used for these registers
+    //::memcpy(csr.bytes, value.GetBytes(),
+    // value.GetByteSize());
+    return false;
+
+  default:
+    return false;
+  }
+  return WriteRegisterSet(set) == 0;
+}
+
+bool RegisterContextDarwin_riscv32::ReadAllRegisterValues(
+    lldb::WritableDataBufferSP &data_sp) {
+  data_sp = std::make_shared<DataBufferHeap>(REG_CONTEXT_SIZE, 0);
+  if (ReadGPR(false) == 0 && ReadFPU(false) == 0 && ReadEXC(false) == 0 &&
+      ReadCSR(false) == 0) {
+    uint8_t *dst = data_sp->GetBytes();
+    ::memcpy(dst, &gpr, sizeof(gpr));
+    dst += sizeof(gpr);
+
+    ::memcpy(dst, &fpr, sizeof(fpr));
+    dst += sizeof(gpr);
+
+    ::memcpy(dst, &exc, sizeof(exc));
+    return true;
+
+    ::memcpy(dst, &csr, sizeof(csr));
+    return true;
+  }
+  return false;
+}
+
+bool RegisterContextDarwin_riscv32::WriteAllRegisterValues(
+    const lldb::DataBufferSP &data_sp) {
+  if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE) {
+    const uint8_t *src = data_sp->GetBytes();
+    ::memcpy(&gpr, src, sizeof(gpr));
+    src += sizeof(gpr);
+
+    ::memcpy(&fpr, src, sizeof(fpr));
+    src += sizeof(fpr);
+
+    ::memcpy(&exc, src, sizeof(exc));
+    src += sizeof(exc);
+
+    ::memcpy(&csr, src, sizeof(csr));
+    uint32_t success_count = 0;
+
+    if (WriteGPR() == 0)
+      ++success_count;
+    if (WriteFPU() == 0)
+      ++success_count;
+    if (WriteEXC() == 0)
+      ++success_count;
+    if (WriteCSR() == 0)
+      ++success_count;
+    return success_count == 3;
+  }
+  return false;
+}
+
+uint32_t RegisterContextDarwin_riscv32::ConvertRegisterKindToRegisterNumber(
+    lldb::RegisterKind kind, uint32_t reg) {
+  if (kind == eRegisterKindGeneric) {
+    switch (reg) {
+    case LLDB_REGNUM_GENERIC_PC:
+      return gpr_pc;
+    case LLDB_REGNUM_GENERIC_SP:
+      return gpr_x2;
+    case LLDB_REGNUM_GENERIC_FP:
+      return gpr_x8;
+    case LLDB_REGNUM_GENERIC_RA:
+      return gpr_x1;
+    default:
+      break;
+    }
+  } else if (kind == eRegisterKindEHFrame || kind == eRegisterKindDWARF) {
+    switch (reg) {
+    case riscv_dwarf::dwarf_gpr_x0:
+    case riscv_dwarf::dwarf_gpr_x1:
+    case riscv_dwarf::dwarf_gpr_x2:
+    case riscv_dwarf::dwarf_gpr_x3:
+    case riscv_dwarf::dwarf_gpr_x4:
+    case riscv_dwarf::dwarf_gpr_x5:
+    case riscv_dwarf::dwarf_gpr_x6:
+    case riscv_dwarf::dwarf_gpr_x7:
+    case riscv_dwarf::dwarf_gpr_x8:
+    case riscv_dwarf::dwarf_gpr_x9:
+    case riscv_dwarf::dwarf_gpr_x10:
+    case riscv_dwarf::dwarf_gpr_x11:
+    case riscv_dwarf::dwarf_gpr_x12:
+    case riscv_dwarf::dwarf_gpr_x13:
+    case riscv_dwarf::dwarf_gpr_x14:
+    case riscv_dwarf::dwarf_gpr_x15:
+    case riscv_dwarf::dwarf_gpr_x16:
+    case riscv_dwarf::dwarf_gpr_x17:
+    case riscv_dwarf::dwarf_gpr_x18:
+    case riscv_dwarf::dwarf_gpr_x19:
+    case riscv_dwarf::dwarf_gpr_x20:
+    case riscv_dwarf::dwarf_gpr_x21:
+    case riscv_dwarf::dwarf_gpr_x22:
+    case riscv_dwarf::dwarf_gpr_x23:
+    case riscv_dwarf::dwarf_gpr_x24:
+    case riscv_dwarf::dwarf_gpr_x25:
+    case riscv_dwarf::dwarf_gpr_x26:
+    case riscv_dwarf::dwarf_gpr_x27:
+    case riscv_dwarf::dwarf_gpr_x28:
+    case riscv_dwarf::dwarf_gpr_x29:
+    case riscv_dwarf::dwarf_gpr_x30:
+    case riscv_dwarf::dwarf_gpr_x31:
+      return gpr_x0 + (reg - riscv_dwarf::dwarf_gpr_x0);
+
+    case riscv_dwarf::dwarf_fpr_f0:
+    case riscv_dwarf::dwarf_fpr_f1:
+    case riscv_dwarf::dwarf_fpr_f2:
+    case riscv_dwarf::dwarf_fpr_f3:
+    case riscv_dwarf::dwarf_fpr_f4:
+    case riscv_dwarf::dwarf_fpr_f5:
+    case riscv_dwarf::dwarf_fpr_f6:
+    case riscv_dwarf::dwarf_fpr_f7:
+    case riscv_dwarf::dwarf_fpr_f8:
+    case riscv_dwarf::dwarf_fpr_f9:
+    case riscv_dwarf::dwarf_fpr_f10:
+    case riscv_dwarf::dwarf_fpr_f11:
+    case riscv_dwarf::dwarf_fpr_f12:
+    case riscv_dwarf::dwarf_fpr_f13:
+    case riscv_dwarf::dwarf_fpr_f14:
+    case riscv_dwarf::dwarf_fpr_f15:
+    case riscv_dwarf::dwarf_fpr_f16:
+    case riscv_dwarf::dwarf_fpr_f17:
+    case riscv_dwarf::dwarf_fpr_f18:
+    case riscv_dwarf::dwarf_fpr_f19:
+    case riscv_dwarf::dwarf_fpr_f20:
+    case riscv_dwarf::dwarf_fpr_f21:
+    case riscv_dwarf::dwarf_fpr_f22:
+    case riscv_dwarf::dwarf_fpr_f23:
+    case riscv_dwarf::dwarf_fpr_f24:
+    case riscv_dwarf::dwarf_fpr_f25:
+    case riscv_dwarf::dwarf_fpr_f26:
+    case riscv_dwarf::dwarf_fpr_f27:
+    case riscv_dwarf::dwarf_fpr_f28:
+    case riscv_dwarf::dwarf_fpr_f29:
+    case riscv_dwarf::dwarf_fpr_f30:
+    case riscv_dwarf::dwarf_fpr_f31:
+      return fpr_f0 + (reg - riscv_dwarf::dwarf_fpr_f0);
+
+    default:
+      break;
+    }
+  } else if (kind == eRegisterKindLLDB) {
+    return reg;
+  }
+  return LLDB_INVALID_REGNUM;
+}
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_riscv32.h b/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_riscv32.h
new file mode 100644
index 0000000000000..22d61aef712a6
--- /dev/null
+++ b/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_riscv32.h
@@ -0,0 +1,260 @@
+//===-- RegisterContextDarwin_riscv32.h -------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTDARWIN_RISCV32_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTDARWIN_RISCV32_H
+
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/lldb-private.h"
+
+class RegisterContextDarwin_riscv32 : public lldb_private::RegisterContext {
+public:
+  RegisterContextDarwin_riscv32(lldb_private::Thread &thread,
+                                uint32_t concrete_frame_idx);
+
+  ~RegisterContextDarwin_riscv32() override;
+
+  void InvalidateAllRegisters() override;
+
+  size_t GetRegisterCount() override;
+
+  const lldb_private::RegisterInfo *GetRegisterInfoAtIndex(size_t reg) override;
+
+  size_t GetRegisterSetCount() override;
+
+  const lldb_private::RegisterSet *GetRegisterSet(size_t set) override;
+
+  bool ReadRegister(const lldb_private::RegisterInfo *reg_info,
+                    lldb_private::RegisterValue &value) override;
+
+  bool WriteRegister(const lldb_private::RegisterInfo *reg_info,
+                     const lldb_private::RegisterValue &value) override;
+
+  bool ReadAllRegisterValues(lldb::WritableDataBufferSP &data_sp) override;
+
+  bool WriteAllRegisterValues(const lldb::DataBufferSP &data_sp) override;
+
+  uint32_t ConvertRegisterKindToRegisterNumber(lldb::RegisterKind kind,
+                                               uint32_t num) override;
+
+  struct GPR {
+    uint32_t x0;
+    uint32_t x1;
+    uint32_t x2;
+    uint32_t x3;
+    uint32_t x4;
+    uint32_t x5;
+    uint32_t x6;
+    uint32_t x7;
+    uint32_t x8;
+    uint32_t x9;
+    uint32_t x10;
+    uint32_t x11;
+    uint32_t x12;
+    uint32_t x13;
+    uint32_t x14;
+    uint32_t x15;
+    uint32_t x16;
+    uint32_t x17;
+    uint32_t x18;
+    uint32_t x19;
+    uint32_t x20;
+    uint32_t x21;
+    uint32_t x22;
+    uint32_t x23;
+    uint32_t x24;
+    uint32_t x25;
+    uint32_t x26;
+    uint32_t x27;
+    uint32_t x28;
+    uint32_t x29;
+    uint32_t x30;
+    uint32_t x31;
+    uint32_t pc;
+  };
+
+  struct FPU {
+    uint32_t f0;
+    uint32_t f1;
+    uint32_t f2;
+    uint32_t f3;
+    uint32_t f4;
+    uint32_t f5;
+    uint32_t f6;
+    uint32_t f7;
+    uint32_t f8;
+    uint32_t f9;
+    uint32_t f10;
+    uint32_t f11;
+    uint32_t f12;
+    uint32_t f13;
+    uint32_t f14;
+    uint32_t f15;
+    uint32_t f16;
+    uint32_t f17;
+    uint32_t f18;
+    uint32_t f19;
+    uint32_t f20;
+    uint32_t f21;
+    uint32_t f22;
+    uint32_t f23;
+    uint32_t f24;
+    uint32_t f25;
+    uint32_t f26;
+    uint32_t f27;
+    uint32_t f28;
+    uint32_t f29;
+    uint32_t f30;
+    uint32_t f31;
+    uint32_t fcsr;
+  };
+
+  struct EXC {
+    uint32_t exception;
+    uint32_t fsr;
+    uint32_t far;
+  };
+
+  struct CSR {
+    uint32_t csr[1024];
+  };
+
+protected:
+  enum {
+    GPRRegSet = 2,  // RV32_THREAD_STATE
+    EXCRegSet = 3,  // RV32_EXCEPTION_STATE
+    FPURegSet = 4,  // RV_FP32_STATE
+    CSRRegSet1 = 6, // RV_CSR_STATE1
+    CSRRegSet2 = 7, // RV_CSR_STATE2
+    CSRRegSet3 = 8, // RV_CSR_STATE3
+    CSRRegSet4 = 9, // RV_CSR_STATE4
+    CSRRegSet = 10  // full 16kbyte CSR reg bank
+  };
+
+  enum {
+    GPRWordCount = sizeof(GPR) / sizeof(uint32_t),
+    FPUWordCount = sizeof(FPU) / sizeof(uint32_t),
+    EXCWordCount = sizeof(EXC) / sizeof(uint32_t),
+    CSRWordCount = sizeof(CSR) / sizeof(uint32_t)
+  };
+
+  enum { Read = 0, Write = 1, kNumErrors = 2 };
+
+  GPR gpr;
+  FPU fpr;
+  EXC exc;
+  CSR csr;
+  int gpr_errs[2]; // Read/Write errors
+  int fpr_errs[2]; // Read/Write errors
+  int exc_errs[2]; // Read/Write errors
+  int csr_errs[2]; // Read/Write errors
+
+  void InvalidateAllRegisterStates() {
+    SetError(GPRRegSet, Read, -1);
+    SetError(FPURegSet, Read, -1);
+    SetError(EXCRegSet, Read, -1);
+    SetError(CSRRegSet, Read, -1);
+  }
+
+  int GetError(int flavor, uint32_t err_idx) const {
+    if (err_idx < kNumErrors) {
+      switch (flavor) {
+      // When getting all errors, just OR all values together to see if
+      // we got any kind of error.
+      case GPRRegSet:
+        return gpr_errs[err_idx];
+      case FPURegSet:
+        return fpr_errs[err_idx];
+      case EXCRegSet:
+        return exc_errs[err_idx];
+      case CSRRegSet:
+        return csr_errs[err_idx];
+      default:
+        break;
+      }
+    }
+    return -1;
+  }
+
+  bool SetError(int flavor, uint32_t err_idx, int err) {
+    if (err_idx < kNumErrors) {
+      switch (flavor) {
+      case GPRRegSet:
+        gpr_errs[err_idx] = err;
+        return true;
+
+      case FPURegSet:
+        fpr_errs[err_idx] = err;
+        return true;
+
+      case EXCRegSet:
+        exc_errs[err_idx] = err;
+        return true;
+
+      case CSRRegSet:
+        csr_errs[err_idx] = err;
+        return true;
+
+      default:
+        break;
+      }
+    }
+    return false;
+  }
+
+  bool RegisterSetIsCached(int set) const { return GetError(set, Read) == 0; }
+
+  void LogGPR(lldb_private::Log *log, const char *title);
+
+  int ReadGPR(bool force);
+
+  int ReadFPU(bool force);
+
+  int ReadEXC(bool force);
+
+  int ReadCSR(bool force);
+
+  int WriteGPR();
+
+  int WriteFPU();
+
+  int WriteEXC();
+
+  int WriteCSR();
+
+  // Subclasses override these to do the actual reading.
+  virtual int DoReadGPR(lldb::tid_t tid, int flavor, GPR &gpr) = 0;
+
+  virtual int DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpr) = 0;
+
+  virtual int DoReadEXC(lldb::tid_t tid, int flavor, EXC &exc) = 0;
+
+  virtual int DoReadCSR(lldb::tid_t tid, int flavor, CSR &exc) = 0;
+
+  virtual int DoWriteGPR(lldb::tid_t tid, int flavor, const GPR &gpr) = 0;
+
+  virtual int DoWriteFPU(lldb::tid_t tid, int flavor, const FPU &fpr) = 0;
+
+  virtual int DoWriteEXC(lldb::tid_t tid, int flavor, const EXC &exc) = 0;
+
+  virtual int DoWriteCSR(lldb::tid_t tid, int flavor, const CSR &exc) = 0;
+
+  int ReadRegisterSet(uint32_t set, bool force);
+
+  int WriteRegisterSet(uint32_t set);
+
+  static uint32_t GetRegisterNumber(uint32_t reg_kind, uint32_t reg_num);
+
+  static int GetSetForNativeRegNum(int reg_num);
+
+  static size_t GetRegisterInfosCount();
+
+  static const lldb_private::RegisterInfo *GetRegisterInfos();
+};
+
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTDARWIN_RISCV32_H
diff --git a/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp b/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
index 5f85f99ce7bdd..6635b15b669f1 100644
--- a/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
+++ b/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
@@ -289,7 +289,7 @@ void ProcessElfCore::UpdateBuildIdForNTFileEntries() {
 UUID ProcessElfCore::FindModuleUUID(const llvm::StringRef path) {
   // Returns the gnu uuid from matched NT_FILE entry
   for (NT_FILE_Entry &entry : m_nt_file_entries)
-    if (path == entry.path)
+    if (path == entry.path && entry.uuid.IsValid())
       return entry.uuid;
   return UUID();
 }
diff --git a/lldb/source/Plugins/SymbolFile/DWARF/CMakeLists.txt b/lldb/source/Plugins/SymbolFile/DWARF/CMakeLists.txt
index e87194dfe74cb..2d2eb73f4513b 100644
--- a/lldb/source/Plugins/SymbolFile/DWARF/CMakeLists.txt
+++ b/lldb/source/Plugins/SymbolFile/DWARF/CMakeLists.txt
@@ -30,6 +30,7 @@ add_lldb_library(lldbPluginSymbolFileDWARF PLUGIN
   DWARFUnit.cpp
   LogChannelDWARF.cpp
   ManualDWARFIndex.cpp
+  ManualDWARFIndexSet.cpp
   NameToDIE.cpp
   SymbolFileDWARF.cpp
   SymbolFileDWARFDwo.cpp
diff --git a/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp b/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
index 98066b4a32cbc..523820874752a 100644
--- a/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
+++ b/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
@@ -77,8 +77,10 @@ void ManualDWARFIndex::Index() {
                           lldb::eDescriptionLevelBrief);
 
   // Include 2 passes per unit to index for extracting DIEs from the unit and
-  // indexing the unit, and then 8 extra entries for finalizing each index set.
-  const uint64_t total_progress = units_to_index.size() * 2 + 8;
+  // indexing the unit, and then extra entries for finalizing each index in the
+  // set.
+  const auto indices = IndexSet<NameToDIE>::Indices();
+  const uint64_t total_progress = units_to_index.size() * 2 + indices.size();
   Progress progress("Manually indexing DWARF", module_desc.GetData(),
                     total_progress, /*debugger=*/nullptr,
                     Progress::kDefaultHighFrequencyReportTime);
@@ -122,7 +124,7 @@ void ManualDWARFIndex::Index() {
   });
 
   // Now index all DWARF unit in parallel.
-  std::vector<IndexSet> sets(num_threads);
+  std::vector<IndexSet<NameToDIE>> sets(num_threads);
   for_each_unit(
       [this, dwp_dwarf, &sets](size_t worker_id, size_t, DWARFUnit *unit) {
         IndexUnit(*unit, dwp_dwarf, sets[worker_id]);
@@ -130,29 +132,22 @@ void ManualDWARFIndex::Index() {
 
   // Merge partial indexes into a single index. Process each index in a set in
   // parallel.
-  auto finalize_fn = [this, &sets, &progress](NameToDIE(IndexSet::*index)) {
-    NameToDIE &result = m_set.*index;
-    for (auto &set : sets)
-      result.Append(set.*index);
-    result.Finalize();
-    progress.Increment();
-  };
-
-  task_group.async(finalize_fn, &IndexSet::function_basenames);
-  task_group.async(finalize_fn, &IndexSet::function_fullnames);
-  task_group.async(finalize_fn, &IndexSet::function_methods);
-  task_group.async(finalize_fn, &IndexSet::function_selectors);
-  task_group.async(finalize_fn, &IndexSet::objc_class_selectors);
-  task_group.async(finalize_fn, &IndexSet::globals);
-  task_group.async(finalize_fn, &IndexSet::types);
-  task_group.async(finalize_fn, &IndexSet::namespaces);
+  for (NameToDIE IndexSet<NameToDIE>::*index : indices) {
+    task_group.async([this, &sets, index, &progress]() {
+      NameToDIE &result = m_set.*index;
+      for (auto &set : sets)
+        result.Append(set.*index);
+      result.Finalize();
+      progress.Increment();
+    });
+  }
   task_group.wait();
 
   SaveToCache();
 }
 
 void ManualDWARFIndex::IndexUnit(DWARFUnit &unit, SymbolFileDWARFDwo *dwp,
-                                 IndexSet &set) {
+                                 IndexSet<NameToDIE> &set) {
   Log *log = GetLog(DWARFLog::Lookups);
 
   if (log) {
@@ -210,7 +205,7 @@ void ManualDWARFIndex::IndexUnit(DWARFUnit &unit, SymbolFileDWARFDwo *dwp,
 
 void ManualDWARFIndex::IndexUnitImpl(DWARFUnit &unit,
                                      const LanguageType cu_language,
-                                     IndexSet &set) {
+                                     IndexSet<NameToDIE> &set) {
   for (const DWARFDebugInfoEntry &die : unit.dies()) {
     const dw_tag_t tag = die.Tag();
 
@@ -555,142 +550,6 @@ void ManualDWARFIndex::Dump(Stream &s) {
   m_set.namespaces.Dump(&s);
 }
 
-constexpr llvm::StringLiteral kIdentifierManualDWARFIndex("DIDX");
-// Define IDs for the different tables when encoding and decoding the
-// ManualDWARFIndex NameToDIE objects so we can avoid saving any empty maps.
-enum DataID {
-  kDataIDFunctionBasenames = 1u,
-  kDataIDFunctionFullnames,
-  kDataIDFunctionMethods,
-  kDataIDFunctionSelectors,
-  kDataIDFunctionObjcClassSelectors,
-  kDataIDGlobals,
-  kDataIDTypes,
-  kDataIDNamespaces,
-  kDataIDEnd = 255u,
-
-};
-
-// Version 2 changes the encoding of DIERef objects used in the DWARF manual
-// index name tables. See DIERef class for details.
-constexpr uint32_t CURRENT_CACHE_VERSION = 2;
-
-bool ManualDWARFIndex::IndexSet::Decode(const DataExtractor &data,
-                                        lldb::offset_t *offset_ptr) {
-  StringTableReader strtab;
-  // We now decode the string table for all strings in the data cache file.
-  if (!strtab.Decode(data, offset_ptr))
-    return false;
-
-  llvm::StringRef identifier((const char *)data.GetData(offset_ptr, 4), 4);
-  if (identifier != kIdentifierManualDWARFIndex)
-    return false;
-  const uint32_t version = data.GetU32(offset_ptr);
-  if (version != CURRENT_CACHE_VERSION)
-    return false;
-
-  bool done = false;
-  while (!done) {
-    switch (data.GetU8(offset_ptr)) {
-    default:
-      // If we got here, this is not expected, we expect the data IDs to match
-      // one of the values from the DataID enumeration.
-      return false;
-    case kDataIDFunctionBasenames:
-      if (!function_basenames.Decode(data, offset_ptr, strtab))
-        return false;
-      break;
-    case kDataIDFunctionFullnames:
-      if (!function_fullnames.Decode(data, offset_ptr, strtab))
-        return false;
-      break;
-    case kDataIDFunctionMethods:
-      if (!function_methods.Decode(data, offset_ptr, strtab))
-        return false;
-      break;
-    case kDataIDFunctionSelectors:
-      if (!function_selectors.Decode(data, offset_ptr, strtab))
-        return false;
-      break;
-    case kDataIDFunctionObjcClassSelectors:
-      if (!objc_class_selectors.Decode(data, offset_ptr, strtab))
-        return false;
-      break;
-    case kDataIDGlobals:
-      if (!globals.Decode(data, offset_ptr, strtab))
-        return false;
-      break;
-    case kDataIDTypes:
-      if (!types.Decode(data, offset_ptr, strtab))
-        return false;
-      break;
-    case kDataIDNamespaces:
-      if (!namespaces.Decode(data, offset_ptr, strtab))
-        return false;
-      break;
-    case kDataIDEnd:
-      // We got to the end of our NameToDIE encodings.
-      done = true;
-      break;
-    }
-  }
-  // Success!
-  return true;
-}
-
-void ManualDWARFIndex::IndexSet::Encode(DataEncoder &encoder) const {
-  ConstStringTable strtab;
-
-  // Encoder the DWARF index into a separate encoder first. This allows us
-  // gather all of the strings we willl need in "strtab" as we will need to
-  // write the string table out before the symbol table.
-  DataEncoder index_encoder(encoder.GetByteOrder(),
-                            encoder.GetAddressByteSize());
-
-  index_encoder.AppendData(kIdentifierManualDWARFIndex);
-  // Encode the data version.
-  index_encoder.AppendU32(CURRENT_CACHE_VERSION);
-
-  if (!function_basenames.IsEmpty()) {
-    index_encoder.AppendU8(kDataIDFunctionBasenames);
-    function_basenames.Encode(index_encoder, strtab);
-  }
-  if (!function_fullnames.IsEmpty()) {
-    index_encoder.AppendU8(kDataIDFunctionFullnames);
-    function_fullnames.Encode(index_encoder, strtab);
-  }
-  if (!function_methods.IsEmpty()) {
-    index_encoder.AppendU8(kDataIDFunctionMethods);
-    function_methods.Encode(index_encoder, strtab);
-  }
-  if (!function_selectors.IsEmpty()) {
-    index_encoder.AppendU8(kDataIDFunctionSelectors);
-    function_selectors.Encode(index_encoder, strtab);
-  }
-  if (!objc_class_selectors.IsEmpty()) {
-    index_encoder.AppendU8(kDataIDFunctionObjcClassSelectors);
-    objc_class_selectors.Encode(index_encoder, strtab);
-  }
-  if (!globals.IsEmpty()) {
-    index_encoder.AppendU8(kDataIDGlobals);
-    globals.Encode(index_encoder, strtab);
-  }
-  if (!types.IsEmpty()) {
-    index_encoder.AppendU8(kDataIDTypes);
-    types.Encode(index_encoder, strtab);
-  }
-  if (!namespaces.IsEmpty()) {
-    index_encoder.AppendU8(kDataIDNamespaces);
-    namespaces.Encode(index_encoder, strtab);
-  }
-  index_encoder.AppendU8(kDataIDEnd);
-
-  // Now that all strings have been gathered, we will emit the string table.
-  strtab.Encode(encoder);
-  // Followed by the symbol table data.
-  encoder.AppendData(index_encoder.GetData());
-}
-
 bool ManualDWARFIndex::Decode(const DataExtractor &data,
                               lldb::offset_t *offset_ptr,
                               bool &signature_mismatch) {
@@ -702,10 +561,10 @@ bool ManualDWARFIndex::Decode(const DataExtractor &data,
     signature_mismatch = true;
     return false;
   }
-  IndexSet set;
-  if (!set.Decode(data, offset_ptr))
+  std::optional<IndexSet<NameToDIE>> set = DecodeIndexSet(data, offset_ptr);
+  if (!set)
     return false;
-  m_set = std::move(set);
+  m_set = std::move(*set);
   return true;
 }
 
@@ -713,7 +572,7 @@ bool ManualDWARFIndex::Encode(DataEncoder &encoder) const {
   CacheSignature signature(m_dwarf->GetObjectFile());
   if (!signature.Encode(encoder))
     return false;
-  m_set.Encode(encoder);
+  EncodeIndexSet(m_set, encoder);
   return true;
 }
 
diff --git a/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.h b/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.h
index 6a52c88a99220..04627b0ad91e6 100644
--- a/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.h
+++ b/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.h
@@ -10,6 +10,7 @@
 #define LLDB_SOURCE_PLUGINS_SYMBOLFILE_DWARF_MANUALDWARFINDEX_H
 
 #include "Plugins/SymbolFile/DWARF/DWARFIndex.h"
+#include "Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.h"
 #include "Plugins/SymbolFile/DWARF/NameToDIE.h"
 #include "llvm/ADT/DenseSet.h"
 
@@ -58,29 +59,6 @@ class ManualDWARFIndex : public DWARFIndex {
 
   void Dump(Stream &s) override;
 
-  // Make IndexSet public so we can unit test the encoding and decoding logic.
-  struct IndexSet {
-    NameToDIE function_basenames;
-    NameToDIE function_fullnames;
-    NameToDIE function_methods;
-    NameToDIE function_selectors;
-    NameToDIE objc_class_selectors;
-    NameToDIE globals;
-    NameToDIE types;
-    NameToDIE namespaces;
-    bool Decode(const DataExtractor &data, lldb::offset_t *offset_ptr);
-    void Encode(DataEncoder &encoder) const;
-    bool operator==(const IndexSet &rhs) const {
-      return function_basenames == rhs.function_basenames &&
-             function_fullnames == rhs.function_fullnames &&
-             function_methods == rhs.function_methods &&
-             function_selectors == rhs.function_selectors &&
-             objc_class_selectors == rhs.objc_class_selectors &&
-             globals == rhs.globals && types == rhs.types &&
-             namespaces == rhs.namespaces;
-    }
-  };
-
 private:
   void Index();
 
@@ -162,11 +140,12 @@ class ManualDWARFIndex : public DWARFIndex {
   ///   false if the symbol table wasn't cached or was out of date.
   bool LoadFromCache();
 
-  void IndexUnit(DWARFUnit &unit, SymbolFileDWARFDwo *dwp, IndexSet &set);
+  void IndexUnit(DWARFUnit &unit, SymbolFileDWARFDwo *dwp,
+                 IndexSet<NameToDIE> &set);
 
   static void IndexUnitImpl(DWARFUnit &unit,
                             const lldb::LanguageType cu_language,
-                            IndexSet &set);
+                            IndexSet<NameToDIE> &set);
 
   /// Return true if this manual DWARF index is covering only part of the DWARF.
   ///
@@ -184,7 +163,7 @@ class ManualDWARFIndex : public DWARFIndex {
   llvm::DenseSet<dw_offset_t> m_units_to_avoid;
   llvm::DenseSet<uint64_t> m_type_sigs_to_avoid;
 
-  IndexSet m_set;
+  IndexSet<NameToDIE> m_set;
   bool m_indexed = false;
 };
 } // namespace dwarf
diff --git a/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.cpp b/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.cpp
new file mode 100644
index 0000000000000..ac6f0815e8f03
--- /dev/null
+++ b/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.cpp
@@ -0,0 +1,154 @@
+//===-- ManualDWARFIndex.cpp ----------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.h"
+#include "lldb/Core/DataFileCache.h"
+#include "lldb/Utility/DataEncoder.h"
+#include "lldb/Utility/DataExtractor.h"
+#include <cstdint>
+
+using namespace lldb_private;
+using namespace lldb_private::plugin::dwarf;
+
+namespace {
+// Define IDs for the different tables when encoding and decoding the
+// ManualDWARFIndex NameToDIE objects so we can avoid saving any empty maps.
+enum DataID {
+  kDataIDFunctionBasenames = 1u,
+  kDataIDFunctionFullnames,
+  kDataIDFunctionMethods,
+  kDataIDFunctionSelectors,
+  kDataIDFunctionObjcClassSelectors,
+  kDataIDGlobals,
+  kDataIDTypes,
+  kDataIDNamespaces,
+  kDataIDEnd = 255u,
+};
+} // namespace
+
+// Version 2 changes the encoding of DIERef objects used in the DWARF manual
+// index name tables. See DIERef class for details.
+static constexpr uint32_t CURRENT_CACHE_VERSION = 2;
+
+static constexpr llvm::StringLiteral kIdentifierManualDWARFIndex("DIDX");
+
+std::optional<IndexSet<NameToDIE>>
+plugin::dwarf::DecodeIndexSet(const DataExtractor &data,
+                              lldb::offset_t *offset_ptr) {
+  StringTableReader strtab;
+  // We now decode the string table for all strings in the data cache file.
+  if (!strtab.Decode(data, offset_ptr))
+    return std::nullopt;
+
+  llvm::StringRef identifier((const char *)data.GetData(offset_ptr, 4), 4);
+  if (identifier != kIdentifierManualDWARFIndex)
+    return std::nullopt;
+  const uint32_t version = data.GetU32(offset_ptr);
+  if (version != CURRENT_CACHE_VERSION)
+    return std::nullopt;
+
+  IndexSet<NameToDIE> result;
+  while (true) {
+    switch (data.GetU8(offset_ptr)) {
+    default:
+      // If we got here, this is not expected, we expect the data IDs to match
+      // one of the values from the DataID enumeration.
+      return std::nullopt;
+    case kDataIDFunctionBasenames:
+      if (!result.function_basenames.Decode(data, offset_ptr, strtab))
+        return std::nullopt;
+      break;
+    case kDataIDFunctionFullnames:
+      if (!result.function_fullnames.Decode(data, offset_ptr, strtab))
+        return std::nullopt;
+      break;
+    case kDataIDFunctionMethods:
+      if (!result.function_methods.Decode(data, offset_ptr, strtab))
+        return std::nullopt;
+      break;
+    case kDataIDFunctionSelectors:
+      if (!result.function_selectors.Decode(data, offset_ptr, strtab))
+        return std::nullopt;
+      break;
+    case kDataIDFunctionObjcClassSelectors:
+      if (!result.objc_class_selectors.Decode(data, offset_ptr, strtab))
+        return std::nullopt;
+      break;
+    case kDataIDGlobals:
+      if (!result.globals.Decode(data, offset_ptr, strtab))
+        return std::nullopt;
+      break;
+    case kDataIDTypes:
+      if (!result.types.Decode(data, offset_ptr, strtab))
+        return std::nullopt;
+      break;
+    case kDataIDNamespaces:
+      if (!result.namespaces.Decode(data, offset_ptr, strtab))
+        return std::nullopt;
+      break;
+    case kDataIDEnd:
+      // We got to the end of our NameToDIE encodings.
+      return std::move(result);
+      break;
+    }
+  }
+}
+
+void plugin::dwarf::EncodeIndexSet(const IndexSet<NameToDIE> &set,
+                                   DataEncoder &encoder) {
+  ConstStringTable strtab;
+
+  // Encoder the DWARF index into a separate encoder first. This allows us
+  // gather all of the strings we willl need in "strtab" as we will need to
+  // write the string table out before the symbol table.
+  DataEncoder index_encoder(encoder.GetByteOrder(),
+                            encoder.GetAddressByteSize());
+
+  index_encoder.AppendData(kIdentifierManualDWARFIndex);
+  // Encode the data version.
+  index_encoder.AppendU32(CURRENT_CACHE_VERSION);
+
+  if (!set.function_basenames.IsEmpty()) {
+    index_encoder.AppendU8(kDataIDFunctionBasenames);
+    set.function_basenames.Encode(index_encoder, strtab);
+  }
+  if (!set.function_fullnames.IsEmpty()) {
+    index_encoder.AppendU8(kDataIDFunctionFullnames);
+    set.function_fullnames.Encode(index_encoder, strtab);
+  }
+  if (!set.function_methods.IsEmpty()) {
+    index_encoder.AppendU8(kDataIDFunctionMethods);
+    set.function_methods.Encode(index_encoder, strtab);
+  }
+  if (!set.function_selectors.IsEmpty()) {
+    index_encoder.AppendU8(kDataIDFunctionSelectors);
+    set.function_selectors.Encode(index_encoder, strtab);
+  }
+  if (!set.objc_class_selectors.IsEmpty()) {
+    index_encoder.AppendU8(kDataIDFunctionObjcClassSelectors);
+    set.objc_class_selectors.Encode(index_encoder, strtab);
+  }
+  if (!set.globals.IsEmpty()) {
+    index_encoder.AppendU8(kDataIDGlobals);
+    set.globals.Encode(index_encoder, strtab);
+  }
+  if (!set.types.IsEmpty()) {
+    index_encoder.AppendU8(kDataIDTypes);
+    set.types.Encode(index_encoder, strtab);
+  }
+  if (!set.namespaces.IsEmpty()) {
+    index_encoder.AppendU8(kDataIDNamespaces);
+    set.namespaces.Encode(index_encoder, strtab);
+  }
+  index_encoder.AppendU8(kDataIDEnd);
+
+  // Now that all strings have been gathered, we will emit the string table.
+  strtab.Encode(encoder);
+  // Followed by the symbol table data.
+  encoder.AppendData(index_encoder.GetData());
+}
diff --git a/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.h b/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.h
new file mode 100644
index 0000000000000..7fb57421c57dd
--- /dev/null
+++ b/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.h
@@ -0,0 +1,54 @@
+//===-- ManualDWARFIndexSet.h -----------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_PLUGINS_SYMBOLFILE_DWARF_MANUALDWARFINDEXSET_H
+#define LLDB_SOURCE_PLUGINS_SYMBOLFILE_DWARF_MANUALDWARFINDEXSET_H
+
+#include "Plugins/SymbolFile/DWARF/NameToDIE.h"
+#include "lldb/Utility/DataEncoder.h"
+#include "lldb/Utility/DataExtractor.h"
+#include "llvm/ADT/STLExtras.h"
+#include <optional>
+
+namespace lldb_private::plugin::dwarf {
+
+template <typename T> struct IndexSet {
+  T function_basenames;
+  T function_fullnames;
+  T function_methods;
+  T function_selectors;
+  T objc_class_selectors;
+  T globals;
+  T types;
+  T namespaces;
+
+  static std::array<T(IndexSet::*), 8> Indices() {
+    return {&IndexSet::function_basenames,
+            &IndexSet::function_fullnames,
+            &IndexSet::function_methods,
+            &IndexSet::function_selectors,
+            &IndexSet::objc_class_selectors,
+            &IndexSet::globals,
+            &IndexSet::types,
+            &IndexSet::namespaces};
+  }
+
+  friend bool operator==(const IndexSet &lhs, const IndexSet &rhs) {
+    return llvm::all_of(Indices(), [&lhs, &rhs](T(IndexSet::*index)) {
+      return lhs.*index == rhs.*index;
+    });
+  }
+};
+
+std::optional<IndexSet<NameToDIE>> DecodeIndexSet(const DataExtractor &data,
+                                                  lldb::offset_t *offset_ptr);
+void EncodeIndexSet(const IndexSet<NameToDIE> &set, DataEncoder &encoder);
+
+} // namespace lldb_private::plugin::dwarf
+
+#endif // LLDB_SOURCE_PLUGINS_SYMBOLFILE_DWARF_MANUALDWARFINDEXSET_H
diff --git a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
index b95159d882bc7..43f8650db4cad 100644
--- a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
+++ b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
@@ -1323,7 +1323,7 @@ bool SymbolFileDWARF::ParseDebugMacros(CompileUnit &comp_unit) {
 
 size_t SymbolFileDWARF::ParseBlocksRecursive(CompileUnit &comp_unit,
                                              Block *parent_block, DWARFDIE die,
-                                             addr_t subprogram_low_pc) {
+                                             addr_t function_file_addr) {
   size_t blocks_added = 0;
   for (; die; die = die.GetSibling()) {
     dw_tag_t tag = die.Tag();
@@ -1346,19 +1346,9 @@ size_t SymbolFileDWARF::ParseBlocksRecursive(CompileUnit &comp_unit,
                                  decl_line, decl_column, call_file, call_line,
                                  call_column, nullptr)) {
       for (const llvm::DWARFAddressRange &range : ranges) {
-        if (!range.valid())
-          continue;
-        if (range.LowPC >= subprogram_low_pc)
-          block->AddRange(Block::Range(range.LowPC - subprogram_low_pc,
+        if (range.valid() && range.LowPC >= m_first_code_address)
+          block->AddRange(Block::Range(range.LowPC - function_file_addr,
                                        range.HighPC - range.LowPC));
-        else {
-          GetObjectFile()->GetModule()->ReportError(
-              "{0:x8}: adding range [{1:x16}-{2:x16}) which has a base "
-              "that is less than the function's low PC {3:x16}. Please file "
-              "a bug and attach the file at the "
-              "start of this error message",
-              block->GetID(), range.LowPC, range.HighPC, subprogram_low_pc);
-        }
       }
       block->FinalizeRanges();
 
@@ -1386,7 +1376,7 @@ size_t SymbolFileDWARF::ParseBlocksRecursive(CompileUnit &comp_unit,
 
       if (die.HasChildren()) {
         blocks_added += ParseBlocksRecursive(
-            comp_unit, block, die.GetFirstChild(), subprogram_low_pc);
+            comp_unit, block, die.GetFirstChild(), function_file_addr);
       }
     }
   }
diff --git a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
index 7309f7a86b659..c9fdfb7b1cf91 100644
--- a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
+++ b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
@@ -391,7 +391,7 @@ class SymbolFileDWARF : public SymbolFileCommon {
   Function *ParseFunction(CompileUnit &comp_unit, const DWARFDIE &die);
 
   size_t ParseBlocksRecursive(CompileUnit &comp_unit, Block *parent_block,
-                              DWARFDIE die, lldb::addr_t subprogram_low_pc);
+                              DWARFDIE die, lldb::addr_t function_file_addr);
 
   size_t ParseTypes(const SymbolContext &sc, const DWARFDIE &die,
                     bool parse_siblings, bool parse_children);
diff --git a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
index ed6297cc6f3e0..59292f4b24af3 100644
--- a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
+++ b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
@@ -9164,33 +9164,36 @@ ConstString TypeSystemClang::DeclGetName(void *opaque_decl) {
 }
 
 ConstString TypeSystemClang::DeclGetMangledName(void *opaque_decl) {
-  if (opaque_decl) {
-    clang::NamedDecl *nd =
-        llvm::dyn_cast<clang::NamedDecl>((clang::Decl *)opaque_decl);
-    if (nd != nullptr && !llvm::isa<clang::ObjCMethodDecl>(nd)) {
-      clang::MangleContext *mc = getMangleContext();
-      if (mc && mc->shouldMangleCXXName(nd)) {
-        llvm::SmallVector<char, 1024> buf;
-        llvm::raw_svector_ostream llvm_ostrm(buf);
-        if (llvm::isa<clang::CXXConstructorDecl>(nd)) {
-          mc->mangleName(
-              clang::GlobalDecl(llvm::dyn_cast<clang::CXXConstructorDecl>(nd),
-                                Ctor_Complete),
-              llvm_ostrm);
-        } else if (llvm::isa<clang::CXXDestructorDecl>(nd)) {
-          mc->mangleName(
-              clang::GlobalDecl(llvm::dyn_cast<clang::CXXDestructorDecl>(nd),
-                                Dtor_Complete),
-              llvm_ostrm);
-        } else {
-          mc->mangleName(nd, llvm_ostrm);
-        }
-        if (buf.size() > 0)
-          return ConstString(buf.data(), buf.size());
-      }
-    }
+  clang::NamedDecl *nd = llvm::dyn_cast_or_null<clang::NamedDecl>(
+      static_cast<clang::Decl *>(opaque_decl));
+
+  if (!nd || llvm::isa<clang::ObjCMethodDecl>(nd))
+    return {};
+
+  clang::MangleContext *mc = getMangleContext();
+  if (!mc || !mc->shouldMangleCXXName(nd))
+    return {};
+
+  llvm::SmallVector<char, 1024> buf;
+  llvm::raw_svector_ostream llvm_ostrm(buf);
+  if (llvm::isa<clang::CXXConstructorDecl>(nd)) {
+    mc->mangleName(
+        clang::GlobalDecl(llvm::dyn_cast<clang::CXXConstructorDecl>(nd),
+                          Ctor_Complete),
+        llvm_ostrm);
+  } else if (llvm::isa<clang::CXXDestructorDecl>(nd)) {
+    mc->mangleName(
+        clang::GlobalDecl(llvm::dyn_cast<clang::CXXDestructorDecl>(nd),
+                          Dtor_Complete),
+        llvm_ostrm);
+  } else {
+    mc->mangleName(nd, llvm_ostrm);
   }
-  return ConstString();
+
+  if (buf.size() > 0)
+    return ConstString(buf.data(), buf.size());
+
+  return {};
 }
 
 CompilerDeclContext TypeSystemClang::DeclGetDeclContext(void *opaque_decl) {
diff --git a/lldb/source/Utility/ArchSpec.cpp b/lldb/source/Utility/ArchSpec.cpp
index 495215459336a..2e6c6a6ffcbe4 100644
--- a/lldb/source/Utility/ArchSpec.cpp
+++ b/lldb/source/Utility/ArchSpec.cpp
@@ -353,6 +353,8 @@ static const ArchDefinitionEntry g_macho_arch_entries[] = {
     {ArchSpec::eCore_x86_64_x86_64,   llvm::MachO::CPU_TYPE_X86_64,     llvm::MachO::CPU_SUBTYPE_X86_ARCH1,     UINT32_MAX, SUBTYPE_MASK},
     {ArchSpec::eCore_x86_64_x86_64h,  llvm::MachO::CPU_TYPE_X86_64,     llvm::MachO::CPU_SUBTYPE_X86_64_H,      UINT32_MAX, SUBTYPE_MASK},
     {ArchSpec::eCore_x86_64_x86_64,   llvm::MachO::CPU_TYPE_X86_64,     CPU_ANY, UINT32_MAX, UINT32_MAX},
+    {ArchSpec::eCore_riscv32,         llvm::MachO::CPU_TYPE_RISCV,      llvm::MachO::CPU_SUBTYPE_RISCV_ALL,     UINT32_MAX, SUBTYPE_MASK},
+    {ArchSpec::eCore_riscv32,         llvm::MachO::CPU_TYPE_RISCV,      CPU_ANY,                                UINT32_MAX, SUBTYPE_MASK},
     // Catch any unknown mach architectures so we can always use the object and symbol mach-o files
     {ArchSpec::eCore_uknownMach32,    0,                                0,                                      0xFF000000u, 0x00000000u},
     {ArchSpec::eCore_uknownMach64,    llvm::MachO::CPU_ARCH_ABI64,      0,                                      0xFF000000u, 0x00000000u}};
diff --git a/lldb/test/API/commands/expression/completion/TestExprCompletion.py b/lldb/test/API/commands/expression/completion/TestExprCompletion.py
index 022b9436ee8ea..09f2ffe790753 100644
--- a/lldb/test/API/commands/expression/completion/TestExprCompletion.py
+++ b/lldb/test/API/commands/expression/completion/TestExprCompletion.py
@@ -297,6 +297,37 @@ def test_expr_completion_with_descriptions(self):
             enforce_order=True,
         )
 
+    def test_expr_completion_max_results(self):
+        self.build()
+        self.main_source = "main.cpp"
+        self.main_source_spec = lldb.SBFileSpec(self.main_source)
+        self.createTestTarget()
+
+        (target, process, thread, bkpt) = lldbutil.run_to_source_breakpoint(
+            self, "// Break here", self.main_source_spec
+        )
+
+        expected_completions = [
+            "some_expr.~Expr()",
+            "some_expr.operator=(",  # Copy operator
+            "some_expr.operator=(",  # Move operator
+            "some_expr.MemberVariableBar",
+            "some_expr.StaticMemberMethodBar()",
+            "some_expr.Self()",
+            "some_expr.FooNoArgsBar()",
+            "some_expr.FooWithArgsBar(",
+            "some_expr.FooNumbersBar1()",
+            "some_expr.FooUnderscoreBar_()",
+            "some_expr.FooWithMultipleArgsBar(",
+        ]
+
+        for i in range(1, len(expected_completions)):
+            self.completions_match(
+                "expr some_expr.",
+                expected_completions[:i],
+                max_completions=i,
+            )
+
     def assume_no_completions(self, str_input, cursor_pos=None):
         interp = self.dbg.GetCommandInterpreter()
         match_strings = lldb.SBStringList()
diff --git a/lldb/test/API/commands/process/reverse-continue/Makefile b/lldb/test/API/commands/process/reverse-continue/Makefile
new file mode 100644
index 0000000000000..10495940055b6
--- /dev/null
+++ b/lldb/test/API/commands/process/reverse-continue/Makefile
@@ -0,0 +1,3 @@
+C_SOURCES := main.c
+
+include Makefile.rules
diff --git a/lldb/test/API/commands/process/reverse-continue/TestReverseContinue.py b/lldb/test/API/commands/process/reverse-continue/TestReverseContinue.py
new file mode 100644
index 0000000000000..c04d2b9d4b5a5
--- /dev/null
+++ b/lldb/test/API/commands/process/reverse-continue/TestReverseContinue.py
@@ -0,0 +1,66 @@
+"""
+Test the "process continue --reverse" and "--forward" options.
+"""
+
+
+import lldb
+from lldbsuite.test.lldbtest import *
+from lldbsuite.test.decorators import *
+from lldbsuite.test.gdbclientutils import *
+from lldbsuite.test.lldbreverse import ReverseTestBase
+from lldbsuite.test import lldbutil
+
+
+class TestReverseContinue(ReverseTestBase):
+    @skipIfRemote
+    def test_reverse_continue(self):
+        target, _, _ = self.setup_recording()
+
+        # Set breakpoint and reverse-continue
+        trigger_bkpt = target.BreakpointCreateByName("trigger_breakpoint", None)
+        self.assertTrue(trigger_bkpt.GetNumLocations() > 0)
+        self.expect(
+            "process continue --reverse",
+            substrs=["stop reason = breakpoint {0}.1".format(trigger_bkpt.GetID())],
+        )
+        # `process continue` should preserve current base direction.
+        self.expect(
+            "process continue",
+            STOPPED_DUE_TO_HISTORY_BOUNDARY,
+            substrs=["stopped", "stop reason = history boundary"],
+        )
+        self.expect(
+            "process continue --forward",
+            substrs=["stop reason = breakpoint {0}.1".format(trigger_bkpt.GetID())],
+        )
+
+    def setup_recording(self):
+        """
+        Record execution of code between "start_recording" and "stop_recording" breakpoints.
+
+        Returns with the target stopped at "stop_recording", with recording disabled,
+        ready to reverse-execute.
+        """
+        self.build()
+        target = self.dbg.CreateTarget(self.getBuildArtifact("a.out"))
+        process = self.connect(target)
+
+        # Record execution from the start of the function "start_recording"
+        # to the start of the function "stop_recording". We want to keep the
+        # interval that we record as small as possible to minimize the run-time
+        # of our single-stepping recorder.
+        start_recording_bkpt = target.BreakpointCreateByName("start_recording", None)
+        self.assertTrue(start_recording_bkpt.GetNumLocations() > 0)
+        initial_threads = lldbutil.continue_to_breakpoint(process, start_recording_bkpt)
+        self.assertEqual(len(initial_threads), 1)
+        target.BreakpointDelete(start_recording_bkpt.GetID())
+        self.start_recording()
+        stop_recording_bkpt = target.BreakpointCreateByName("stop_recording", None)
+        self.assertTrue(stop_recording_bkpt.GetNumLocations() > 0)
+        lldbutil.continue_to_breakpoint(process, stop_recording_bkpt)
+        target.BreakpointDelete(stop_recording_bkpt.GetID())
+        self.stop_recording()
+
+        self.dbg.SetAsync(False)
+
+        return target, process, initial_threads
diff --git a/lldb/test/API/commands/process/reverse-continue/TestReverseContinueNotSupported.py b/lldb/test/API/commands/process/reverse-continue/TestReverseContinueNotSupported.py
new file mode 100644
index 0000000000000..54d757dc4b98b
--- /dev/null
+++ b/lldb/test/API/commands/process/reverse-continue/TestReverseContinueNotSupported.py
@@ -0,0 +1,52 @@
+"""
+Test the "process continue --reverse" and "--forward" options
+when reverse-continue is not supported.
+"""
+
+
+import lldb
+from lldbsuite.test.lldbtest import *
+from lldbsuite.test.decorators import *
+from lldbsuite.test import lldbutil
+
+
+class TestReverseContinueNotSupported(TestBase):
+    @skipIfWindows
+    def test_reverse_continue_not_supported(self):
+        target = self.connect()
+
+        # Set breakpoint and reverse-continue
+        trigger_bkpt = target.BreakpointCreateByName("trigger_breakpoint", None)
+        self.assertTrue(trigger_bkpt, VALID_BREAKPOINT)
+        # `process continue --forward` should work.
+        self.expect(
+            "process continue --forward",
+            substrs=["stop reason = breakpoint {0}.1".format(trigger_bkpt.GetID())],
+        )
+        self.expect(
+            "process continue --reverse",
+            error=True,
+            substrs=["target does not support reverse-continue"],
+        )
+
+    def test_reverse_continue_forward_and_reverse(self):
+        self.connect()
+
+        self.expect(
+            "process continue --forward --reverse",
+            error=True,
+            substrs=["invalid combination of options for the given command"],
+        )
+
+    def connect(self):
+        self.build()
+        exe = self.getBuildArtifact("a.out")
+        target = self.dbg.CreateTarget(exe)
+        self.assertTrue(target, VALID_TARGET)
+
+        main_bkpt = target.BreakpointCreateByName("main", None)
+        self.assertTrue(main_bkpt, VALID_BREAKPOINT)
+
+        process = target.LaunchSimple(None, None, self.get_process_working_directory())
+        self.assertTrue(process, PROCESS_IS_VALID)
+        return target
diff --git a/lldb/test/API/commands/process/reverse-continue/main.c b/lldb/test/API/commands/process/reverse-continue/main.c
new file mode 100644
index 0000000000000..ccec2bb27658d
--- /dev/null
+++ b/lldb/test/API/commands/process/reverse-continue/main.c
@@ -0,0 +1,12 @@
+static void start_recording() {}
+
+static void trigger_breakpoint() {}
+
+static void stop_recording() {}
+
+int main() {
+  start_recording();
+  trigger_breakpoint();
+  stop_recording();
+  return 0;
+}
diff --git a/lldb/test/API/commands/settings/TestSettings.py b/lldb/test/API/commands/settings/TestSettings.py
index b9b66ea953971..f05a285b47d16 100644
--- a/lldb/test/API/commands/settings/TestSettings.py
+++ b/lldb/test/API/commands/settings/TestSettings.py
@@ -1041,6 +1041,9 @@ def test_settings_api(self):
         # Test OptionValueLanguage
         self.verify_setting_value_json("repl-lang", "c++")
 
+        # Test OptionValueEnumeration
+        self.verify_setting_value_json("target.x86-disassembly-flavor", "intel")
+
     def test_global_option(self):
         # This command used to crash the settings because -g was signaled by a
         # NULL execution context (not one with an empty Target...) and in the
diff --git a/lldb/test/API/functionalities/statusline/TestStatusline.py b/lldb/test/API/functionalities/statusline/TestStatusline.py
index dcededdb11e39..da6b4e7c8f320 100644
--- a/lldb/test/API/functionalities/statusline/TestStatusline.py
+++ b/lldb/test/API/functionalities/statusline/TestStatusline.py
@@ -46,8 +46,10 @@ def test(self):
         self.child.expect(re.escape("a.out | main.c:2:11 | bre"))
         self.child.setwinsize(terminal_height, terminal_width)
 
+        # Change the separator.
+        self.expect('set set separator "S "', ["a.out S main.c:2:11"])
+
         # Change the format.
-        self.expect('set set separator "S"')
         self.expect(
             'set set statusline-format "target = {${target.file.basename}} ${separator}"',
             ["target = a.out S"],
diff --git a/lldb/test/API/macosx/riscv32-corefile/Makefile b/lldb/test/API/macosx/riscv32-corefile/Makefile
new file mode 100644
index 0000000000000..04f268758d00c
--- /dev/null
+++ b/lldb/test/API/macosx/riscv32-corefile/Makefile
@@ -0,0 +1,7 @@
+MAKE_DSYM := NO
+CXX_SOURCES := create-empty-riscv-corefile.cpp
+EXE := create-empty-riscv-corefile
+
+all: create-empty-riscv-corefile
+
+include Makefile.rules
diff --git a/lldb/test/API/macosx/riscv32-corefile/TestRV32MachOCorefile.py b/lldb/test/API/macosx/riscv32-corefile/TestRV32MachOCorefile.py
new file mode 100644
index 0000000000000..8d11821d38985
--- /dev/null
+++ b/lldb/test/API/macosx/riscv32-corefile/TestRV32MachOCorefile.py
@@ -0,0 +1,82 @@
+"""Test that all of the GPR registers are read correctly from a riscv32 corefile."""
+
+import os
+import re
+import subprocess
+
+import lldb
+from lldbsuite.test.decorators import *
+from lldbsuite.test.lldbtest import *
+from lldbsuite.test import lldbutil
+
+
+class TestRV32MachOCorefile(TestBase):
+    NO_DEBUG_INFO_TESTCASE = True
+
+    @skipUnlessDarwin
+    def test_riscv32_gpr_corefile_registers(self):
+        self.build()
+        create_corefile = self.getBuildArtifact("create-empty-riscv-corefile")
+        corefile = self.getBuildArtifact("core")
+        call(create_corefile + " " + corefile, shell=True)
+
+        target = self.dbg.CreateTarget("")
+        process = target.LoadCore(corefile)
+
+        process = target.GetProcess()
+        self.assertEqual(process.GetNumThreads(), 1)
+
+        thread = process.GetThreadAtIndex(0)
+        self.assertEqual(thread.GetNumFrames(), 1)
+
+        frame = thread.GetFrameAtIndex(0)
+        gpr_regs = frame.registers.GetValueAtIndex(0)
+
+        self.assertEqual(gpr_regs.GetName(), "General Purpose Registers")
+        self.assertEqual(gpr_regs.GetNumChildren(), 33)
+        regnames = [
+            "zero",
+            "ra",
+            "sp",
+            "gp",
+            "tp",
+            "t0",
+            "t1",
+            "t2",
+            "fp",
+            "s1",
+            "a0",
+            "a1",
+            "a2",
+            "a3",
+            "a4",
+            "a5",
+            "a6",
+            "a7",
+            "s2",
+            "s3",
+            "s4",
+            "s5",
+            "s6",
+            "s7",
+            "s8",
+            "s9",
+            "s10",
+            "s11",
+            "t3",
+            "t4",
+            "t5",
+            "t6",
+            "pc",
+        ]
+
+        idx = 0
+        while idx < len(regnames):
+            self.assertEqual(gpr_regs.GetChildAtIndex(idx).GetName(), regnames[idx])
+            idx = idx + 1
+
+        idx = 0
+        while idx < len(regnames):
+            val = idx | (idx << 8) | (idx << 16) | (idx << 24)
+            self.assertEqual(gpr_regs.GetChildAtIndex(idx).GetValueAsUnsigned(), val)
+            idx = idx + 1
diff --git a/lldb/test/API/macosx/riscv32-corefile/create-empty-riscv-corefile.cpp b/lldb/test/API/macosx/riscv32-corefile/create-empty-riscv-corefile.cpp
new file mode 100644
index 0000000000000..907cca3b70b41
--- /dev/null
+++ b/lldb/test/API/macosx/riscv32-corefile/create-empty-riscv-corefile.cpp
@@ -0,0 +1,116 @@
+#include <inttypes.h>
+#include <mach-o/loader.h>
+#include <mach/thread_status.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <string>
+#include <sys/errno.h>
+#include <uuid/uuid.h>
+#include <vector>
+
+#define CPU_TYPE_RISCV 24
+#define CPU_SUBTYPE_RISCV_ALL 0
+#define RV32_THREAD_STATE 2
+// x0-x31 + pc, all 32-bit
+#define RV32_THREAD_STATE_COUNT 33
+
+union uint32_buf {
+  uint8_t bytebuf[4];
+  uint32_t val;
+};
+
+union uint64_buf {
+  uint8_t bytebuf[8];
+  uint64_t val;
+};
+
+void add_uint64(std::vector<uint8_t> &buf, uint64_t val) {
+  uint64_buf conv;
+  conv.val = val;
+  for (int i = 0; i < 8; i++)
+    buf.push_back(conv.bytebuf[i]);
+}
+
+void add_uint32(std::vector<uint8_t> &buf, uint32_t val) {
+  uint32_buf conv;
+  conv.val = val;
+  for (int i = 0; i < 4; i++)
+    buf.push_back(conv.bytebuf[i]);
+}
+
+std::vector<uint8_t> lc_thread_load_command() {
+  std::vector<uint8_t> data;
+  add_uint32(data, LC_THREAD); // thread_command.cmd
+  add_uint32(data, 4 + 4 + 4 + 4 +
+                       (RV32_THREAD_STATE_COUNT * 4)); // thread_command.cmdsize
+  add_uint32(data, RV32_THREAD_STATE);                 // thread_command.flavor
+  add_uint32(data, RV32_THREAD_STATE_COUNT);           // thread_command.count
+  for (int i = 0; i < RV32_THREAD_STATE_COUNT; i++) {
+    add_uint32(data, i | (i << 8) | (i << 16) | (i << 24));
+  }
+  return data;
+}
+
+int main(int argc, char **argv) {
+  if (argc != 2) {
+    fprintf(stderr,
+            "usage: create-empty-riscv-corefile output-corefile-name\n");
+    exit(1);
+  }
+
+  cpu_type_t cputype = CPU_TYPE_RISCV;
+  cpu_subtype_t cpusubtype = CPU_SUBTYPE_RISCV_ALL;
+
+  // An array of load commands (in the form of byte arrays)
+  std::vector<std::vector<uint8_t>> load_commands;
+
+  // An array of corefile contents (page data, lc_note data, etc)
+  std::vector<uint8_t> payload;
+
+  // First add all the load commands / payload so we can figure out how large
+  // the load commands will actually be.
+  load_commands.push_back(lc_thread_load_command());
+
+  int size_of_load_commands = 0;
+  for (const auto &lc : load_commands)
+    size_of_load_commands += lc.size();
+
+  int header_and_load_cmd_room =
+      sizeof(struct mach_header_64) + size_of_load_commands;
+
+  // Erase the load commands / payload now that we know how much space is
+  // needed, redo it.
+  load_commands.clear();
+  payload.clear();
+
+  load_commands.push_back(lc_thread_load_command());
+
+  struct mach_header mh;
+  mh.magic = MH_MAGIC;
+  mh.cputype = cputype;
+
+  mh.cpusubtype = cpusubtype;
+  mh.filetype = MH_CORE;
+  mh.ncmds = load_commands.size();
+  mh.sizeofcmds = size_of_load_commands;
+  mh.flags = 0;
+
+  FILE *f = fopen(argv[1], "w");
+
+  if (f == nullptr) {
+    fprintf(stderr, "Unable to open file %s for writing\n", argv[1]);
+    exit(1);
+  }
+
+  fwrite(&mh, sizeof(struct mach_header), 1, f);
+
+  for (const auto &lc : load_commands)
+    fwrite(lc.data(), lc.size(), 1, f);
+
+  fseek(f, header_and_load_cmd_room, SEEK_SET);
+
+  fwrite(payload.data(), payload.size(), 1, f);
+
+  fclose(f);
+}
diff --git a/lldb/test/Shell/SymbolFile/DWARF/range-lower-then-low-pc.s b/lldb/test/Shell/SymbolFile/DWARF/range-lower-then-low-pc.s
deleted file mode 100644
index e3cc84db12652..0000000000000
--- a/lldb/test/Shell/SymbolFile/DWARF/range-lower-then-low-pc.s
+++ /dev/null
@@ -1,317 +0,0 @@
-# REQUIRES: x86
-
-# RUN: llvm-mc -triple=x86_64-pc-linux -filetype=obj %s > %t
-# RUN: lldb-test symbols %t &> %t.txt
-# RUN: cat %t.txt | FileCheck %s
-
-# Tests that error is printed correctly when DW_AT_low_pc value is
-# greater then a range entry.
-
-# CHECK: 0x0000006e: adding range [0x0000000000000000-0x000000000000001f)
-# CHECK-SAME: which has a base that is less than the function's low PC 0x0000000000000021.
-# CHECK-SAME: Please file a bug and attach the file at the start of this error message
-
-
-
-# Test was manually modified to change DW_TAG_lexical_block
-# to use DW_AT_ranges, and value lower then DW_AT_low_pc value
-# in DW_TAG_subprogram
-# static int foo(bool b) {
-#   if (b) {
-#    int food = 1;
-#     return food;
-#   }
-#   return 0;
-# }
-# int main() {
-#   return foo(true);
-# }
-	.text
-	.file	"main.cpp"
-	.section	.text.main,"ax",@progbits
-	.globl	main                            # -- Begin function main
-	.p2align	4, 0x90
-	.type	main,@function
-main:                                   # @main
-.Lfunc_begin0:
-	.file	1 "base-lower-then-range-entry" "main.cpp"
-	.loc	1 8 0                           # main.cpp:8:0
-	.cfi_startproc
-# %bb.0:                                # %entry
-	pushq	%rbp
-	.cfi_def_cfa_offset 16
-	.cfi_offset %rbp, -16
-	movq	%rsp, %rbp
-	.cfi_def_cfa_register %rbp
-	subq	$16, %rsp
-	movl	$0, -4(%rbp)
-.Ltmp0:
-	.loc	1 9 10 prologue_end             # main.cpp:9:10
-	movl	$1, %edi
-	callq	_ZL3foob
-	.loc	1 9 3 epilogue_begin is_stmt 0  # main.cpp:9:3
-	addq	$16, %rsp
-	popq	%rbp
-	.cfi_def_cfa %rsp, 8
-	retq
-.Ltmp1:
-.Lfunc_end0:
-	.size	main, .Lfunc_end0-main
-	.cfi_endproc
-                                        # -- End function
-	.section	.text._ZL3foob,"ax",@progbits
-	.p2align	4, 0x90                         # -- Begin function _ZL3foob
-	.type	_ZL3foob,@function
-_ZL3foob:                               # @_ZL3foob
-.Lfunc_begin1:
-	.loc	1 1 0 is_stmt 1                 # main.cpp:1:0
-	.cfi_startproc
-# %bb.0:                                # %entry
-	pushq	%rbp
-	.cfi_def_cfa_offset 16
-	.cfi_offset %rbp, -16
-	movq	%rsp, %rbp
-	.cfi_def_cfa_register %rbp
-	movb	%dil, %al
-	andb	$1, %al
-	movb	%al, -5(%rbp)
-.Ltmp2:
-	.loc	1 2 7 prologue_end              # main.cpp:2:7
-	testb	$1, -5(%rbp)
-	je	.LBB1_2
-# %bb.1:                                # %if.then
-.Ltmp3:
-	.loc	1 3 8                           # main.cpp:3:8
-	movl	$1, -12(%rbp)
-	.loc	1 4 12                          # main.cpp:4:12
-	movl	-12(%rbp), %eax
-	.loc	1 4 5 is_stmt 0                 # main.cpp:4:5
-	movl	%eax, -4(%rbp)
-	jmp	.LBB1_3
-.Ltmp4:
-.LBB1_2:                                # %if.end
-	.loc	1 6 3 is_stmt 1                 # main.cpp:6:3
-	movl	$0, -4(%rbp)
-.LBB1_3:                                # %return
-	.loc	1 7 1                           # main.cpp:7:1
-	movl	-4(%rbp), %eax
-	.loc	1 7 1 epilogue_begin is_stmt 0  # main.cpp:7:1
-	popq	%rbp
-	.cfi_def_cfa %rsp, 8
-	retq
-.Ltmp5:
-.Lfunc_end1:
-	.size	_ZL3foob, .Lfunc_end1-_ZL3foob
-	.cfi_endproc
-                                        # -- End function
-	.section	.debug_abbrev,"",@progbits
-	.byte	1                               # Abbreviation Code
-	.byte	17                              # DW_TAG_compile_unit
-	.byte	1                               # DW_CHILDREN_yes
-	.byte	37                              # DW_AT_producer
-	.byte	14                              # DW_FORM_strp
-	.byte	19                              # DW_AT_language
-	.byte	5                               # DW_FORM_data2
-	.byte	3                               # DW_AT_name
-	.byte	14                              # DW_FORM_strp
-	.byte	16                              # DW_AT_stmt_list
-	.byte	23                              # DW_FORM_sec_offset
-	.byte	27                              # DW_AT_comp_dir
-	.byte	14                              # DW_FORM_strp
-	.byte	17                              # DW_AT_low_pc
-	.byte	1                               # DW_FORM_addr
-	.byte	85                              # DW_AT_ranges
-	.byte	23                              # DW_FORM_sec_offset
-	.byte	0                               # EOM(1)
-	.byte	0                               # EOM(2)
-	.byte	2                               # Abbreviation Code
-	.byte	46                              # DW_TAG_subprogram
-	.byte	0                               # DW_CHILDREN_no
-	.byte	17                              # DW_AT_low_pc
-	.byte	1                               # DW_FORM_addr
-	.byte	18                              # DW_AT_high_pc
-	.byte	6                               # DW_FORM_data4
-	.byte	64                              # DW_AT_frame_base
-	.byte	24                              # DW_FORM_exprloc
-	.byte	3                               # DW_AT_name
-	.byte	14                              # DW_FORM_strp
-	.byte	58                              # DW_AT_decl_file
-	.byte	11                              # DW_FORM_data1
-	.byte	59                              # DW_AT_decl_line
-	.byte	11                              # DW_FORM_data1
-	.byte	73                              # DW_AT_type
-	.byte	19                              # DW_FORM_ref4
-	.byte	63                              # DW_AT_external
-	.byte	25                              # DW_FORM_flag_present
-	.byte	0                               # EOM(1)
-	.byte	0                               # EOM(2)
-	.byte	3                               # Abbreviation Code
-	.byte	46                              # DW_TAG_subprogram
-	.byte	1                               # DW_CHILDREN_yes
-	.byte	17                              # DW_AT_low_pc
-	.byte	1                               # DW_FORM_addr
-	.byte	18                              # DW_AT_high_pc
-	.byte	6                               # DW_FORM_data4
-	.byte	64                              # DW_AT_frame_base
-	.byte	24                              # DW_FORM_exprloc
-	.byte	110                             # DW_AT_linkage_name
-	.byte	14                              # DW_FORM_strp
-	.byte	3                               # DW_AT_name
-	.byte	14                              # DW_FORM_strp
-	.byte	58                              # DW_AT_decl_file
-	.byte	11                              # DW_FORM_data1
-	.byte	59                              # DW_AT_decl_line
-	.byte	11                              # DW_FORM_data1
-	.byte	73                              # DW_AT_type
-	.byte	19                              # DW_FORM_ref4
-	.byte	0                               # EOM(1)
-	.byte	0                               # EOM(2)
-	.byte	4                               # Abbreviation Code
-	.byte	5                               # DW_TAG_formal_parameter
-	.byte	0                               # DW_CHILDREN_no
-	.byte	2                               # DW_AT_location
-	.byte	24                              # DW_FORM_exprloc
-	.byte	3                               # DW_AT_name
-	.byte	14                              # DW_FORM_strp
-	.byte	58                              # DW_AT_decl_file
-	.byte	11                              # DW_FORM_data1
-	.byte	59                              # DW_AT_decl_line
-	.byte	11                              # DW_FORM_data1
-	.byte	73                              # DW_AT_type
-	.byte	19                              # DW_FORM_ref4
-	.byte	0                               # EOM(1)
-	.byte	0                               # EOM(2)
-	.byte	5                               # Abbreviation Code
-	.byte	11                              # DW_TAG_lexical_block
-	.byte	1                               # DW_CHILDREN_yes
-	.byte	85                              # DW_AT_ranges   <------ Manually modified. Replaced low_pc/high)_pc with rangres.
-	.byte	23                              # DW_FORM_sec_offset
-	.byte	0                               # EOM(1)
-	.byte	0                               # EOM(2)
-	.byte	6                               # Abbreviation Code
-	.byte	52                              # DW_TAG_variable
-	.byte	0                               # DW_CHILDREN_no
-	.byte	2                               # DW_AT_location
-	.byte	24                              # DW_FORM_exprloc
-	.byte	3                               # DW_AT_name
-	.byte	14                              # DW_FORM_strp
-	.byte	58                              # DW_AT_decl_file
-	.byte	11                              # DW_FORM_data1
-	.byte	59                              # DW_AT_decl_line
-	.byte	11                              # DW_FORM_data1
-	.byte	73                              # DW_AT_type
-	.byte	19                              # DW_FORM_ref4
-	.byte	0                               # EOM(1)
-	.byte	0                               # EOM(2)
-	.byte	7                               # Abbreviation Code
-	.byte	36                              # DW_TAG_base_type
-	.byte	0                               # DW_CHILDREN_no
-	.byte	3                               # DW_AT_name
-	.byte	14                              # DW_FORM_strp
-	.byte	62                              # DW_AT_encoding
-	.byte	11                              # DW_FORM_data1
-	.byte	11                              # DW_AT_byte_size
-	.byte	11                              # DW_FORM_data1
-	.byte	0                               # EOM(1)
-	.byte	0                               # EOM(2)
-	.byte	0                               # EOM(3)
-	.section	.debug_info,"",@progbits
-.Lcu_begin0:
-	.long	.Ldebug_info_end0-.Ldebug_info_start0 # Length of Unit
-.Ldebug_info_start0:
-	.short	4                               # DWARF version number
-	.long	.debug_abbrev                   # Offset Into Abbrev. Section
-	.byte	8                               # Address Size (in bytes)
-	.byte	1                               # Abbrev [1] 0xb:0x8f DW_TAG_compile_unit
-	.long	.Linfo_string0                  # DW_AT_producer
-	.short	33                              # DW_AT_language
-	.long	.Linfo_string1                  # DW_AT_name
-	.long	.Lline_table_start0             # DW_AT_stmt_list
-	.long	.Linfo_string2                  # DW_AT_comp_dir
-	.quad	0                               # DW_AT_low_pc
-	.long	.Ldebug_ranges0                 # DW_AT_ranges
-	.byte	2                               # Abbrev [2] 0x2a:0x19 DW_TAG_subprogram
-	.quad	.Lfunc_begin0                   # DW_AT_low_pc
-	.long	.Lfunc_end0-.Lfunc_begin0       # DW_AT_high_pc
-	.byte	1                               # DW_AT_frame_base
-	.byte	86
-	.long	.Linfo_string3                  # DW_AT_name
-	.byte	1                               # DW_AT_decl_file
-	.byte	8                               # DW_AT_decl_line
-	.long	138                             # DW_AT_type
-                                        # DW_AT_external
-	.byte	3                               # Abbrev [3] 0x43:0x48 DW_TAG_subprogram
-	.quad	.Lfunc_begin1 + 1               # DW_AT_low_pc
-	.long	.Lfunc_end1-.Lfunc_begin1       # DW_AT_high_pc
-	.byte	1                               # DW_AT_frame_base
-	.byte	86
-	.long	.Linfo_string5                  # DW_AT_linkage_name
-	.long	.Linfo_string6                  # DW_AT_name
-	.byte	1                               # DW_AT_decl_file
-	.byte	1                               # DW_AT_decl_line
-	.long	138                             # DW_AT_type
-	.byte	4                               # Abbrev [4] 0x60:0xe DW_TAG_formal_parameter
-	.byte	2                               # DW_AT_location
-	.byte	145
-	.byte	123
-	.long	.Linfo_string7                  # DW_AT_name
-	.byte	1                               # DW_AT_decl_file
-	.byte	1                               # DW_AT_decl_line
-	.long	138                             # DW_AT_type
-	.byte	5                               # Abbrev [5] 0x6e:0x1c DW_TAG_lexical_block
-	.long	.Ldebug_ranges0                 # DW_AT_ranges  <-- Manually modified replaced low_pc/high_pc to rangres.
-	.byte	6                               # Abbrev [6] 0x7b:0xe DW_TAG_variable
-	.byte	2                               # DW_AT_location
-	.byte	145
-	.byte	116
-	.long	.Linfo_string9                  # DW_AT_name
-	.byte	1                               # DW_AT_decl_file
-	.byte	3                               # DW_AT_decl_line
-	.long	138                             # DW_AT_type
-	.byte	0                               # End Of Children Mark
-	.byte	0                               # End Of Children Mark
-	.byte	7                               # Abbrev [7] 0x8b:0x7 DW_TAG_base_type
-	.long	.Linfo_string4                  # DW_AT_name
-	.byte	5                               # DW_AT_encoding
-	.byte	4                               # DW_AT_byte_size
-	.byte	7                               # Abbrev [7] 0x92:0x7 DW_TAG_base_type
-	.long	.Linfo_string8                  # DW_AT_name
-	.byte	2                               # DW_AT_encoding
-	.byte	1                               # DW_AT_byte_size
-	.byte	0                               # End Of Children Mark
-.Ldebug_info_end0:
-	.section	.debug_ranges,"",@progbits
-.Ldebug_ranges0:
-	.quad	.Lfunc_begin0
-	.quad	.Lfunc_end0
-	.quad	.Lfunc_begin1
-	.quad	.Lfunc_end1
-	.quad	0
-	.quad	0
-	.section	.debug_str,"MS",@progbits,1
-.Linfo_string0:
-	.asciz	"clang version 17.0.0 (https://github.com/llvm/llvm-project.git 73027ae39b1492e5b6033358a13b86d7d1e781ae)" # string offset=0
-.Linfo_string1:
-	.asciz	"main.cpp"                      # string offset=105
-.Linfo_string2:
-	.asciz	"base-lower-then-range-entry" # string offset=114
-.Linfo_string3:
-	.asciz	"main"                          # string offset=179
-.Linfo_string4:
-	.asciz	"int"                           # string offset=184
-.Linfo_string5:
-	.asciz	"_ZL3foob"                      # string offset=188
-.Linfo_string6:
-	.asciz	"foo"                           # string offset=197
-.Linfo_string7:
-	.asciz	"b"                             # string offset=201
-.Linfo_string8:
-	.asciz	"bool"                          # string offset=203
-.Linfo_string9:
-	.asciz	"food"                          # string offset=208
-	.ident	"clang version 17.0.0 (https://github.com/llvm/llvm-project.git 73027ae39b1492e5b6033358a13b86d7d1e781ae)"
-	.section	".note.GNU-stack","",@progbits
-	.addrsig
-	.addrsig_sym _ZL3foob
-	.section	.debug_line,"",@progbits
-.Lline_table_start0:
diff --git a/lldb/test/Shell/SymbolFile/DWARF/x86/discontinuous-inline-function.s b/lldb/test/Shell/SymbolFile/DWARF/x86/discontinuous-inline-function.s
index 399f4e4db5b2f..9afb272b3496f 100644
--- a/lldb/test/Shell/SymbolFile/DWARF/x86/discontinuous-inline-function.s
+++ b/lldb/test/Shell/SymbolFile/DWARF/x86/discontinuous-inline-function.s
@@ -6,28 +6,13 @@
 # RUN: %lldb %t -o "image lookup -v -n look_me_up" -o exit | FileCheck %s
 
 # CHECK:      1 match found in {{.*}}
-# CHECK:      Summary: {{.*}}`foo + 6 [inlined] foo_inl + 1
-# CHECK-NEXT:          {{.*}}`foo + 5
-# CHECK:      Blocks: id = {{.*}}, ranges = [0x00000000-0x00000003)[0x00000004-0x00000008)
-# CHECK-NEXT:         id = {{.*}}, ranges = [0x00000001-0x00000002)[0x00000005-0x00000007), name = "foo_inl"
+# CHECK:      Summary: {{.*}}`foo - 3 [inlined] foo_inl + 1
+# CHECK-NEXT:          {{.*}}`foo - 4
+# CHECK:      Blocks: id = {{.*}}, ranges = [0x00000000-0x00000004)[0x00000005-0x00000008)
+# CHECK-NEXT:         id = {{.*}}, ranges = [0x00000001-0x00000003)[0x00000006-0x00000007), name = "foo_inl"
 
         .text
 
-        .type   foo,@function
-foo:
-        nop
-.Lfoo_inl:
-        nop
-.Lfoo_inl_end:
-        nop
-.Lfoo_end:
-        .size   foo, .Lfoo_end-foo
-
-bar:
-        nop
-.Lbar_end:
-        .size   bar, .Lbar_end-bar
-
         .section        .text.__part1,"ax",@progbits
 foo.__part.1:
         nop
@@ -42,6 +27,21 @@ look_me_up:
         .size   foo.__part.1, .Lfoo.__part.1_end-foo.__part.1
 
 
+bar:
+        nop
+.Lbar_end:
+        .size   bar, .Lbar_end-bar
+
+        .type   foo,@function
+foo:
+        nop
+.Lfoo_inl:
+        nop
+.Lfoo_inl_end:
+        nop
+.Lfoo_end:
+        .size   foo, .Lfoo_end-foo
+
         .section        .debug_abbrev,"",@progbits
         .byte   1                               # Abbreviation Code
         .byte   17                              # DW_TAG_compile_unit
diff --git a/lldb/tools/lldb-dap/DAP.cpp b/lldb/tools/lldb-dap/DAP.cpp
index 597fe3a1e323b..134762711b89d 100644
--- a/lldb/tools/lldb-dap/DAP.cpp
+++ b/lldb/tools/lldb-dap/DAP.cpp
@@ -28,6 +28,7 @@
 #include "lldb/Utility/Status.h"
 #include "lldb/lldb-defines.h"
 #include "lldb/lldb-enumerations.h"
+#include "lldb/lldb-types.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/ScopeExit.h"
@@ -499,6 +500,10 @@ ExceptionBreakpoint *DAP::GetExceptionBPFromStopReason(lldb::SBThread &thread) {
   return exc_bp;
 }
 
+lldb::SBThread DAP::GetLLDBThread(lldb::tid_t tid) {
+  return target.GetProcess().GetThreadByID(tid);
+}
+
 lldb::SBThread DAP::GetLLDBThread(const llvm::json::Object &arguments) {
   auto tid = GetInteger<int64_t>(arguments, "threadId")
                  .value_or(LLDB_INVALID_THREAD_ID);
diff --git a/lldb/tools/lldb-dap/DAP.h b/lldb/tools/lldb-dap/DAP.h
index b79a0d9d0f25c..727e5c00623e8 100644
--- a/lldb/tools/lldb-dap/DAP.h
+++ b/lldb/tools/lldb-dap/DAP.h
@@ -266,6 +266,7 @@ struct DAP {
 
   ExceptionBreakpoint *GetExceptionBPFromStopReason(lldb::SBThread &thread);
 
+  lldb::SBThread GetLLDBThread(lldb::tid_t id);
   lldb::SBThread GetLLDBThread(const llvm::json::Object &arguments);
 
   lldb::SBFrame GetLLDBFrame(const llvm::json::Object &arguments);
diff --git a/lldb/tools/lldb-dap/Handler/CancelRequestHandler.cpp b/lldb/tools/lldb-dap/Handler/CancelRequestHandler.cpp
index f09de13c3ff72..995fe38362f60 100644
--- a/lldb/tools/lldb-dap/Handler/CancelRequestHandler.cpp
+++ b/lldb/tools/lldb-dap/Handler/CancelRequestHandler.cpp
@@ -10,7 +10,7 @@
 #include "Protocol/ProtocolRequests.h"
 #include "llvm/Support/Error.h"
 
-using namespace lldb_dap;
+using namespace llvm;
 using namespace lldb_dap::protocol;
 
 namespace lldb_dap {
@@ -45,12 +45,11 @@ namespace lldb_dap {
 ///
 /// A client cannot assume that progress just got cancelled after sending
 /// the `cancel` request.
-llvm::Expected<CancelResponseBody>
-CancelRequestHandler::Run(const CancelArguments &arguments) const {
+Error CancelRequestHandler::Run(const CancelArguments &arguments) const {
   // Cancel support is built into the DAP::Loop handler for detecting
   // cancellations of pending or inflight requests.
   dap.ClearCancelRequest(arguments);
-  return CancelResponseBody();
+  return Error::success();
 }
 
 } // namespace lldb_dap
diff --git a/lldb/tools/lldb-dap/Handler/DisconnectRequestHandler.cpp b/lldb/tools/lldb-dap/Handler/DisconnectRequestHandler.cpp
index f12fecfb2ff65..81e94c7551836 100644
--- a/lldb/tools/lldb-dap/Handler/DisconnectRequestHandler.cpp
+++ b/lldb/tools/lldb-dap/Handler/DisconnectRequestHandler.cpp
@@ -18,7 +18,7 @@ using namespace lldb_dap::protocol;
 namespace lldb_dap {
 
 /// Disconnect request; value of command field is 'disconnect'.
-Expected<DisconnectResponse> DisconnectRequestHandler::Run(
+Error DisconnectRequestHandler::Run(
     const std::optional<DisconnectArguments> &arguments) const {
   bool terminateDebuggee = dap.is_attach ? false : true;
 
@@ -28,6 +28,6 @@ Expected<DisconnectResponse> DisconnectRequestHandler::Run(
   if (Error error = dap.Disconnect(terminateDebuggee))
     return error;
 
-  return DisconnectResponse();
+  return Error::success();
 }
 } // namespace lldb_dap
diff --git a/lldb/tools/lldb-dap/Handler/NextRequestHandler.cpp b/lldb/tools/lldb-dap/Handler/NextRequestHandler.cpp
index 216e710035cb1..3fa167686d2f9 100644
--- a/lldb/tools/lldb-dap/Handler/NextRequestHandler.cpp
+++ b/lldb/tools/lldb-dap/Handler/NextRequestHandler.cpp
@@ -8,72 +8,38 @@
 
 #include "DAP.h"
 #include "EventHelper.h"
-#include "JSONUtils.h"
+#include "Protocol/ProtocolTypes.h"
 #include "RequestHandler.h"
+#include "llvm/Support/Error.h"
+
+using namespace llvm;
+using namespace lldb;
+using namespace lldb_dap::protocol;
 
 namespace lldb_dap {
 
-// "NextRequest": {
-//   "allOf": [ { "$ref": "#/definitions/Request" }, {
-//     "type": "object",
-//     "description": "Next request; value of command field is 'next'. The
-//                     request starts the debuggee to run again for one step.
-//                     The debug adapter first sends the NextResponse and then
-//                     a StoppedEvent (event type 'step') after the step has
-//                     completed.",
-//     "properties": {
-//       "command": {
-//         "type": "string",
-//         "enum": [ "next" ]
-//       },
-//       "arguments": {
-//         "$ref": "#/definitions/NextArguments"
-//       }
-//     },
-//     "required": [ "command", "arguments"  ]
-//   }]
-// },
-// "NextArguments": {
-//   "type": "object",
-//   "description": "Arguments for 'next' request.",
-//   "properties": {
-//     "threadId": {
-//       "type": "integer",
-//       "description": "Execute 'next' for this thread."
-//     },
-//     "granularity": {
-//       "$ref": "#/definitions/SteppingGranularity",
-//       "description": "Stepping granularity. If no granularity is specified, a
-//                       granularity of `statement` is assumed."
-//     }
-//   },
-//   "required": [ "threadId" ]
-// },
-// "NextResponse": {
-//   "allOf": [ { "$ref": "#/definitions/Response" }, {
-//     "type": "object",
-//     "description": "Response to 'next' request. This is just an
-//                     acknowledgement, so no body field is required."
-//   }]
-// }
-void NextRequestHandler::operator()(const llvm::json::Object &request) const {
-  llvm::json::Object response;
-  FillResponse(request, response);
-  const auto *arguments = request.getObject("arguments");
-  lldb::SBThread thread = dap.GetLLDBThread(*arguments);
-  if (thread.IsValid()) {
-    // Remember the thread ID that caused the resume so we can set the
-    // "threadCausedFocus" boolean value in the "stopped" events.
-    dap.focus_tid = thread.GetThreadID();
-    if (HasInstructionGranularity(*arguments)) {
-      thread.StepInstruction(/*step_over=*/true);
-    } else {
-      thread.StepOver();
-    }
+/// The request executes one step (in the given granularity) for the specified
+/// thread and allows all other threads to run freely by resuming them. If the
+/// debug adapter supports single thread execution (see capability
+/// `supportsSingleThreadExecutionRequests`), setting the `singleThread`
+/// argument to true prevents other suspended threads from resuming. The debug
+/// adapter first sends the response and then a `stopped` event (with reason
+/// `step`) after the step has completed.
+Error NextRequestHandler::Run(const NextArguments &args) const {
+  lldb::SBThread thread = dap.GetLLDBThread(args.threadId);
+  if (!thread.IsValid())
+    return make_error<DAPError>("invalid thread");
+
+  // Remember the thread ID that caused the resume so we can set the
+  // "threadCausedFocus" boolean value in the "stopped" events.
+  dap.focus_tid = thread.GetThreadID();
+  if (args.granularity == eSteppingGranularityInstruction) {
+    thread.StepInstruction(/*step_over=*/true);
   } else {
-    response["success"] = llvm::json::Value(false);
+    thread.StepOver(args.singleThread ? eOnlyThisThread : eOnlyDuringStepping);
   }
-  dap.SendJSON(llvm::json::Value(std::move(response)));
+
+  return Error::success();
 }
 
 } // namespace lldb_dap
diff --git a/lldb/tools/lldb-dap/Handler/RequestHandler.cpp b/lldb/tools/lldb-dap/Handler/RequestHandler.cpp
index 3520dc2c71a55..be9273963654a 100644
--- a/lldb/tools/lldb-dap/Handler/RequestHandler.cpp
+++ b/lldb/tools/lldb-dap/Handler/RequestHandler.cpp
@@ -14,6 +14,7 @@
 #include "Protocol/ProtocolBase.h"
 #include "RunInTerminal.h"
 #include "llvm/Support/Error.h"
+#include <mutex>
 
 #if !defined(_WIN32)
 #include <unistd.h>
@@ -180,6 +181,9 @@ void BaseRequestHandler::Run(const Request &request) {
     return;
   }
 
+  lldb::SBMutex lock = dap.GetAPIMutex();
+  std::lock_guard<lldb::SBMutex> guard(lock);
+
   // FIXME: After all the requests have migrated from LegacyRequestHandler >
   // RequestHandler<> we should be able to move this into
   // RequestHandler<>::operator().
diff --git a/lldb/tools/lldb-dap/Handler/RequestHandler.h b/lldb/tools/lldb-dap/Handler/RequestHandler.h
index 7e56c258ad78a..e13f7a3749e00 100644
--- a/lldb/tools/lldb-dap/Handler/RequestHandler.h
+++ b/lldb/tools/lldb-dap/Handler/RequestHandler.h
@@ -94,10 +94,10 @@ class LegacyRequestHandler : public BaseRequestHandler {
 /// Base class for handling DAP requests. Handlers should declare their
 /// arguments and response body types like:
 ///
-/// class MyRequestHandler : public RequestHandler<Arguments, ResponseBody> {
+/// class MyRequestHandler : public RequestHandler<Arguments, Response> {
 ///   ....
 /// };
-template <typename Args, typename Body>
+template <typename Args, typename Resp>
 class RequestHandler : public BaseRequestHandler {
   using BaseRequestHandler::BaseRequestHandler;
 
@@ -128,41 +128,29 @@ class RequestHandler : public BaseRequestHandler {
          << "': " << llvm::toString(root.getError()) << "\n";
       root.printErrorContext(*request.arguments, OS);
 
-      protocol::ErrorMessage error_message;
-      error_message.format = parse_failure;
-
-      protocol::ErrorResponseBody body;
-      body.error = error_message;
-
       response.success = false;
-      response.body = std::move(body);
+      response.body = ToResponse(llvm::make_error<DAPError>(parse_failure));
 
       dap.Send(response);
       return;
     }
 
-    llvm::Expected<Body> body = Run(arguments);
-    if (auto Err = body.takeError()) {
-      protocol::ErrorMessage error_message;
-      error_message.sendTelemetry = false;
-      if (llvm::Error unhandled = llvm::handleErrors(
-              std::move(Err), [&](const DAPError &E) -> llvm::Error {
-                error_message.format = E.getMessage();
-                error_message.showUser = E.getShowUser();
-                error_message.id = E.convertToErrorCode().value();
-                error_message.url = E.getURL();
-                error_message.urlLabel = E.getURLLabel();
-                return llvm::Error::success();
-              }))
-        error_message.format = llvm::toString(std::move(unhandled));
-      protocol::ErrorResponseBody body;
-      body.error = error_message;
-      response.success = false;
-      response.body = std::move(body);
+    if constexpr (std::is_same_v<Resp, llvm::Error>) {
+      if (llvm::Error err = Run(arguments)) {
+        response.success = false;
+        response.body = ToResponse(std::move(err));
+      } else {
+        response.success = true;
+      }
     } else {
-      response.success = true;
-      if constexpr (!std::is_same_v<Body, std::monostate>)
+      Resp body = Run(arguments);
+      if (llvm::Error err = body.takeError()) {
+        response.success = false;
+        response.body = ToResponse(std::move(err));
+      } else {
+        response.success = true;
         response.body = std::move(*body);
+      }
     }
 
     // Mark the request as 'cancelled' if the debugger was interrupted while
@@ -177,7 +165,25 @@ class RequestHandler : public BaseRequestHandler {
     dap.Send(response);
   };
 
-  virtual llvm::Expected<Body> Run(const Args &) const = 0;
+  virtual Resp Run(const Args &) const = 0;
+
+  protocol::ErrorResponseBody ToResponse(llvm::Error err) const {
+    protocol::ErrorMessage error_message;
+    error_message.sendTelemetry = false;
+    if (llvm::Error unhandled = llvm::handleErrors(
+            std::move(err), [&](const DAPError &E) -> llvm::Error {
+              error_message.format = E.getMessage();
+              error_message.showUser = E.getShowUser();
+              error_message.id = E.convertToErrorCode().value();
+              error_message.url = E.getURL();
+              error_message.urlLabel = E.getURLLabel();
+              return llvm::Error::success();
+            }))
+      error_message.format = llvm::toString(std::move(unhandled));
+    protocol::ErrorResponseBody body;
+    body.error = error_message;
+    return body;
+  }
 };
 
 class AttachRequestHandler : public LegacyRequestHandler {
@@ -233,7 +239,7 @@ class DisconnectRequestHandler
   FeatureSet GetSupportedFeatures() const override {
     return {protocol::eAdapterFeatureTerminateDebuggee};
   }
-  llvm::Expected<protocol::DisconnectResponse>
+  llvm::Error
   Run(const std::optional<protocol::DisconnectArguments> &args) const override;
 };
 
@@ -259,7 +265,7 @@ class ExceptionInfoRequestHandler : public LegacyRequestHandler {
 
 class InitializeRequestHandler
     : public RequestHandler<protocol::InitializeRequestArguments,
-                            protocol::InitializeResponseBody> {
+                            llvm::Expected<protocol::InitializeResponseBody>> {
 public:
   using RequestHandler::RequestHandler;
   static llvm::StringLiteral GetCommand() { return "initialize"; }
@@ -284,18 +290,20 @@ class RestartRequestHandler : public LegacyRequestHandler {
   void operator()(const llvm::json::Object &request) const override;
 };
 
-class NextRequestHandler : public LegacyRequestHandler {
+class NextRequestHandler
+    : public RequestHandler<protocol::NextArguments, protocol::NextResponse> {
 public:
-  using LegacyRequestHandler::LegacyRequestHandler;
+  using RequestHandler::RequestHandler;
   static llvm::StringLiteral GetCommand() { return "next"; }
-  void operator()(const llvm::json::Object &request) const override;
+  llvm::Error Run(const protocol::NextArguments &args) const override;
 };
 
-class StepInRequestHandler : public LegacyRequestHandler {
+class StepInRequestHandler : public RequestHandler<protocol::StepInArguments,
+                                                   protocol::StepInResponse> {
 public:
-  using LegacyRequestHandler::LegacyRequestHandler;
+  using RequestHandler::RequestHandler;
   static llvm::StringLiteral GetCommand() { return "stepIn"; }
-  void operator()(const llvm::json::Object &request) const override;
+  llvm::Error Run(const protocol::StepInArguments &args) const override;
 };
 
 class StepInTargetsRequestHandler : public LegacyRequestHandler {
@@ -418,7 +426,7 @@ class SetVariableRequestHandler : public LegacyRequestHandler {
 
 class SourceRequestHandler
     : public RequestHandler<protocol::SourceArguments,
-                            protocol::SourceResponseBody> {
+                            llvm::Expected<protocol::SourceResponseBody>> {
 public:
   using RequestHandler::RequestHandler;
   static llvm::StringLiteral GetCommand() { return "source"; }
@@ -486,8 +494,7 @@ class CancelRequestHandler
   FeatureSet GetSupportedFeatures() const override {
     return {protocol::eAdapterFeatureCancelRequest};
   }
-  llvm::Expected<protocol::CancelResponseBody>
-  Run(const protocol::CancelArguments &args) const override;
+  llvm::Error Run(const protocol::CancelArguments &args) const override;
 };
 
 /// A request used in testing to get the details on all breakpoints that are
diff --git a/lldb/tools/lldb-dap/Handler/SourceRequestHandler.cpp b/lldb/tools/lldb-dap/Handler/SourceRequestHandler.cpp
index 1a7a13d9f267a..327198bab0395 100644
--- a/lldb/tools/lldb-dap/Handler/SourceRequestHandler.cpp
+++ b/lldb/tools/lldb-dap/Handler/SourceRequestHandler.cpp
@@ -11,6 +11,7 @@
 #include "LLDBUtils.h"
 #include "Protocol/ProtocolRequests.h"
 #include "Protocol/ProtocolTypes.h"
+#include "lldb/API/SBExecutionContext.h"
 #include "lldb/API/SBFrame.h"
 #include "lldb/API/SBInstructionList.h"
 #include "lldb/API/SBProcess.h"
@@ -43,7 +44,8 @@ SourceRequestHandler::Run(const protocol::SourceArguments &args) const {
 
   lldb::SBInstructionList insts = frame.GetSymbol().GetInstructions(dap.target);
   lldb::SBStream stream;
-  insts.GetDescription(stream);
+  lldb::SBExecutionContext exe_ctx(frame);
+  insts.GetDescription(stream, exe_ctx);
 
   return protocol::SourceResponseBody{/*content=*/stream.GetData(),
                                       /*mimeType=*/"text/x-lldb.disassembly"};
diff --git a/lldb/tools/lldb-dap/Handler/StepInRequestHandler.cpp b/lldb/tools/lldb-dap/Handler/StepInRequestHandler.cpp
index 9d8d75b359447..15f242a9e18ff 100644
--- a/lldb/tools/lldb-dap/Handler/StepInRequestHandler.cpp
+++ b/lldb/tools/lldb-dap/Handler/StepInRequestHandler.cpp
@@ -8,91 +8,50 @@
 
 #include "DAP.h"
 #include "EventHelper.h"
-#include "JSONUtils.h"
+#include "Protocol/ProtocolRequests.h"
+#include "Protocol/ProtocolTypes.h"
 #include "RequestHandler.h"
 
+using namespace llvm;
+using namespace lldb;
+using namespace lldb_dap::protocol;
+
 namespace lldb_dap {
 
-// "StepInRequest": {
-//   "allOf": [ { "$ref": "#/definitions/Request" }, {
-//     "type": "object",
-//     "description": "StepIn request; value of command field is 'stepIn'. The
-//     request starts the debuggee to step into a function/method if possible.
-//     If it cannot step into a target, 'stepIn' behaves like 'next'. The debug
-//     adapter first sends the StepInResponse and then a StoppedEvent (event
-//     type 'step') after the step has completed. If there are multiple
-//     function/method calls (or other targets) on the source line, the optional
-//     argument 'targetId' can be used to control into which target the 'stepIn'
-//     should occur. The list of possible targets for a given source line can be
-//     retrieved via the 'stepInTargets' request.", "properties": {
-//       "command": {
-//         "type": "string",
-//         "enum": [ "stepIn" ]
-//       },
-//       "arguments": {
-//         "$ref": "#/definitions/StepInArguments"
-//       }
-//     },
-//     "required": [ "command", "arguments"  ]
-//   }]
-// },
-// "StepInArguments": {
-//   "type": "object",
-//   "description": "Arguments for 'stepIn' request.",
-//   "properties": {
-//     "threadId": {
-//       "type": "integer",
-//       "description": "Execute 'stepIn' for this thread."
-//     },
-//     "targetId": {
-//       "type": "integer",
-//       "description": "Optional id of the target to step into."
-//     },
-//     "granularity": {
-//       "$ref": "#/definitions/SteppingGranularity",
-//       "description": "Stepping granularity. If no granularity is specified, a
-//                       granularity of `statement` is assumed."
-//     }
-//   },
-//   "required": [ "threadId" ]
-// },
-// "StepInResponse": {
-//   "allOf": [ { "$ref": "#/definitions/Response" }, {
-//     "type": "object",
-//     "description": "Response to 'stepIn' request. This is just an
-//     acknowledgement, so no body field is required."
-//   }]
-// }
-void StepInRequestHandler::operator()(const llvm::json::Object &request) const {
-  llvm::json::Object response;
-  FillResponse(request, response);
-  const auto *arguments = request.getObject("arguments");
+// The request resumes the given thread to step into a function/method and
+// allows all other threads to run freely by resuming them. If the debug adapter
+// supports single thread execution (see capability
+// `supportsSingleThreadExecutionRequests`), setting the `singleThread` argument
+// to true prevents other suspended threads from resuming. If the request cannot
+// step into a target, `stepIn` behaves like the `next` request. The debug
+// adapter first sends the response and then a `stopped` event (with reason
+// `step`) after the step has completed. If there are multiple function/method
+// calls (or other targets) on the source line, the argument `targetId` can be
+// used to control into which target the `stepIn` should occur. The list of
+// possible targets for a given source line can be retrieved via the
+// `stepInTargets` request.
+Error StepInRequestHandler::Run(const StepInArguments &args) const {
+  SBThread thread = dap.GetLLDBThread(args.threadId);
+  if (!thread.IsValid())
+    return make_error<DAPError>("invalid thread");
+
+  // Remember the thread ID that caused the resume so we can set the
+  // "threadCausedFocus" boolean value in the "stopped" events.
+  dap.focus_tid = thread.GetThreadID();
+
+  if (args.granularity == eSteppingGranularityInstruction) {
+    thread.StepInstruction(/*step_over=*/false);
+    return Error::success();
+  }
 
   std::string step_in_target;
-  const auto target_id =
-      GetInteger<uint64_t>(arguments, "targetId").value_or(0);
-  auto it = dap.step_in_targets.find(target_id);
+  auto it = dap.step_in_targets.find(args.targetId.value_or(0));
   if (it != dap.step_in_targets.end())
     step_in_target = it->second;
 
-  const bool single_thread =
-      GetBoolean(arguments, "singleThread").value_or(false);
-  lldb::RunMode run_mode =
-      single_thread ? lldb::eOnlyThisThread : lldb::eOnlyDuringStepping;
-  lldb::SBThread thread = dap.GetLLDBThread(*arguments);
-  if (thread.IsValid()) {
-    // Remember the thread ID that caused the resume so we can set the
-    // "threadCausedFocus" boolean value in the "stopped" events.
-    dap.focus_tid = thread.GetThreadID();
-    if (HasInstructionGranularity(*arguments)) {
-      thread.StepInstruction(/*step_over=*/false);
-    } else {
-      thread.StepInto(step_in_target.c_str(), run_mode);
-    }
-  } else {
-    response["success"] = llvm::json::Value(false);
-  }
-  dap.SendJSON(llvm::json::Value(std::move(response)));
+  RunMode run_mode = args.singleThread ? eOnlyThisThread : eOnlyDuringStepping;
+  thread.StepInto(step_in_target.c_str(), run_mode);
+  return Error::success();
 }
 
 } // namespace lldb_dap
diff --git a/lldb/tools/lldb-dap/Protocol/ProtocolBase.h b/lldb/tools/lldb-dap/Protocol/ProtocolBase.h
index 2c647610de11c..bad0e886d94d2 100644
--- a/lldb/tools/lldb-dap/Protocol/ProtocolBase.h
+++ b/lldb/tools/lldb-dap/Protocol/ProtocolBase.h
@@ -149,7 +149,7 @@ struct ErrorResponseBody {
 llvm::json::Value toJSON(const ErrorResponseBody &);
 
 /// This is just an acknowledgement, so no body field is required.
-using VoidResponse = std::monostate;
+using VoidResponse = llvm::Error;
 
 } // namespace lldb_dap::protocol
 
diff --git a/lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp b/lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
index 3523f8ac87ec9..ee7c653ee9f1b 100644
--- a/lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
+++ b/lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
@@ -7,7 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 #include "Protocol/ProtocolRequests.h"
-#include "DAP.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/Support/JSON.h"
@@ -114,4 +113,21 @@ json::Value toJSON(const SourceResponseBody &SA) {
   return std::move(Result);
 }
 
+bool fromJSON(const llvm::json::Value &Params, NextArguments &NA,
+              llvm::json::Path P) {
+  json::ObjectMapper OM(Params, P);
+  return OM && OM.map("threadId", NA.threadId) &&
+         OM.mapOptional("singleThread", NA.singleThread) &&
+         OM.mapOptional("granularity", NA.granularity);
+}
+
+bool fromJSON(const llvm::json::Value &Params, StepInArguments &SIA,
+              llvm::json::Path P) {
+  json::ObjectMapper OM(Params, P);
+  return OM && OM.map("threadId", SIA.threadId) &&
+         OM.map("targetId", SIA.targetId) &&
+         OM.mapOptional("singleThread", SIA.singleThread) &&
+         OM.mapOptional("granularity", SIA.granularity);
+}
+
 } // namespace lldb_dap::protocol
diff --git a/lldb/tools/lldb-dap/Protocol/ProtocolRequests.h b/lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
index 6623dfa0db05c..50c16c15cef32 100644
--- a/lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
+++ b/lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
@@ -22,6 +22,7 @@
 
 #include "Protocol/ProtocolBase.h"
 #include "Protocol/ProtocolTypes.h"
+#include "lldb/lldb-defines.h"
 #include "llvm/ADT/DenseSet.h"
 #include "llvm/Support/JSON.h"
 #include <cstdint>
@@ -236,6 +237,47 @@ struct SourceResponseBody {
 };
 llvm::json::Value toJSON(const SourceResponseBody &);
 
+/// Arguments for `next` request.
+struct NextArguments {
+  /// Specifies the thread for which to resume execution for one step (of the
+  /// given granularity).
+  uint64_t threadId = LLDB_INVALID_THREAD_ID;
+
+  /// If this flag is true, all other suspended threads are not resumed.
+  bool singleThread = false;
+
+  /// Stepping granularity. If no granularity is specified, a granularity of
+  /// `statement` is assumed.
+  SteppingGranularity granularity = eSteppingGranularityStatement;
+};
+bool fromJSON(const llvm::json::Value &, NextArguments &, llvm::json::Path);
+
+/// Response to `next` request. This is just an acknowledgement, so no
+/// body field is required.
+using NextResponse = VoidResponse;
+
+/// Arguments for `stepIn` request.
+struct StepInArguments {
+  /// Specifies the thread for which to resume execution for one step-into (of
+  /// the given granularity).
+  uint64_t threadId = LLDB_INVALID_THREAD_ID;
+
+  /// If this flag is true, all other suspended threads are not resumed.
+  bool singleThread = false;
+
+  /// Id of the target to step into.
+  std::optional<uint64_t> targetId;
+
+  /// Stepping granularity. If no granularity is specified, a granularity of
+  /// `statement` is assumed.
+  SteppingGranularity granularity = eSteppingGranularityStatement;
+};
+bool fromJSON(const llvm::json::Value &, StepInArguments &, llvm::json::Path);
+
+/// Response to `stepIn` request. This is just an acknowledgement, so no
+/// body field is required.
+using StepInResponse = VoidResponse;
+
 } // namespace lldb_dap::protocol
 
 #endif
diff --git a/lldb/tools/lldb-dap/Protocol/ProtocolTypes.cpp b/lldb/tools/lldb-dap/Protocol/ProtocolTypes.cpp
index 4d1e90215bbb4..e64998c4ca488 100644
--- a/lldb/tools/lldb-dap/Protocol/ProtocolTypes.cpp
+++ b/lldb/tools/lldb-dap/Protocol/ProtocolTypes.cpp
@@ -233,4 +233,25 @@ json::Value toJSON(const Capabilities &C) {
   return result;
 }
 
+bool fromJSON(const llvm::json::Value &Params, SteppingGranularity &SG,
+              llvm::json::Path P) {
+  auto raw_granularity = Params.getAsString();
+  if (!raw_granularity) {
+    P.report("expected a string");
+    return false;
+  }
+  std::optional<SteppingGranularity> granularity =
+      StringSwitch<std::optional<SteppingGranularity>>(*raw_granularity)
+          .Case("statement", eSteppingGranularityStatement)
+          .Case("line", eSteppingGranularityLine)
+          .Case("instruction", eSteppingGranularityInstruction)
+          .Default(std::nullopt);
+  if (!granularity) {
+    P.report("unexpected value");
+    return false;
+  }
+  SG = *granularity;
+  return true;
+}
+
 } // namespace lldb_dap::protocol
diff --git a/lldb/tools/lldb-dap/Protocol/ProtocolTypes.h b/lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
index 8f38c524ea649..54941f24efbd9 100644
--- a/lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
+++ b/lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
@@ -303,6 +303,25 @@ struct Source {
 };
 bool fromJSON(const llvm::json::Value &, Source &, llvm::json::Path);
 
+/// The granularity of one `step` in the stepping requests `next`, `stepIn`,
+/// `stepOut` and `stepBack`.
+enum SteppingGranularity : unsigned {
+  /// The step should allow the program to run until the current statement has
+  /// finished executing. The meaning of a statement is determined by the
+  /// adapter and it may be considered equivalent to a line. For example
+  /// `for(int i = 0; i < 10; i++)` could be considered to have 3 statements
+  /// `int i = 0`, `i < 10`, and `i++`.
+  eSteppingGranularityStatement,
+  /// The step should allow the program to run until the current source line has
+  /// executed.
+  eSteppingGranularityLine,
+  /// The step should allow one instruction to execute (e.g. one x86
+  /// instruction).
+  eSteppingGranularityInstruction,
+};
+bool fromJSON(const llvm::json::Value &, SteppingGranularity &,
+              llvm::json::Path);
+
 } // namespace lldb_dap::protocol
 
 #endif
diff --git a/lldb/tools/lldb-dap/Transport.cpp b/lldb/tools/lldb-dap/Transport.cpp
index ffd0c49f1770b..4e322e9ff1358 100644
--- a/lldb/tools/lldb-dap/Transport.cpp
+++ b/lldb/tools/lldb-dap/Transport.cpp
@@ -137,7 +137,8 @@ Expected<Message> Transport::Read(const std::chrono::microseconds &timeout) {
 
   DAP_LOG(m_log, "--> ({0}) {1}", m_client_name, *raw_json);
 
-  return json::parse<Message>(*raw_json);
+  return json::parse<Message>(/*JSON=*/*raw_json,
+                              /*RootName=*/"protocol_message");
 }
 
 Error Transport::Write(const Message &message) {
diff --git a/lldb/unittests/SymbolFile/DWARF/DWARFIndexCachingTest.cpp b/lldb/unittests/SymbolFile/DWARF/DWARFIndexCachingTest.cpp
index c5f25780a18f3..31cf9494eefc0 100644
--- a/lldb/unittests/SymbolFile/DWARF/DWARFIndexCachingTest.cpp
+++ b/lldb/unittests/SymbolFile/DWARF/DWARFIndexCachingTest.cpp
@@ -8,7 +8,7 @@
 
 #include "Plugins/SymbolFile/DWARF/DIERef.h"
 #include "Plugins/SymbolFile/DWARF/DWARFDIE.h"
-#include "Plugins/SymbolFile/DWARF/ManualDWARFIndex.h"
+#include "Plugins/SymbolFile/DWARF/ManualDWARFIndexSet.h"
 #include "Plugins/SymbolFile/DWARF/NameToDIE.h"
 #include "TestingSupport/Symbol/YAMLModuleTester.h"
 #include "lldb/Core/DataFileCache.h"
@@ -109,27 +109,25 @@ TEST(DWARFIndexCachingTest, NameToDIEEncodeDecode) {
   EncodeDecode(map);
 }
 
-static void EncodeDecode(const ManualDWARFIndex::IndexSet &object,
+static void EncodeDecode(const IndexSet<NameToDIE> &object,
                          ByteOrder byte_order) {
   const uint8_t addr_size = 8;
   DataEncoder encoder(byte_order, addr_size);
   DataEncoder strtab_encoder(byte_order, addr_size);
-  object.Encode(encoder);
+  EncodeIndexSet(object, encoder);
   llvm::ArrayRef<uint8_t> bytes = encoder.GetData();
   DataExtractor data(bytes.data(), bytes.size(), byte_order, addr_size);
-  ManualDWARFIndex::IndexSet decoded_object;
   offset_t data_offset = 0;
-  decoded_object.Decode(data, &data_offset);
-  EXPECT_TRUE(object == decoded_object);
+  EXPECT_EQ(DecodeIndexSet(data, &data_offset), object);
 }
 
-static void EncodeDecode(const ManualDWARFIndex::IndexSet &object) {
+static void EncodeDecode(const IndexSet<NameToDIE> &object) {
   EncodeDecode(object, eByteOrderLittle);
   EncodeDecode(object, eByteOrderBig);
 }
 
 TEST(DWARFIndexCachingTest, ManualDWARFIndexIndexSetEncodeDecode) {
-  ManualDWARFIndex::IndexSet set;
+  IndexSet<NameToDIE> set;
   // Make sure empty IndexSet can be encoded and decoded correctly
   EncodeDecode(set);
 
diff --git a/lldb/unittests/Utility/ArchSpecTest.cpp b/lldb/unittests/Utility/ArchSpecTest.cpp
index 2c78629849c64..3bf1c3f81876f 100644
--- a/lldb/unittests/Utility/ArchSpecTest.cpp
+++ b/lldb/unittests/Utility/ArchSpecTest.cpp
@@ -113,6 +113,14 @@ TEST(ArchSpecTest, TestSetTriple) {
                   .consume_front("powerpc-apple-darwin"));
   EXPECT_EQ(ArchSpec::eCore_ppc_ppc970, AS.GetCore());
 
+  AS = ArchSpec();
+  EXPECT_TRUE(AS.SetTriple("24-0-apple-unknown"));
+  EXPECT_EQ(uint32_t(llvm::MachO::CPU_TYPE_RISCV), AS.GetMachOCPUType());
+  EXPECT_EQ(0u, AS.GetMachOCPUSubType());
+  EXPECT_TRUE(llvm::StringRef(AS.GetTriple().str())
+                  .consume_front("riscv32-apple-unknown"));
+  EXPECT_EQ(ArchSpec::eCore_riscv32, AS.GetCore());
+
   AS = ArchSpec();
   EXPECT_TRUE(AS.SetTriple("i686-pc-windows"));
   EXPECT_EQ(llvm::Triple::x86, AS.GetTriple().getArch());
diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt
index 693cb085b8e2f..d47ac3ccffd05 100644
--- a/llvm/CMakeLists.txt
+++ b/llvm/CMakeLists.txt
@@ -273,7 +273,7 @@ if(LLVM_CCACHE_BUILD)
   if(CCACHE_PROGRAM)
     set(LLVM_CCACHE_MAXSIZE "" CACHE STRING "Size of ccache")
     set(LLVM_CCACHE_DIR "" CACHE STRING "Directory to keep ccached data")
-    set(LLVM_CCACHE_PARAMS "CCACHE_CPP2=yes CCACHE_HASHDIR=yes"
+    set(LLVM_CCACHE_PARAMS "CCACHE_CPP2=yes CCACHE_HASHDIR=yes CCACHE_SLOPPINESS=pch_defines,time_macros"
         CACHE STRING "Parameters to pass through to ccache")
 
     if(NOT CMAKE_SYSTEM_NAME MATCHES "Windows")
@@ -287,7 +287,7 @@ if(LLVM_CCACHE_BUILD)
       set_property(GLOBAL PROPERTY RULE_LAUNCH_COMPILE ${CCACHE_PROGRAM})
     else()
       if(LLVM_CCACHE_MAXSIZE OR LLVM_CCACHE_DIR OR
-         NOT LLVM_CCACHE_PARAMS MATCHES "CCACHE_CPP2=yes CCACHE_HASHDIR=yes")
+         NOT LLVM_CCACHE_PARAMS MATCHES "CCACHE_CPP2=yes CCACHE_HASHDIR=yes CCACHE_SLOPPINESS=pch_defines,time_macros")
         message(FATAL_ERROR "Ccache configuration through CMake is not supported on Windows. Please use environment variables.")
       endif()
       # RULE_LAUNCH_COMPILE should work with Ninja but currently has issues
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index cc4fd38944ff6..298b716801da7 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -168,6 +168,8 @@ Changes to the RISC-V Backend
   and branch and linker relaxation. This can be disabled with ``.option noexact``,
   which is also the default.
 * `-mcpu=xiangshan-kunminghu` was added.
+* `-mcpu=andes-n45` and `-mcpu=andes-nx45` were added.
+* `-mcpu=andes-a45` and `-mcpu=andes-ax45` were added.
 
 Changes to the WebAssembly Backend
 ----------------------------------
@@ -234,6 +236,10 @@ Changes to LLDB
 * The `min-gdbserver-port` and `max-gdbserver-port` options have been removed
   from `lldb-server`'s platform mode. Since the changes to `lldb-server`'s port
   handling in LLDB 20, these options have had no effect.
+* LLDB now supports `process continue --reverse` when used with debug servers
+  supporting reverse execution, such as [rr](https://rr-project.org).
+  When using reverse execution, `process continue --forward` returns to the
+  forward execution.
 
 ### Changes to lldb-dap
 
diff --git a/llvm/docs/SPIRVUsage.rst b/llvm/docs/SPIRVUsage.rst
index 406dfbea20b73..6ff8034cac00c 100644
--- a/llvm/docs/SPIRVUsage.rst
+++ b/llvm/docs/SPIRVUsage.rst
@@ -211,6 +211,8 @@ list of supported SPIR-V extensions, sorted alphabetically by their extension na
      - Adds the ability to specify the maximum error for floating-point operations.
    * - ``SPV_INTEL_ternary_bitwise_function``
      - Adds a bitwise instruction on three operands and a look-up table index for specifying the bitwise operation to perform. 
+   * - ``SPV_INTEL_subgroup_matrix_multiply_accumulate``
+     - Adds an instruction to compute the matrix product of an M x K matrix with a K x N matrix and then add an M x N matrix. 
 
 To enable multiple extensions, list them separated by comma. For example, to enable support for atomic operations on floating-point numbers and arbitrary precision integers, use:
 
diff --git a/llvm/include/llvm/Analysis/DXILResource.h b/llvm/include/llvm/Analysis/DXILResource.h
index 96e90e563e230..9f0b5f18d127d 100644
--- a/llvm/include/llvm/Analysis/DXILResource.h
+++ b/llvm/include/llvm/Analysis/DXILResource.h
@@ -196,6 +196,24 @@ class SamplerExtType : public TargetExtType {
   }
 };
 
+class AnyResourceExtType : public TargetExtType {
+public:
+  AnyResourceExtType() = delete;
+  AnyResourceExtType(const AnyResourceExtType &) = delete;
+  AnyResourceExtType &operator=(const AnyResourceExtType &) = delete;
+
+  static bool classof(const TargetExtType *T) {
+    return isa<RawBufferExtType>(T) || isa<TypedBufferExtType>(T) ||
+           isa<TextureExtType>(T) || isa<MSTextureExtType>(T) ||
+           isa<FeedbackTextureExtType>(T) || isa<CBufferExtType>(T) ||
+           isa<SamplerExtType>(T);
+  }
+
+  static bool classof(const Type *T) {
+    return isa<TargetExtType>(T) && classof(cast<TargetExtType>(T));
+  }
+};
+
 /// The dx.Layout target extension type
 ///
 /// `target("dx.Layout", <Type>, <size>, [offsets...])`
diff --git a/llvm/include/llvm/BinaryFormat/MachO.h b/llvm/include/llvm/BinaryFormat/MachO.h
index 83aaf19c71e50..5afe70bffc24b 100644
--- a/llvm/include/llvm/BinaryFormat/MachO.h
+++ b/llvm/include/llvm/BinaryFormat/MachO.h
@@ -1571,7 +1571,9 @@ enum CPUType {
   CPU_TYPE_ARM64_32 = CPU_TYPE_ARM | CPU_ARCH_ABI64_32,
   CPU_TYPE_SPARC = 14,
   CPU_TYPE_POWERPC = 18,
-  CPU_TYPE_POWERPC64 = CPU_TYPE_POWERPC | CPU_ARCH_ABI64
+  CPU_TYPE_POWERPC64 = CPU_TYPE_POWERPC | CPU_ARCH_ABI64,
+
+  CPU_TYPE_RISCV = 24,
 };
 
 enum : uint32_t {
@@ -1698,6 +1700,10 @@ enum CPUSubTypePowerPC {
   CPU_SUBTYPE_MC98601 = CPU_SUBTYPE_POWERPC_601
 };
 
+enum CPUSubTypeRISCV {
+  CPU_SUBTYPE_RISCV_ALL = 0,
+};
+
 Expected<uint32_t> getCPUType(const Triple &T);
 Expected<uint32_t> getCPUSubType(const Triple &T);
 Expected<uint32_t> getCPUSubType(const Triple &T, unsigned PtrAuthABIVersion,
diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
index 0ef6bf5d45f4d..edb7701402205 100644
--- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h
+++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
@@ -1610,7 +1610,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
 
       // Scale the cost of the load by the fraction of legal instructions that
       // will be used.
-      Cost = divideCeil(UsedInsts.count() * *Cost.getValue(), NumLegalInsts);
+      Cost = divideCeil(UsedInsts.count() * Cost.getValue(), NumLegalInsts);
     }
 
     // Then plus the cost of interleave operation.
@@ -2503,7 +2503,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
         return (LT.first * 2);
       else
         return (LT.first * 1);
-    } else if (!TLI->isOperationExpand(ISD, LT.second)) {
+    } else if (TLI->isOperationCustom(ISD, LT.second)) {
       // If the operation is custom lowered then assume
       // that the code is twice as expensive.
       return (LT.first * 2);
@@ -2878,7 +2878,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
           SubTp && SubTp->getElementType() == FTp->getElementType())
         return divideCeil(FTp->getNumElements(), SubTp->getNumElements());
     }
-    return *LT.first.getValue();
+    return LT.first.getValue();
   }
 
   InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *,
diff --git a/llvm/include/llvm/CodeGen/MachinePipeliner.h b/llvm/include/llvm/CodeGen/MachinePipeliner.h
index fee6937e7d502..966ffb7a1fbd2 100644
--- a/llvm/include/llvm/CodeGen/MachinePipeliner.h
+++ b/llvm/include/llvm/CodeGen/MachinePipeliner.h
@@ -278,6 +278,13 @@ class SwingSchedulerDAG : public ScheduleDAGInstrs {
   /// Ordered list of DAG postprocessing steps.
   std::vector<std::unique_ptr<ScheduleDAGMutation>> Mutations;
 
+  /// Used to compute single-iteration dependencies (i.e., buildSchedGraph).
+  AliasAnalysis *AA;
+
+  /// Used to compute loop-carried dependencies (i.e.,
+  /// addLoopCarriedDependences).
+  BatchAAResults BAA;
+
   /// Helper class to implement Johnson's circuit finding algorithm.
   class Circuits {
     std::vector<SUnit> &SUnits;
@@ -323,13 +330,14 @@ class SwingSchedulerDAG : public ScheduleDAGInstrs {
 public:
   SwingSchedulerDAG(MachinePipeliner &P, MachineLoop &L, LiveIntervals &lis,
                     const RegisterClassInfo &rci, unsigned II,
-                    TargetInstrInfo::PipelinerLoopInfo *PLI)
+                    TargetInstrInfo::PipelinerLoopInfo *PLI, AliasAnalysis *AA)
       : ScheduleDAGInstrs(*P.MF, P.MLI, false), Pass(P), Loop(L), LIS(lis),
         RegClassInfo(rci), II_setByPragma(II), LoopPipelinerInfo(PLI),
-        Topo(SUnits, &ExitSU) {
+        Topo(SUnits, &ExitSU), AA(AA), BAA(*AA) {
     P.MF->getSubtarget().getSMSMutations(Mutations);
     if (SwpEnableCopyToPhi)
       Mutations.push_back(std::make_unique<CopyToPhiMutation>());
+    BAA.enableCrossIterationMode();
   }
 
   void schedule() override;
@@ -394,7 +402,7 @@ class SwingSchedulerDAG : public ScheduleDAGInstrs {
                              const MachineInstr *OtherMI) const;
 
 private:
-  void addLoopCarriedDependences(AAResults *AA);
+  void addLoopCarriedDependences();
   void updatePhiDependences();
   void changeDependences();
   unsigned calculateResMII();
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 00c36266a069f..abe261728a3e6 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -1650,6 +1650,24 @@ class TargetLoweringBase {
            getCondCodeAction(CC, VT) == Custom;
   }
 
+  /// Return how a PARTIAL_REDUCE_U/SMLA node with Acc type AccVT and Input type
+  /// InputVT should be treated. Either it's legal, needs to be promoted to a
+  /// larger size, needs to be expanded to some other code sequence, or the
+  /// target has a custom expander for it.
+  LegalizeAction getPartialReduceMLAAction(EVT AccVT, EVT InputVT) const {
+    PartialReduceActionTypes TypePair = {AccVT.getSimpleVT().SimpleTy,
+                                         InputVT.getSimpleVT().SimpleTy};
+    auto It = PartialReduceMLAActions.find(TypePair);
+    return It != PartialReduceMLAActions.end() ? It->second : Expand;
+  }
+
+  /// Return true if a PARTIAL_REDUCE_U/SMLA node with the specified types is
+  /// legal or custom for this target.
+  bool isPartialReduceMLALegalOrCustom(EVT AccVT, EVT InputVT) const {
+    LegalizeAction Action = getPartialReduceMLAAction(AccVT, InputVT);
+    return Action == Legal || Action == Custom;
+  }
+
   /// If the action for this operation is to promote, this method returns the
   /// ValueType to promote to.
   MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
@@ -1823,9 +1841,13 @@ class TargetLoweringBase {
   virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
 
   /// Return true if it is profitable to reduce a load to a smaller type.
+  /// \p ByteOffset is only set if we know the pointer offset at compile time
+  /// otherwise we should assume that additional pointer math is required.
   /// Example: (i16 (trunc (i32 (load x))) -> i16 load x
-  virtual bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
-                                     EVT NewVT) const {
+  /// Example: (i16 (trunc (srl (i32 (load x)), 16)) -> i16 load x+2
+  virtual bool shouldReduceLoadWidth(
+      SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT,
+      std::optional<unsigned> ByteOffset = std::nullopt) const {
     // By default, assume that it is cheaper to extract a subvector from a wide
     // vector load rather than creating multiple narrow vector loads.
     if (NewVT.isVector() && !SDValue(Load, 0).hasOneUse())
@@ -2723,6 +2745,18 @@ class TargetLoweringBase {
       setCondCodeAction(CCs, VT, Action);
   }
 
+  /// Indicate how a PARTIAL_REDUCE_U/SMLA node with Acc type AccVT and Input
+  /// type InputVT should be treated by the target. Either it's legal, needs to
+  /// be promoted to a larger size, needs to be expanded to some other code
+  /// sequence, or the target has a custom expander for it.
+  void setPartialReduceMLAAction(MVT AccVT, MVT InputVT,
+                                 LegalizeAction Action) {
+    assert(AccVT.isValid() && InputVT.isValid() &&
+           "setPartialReduceMLAAction types aren't valid");
+    PartialReduceActionTypes TypePair = {AccVT.SimpleTy, InputVT.SimpleTy};
+    PartialReduceMLAActions[TypePair] = Action;
+  }
+
   /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
   /// to trying a larger integer/fp until it can find one that works. If that
   /// default is insufficient, this method can be used by the target to override
@@ -3702,6 +3736,13 @@ class TargetLoweringBase {
   /// up the MVT::VALUETYPE_SIZE value to the next multiple of 8.
   uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::VALUETYPE_SIZE + 7) / 8];
 
+  using PartialReduceActionTypes =
+      std::pair<MVT::SimpleValueType, MVT::SimpleValueType>;
+  /// For each result type and input type for the ISD::PARTIAL_REDUCE_U/SMLA
+  /// nodes, keep a LegalizeAction which indicates how instruction selection
+  /// should deal with this operation.
+  DenseMap<PartialReduceActionTypes, LegalizeAction> PartialReduceMLAActions;
+
   ValueTypeActionImpl ValueTypeActions;
 
 private:
diff --git a/llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h b/llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
index c1b67844c747f..778b0c397f9cf 100644
--- a/llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
+++ b/llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
@@ -23,6 +23,13 @@ namespace rootsig {
 
 // Definitions of the in-memory data layout structures
 
+// Models the different registers: bReg | tReg | uReg | sReg
+enum class RegisterType { BReg, TReg, UReg, SReg };
+struct Register {
+  RegisterType ViewType;
+  uint32_t Number;
+};
+
 // Models the end of a descriptor table and stores its visibility
 struct DescriptorTable {
   uint32_t NumClauses = 0; // The number of clauses in the table
@@ -32,6 +39,8 @@ struct DescriptorTable {
 using ClauseType = llvm::dxil::ResourceClass;
 struct DescriptorTableClause {
   ClauseType Type;
+  Register Reg;
+  uint32_t Space = 0;
 };
 
 // Models RootElement : DescriptorTable | DescriptorTableClause
diff --git a/llvm/include/llvm/Frontend/OpenACC/ACC.td b/llvm/include/llvm/Frontend/OpenACC/ACC.td
index 7dc97e6c89bee..d372fc221e4b4 100644
--- a/llvm/include/llvm/Frontend/OpenACC/ACC.td
+++ b/llvm/include/llvm/Frontend/OpenACC/ACC.td
@@ -284,11 +284,11 @@ def ACC_Atomic : Directive<"atomic"> {
 // 2.6.5
 def ACC_Data : Directive<"data"> {
   let allowedOnceClauses = [
-    VersionedClause<ACCC_Async, 32>,
     VersionedClause<ACCC_If>,
     VersionedClause<ACCC_Default>
   ];
   let allowedClauses = [
+    VersionedClause<ACCC_Async, 32>,
     VersionedClause<ACCC_DeviceType, 32>,
     VersionedClause<ACCC_Wait, 32>
   ];
diff --git a/llvm/include/llvm/Frontend/OpenMP/OMPDeviceConstants.h b/llvm/include/llvm/Frontend/OpenMP/OMPDeviceConstants.h
index ccf8e727c4045..3ae447b14f320 100644
--- a/llvm/include/llvm/Frontend/OpenMP/OMPDeviceConstants.h
+++ b/llvm/include/llvm/Frontend/OpenMP/OMPDeviceConstants.h
@@ -19,6 +19,7 @@ namespace llvm {
 namespace omp {
 
 enum OMPTgtExecModeFlags : unsigned char {
+  OMP_TGT_EXEC_MODE_BARE = 0,
   OMP_TGT_EXEC_MODE_GENERIC = 1 << 0,
   OMP_TGT_EXEC_MODE_SPMD = 1 << 1,
   OMP_TGT_EXEC_MODE_GENERIC_SPMD =
diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td
index c493198e8ef8f..67fd91f0896eb 100644
--- a/llvm/include/llvm/IR/IntrinsicsAArch64.td
+++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td
@@ -3068,14 +3068,14 @@ let TargetPrefix = "aarch64" in {
       : DefaultAttrsIntrinsic<[],
           [llvm_i32_ty,
           llvm_anyvector_ty,
-          LLVMMatchType<0>], [ImmArg<ArgIndex<0>>, IntrNoMem, IntrHasSideEffects]>;
+          LLVMMatchType<0>], [ImmArg<ArgIndex<0>>, IntrInaccessibleMemOnly, IntrHasSideEffects]>;
 
   class SME_OuterProduct_QuarterTile_Single_Multi
       : DefaultAttrsIntrinsic<[],
           [llvm_i32_ty,
           llvm_anyvector_ty,
           LLVMMatchType<0>,
-          LLVMMatchType<0>], [ImmArg<ArgIndex<0>>, IntrNoMem, IntrHasSideEffects]>;
+          LLVMMatchType<0>], [ImmArg<ArgIndex<0>>, IntrInaccessibleMemOnly, IntrHasSideEffects]>;
 
   class SME_OuterProduct_QuarterTile_Multi_Multi
       : DefaultAttrsIntrinsic<[],
@@ -3083,7 +3083,7 @@ let TargetPrefix = "aarch64" in {
           llvm_anyvector_ty,
           LLVMMatchType<0>,
           LLVMMatchType<0>,
-          LLVMMatchType<0>], [ImmArg<ArgIndex<0>>, IntrNoMem, IntrHasSideEffects]>;
+          LLVMMatchType<0>], [ImmArg<ArgIndex<0>>, IntrInaccessibleMemOnly, IntrHasSideEffects]>;
 
   // 2-way and 4-way multi-vector signed/unsigned Quarter Tile Quarter Product A/S
   foreach mode = ["s", "a"] in {
@@ -3125,6 +3125,14 @@ let TargetPrefix = "aarch64" in {
   def int_aarch64_sme_sutmopa_za32 : SME_OuterProduct_TMOP_Intrinsic;
   def int_aarch64_sme_ustmopa_za32 : SME_OuterProduct_TMOP_Intrinsic;
 
+  // 16 and 32 bit multi-vector floating point 8 Quarter Tile Quarter Product
+  foreach za = ["za16", "za32"] in {
+    def int_aarch64_sme_fp8_fmop4a_ # za # "_1x1" : SME_OuterProduct_QuarterTile_Single_Single;
+    def int_aarch64_sme_fp8_fmop4a_ # za # "_1x2" : SME_OuterProduct_QuarterTile_Single_Multi;
+    def int_aarch64_sme_fp8_fmop4a_ # za # "_2x1" : SME_OuterProduct_QuarterTile_Single_Multi;
+    def int_aarch64_sme_fp8_fmop4a_ # za # "_2x2" : SME_OuterProduct_QuarterTile_Multi_Multi;
+  }
+
   class SME_AddVectorToTile_Intrinsic
       : DefaultAttrsIntrinsic<[],
           [llvm_i32_ty,
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index b57102ef68f09..8d91b5fdd04fe 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1677,6 +1677,22 @@ let TargetPrefix = "ppc" in {
       DefaultAttrsIntrinsic<[llvm_v1024i1_ty], [llvm_v1024i1_ty,
                              llvm_v1024i1_ty], [IntrNoMem]>;
 
+  def int_ppc_mma_dmxxextfdmr512 :
+      DefaultAttrsIntrinsic<[llvm_v256i1_ty, llvm_v256i1_ty], [llvm_v1024i1_ty,
+                             llvm_i32_ty], [IntrNoMem]>;
+
+  def int_ppc_mma_dmxxinstdmr512 :
+      DefaultAttrsIntrinsic<[llvm_v1024i1_ty], [llvm_v1024i1_ty, llvm_v256i1_ty,
+                             llvm_v256i1_ty, llvm_i32_ty], [IntrNoMem]>;
+
+  def int_ppc_mma_dmxxextfdmr256 :
+      DefaultAttrsIntrinsic<[llvm_v256i1_ty], [llvm_v1024i1_ty, llvm_i32_ty],
+                            [IntrNoMem]>;
+
+  def int_ppc_mma_dmxxinstdmr256 :
+      DefaultAttrsIntrinsic<[llvm_v1024i1_ty], [llvm_v1024i1_ty, llvm_v256i1_ty,
+                             llvm_i32_ty], [IntrNoMem]>;
+
   // MMA Reduced-Precision: Outer Product Intrinsic Definitions.
   defm int_ppc_mma_xvi4ger8 :
         PowerPC_MMA_ACC_PP_Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty]>;
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.def b/llvm/include/llvm/IR/RuntimeLibcalls.def
index 2545aebc73391..cd8e9b598044c 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.def
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.def
@@ -85,6 +85,9 @@ HANDLE_LIBCALL(NEG_I64, "__negdi2")
 HANDLE_LIBCALL(CTLZ_I32, "__clzsi2")
 HANDLE_LIBCALL(CTLZ_I64, "__clzdi2")
 HANDLE_LIBCALL(CTLZ_I128, "__clzti2")
+HANDLE_LIBCALL(CTPOP_I32, "__popcountsi2")
+HANDLE_LIBCALL(CTPOP_I64, "__popcountdi2")
+HANDLE_LIBCALL(CTPOP_I128, "__popcountti2")
 
 // Floating-point
 HANDLE_LIBCALL(ADD_F32, "__addsf3")
diff --git a/llvm/include/llvm/IR/Value.h b/llvm/include/llvm/IR/Value.h
index cfed12e2f5f8d..bf1de7eef9932 100644
--- a/llvm/include/llvm/IR/Value.h
+++ b/llvm/include/llvm/IR/Value.h
@@ -290,9 +290,7 @@ class Value {
   /// \note It is an error to call V->takeName(V).
   void takeName(Value *V);
 
-#ifndef NDEBUG
   std::string getNameOrAsOperand() const;
-#endif
 
   /// Change all uses of this to point to a new Value.
   ///
diff --git a/llvm/include/llvm/ProfileData/IndexedMemProfData.h b/llvm/include/llvm/ProfileData/IndexedMemProfData.h
new file mode 100644
index 0000000000000..3c6c329d1c49d
--- /dev/null
+++ b/llvm/include/llvm/ProfileData/IndexedMemProfData.h
@@ -0,0 +1,23 @@
+//===- IndexedMemProfData.h - MemProf format support ------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// MemProf data is serialized in writeMemProf provided in this header file.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/ProfileData/InstrProf.h"
+#include "llvm/ProfileData/MemProf.h"
+
+namespace llvm {
+
+// Write the MemProf data to OS.
+Error writeMemProf(ProfOStream &OS, memprof::IndexedMemProfData &MemProfData,
+                   memprof::IndexedVersion MemProfVersionRequested,
+                   bool MemProfFullSchema);
+
+} // namespace llvm
diff --git a/llvm/include/llvm/ProfileData/InstrProf.h b/llvm/include/llvm/ProfileData/InstrProf.h
index 7133c0c6a302c..2d011c89f27cb 100644
--- a/llvm/include/llvm/ProfileData/InstrProf.h
+++ b/llvm/include/llvm/ProfileData/InstrProf.h
@@ -28,6 +28,7 @@
 #include "llvm/Support/BalancedPartitioning.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Compiler.h"
+#include "llvm/Support/EndianStream.h"
 #include "llvm/Support/Error.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MD5.h"
@@ -57,6 +58,37 @@ class Instruction;
 class MDNode;
 class Module;
 
+// A struct to define how the data stream should be patched. For Indexed
+// profiling, only uint64_t data type is needed.
+struct PatchItem {
+  uint64_t Pos;         // Where to patch.
+  ArrayRef<uint64_t> D; // An array of source data.
+};
+
+// A wrapper class to abstract writer stream with support of bytes
+// back patching.
+class ProfOStream {
+public:
+  ProfOStream(raw_fd_ostream &FD);
+  ProfOStream(raw_string_ostream &STR);
+
+  [[nodiscard]] uint64_t tell() const;
+  void write(uint64_t V);
+  void write32(uint32_t V);
+  void writeByte(uint8_t V);
+
+  // \c patch can only be called when all data is written and flushed.
+  // For raw_string_ostream, the patch is done on the target string
+  // directly and it won't be reflected in the stream's internal buffer.
+  void patch(ArrayRef<PatchItem> P);
+
+  // If \c OS is an instance of \c raw_fd_ostream, this field will be
+  // true. Otherwise, \c OS will be an raw_string_ostream.
+  bool IsFDOStream;
+  raw_ostream &OS;
+  support::endian::Writer LE;
+};
+
 enum InstrProfSectKind {
 #define INSTR_PROF_SECT_ENTRY(Kind, SectNameCommon, SectNameCoff, Prefix) Kind,
 #include "llvm/ProfileData/InstrProfData.inc"
diff --git a/llvm/include/llvm/Support/InstructionCost.h b/llvm/include/llvm/Support/InstructionCost.h
index b5af0e0401ef2..d5f7457e04748 100644
--- a/llvm/include/llvm/Support/InstructionCost.h
+++ b/llvm/include/llvm/Support/InstructionCost.h
@@ -20,7 +20,6 @@
 
 #include "llvm/Support/MathExtras.h"
 #include <limits>
-#include <optional>
 
 namespace llvm {
 
@@ -84,10 +83,9 @@ class InstructionCost {
   /// This function is intended to be used as sparingly as possible, since the
   /// class provides the full range of operator support required for arithmetic
   /// and comparisons.
-  std::optional<CostType> getValue() const {
-    if (isValid())
-      return Value;
-    return std::nullopt;
+  CostType getValue() const {
+    assert(isValid());
+    return Value;
   }
 
   /// For all of the arithmetic operators provided here any invalid state is
diff --git a/llvm/include/llvm/Target/TargetSelectionDAG.td b/llvm/include/llvm/Target/TargetSelectionDAG.td
index 9c241b6c4df0f..cd0dc26a1f257 100644
--- a/llvm/include/llvm/Target/TargetSelectionDAG.td
+++ b/llvm/include/llvm/Target/TargetSelectionDAG.td
@@ -313,6 +313,10 @@ def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert
   SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3>
 ]>;
 
+def SDTPartialReduceMLA : SDTypeProfile<1, 3, [ // partial reduce mla
+  SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>
+]>;
+
 def SDTPrefetch : SDTypeProfile<0, 4, [     // prefetch
   SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1>
 ]>;
@@ -513,6 +517,11 @@ def vecreduce_fmax  : SDNode<"ISD::VECREDUCE_FMAX", SDTFPVecReduce>;
 def vecreduce_fminimum : SDNode<"ISD::VECREDUCE_FMINIMUM", SDTFPVecReduce>;
 def vecreduce_fmaximum : SDNode<"ISD::VECREDUCE_FMAXIMUM", SDTFPVecReduce>;
 
+def partial_reduce_umla : SDNode<"ISD::PARTIAL_REDUCE_UMLA",
+                                 SDTPartialReduceMLA>;
+def partial_reduce_smla : SDNode<"ISD::PARTIAL_REDUCE_SMLA",
+                                 SDTPartialReduceMLA>;
+
 def fadd       : SDNode<"ISD::FADD"       , SDTFPBinOp, [SDNPCommutative]>;
 def fsub       : SDNode<"ISD::FSUB"       , SDTFPBinOp>;
 def fmul       : SDNode<"ISD::FMUL"       , SDTFPBinOp, [SDNPCommutative]>;
@@ -1315,25 +1324,21 @@ def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
                            (truncstore node:$val, node:$ptr)> {
   let IsStore = true;
   let MemoryVT = i8;
-  let IsTruncStore = true;
 }
 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
                             (truncstore node:$val, node:$ptr)> {
   let IsStore = true;
   let MemoryVT = i16;
-  let IsTruncStore = true;
 }
 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
                             (truncstore node:$val, node:$ptr)> {
   let IsStore = true;
   let MemoryVT = i32;
-  let IsTruncStore = true;
 }
 def truncstorei64 : PatFrag<(ops node:$val, node:$ptr),
                             (truncstore node:$val, node:$ptr)> {
   let IsStore = true;
   let MemoryVT = i64;
-  let IsTruncStore = true;
 }
 def truncstoref16 : PatFrag<(ops node:$val, node:$ptr),
                             (truncstore node:$val, node:$ptr)> {
@@ -1843,6 +1848,13 @@ def atomic_load_sext :
   let IsSignExtLoad = true;
 }
 
+/// Atomic load which any extends the excess high bits.
+def atomic_load_aext :
+  PatFrag<(ops node:$ptr), (atomic_load node:$ptr)> {
+  let IsAtomic = true; // FIXME: Should be IsLoad and/or IsAtomic?
+  let IsAnyExtLoad = true;
+}
+
 def atomic_load_8 :
   PatFrag<(ops node:$ptr),
           (atomic_load node:$ptr)> {
@@ -1882,6 +1894,12 @@ def atomic_load_zext_16 :
   let MemoryVT = i16;
 }
 
+def atomic_load_zext_32 :
+  PatFrag<(ops node:$ptr), (atomic_load_zext node:$ptr)> {
+  let IsAtomic = true; // FIXME: Should be IsLoad and/or IsAtomic?
+  let MemoryVT = i32;
+}
+
 def atomic_load_sext_8 :
   PatFrag<(ops node:$ptr), (atomic_load_sext node:$ptr)> {
   let IsAtomic = true; // FIXME: Should be IsLoad and/or IsAtomic?
@@ -1894,15 +1912,54 @@ def atomic_load_sext_16 :
   let MemoryVT = i16;
 }
 
+def atomic_load_sext_32 :
+  PatFrag<(ops node:$ptr), (atomic_load_sext node:$ptr)> {
+  let IsAtomic = true; // FIXME: Should be IsLoad and/or IsAtomic?
+  let MemoryVT = i32;
+}
+
+def atomic_load_aext_8 :
+  PatFrag<(ops node:$ptr), (atomic_load_aext node:$ptr)> {
+  let IsAtomic = true; // FIXME: Should be IsLoad and/or IsAtomic?
+  let MemoryVT = i8;
+}
+
+def atomic_load_aext_16 :
+  PatFrag<(ops node:$ptr), (atomic_load_aext node:$ptr)> {
+  let IsAtomic = true; // FIXME: Should be IsLoad and/or IsAtomic?
+  let MemoryVT = i16;
+}
+
+def atomic_load_aext_32 :
+  PatFrag<(ops node:$ptr), (atomic_load_aext node:$ptr)> {
+  let IsAtomic = true; // FIXME: Should be IsLoad and/or IsAtomic?
+  let MemoryVT = i32;
+}
+
 // Atomic load which zeroes or anyextends the high bits.
-def atomic_load_az_8 : PatFrags<(ops node:$op),
-                                [(atomic_load_8 node:$op),
-                                 (atomic_load_zext_8 node:$op)]>;
+def atomic_load_azext_8 : PatFrags<(ops node:$op),
+                                   [(atomic_load_aext_8 node:$op),
+                                    (atomic_load_zext_8 node:$op)]>;
 
 // Atomic load which zeroes or anyextends the high bits.
-def atomic_load_az_16 : PatFrags<(ops node:$op),
-                                 [(atomic_load_16 node:$op),
-                                  (atomic_load_zext_16 node:$op)]>;
+def atomic_load_azext_16 : PatFrags<(ops node:$op),
+                                    [(atomic_load_aext_16 node:$op),
+                                     (atomic_load_zext_16 node:$op)]>;
+
+// Atomic load which sign extends or anyextends the high bits.
+def atomic_load_asext_8 : PatFrags<(ops node:$op),
+                                   [(atomic_load_aext_8 node:$op),
+                                    (atomic_load_sext_8 node:$op)]>;
+
+// Atomic load which sign extends or anyextends the high bits.
+def atomic_load_asext_16 : PatFrags<(ops node:$op),
+                                    [(atomic_load_aext_16 node:$op),
+                                     (atomic_load_sext_16 node:$op)]>;
+
+// Atomic load which sign extends or anyextends the high bits.
+def atomic_load_asext_32 : PatFrags<(ops node:$op),
+                                    [(atomic_load_aext_32 node:$op),
+                                     (atomic_load_sext_32 node:$op)]>;
 
 def nonext_masked_gather :
   PatFrag<(ops node:$def, node:$pred, node:$ptr, node:$idx),
diff --git a/llvm/include/llvm/Transforms/Utils/UnrollLoop.h b/llvm/include/llvm/Transforms/Utils/UnrollLoop.h
index ed560f6f6e2fa..6759afd8077e9 100644
--- a/llvm/include/llvm/Transforms/Utils/UnrollLoop.h
+++ b/llvm/include/llvm/Transforms/Utils/UnrollLoop.h
@@ -143,7 +143,7 @@ class UnrollCostEstimator {
   /// Whether it is legal to unroll this loop.
   bool canUnroll() const;
 
-  uint64_t getRolledLoopSize() const { return *LoopSize.getValue(); }
+  uint64_t getRolledLoopSize() const { return LoopSize.getValue(); }
 
   /// Returns loop size estimation for unrolled loop, given the unrolling
   /// configuration specified by UP.
diff --git a/llvm/lib/Analysis/CostModel.cpp b/llvm/lib/Analysis/CostModel.cpp
index cec0fb6b98dea..6d8bd7d924074 100644
--- a/llvm/lib/Analysis/CostModel.cpp
+++ b/llvm/lib/Analysis/CostModel.cpp
@@ -128,8 +128,8 @@ PreservedAnalyses CostModelPrinterPass::run(Function &F,
       } else {
         InstructionCost Cost =
             getCost(Inst, OutputCostKindToTargetCostKind(CostKind), TTI, TLI);
-        if (auto CostVal = Cost.getValue())
-          OS << "Found an estimated cost of " << *CostVal;
+        if (Cost.isValid())
+          OS << "Found an estimated cost of " << Cost.getValue();
         else
           OS << "Invalid cost";
         OS << " for instruction: " << Inst << "\n";
diff --git a/llvm/lib/Analysis/InlineSizeEstimatorAnalysis.cpp b/llvm/lib/Analysis/InlineSizeEstimatorAnalysis.cpp
index fcecfc795b571..fc635726a6aa4 100644
--- a/llvm/lib/Analysis/InlineSizeEstimatorAnalysis.cpp
+++ b/llvm/lib/Analysis/InlineSizeEstimatorAnalysis.cpp
@@ -128,8 +128,9 @@ size_t getSize(Function &F, TargetTransformInfo &TTI) {
   size_t Ret = 0;
   for (const auto &BB : F)
     for (const auto &I : BB)
-      Ret += *(TTI.getInstructionCost(
-          &I, TargetTransformInfo::TargetCostKind::TCK_CodeSize).getValue());
+      Ret += TTI.getInstructionCost(
+                    &I, TargetTransformInfo::TargetCostKind::TCK_CodeSize)
+                 .getValue();
   return Ret;
 }
 
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
index 3939dae81841f..a20c374e08935 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
@@ -782,6 +782,8 @@ DIE *DwarfCompileUnit::constructLexicalScopeDIE(LexicalScope *Scope) {
     assert(!LexicalBlockDIEs.count(DS) &&
            "Concrete out-of-line DIE for this scope exists!");
     LexicalBlockDIEs[DS] = ScopeDIE;
+  } else {
+    InlinedLocalScopeDIEs[DS].push_back(ScopeDIE);
   }
 
   attachRangesOrLowHighPC(*ScopeDIE, Scope->getRanges());
@@ -1491,6 +1493,19 @@ void DwarfCompileUnit::finishEntityDefinition(const DbgEntity *Entity) {
     getDwarfDebug().addAccelName(*this, CUNode->getNameTableKind(), Name, *Die);
 }
 
+void DwarfCompileUnit::attachLexicalScopesAbstractOrigins() {
+  auto AttachAO = [&](const DILocalScope *LS, DIE *ScopeDIE) {
+    if (auto *AbsLSDie = getAbstractScopeDIEs().lookup(LS))
+      addDIEEntry(*ScopeDIE, dwarf::DW_AT_abstract_origin, *AbsLSDie);
+  };
+
+  for (auto [LScope, ScopeDIE] : LexicalBlockDIEs)
+    AttachAO(LScope, ScopeDIE);
+  for (auto &[LScope, ScopeDIEs] : InlinedLocalScopeDIEs)
+    for (auto *ScopeDIE : ScopeDIEs)
+      AttachAO(LScope, ScopeDIE);
+}
+
 DbgEntity *DwarfCompileUnit::getExistingAbstractEntity(const DINode *Node) {
   auto &AbstractEntities = getAbstractEntities();
   auto I = AbstractEntities.find(Node);
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
index 104039db03c7c..09be22ce35e36 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
@@ -82,6 +82,10 @@ class DwarfCompileUnit final : public DwarfUnit {
   // List of abstract local scopes (either DISubprogram or DILexicalBlock).
   DenseMap<const DILocalScope *, DIE *> AbstractLocalScopeDIEs;
 
+  // List of inlined lexical block scopes that belong to subprograms within this
+  // CU.
+  DenseMap<const DILocalScope *, SmallVector<DIE *, 2>> InlinedLocalScopeDIEs;
+
   DenseMap<const DINode *, std::unique_ptr<DbgEntity>> AbstractEntities;
 
   /// DWO ID for correlating skeleton and split units.
@@ -299,6 +303,7 @@ class DwarfCompileUnit final : public DwarfUnit {
 
   void finishSubprogramDefinition(const DISubprogram *SP);
   void finishEntityDefinition(const DbgEntity *Entity);
+  void attachLexicalScopesAbstractOrigins();
 
   /// Find abstract variable associated with Var.
   using InlinedEntity = DbgValueHistoryMap::InlinedEntity;
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
index 39f1299a24e81..6c932651750ee 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
@@ -1262,6 +1262,7 @@ void DwarfDebug::finalizeModuleInfo() {
     auto &TheCU = *P.second;
     if (TheCU.getCUNode()->isDebugDirectivesOnly())
       continue;
+    TheCU.attachLexicalScopesAbstractOrigins();
     // Emit DW_AT_containing_type attribute to connect types with their
     // vtable holding type.
     TheCU.constructContainingTypeDIEs();
diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp
index 12a668507fe65..e8dc7752b23c0 100644
--- a/llvm/lib/CodeGen/CodeGenPrepare.cpp
+++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp
@@ -474,6 +474,7 @@ class CodeGenPrepare {
   bool optimizeURem(Instruction *Rem);
   bool combineToUSubWithOverflow(CmpInst *Cmp, ModifyDT &ModifiedDT);
   bool combineToUAddWithOverflow(CmpInst *Cmp, ModifyDT &ModifiedDT);
+  bool unfoldPowerOf2Test(CmpInst *Cmp);
   void verifyBFIUpdates(Function &F);
   bool _run(Function &F);
 };
@@ -1762,6 +1763,75 @@ bool CodeGenPrepare::combineToUSubWithOverflow(CmpInst *Cmp,
   return true;
 }
 
+// Decanonicalizes icmp+ctpop power-of-two test if ctpop is slow.
+// The same transformation exists in DAG combiner, but we repeat it here because
+// DAG builder can break the pattern by moving icmp into a successor block.
+bool CodeGenPrepare::unfoldPowerOf2Test(CmpInst *Cmp) {
+  CmpPredicate Pred;
+  Value *X;
+  const APInt *C;
+
+  // (icmp (ctpop x), c)
+  if (!match(Cmp, m_ICmp(Pred, m_Intrinsic<Intrinsic::ctpop>(m_Value(X)),
+                         m_APIntAllowPoison(C))))
+    return false;
+
+  // We're only interested in "is power of 2 [or zero]" patterns.
+  bool IsStrictlyPowerOf2Test = ICmpInst::isEquality(Pred) && *C == 1;
+  bool IsPowerOf2OrZeroTest = (Pred == CmpInst::ICMP_ULT && *C == 2) ||
+                              (Pred == CmpInst::ICMP_UGT && *C == 1);
+  if (!IsStrictlyPowerOf2Test && !IsPowerOf2OrZeroTest)
+    return false;
+
+  // Some targets have better codegen for `ctpop(x) u</u>= 2/1`than for
+  // `ctpop(x) ==/!= 1`. If ctpop is fast, only try changing the comparison,
+  // and otherwise expand ctpop into a few simple instructions.
+  Type *OpTy = X->getType();
+  if (TLI->isCtpopFast(TLI->getValueType(*DL, OpTy))) {
+    // Look for `ctpop(x) ==/!= 1`, where `ctpop(x)` is known to be non-zero.
+    if (!IsStrictlyPowerOf2Test || !isKnownNonZero(Cmp->getOperand(0), *DL))
+      return false;
+
+    // ctpop(x) == 1 -> ctpop(x) u< 2
+    // ctpop(x) != 1 -> ctpop(x) u> 1
+    if (Pred == ICmpInst::ICMP_EQ) {
+      Cmp->setOperand(1, ConstantInt::get(OpTy, 2));
+      Cmp->setPredicate(ICmpInst::ICMP_ULT);
+    } else {
+      Cmp->setPredicate(ICmpInst::ICMP_UGT);
+    }
+    return true;
+  }
+
+  Value *NewCmp;
+  if (IsPowerOf2OrZeroTest ||
+      (IsStrictlyPowerOf2Test && isKnownNonZero(Cmp->getOperand(0), *DL))) {
+    // ctpop(x) u< 2 -> (x & (x - 1)) == 0
+    // ctpop(x) u> 1 -> (x & (x - 1)) != 0
+    IRBuilder<> Builder(Cmp);
+    Value *Sub = Builder.CreateAdd(X, Constant::getAllOnesValue(OpTy));
+    Value *And = Builder.CreateAnd(X, Sub);
+    CmpInst::Predicate NewPred =
+        (Pred == CmpInst::ICMP_ULT || Pred == CmpInst::ICMP_EQ)
+            ? CmpInst::ICMP_EQ
+            : CmpInst::ICMP_NE;
+    NewCmp = Builder.CreateICmp(NewPred, And, ConstantInt::getNullValue(OpTy));
+  } else {
+    // ctpop(x) == 1 -> (x ^ (x - 1)) u> (x - 1)
+    // ctpop(x) != 1 -> (x ^ (x - 1)) u<= (x - 1)
+    IRBuilder<> Builder(Cmp);
+    Value *Sub = Builder.CreateAdd(X, Constant::getAllOnesValue(OpTy));
+    Value *Xor = Builder.CreateXor(X, Sub);
+    CmpInst::Predicate NewPred =
+        Pred == CmpInst::ICMP_EQ ? CmpInst::ICMP_UGT : CmpInst::ICMP_ULE;
+    NewCmp = Builder.CreateICmp(NewPred, Xor, Sub);
+  }
+
+  Cmp->replaceAllUsesWith(NewCmp);
+  RecursivelyDeleteTriviallyDeadInstructions(Cmp);
+  return true;
+}
+
 /// Sink the given CmpInst into user blocks to reduce the number of virtual
 /// registers that must be created and coalesced. This is a clear win except on
 /// targets with multiple condition code registers (PowerPC), where it might
@@ -2148,31 +2218,6 @@ bool CodeGenPrepare::optimizeURem(Instruction *Rem) {
   return false;
 }
 
-/// Some targets have better codegen for `ctpop(X) u< 2` than `ctpop(X) == 1`.
-/// This function converts `ctpop(X) ==/!= 1` into `ctpop(X) u</u> 2/1` if the
-/// result cannot be zero.
-static bool adjustIsPower2Test(CmpInst *Cmp, const TargetLowering &TLI,
-                               const TargetTransformInfo &TTI,
-                               const DataLayout &DL) {
-  CmpPredicate Pred;
-  if (!match(Cmp, m_ICmp(Pred, m_Intrinsic<Intrinsic::ctpop>(), m_One())))
-    return false;
-  if (!ICmpInst::isEquality(Pred))
-    return false;
-  auto *II = cast<IntrinsicInst>(Cmp->getOperand(0));
-
-  if (isKnownNonZero(II, DL)) {
-    if (Pred == ICmpInst::ICMP_EQ) {
-      Cmp->setOperand(1, ConstantInt::get(II->getType(), 2));
-      Cmp->setPredicate(ICmpInst::ICMP_ULT);
-    } else {
-      Cmp->setPredicate(ICmpInst::ICMP_UGT);
-    }
-    return true;
-  }
-  return false;
-}
-
 bool CodeGenPrepare::optimizeCmp(CmpInst *Cmp, ModifyDT &ModifiedDT) {
   if (sinkCmpExpression(Cmp, *TLI))
     return true;
@@ -2183,6 +2228,9 @@ bool CodeGenPrepare::optimizeCmp(CmpInst *Cmp, ModifyDT &ModifiedDT) {
   if (combineToUSubWithOverflow(Cmp, ModifiedDT))
     return true;
 
+  if (unfoldPowerOf2Test(Cmp))
+    return true;
+
   if (foldICmpWithDominatingICmp(Cmp, *TLI))
     return true;
 
@@ -2192,9 +2240,6 @@ bool CodeGenPrepare::optimizeCmp(CmpInst *Cmp, ModifyDT &ModifiedDT) {
   if (foldFCmpToFPClassTest(Cmp, *TLI, *DL))
     return true;
 
-  if (adjustIsPower2Test(Cmp, *TLI, *TTI, *DL))
-    return true;
-
   return false;
 }
 
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index 223d69c362185..d8cc86b34a819 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -1385,7 +1385,8 @@ bool llvm::isBuildVectorConstantSplat(const Register Reg,
                                       const MachineRegisterInfo &MRI,
                                       int64_t SplatValue, bool AllowUndef) {
   if (auto SplatValAndReg = getAnyConstantSplat(Reg, MRI, AllowUndef))
-    return mi_match(SplatValAndReg->VReg, MRI, m_SpecificICst(SplatValue));
+    return SplatValAndReg->Value.getSExtValue() == SplatValue;
+
   return false;
 }
 
diff --git a/llvm/lib/CodeGen/InterleavedAccessPass.cpp b/llvm/lib/CodeGen/InterleavedAccessPass.cpp
index 9e47510e9cd1a..73f41c05711b7 100644
--- a/llvm/lib/CodeGen/InterleavedAccessPass.cpp
+++ b/llvm/lib/CodeGen/InterleavedAccessPass.cpp
@@ -632,8 +632,7 @@ getVectorDeinterleaveFactor(IntrinsicInst *II,
 
 // Return the corresponded deinterleaved mask, or nullptr if there is no valid
 // mask.
-static Value *getMask(Value *WideMask, unsigned Factor,
-                      VectorType *LeafValueTy) {
+static Value *getMask(Value *WideMask, unsigned Factor) {
   using namespace llvm::PatternMatch;
   if (auto *IMI = dyn_cast<IntrinsicInst>(WideMask)) {
     SmallVector<Value *, 8> Operands;
@@ -676,8 +675,7 @@ bool InterleavedAccessImpl::lowerDeinterleaveIntrinsic(
       return false;
     // Check mask operand. Handle both all-true and interleaved mask.
     Value *WideMask = VPLoad->getOperand(1);
-    Value *Mask = getMask(WideMask, Factor,
-                          cast<VectorType>(DeinterleaveValues[0]->getType()));
+    Value *Mask = getMask(WideMask, Factor);
     if (!Mask)
       return false;
 
@@ -729,8 +727,7 @@ bool InterleavedAccessImpl::lowerInterleaveIntrinsic(
       return false;
 
     Value *WideMask = VPStore->getOperand(2);
-    Value *Mask = getMask(WideMask, Factor,
-                          cast<VectorType>(InterleaveValues[0]->getType()));
+    Value *Mask = getMask(WideMask, Factor);
     if (!Mask)
       return false;
 
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index 6cb0299a30d7a..07bffc6c3de90 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -237,6 +237,37 @@ INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
 INITIALIZE_PASS_END(MachinePipeliner, DEBUG_TYPE,
                     "Modulo Software Pipelining", false, false)
 
+namespace {
+
+/// This class holds an SUnit corresponding to a memory operation and other
+/// information related to the instruction.
+struct SUnitWithMemInfo {
+  SUnit *SU;
+  SmallVector<const Value *, 2> UnderlyingObjs;
+
+  /// The value of a memory operand.
+  const Value *MemOpValue = nullptr;
+
+  /// The offset of a memory operand.
+  int64_t MemOpOffset = 0;
+
+  AAMDNodes AATags;
+
+  /// True if all the underlying objects are identified.
+  bool IsAllIdentified = false;
+
+  SUnitWithMemInfo(SUnit *SU);
+
+  bool isTriviallyDisjoint(const SUnitWithMemInfo &Other) const;
+
+  bool isUnknown() const { return MemOpValue == nullptr; }
+
+private:
+  bool getUnderlyingObjects();
+};
+
+} // end anonymous namespace
+
 /// The "main" function for implementing Swing Modulo Scheduling.
 bool MachinePipeliner::runOnMachineFunction(MachineFunction &mf) {
   if (skipFunction(mf.getFunction()))
@@ -470,9 +501,10 @@ void MachinePipeliner::preprocessPhiNodes(MachineBasicBlock &B) {
 bool MachinePipeliner::swingModuloScheduler(MachineLoop &L) {
   assert(L.getBlocks().size() == 1 && "SMS works on single blocks only.");
 
+  AliasAnalysis *AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
   SwingSchedulerDAG SMS(
       *this, L, getAnalysis<LiveIntervalsWrapperPass>().getLIS(), RegClassInfo,
-      II_setByPragma, LI.LoopPipelinerInfo.get());
+      II_setByPragma, LI.LoopPipelinerInfo.get(), AA);
 
   MachineBasicBlock *MBB = L.getHeader();
   // The kernel should not include any terminator instructions.  These
@@ -560,9 +592,8 @@ void SwingSchedulerDAG::setMAX_II() {
 /// We override the schedule function in ScheduleDAGInstrs to implement the
 /// scheduling part of the Swing Modulo Scheduling algorithm.
 void SwingSchedulerDAG::schedule() {
-  AliasAnalysis *AA = &Pass.getAnalysis<AAResultsWrapperPass>().getAAResults();
   buildSchedGraph(AA);
-  addLoopCarriedDependences(AA);
+  addLoopCarriedDependences();
   updatePhiDependences();
   Topo.InitDAGTopologicalSorting();
   changeDependences();
@@ -810,113 +841,131 @@ static bool isDependenceBarrier(MachineInstr &MI) {
           (!MI.mayLoad() || !MI.isDereferenceableInvariantLoad()));
 }
 
-/// Return the underlying objects for the memory references of an instruction.
+SUnitWithMemInfo::SUnitWithMemInfo(SUnit *SU) : SU(SU) {
+  if (!getUnderlyingObjects())
+    return;
+  for (const Value *Obj : UnderlyingObjs)
+    if (!isIdentifiedObject(Obj)) {
+      IsAllIdentified = false;
+      break;
+    }
+}
+
+bool SUnitWithMemInfo::isTriviallyDisjoint(
+    const SUnitWithMemInfo &Other) const {
+  // If all underlying objects are identified objects and there is no overlap
+  // between them, then these two instructions are disjoint.
+  if (!IsAllIdentified || !Other.IsAllIdentified)
+    return false;
+  for (const Value *Obj : UnderlyingObjs)
+    if (llvm::is_contained(Other.UnderlyingObjs, Obj))
+      return false;
+  return true;
+}
+
+/// Collect the underlying objects for the memory references of an instruction.
 /// This function calls the code in ValueTracking, but first checks that the
 /// instruction has a memory operand.
-static void getUnderlyingObjects(const MachineInstr *MI,
-                                 SmallVectorImpl<const Value *> &Objs) {
+/// Returns false if we cannot find the underlying objects.
+bool SUnitWithMemInfo::getUnderlyingObjects() {
+  const MachineInstr *MI = SU->getInstr();
   if (!MI->hasOneMemOperand())
-    return;
+    return false;
   MachineMemOperand *MM = *MI->memoperands_begin();
   if (!MM->getValue())
-    return;
-  getUnderlyingObjects(MM->getValue(), Objs);
-  for (const Value *V : Objs) {
-    if (!isIdentifiedObject(V)) {
-      Objs.clear();
-      return;
-    }
-  }
+    return false;
+  MemOpValue = MM->getValue();
+  MemOpOffset = MM->getOffset();
+  llvm::getUnderlyingObjects(MemOpValue, UnderlyingObjs);
+
+  // TODO: A no alias scope may be valid only in a single iteration. In this
+  // case we need to peel off it like LoopAccessAnalysis does.
+  AATags = MM->getAAInfo();
+  return true;
 }
 
 /// Add a chain edge between a load and store if the store can be an
 /// alias of the load on a subsequent iteration, i.e., a loop carried
 /// dependence. This code is very similar to the code in ScheduleDAGInstrs
 /// but that code doesn't create loop carried dependences.
-void SwingSchedulerDAG::addLoopCarriedDependences(AliasAnalysis *AA) {
-  MapVector<const Value *, SmallVector<SUnit *, 4>> PendingLoads;
-  Value *UnknownValue =
-    UndefValue::get(Type::getVoidTy(MF.getFunction().getContext()));
+void SwingSchedulerDAG::addLoopCarriedDependences() {
+  SmallVector<SUnitWithMemInfo, 4> PendingLoads;
   for (auto &SU : SUnits) {
     MachineInstr &MI = *SU.getInstr();
     if (isDependenceBarrier(MI))
       PendingLoads.clear();
     else if (MI.mayLoad()) {
-      SmallVector<const Value *, 4> Objs;
-      ::getUnderlyingObjects(&MI, Objs);
-      if (Objs.empty())
-        Objs.push_back(UnknownValue);
-      for (const auto *V : Objs) {
-        SmallVector<SUnit *, 4> &SUs = PendingLoads[V];
-        SUs.push_back(&SU);
-      }
+      PendingLoads.emplace_back(&SU);
     } else if (MI.mayStore()) {
-      SmallVector<const Value *, 4> Objs;
-      ::getUnderlyingObjects(&MI, Objs);
-      if (Objs.empty())
-        Objs.push_back(UnknownValue);
-      for (const auto *V : Objs) {
-        MapVector<const Value *, SmallVector<SUnit *, 4>>::iterator I =
-            PendingLoads.find(V);
-        if (I == PendingLoads.end())
+      SUnitWithMemInfo Store(&SU);
+      for (const SUnitWithMemInfo &Load : PendingLoads) {
+        if (Load.isTriviallyDisjoint(Store))
           continue;
-        for (auto *Load : I->second) {
-          if (isSuccOrder(Load, &SU))
-            continue;
-          MachineInstr &LdMI = *Load->getInstr();
-          // First, perform the cheaper check that compares the base register.
-          // If they are the same and the load offset is less than the store
-          // offset, then mark the dependence as loop carried potentially.
-          const MachineOperand *BaseOp1, *BaseOp2;
-          int64_t Offset1, Offset2;
-          bool Offset1IsScalable, Offset2IsScalable;
-          if (TII->getMemOperandWithOffset(LdMI, BaseOp1, Offset1,
-                                           Offset1IsScalable, TRI) &&
-              TII->getMemOperandWithOffset(MI, BaseOp2, Offset2,
-                                           Offset2IsScalable, TRI)) {
-            if (BaseOp1->isIdenticalTo(*BaseOp2) &&
-                Offset1IsScalable == Offset2IsScalable &&
-                (int)Offset1 < (int)Offset2) {
-              assert(TII->areMemAccessesTriviallyDisjoint(LdMI, MI) &&
-                     "What happened to the chain edge?");
-              SDep Dep(Load, SDep::Barrier);
-              Dep.setLatency(1);
-              SU.addPred(Dep);
-              continue;
-            }
-          }
-          // Second, the more expensive check that uses alias analysis on the
-          // base registers. If they alias, and the load offset is less than
-          // the store offset, the mark the dependence as loop carried.
-          if (!AA) {
-            SDep Dep(Load, SDep::Barrier);
-            Dep.setLatency(1);
-            SU.addPred(Dep);
-            continue;
-          }
-          MachineMemOperand *MMO1 = *LdMI.memoperands_begin();
-          MachineMemOperand *MMO2 = *MI.memoperands_begin();
-          if (!MMO1->getValue() || !MMO2->getValue()) {
-            SDep Dep(Load, SDep::Barrier);
-            Dep.setLatency(1);
-            SU.addPred(Dep);
-            continue;
-          }
-          if (MMO1->getValue() == MMO2->getValue() &&
-              MMO1->getOffset() <= MMO2->getOffset()) {
-            SDep Dep(Load, SDep::Barrier);
+        if (isSuccOrder(Load.SU, Store.SU))
+          continue;
+        MachineInstr &LdMI = *Load.SU->getInstr();
+        // First, perform the cheaper check that compares the base register.
+        // If they are the same and the load offset is less than the store
+        // offset, then mark the dependence as loop carried potentially.
+        const MachineOperand *BaseOp1, *BaseOp2;
+        int64_t Offset1, Offset2;
+        bool Offset1IsScalable, Offset2IsScalable;
+        if (TII->getMemOperandWithOffset(LdMI, BaseOp1, Offset1,
+                                         Offset1IsScalable, TRI) &&
+            TII->getMemOperandWithOffset(MI, BaseOp2, Offset2,
+                                         Offset2IsScalable, TRI)) {
+          if (BaseOp1->isIdenticalTo(*BaseOp2) &&
+              Offset1IsScalable == Offset2IsScalable &&
+              (int)Offset1 < (int)Offset2) {
+            assert(TII->areMemAccessesTriviallyDisjoint(LdMI, MI) &&
+                   "What happened to the chain edge?");
+            SDep Dep(Load.SU, SDep::Barrier);
             Dep.setLatency(1);
             SU.addPred(Dep);
             continue;
           }
-          if (!AA->isNoAlias(
-                  MemoryLocation::getAfter(MMO1->getValue(), MMO1->getAAInfo()),
-                  MemoryLocation::getAfter(MMO2->getValue(),
-                                           MMO2->getAAInfo()))) {
-            SDep Dep(Load, SDep::Barrier);
-            Dep.setLatency(1);
-            SU.addPred(Dep);
-          }
+        }
+        // Second, the more expensive check that uses alias analysis on the
+        // base registers. If they alias, and the load offset is less than
+        // the store offset, the mark the dependence as loop carried.
+        if (Load.isUnknown() || Store.isUnknown()) {
+          SDep Dep(Load.SU, SDep::Barrier);
+          Dep.setLatency(1);
+          SU.addPred(Dep);
+          continue;
+        }
+        if (Load.MemOpValue == Store.MemOpValue &&
+            Load.MemOpOffset <= Store.MemOpOffset) {
+          SDep Dep(Load.SU, SDep::Barrier);
+          Dep.setLatency(1);
+          SU.addPred(Dep);
+          continue;
+        }
+
+        bool IsNoAlias = [&] {
+          if (BAA.isNoAlias(MemoryLocation::getBeforeOrAfter(Load.MemOpValue,
+                                                             Load.AATags),
+                            MemoryLocation::getBeforeOrAfter(Store.MemOpValue,
+                                                             Store.AATags)))
+            return true;
+
+          // AliasAnalysis sometimes gives up on following the underlying
+          // object. In such a case, separate checks for underlying objects may
+          // prove that there are no aliases between two accesses.
+          for (const Value *LoadObj : Load.UnderlyingObjs)
+            for (const Value *StoreObj : Store.UnderlyingObjs)
+              if (!BAA.isNoAlias(
+                      MemoryLocation::getBeforeOrAfter(LoadObj, Load.AATags),
+                      MemoryLocation::getBeforeOrAfter(StoreObj, Store.AATags)))
+                return false;
+
+          return true;
+        }();
+
+        if (!IsNoAlias) {
+          SDep Dep(Load.SU, SDep::Barrier);
+          Dep.setLatency(1);
+          SU.addPred(Dep);
         }
       }
     }
diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
index 9b852c0fd49cf..ac4090252cea0 100644
--- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -608,9 +608,9 @@ static void insertCSRSaves(MachineBasicBlock &SaveBlock,
       MCRegister Reg = CS.getReg();
 
       if (CS.isSpilledToReg()) {
-        BuildMI(SaveBlock, I, DebugLoc(),
-                TII.get(TargetOpcode::COPY), CS.getDstReg())
-          .addReg(Reg, getKillRegState(true));
+        BuildMI(SaveBlock, I, DebugLoc(), TII.get(TargetOpcode::COPY),
+                CS.getDstReg())
+            .addReg(Reg, getKillRegState(true));
       } else {
         const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
         TII.storeRegToStackSlot(SaveBlock, I, Reg, true, CS.getFrameIdx(), RC,
@@ -637,7 +637,7 @@ static void insertCSRRestores(MachineBasicBlock &RestoreBlock,
       MCRegister Reg = CI.getReg();
       if (CI.isSpilledToReg()) {
         BuildMI(RestoreBlock, I, DebugLoc(), TII.get(TargetOpcode::COPY), Reg)
-          .addReg(CI.getDstReg(), getKillRegState(true));
+            .addReg(CI.getDstReg(), getKillRegState(true));
       } else {
         const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
         TII.loadRegFromStackSlot(RestoreBlock, I, Reg, CI.getFrameIdx(), RC,
diff --git a/llvm/lib/CodeGen/SelectOptimize.cpp b/llvm/lib/CodeGen/SelectOptimize.cpp
index 00148b075134a..13ed8f28d5507 100644
--- a/llvm/lib/CodeGen/SelectOptimize.cpp
+++ b/llvm/lib/CodeGen/SelectOptimize.cpp
@@ -206,7 +206,7 @@ class SelectOptimizeImpl {
           getI()->getOpcode(), I->getType(), TargetTransformInfo::TCK_Latency,
           {TargetTransformInfo::OK_AnyValue, TargetTransformInfo::OP_None},
           {TTI::OK_UniformConstantValue, TTI::OP_PowerOf2});
-      auto TotalCost = Scaled64::get(*Cost.getValue());
+      auto TotalCost = Scaled64::get(Cost.getValue());
       if (auto *OpI = dyn_cast<Instruction>(I->getOperand(1 - CondIdx))) {
         auto It = InstCostMap.find(OpI);
         if (It != InstCostMap.end())
@@ -1380,8 +1380,8 @@ std::optional<uint64_t>
 SelectOptimizeImpl::computeInstCost(const Instruction *I) {
   InstructionCost ICost =
       TTI->getInstructionCost(I, TargetTransformInfo::TCK_Latency);
-  if (auto OC = ICost.getValue())
-    return std::optional<uint64_t>(*OC);
+  if (ICost.isValid())
+    return std::optional<uint64_t>(ICost.getValue());
   return std::nullopt;
 }
 
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index b571f635c744f..fc673d7642fd0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -6037,7 +6037,10 @@ SDValue DAGCombiner::hoistLogicOpWithSameOpcodeHands(SDNode *N) {
         LegalTypes && !TLI.isTypeDesirableForOp(LogicOpcode, XVT))
       return SDValue();
     // logic_op (hand_op X), (hand_op Y) --> hand_op (logic_op X, Y)
-    SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
+    SDNodeFlags LogicFlags;
+    LogicFlags.setDisjoint(N->getFlags().hasDisjoint() &&
+                           ISD::isExtOpcode(HandOpcode));
+    SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y, LogicFlags);
     if (HandOpcode == ISD::SIGN_EXTEND_INREG)
       return DAG.getNode(HandOpcode, DL, VT, Logic, N0.getOperand(1));
     return DAG.getNode(HandOpcode, DL, VT, Logic);
@@ -6690,7 +6693,7 @@ bool DAGCombiner::isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN,
       !TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))
     return false;
 
-  if (!TLI.shouldReduceLoadWidth(LoadN, ISD::ZEXTLOAD, ExtVT))
+  if (!TLI.shouldReduceLoadWidth(LoadN, ISD::ZEXTLOAD, ExtVT, /*ByteOffset=*/0))
     return false;
 
   return true;
@@ -6701,9 +6704,11 @@ bool DAGCombiner::isLegalNarrowLdSt(LSBaseSDNode *LDST,
                                     unsigned ShAmt) {
   if (!LDST)
     return false;
+
   // Only allow byte offsets.
   if (ShAmt % 8)
     return false;
+  const unsigned ByteShAmt = ShAmt / 8;
 
   // Do not generate loads of non-round integer types since these can
   // be expensive (and would be wrong if the type is not byte sized).
@@ -6727,8 +6732,6 @@ bool DAGCombiner::isLegalNarrowLdSt(LSBaseSDNode *LDST,
 
   // Ensure that this isn't going to produce an unsupported memory access.
   if (ShAmt) {
-    assert(ShAmt % 8 == 0 && "ShAmt is byte offset");
-    const unsigned ByteShAmt = ShAmt / 8;
     const Align LDSTAlign = LDST->getAlign();
     const Align NarrowAlign = commonAlignment(LDSTAlign, ByteShAmt);
     if (!TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), MemVT,
@@ -6768,7 +6771,7 @@ bool DAGCombiner::isLegalNarrowLdSt(LSBaseSDNode *LDST,
         Load->getMemoryVT().getSizeInBits() < MemVT.getSizeInBits() + ShAmt)
       return false;
 
-    if (!TLI.shouldReduceLoadWidth(Load, ExtType, MemVT))
+    if (!TLI.shouldReduceLoadWidth(Load, ExtType, MemVT, ByteShAmt))
       return false;
   } else {
     assert(isa<StoreSDNode>(LDST) && "It is not a Load nor a Store SDNode");
@@ -12641,8 +12644,13 @@ SDValue DAGCombiner::visitPARTIAL_REDUCE_MLA(SDNode *N) {
   if (LHSExtOpVT != RHSExtOp.getValueType() || LHSOpcode != RHSOpcode)
     return SDValue();
 
-  // FIXME: Add a check to only perform the DAG combine if there is lowering
-  // provided by the target
+  // Only perform the DAG combine if there is custom lowering provided by the
+  // target
+  auto *Context = DAG.getContext();
+  if (!TLI.isPartialReduceMLALegalOrCustom(
+          TLI.getTypeToTransformTo(*Context, N->getValueType(0)),
+          TLI.getTypeToTransformTo(*Context, LHSExtOpVT)))
+    return SDValue();
 
   bool ExtIsSigned = LHSOpcode == ISD::SIGN_EXTEND;
 
@@ -25235,7 +25243,8 @@ static SDValue narrowExtractedVectorBinOp(SDNode *Extract, SelectionDAG &DAG,
 /// If we are extracting a subvector from a wide vector load, convert to a
 /// narrow load to eliminate the extraction:
 /// (extract_subvector (load wide vector)) --> (load narrow vector)
-static SDValue narrowExtractedVectorLoad(SDNode *Extract, SelectionDAG &DAG) {
+static SDValue narrowExtractedVectorLoad(SDNode *Extract, const SDLoc &DL,
+                                         SelectionDAG &DAG) {
   // TODO: Add support for big-endian. The offset calculation must be adjusted.
   if (DAG.getDataLayout().isBigEndian())
     return SDValue();
@@ -25265,15 +25274,16 @@ static SDValue narrowExtractedVectorLoad(SDNode *Extract, SelectionDAG &DAG) {
 
   // It's fine to use TypeSize here as we know the offset will not be negative.
   TypeSize Offset = VT.getStoreSize() * (Index / NumElts);
+  std::optional<unsigned> ByteOffset;
+  if (Offset.isFixed())
+    ByteOffset = Offset.getFixedValue();
 
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
-  if (!TLI.shouldReduceLoadWidth(Ld, Ld->getExtensionType(), VT))
+  if (!TLI.shouldReduceLoadWidth(Ld, Ld->getExtensionType(), VT, ByteOffset))
     return SDValue();
 
   // The narrow load will be offset from the base address of the old load if
   // we are extracting from something besides index 0 (little-endian).
-  SDLoc DL(Extract);
-
   // TODO: Use "BaseIndexOffset" to make this more effective.
   SDValue NewAddr = DAG.getMemBasePlusOffset(Ld->getBasePtr(), Offset, DL);
 
@@ -25457,7 +25467,7 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) {
     return DAG.getUNDEF(NVT);
 
   if (TLI.isOperationLegalOrCustomOrPromote(ISD::LOAD, NVT))
-    if (SDValue NarrowLoad = narrowExtractedVectorLoad(N, DAG))
+    if (SDValue NarrowLoad = narrowExtractedVectorLoad(N, DL, DAG))
       return NarrowLoad;
 
   // Combine an extract of an extract into a single extract_subvector.
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index b596f6b8d6ce2..3e47136edbefc 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -129,7 +129,8 @@ class SelectionDAGLegalize {
                                      ArrayRef<int> Mask) const;
 
   std::pair<SDValue, SDValue> ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
-                        TargetLowering::ArgListTy &&Args, bool isSigned);
+                                            TargetLowering::ArgListTy &&Args,
+                                            bool IsSigned, EVT RetVT);
   std::pair<SDValue, SDValue> ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
 
   void ExpandFPLibCall(SDNode *Node, RTLIB::Libcall LC,
@@ -150,6 +151,9 @@ class SelectionDAGLegalize {
                           RTLIB::Libcall Call_F80, RTLIB::Libcall Call_F128,
                           RTLIB::Libcall Call_PPCF128,
                           SmallVectorImpl<SDValue> &Results);
+  SDValue ExpandBitCountingLibCall(SDNode *Node, RTLIB::Libcall CallI32,
+                                   RTLIB::Libcall CallI64,
+                                   RTLIB::Libcall CallI128);
   void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
   void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
 
@@ -2114,9 +2118,10 @@ SDValue SelectionDAGLegalize::ExpandSPLAT_VECTOR(SDNode *Node) {
 // register, return the lo part and set the hi part to the by-reg argument in
 // the first.  If it does fit into a single register, return the result and
 // leave the Hi part unset.
-std::pair<SDValue, SDValue> SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
-                                            TargetLowering::ArgListTy &&Args,
-                                            bool isSigned) {
+std::pair<SDValue, SDValue>
+SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
+                                    TargetLowering::ArgListTy &&Args,
+                                    bool IsSigned, EVT RetVT) {
   EVT CodePtrTy = TLI.getPointerTy(DAG.getDataLayout());
   SDValue Callee;
   if (const char *LibcallName = TLI.getLibcallName(LC))
@@ -2127,7 +2132,6 @@ std::pair<SDValue, SDValue> SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall L
                                 Node->getOperationName(&DAG));
   }
 
-  EVT RetVT = Node->getValueType(0);
   Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
 
   // By default, the input chain to this libcall is the entry node of the
@@ -2147,7 +2151,7 @@ std::pair<SDValue, SDValue> SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall L
     InChain = TCChain;
 
   TargetLowering::CallLoweringInfo CLI(DAG);
-  bool signExtend = TLI.shouldSignExtendTypeInLibCall(RetTy, isSigned);
+  bool signExtend = TLI.shouldSignExtendTypeInLibCall(RetTy, IsSigned);
   CLI.setDebugLoc(SDLoc(Node))
       .setChain(InChain)
       .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
@@ -2183,7 +2187,8 @@ std::pair<SDValue, SDValue> SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall L
     Args.push_back(Entry);
   }
 
-  return ExpandLibCall(LC, Node, std::move(Args), isSigned);
+  return ExpandLibCall(LC, Node, std::move(Args), isSigned,
+                       Node->getValueType(0));
 }
 
 void SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
@@ -2259,6 +2264,50 @@ void SelectionDAGLegalize::ExpandArgFPLibCall(SDNode* Node,
   ExpandFPLibCall(Node, LC, Results);
 }
 
+SDValue SelectionDAGLegalize::ExpandBitCountingLibCall(
+    SDNode *Node, RTLIB::Libcall CallI32, RTLIB::Libcall CallI64,
+    RTLIB::Libcall CallI128) {
+  RTLIB::Libcall LC;
+  switch (Node->getSimpleValueType(0).SimpleTy) {
+  default:
+    llvm_unreachable("Unexpected request for libcall!");
+  case MVT::i32:
+    LC = CallI32;
+    break;
+  case MVT::i64:
+    LC = CallI64;
+    break;
+  case MVT::i128:
+    LC = CallI128;
+    break;
+  }
+
+  // Bit-counting libcalls have one unsigned argument and return `int`.
+  // Note that `int` may be illegal on this target; ExpandLibCall will
+  // take care of promoting it to a legal type.
+  SDValue Op = Node->getOperand(0);
+  EVT IntVT =
+      EVT::getIntegerVT(*DAG.getContext(), DAG.getLibInfo().getIntSize());
+
+  TargetLowering::ArgListEntry Arg;
+  EVT ArgVT = Op.getValueType();
+  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
+  Arg.Node = Op;
+  Arg.Ty = ArgTy;
+  Arg.IsSExt = TLI.shouldSignExtendTypeInLibCall(ArgTy, /*IsSigned=*/false);
+  Arg.IsZExt = !Arg.IsSExt;
+
+  SDValue Res = ExpandLibCall(LC, Node, TargetLowering::ArgListTy{Arg},
+                              /*IsSigned=*/true, IntVT)
+                    .first;
+
+  // If ExpandLibCall created a tail call, the result was already
+  // of the correct type. Otherwise, we need to sign extend it.
+  if (Res.getValueType() != MVT::Other)
+    Res = DAG.getSExtOrTrunc(Res, SDLoc(Node), Node->getValueType(0));
+  return Res;
+}
+
 /// Issue libcalls to __{u}divmod to compute div / rem pairs.
 void
 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
@@ -4993,19 +5042,12 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
                                        RTLIB::MUL_I64, RTLIB::MUL_I128));
     break;
   case ISD::CTLZ_ZERO_UNDEF:
-    switch (Node->getSimpleValueType(0).SimpleTy) {
-    default:
-      llvm_unreachable("LibCall explicitly requested, but not available");
-    case MVT::i32:
-      Results.push_back(ExpandLibCall(RTLIB::CTLZ_I32, Node, false).first);
-      break;
-    case MVT::i64:
-      Results.push_back(ExpandLibCall(RTLIB::CTLZ_I64, Node, false).first);
-      break;
-    case MVT::i128:
-      Results.push_back(ExpandLibCall(RTLIB::CTLZ_I128, Node, false).first);
-      break;
-    }
+    Results.push_back(ExpandBitCountingLibCall(
+        Node, RTLIB::CTLZ_I32, RTLIB::CTLZ_I64, RTLIB::CTLZ_I128));
+    break;
+  case ISD::CTPOP:
+    Results.push_back(ExpandBitCountingLibCall(
+        Node, RTLIB::CTPOP_I32, RTLIB::CTPOP_I64, RTLIB::CTPOP_I128));
     break;
   case ISD::RESET_FPENV: {
     // It is legalized to call 'fesetenv(FE_DFL_ENV)'. On most targets
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 53244a990a864..83dd519fb2ea4 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -4012,15 +4012,35 @@ void DAGTypeLegalizer::ExpandIntRes_ABD(SDNode *N, SDValue &Lo, SDValue &Hi) {
   SplitInteger(Result, Lo, Hi);
 }
 
-void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
-                                          SDValue &Lo, SDValue &Hi) {
-  SDLoc dl(N);
+void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, SDValue &Lo, SDValue &Hi) {
+  SDValue Op = N->getOperand(0);
+  EVT VT = N->getValueType(0);
+  SDLoc DL(N);
+
+  if (TLI.getOperationAction(ISD::CTPOP, VT) == TargetLoweringBase::LibCall) {
+    RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
+    if (VT == MVT::i32)
+      LC = RTLIB::CTPOP_I32;
+    else if (VT == MVT::i64)
+      LC = RTLIB::CTPOP_I64;
+    else if (VT == MVT::i128)
+      LC = RTLIB::CTPOP_I128;
+    assert(LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC) &&
+           "LibCall explicitly requested, but not available");
+    TargetLowering::MakeLibCallOptions CallOptions;
+    EVT IntVT =
+        EVT::getIntegerVT(*DAG.getContext(), DAG.getLibInfo().getIntSize());
+    SDValue Res = TLI.makeLibCall(DAG, LC, IntVT, Op, CallOptions, DL).first;
+    SplitInteger(DAG.getSExtOrTrunc(Res, DL, VT), Lo, Hi);
+    return;
+  }
+
   // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
-  GetExpandedInteger(N->getOperand(0), Lo, Hi);
+  GetExpandedInteger(Op, Lo, Hi);
   EVT NVT = Lo.getValueType();
-  Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
-                   DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
-  Hi = DAG.getConstant(0, dl, NVT);
+  Lo = DAG.getNode(ISD::ADD, DL, NVT, DAG.getNode(ISD::CTPOP, DL, NVT, Lo),
+                   DAG.getNode(ISD::CTPOP, DL, NVT, Hi));
+  Hi = DAG.getConstant(0, DL, NVT);
 }
 
 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index 27bde7b96c857..c61e5b263a967 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -469,8 +469,6 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
   case ISD::VECTOR_COMPRESS:
   case ISD::SCMP:
   case ISD::UCMP:
-  case ISD::PARTIAL_REDUCE_UMLA:
-  case ISD::PARTIAL_REDUCE_SMLA:
     Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
     break;
   case ISD::SMULFIX:
@@ -530,6 +528,11 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
       Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
     break;
   }
+  case ISD::PARTIAL_REDUCE_UMLA:
+  case ISD::PARTIAL_REDUCE_SMLA:
+    Action = TLI.getPartialReduceMLAAction(Node->getValueType(0),
+                                           Node->getOperand(1).getValueType());
+    break;
 
 #define BEGIN_REGISTER_VP_SDNODE(VPID, LEGALPOS, ...)                          \
   case ISD::VPID: {                                                            \
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index a41efd58ce4e4..cf88c1f4ae937 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -967,6 +967,9 @@ static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) {
   case ISD::INTRINSIC_W_CHAIN:
     // Handled by MemIntrinsicSDNode check after the switch.
     break;
+  case ISD::MDNODE_SDNODE:
+    ID.AddPointer(cast<MDNodeSDNode>(N)->getMD());
+    break;
   } // end switch (N->getOpcode())
 
   // MemIntrinsic nodes could also have subclass data, address spaces, and flags
@@ -9021,7 +9024,9 @@ SDValue SelectionDAG::getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT,
 
   CSEMap.InsertNode(N, IP);
   InsertNode(N);
-  return SDValue(N, 0);
+  SDValue V(N, 0);
+  NewSDValueDbgMsg(V, "Creating new node: ", this);
+  return V;
 }
 
 SDValue SelectionDAG::getAtomicCmpSwap(unsigned Opcode, const SDLoc &dl,
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 3995216e3d689..6930b54ddb14a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -4726,8 +4726,6 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
         // for the narrowed load.
         for (unsigned width = 8; width < origWidth; width *= 2) {
           EVT newVT = EVT::getIntegerVT(*DAG.getContext(), width);
-          if (!shouldReduceLoadWidth(Lod, ISD::NON_EXTLOAD, newVT))
-            continue;
           APInt newMask = APInt::getLowBitsSet(maskWidth, width);
           // Avoid accessing any padding here for now (we could use memWidth
           // instead of origWidth here otherwise).
@@ -4737,8 +4735,11 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
               unsigned ptrOffset =
                   Layout.isLittleEndian() ? offset : memWidth - width - offset;
               unsigned IsFast = 0;
+              assert((ptrOffset % 8) == 0 && "Non-Bytealigned pointer offset");
               Align NewAlign = commonAlignment(Lod->getAlign(), ptrOffset / 8);
-              if (allowsMemoryAccess(
+              if (shouldReduceLoadWidth(Lod, ISD::NON_EXTLOAD, newVT,
+                                        ptrOffset / 8) &&
+                  allowsMemoryAccess(
                       *DAG.getContext(), Layout, newVT, Lod->getAddressSpace(),
                       NewAlign, Lod->getMemOperand()->getFlags(), &IsFast) &&
                   IsFast) {
@@ -9390,8 +9391,9 @@ SDValue TargetLowering::expandCTTZ(SDNode *Node, SelectionDAG &DAG) const {
                         !isOperationLegalOrCustomOrPromote(ISD::XOR, VT)))
     return SDValue();
 
-  // Emit Table Lookup if ISD::CTLZ and ISD::CTPOP are not legal.
-  if (!VT.isVector() && isOperationExpand(ISD::CTPOP, VT) &&
+  // Emit Table Lookup if ISD::CTPOP used in the fallback path below is going
+  // to be expanded or converted to a libcall.
+  if (!VT.isVector() && !isOperationLegalOrCustomOrPromote(ISD::CTPOP, VT) &&
       !isOperationLegal(ISD::CTLZ, VT))
     if (SDValue V = CTTZTableLookup(Node, DAG, dl, VT, Op, NumBitsPerElt))
       return V;
@@ -12175,17 +12177,17 @@ SDValue TargetLowering::scalarizeExtractedVectorLoad(EVT ResultVT,
 
   ISD::LoadExtType ExtTy =
       ResultVT.bitsGT(VecEltVT) ? ISD::EXTLOAD : ISD::NON_EXTLOAD;
-  if (!isOperationLegalOrCustom(ISD::LOAD, VecEltVT) ||
-      !shouldReduceLoadWidth(OriginalLoad, ExtTy, VecEltVT))
+  if (!isOperationLegalOrCustom(ISD::LOAD, VecEltVT))
     return SDValue();
 
+  std::optional<unsigned> ByteOffset;
   Align Alignment = OriginalLoad->getAlign();
   MachinePointerInfo MPI;
   if (auto *ConstEltNo = dyn_cast<ConstantSDNode>(EltNo)) {
     int Elt = ConstEltNo->getZExtValue();
-    unsigned PtrOff = VecEltVT.getSizeInBits() * Elt / 8;
-    MPI = OriginalLoad->getPointerInfo().getWithOffset(PtrOff);
-    Alignment = commonAlignment(Alignment, PtrOff);
+    ByteOffset = VecEltVT.getSizeInBits() * Elt / 8;
+    MPI = OriginalLoad->getPointerInfo().getWithOffset(*ByteOffset);
+    Alignment = commonAlignment(Alignment, *ByteOffset);
   } else {
     // Discard the pointer info except the address space because the memory
     // operand can't represent this new access since the offset is variable.
@@ -12193,6 +12195,9 @@ SDValue TargetLowering::scalarizeExtractedVectorLoad(EVT ResultVT,
     Alignment = commonAlignment(Alignment, VecEltVT.getSizeInBits() / 8);
   }
 
+  if (!shouldReduceLoadWidth(OriginalLoad, ExtTy, VecEltVT, ByteOffset))
+    return SDValue();
+
   unsigned IsFast = 0;
   if (!allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VecEltVT,
                           OriginalLoad->getAddressSpace(), Alignment,
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index 483e52d16d537..c85f0c71ef25f 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -843,10 +843,6 @@ void TargetLoweringBase::initActions() {
     setOperationAction(ISD::GET_FPENV, VT, Expand);
     setOperationAction(ISD::SET_FPENV, VT, Expand);
     setOperationAction(ISD::RESET_FPENV, VT, Expand);
-
-    // PartialReduceMLA operations default to expand.
-    setOperationAction({ISD::PARTIAL_REDUCE_UMLA, ISD::PARTIAL_REDUCE_SMLA}, VT,
-                       Expand);
   }
 
   // Most targets ignore the @llvm.prefetch intrinsic.
diff --git a/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp b/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
index f032d5cb30f23..cca99591c8c45 100644
--- a/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
+++ b/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
@@ -662,7 +662,18 @@ bool RuntimeDyldELF::resolveLoongArch64ShortBranch(
   }
   uint64_t Offset = RelI->getOffset();
   uint64_t SourceAddress = Sections[SectionID].getLoadAddressWithOffset(Offset);
-  if (!isInt<28>(Address + Value.Addend - SourceAddress))
+  uint64_t Delta = Address + Value.Addend - SourceAddress;
+  // Normal call
+  if (RelI->getType() == ELF::R_LARCH_B26) {
+    if (!isInt<28>(Delta))
+      return false;
+    resolveRelocation(Sections[SectionID], Offset, Address, RelI->getType(),
+                      Value.Addend);
+    return true;
+  }
+  // Medium call: R_LARCH_CALL36
+  // Range: [-128G - 0x20000, +128G - 0x20000)
+  if (((int64_t)Delta + 0x20000) != llvm::SignExtend64(Delta + 0x20000, 38))
     return false;
   resolveRelocation(Sections[SectionID], Offset, Address, RelI->getType(),
                     Value.Addend);
@@ -1743,7 +1754,8 @@ RuntimeDyldELF::processRelocationRef(
       processSimpleRelocation(SectionID, Offset, RelType, Value);
     }
   } else if (Arch == Triple::loongarch64) {
-    if (RelType == ELF::R_LARCH_B26 && MemMgr.allowStubAllocation()) {
+    if ((RelType == ELF::R_LARCH_B26 || RelType == ELF::R_LARCH_CALL36) &&
+        MemMgr.allowStubAllocation()) {
       resolveLoongArch64Branch(SectionID, Value, RelI, Stubs);
     } else if (RelType == ELF::R_LARCH_GOT_PC_HI20 ||
                RelType == ELF::R_LARCH_GOT_PC_LO12) {
diff --git a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
index 439c46645c342..be05f01c94603 100644
--- a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+++ b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
@@ -1314,8 +1314,7 @@ static void targetParallelCallback(
       /* if expression */ Cond,
       /* number of threads */ NumThreads ? NumThreads : Builder.getInt32(-1),
       /* Proc bind */ Builder.getInt32(-1),
-      /* outlined function */
-      Builder.CreateBitCast(&OutlinedFn, OMPIRBuilder->ParallelTaskPtr),
+      /* outlined function */ &OutlinedFn,
       /* wrapper function */ NullPtrValue,
       /* arguments of the outlined funciton*/ Args,
       /* number of arguments */ Builder.getInt64(NumCapturedVars)};
@@ -1389,9 +1388,8 @@ hostParallelCallback(OpenMPIRBuilder *OMPIRBuilder, Function &OutlinedFn,
   Builder.SetInsertPoint(CI);
 
   // Build call __kmpc_fork_call[_if](Ident, n, microtask, var1, .., varn);
-  Value *ForkCallArgs[] = {
-      Ident, Builder.getInt32(NumCapturedVars),
-      Builder.CreateBitCast(&OutlinedFn, OMPIRBuilder->ParallelTaskPtr)};
+  Value *ForkCallArgs[] = {Ident, Builder.getInt32(NumCapturedVars),
+                           &OutlinedFn};
 
   SmallVector<Value *, 16> RealArgs;
   RealArgs.append(std::begin(ForkCallArgs), std::end(ForkCallArgs));
@@ -1408,8 +1406,6 @@ hostParallelCallback(OpenMPIRBuilder *OMPIRBuilder, Function &OutlinedFn,
     Value *NullPtrValue = Constant::getNullValue(PtrTy);
     RealArgs.push_back(NullPtrValue);
   }
-  if (IfCondition && RealArgs.back()->getType() != PtrTy)
-    RealArgs.back() = Builder.CreateBitCast(RealArgs.back(), PtrTy);
 
   Builder.CreateCall(RTLFn, RealArgs);
 
@@ -4494,10 +4490,11 @@ getKmpcForStaticLoopForType(Type *Ty, OpenMPIRBuilder *OMPBuilder,
 
 // Inserts a call to proper OpenMP Device RTL function which handles
 // loop worksharing.
-static void createTargetLoopWorkshareCall(
-    OpenMPIRBuilder *OMPBuilder, WorksharingLoopType LoopType,
-    BasicBlock *InsertBlock, Value *Ident, Value *LoopBodyArg,
-    Type *ParallelTaskPtr, Value *TripCount, Function &LoopBodyFn) {
+static void createTargetLoopWorkshareCall(OpenMPIRBuilder *OMPBuilder,
+                                          WorksharingLoopType LoopType,
+                                          BasicBlock *InsertBlock, Value *Ident,
+                                          Value *LoopBodyArg, Value *TripCount,
+                                          Function &LoopBodyFn) {
   Type *TripCountTy = TripCount->getType();
   Module &M = OMPBuilder->M;
   IRBuilder<> &Builder = OMPBuilder->Builder;
@@ -4505,7 +4502,7 @@ static void createTargetLoopWorkshareCall(
       getKmpcForStaticLoopForType(TripCountTy, OMPBuilder, LoopType);
   SmallVector<Value *, 8> RealArgs;
   RealArgs.push_back(Ident);
-  RealArgs.push_back(Builder.CreateBitCast(&LoopBodyFn, ParallelTaskPtr));
+  RealArgs.push_back(&LoopBodyFn);
   RealArgs.push_back(LoopBodyArg);
   RealArgs.push_back(TripCount);
   if (LoopType == WorksharingLoopType::DistributeStaticLoop) {
@@ -4529,12 +4526,10 @@ static void createTargetLoopWorkshareCall(
   Builder.CreateCall(RTLFn, RealArgs);
 }
 
-static void
-workshareLoopTargetCallback(OpenMPIRBuilder *OMPIRBuilder,
-                            CanonicalLoopInfo *CLI, Value *Ident,
-                            Function &OutlinedFn, Type *ParallelTaskPtr,
-                            const SmallVector<Instruction *, 4> &ToBeDeleted,
-                            WorksharingLoopType LoopType) {
+static void workshareLoopTargetCallback(
+    OpenMPIRBuilder *OMPIRBuilder, CanonicalLoopInfo *CLI, Value *Ident,
+    Function &OutlinedFn, const SmallVector<Instruction *, 4> &ToBeDeleted,
+    WorksharingLoopType LoopType) {
   IRBuilder<> &Builder = OMPIRBuilder->Builder;
   BasicBlock *Preheader = CLI->getPreheader();
   Value *TripCount = CLI->getTripCount();
@@ -4581,8 +4576,7 @@ workshareLoopTargetCallback(OpenMPIRBuilder *OMPIRBuilder,
   OutlinedFnCallInstruction->eraseFromParent();
 
   createTargetLoopWorkshareCall(OMPIRBuilder, LoopType, Preheader, Ident,
-                                LoopBodyArg, ParallelTaskPtr, TripCount,
-                                OutlinedFn);
+                                LoopBodyArg, TripCount, OutlinedFn);
 
   for (auto &ToBeDeletedItem : ToBeDeleted)
     ToBeDeletedItem->eraseFromParent();
@@ -4676,8 +4670,8 @@ OpenMPIRBuilder::applyWorkshareLoopTarget(DebugLoc DL, CanonicalLoopInfo *CLI,
   //
   OI.PostOutlineCB = [=, ToBeDeletedVec =
                              std::move(ToBeDeleted)](Function &OutlinedFn) {
-    workshareLoopTargetCallback(this, CLI, Ident, OutlinedFn, ParallelTaskPtr,
-                                ToBeDeletedVec, LoopType);
+    workshareLoopTargetCallback(this, CLI, Ident, OutlinedFn, ToBeDeletedVec,
+                                LoopType);
   };
   addOutlineInfo(std::move(OI));
   return CLI->getAfterIP();
@@ -8126,7 +8120,7 @@ Expected<Function *> OpenMPIRBuilder::emitUserDefinedMapper(
   // Convert the size in bytes into the number of array elements.
   TypeSize ElementSize = M.getDataLayout().getTypeStoreSize(ElemTy);
   Size = Builder.CreateExactUDiv(Size, Builder.getInt64(ElementSize));
-  Value *PtrBegin = Builder.CreateBitCast(BeginIn, Builder.getPtrTy());
+  Value *PtrBegin = BeginIn;
   Value *PtrEnd = Builder.CreateGEP(ElemTy, PtrBegin, Size);
 
   // Emit array initiation if this is an array section and \p MapType indicates
@@ -8170,10 +8164,8 @@ Expected<Function *> OpenMPIRBuilder::emitUserDefinedMapper(
 
   // Fill up the runtime mapper handle for all components.
   for (unsigned I = 0; I < Info->BasePointers.size(); ++I) {
-    Value *CurBaseArg =
-        Builder.CreateBitCast(Info->BasePointers[I], Builder.getPtrTy());
-    Value *CurBeginArg =
-        Builder.CreateBitCast(Info->Pointers[I], Builder.getPtrTy());
+    Value *CurBaseArg = Info->BasePointers[I];
+    Value *CurBeginArg = Info->Pointers[I];
     Value *CurSizeArg = Info->Sizes[I];
     Value *CurNameArg = Info->Names.size()
                             ? Info->Names[I]
diff --git a/llvm/lib/IR/Value.cpp b/llvm/lib/IR/Value.cpp
index 0eaf75b7bfaec..aa97b70f21aeb 100644
--- a/llvm/lib/IR/Value.cpp
+++ b/llvm/lib/IR/Value.cpp
@@ -441,7 +441,6 @@ void Value::takeName(Value *V) {
     ST->reinsertValue(this);
 }
 
-#ifndef NDEBUG
 std::string Value::getNameOrAsOperand() const {
   if (!getName().empty())
     return std::string(getName());
@@ -451,7 +450,6 @@ std::string Value::getNameOrAsOperand() const {
   printAsOperand(OS, false);
   return OS.str();
 }
-#endif
 
 void Value::assertModuleIsMaterializedImpl() const {
 #ifndef NDEBUG
diff --git a/llvm/lib/MC/MCParser/MasmParser.cpp b/llvm/lib/MC/MCParser/MasmParser.cpp
index f758020566465..51ac19c623732 100644
--- a/llvm/lib/MC/MCParser/MasmParser.cpp
+++ b/llvm/lib/MC/MCParser/MasmParser.cpp
@@ -765,6 +765,19 @@ class MasmParser : public MCAsmParser {
   std::optional<std::string> evaluateBuiltinTextMacro(BuiltinSymbol Symbol,
                                                       SMLoc StartLoc);
 
+  // Generic (target and platform independent) directive parsing.
+  enum BuiltinFunction {
+    BI_NO_FUNCTION, // Placeholder
+    BI_CATSTR,
+  };
+
+  /// Maps builtin name --> BuiltinFunction enum, for builtins handled by this
+  /// class.
+  StringMap<BuiltinFunction> BuiltinFunctionMap;
+
+  bool evaluateBuiltinMacroFunction(BuiltinFunction Function, StringRef Name,
+                                    std::string &Res);
+
   // ".ascii", ".asciz", ".string"
   bool parseDirectiveAscii(StringRef IDVal, bool ZeroTerminated);
 
@@ -946,7 +959,7 @@ class MasmParser : public MCAsmParser {
   bool parseDirectiveEcho(SMLoc DirectiveLoc);
 
   void initializeDirectiveKindMap();
-  void initializeBuiltinSymbolMap();
+  void initializeBuiltinSymbolMaps();
 };
 
 } // end anonymous namespace
@@ -986,7 +999,7 @@ MasmParser::MasmParser(SourceMgr &SM, MCContext &Ctx, MCStreamer &Out,
 
   initializeDirectiveKindMap();
   PlatformParser->Initialize(*this);
-  initializeBuiltinSymbolMap();
+  initializeBuiltinSymbolMaps();
 
   NumOfMacroInstantiations = 0;
 }
@@ -1071,15 +1084,25 @@ bool MasmParser::expandMacros() {
   }
 
   std::optional<std::string> ExpandedValue;
-  auto BuiltinIt = BuiltinSymbolMap.find(IDLower);
-  if (BuiltinIt != BuiltinSymbolMap.end()) {
+
+  if (auto BuiltinIt = BuiltinSymbolMap.find(IDLower);
+      BuiltinIt != BuiltinSymbolMap.end()) {
     ExpandedValue =
         evaluateBuiltinTextMacro(BuiltinIt->getValue(), Tok.getLoc());
-  } else {
-    auto VarIt = Variables.find(IDLower);
-    if (VarIt != Variables.end() && VarIt->getValue().IsText) {
-      ExpandedValue = VarIt->getValue().TextValue;
+  } else if (auto BuiltinFuncIt = BuiltinFunctionMap.find(IDLower);
+             BuiltinFuncIt != BuiltinFunctionMap.end()) {
+    StringRef Name;
+    if (parseIdentifier(Name)) {
+      return true;
+    }
+    std::string Res;
+    if (evaluateBuiltinMacroFunction(BuiltinFuncIt->getValue(), Name, Res)) {
+      return true;
     }
+    ExpandedValue = Res;
+  } else if (auto VarIt = Variables.find(IDLower);
+             VarIt != Variables.end() && VarIt->getValue().IsText) {
+    ExpandedValue = VarIt->getValue().TextValue;
   }
 
   if (!ExpandedValue)
@@ -3104,6 +3127,18 @@ bool MasmParser::parseTextItem(std::string &Data) {
         continue;
       }
 
+      // Try to resolve as a built-in macro function
+      auto BuiltinFuncIt = BuiltinFunctionMap.find(ID.lower());
+      if (BuiltinFuncIt != BuiltinFunctionMap.end()) {
+        Data.clear();
+        if (evaluateBuiltinMacroFunction(BuiltinFuncIt->getValue(), ID, Data)) {
+          return true;
+        }
+        ID = StringRef(Data);
+        Expanded = true;
+        continue;
+      }
+
       // Try to resolve as a variable text macro
       auto VarIt = Variables.find(ID.lower());
       if (VarIt != Variables.end()) {
@@ -6110,7 +6145,7 @@ bool MasmParser::parseMSInlineAsm(
   return false;
 }
 
-void MasmParser::initializeBuiltinSymbolMap() {
+void MasmParser::initializeBuiltinSymbolMaps() {
   // Numeric built-ins (supported in all versions)
   BuiltinSymbolMap["@version"] = BI_VERSION;
   BuiltinSymbolMap["@line"] = BI_LINE;
@@ -6122,6 +6157,9 @@ void MasmParser::initializeBuiltinSymbolMap() {
   BuiltinSymbolMap["@filename"] = BI_FILENAME;
   BuiltinSymbolMap["@curseg"] = BI_CURSEG;
 
+  // Function built-ins (supported in all versions)
+  BuiltinFunctionMap["@catstr"] = BI_CATSTR;
+
   // Some built-ins exist only for MASM32 (32-bit x86)
   if (getContext().getSubtargetInfo()->getTargetTriple().getArch() ==
       Triple::x86) {
@@ -6195,6 +6233,48 @@ MasmParser::evaluateBuiltinTextMacro(BuiltinSymbol Symbol, SMLoc StartLoc) {
   llvm_unreachable("unhandled built-in symbol");
 }
 
+bool MasmParser::evaluateBuiltinMacroFunction(BuiltinFunction Function,
+                                              StringRef Name,
+                                              std::string &Res) {
+  if (parseToken(AsmToken::LParen, "invoking macro function '" + Name +
+                                       "' requires arguments in parentheses")) {
+    return true;
+  }
+
+  MCAsmMacroParameters P;
+  switch (Function) {
+  default:
+    return true;
+  case BI_CATSTR:
+    break;
+  }
+  MCAsmMacro M(Name, "", P, {}, true);
+
+  MCAsmMacroArguments A;
+  if (parseMacroArguments(&M, A, AsmToken::RParen) || parseRParen()) {
+    return true;
+  }
+
+  switch (Function) {
+  default:
+    llvm_unreachable("unhandled built-in function");
+  case BI_CATSTR: {
+    for (const MCAsmMacroArgument &Arg : A) {
+      for (const AsmToken &Tok : Arg) {
+        if (Tok.is(AsmToken::String)) {
+          Res.append(Tok.getStringContents());
+        } else {
+          Res.append(Tok.getString());
+        }
+      }
+    }
+    return false;
+  }
+  }
+  llvm_unreachable("unhandled built-in function");
+  return true;
+}
+
 /// Create an MCAsmParser instance.
 MCAsmParser *llvm::createMCMasmParser(SourceMgr &SM, MCContext &C,
                                       MCStreamer &Out, const MCAsmInfo &MAI,
diff --git a/llvm/lib/ProfileData/CMakeLists.txt b/llvm/lib/ProfileData/CMakeLists.txt
index 4fa1b76f0a062..eb7c2a3c1a28a 100644
--- a/llvm/lib/ProfileData/CMakeLists.txt
+++ b/llvm/lib/ProfileData/CMakeLists.txt
@@ -1,5 +1,6 @@
 add_llvm_component_library(LLVMProfileData
   GCOV.cpp
+  IndexedMemProfData.cpp
   InstrProf.cpp
   InstrProfCorrelator.cpp
   InstrProfReader.cpp
diff --git a/llvm/lib/ProfileData/IndexedMemProfData.cpp b/llvm/lib/ProfileData/IndexedMemProfData.cpp
new file mode 100644
index 0000000000000..5e78ffdb86d67
--- /dev/null
+++ b/llvm/lib/ProfileData/IndexedMemProfData.cpp
@@ -0,0 +1,424 @@
+//===- IndexedMemProfData.h - MemProf format support ------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// MemProf data is serialized in writeMemProf provided in this file.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/ProfileData/InstrProf.h"
+#include "llvm/ProfileData/InstrProfReader.h"
+#include "llvm/ProfileData/MemProf.h"
+#include "llvm/Support/FormatVariadic.h"
+#include "llvm/Support/OnDiskHashTable.h"
+
+namespace llvm {
+
+// Serialize Schema.
+static void writeMemProfSchema(ProfOStream &OS,
+                               const memprof::MemProfSchema &Schema) {
+  OS.write(static_cast<uint64_t>(Schema.size()));
+  for (const auto Id : Schema)
+    OS.write(static_cast<uint64_t>(Id));
+}
+
+// Serialize MemProfRecordData.  Return RecordTableOffset.
+static uint64_t writeMemProfRecords(
+    ProfOStream &OS,
+    llvm::MapVector<GlobalValue::GUID, memprof::IndexedMemProfRecord>
+        &MemProfRecordData,
+    memprof::MemProfSchema *Schema, memprof::IndexedVersion Version,
+    llvm::DenseMap<memprof::CallStackId, memprof::LinearCallStackId>
+        *MemProfCallStackIndexes = nullptr) {
+  memprof::RecordWriterTrait RecordWriter(Schema, Version,
+                                          MemProfCallStackIndexes);
+  OnDiskChainedHashTableGenerator<memprof::RecordWriterTrait>
+      RecordTableGenerator;
+  for (auto &[GUID, Record] : MemProfRecordData) {
+    // Insert the key (func hash) and value (memprof record).
+    RecordTableGenerator.insert(GUID, Record, RecordWriter);
+  }
+  // Release the memory of this MapVector as it is no longer needed.
+  MemProfRecordData.clear();
+
+  // The call to Emit invokes RecordWriterTrait::EmitData which destructs
+  // the memprof record copies owned by the RecordTableGenerator. This works
+  // because the RecordTableGenerator is not used after this point.
+  return RecordTableGenerator.Emit(OS.OS, RecordWriter);
+}
+
+// Serialize MemProfFrameData.  Return FrameTableOffset.
+static uint64_t writeMemProfFrames(
+    ProfOStream &OS,
+    llvm::MapVector<memprof::FrameId, memprof::Frame> &MemProfFrameData) {
+  OnDiskChainedHashTableGenerator<memprof::FrameWriterTrait>
+      FrameTableGenerator;
+  for (auto &[FrameId, Frame] : MemProfFrameData) {
+    // Insert the key (frame id) and value (frame contents).
+    FrameTableGenerator.insert(FrameId, Frame);
+  }
+  // Release the memory of this MapVector as it is no longer needed.
+  MemProfFrameData.clear();
+
+  return FrameTableGenerator.Emit(OS.OS);
+}
+
+// Serialize MemProfFrameData.  Return the mapping from FrameIds to their
+// indexes within the frame array.
+static llvm::DenseMap<memprof::FrameId, memprof::LinearFrameId>
+writeMemProfFrameArray(
+    ProfOStream &OS,
+    llvm::MapVector<memprof::FrameId, memprof::Frame> &MemProfFrameData,
+    llvm::DenseMap<memprof::FrameId, memprof::FrameStat> &FrameHistogram) {
+  // Mappings from FrameIds to array indexes.
+  llvm::DenseMap<memprof::FrameId, memprof::LinearFrameId> MemProfFrameIndexes;
+
+  // Compute the order in which we serialize Frames.  The order does not matter
+  // in terms of correctness, but we still compute it for deserialization
+  // performance.  Specifically, if we serialize frequently used Frames one
+  // after another, we have better cache utilization.  For two Frames that
+  // appear equally frequently, we break a tie by serializing the one that tends
+  // to appear earlier in call stacks.  We implement the tie-breaking mechanism
+  // by computing the sum of indexes within call stacks for each Frame.  If we
+  // still have a tie, then we just resort to compare two FrameIds, which is
+  // just for stability of output.
+  std::vector<std::pair<memprof::FrameId, const memprof::Frame *>> FrameIdOrder;
+  FrameIdOrder.reserve(MemProfFrameData.size());
+  for (const auto &[Id, Frame] : MemProfFrameData)
+    FrameIdOrder.emplace_back(Id, &Frame);
+  assert(MemProfFrameData.size() == FrameIdOrder.size());
+  llvm::sort(FrameIdOrder,
+             [&](const std::pair<memprof::FrameId, const memprof::Frame *> &L,
+                 const std::pair<memprof::FrameId, const memprof::Frame *> &R) {
+               const auto &SL = FrameHistogram[L.first];
+               const auto &SR = FrameHistogram[R.first];
+               // Popular FrameIds should come first.
+               if (SL.Count != SR.Count)
+                 return SL.Count > SR.Count;
+               // If they are equally popular, then the one that tends to appear
+               // earlier in call stacks should come first.
+               if (SL.PositionSum != SR.PositionSum)
+                 return SL.PositionSum < SR.PositionSum;
+               // Compare their FrameIds for sort stability.
+               return L.first < R.first;
+             });
+
+  // Serialize all frames while creating mappings from linear IDs to FrameIds.
+  uint64_t Index = 0;
+  MemProfFrameIndexes.reserve(FrameIdOrder.size());
+  for (const auto &[Id, F] : FrameIdOrder) {
+    F->serialize(OS.OS);
+    MemProfFrameIndexes.insert({Id, Index});
+    ++Index;
+  }
+  assert(MemProfFrameData.size() == Index);
+  assert(MemProfFrameData.size() == MemProfFrameIndexes.size());
+
+  // Release the memory of this MapVector as it is no longer needed.
+  MemProfFrameData.clear();
+
+  return MemProfFrameIndexes;
+}
+
+static uint64_t writeMemProfCallStacks(
+    ProfOStream &OS,
+    llvm::MapVector<memprof::CallStackId, llvm::SmallVector<memprof::FrameId>>
+        &MemProfCallStackData) {
+  OnDiskChainedHashTableGenerator<memprof::CallStackWriterTrait>
+      CallStackTableGenerator;
+  for (auto &[CSId, CallStack] : MemProfCallStackData)
+    CallStackTableGenerator.insert(CSId, CallStack);
+  // Release the memory of this vector as it is no longer needed.
+  MemProfCallStackData.clear();
+
+  return CallStackTableGenerator.Emit(OS.OS);
+}
+
+static llvm::DenseMap<memprof::CallStackId, memprof::LinearCallStackId>
+writeMemProfCallStackArray(
+    ProfOStream &OS,
+    llvm::MapVector<memprof::CallStackId, llvm::SmallVector<memprof::FrameId>>
+        &MemProfCallStackData,
+    llvm::DenseMap<memprof::FrameId, memprof::LinearFrameId>
+        &MemProfFrameIndexes,
+    llvm::DenseMap<memprof::FrameId, memprof::FrameStat> &FrameHistogram,
+    unsigned &NumElements) {
+  llvm::DenseMap<memprof::CallStackId, memprof::LinearCallStackId>
+      MemProfCallStackIndexes;
+
+  memprof::CallStackRadixTreeBuilder<memprof::FrameId> Builder;
+  Builder.build(std::move(MemProfCallStackData), &MemProfFrameIndexes,
+                FrameHistogram);
+  for (auto I : Builder.getRadixArray())
+    OS.write32(I);
+  NumElements = Builder.getRadixArray().size();
+  MemProfCallStackIndexes = Builder.takeCallStackPos();
+
+  // Release the memory of this vector as it is no longer needed.
+  MemProfCallStackData.clear();
+
+  return MemProfCallStackIndexes;
+}
+
+// Write out MemProf Version2 as follows:
+// uint64_t Version
+// uint64_t RecordTableOffset = RecordTableGenerator.Emit
+// uint64_t FramePayloadOffset = Offset for the frame payload
+// uint64_t FrameTableOffset = FrameTableGenerator.Emit
+// uint64_t CallStackPayloadOffset = Offset for the call stack payload (NEW V2)
+// uint64_t CallStackTableOffset = CallStackTableGenerator.Emit (NEW in V2)
+// uint64_t Num schema entries
+// uint64_t Schema entry 0
+// uint64_t Schema entry 1
+// ....
+// uint64_t Schema entry N - 1
+// OnDiskChainedHashTable MemProfRecordData
+// OnDiskChainedHashTable MemProfFrameData
+// OnDiskChainedHashTable MemProfCallStackData (NEW in V2)
+static Error writeMemProfV2(ProfOStream &OS,
+                            memprof::IndexedMemProfData &MemProfData,
+                            bool MemProfFullSchema) {
+  OS.write(memprof::Version2);
+  uint64_t HeaderUpdatePos = OS.tell();
+  OS.write(0ULL); // Reserve space for the memprof record table offset.
+  OS.write(0ULL); // Reserve space for the memprof frame payload offset.
+  OS.write(0ULL); // Reserve space for the memprof frame table offset.
+  OS.write(0ULL); // Reserve space for the memprof call stack payload offset.
+  OS.write(0ULL); // Reserve space for the memprof call stack table offset.
+
+  auto Schema = memprof::getHotColdSchema();
+  if (MemProfFullSchema)
+    Schema = memprof::getFullSchema();
+  writeMemProfSchema(OS, Schema);
+
+  uint64_t RecordTableOffset =
+      writeMemProfRecords(OS, MemProfData.Records, &Schema, memprof::Version2);
+
+  uint64_t FramePayloadOffset = OS.tell();
+  uint64_t FrameTableOffset = writeMemProfFrames(OS, MemProfData.Frames);
+
+  uint64_t CallStackPayloadOffset = OS.tell();
+  uint64_t CallStackTableOffset =
+      writeMemProfCallStacks(OS, MemProfData.CallStacks);
+
+  uint64_t Header[] = {
+      RecordTableOffset,      FramePayloadOffset,   FrameTableOffset,
+      CallStackPayloadOffset, CallStackTableOffset,
+  };
+  OS.patch({{HeaderUpdatePos, Header}});
+
+  return Error::success();
+}
+
+// Write out MemProf Version3 as follows:
+// uint64_t Version
+// uint64_t CallStackPayloadOffset = Offset for the call stack payload
+// uint64_t RecordPayloadOffset = Offset for the record payload
+// uint64_t RecordTableOffset = RecordTableGenerator.Emit
+// uint64_t Num schema entries
+// uint64_t Schema entry 0
+// uint64_t Schema entry 1
+// ....
+// uint64_t Schema entry N - 1
+// Frames serialized one after another
+// Call stacks encoded as a radix tree
+// OnDiskChainedHashTable MemProfRecordData
+static Error writeMemProfV3(ProfOStream &OS,
+                            memprof::IndexedMemProfData &MemProfData,
+                            bool MemProfFullSchema) {
+  OS.write(memprof::Version3);
+  uint64_t HeaderUpdatePos = OS.tell();
+  OS.write(0ULL); // Reserve space for the memprof call stack payload offset.
+  OS.write(0ULL); // Reserve space for the memprof record payload offset.
+  OS.write(0ULL); // Reserve space for the memprof record table offset.
+
+  auto Schema = memprof::getHotColdSchema();
+  if (MemProfFullSchema)
+    Schema = memprof::getFullSchema();
+  writeMemProfSchema(OS, Schema);
+
+  llvm::DenseMap<memprof::FrameId, memprof::FrameStat> FrameHistogram =
+      memprof::computeFrameHistogram(MemProfData.CallStacks);
+  assert(MemProfData.Frames.size() == FrameHistogram.size());
+
+  llvm::DenseMap<memprof::FrameId, memprof::LinearFrameId> MemProfFrameIndexes =
+      writeMemProfFrameArray(OS, MemProfData.Frames, FrameHistogram);
+
+  uint64_t CallStackPayloadOffset = OS.tell();
+  // The number of elements in the call stack array.
+  unsigned NumElements = 0;
+  llvm::DenseMap<memprof::CallStackId, memprof::LinearCallStackId>
+      MemProfCallStackIndexes =
+          writeMemProfCallStackArray(OS, MemProfData.CallStacks,
+                                     MemProfFrameIndexes, FrameHistogram,
+                                     NumElements);
+
+  uint64_t RecordPayloadOffset = OS.tell();
+  uint64_t RecordTableOffset =
+      writeMemProfRecords(OS, MemProfData.Records, &Schema, memprof::Version3,
+                          &MemProfCallStackIndexes);
+
+  // IndexedMemProfReader::deserializeV3 computes the number of elements in the
+  // call stack array from the difference between CallStackPayloadOffset and
+  // RecordPayloadOffset.  Verify that the computation works.
+  assert(CallStackPayloadOffset +
+             NumElements * sizeof(memprof::LinearFrameId) ==
+         RecordPayloadOffset);
+
+  uint64_t Header[] = {
+      CallStackPayloadOffset,
+      RecordPayloadOffset,
+      RecordTableOffset,
+  };
+  OS.patch({{HeaderUpdatePos, Header}});
+
+  return Error::success();
+}
+
+// Write out the MemProf data in a requested version.
+Error writeMemProf(ProfOStream &OS, memprof::IndexedMemProfData &MemProfData,
+                   memprof::IndexedVersion MemProfVersionRequested,
+                   bool MemProfFullSchema) {
+  switch (MemProfVersionRequested) {
+  case memprof::Version2:
+    return writeMemProfV2(OS, MemProfData, MemProfFullSchema);
+  case memprof::Version3:
+    return writeMemProfV3(OS, MemProfData, MemProfFullSchema);
+  }
+
+  return make_error<InstrProfError>(
+      instrprof_error::unsupported_version,
+      formatv("MemProf version {} not supported; "
+              "requires version between {} and {}, inclusive",
+              MemProfVersionRequested, memprof::MinimumSupportedVersion,
+              memprof::MaximumSupportedVersion));
+}
+
+Error IndexedMemProfReader::deserializeV2(const unsigned char *Start,
+                                          const unsigned char *Ptr) {
+  // The value returned from RecordTableGenerator.Emit.
+  const uint64_t RecordTableOffset =
+      support::endian::readNext<uint64_t, llvm::endianness::little>(Ptr);
+  // The offset in the stream right before invoking
+  // FrameTableGenerator.Emit.
+  const uint64_t FramePayloadOffset =
+      support::endian::readNext<uint64_t, llvm::endianness::little>(Ptr);
+  // The value returned from FrameTableGenerator.Emit.
+  const uint64_t FrameTableOffset =
+      support::endian::readNext<uint64_t, llvm::endianness::little>(Ptr);
+
+  // The offset in the stream right before invoking
+  // CallStackTableGenerator.Emit.
+  uint64_t CallStackPayloadOffset = 0;
+  // The value returned from CallStackTableGenerator.Emit.
+  uint64_t CallStackTableOffset = 0;
+  if (Version >= memprof::Version2) {
+    CallStackPayloadOffset =
+        support::endian::readNext<uint64_t, llvm::endianness::little>(Ptr);
+    CallStackTableOffset =
+        support::endian::readNext<uint64_t, llvm::endianness::little>(Ptr);
+  }
+
+  // Read the schema.
+  auto SchemaOr = memprof::readMemProfSchema(Ptr);
+  if (!SchemaOr)
+    return SchemaOr.takeError();
+  Schema = SchemaOr.get();
+
+  // Now initialize the table reader with a pointer into data buffer.
+  MemProfRecordTable.reset(MemProfRecordHashTable::Create(
+      /*Buckets=*/Start + RecordTableOffset,
+      /*Payload=*/Ptr,
+      /*Base=*/Start, memprof::RecordLookupTrait(Version, Schema)));
+
+  // Initialize the frame table reader with the payload and bucket offsets.
+  MemProfFrameTable.reset(MemProfFrameHashTable::Create(
+      /*Buckets=*/Start + FrameTableOffset,
+      /*Payload=*/Start + FramePayloadOffset,
+      /*Base=*/Start));
+
+  if (Version >= memprof::Version2)
+    MemProfCallStackTable.reset(MemProfCallStackHashTable::Create(
+        /*Buckets=*/Start + CallStackTableOffset,
+        /*Payload=*/Start + CallStackPayloadOffset,
+        /*Base=*/Start));
+
+  return Error::success();
+}
+
+Error IndexedMemProfReader::deserializeV3(const unsigned char *Start,
+                                          const unsigned char *Ptr) {
+  // The offset in the stream right before invoking
+  // CallStackTableGenerator.Emit.
+  const uint64_t CallStackPayloadOffset =
+      support::endian::readNext<uint64_t, llvm::endianness::little>(Ptr);
+  // The offset in the stream right before invoking RecordTableGenerator.Emit.
+  const uint64_t RecordPayloadOffset =
+      support::endian::readNext<uint64_t, llvm::endianness::little>(Ptr);
+  // The value returned from RecordTableGenerator.Emit.
+  const uint64_t RecordTableOffset =
+      support::endian::readNext<uint64_t, llvm::endianness::little>(Ptr);
+
+  // Read the schema.
+  auto SchemaOr = memprof::readMemProfSchema(Ptr);
+  if (!SchemaOr)
+    return SchemaOr.takeError();
+  Schema = SchemaOr.get();
+
+  FrameBase = Ptr;
+  CallStackBase = Start + CallStackPayloadOffset;
+
+  // Compute the number of elements in the radix tree array.  Since we use this
+  // to reserve enough bits in a BitVector, it's totally OK if we overestimate
+  // this number a little bit because of padding just before the next section.
+  RadixTreeSize = (RecordPayloadOffset - CallStackPayloadOffset) /
+                  sizeof(memprof::LinearFrameId);
+
+  // Now initialize the table reader with a pointer into data buffer.
+  MemProfRecordTable.reset(MemProfRecordHashTable::Create(
+      /*Buckets=*/Start + RecordTableOffset,
+      /*Payload=*/Start + RecordPayloadOffset,
+      /*Base=*/Start, memprof::RecordLookupTrait(memprof::Version3, Schema)));
+
+  return Error::success();
+}
+
+Error IndexedMemProfReader::deserialize(const unsigned char *Start,
+                                        uint64_t MemProfOffset) {
+  const unsigned char *Ptr = Start + MemProfOffset;
+
+  // Read the MemProf version number.
+  const uint64_t FirstWord =
+      support::endian::readNext<uint64_t, llvm::endianness::little>(Ptr);
+
+  if (FirstWord == memprof::Version2 || FirstWord == memprof::Version3) {
+    // Everything is good.  We can proceed to deserialize the rest.
+    Version = static_cast<memprof::IndexedVersion>(FirstWord);
+  } else {
+    return make_error<InstrProfError>(
+        instrprof_error::unsupported_version,
+        formatv("MemProf version {} not supported; "
+                "requires version between {} and {}, inclusive",
+                FirstWord, memprof::MinimumSupportedVersion,
+                memprof::MaximumSupportedVersion));
+  }
+
+  switch (Version) {
+  case memprof::Version2:
+    if (Error E = deserializeV2(Start, Ptr))
+      return E;
+    break;
+  case memprof::Version3:
+    if (Error E = deserializeV3(Start, Ptr))
+      return E;
+    break;
+  }
+
+  return Error::success();
+}
+
+} // namespace llvm
diff --git a/llvm/lib/ProfileData/InstrProf.cpp b/llvm/lib/ProfileData/InstrProf.cpp
index 1e427ca63c5cf..88621787c1dd9 100644
--- a/llvm/lib/ProfileData/InstrProf.cpp
+++ b/llvm/lib/ProfileData/InstrProf.cpp
@@ -42,6 +42,7 @@
 #include "llvm/Support/Path.h"
 #include "llvm/Support/SwapByteOrder.h"
 #include "llvm/Support/VirtualFileSystem.h"
+#include "llvm/Support/raw_ostream.h"
 #include "llvm/TargetParser/Triple.h"
 #include <algorithm>
 #include <cassert>
@@ -258,6 +259,46 @@ std::string InstrProfError::message() const {
 
 char InstrProfError::ID = 0;
 
+ProfOStream::ProfOStream(raw_fd_ostream &FD)
+    : IsFDOStream(true), OS(FD), LE(FD, llvm::endianness::little) {}
+
+ProfOStream::ProfOStream(raw_string_ostream &STR)
+    : IsFDOStream(false), OS(STR), LE(STR, llvm::endianness::little) {}
+
+uint64_t ProfOStream::tell() const { return OS.tell(); }
+void ProfOStream::write(uint64_t V) { LE.write<uint64_t>(V); }
+void ProfOStream::write32(uint32_t V) { LE.write<uint32_t>(V); }
+void ProfOStream::writeByte(uint8_t V) { LE.write<uint8_t>(V); }
+
+void ProfOStream::patch(ArrayRef<PatchItem> P) {
+  using namespace support;
+
+  if (IsFDOStream) {
+    raw_fd_ostream &FDOStream = static_cast<raw_fd_ostream &>(OS);
+    const uint64_t LastPos = FDOStream.tell();
+    for (const auto &K : P) {
+      FDOStream.seek(K.Pos);
+      for (uint64_t Elem : K.D)
+        write(Elem);
+    }
+    // Reset the stream to the last position after patching so that users
+    // don't accidentally overwrite data. This makes it consistent with
+    // the string stream below which replaces the data directly.
+    FDOStream.seek(LastPos);
+  } else {
+    raw_string_ostream &SOStream = static_cast<raw_string_ostream &>(OS);
+    std::string &Data = SOStream.str(); // with flush
+    for (const auto &K : P) {
+      for (int I = 0, E = K.D.size(); I != E; I++) {
+        uint64_t Bytes =
+            endian::byte_swap<uint64_t, llvm::endianness::little>(K.D[I]);
+        Data.replace(K.Pos + I * sizeof(uint64_t), sizeof(uint64_t),
+                     (const char *)&Bytes, sizeof(uint64_t));
+      }
+    }
+  }
+}
+
 std::string getPGOFuncName(StringRef Name, GlobalValue::LinkageTypes Linkage,
                            StringRef FileName,
                            uint64_t Version LLVM_ATTRIBUTE_UNUSED) {
diff --git a/llvm/lib/ProfileData/InstrProfReader.cpp b/llvm/lib/ProfileData/InstrProfReader.cpp
index 4075b513c218d..295f2a633e6c7 100644
--- a/llvm/lib/ProfileData/InstrProfReader.cpp
+++ b/llvm/lib/ProfileData/InstrProfReader.cpp
@@ -1230,129 +1230,6 @@ IndexedInstrProfReader::readSummary(IndexedInstrProf::ProfVersion Version,
   }
 }
 
-Error IndexedMemProfReader::deserializeV2(const unsigned char *Start,
-                                          const unsigned char *Ptr) {
-  // The value returned from RecordTableGenerator.Emit.
-  const uint64_t RecordTableOffset =
-      support::endian::readNext<uint64_t, llvm::endianness::little>(Ptr);
-  // The offset in the stream right before invoking
-  // FrameTableGenerator.Emit.
-  const uint64_t FramePayloadOffset =
-      support::endian::readNext<uint64_t, llvm::endianness::little>(Ptr);
-  // The value returned from FrameTableGenerator.Emit.
-  const uint64_t FrameTableOffset =
-      support::endian::readNext<uint64_t, llvm::endianness::little>(Ptr);
-
-  // The offset in the stream right before invoking
-  // CallStackTableGenerator.Emit.
-  uint64_t CallStackPayloadOffset = 0;
-  // The value returned from CallStackTableGenerator.Emit.
-  uint64_t CallStackTableOffset = 0;
-  if (Version >= memprof::Version2) {
-    CallStackPayloadOffset =
-        support::endian::readNext<uint64_t, llvm::endianness::little>(Ptr);
-    CallStackTableOffset =
-        support::endian::readNext<uint64_t, llvm::endianness::little>(Ptr);
-  }
-
-  // Read the schema.
-  auto SchemaOr = memprof::readMemProfSchema(Ptr);
-  if (!SchemaOr)
-    return SchemaOr.takeError();
-  Schema = SchemaOr.get();
-
-  // Now initialize the table reader with a pointer into data buffer.
-  MemProfRecordTable.reset(MemProfRecordHashTable::Create(
-      /*Buckets=*/Start + RecordTableOffset,
-      /*Payload=*/Ptr,
-      /*Base=*/Start, memprof::RecordLookupTrait(Version, Schema)));
-
-  // Initialize the frame table reader with the payload and bucket offsets.
-  MemProfFrameTable.reset(MemProfFrameHashTable::Create(
-      /*Buckets=*/Start + FrameTableOffset,
-      /*Payload=*/Start + FramePayloadOffset,
-      /*Base=*/Start));
-
-  if (Version >= memprof::Version2)
-    MemProfCallStackTable.reset(MemProfCallStackHashTable::Create(
-        /*Buckets=*/Start + CallStackTableOffset,
-        /*Payload=*/Start + CallStackPayloadOffset,
-        /*Base=*/Start));
-
-  return Error::success();
-}
-
-Error IndexedMemProfReader::deserializeV3(const unsigned char *Start,
-                                          const unsigned char *Ptr) {
-  // The offset in the stream right before invoking
-  // CallStackTableGenerator.Emit.
-  const uint64_t CallStackPayloadOffset =
-      support::endian::readNext<uint64_t, llvm::endianness::little>(Ptr);
-  // The offset in the stream right before invoking RecordTableGenerator.Emit.
-  const uint64_t RecordPayloadOffset =
-      support::endian::readNext<uint64_t, llvm::endianness::little>(Ptr);
-  // The value returned from RecordTableGenerator.Emit.
-  const uint64_t RecordTableOffset =
-      support::endian::readNext<uint64_t, llvm::endianness::little>(Ptr);
-
-  // Read the schema.
-  auto SchemaOr = memprof::readMemProfSchema(Ptr);
-  if (!SchemaOr)
-    return SchemaOr.takeError();
-  Schema = SchemaOr.get();
-
-  FrameBase = Ptr;
-  CallStackBase = Start + CallStackPayloadOffset;
-
-  // Compute the number of elements in the radix tree array.  Since we use this
-  // to reserve enough bits in a BitVector, it's totally OK if we overestimate
-  // this number a little bit because of padding just before the next section.
-  RadixTreeSize = (RecordPayloadOffset - CallStackPayloadOffset) /
-                  sizeof(memprof::LinearFrameId);
-
-  // Now initialize the table reader with a pointer into data buffer.
-  MemProfRecordTable.reset(MemProfRecordHashTable::Create(
-      /*Buckets=*/Start + RecordTableOffset,
-      /*Payload=*/Start + RecordPayloadOffset,
-      /*Base=*/Start, memprof::RecordLookupTrait(memprof::Version3, Schema)));
-
-  return Error::success();
-}
-
-Error IndexedMemProfReader::deserialize(const unsigned char *Start,
-                                        uint64_t MemProfOffset) {
-  const unsigned char *Ptr = Start + MemProfOffset;
-
-  // Read the MemProf version number.
-  const uint64_t FirstWord =
-      support::endian::readNext<uint64_t, llvm::endianness::little>(Ptr);
-
-  if (FirstWord == memprof::Version2 || FirstWord == memprof::Version3) {
-    // Everything is good.  We can proceed to deserialize the rest.
-    Version = static_cast<memprof::IndexedVersion>(FirstWord);
-  } else {
-    return make_error<InstrProfError>(
-        instrprof_error::unsupported_version,
-        formatv("MemProf version {} not supported; "
-                "requires version between {} and {}, inclusive",
-                FirstWord, memprof::MinimumSupportedVersion,
-                memprof::MaximumSupportedVersion));
-  }
-
-  switch (Version) {
-  case memprof::Version2:
-    if (Error E = deserializeV2(Start, Ptr))
-      return E;
-    break;
-  case memprof::Version3:
-    if (Error E = deserializeV3(Start, Ptr))
-      return E;
-    break;
-  }
-
-  return Error::success();
-}
-
 Error IndexedInstrProfReader::readHeader() {
   using namespace support;
 
diff --git a/llvm/lib/ProfileData/InstrProfWriter.cpp b/llvm/lib/ProfileData/InstrProfWriter.cpp
index 18aa76c865bc8..2759346935b14 100644
--- a/llvm/lib/ProfileData/InstrProfWriter.cpp
+++ b/llvm/lib/ProfileData/InstrProfWriter.cpp
@@ -16,6 +16,7 @@
 #include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/IR/ProfileSummary.h"
+#include "llvm/ProfileData/IndexedMemProfData.h"
 #include "llvm/ProfileData/InstrProf.h"
 #include "llvm/ProfileData/MemProf.h"
 #include "llvm/ProfileData/ProfileCommon.h"
@@ -23,7 +24,6 @@
 #include "llvm/Support/Endian.h"
 #include "llvm/Support/EndianStream.h"
 #include "llvm/Support/Error.h"
-#include "llvm/Support/FormatVariadic.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/OnDiskHashTable.h"
 #include "llvm/Support/raw_ostream.h"
@@ -37,68 +37,8 @@
 
 using namespace llvm;
 
-// A struct to define how the data stream should be patched. For Indexed
-// profiling, only uint64_t data type is needed.
-struct PatchItem {
-  uint64_t Pos;         // Where to patch.
-  ArrayRef<uint64_t> D; // An array of source data.
-};
-
 namespace llvm {
 
-// A wrapper class to abstract writer stream with support of bytes
-// back patching.
-class ProfOStream {
-public:
-  ProfOStream(raw_fd_ostream &FD)
-      : IsFDOStream(true), OS(FD), LE(FD, llvm::endianness::little) {}
-  ProfOStream(raw_string_ostream &STR)
-      : IsFDOStream(false), OS(STR), LE(STR, llvm::endianness::little) {}
-
-  [[nodiscard]] uint64_t tell() const { return OS.tell(); }
-  void write(uint64_t V) { LE.write<uint64_t>(V); }
-  void write32(uint32_t V) { LE.write<uint32_t>(V); }
-  void writeByte(uint8_t V) { LE.write<uint8_t>(V); }
-
-  // \c patch can only be called when all data is written and flushed.
-  // For raw_string_ostream, the patch is done on the target string
-  // directly and it won't be reflected in the stream's internal buffer.
-  void patch(ArrayRef<PatchItem> P) {
-    using namespace support;
-
-    if (IsFDOStream) {
-      raw_fd_ostream &FDOStream = static_cast<raw_fd_ostream &>(OS);
-      const uint64_t LastPos = FDOStream.tell();
-      for (const auto &K : P) {
-        FDOStream.seek(K.Pos);
-        for (uint64_t Elem : K.D)
-          write(Elem);
-      }
-      // Reset the stream to the last position after patching so that users
-      // don't accidentally overwrite data. This makes it consistent with
-      // the string stream below which replaces the data directly.
-      FDOStream.seek(LastPos);
-    } else {
-      raw_string_ostream &SOStream = static_cast<raw_string_ostream &>(OS);
-      std::string &Data = SOStream.str(); // with flush
-      for (const auto &K : P) {
-        for (int I = 0, E = K.D.size(); I != E; I++) {
-          uint64_t Bytes =
-              endian::byte_swap<uint64_t, llvm::endianness::little>(K.D[I]);
-          Data.replace(K.Pos + I * sizeof(uint64_t), sizeof(uint64_t),
-                       (const char *)&Bytes, sizeof(uint64_t));
-        }
-      }
-    }
-  }
-
-  // If \c OS is an instance of \c raw_fd_ostream, this field will be
-  // true. Otherwise, \c OS will be an raw_string_ostream.
-  bool IsFDOStream;
-  raw_ostream &OS;
-  support::endian::Writer LE;
-};
-
 class InstrProfRecordWriterTrait {
 public:
   using key_type = StringRef;
@@ -509,287 +449,6 @@ static void setSummary(IndexedInstrProf::Summary *TheSummary,
     TheSummary->setEntry(I, Res[I]);
 }
 
-// Serialize Schema.
-static void writeMemProfSchema(ProfOStream &OS,
-                               const memprof::MemProfSchema &Schema) {
-  OS.write(static_cast<uint64_t>(Schema.size()));
-  for (const auto Id : Schema)
-    OS.write(static_cast<uint64_t>(Id));
-}
-
-// Serialize MemProfRecordData.  Return RecordTableOffset.
-static uint64_t writeMemProfRecords(
-    ProfOStream &OS,
-    llvm::MapVector<GlobalValue::GUID, memprof::IndexedMemProfRecord>
-        &MemProfRecordData,
-    memprof::MemProfSchema *Schema, memprof::IndexedVersion Version,
-    llvm::DenseMap<memprof::CallStackId, memprof::LinearCallStackId>
-        *MemProfCallStackIndexes = nullptr) {
-  memprof::RecordWriterTrait RecordWriter(Schema, Version,
-                                          MemProfCallStackIndexes);
-  OnDiskChainedHashTableGenerator<memprof::RecordWriterTrait>
-      RecordTableGenerator;
-  for (auto &[GUID, Record] : MemProfRecordData) {
-    // Insert the key (func hash) and value (memprof record).
-    RecordTableGenerator.insert(GUID, Record, RecordWriter);
-  }
-  // Release the memory of this MapVector as it is no longer needed.
-  MemProfRecordData.clear();
-
-  // The call to Emit invokes RecordWriterTrait::EmitData which destructs
-  // the memprof record copies owned by the RecordTableGenerator. This works
-  // because the RecordTableGenerator is not used after this point.
-  return RecordTableGenerator.Emit(OS.OS, RecordWriter);
-}
-
-// Serialize MemProfFrameData.  Return FrameTableOffset.
-static uint64_t writeMemProfFrames(
-    ProfOStream &OS,
-    llvm::MapVector<memprof::FrameId, memprof::Frame> &MemProfFrameData) {
-  OnDiskChainedHashTableGenerator<memprof::FrameWriterTrait>
-      FrameTableGenerator;
-  for (auto &[FrameId, Frame] : MemProfFrameData) {
-    // Insert the key (frame id) and value (frame contents).
-    FrameTableGenerator.insert(FrameId, Frame);
-  }
-  // Release the memory of this MapVector as it is no longer needed.
-  MemProfFrameData.clear();
-
-  return FrameTableGenerator.Emit(OS.OS);
-}
-
-// Serialize MemProfFrameData.  Return the mapping from FrameIds to their
-// indexes within the frame array.
-static llvm::DenseMap<memprof::FrameId, memprof::LinearFrameId>
-writeMemProfFrameArray(
-    ProfOStream &OS,
-    llvm::MapVector<memprof::FrameId, memprof::Frame> &MemProfFrameData,
-    llvm::DenseMap<memprof::FrameId, memprof::FrameStat> &FrameHistogram) {
-  // Mappings from FrameIds to array indexes.
-  llvm::DenseMap<memprof::FrameId, memprof::LinearFrameId> MemProfFrameIndexes;
-
-  // Compute the order in which we serialize Frames.  The order does not matter
-  // in terms of correctness, but we still compute it for deserialization
-  // performance.  Specifically, if we serialize frequently used Frames one
-  // after another, we have better cache utilization.  For two Frames that
-  // appear equally frequently, we break a tie by serializing the one that tends
-  // to appear earlier in call stacks.  We implement the tie-breaking mechanism
-  // by computing the sum of indexes within call stacks for each Frame.  If we
-  // still have a tie, then we just resort to compare two FrameIds, which is
-  // just for stability of output.
-  std::vector<std::pair<memprof::FrameId, const memprof::Frame *>> FrameIdOrder;
-  FrameIdOrder.reserve(MemProfFrameData.size());
-  for (const auto &[Id, Frame] : MemProfFrameData)
-    FrameIdOrder.emplace_back(Id, &Frame);
-  assert(MemProfFrameData.size() == FrameIdOrder.size());
-  llvm::sort(FrameIdOrder,
-             [&](const std::pair<memprof::FrameId, const memprof::Frame *> &L,
-                 const std::pair<memprof::FrameId, const memprof::Frame *> &R) {
-               const auto &SL = FrameHistogram[L.first];
-               const auto &SR = FrameHistogram[R.first];
-               // Popular FrameIds should come first.
-               if (SL.Count != SR.Count)
-                 return SL.Count > SR.Count;
-               // If they are equally popular, then the one that tends to appear
-               // earlier in call stacks should come first.
-               if (SL.PositionSum != SR.PositionSum)
-                 return SL.PositionSum < SR.PositionSum;
-               // Compare their FrameIds for sort stability.
-               return L.first < R.first;
-             });
-
-  // Serialize all frames while creating mappings from linear IDs to FrameIds.
-  uint64_t Index = 0;
-  MemProfFrameIndexes.reserve(FrameIdOrder.size());
-  for (const auto &[Id, F] : FrameIdOrder) {
-    F->serialize(OS.OS);
-    MemProfFrameIndexes.insert({Id, Index});
-    ++Index;
-  }
-  assert(MemProfFrameData.size() == Index);
-  assert(MemProfFrameData.size() == MemProfFrameIndexes.size());
-
-  // Release the memory of this MapVector as it is no longer needed.
-  MemProfFrameData.clear();
-
-  return MemProfFrameIndexes;
-}
-
-static uint64_t writeMemProfCallStacks(
-    ProfOStream &OS,
-    llvm::MapVector<memprof::CallStackId, llvm::SmallVector<memprof::FrameId>>
-        &MemProfCallStackData) {
-  OnDiskChainedHashTableGenerator<memprof::CallStackWriterTrait>
-      CallStackTableGenerator;
-  for (auto &[CSId, CallStack] : MemProfCallStackData)
-    CallStackTableGenerator.insert(CSId, CallStack);
-  // Release the memory of this vector as it is no longer needed.
-  MemProfCallStackData.clear();
-
-  return CallStackTableGenerator.Emit(OS.OS);
-}
-
-static llvm::DenseMap<memprof::CallStackId, memprof::LinearCallStackId>
-writeMemProfCallStackArray(
-    ProfOStream &OS,
-    llvm::MapVector<memprof::CallStackId, llvm::SmallVector<memprof::FrameId>>
-        &MemProfCallStackData,
-    llvm::DenseMap<memprof::FrameId, memprof::LinearFrameId>
-        &MemProfFrameIndexes,
-    llvm::DenseMap<memprof::FrameId, memprof::FrameStat> &FrameHistogram,
-    unsigned &NumElements) {
-  llvm::DenseMap<memprof::CallStackId, memprof::LinearCallStackId>
-      MemProfCallStackIndexes;
-
-  memprof::CallStackRadixTreeBuilder<memprof::FrameId> Builder;
-  Builder.build(std::move(MemProfCallStackData), &MemProfFrameIndexes,
-                FrameHistogram);
-  for (auto I : Builder.getRadixArray())
-    OS.write32(I);
-  NumElements = Builder.getRadixArray().size();
-  MemProfCallStackIndexes = Builder.takeCallStackPos();
-
-  // Release the memory of this vector as it is no longer needed.
-  MemProfCallStackData.clear();
-
-  return MemProfCallStackIndexes;
-}
-
-// Write out MemProf Version2 as follows:
-// uint64_t Version
-// uint64_t RecordTableOffset = RecordTableGenerator.Emit
-// uint64_t FramePayloadOffset = Offset for the frame payload
-// uint64_t FrameTableOffset = FrameTableGenerator.Emit
-// uint64_t CallStackPayloadOffset = Offset for the call stack payload (NEW V2)
-// uint64_t CallStackTableOffset = CallStackTableGenerator.Emit (NEW in V2)
-// uint64_t Num schema entries
-// uint64_t Schema entry 0
-// uint64_t Schema entry 1
-// ....
-// uint64_t Schema entry N - 1
-// OnDiskChainedHashTable MemProfRecordData
-// OnDiskChainedHashTable MemProfFrameData
-// OnDiskChainedHashTable MemProfCallStackData (NEW in V2)
-static Error writeMemProfV2(ProfOStream &OS,
-                            memprof::IndexedMemProfData &MemProfData,
-                            bool MemProfFullSchema) {
-  OS.write(memprof::Version2);
-  uint64_t HeaderUpdatePos = OS.tell();
-  OS.write(0ULL); // Reserve space for the memprof record table offset.
-  OS.write(0ULL); // Reserve space for the memprof frame payload offset.
-  OS.write(0ULL); // Reserve space for the memprof frame table offset.
-  OS.write(0ULL); // Reserve space for the memprof call stack payload offset.
-  OS.write(0ULL); // Reserve space for the memprof call stack table offset.
-
-  auto Schema = memprof::getHotColdSchema();
-  if (MemProfFullSchema)
-    Schema = memprof::getFullSchema();
-  writeMemProfSchema(OS, Schema);
-
-  uint64_t RecordTableOffset =
-      writeMemProfRecords(OS, MemProfData.Records, &Schema, memprof::Version2);
-
-  uint64_t FramePayloadOffset = OS.tell();
-  uint64_t FrameTableOffset = writeMemProfFrames(OS, MemProfData.Frames);
-
-  uint64_t CallStackPayloadOffset = OS.tell();
-  uint64_t CallStackTableOffset =
-      writeMemProfCallStacks(OS, MemProfData.CallStacks);
-
-  uint64_t Header[] = {
-      RecordTableOffset,      FramePayloadOffset,   FrameTableOffset,
-      CallStackPayloadOffset, CallStackTableOffset,
-  };
-  OS.patch({{HeaderUpdatePos, Header}});
-
-  return Error::success();
-}
-
-// Write out MemProf Version3 as follows:
-// uint64_t Version
-// uint64_t CallStackPayloadOffset = Offset for the call stack payload
-// uint64_t RecordPayloadOffset = Offset for the record payload
-// uint64_t RecordTableOffset = RecordTableGenerator.Emit
-// uint64_t Num schema entries
-// uint64_t Schema entry 0
-// uint64_t Schema entry 1
-// ....
-// uint64_t Schema entry N - 1
-// Frames serialized one after another
-// Call stacks encoded as a radix tree
-// OnDiskChainedHashTable MemProfRecordData
-static Error writeMemProfV3(ProfOStream &OS,
-                            memprof::IndexedMemProfData &MemProfData,
-                            bool MemProfFullSchema) {
-  OS.write(memprof::Version3);
-  uint64_t HeaderUpdatePos = OS.tell();
-  OS.write(0ULL); // Reserve space for the memprof call stack payload offset.
-  OS.write(0ULL); // Reserve space for the memprof record payload offset.
-  OS.write(0ULL); // Reserve space for the memprof record table offset.
-
-  auto Schema = memprof::getHotColdSchema();
-  if (MemProfFullSchema)
-    Schema = memprof::getFullSchema();
-  writeMemProfSchema(OS, Schema);
-
-  llvm::DenseMap<memprof::FrameId, memprof::FrameStat> FrameHistogram =
-      memprof::computeFrameHistogram(MemProfData.CallStacks);
-  assert(MemProfData.Frames.size() == FrameHistogram.size());
-
-  llvm::DenseMap<memprof::FrameId, memprof::LinearFrameId> MemProfFrameIndexes =
-      writeMemProfFrameArray(OS, MemProfData.Frames, FrameHistogram);
-
-  uint64_t CallStackPayloadOffset = OS.tell();
-  // The number of elements in the call stack array.
-  unsigned NumElements = 0;
-  llvm::DenseMap<memprof::CallStackId, memprof::LinearCallStackId>
-      MemProfCallStackIndexes =
-          writeMemProfCallStackArray(OS, MemProfData.CallStacks,
-                                     MemProfFrameIndexes, FrameHistogram,
-                                     NumElements);
-
-  uint64_t RecordPayloadOffset = OS.tell();
-  uint64_t RecordTableOffset =
-      writeMemProfRecords(OS, MemProfData.Records, &Schema, memprof::Version3,
-                          &MemProfCallStackIndexes);
-
-  // IndexedMemProfReader::deserializeV3 computes the number of elements in the
-  // call stack array from the difference between CallStackPayloadOffset and
-  // RecordPayloadOffset.  Verify that the computation works.
-  assert(CallStackPayloadOffset +
-             NumElements * sizeof(memprof::LinearFrameId) ==
-         RecordPayloadOffset);
-
-  uint64_t Header[] = {
-      CallStackPayloadOffset,
-      RecordPayloadOffset,
-      RecordTableOffset,
-  };
-  OS.patch({{HeaderUpdatePos, Header}});
-
-  return Error::success();
-}
-
-// Write out the MemProf data in a requested version.
-static Error writeMemProf(ProfOStream &OS,
-                          memprof::IndexedMemProfData &MemProfData,
-                          memprof::IndexedVersion MemProfVersionRequested,
-                          bool MemProfFullSchema) {
-  switch (MemProfVersionRequested) {
-  case memprof::Version2:
-    return writeMemProfV2(OS, MemProfData, MemProfFullSchema);
-  case memprof::Version3:
-    return writeMemProfV3(OS, MemProfData, MemProfFullSchema);
-  }
-
-  return make_error<InstrProfError>(
-      instrprof_error::unsupported_version,
-      formatv("MemProf version {} not supported; "
-              "requires version between {} and {}, inclusive",
-              MemProfVersionRequested, memprof::MinimumSupportedVersion,
-              memprof::MaximumSupportedVersion));
-}
-
 uint64_t InstrProfWriter::writeHeader(const IndexedInstrProf::Header &Header,
                                       const bool WritePrevVersion,
                                       ProfOStream &OS) {
diff --git a/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp b/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
index acc22da393ee0..a79fbdc141835 100644
--- a/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
@@ -78,9 +78,7 @@ class AArch64Arm64ECCallLowering : public ModulePass {
 private:
   int cfguard_module_flag = 0;
   FunctionType *GuardFnType = nullptr;
-  PointerType *GuardFnPtrType = nullptr;
   FunctionType *DispatchFnType = nullptr;
-  PointerType *DispatchFnPtrType = nullptr;
   Constant *GuardFnCFGlobal = nullptr;
   Constant *GuardFnGlobal = nullptr;
   Constant *DispatchFnGlobal = nullptr;
@@ -463,7 +461,7 @@ Function *AArch64Arm64ECCallLowering::buildExitThunk(FunctionType *FT,
       IRB.CreateStore(&Arg, Mem);
       if (ArgTranslation == ThunkArgTranslation::Bitcast) {
         Type *IntTy = IRB.getIntNTy(DL.getTypeStoreSizeInBits(Arg.getType()));
-        Args.push_back(IRB.CreateLoad(IntTy, IRB.CreateBitCast(Mem, PtrTy)));
+        Args.push_back(IRB.CreateLoad(IntTy, Mem));
       } else {
         assert(ArgTranslation == ThunkArgTranslation::PointerIndirection);
         Args.push_back(Mem);
@@ -475,7 +473,6 @@ Function *AArch64Arm64ECCallLowering::buildExitThunk(FunctionType *FT,
   }
   // FIXME: Transfer necessary attributes? sret? anything else?
 
-  Callee = IRB.CreateBitCast(Callee, PtrTy);
   CallInst *Call = IRB.CreateCall(X64Ty, Callee, Args);
   Call->setCallingConv(CallingConv::ARM64EC_Thunk_X64);
 
@@ -487,7 +484,7 @@ Function *AArch64Arm64ECCallLowering::buildExitThunk(FunctionType *FT,
       RetVal = IRB.CreateLoad(RetTy, Args[1]);
     } else {
       Value *CastAlloca = IRB.CreateAlloca(RetTy);
-      IRB.CreateStore(Call, IRB.CreateBitCast(CastAlloca, PtrTy));
+      IRB.CreateStore(Call, CastAlloca);
       RetVal = IRB.CreateLoad(RetTy, CastAlloca);
     }
   }
@@ -542,11 +539,11 @@ Function *AArch64Arm64ECCallLowering::buildEntryThunk(Function *F) {
       // Translate array/struct arguments to the expected type.
       if (ArgTranslation == ThunkArgTranslation::Bitcast) {
         Value *CastAlloca = IRB.CreateAlloca(ArgTy);
-        IRB.CreateStore(Arg, IRB.CreateBitCast(CastAlloca, PtrTy));
+        IRB.CreateStore(Arg, CastAlloca);
         Arg = IRB.CreateLoad(ArgTy, CastAlloca);
       } else {
         assert(ArgTranslation == ThunkArgTranslation::PointerIndirection);
-        Arg = IRB.CreateLoad(ArgTy, IRB.CreateBitCast(Arg, PtrTy));
+        Arg = IRB.CreateLoad(ArgTy, Arg);
       }
     }
     assert(Arg->getType() == ArgTy);
@@ -571,7 +568,6 @@ Function *AArch64Arm64ECCallLowering::buildEntryThunk(Function *F) {
 
   // Call the function passed to the thunk.
   Value *Callee = Thunk->getArg(0);
-  Callee = IRB.CreateBitCast(Callee, PtrTy);
   CallInst *Call = IRB.CreateCall(Arm64Ty, Callee, Args);
 
   auto SRetAttr = F->getAttributes().getParamAttr(0, Attribute::StructRet);
@@ -583,10 +579,10 @@ Function *AArch64Arm64ECCallLowering::buildEntryThunk(Function *F) {
 
   Value *RetVal = Call;
   if (TransformDirectToSRet) {
-    IRB.CreateStore(RetVal, IRB.CreateBitCast(Thunk->getArg(1), PtrTy));
+    IRB.CreateStore(RetVal, Thunk->getArg(1));
   } else if (X64RetType != RetTy) {
     Value *CastAlloca = IRB.CreateAlloca(X64RetType);
-    IRB.CreateStore(Call, IRB.CreateBitCast(CastAlloca, PtrTy));
+    IRB.CreateStore(Call, CastAlloca);
     RetVal = IRB.CreateLoad(X64RetType, CastAlloca);
   }
 
@@ -643,21 +639,19 @@ Function *AArch64Arm64ECCallLowering::buildGuestExitThunk(Function *F) {
     GuardFn = GuardFnCFGlobal;
   else
     GuardFn = GuardFnGlobal;
-  LoadInst *GuardCheckLoad = B.CreateLoad(GuardFnPtrType, GuardFn);
+  LoadInst *GuardCheckLoad = B.CreateLoad(PtrTy, GuardFn);
 
   // Create new call instruction. The CFGuard check should always be a call,
   // even if the original CallBase is an Invoke or CallBr instruction.
   Function *Thunk = buildExitThunk(F->getFunctionType(), F->getAttributes());
   CallInst *GuardCheck = B.CreateCall(
-      GuardFnType, GuardCheckLoad,
-      {B.CreateBitCast(F, B.getPtrTy()), B.CreateBitCast(Thunk, B.getPtrTy())});
+      GuardFnType, GuardCheckLoad, {F, Thunk});
 
   // Ensure that the first argument is passed in the correct register.
   GuardCheck->setCallingConv(CallingConv::CFGuard_Check);
 
-  Value *GuardRetVal = B.CreateBitCast(GuardCheck, PtrTy);
   SmallVector<Value *> Args(llvm::make_pointer_range(GuestExit->args()));
-  CallInst *Call = B.CreateCall(Arm64Ty, GuardRetVal, Args);
+  CallInst *Call = B.CreateCall(Arm64Ty, GuardCheck, Args);
   Call->setTailCallKind(llvm::CallInst::TCK_MustTail);
 
   if (Call->getType()->isVoidTy())
@@ -700,7 +694,7 @@ AArch64Arm64ECCallLowering::buildPatchableThunk(GlobalAlias *UnmangledAlias,
   IRBuilder<> B(BB);
 
   // Load the global symbol as a pointer to the check function.
-  LoadInst *DispatchLoad = B.CreateLoad(DispatchFnPtrType, DispatchFnGlobal);
+  LoadInst *DispatchLoad = B.CreateLoad(PtrTy, DispatchFnGlobal);
 
   // Create new dispatch call instruction.
   Function *ExitThunk =
@@ -712,9 +706,8 @@ AArch64Arm64ECCallLowering::buildPatchableThunk(GlobalAlias *UnmangledAlias,
   // Ensure that the first arguments are passed in the correct registers.
   Dispatch->setCallingConv(CallingConv::CFGuard_Check);
 
-  Value *DispatchRetVal = B.CreateBitCast(Dispatch, PtrTy);
   SmallVector<Value *> Args(llvm::make_pointer_range(GuestExit->args()));
-  CallInst *Call = B.CreateCall(Arm64Ty, DispatchRetVal, Args);
+  CallInst *Call = B.CreateCall(Arm64Ty, Dispatch, Args);
   Call->setTailCallKind(llvm::CallInst::TCK_MustTail);
 
   if (Call->getType()->isVoidTy())
@@ -753,22 +746,19 @@ void AArch64Arm64ECCallLowering::lowerCall(CallBase *CB) {
     GuardFn = GuardFnCFGlobal;
   else
     GuardFn = GuardFnGlobal;
-  LoadInst *GuardCheckLoad = B.CreateLoad(GuardFnPtrType, GuardFn);
+  LoadInst *GuardCheckLoad = B.CreateLoad(PtrTy, GuardFn);
 
   // Create new call instruction. The CFGuard check should always be a call,
   // even if the original CallBase is an Invoke or CallBr instruction.
   Function *Thunk = buildExitThunk(CB->getFunctionType(), CB->getAttributes());
   CallInst *GuardCheck =
-      B.CreateCall(GuardFnType, GuardCheckLoad,
-                   {B.CreateBitCast(CalledOperand, B.getPtrTy()),
-                    B.CreateBitCast(Thunk, B.getPtrTy())},
+      B.CreateCall(GuardFnType, GuardCheckLoad, {CalledOperand, Thunk},
                    Bundles);
 
   // Ensure that the first argument is passed in the correct register.
   GuardCheck->setCallingConv(CallingConv::CFGuard_Check);
 
-  Value *GuardRetVal = B.CreateBitCast(GuardCheck, CalledOperand->getType());
-  CB->setCalledOperand(GuardRetVal);
+  CB->setCalledOperand(GuardCheck);
 }
 
 bool AArch64Arm64ECCallLowering::runOnModule(Module &Mod) {
@@ -787,15 +777,10 @@ bool AArch64Arm64ECCallLowering::runOnModule(Module &Mod) {
   VoidTy = Type::getVoidTy(M->getContext());
 
   GuardFnType = FunctionType::get(PtrTy, {PtrTy, PtrTy}, false);
-  GuardFnPtrType = PointerType::get(M->getContext(), 0);
   DispatchFnType = FunctionType::get(PtrTy, {PtrTy, PtrTy, PtrTy}, false);
-  DispatchFnPtrType = PointerType::get(M->getContext(), 0);
-  GuardFnCFGlobal =
-      M->getOrInsertGlobal("__os_arm64x_check_icall_cfg", GuardFnPtrType);
-  GuardFnGlobal =
-      M->getOrInsertGlobal("__os_arm64x_check_icall", GuardFnPtrType);
-  DispatchFnGlobal =
-      M->getOrInsertGlobal("__os_arm64x_dispatch_call", DispatchFnPtrType);
+  GuardFnCFGlobal = M->getOrInsertGlobal("__os_arm64x_check_icall_cfg", PtrTy);
+  GuardFnGlobal = M->getOrInsertGlobal("__os_arm64x_check_icall", PtrTy);
+  DispatchFnGlobal = M->getOrInsertGlobal("__os_arm64x_dispatch_call", PtrTy);
 
   // Mangle names of function aliases and add the alias name to
   // arm64ec_unmangled_name metadata to ensure a weak anti-dependency symbol is
@@ -912,8 +897,7 @@ bool AArch64Arm64ECCallLowering::runOnModule(Module &Mod) {
     SmallVector<Constant *> ThunkMappingArrayElems;
     for (ThunkInfo &Thunk : ThunkMapping) {
       ThunkMappingArrayElems.push_back(ConstantStruct::getAnon(
-          {ConstantExpr::getBitCast(Thunk.Src, PtrTy),
-           ConstantExpr::getBitCast(Thunk.Dst, PtrTy),
+          {Thunk.Src, Thunk.Dst,
            ConstantInt::get(M->getContext(), APInt(32, uint8_t(Thunk.Kind)))}));
     }
     Constant *ThunkMappingArray = ConstantArray::get(
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 771eee1b3fecf..713f814121aa3 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1850,6 +1850,14 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
       setOperationAction(ISD::INTRINSIC_WO_CHAIN, VT, Custom);
   }
 
+  // Handle partial reduction operations
+  if (EnablePartialReduceNodes && Subtarget->isSVEorStreamingSVEAvailable()) {
+    // Mark known legal pairs as 'Legal' (these will expand to UDOT or SDOT).
+    // Other pairs will default to 'Expand'.
+    setPartialReduceMLAAction(MVT::nxv2i64, MVT::nxv8i16, Legal);
+    setPartialReduceMLAAction(MVT::nxv4i32, MVT::nxv16i8, Legal);
+  }
+
   // Handle operations that are only available in non-streaming SVE mode.
   if (Subtarget->isSVEAvailable()) {
     for (auto VT : {MVT::nxv16i8,  MVT::nxv8i16, MVT::nxv4i32,  MVT::nxv2i64,
@@ -1889,7 +1897,6 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
     }
   }
 
-
   if (Subtarget->hasMOPS() && Subtarget->hasMTE()) {
     // Only required for llvm.aarch64.mops.memset.tag
     setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
@@ -2595,11 +2602,6 @@ unsigned AArch64TargetLowering::ComputeNumSignBitsForTargetNode(
   case AArch64ISD::FCMEQ:
   case AArch64ISD::FCMGE:
   case AArch64ISD::FCMGT:
-  case AArch64ISD::FCMEQz:
-  case AArch64ISD::FCMGEz:
-  case AArch64ISD::FCMGTz:
-  case AArch64ISD::FCMLEz:
-  case AArch64ISD::FCMLTz:
     // Compares return either 0 or all-ones
     return VTBits;
   case AArch64ISD::VASHR: {
@@ -2816,11 +2818,6 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
     MAKE_CASE(AArch64ISD::FCMEQ)
     MAKE_CASE(AArch64ISD::FCMGE)
     MAKE_CASE(AArch64ISD::FCMGT)
-    MAKE_CASE(AArch64ISD::FCMEQz)
-    MAKE_CASE(AArch64ISD::FCMGEz)
-    MAKE_CASE(AArch64ISD::FCMGTz)
-    MAKE_CASE(AArch64ISD::FCMLEz)
-    MAKE_CASE(AArch64ISD::FCMLTz)
     MAKE_CASE(AArch64ISD::SADDV)
     MAKE_CASE(AArch64ISD::UADDV)
     MAKE_CASE(AArch64ISD::UADDLV)
@@ -8595,6 +8592,10 @@ static bool callConvSupportsVarArgs(CallingConv::ID CC) {
   switch (CC) {
   case CallingConv::C:
   case CallingConv::PreserveNone:
+  // SVE vector call is only partially supported, but it should
+  // support named arguments being passed. Any arguments being passed
+  // as varargs, are still unsupported.
+  case CallingConv::AArch64_SVE_VectorCall:
     return true;
   default:
     return false;
@@ -13872,25 +13873,27 @@ static SDValue tryToConvertShuffleOfTbl2ToTbl4(SDValue Op,
       DAG.getTargetConstant(Intrinsic::aarch64_neon_tbl2, dl, MVT::i64);
 
   EVT VT = Op.getValueType();
-  if (Tbl1->getOpcode() != ISD::INTRINSIC_WO_CHAIN ||
-      Tbl1->getOperand(0) != Tbl2ID ||
-      Tbl2->getOpcode() != ISD::INTRINSIC_WO_CHAIN ||
-      Tbl2->getOperand(0) != Tbl2ID)
+  if (Tbl1.getOpcode() != ISD::INTRINSIC_WO_CHAIN ||
+      Tbl1.getOperand(0) != Tbl2ID ||
+      Tbl2.getOpcode() != ISD::INTRINSIC_WO_CHAIN ||
+      Tbl2.getOperand(0) != Tbl2ID)
+    return SDValue();
+
+  if (Tbl1.getValueType() != MVT::v16i8 || Tbl2.getValueType() != MVT::v16i8)
     return SDValue();
 
-  if (Tbl1->getValueType(0) != MVT::v16i8 ||
-      Tbl2->getValueType(0) != MVT::v16i8)
+  SDValue Mask1 = Tbl1.getOperand(3);
+  SDValue Mask2 = Tbl2.getOperand(3);
+  if (Mask1.getOpcode() != ISD::BUILD_VECTOR ||
+      Mask2.getOpcode() != ISD::BUILD_VECTOR)
     return SDValue();
 
-  SDValue Mask1 = Tbl1->getOperand(3);
-  SDValue Mask2 = Tbl2->getOperand(3);
   SmallVector<SDValue, 16> TBLMaskParts(16, SDValue());
   for (unsigned I = 0; I < 16; I++) {
     if (ShuffleMask[I] < 16)
-      TBLMaskParts[I] = Mask1->getOperand(ShuffleMask[I]);
+      TBLMaskParts[I] = Mask1.getOperand(ShuffleMask[I]);
     else {
-      auto *C =
-          dyn_cast<ConstantSDNode>(Mask2->getOperand(ShuffleMask[I] - 16));
+      auto *C = dyn_cast<ConstantSDNode>(Mask2.getOperand(ShuffleMask[I] - 16));
       if (!C)
         return SDValue();
       TBLMaskParts[I] = DAG.getConstant(C->getSExtValue() + 32, dl, MVT::i32);
@@ -15827,40 +15830,19 @@ static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
   assert(VT.getSizeInBits() == SrcVT.getSizeInBits() &&
          "function only supposed to emit natural comparisons");
 
-  APInt SplatValue;
-  APInt SplatUndef;
-  unsigned SplatBitSize = 0;
-  bool HasAnyUndefs;
-
-  BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
-  bool IsCnst = BVN && BVN->isConstantSplat(SplatValue, SplatUndef,
-                                            SplatBitSize, HasAnyUndefs);
-
-  bool IsZero = IsCnst && SplatValue == 0;
-
   if (SrcVT.getVectorElementType().isFloatingPoint()) {
     switch (CC) {
     default:
       return SDValue();
     case AArch64CC::NE: {
-      SDValue Fcmeq;
-      if (IsZero)
-        Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
-      else
-        Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
+      SDValue Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
       return DAG.getNOT(dl, Fcmeq, VT);
     }
     case AArch64CC::EQ:
-      if (IsZero)
-        return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
       return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
     case AArch64CC::GE:
-      if (IsZero)
-        return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
       return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
     case AArch64CC::GT:
-      if (IsZero)
-        return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
       return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
     case AArch64CC::LE:
       if (!NoNans)
@@ -15868,8 +15850,6 @@ static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
       // If we ignore NaNs then we can use to the LS implementation.
       [[fallthrough]];
     case AArch64CC::LS:
-      if (IsZero)
-        return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
       return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
     case AArch64CC::LT:
       if (!NoNans)
@@ -15877,8 +15857,6 @@ static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
       // If we ignore NaNs then we can use to the MI implementation.
       [[fallthrough]];
     case AArch64CC::MI:
-      if (IsZero)
-        return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
       return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
     }
   }
@@ -16519,11 +16497,12 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
   return false;
 }
 
-bool AArch64TargetLowering::shouldReduceLoadWidth(SDNode *Load,
-                                                  ISD::LoadExtType ExtTy,
-                                                  EVT NewVT) const {
+bool AArch64TargetLowering::shouldReduceLoadWidth(
+    SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT,
+    std::optional<unsigned> ByteOffset) const {
   // TODO: This may be worth removing. Check regression tests for diffs.
-  if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT))
+  if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT,
+                                                 ByteOffset))
     return false;
 
   // If we're reducing the load width in order to avoid having to use an extra
@@ -28530,7 +28509,7 @@ bool AArch64TargetLowering::shouldLocalize(
         Imm, CI->getType(), TargetTransformInfo::TCK_CodeSize);
     assert(Cost.isValid() && "Expected a valid imm cost");
 
-    unsigned RematCost = *Cost.getValue();
+    unsigned RematCost = Cost.getValue();
     RematCost += AdditionalCost;
     Register Reg = MI.getOperand(0).getReg();
     unsigned MaxUses = maxUses(RematCost);
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 0d51ef2be8631..d9b535b910b80 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -245,13 +245,6 @@ enum NodeType : unsigned {
   FCMGE,
   FCMGT,
 
-  // Vector zero comparisons
-  FCMEQz,
-  FCMGEz,
-  FCMGTz,
-  FCMLEz,
-  FCMLTz,
-
   // Round wide FP to narrow FP with inexact results to odd.
   FCVTXN,
 
@@ -695,8 +688,8 @@ class AArch64TargetLowering : public TargetLowering {
                           MachineFunction &MF,
                           unsigned Intrinsic) const override;
 
-  bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
-                             EVT NewVT) const override;
+  bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT,
+                             std::optional<unsigned> ByteOffset) const override;
 
   bool shouldRemoveRedundantExtend(SDValue Op) const override;
 
diff --git a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
index 2d7a9d6f00bd0..a5f7b384b3e5d 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
@@ -61,34 +61,34 @@ let Predicates = [HasRCPC] in {
 }
 
 // 8-bit loads
-def : Pat<(seq_cst_load<atomic_load_az_8>  GPR64sp:$ptr), (LDARB GPR64sp:$ptr)>;
-def : Pat<(acquiring_load<atomic_load_az_8>  GPR64sp:$ptr), (LDARB GPR64sp:$ptr)>;
-def : Pat<(relaxed_load<atomic_load_az_8> (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
-                                                     ro_Wextend8:$offset)),
+def : Pat<(seq_cst_load<atomic_load_azext_8>  GPR64sp:$ptr), (LDARB GPR64sp:$ptr)>;
+def : Pat<(acquiring_load<atomic_load_azext_8>  GPR64sp:$ptr), (LDARB GPR64sp:$ptr)>;
+def : Pat<(relaxed_load<atomic_load_azext_8> (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
+                                                        ro_Wextend8:$offset)),
           (LDRBBroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$offset)>;
-def : Pat<(relaxed_load<atomic_load_az_8> (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
-                                                        ro_Xextend8:$offset)),
+def : Pat<(relaxed_load<atomic_load_azext_8> (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
+                                                           ro_Xextend8:$offset)),
           (LDRBBroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$offset)>;
-def : Pat<(relaxed_load<atomic_load_az_8> (am_indexed8 GPR64sp:$Rn,
-                                           uimm12s1:$offset)),
+def : Pat<(relaxed_load<atomic_load_azext_8> (am_indexed8 GPR64sp:$Rn,
+                                              uimm12s1:$offset)),
           (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
-def : Pat<(relaxed_load<atomic_load_az_8>
+def : Pat<(relaxed_load<atomic_load_azext_8>
                (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
           (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
 
 // 16-bit loads
-def : Pat<(seq_cst_load<atomic_load_az_16> GPR64sp:$ptr), (LDARH GPR64sp:$ptr)>;
-def : Pat<(acquiring_load<atomic_load_az_16> GPR64sp:$ptr), (LDARH GPR64sp:$ptr)>;
-def : Pat<(relaxed_load<atomic_load_az_16> (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
-                                                       ro_Wextend16:$extend)),
+def : Pat<(seq_cst_load<atomic_load_azext_16> GPR64sp:$ptr), (LDARH GPR64sp:$ptr)>;
+def : Pat<(acquiring_load<atomic_load_azext_16> GPR64sp:$ptr), (LDARH GPR64sp:$ptr)>;
+def : Pat<(relaxed_load<atomic_load_azext_16> (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
+                                                          ro_Wextend16:$extend)),
           (LDRHHroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend)>;
-def : Pat<(relaxed_load<atomic_load_az_16> (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
-                                                          ro_Xextend16:$extend)),
+def : Pat<(relaxed_load<atomic_load_azext_16> (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
+                                                             ro_Xextend16:$extend)),
           (LDRHHroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend)>;
-def : Pat<(relaxed_load<atomic_load_az_16> (am_indexed16 GPR64sp:$Rn,
-                                                         uimm12s2:$offset)),
+def : Pat<(relaxed_load<atomic_load_azext_16> (am_indexed16 GPR64sp:$Rn,
+                                                            uimm12s2:$offset)),
           (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>;
-def : Pat<(relaxed_load<atomic_load_az_16>
+def : Pat<(relaxed_load<atomic_load_azext_16>
                (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
           (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
 
@@ -591,10 +591,10 @@ let Predicates = [HasRCPC3, HasNEON] in {
 // v8.4a FEAT_LRCPC2 patterns
 let Predicates = [HasRCPC_IMMO, UseLDAPUR] in {
   // Load-Acquire RCpc Register unscaled loads
-  def : Pat<(acquiring_load<atomic_load_az_8>
+  def : Pat<(acquiring_load<atomic_load_azext_8>
                (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
           (LDAPURBi GPR64sp:$Rn, simm9:$offset)>;
-  def : Pat<(acquiring_load<atomic_load_az_16>
+  def : Pat<(acquiring_load<atomic_load_azext_16>
                (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
           (LDAPURHi GPR64sp:$Rn, simm9:$offset)>;
   def : Pat<(acquiring_load<atomic_load_32>
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 9bbcb6f3aedf5..2a0da9a1373ee 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -7136,7 +7136,7 @@ multiclass SIMDCmpTwoVector<bit U, bits<5> opc, string asm,
 
 // FP Comparisons support only S and D element sizes (and H for v8.2a).
 multiclass SIMDFPCmpTwoVector<bit U, bit S, bits<5> opc,
-                              string asm, SDNode OpNode> {
+                              string asm, SDPatternOperator OpNode> {
 
   let mayRaiseFPException = 1, Uses = [FPCR] in {
   let Predicates = [HasNEON, HasFullFP16] in {
diff --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
index a99019d72b4ac..7322212c5bb24 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
@@ -179,36 +179,6 @@ def G_FCMGT : AArch64GenericInstruction {
   let hasSideEffects = 0;
 }
 
-def G_FCMEQZ : AArch64GenericInstruction {
-  let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins type0:$src);
-  let hasSideEffects = 0;
-}
-
-def G_FCMGEZ : AArch64GenericInstruction {
-  let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins type0:$src);
-  let hasSideEffects = 0;
-}
-
-def G_FCMGTZ : AArch64GenericInstruction {
-  let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins type0:$src);
-  let hasSideEffects = 0;
-}
-
-def G_FCMLEZ : AArch64GenericInstruction {
-  let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins type0:$src);
-  let hasSideEffects = 0;
-}
-
-def G_FCMLTZ : AArch64GenericInstruction {
-  let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins type0:$src);
-  let hasSideEffects = 0;
-}
-
 def G_AARCH64_PREFETCH : AArch64GenericInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins type0:$imm, ptype0:$src1);
@@ -295,12 +265,6 @@ def : GINodeEquiv<G_FCMEQ, AArch64fcmeq>;
 def : GINodeEquiv<G_FCMGE, AArch64fcmge>;
 def : GINodeEquiv<G_FCMGT, AArch64fcmgt>;
 
-def : GINodeEquiv<G_FCMEQZ, AArch64fcmeqz>;
-def : GINodeEquiv<G_FCMGEZ, AArch64fcmgez>;
-def : GINodeEquiv<G_FCMGTZ, AArch64fcmgtz>;
-def : GINodeEquiv<G_FCMLEZ, AArch64fcmlez>;
-def : GINodeEquiv<G_FCMLTZ, AArch64fcmltz>;
-
 def : GINodeEquiv<G_BSP, AArch64bsp>;
 
 def : GINodeEquiv<G_UMULL, AArch64umull>;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index a060a2f597ccd..7f7e1d20ae604 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -882,11 +882,20 @@ def AArch64cmltz : PatFrag<(ops node:$lhs),
 def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
                            (vnot (AArch64cmeqz (and node:$LHS, node:$RHS)))>;
 
-def AArch64fcmeqz: SDNode<"AArch64ISD::FCMEQz", SDT_AArch64fcmpz>;
-def AArch64fcmgez: SDNode<"AArch64ISD::FCMGEz", SDT_AArch64fcmpz>;
-def AArch64fcmgtz: SDNode<"AArch64ISD::FCMGTz", SDT_AArch64fcmpz>;
-def AArch64fcmlez: SDNode<"AArch64ISD::FCMLEz", SDT_AArch64fcmpz>;
-def AArch64fcmltz: SDNode<"AArch64ISD::FCMLTz", SDT_AArch64fcmpz>;
+def AArch64fcmeqz : PatFrag<(ops node:$lhs),
+                            (AArch64fcmeq node:$lhs, immAllZerosV)>;
+
+def AArch64fcmgez : PatFrag<(ops node:$lhs),
+                            (AArch64fcmge node:$lhs, immAllZerosV)>;
+
+def AArch64fcmgtz : PatFrag<(ops node:$lhs),
+                            (AArch64fcmgt node:$lhs, immAllZerosV)>;
+
+def AArch64fcmlez : PatFrag<(ops node:$lhs),
+                            (AArch64fcmge immAllZerosV, node:$lhs)>;
+
+def AArch64fcmltz : PatFrag<(ops node:$lhs),
+                            (AArch64fcmgt immAllZerosV, node:$lhs)>;
 
 def AArch64fcvtxn_n: SDNode<"AArch64ISD::FCVTXN", SDTFPRoundOp>;
 def AArch64fcvtxnsdr: PatFrags<(ops node:$Rn),
@@ -5679,6 +5688,17 @@ def : Pat<(v4i32 (bswap (v4i32 V128:$Rn))),
 def : Pat<(v2i64 (bswap (v2i64 V128:$Rn))),
           (v2i64 (REV64v16i8 (v2i64 V128:$Rn)))>;
 
+// Patterns for funnel shifts to be matched to equivalent REV instructions
+def : Pat<(v2i64 (or (v2i64 (AArch64vshl (v2i64 V128:$Rn), (i32 32))), 
+                     (v2i64 (AArch64vlshr (v2i64 V128:$Rn), (i32 32))))), 
+          (v2i64 (REV64v4i32 (v2i64 V128:$Rn)))>;
+def : Pat<(v4i32 (or (v4i32 (AArch64vshl (v4i32 V128:$Rn), (i32 16))), 
+                     (v4i32 (AArch64vlshr (v4i32 V128:$Rn), (i32 16))))), 
+          (v4i32 (REV32v8i16 (v4i32 V128:$Rn)))>;
+def : Pat<(v2i32 (or (v2i32 (AArch64vshl (v2i32 V64:$Rn), (i32 16))), 
+                     (v2i32 (AArch64vlshr (v2i32 V64:$Rn), (i32 16))))), 
+          (v2i32 (REV32v4i16 (v2i32 V64:$Rn)))>;
+
 //===----------------------------------------------------------------------===//
 // Advanced SIMD three vector instructions.
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
index 7c47492cf1a8e..0e26005f6e6be 100644
--- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -892,11 +892,10 @@ AArch64LoadStoreOpt::mergeNarrowZeroStores(MachineBasicBlock::iterator I,
     OffsetImm = IOffsetInBytes;
 
   int NewOpcode = getMatchingWideOpcode(Opc);
-  bool FinalIsScaled = !TII->hasUnscaledLdStOffset(NewOpcode);
-
-  // Adjust final offset if the result opcode is a scaled store.
-  if (FinalIsScaled) {
-    int NewOffsetStride = FinalIsScaled ? TII->getMemScale(NewOpcode) : 1;
+  // Adjust final offset on scaled stores because the new instruction
+  // has a different scale.
+  if (!TII->hasUnscaledLdStOffset(NewOpcode)) {
+    int NewOffsetStride = TII->getMemScale(NewOpcode);
     assert(((OffsetImm % NewOffsetStride) == 0) &&
            "Offset should be a multiple of the store memory scale");
     OffsetImm = OffsetImm / NewOffsetStride;
@@ -906,7 +905,7 @@ AArch64LoadStoreOpt::mergeNarrowZeroStores(MachineBasicBlock::iterator I,
   DebugLoc DL = I->getDebugLoc();
   MachineBasicBlock *MBB = I->getParent();
   MachineInstrBuilder MIB;
-  MIB = BuildMI(*MBB, InsertionPoint, DL, TII->get(getMatchingWideOpcode(Opc)))
+  MIB = BuildMI(*MBB, InsertionPoint, DL, TII->get(NewOpcode))
             .addReg(isNarrowStore(Opc) ? AArch64::WZR : AArch64::XZR)
             .add(BaseRegOp)
             .addImm(OffsetImm)
diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
index a83b17f7c9000..363ecee49c0f2 100644
--- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
@@ -1091,8 +1091,8 @@ let Predicates = [HasSME2p2] in {
 
 } // [HasSME2p2]
 
-let Predicates = [HasSME_MOP4, HasSMEF8F16], Uses = [FPMR, FPCR] in {
-  defm FMOP4A : sme2_fmop4a_fp8_fp16_2way<"fmop4a">;
+let Predicates = [HasSME_MOP4, HasSMEF8F16] in {
+  defm FMOP4A : sme2_fmop4a_fp8_fp16_2way<"fmop4a", "int_aarch64_sme_fp8_fmop4a_za16">;
 }
 
 let Predicates = [HasSME_MOP4, HasSMEF16F16] in {
@@ -1105,10 +1105,8 @@ let Predicates = [HasSME2, HasSVEBFSCALE] in {
   defm BFMUL : sme2_bfmul_multi<"bfmul">;
 }
 
-let Uses = [FPMR, FPCR] in {
 let Predicates = [HasSME_MOP4, HasSMEF8F32] in {
-  defm FMOP4A : sme2_fmop4a_fp8_fp32_4way<"fmop4a">;
-}
+  defm FMOP4A : sme2_fmop4a_fp8_fp32_4way<"fmop4a", "int_aarch64_sme_fp8_fmop4a_za32">;
 }
 
 let Predicates = [HasSME_MOP4, HasSMEB16B16] in {
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index d13728ec930c8..bd394671881e8 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -653,6 +653,17 @@ let Predicates = [HasSVE_or_SME] in {
   defm SDOT_ZZZ : sve_intx_dot<0b0, "sdot", AArch64sdot>;
   defm UDOT_ZZZ : sve_intx_dot<0b1, "udot", AArch64udot>;
 
+  let Predicates = [HasSVE_or_SME] in {
+    def : Pat<(nxv4i32 (partial_reduce_umla nxv4i32:$Acc, nxv16i8:$MulLHS, nxv16i8:$MulRHS)),
+              (UDOT_ZZZ_S $Acc, $MulLHS, $MulRHS)>;
+    def : Pat<(nxv4i32 (partial_reduce_smla nxv4i32:$Acc, nxv16i8:$MulLHS, nxv16i8:$MulRHS)),
+              (SDOT_ZZZ_S $Acc, $MulLHS, $MulRHS)>;
+    def : Pat<(nxv2i64 (partial_reduce_umla nxv2i64:$Acc, nxv8i16:$MulLHS, nxv8i16:$MulRHS)),
+              (UDOT_ZZZ_D $Acc, $MulLHS, $MulRHS)>;
+    def : Pat<(nxv2i64 (partial_reduce_smla nxv2i64:$Acc, nxv8i16:$MulLHS, nxv8i16:$MulRHS)),
+              (SDOT_ZZZ_D $Acc, $MulLHS, $MulRHS)>;
+  } // End HasSVE_or_SME
+
   defm SDOT_ZZZI : sve_intx_dot_by_indexed_elem<0b0, "sdot", int_aarch64_sve_sdot_lane>;
   defm UDOT_ZZZI : sve_intx_dot_by_indexed_elem<0b1, "udot", int_aarch64_sve_udot_lane>;
 
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index a20f1c104834d..c670b2ae71bf3 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -1497,6 +1497,65 @@ static bool isAllActivePredicate(Value *Pred) {
   return (C && C->isAllOnesValue());
 }
 
+// Simplify `V` by only considering the operations that affect active lanes.
+// This function should only return existing Values or newly created Constants.
+static Value *stripInactiveLanes(Value *V, const Value *Pg) {
+  auto *Dup = dyn_cast<IntrinsicInst>(V);
+  if (Dup && Dup->getIntrinsicID() == Intrinsic::aarch64_sve_dup &&
+      Dup->getOperand(1) == Pg && isa<Constant>(Dup->getOperand(2)))
+    return ConstantVector::getSplat(
+        cast<VectorType>(V->getType())->getElementCount(),
+        cast<Constant>(Dup->getOperand(2)));
+
+  return V;
+}
+
+static std::optional<Instruction *>
+simplifySVEIntrinsicBinOp(InstCombiner &IC, IntrinsicInst &II,
+                          const SVEIntrinsicInfo &IInfo) {
+  const unsigned Opc = IInfo.getMatchingIROpode();
+  assert(Instruction::isBinaryOp(Opc) && "Expected a binary operation!");
+
+  Value *Pg = II.getOperand(0);
+  Value *Op1 = II.getOperand(1);
+  Value *Op2 = II.getOperand(2);
+  const DataLayout &DL = II.getDataLayout();
+
+  // Canonicalise constants to the RHS.
+  if (Instruction::isCommutative(Opc) && IInfo.inactiveLanesAreNotDefined() &&
+      isa<Constant>(Op1) && !isa<Constant>(Op2)) {
+    IC.replaceOperand(II, 1, Op2);
+    IC.replaceOperand(II, 2, Op1);
+    return &II;
+  }
+
+  // Only active lanes matter when simplifying the operation.
+  Op1 = stripInactiveLanes(Op1, Pg);
+  Op2 = stripInactiveLanes(Op2, Pg);
+
+  Value *SimpleII;
+  if (auto FII = dyn_cast<FPMathOperator>(&II))
+    SimpleII = simplifyBinOp(Opc, Op1, Op2, FII->getFastMathFlags(), DL);
+  else
+    SimpleII = simplifyBinOp(Opc, Op1, Op2, DL);
+
+  if (!SimpleII)
+    return std::nullopt;
+
+  if (IInfo.inactiveLanesAreNotDefined())
+    return IC.replaceInstUsesWith(II, SimpleII);
+
+  Value *Inactive = II.getOperand(IInfo.getOperandIdxInactiveLanesTakenFrom());
+
+  // The intrinsic does nothing (e.g. sve.mul(pg, A, 1.0)).
+  if (SimpleII == Inactive)
+    return IC.replaceInstUsesWith(II, SimpleII);
+
+  // Inactive lanes must be preserved.
+  SimpleII = IC.Builder.CreateSelect(Pg, SimpleII, Inactive);
+  return IC.replaceInstUsesWith(II, SimpleII);
+}
+
 // Use SVE intrinsic info to eliminate redundant operands and/or canonicalise
 // to operations with less strict inactive lane requirements.
 static std::optional<Instruction *>
@@ -1537,6 +1596,11 @@ simplifySVEIntrinsic(InstCombiner &IC, IntrinsicInst &II,
     }
   }
 
+  // Operation specific simplifications.
+  if (IInfo.hasMatchingIROpode() &&
+      Instruction::isBinaryOp(IInfo.getMatchingIROpode()))
+    return simplifySVEIntrinsicBinOp(IC, II, IInfo);
+
   return std::nullopt;
 }
 
@@ -2220,68 +2284,6 @@ static std::optional<Instruction *> instCombineSVEVectorSub(InstCombiner &IC,
   return std::nullopt;
 }
 
-// Simplify `V` by only considering the operations that affect active lanes.
-// This function should only return existing Values or newly created Constants.
-static Value *stripInactiveLanes(Value *V, const Value *Pg) {
-  auto *Dup = dyn_cast<IntrinsicInst>(V);
-  if (Dup && Dup->getIntrinsicID() == Intrinsic::aarch64_sve_dup &&
-      Dup->getOperand(1) == Pg && isa<Constant>(Dup->getOperand(2)))
-    return ConstantVector::getSplat(
-        cast<VectorType>(V->getType())->getElementCount(),
-        cast<Constant>(Dup->getOperand(2)));
-
-  return V;
-}
-
-static std::optional<Instruction *>
-instCombineSVEVectorMul(InstCombiner &IC, IntrinsicInst &II,
-                        const SVEIntrinsicInfo &IInfo) {
-  const unsigned Opc = IInfo.getMatchingIROpode();
-  if (!Instruction::isBinaryOp(Opc))
-    return std::nullopt;
-
-  Value *Pg = II.getOperand(0);
-  Value *Op1 = II.getOperand(1);
-  Value *Op2 = II.getOperand(2);
-  const DataLayout &DL = II.getDataLayout();
-
-  // Canonicalise constants to the RHS.
-  if (Instruction::isCommutative(Opc) && IInfo.inactiveLanesAreNotDefined() &&
-      isa<Constant>(Op1) && !isa<Constant>(Op2)) {
-    IC.replaceOperand(II, 1, Op2);
-    IC.replaceOperand(II, 2, Op1);
-    return &II;
-  }
-
-  // Only active lanes matter when simplifying the operation.
-  Op1 = stripInactiveLanes(Op1, Pg);
-  Op2 = stripInactiveLanes(Op2, Pg);
-
-  Value *SimpleII;
-  if (auto FII = dyn_cast<FPMathOperator>(&II))
-    SimpleII = simplifyBinOp(Opc, Op1, Op2, FII->getFastMathFlags(), DL);
-  else
-    SimpleII = simplifyBinOp(Opc, Op1, Op2, DL);
-
-  if (SimpleII) {
-    if (IInfo.inactiveLanesAreNotDefined())
-      return IC.replaceInstUsesWith(II, SimpleII);
-
-    Value *Inactive =
-        II.getOperand(IInfo.getOperandIdxInactiveLanesTakenFrom());
-
-    // The intrinsic does nothing (e.g. sve.mul(pg, A, 1.0)).
-    if (SimpleII == Inactive)
-      return IC.replaceInstUsesWith(II, SimpleII);
-
-    // Inactive lanes must be preserved.
-    SimpleII = IC.Builder.CreateSelect(Pg, SimpleII, Inactive);
-    return IC.replaceInstUsesWith(II, SimpleII);
-  }
-
-  return instCombineSVEVectorBinOp(IC, II);
-}
-
 static std::optional<Instruction *> instCombineSVEUnpack(InstCombiner &IC,
                                                          IntrinsicInst &II) {
   Value *UnpackArg = II.getArgOperand(0);
@@ -2689,10 +2691,8 @@ AArch64TTIImpl::instCombineIntrinsic(InstCombiner &IC,
     return instCombineSVEVectorFAdd(IC, II);
   case Intrinsic::aarch64_sve_fadd_u:
     return instCombineSVEVectorFAddU(IC, II);
-  case Intrinsic::aarch64_sve_fmul:
-    return instCombineSVEVectorMul(IC, II, IInfo);
   case Intrinsic::aarch64_sve_fmul_u:
-    return instCombineSVEVectorMul(IC, II, IInfo);
+    return instCombineSVEVectorBinOp(IC, II);
   case Intrinsic::aarch64_sve_fsub:
     return instCombineSVEVectorFSub(IC, II);
   case Intrinsic::aarch64_sve_fsub_u:
@@ -2703,10 +2703,6 @@ AArch64TTIImpl::instCombineIntrinsic(InstCombiner &IC,
     return instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_mul_u,
                                              Intrinsic::aarch64_sve_mla_u>(
         IC, II, true);
-  case Intrinsic::aarch64_sve_mul:
-    return instCombineSVEVectorMul(IC, II, IInfo);
-  case Intrinsic::aarch64_sve_mul_u:
-    return instCombineSVEVectorMul(IC, II, IInfo);
   case Intrinsic::aarch64_sve_sub:
     return instCombineSVEVectorSub(IC, II);
   case Intrinsic::aarch64_sve_sub_u:
@@ -4618,7 +4614,7 @@ static bool isLoopSizeWithinBudget(Loop *L, const AArch64TTIImpl &TTI,
   }
 
   if (FinalSize)
-    *FinalSize = *LoopCost.getValue();
+    *FinalSize = LoopCost.getValue();
   return true;
 }
 
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 2afd24555b28c..e0c693bff3c0a 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -5743,9 +5743,13 @@ AArch64InstructionSelector::emitConstantVector(Register Dst, Constant *CV,
     }
   }
 
-  if (CV->getSplatValue()) {
+  if (Constant *SplatValue = CV->getSplatValue()) {
+    APInt SplatValueAsInt =
+        isa<ConstantFP>(SplatValue)
+            ? cast<ConstantFP>(SplatValue)->getValueAPF().bitcastToAPInt()
+            : SplatValue->getUniqueInteger();
     APInt DefBits = APInt::getSplat(
-        DstSize, CV->getUniqueInteger().trunc(DstTy.getScalarSizeInBits()));
+        DstSize, SplatValueAsInt.trunc(DstTy.getScalarSizeInBits()));
     auto TryMOVIWithBits = [&](APInt DefBits) -> MachineInstr * {
       MachineInstr *NewOp;
       bool Inv = false;
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index 4785c7b68d94d..81ee525ed0501 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -808,16 +808,14 @@ void applyScalarizeVectorUnmerge(MachineInstr &MI, MachineRegisterInfo &MRI,
 
 bool matchBuildVectorToDup(MachineInstr &MI, MachineRegisterInfo &MRI) {
   assert(MI.getOpcode() == TargetOpcode::G_BUILD_VECTOR);
-  auto Splat = getAArch64VectorSplat(MI, MRI);
-  if (!Splat)
-    return false;
-  if (Splat->isReg())
-    return true;
+
   // Later, during selection, we'll try to match imported patterns using
   // immAllOnesV and immAllZerosV. These require G_BUILD_VECTOR. Don't lower
   // G_BUILD_VECTORs which could match those patterns.
-  int64_t Cst = Splat->getCst();
-  return (Cst != 0 && Cst != -1);
+  if (isBuildVectorAllZeros(MI, MRI) || isBuildVectorAllOnes(MI, MRI))
+    return false;
+
+  return getAArch64VectorSplat(MI, MRI).has_value();
 }
 
 void applyBuildVectorToDup(MachineInstr &MI, MachineRegisterInfo &MRI,
@@ -933,11 +931,10 @@ void applySwapICmpOperands(MachineInstr &MI, GISelChangeObserver &Observer) {
 
 /// \returns a function which builds a vector floating point compare instruction
 /// for a condition code \p CC.
-/// \param [in] IsZero - True if the comparison is against 0.
 /// \param [in] NoNans - True if the target has NoNansFPMath.
 std::function<Register(MachineIRBuilder &)>
-getVectorFCMP(AArch64CC::CondCode CC, Register LHS, Register RHS, bool IsZero,
-              bool NoNans, MachineRegisterInfo &MRI) {
+getVectorFCMP(AArch64CC::CondCode CC, Register LHS, Register RHS, bool NoNans,
+              MachineRegisterInfo &MRI) {
   LLT DstTy = MRI.getType(LHS);
   assert(DstTy.isVector() && "Expected vector types only?");
   assert(DstTy == MRI.getType(RHS) && "Src and Dst types must match!");
@@ -945,46 +942,29 @@ getVectorFCMP(AArch64CC::CondCode CC, Register LHS, Register RHS, bool IsZero,
   default:
     llvm_unreachable("Unexpected condition code!");
   case AArch64CC::NE:
-    return [LHS, RHS, IsZero, DstTy](MachineIRBuilder &MIB) {
-      auto FCmp = IsZero
-                      ? MIB.buildInstr(AArch64::G_FCMEQZ, {DstTy}, {LHS})
-                      : MIB.buildInstr(AArch64::G_FCMEQ, {DstTy}, {LHS, RHS});
+    return [LHS, RHS, DstTy](MachineIRBuilder &MIB) {
+      auto FCmp = MIB.buildInstr(AArch64::G_FCMEQ, {DstTy}, {LHS, RHS});
       return MIB.buildNot(DstTy, FCmp).getReg(0);
     };
   case AArch64CC::EQ:
-    return [LHS, RHS, IsZero, DstTy](MachineIRBuilder &MIB) {
-      return IsZero
-                 ? MIB.buildInstr(AArch64::G_FCMEQZ, {DstTy}, {LHS}).getReg(0)
-                 : MIB.buildInstr(AArch64::G_FCMEQ, {DstTy}, {LHS, RHS})
-                       .getReg(0);
+    return [LHS, RHS, DstTy](MachineIRBuilder &MIB) {
+      return MIB.buildInstr(AArch64::G_FCMEQ, {DstTy}, {LHS, RHS}).getReg(0);
     };
   case AArch64CC::GE:
-    return [LHS, RHS, IsZero, DstTy](MachineIRBuilder &MIB) {
-      return IsZero
-                 ? MIB.buildInstr(AArch64::G_FCMGEZ, {DstTy}, {LHS}).getReg(0)
-                 : MIB.buildInstr(AArch64::G_FCMGE, {DstTy}, {LHS, RHS})
-                       .getReg(0);
+    return [LHS, RHS, DstTy](MachineIRBuilder &MIB) {
+      return MIB.buildInstr(AArch64::G_FCMGE, {DstTy}, {LHS, RHS}).getReg(0);
     };
   case AArch64CC::GT:
-    return [LHS, RHS, IsZero, DstTy](MachineIRBuilder &MIB) {
-      return IsZero
-                 ? MIB.buildInstr(AArch64::G_FCMGTZ, {DstTy}, {LHS}).getReg(0)
-                 : MIB.buildInstr(AArch64::G_FCMGT, {DstTy}, {LHS, RHS})
-                       .getReg(0);
+    return [LHS, RHS, DstTy](MachineIRBuilder &MIB) {
+      return MIB.buildInstr(AArch64::G_FCMGT, {DstTy}, {LHS, RHS}).getReg(0);
     };
   case AArch64CC::LS:
-    return [LHS, RHS, IsZero, DstTy](MachineIRBuilder &MIB) {
-      return IsZero
-                 ? MIB.buildInstr(AArch64::G_FCMLEZ, {DstTy}, {LHS}).getReg(0)
-                 : MIB.buildInstr(AArch64::G_FCMGE, {DstTy}, {RHS, LHS})
-                       .getReg(0);
+    return [LHS, RHS, DstTy](MachineIRBuilder &MIB) {
+      return MIB.buildInstr(AArch64::G_FCMGE, {DstTy}, {RHS, LHS}).getReg(0);
     };
   case AArch64CC::MI:
-    return [LHS, RHS, IsZero, DstTy](MachineIRBuilder &MIB) {
-      return IsZero
-                 ? MIB.buildInstr(AArch64::G_FCMLTZ, {DstTy}, {LHS}).getReg(0)
-                 : MIB.buildInstr(AArch64::G_FCMGT, {DstTy}, {RHS, LHS})
-                       .getReg(0);
+    return [LHS, RHS, DstTy](MachineIRBuilder &MIB) {
+      return MIB.buildInstr(AArch64::G_FCMGT, {DstTy}, {RHS, LHS}).getReg(0);
     };
   }
 }
@@ -1024,23 +1004,17 @@ void applyLowerVectorFCMP(MachineInstr &MI, MachineRegisterInfo &MRI,
 
   LLT DstTy = MRI.getType(Dst);
 
-  auto Splat = getAArch64VectorSplat(*MRI.getVRegDef(RHS), MRI);
-
-  // Compares against 0 have special target-specific pseudos.
-  bool IsZero = Splat && Splat->isCst() && Splat->getCst() == 0;
-
   bool Invert = false;
   AArch64CC::CondCode CC, CC2 = AArch64CC::AL;
   if ((Pred == CmpInst::Predicate::FCMP_ORD ||
        Pred == CmpInst::Predicate::FCMP_UNO) &&
-      IsZero) {
+      isBuildVectorAllZeros(*MRI.getVRegDef(RHS), MRI)) {
     // The special case "fcmp ord %a, 0" is the canonical check that LHS isn't
     // NaN, so equivalent to a == a and doesn't need the two comparisons an
     // "ord" normally would.
     // Similarly, "fcmp uno %a, 0" is the canonical check that LHS is NaN and is
     // thus equivalent to a != a.
     RHS = LHS;
-    IsZero = false;
     CC = Pred == CmpInst::Predicate::FCMP_ORD ? AArch64CC::EQ : AArch64CC::NE;
   } else
     changeVectorFCMPPredToAArch64CC(Pred, CC, CC2, Invert);
@@ -1051,12 +1025,12 @@ void applyLowerVectorFCMP(MachineInstr &MI, MachineRegisterInfo &MRI,
   const bool NoNans =
       ST.getTargetLowering()->getTargetMachine().Options.NoNaNsFPMath;
 
-  auto Cmp = getVectorFCMP(CC, LHS, RHS, IsZero, NoNans, MRI);
+  auto Cmp = getVectorFCMP(CC, LHS, RHS, NoNans, MRI);
   Register CmpRes;
   if (CC2 == AArch64CC::AL)
     CmpRes = Cmp(MIB);
   else {
-    auto Cmp2 = getVectorFCMP(CC2, LHS, RHS, IsZero, NoNans, MRI);
+    auto Cmp2 = getVectorFCMP(CC2, LHS, RHS, NoNans, MRI);
     auto Cmp2Dst = Cmp2(MIB);
     auto Cmp1Dst = Cmp(MIB);
     CmpRes = MIB.buildOr(DstTy, Cmp1Dst, Cmp2Dst).getReg(0);
diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td
index b174a2a733851..446aa45aaa38a 100644
--- a/llvm/lib/Target/AArch64/SMEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td
@@ -5815,20 +5815,37 @@ class sme2_fp8_fp32_quarter_tile_outer_product<bit M, bit N, string mnemonic, Re
   let Inst{1-0} = ZAda;
 
   let Constraints = "$ZAda = $_ZAda";
+  let Uses = [FPMR, FPCR];
 }
 
-multiclass sme2_fmop4a_fp8_fp32_4way<string mnemonic> {
+multiclass sme2_fmop4a_fp8_fp32_4way<string mnemonic, string op> {
   // Single vectors
-  def _MZZ_BtoS : sme2_fp8_fp32_quarter_tile_outer_product<0, 0, mnemonic, ZPR8Mul2_Lo, ZPR8Mul2_Hi>;
+  def _MZZ_BtoS : sme2_fp8_fp32_quarter_tile_outer_product<0, 0, mnemonic, ZPR8Mul2_Lo, ZPR8Mul2_Hi>, SMEPseudo2Instr<NAME # _MZZ_BtoS, 1>;
+
+  def NAME # _MZZ_BtoS_PSEUDO : sme2_quarter_tile_outer_product_pseudo<ZPR8Mul2_Lo, ZPR8Mul2_Hi, SMEMatrixTileS>, SMEPseudo2Instr<NAME # _MZZ_BtoS, 0>;
+
+  def : SME2_ZA_Tile_Vec_Single_Single_Pat<NAME # _MZZ_BtoS, !cast<SDPatternOperator>(op # "_1x1"), timm32_0_3, nxv16i8>;
 
   // Multiple and single vectors
-  def _M2ZZ_BtoS : sme2_fp8_fp32_quarter_tile_outer_product<0, 1, mnemonic, ZZ_b_mul_r_Lo, ZPR8Mul2_Hi>;
+  def _M2ZZ_BtoS : sme2_fp8_fp32_quarter_tile_outer_product<0, 1, mnemonic, ZZ_b_mul_r_Lo, ZPR8Mul2_Hi>, SMEPseudo2Instr<NAME # _M2ZZ_BtoS, 1>;
+
+  def NAME # _M2ZZ_BtoS_PSEUDO : sme2_quarter_tile_outer_product_pseudo<ZZ_b_mul_r_Lo, ZPR8Mul2_Hi, SMEMatrixTileS>, SMEPseudo2Instr<NAME # _M2ZZ_BtoS, 0>;
+
+  def : SME2_ZA_Tile_Vec_Multi_Single_Pat<NAME # _M2ZZ_BtoS, !cast<SDPatternOperator>(op # "_2x1"), timm32_0_3, nxv16i8>;
 
   // Single and multiple vectors
-  def _MZ2Z_BtoS : sme2_fp8_fp32_quarter_tile_outer_product<1, 0, mnemonic, ZPR8Mul2_Lo, ZZ_b_mul_r_Hi>;
+  def _MZ2Z_BtoS : sme2_fp8_fp32_quarter_tile_outer_product<1, 0, mnemonic, ZPR8Mul2_Lo, ZZ_b_mul_r_Hi>, SMEPseudo2Instr<NAME # _MZ2Z_BtoS, 1>;
+
+  def NAME # _MZ2Z_BtoS_PSEUDO : sme2_quarter_tile_outer_product_pseudo<ZPR8Mul2_Lo, ZZ_b_mul_r_Hi, SMEMatrixTileS>, SMEPseudo2Instr<NAME # _MZ2Z_BtoS, 0>;
+
+  def : SME2_ZA_Tile_Vec_Multi_Pat<NAME # _MZ2Z_BtoS, !cast<SDPatternOperator>(op # "_1x2"), timm32_0_3, nxv16i8>;
 
   // Multiple vectors
-  def _M2Z2Z_BtoS : sme2_fp8_fp32_quarter_tile_outer_product<1, 1, mnemonic, ZZ_b_mul_r_Lo, ZZ_b_mul_r_Hi>;
+  def _M2Z2Z_BtoS : sme2_fp8_fp32_quarter_tile_outer_product<1, 1, mnemonic, ZZ_b_mul_r_Lo, ZZ_b_mul_r_Hi>, SMEPseudo2Instr<NAME # _M2Z2Z_BtoS, 1>;
+
+  def NAME # _M2Z2Z_BtoS_PSEUDO : sme2_quarter_tile_outer_product_pseudo<ZZ_b_mul_r_Lo, ZZ_b_mul_r_Hi, SMEMatrixTileS>, SMEPseudo2Instr<NAME # _M2Z2Z_BtoS, 0>;
+
+  def : SME2_ZA_Tile_Vec_Multi_Multi_Pat<NAME # _M2Z2Z_BtoS, !cast<SDPatternOperator>(op # "_2x2"), timm32_0_3, nxv16i8>;
 }
 
 class sme2_bf16_fp16_quarter_tile_outer_product<bit M, bit N, bit S, string mnemonic, RegisterOperand zn_ty, RegisterOperand zm_ty>
@@ -6062,20 +6079,38 @@ class sme2_fp8_fp16_quarter_tile_outer_product<bit M, bit N, string mnemonic, Re
   let Inst{0} = ZAda;
 
   let Constraints = "$ZAda = $_ZAda";
+  let Uses = [FPMR, FPCR];
 }
 
-multiclass sme2_fmop4a_fp8_fp16_2way<string mnemonic> {
+multiclass sme2_fmop4a_fp8_fp16_2way<string mnemonic, string op> {
+
   // Single vectors
-  def _MZZ_BtoH : sme2_fp8_fp16_quarter_tile_outer_product<0b0, 0b0, mnemonic, ZPR8Mul2_Lo, ZPR8Mul2_Hi>;
+  def _MZZ_BtoH : sme2_fp8_fp16_quarter_tile_outer_product<0b0, 0b0, mnemonic, ZPR8Mul2_Lo, ZPR8Mul2_Hi>, SMEPseudo2Instr<NAME # _MZZ_BtoH, 1>;
+
+  def NAME # _MZZ_BtoH_PSEUDO : sme2_quarter_tile_outer_product_pseudo<ZPR8Mul2_Lo, ZPR8Mul2_Hi, SMEMatrixTileH>, SMEPseudo2Instr<NAME # _MZZ_BtoH, 0>;
+
+  def : SME2_ZA_Tile_Vec_Single_Single_Pat<NAME # _MZZ_BtoH, !cast<SDPatternOperator>(op # "_1x1"), timm32_0_1, nxv16i8>;
 
   // Multiple and single vectors
-  def _M2ZZ_BtoH : sme2_fp8_fp16_quarter_tile_outer_product<0b0, 0b1, mnemonic, ZZ_b_mul_r_Lo, ZPR8Mul2_Hi>;
+  def _M2ZZ_BtoH : sme2_fp8_fp16_quarter_tile_outer_product<0b0, 0b1, mnemonic, ZZ_b_mul_r_Lo, ZPR8Mul2_Hi>, SMEPseudo2Instr<NAME # _M2ZZ_BtoH, 1>;
+
+  def NAME # _M2ZZ_BtoH_PSEUDO : sme2_quarter_tile_outer_product_pseudo<ZZ_b_mul_r_Lo, ZPR8Mul2_Hi, SMEMatrixTileH>, SMEPseudo2Instr<NAME # _M2ZZ_BtoH, 0>;
+
+  def : SME2_ZA_Tile_Vec_Multi_Single_Pat<NAME # _M2ZZ_BtoH, !cast<SDPatternOperator>(op # "_2x1"), timm32_0_1, nxv16i8>;
 
   // Single and multiple vectors
-  def _MZ2Z_BtoH : sme2_fp8_fp16_quarter_tile_outer_product<0b1, 0b0, mnemonic, ZPR8Mul2_Lo, ZZ_b_mul_r_Hi>;
+  def _MZ2Z_BtoH : sme2_fp8_fp16_quarter_tile_outer_product<0b1, 0b0, mnemonic, ZPR8Mul2_Lo, ZZ_b_mul_r_Hi>, SMEPseudo2Instr<NAME # _MZ2Z_BtoH, 1>;
+
+  def NAME # _MZ2Z_BtoH_PSEUDO : sme2_quarter_tile_outer_product_pseudo<ZPR8Mul2_Lo, ZZ_b_mul_r_Hi, SMEMatrixTileH>, SMEPseudo2Instr<NAME # _MZ2Z_BtoH, 0>;
+
+  def : SME2_ZA_Tile_Vec_Multi_Pat<NAME # _MZ2Z_BtoH, !cast<SDPatternOperator>(op # "_1x2"), timm32_0_1, nxv16i8>;
 
   // Multiple vectors
-  def _M2Z2Z_BtoH : sme2_fp8_fp16_quarter_tile_outer_product<0b1, 0b1, mnemonic, ZZ_b_mul_r_Lo, ZZ_b_mul_r_Hi>;
+  def _M2Z2Z_BtoH : sme2_fp8_fp16_quarter_tile_outer_product<0b1, 0b1, mnemonic, ZZ_b_mul_r_Lo, ZZ_b_mul_r_Hi>, SMEPseudo2Instr<NAME # _M2Z2Z_BtoH, 1>;
+
+  def NAME # _M2Z2Z_BtoH_PSEUDO : sme2_quarter_tile_outer_product_pseudo<ZZ_b_mul_r_Lo, ZZ_b_mul_r_Hi, SMEMatrixTileH>, SMEPseudo2Instr<NAME # _M2Z2Z_BtoH, 0>;
+
+  def : SME2_ZA_Tile_Vec_Multi_Multi_Pat<NAME # _M2Z2Z_BtoH, !cast<SDPatternOperator>(op # "_2x2"), timm32_0_1, nxv16i8>;
 }
 
 // FP8 SME FDOT instructions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
index a37128b0d745a..6617373f89c8b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
@@ -2123,7 +2123,7 @@ static bool isPtrKnownNeverNull(const Value *V, const DataLayout &DL,
   // Pointer cannot be null if it's a block address, GV or alloca.
   // NOTE: We don't support extern_weak, but if we did, we'd need to check for
   // it as the symbol could be null in such cases.
-  if (isa<BlockAddress>(V) || isa<GlobalValue>(V) || isa<AllocaInst>(V))
+  if (isa<BlockAddress, GlobalValue, AllocaInst>(V))
     return true;
 
   // Check nonnull arguments.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
index 87c1d2586cce5..4ff49c1e46dfe 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
@@ -1885,7 +1885,6 @@ class MFMASmallGemmSingleWaveOpt final : public IGLPStrategy {
         }
       }
 
-      assert(Cache->size());
       auto *DAG = SyncPipe[0].DAG;
       for (auto &Elt : *Cache) {
         if (DAG->IsReachable(Elt, const_cast<SUnit *>(SU)))
@@ -1922,8 +1921,6 @@ class MFMASmallGemmSingleWaveOpt final : public IGLPStrategy {
         return FitsInGroup;
       }
 
-      assert(Cache->size());
-
       // Does the VALU have a DS_WRITE successor that is the same as other
       // VALU already in the group. The V_PERMs will all share 1 DS_W succ
       return llvm::any_of(*Cache, [&SU](SUnit *Elt) {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 2846405a2538c..236c373e70250 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -819,11 +819,11 @@ bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
   return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
 }
 
-bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
-                                                 ISD::LoadExtType ExtTy,
-                                                 EVT NewVT) const {
+bool AMDGPUTargetLowering::shouldReduceLoadWidth(
+    SDNode *N, ISD::LoadExtType ExtTy, EVT NewVT,
+    std::optional<unsigned> ByteOffset) const {
   // TODO: This may be worth removing. Check regression tests for diffs.
-  if (!TargetLoweringBase::shouldReduceLoadWidth(N, ExtTy, NewVT))
+  if (!TargetLoweringBase::shouldReduceLoadWidth(N, ExtTy, NewVT, ByteOffset))
     return false;
 
   unsigned NewSize = NewVT.getStoreSizeInBits();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
index fa9d61ec37c24..a42214865ccfd 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -215,9 +215,8 @@ class AMDGPUTargetLowering : public TargetLowering {
   bool isFPImmLegal(const APFloat &Imm, EVT VT,
                     bool ForCodeSize) const override;
   bool ShouldShrinkFPConstant(EVT VT) const override;
-  bool shouldReduceLoadWidth(SDNode *Load,
-                             ISD::LoadExtType ExtType,
-                             EVT ExtVT) const override;
+  bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtType, EVT ExtVT,
+                             std::optional<unsigned> ByteOffset) const override;
 
   bool isLoadBitCastBeneficial(EVT, EVT, const SelectionDAG &DAG,
                                const MachineMemOperand &MMO) const final;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
index fa75c9284c75b..7ec2ee06b811a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
@@ -103,7 +103,7 @@ static bool canSafelyConvertTo16Bit(Value &V, bool IsFloat) {
 // Convert a value to 16-bit.
 static Value *convertTo16Bit(Value &V, InstCombiner::BuilderTy &Builder) {
   Type *VTy = V.getType();
-  if (isa<FPExtInst>(&V) || isa<SExtInst>(&V) || isa<ZExtInst>(&V))
+  if (isa<FPExtInst, SExtInst, ZExtInst>(&V))
     return cast<Instruction>(&V)->getOperand(0);
   if (VTy->isIntegerTy())
     return Builder.CreateIntCast(&V, Type::getInt16Ty(V.getContext()), false);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
index d41e704a4a11a..627ac6b0063e1 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
@@ -38,8 +38,7 @@ bool AMDGPUInstrInfo::isUniformMMO(const MachineMemOperand *MMO) {
   // Sometimes LDS instructions have constant pointers.
   // If Ptr is null, then that means this mem operand contains a
   // PseudoSourceValue like GOT.
-  if (!Ptr || isa<UndefValue>(Ptr) ||
-      isa<Constant>(Ptr) || isa<GlobalValue>(Ptr))
+  if (!Ptr || isa<UndefValue, Constant, GlobalValue>(Ptr))
     return true;
 
   if (MMO->getAddrSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 6ef7505ec6f62..2fa03e3964207 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -2946,8 +2946,7 @@ bool AMDGPUInstructionSelector::isInstrUniform(const MachineInstr &MI) const {
   // Sometimes LDS instructions have constant pointers.
   // If Ptr is null, then that means this mem operand contains a
   // PseudoSourceValue like GOT.
-  if (!Ptr || isa<UndefValue>(Ptr) || isa<Argument>(Ptr) ||
-      isa<Constant>(Ptr) || isa<GlobalValue>(Ptr))
+  if (!Ptr || isa<UndefValue, Argument, Constant, GlobalValue>(Ptr))
     return true;
 
   if (MMO->getAddrSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp b/llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
index 9ae043048b932..eab76bb79c969 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
@@ -127,9 +127,7 @@ class LiveRegOptimizer {
     return LK.first != TargetLoweringBase::TypeLegal;
   }
 
-  bool isOpLegal(Instruction *I) {
-    return isa<StoreInst>(I) || isa<IntrinsicInst>(I);
-  }
+  bool isOpLegal(Instruction *I) { return isa<StoreInst, IntrinsicInst>(I); }
 
   bool isCoercionProfitable(Instruction *II) {
     SmallPtrSet<Instruction *, 4> CVisited;
@@ -144,9 +142,8 @@ class LiveRegOptimizer {
     auto IsLookThru = [](Instruction *II) {
       if (const auto *Intr = dyn_cast<IntrinsicInst>(II))
         return Intr->getIntrinsicID() == Intrinsic::amdgcn_perm;
-      return isa<PHINode>(II) || isa<ShuffleVectorInst>(II) ||
-             isa<InsertElementInst>(II) || isa<ExtractElementInst>(II) ||
-             isa<CastInst>(II);
+      return isa<PHINode, ShuffleVectorInst, InsertElementInst,
+                 ExtractElementInst, CastInst>(II);
     };
 
     while (!UserList.empty()) {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp b/llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
index a62fc60461193..7163ad2aa7dca 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
@@ -2408,7 +2408,7 @@ bool AMDGPULowerBufferFatPointers::run(Module &M, const TargetMachine &TM) {
     for (Function &F : M.functions())
       for (Instruction &I : instructions(F))
         for (Value *Op : I.operands())
-          if (isa<ConstantExpr>(Op) || isa<ConstantAggregate>(Op))
+          if (isa<ConstantExpr, ConstantAggregate>(Op))
             Worklist.push_back(cast<Constant>(Op));
 
     // Recursively look for any referenced buffer pointer constants.
@@ -2421,7 +2421,7 @@ bool AMDGPULowerBufferFatPointers::run(Module &M, const TargetMachine &TM) {
       if (isBufferFatPtrOrVector(C->getType()))
         BufferFatPtrConsts.insert(C);
       for (Value *Op : C->operands())
-        if (isa<ConstantExpr>(Op) || isa<ConstantAggregate>(Op))
+        if (isa<ConstantExpr, ConstantAggregate>(Op))
           Worklist.push_back(cast<Constant>(Op));
     }
 
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
index dd3bec774ec67..ed9a4d9888dc4 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
@@ -205,8 +205,9 @@ static CostType calculateFunctionCosts(GetTTIFn GetTTI, Module &M,
             TTI.getInstructionCost(&I, TargetTransformInfo::TCK_CodeSize);
         assert(Cost != InstructionCost::getMax());
         // Assume expensive if we can't tell the cost of an instruction.
-        CostType CostVal =
-            Cost.getValue().value_or(TargetTransformInfo::TCC_Expensive);
+        CostType CostVal = Cost.isValid()
+                               ? Cost.getValue()
+                               : (CostType)TargetTransformInfo::TCC_Expensive;
         assert((FnCost + CostVal) >= FnCost && "Overflow!");
         FnCost += CostVal;
       }
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
index cc2ca77ffb792..204d3df546bbf 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
@@ -941,7 +941,7 @@ bool GCNTTIImpl::isSourceOfDivergence(const Value *V) const {
   // atomic operation refers to the same address in each thread, then each
   // thread after the first sees the value written by the previous thread as
   // original value.
-  if (isa<AtomicRMWInst>(V) || isa<AtomicCmpXchgInst>(V))
+  if (isa<AtomicRMWInst, AtomicCmpXchgInst>(V))
     return true;
 
   if (const IntrinsicInst *Intrinsic = dyn_cast<IntrinsicInst>(V)) {
@@ -1277,9 +1277,9 @@ static unsigned adjustInliningThresholdUsingCallee(const CallBase *CB,
   // The penalty cost is computed relative to the cost of instructions and does
   // not model any storage costs.
   adjustThreshold += std::max(0, SGPRsInUse - NrOfSGPRUntilSpill) *
-                     *ArgStackCost.getValue() * InlineConstants::getInstrCost();
+                     ArgStackCost.getValue() * InlineConstants::getInstrCost();
   adjustThreshold += std::max(0, VGPRsInUse - NrOfVGPRUntilSpill) *
-                     *ArgStackCost.getValue() * InlineConstants::getInstrCost();
+                     ArgStackCost.getValue() * InlineConstants::getInstrCost();
   return adjustThreshold;
 }
 
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
index 1e82ee36dc0eb..9cf712318bfa1 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
@@ -647,13 +647,15 @@ void AMDGPUMCCodeEmitter::getMachineOpValueT16Lo128(
 void AMDGPUMCCodeEmitter::getMachineOpValueCommon(
     const MCInst &MI, const MCOperand &MO, unsigned OpNo, APInt &Op,
     SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
+  bool isLikeImm = false;
   int64_t Val;
-  if (MO.isExpr() && MO.getExpr()->evaluateAsAbsolute(Val)) {
-    Op = Val;
-    return;
-  }
 
-  if (MO.isExpr() && MO.getExpr()->getKind() != MCExpr::Constant) {
+  if (MO.isImm()) {
+    Val = MO.getImm();
+    isLikeImm = true;
+  } else if (MO.isExpr() && MO.getExpr()->evaluateAsAbsolute(Val)) {
+    isLikeImm = true;
+  } else if (MO.isExpr()) {
     // FIXME: If this is expression is PCRel or not should not depend on what
     // the expression looks like. Given that this is just a general expression,
     // it should probably be FK_Data_4 and whatever is producing
@@ -683,8 +685,12 @@ void AMDGPUMCCodeEmitter::getMachineOpValueCommon(
       Op = *Enc;
       return;
     }
-  } else if (MO.isImm()) {
-    Op = MO.getImm();
+
+    llvm_unreachable("Operand not supported for SISrc");
+  }
+
+  if (isLikeImm) {
+    Op = Val;
     return;
   }
 
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 2e3cd5ca6692d..aed5571dfb27c 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -7370,8 +7370,7 @@ SDValue SITargetLowering::getSegmentAperture(unsigned AS, const SDLoc &DL,
 /// not necessary.
 static bool isKnownNonNull(SDValue Val, SelectionDAG &DAG,
                            const AMDGPUTargetMachine &TM, unsigned AddrSpace) {
-  if (isa<FrameIndexSDNode>(Val) || isa<GlobalAddressSDNode>(Val) ||
-      isa<BasicBlockSDNode>(Val))
+  if (isa<FrameIndexSDNode, GlobalAddressSDNode, BasicBlockSDNode>(Val))
     return true;
 
   if (auto *ConstVal = dyn_cast<ConstantSDNode>(Val))
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 23a7f508dcda2..51433020eeae7 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -544,14 +544,12 @@ def truncstorei8_glue : PatFrag<(ops node:$val, node:$ptr),
                            (truncstore_glue node:$val, node:$ptr)> {
   let IsStore = 1;
   let MemoryVT = i8;
-  let IsTruncStore = 1;
 }
 
 def truncstorei16_glue : PatFrag<(ops node:$val, node:$ptr),
                            (truncstore_glue node:$val, node:$ptr)> {
   let IsStore = 1;
   let MemoryVT = i16;
-  let IsTruncStore = 1;
 }
 
 let IsStore = 1, AddressSpaces = StoreAddress_local.AddrSpaces in {
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index c1ac9491b2363..7838fd91a94da 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -2510,7 +2510,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
       bool IsWWMRegSpill = TII->isWWMRegSpillOpcode(MI->getOpcode());
       if (IsWWMRegSpill) {
         TII->insertScratchExecCopy(*MF, *MBB, MI, DL, MFI->getSGPRForEXECCopy(),
-                                  RS->isRegUsed(AMDGPU::SCC));
+                                   RS->isRegUsed(AMDGPU::SCC));
       }
 
       buildSpillLoadStore(
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 2290ac2728c6d..03364d9025208 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -1221,7 +1221,10 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::ROTR, VT, Expand);
   }
   setOperationAction(ISD::CTTZ,  MVT::i32, Custom);
+  // TODO: These two should be set to LibCall, but this currently breaks
+  //   the Linux kernel build. See #101786.
   setOperationAction(ISD::CTPOP, MVT::i32, Expand);
+  setOperationAction(ISD::CTPOP, MVT::i64, Expand);
   if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) {
     setOperationAction(ISD::CTLZ, MVT::i32, Expand);
     setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, LibCall);
diff --git a/llvm/lib/Target/BPF/BPFISelLowering.h b/llvm/lib/Target/BPF/BPFISelLowering.h
index ad048ad05e6dd..8104895cb7f14 100644
--- a/llvm/lib/Target/BPF/BPFISelLowering.h
+++ b/llvm/lib/Target/BPF/BPFISelLowering.h
@@ -135,8 +135,9 @@ class BPFTargetLowering : public TargetLowering {
   //   ctx = ctx + reloc_offset
   //   ... (*(u8 *)(ctx + 1)) & 0x80 ...
   // which will be rejected by the verifier.
-  bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
-                             EVT NewVT) const override {
+  bool
+  shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT,
+                        std::optional<unsigned> ByteOffset) const override {
     return false;
   }
 
diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.td b/llvm/lib/Target/BPF/BPFInstrInfo.td
index 2dcf1eae086be..e717ac1a1d209 100644
--- a/llvm/lib/Target/BPF/BPFInstrInfo.td
+++ b/llvm/lib/Target/BPF/BPFInstrInfo.td
@@ -1342,11 +1342,11 @@ let Predicates = [BPFHasALU32] in {
 
   let Predicates = [BPFHasLoadAcqStoreRel] in {
     foreach P = [[relaxed_load<atomic_load_32>, LDW32],
-                 [relaxed_load<atomic_load_az_16>, LDH32],
-                 [relaxed_load<atomic_load_az_8>, LDB32],
+                 [relaxed_load<atomic_load_azext_16>, LDH32],
+                 [relaxed_load<atomic_load_azext_8>, LDB32],
                  [acquiring_load<atomic_load_32>, LDWACQ32],
-                 [acquiring_load<atomic_load_az_16>, LDHACQ32],
-                 [acquiring_load<atomic_load_az_8>, LDBACQ32],
+                 [acquiring_load<atomic_load_azext_16>, LDHACQ32],
+                 [acquiring_load<atomic_load_azext_8>, LDBACQ32],
                 ] in {
       def : Pat<(P[0] ADDRri:$addr), (P[1] ADDRri:$addr)>;
     }
diff --git a/llvm/lib/Target/DirectX/CMakeLists.txt b/llvm/lib/Target/DirectX/CMakeLists.txt
index c55028bc75dd6..65105d3a5f4c3 100644
--- a/llvm/lib/Target/DirectX/CMakeLists.txt
+++ b/llvm/lib/Target/DirectX/CMakeLists.txt
@@ -23,6 +23,7 @@ add_llvm_target(DirectXCodeGen
   DXILCBufferAccess.cpp
   DXILDataScalarization.cpp
   DXILFinalizeLinkage.cpp
+  DXILForwardHandleAccesses.cpp
   DXILFlattenArrays.cpp
   DXILIntrinsicExpansion.cpp
   DXILOpBuilder.cpp
diff --git a/llvm/lib/Target/DirectX/DXILForwardHandleAccesses.cpp b/llvm/lib/Target/DirectX/DXILForwardHandleAccesses.cpp
new file mode 100644
index 0000000000000..888ba6b00d9e8
--- /dev/null
+++ b/llvm/lib/Target/DirectX/DXILForwardHandleAccesses.cpp
@@ -0,0 +1,165 @@
+//===- DXILForwardHandleAccesses.cpp - Cleanup Handles --------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "DXILForwardHandleAccesses.h"
+#include "DXILShaderFlags.h"
+#include "DirectX.h"
+#include "llvm/Analysis/DXILResource.h"
+#include "llvm/Analysis/Loads.h"
+#include "llvm/IR/DiagnosticInfo.h"
+#include "llvm/IR/Dominators.h"
+#include "llvm/IR/IntrinsicInst.h"
+#include "llvm/IR/Intrinsics.h"
+#include "llvm/IR/IntrinsicsDirectX.h"
+#include "llvm/IR/Module.h"
+#include "llvm/InitializePasses.h"
+#include "llvm/Pass.h"
+#include "llvm/Transforms/Utils/Local.h"
+
+#define DEBUG_TYPE "dxil-forward-handle-accesses"
+
+using namespace llvm;
+
+static void diagnoseAmbiguousHandle(IntrinsicInst *NewII,
+                                    IntrinsicInst *PrevII) {
+  Function *F = NewII->getFunction();
+  LLVMContext &Context = F->getParent()->getContext();
+  Context.diagnose(DiagnosticInfoGeneric(
+      Twine("Handle at \"") + NewII->getName() + "\" overwrites handle at \"" +
+      PrevII->getName() + "\""));
+}
+
+static void diagnoseHandleNotFound(LoadInst *LI) {
+  Function *F = LI->getFunction();
+  LLVMContext &Context = F->getParent()->getContext();
+  Context.diagnose(DiagnosticInfoGeneric(
+      LI, Twine("Load of \"") + LI->getPointerOperand()->getName() +
+              "\" is not a global resource handle"));
+}
+
+static void diagnoseUndominatedLoad(LoadInst *LI, IntrinsicInst *Handle) {
+  Function *F = LI->getFunction();
+  LLVMContext &Context = F->getParent()->getContext();
+  Context.diagnose(DiagnosticInfoGeneric(
+      LI, Twine("Load at \"") + LI->getName() +
+              "\" is not dominated by handle creation at \"" +
+              Handle->getName() + "\""));
+}
+
+static void
+processHandle(IntrinsicInst *II,
+              DenseMap<GlobalVariable *, IntrinsicInst *> &HandleMap) {
+  for (User *U : II->users())
+    if (auto *SI = dyn_cast<StoreInst>(U))
+      if (auto *GV = dyn_cast<GlobalVariable>(SI->getPointerOperand())) {
+        auto Entry = HandleMap.try_emplace(GV, II);
+        if (Entry.second)
+          LLVM_DEBUG(dbgs() << "Added " << GV->getName() << " to handle map\n");
+        else
+          diagnoseAmbiguousHandle(II, Entry.first->second);
+      }
+}
+
+static bool forwardHandleAccesses(Function &F, DominatorTree &DT) {
+  bool Changed = false;
+
+  DenseMap<GlobalVariable *, IntrinsicInst *> HandleMap;
+  SmallVector<LoadInst *> LoadsToProcess;
+  for (BasicBlock &BB : F)
+    for (Instruction &Inst : BB)
+      if (auto *II = dyn_cast<IntrinsicInst>(&Inst)) {
+        switch (II->getIntrinsicID()) {
+        case Intrinsic::dx_resource_handlefrombinding:
+          processHandle(II, HandleMap);
+          break;
+        default:
+          continue;
+        }
+      } else if (auto *LI = dyn_cast<LoadInst>(&Inst))
+        if (isa<dxil::AnyResourceExtType>(LI->getType()))
+          LoadsToProcess.push_back(LI);
+
+  for (LoadInst *LI : LoadsToProcess) {
+    Value *V = LI->getPointerOperand();
+    auto *GV = dyn_cast<GlobalVariable>(LI->getPointerOperand());
+
+    // If we didn't find the global, we may need to walk through a level of
+    // indirection. This generally happens at -O0.
+    if (!GV)
+      if (auto *NestedLI = dyn_cast<LoadInst>(V)) {
+        BasicBlock::iterator BBI(NestedLI);
+        Value *Loaded = FindAvailableLoadedValue(
+            NestedLI, NestedLI->getParent(), BBI, 0, nullptr, nullptr);
+        GV = dyn_cast_or_null<GlobalVariable>(Loaded);
+      }
+
+    auto It = HandleMap.find(GV);
+    if (It == HandleMap.end()) {
+      diagnoseHandleNotFound(LI);
+      continue;
+    }
+    Changed = true;
+
+    if (!DT.dominates(It->second, LI)) {
+      diagnoseUndominatedLoad(LI, It->second);
+      continue;
+    }
+
+    LLVM_DEBUG(dbgs() << "Replacing uses of " << GV->getName() << " at "
+                      << LI->getName() << " with " << It->second->getName()
+                      << "\n");
+    LI->replaceAllUsesWith(It->second);
+    LI->eraseFromParent();
+  }
+
+  return Changed;
+}
+
+PreservedAnalyses DXILForwardHandleAccesses::run(Function &F,
+                                                 FunctionAnalysisManager &AM) {
+  PreservedAnalyses PA;
+
+  DominatorTree *DT = &AM.getResult<DominatorTreeAnalysis>(F);
+  bool Changed = forwardHandleAccesses(F, *DT);
+
+  if (!Changed)
+    return PreservedAnalyses::all();
+  return PA;
+}
+
+namespace {
+class DXILForwardHandleAccessesLegacy : public FunctionPass {
+public:
+  bool runOnFunction(Function &F) override {
+    DominatorTree *DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
+    return forwardHandleAccesses(F, *DT);
+  }
+  StringRef getPassName() const override {
+    return "DXIL Forward Handle Accesses";
+  }
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.addRequired<DominatorTreeWrapperPass>();
+  }
+
+  DXILForwardHandleAccessesLegacy() : FunctionPass(ID) {}
+
+  static char ID; // Pass identification.
+};
+char DXILForwardHandleAccessesLegacy::ID = 0;
+} // end anonymous namespace
+
+INITIALIZE_PASS_BEGIN(DXILForwardHandleAccessesLegacy, DEBUG_TYPE,
+                      "DXIL Forward Handle Accesses", false, false)
+INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
+INITIALIZE_PASS_END(DXILForwardHandleAccessesLegacy, DEBUG_TYPE,
+                    "DXIL Forward Handle Accesses", false, false)
+
+FunctionPass *llvm::createDXILForwardHandleAccessesLegacyPass() {
+  return new DXILForwardHandleAccessesLegacy();
+}
diff --git a/llvm/lib/Target/DirectX/DXILForwardHandleAccesses.h b/llvm/lib/Target/DirectX/DXILForwardHandleAccesses.h
new file mode 100644
index 0000000000000..76940287a50ad
--- /dev/null
+++ b/llvm/lib/Target/DirectX/DXILForwardHandleAccesses.h
@@ -0,0 +1,28 @@
+//===- DXILForwardHandleAccesses.h - Cleanup Handles ------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// \file Eliminate redundant stores and loads from handle globals.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_DIRECTX_DXILFORWARDHANDLEACCESS_H
+#define LLVM_LIB_TARGET_DIRECTX_DXILFORWARDHANDLEACCESS_H
+
+#include "llvm/IR/PassManager.h"
+
+namespace llvm {
+
+class DXILForwardHandleAccesses
+    : public PassInfoMixin<DXILForwardHandleAccesses> {
+public:
+  PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
+};
+
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_DIRECTX_DXILFORWARDHANDLEACCESS_H
diff --git a/llvm/lib/Target/DirectX/DirectX.h b/llvm/lib/Target/DirectX/DirectX.h
index c0eb221d12203..f64aaaf65d937 100644
--- a/llvm/lib/Target/DirectX/DirectX.h
+++ b/llvm/lib/Target/DirectX/DirectX.h
@@ -53,6 +53,12 @@ void initializeDXILFlattenArraysLegacyPass(PassRegistry &);
 /// Pass to flatten arrays into a one dimensional DXIL legal form
 ModulePass *createDXILFlattenArraysLegacyPass();
 
+/// Initializer for DXIL Forward Handle Accesses Pass
+void initializeDXILForwardHandleAccessesLegacyPass(PassRegistry &);
+
+/// Pass to eliminate redundant stores and loads from handle globals.
+FunctionPass *createDXILForwardHandleAccessesLegacyPass();
+
 /// Initializer DXIL legalizationPass
 void initializeDXILLegalizeLegacyPass(PassRegistry &);
 
diff --git a/llvm/lib/Target/DirectX/DirectXPassRegistry.def b/llvm/lib/Target/DirectX/DirectXPassRegistry.def
index 37093f16680a9..da239402d01eb 100644
--- a/llvm/lib/Target/DirectX/DirectXPassRegistry.def
+++ b/llvm/lib/Target/DirectX/DirectXPassRegistry.def
@@ -38,6 +38,7 @@ MODULE_PASS("print<dxil-root-signature>", dxil::RootSignatureAnalysisPrinter(dbg
 #ifndef FUNCTION_PASS
 #define FUNCTION_PASS(NAME, CREATE_PASS)
 #endif
+FUNCTION_PASS("dxil-forward-handle-accesses", DXILForwardHandleAccesses())
 FUNCTION_PASS("dxil-resource-access", DXILResourceAccess())
 FUNCTION_PASS("dxil-legalize", DXILLegalizePass())
 #undef FUNCTION_PASS
diff --git a/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp b/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
index 41f6f37a41f9d..d3d1f94f3ab1c 100644
--- a/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
+++ b/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
@@ -15,6 +15,7 @@
 #include "DXILCBufferAccess.h"
 #include "DXILDataScalarization.h"
 #include "DXILFlattenArrays.h"
+#include "DXILForwardHandleAccesses.h"
 #include "DXILIntrinsicExpansion.h"
 #include "DXILLegalizePass.h"
 #include "DXILOpLowering.h"
@@ -66,6 +67,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeDirectXTarget() {
   initializeRootSignatureAnalysisWrapperPass(*PR);
   initializeDXILFinalizeLinkageLegacyPass(*PR);
   initializeDXILPrettyPrinterLegacyPass(*PR);
+  initializeDXILForwardHandleAccessesLegacyPass(*PR);
   initializeDXILCBufferAccessLegacyPass(*PR);
 }
 
@@ -105,6 +107,7 @@ class DirectXPassConfig : public TargetPassConfig {
     ScalarizerPassOptions DxilScalarOptions;
     DxilScalarOptions.ScalarizeLoadStore = true;
     addPass(createScalarizerPass(DxilScalarOptions));
+    addPass(createDXILForwardHandleAccessesLegacyPass());
     addPass(createDXILLegalizeLegacyPass());
     addPass(createDXILTranslateMetadataLegacyPass());
     addPass(createDXILOpLoweringLegacyPass());
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 4c479ac41be12..fe12f99b91cd3 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -3821,19 +3821,21 @@ HexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
   return TargetLowering::findRepresentativeClass(TRI, VT);
 }
 
-bool HexagonTargetLowering::shouldReduceLoadWidth(SDNode *Load,
-      ISD::LoadExtType ExtTy, EVT NewVT) const {
+bool HexagonTargetLowering::shouldReduceLoadWidth(
+    SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT,
+    std::optional<unsigned> ByteOffset) const {
   // TODO: This may be worth removing. Check regression tests for diffs.
-  if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT))
+  if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT,
+                                                 ByteOffset))
     return false;
 
   auto *L = cast<LoadSDNode>(Load);
-  std::pair<SDValue,int> BO = getBaseAndOffset(L->getBasePtr());
+  std::pair<SDValue, int> BO = getBaseAndOffset(L->getBasePtr());
   // Small-data object, do not shrink.
   if (BO.first.getOpcode() == HexagonISD::CONST32_GP)
     return false;
   if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(BO.first)) {
-    auto &HTM = static_cast<const HexagonTargetMachine&>(getTargetMachine());
+    auto &HTM = static_cast<const HexagonTargetMachine &>(getTargetMachine());
     const auto *GO = dyn_cast_or_null<const GlobalObject>(GA->getGlobal());
     return !GO || !HTM.getObjFileLowering()->isGlobalInSmallSection(GO, HTM);
   }
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
index 4df88b3a8abd7..1321bee44a295 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
@@ -342,8 +342,8 @@ class HexagonTargetLowering : public TargetLowering {
   SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG)
                                    const override;
 
-  bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
-                             EVT NewVT) const override;
+  bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT,
+                             std::optional<unsigned> ByteOffset) const override;
 
   void AdjustInstrPostInstrSelection(MachineInstr &MI,
                                      SDNode *Node) const override;
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
index f70d68c212e4a..295ed666a1902 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -1868,7 +1868,7 @@ bool NVPTXDAGToDAGISel::tryStoreParam(SDNode *N) {
     case 1: {
       MVT::SimpleValueType MemTy = Mem->getMemoryVT().getSimpleVT().SimpleTy;
       SDValue Imm = Ops[0];
-      if (MemTy != MVT::f16 && MemTy != MVT::v2f16 &&
+      if (MemTy != MVT::f16 && MemTy != MVT::bf16 &&
           (isa<ConstantSDNode>(Imm) || isa<ConstantFPSDNode>(Imm))) {
         // Convert immediate to target constant
         if (MemTy == MVT::f32 || MemTy == MVT::f64) {
diff --git a/llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
index 142388893082a..6b9797c3e6aae 100644
--- a/llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
@@ -26,9 +26,9 @@ using namespace llvm;
 namespace llvm {
 StringRef getNVPTXRegClassName(TargetRegisterClass const *RC) {
   if (RC == &NVPTX::Float32RegsRegClass)
-    return ".f32";
+    return ".b32";
   if (RC == &NVPTX::Float64RegsRegClass)
-    return ".f64";
+    return ".b64";
   if (RC == &NVPTX::Int128RegsRegClass)
     return ".b128";
   if (RC == &NVPTX::Int64RegsRegClass)
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
index d6744014949ce..a088096c92a68 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
@@ -294,6 +294,10 @@ static inline bool isVFRegister(unsigned Reg) {
 static inline bool isVRRegister(unsigned Reg) {
   return Reg >= PPC::V0 && Reg <= PPC::V31;
 }
+
+static inline bool isDMRROWpRegister(unsigned Reg) {
+  return Reg >= PPC::DMRROWp0 && Reg <= PPC::DMRROWp31;
+}
 } // namespace PPC
 } // namespace llvm
 
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 1f75425752a78..0800ed5dfce2c 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -11146,6 +11146,116 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
     return DAG.getMergeValues(RetOps, dl);
   }
 
+  case Intrinsic::ppc_mma_dmxxextfdmr512: {
+    assert(Subtarget.isISAFuture() && "dmxxextfdmr512 requires ISA Future");
+    auto *Idx = dyn_cast<ConstantSDNode>(Op.getOperand(2));
+    assert(Idx && (Idx->getSExtValue() == 0 || Idx->getSExtValue() == 1) &&
+           "Specify P of 0 or 1 for lower or upper 512 bytes");
+    unsigned HiLo = Idx->getSExtValue();
+    unsigned Opcode;
+    unsigned Subx;
+    if (HiLo == 0) {
+      Opcode = PPC::DMXXEXTFDMR512;
+      Subx = PPC::sub_wacc_lo;
+    } else {
+      Opcode = PPC::DMXXEXTFDMR512_HI;
+      Subx = PPC::sub_wacc_hi;
+    }
+    SDValue Subreg(
+        DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, MVT::v512i1,
+                           Op.getOperand(1),
+                           DAG.getTargetConstant(Subx, dl, MVT::i32)),
+        0);
+    EVT ReturnTypes[] = {MVT::v256i1, MVT::v256i1};
+    return SDValue(DAG.getMachineNode(Opcode, dl, ReturnTypes, Subreg), 0);
+  }
+
+  case Intrinsic::ppc_mma_dmxxextfdmr256: {
+    assert(Subtarget.isISAFuture() && "dmxxextfdmr256 requires ISA Future");
+    auto *Idx = dyn_cast<ConstantSDNode>(Op.getOperand(2));
+    assert(Idx && (Idx->getSExtValue() >= 0 || Idx->getSExtValue() <= 3) &&
+           "Specify a dmr row pair 0-3");
+    unsigned IdxVal = Idx->getSExtValue();
+    unsigned Subx;
+    switch (IdxVal) {
+    case 0:
+      Subx = PPC::sub_dmrrowp0;
+      break;
+    case 1:
+      Subx = PPC::sub_dmrrowp1;
+      break;
+    case 2:
+      Subx = PPC::sub_wacc_hi_then_sub_dmrrowp0;
+      break;
+    case 3:
+      Subx = PPC::sub_wacc_hi_then_sub_dmrrowp1;
+      break;
+    }
+    SDValue Subreg(
+        DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, MVT::v256i1,
+                           Op.getOperand(1),
+                           DAG.getTargetConstant(Subx, dl, MVT::i32)),
+        0);
+    SDValue P = DAG.getTargetConstant(IdxVal, dl, MVT::i32);
+    return SDValue(
+        DAG.getMachineNode(PPC::DMXXEXTFDMR256, dl, MVT::v256i1, {Subreg, P}),
+        0);
+  }
+
+  case Intrinsic::ppc_mma_dmxxinstdmr512: {
+    assert(Subtarget.isISAFuture() && "dmxxinstdmr512 requires ISA Future");
+    auto *Idx = dyn_cast<ConstantSDNode>(Op.getOperand(4));
+    assert(Idx && (Idx->getSExtValue() == 0 || Idx->getSExtValue() == 1) &&
+           "Specify P of 0 or 1 for lower or upper 512 bytes");
+    unsigned HiLo = Idx->getSExtValue();
+    unsigned Opcode;
+    unsigned Subx;
+    if (HiLo == 0) {
+      Opcode = PPC::DMXXINSTDMR512;
+      Subx = PPC::sub_wacc_lo;
+    } else {
+      Opcode = PPC::DMXXINSTDMR512_HI;
+      Subx = PPC::sub_wacc_hi;
+    }
+    SDValue Ops[] = {Op.getOperand(2), Op.getOperand(3)};
+    SDValue Wacc = SDValue(DAG.getMachineNode(Opcode, dl, MVT::v512i1, Ops), 0);
+    SDValue SubReg = DAG.getTargetConstant(Subx, dl, MVT::i32);
+    return SDValue(DAG.getMachineNode(PPC::INSERT_SUBREG, dl, MVT::v1024i1,
+                                      Op.getOperand(1), Wacc, SubReg),
+                   0);
+  }
+
+  case Intrinsic::ppc_mma_dmxxinstdmr256: {
+    assert(Subtarget.isISAFuture() && "dmxxinstdmr256 requires ISA Future");
+    auto *Idx = dyn_cast<ConstantSDNode>(Op.getOperand(3));
+    assert(Idx && (Idx->getSExtValue() >= 0 || Idx->getSExtValue() <= 3) &&
+           "Specify a dmr row pair 0-3");
+    unsigned IdxVal = Idx->getSExtValue();
+    unsigned Subx;
+    switch (IdxVal) {
+    case 0:
+      Subx = PPC::sub_dmrrowp0;
+      break;
+    case 1:
+      Subx = PPC::sub_dmrrowp1;
+      break;
+    case 2:
+      Subx = PPC::sub_wacc_hi_then_sub_dmrrowp0;
+      break;
+    case 3:
+      Subx = PPC::sub_wacc_hi_then_sub_dmrrowp1;
+      break;
+    }
+    SDValue SubReg = DAG.getTargetConstant(Subx, dl, MVT::i32);
+    SDValue P = DAG.getTargetConstant(IdxVal, dl, MVT::i32);
+    SDValue Ops[] = {Op.getOperand(2), P};
+    SDValue DMRRowp = SDValue(
+        DAG.getMachineNode(PPC::DMXXINSTDMR256, dl, MVT::v256i1, Ops), 0);
+    return SDValue(DAG.getMachineNode(PPC::INSERT_SUBREG, dl, MVT::v1024i1,
+                                      Op.getOperand(1), DMRRowp, SubReg),
+                   0);
+  }
+
   case Intrinsic::ppc_mma_xxmfacc:
   case Intrinsic::ppc_mma_xxmtacc: {
     // Allow pre-isa-future subtargets to lower as normal.
diff --git a/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp b/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
index 13cee8dd783bb..0a04b7fb8d169 100644
--- a/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
@@ -196,6 +196,12 @@ bool llvm::LowerPPCMachineOperandToMCOperand(const MachineOperand &MO,
     assert(MO.getReg() > PPC::NoRegister &&
            MO.getReg() < PPC::NUM_TARGET_REGS &&
            "Invalid register for this target!");
+    // ISA instructions refer to the containing dmr reg.
+    if (PPC::isDMRROWpRegister(MO.getReg())) {
+      OutMO =
+          MCOperand::createReg(PPC::DMR0 + (MO.getReg() - PPC::DMRROWp0) / 4);
+      return true;
+    }
     // Ignore all implicit register operands.
     if (MO.isImplicit())
       return false;
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
index eb487bdaa88b9..bf2a95b2d1ddc 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -1096,7 +1096,7 @@ InstructionCost PPCTTIImpl::getVPMemoryOpCost(unsigned Opcode, Type *Src,
     float AlignmentProb = ((float)Alignment.value()) / DesiredAlignment.value();
     float MisalignmentProb = 1.0 - AlignmentProb;
     return (MisalignmentProb * P9PipelineFlushEstimate) +
-           (AlignmentProb * *Cost.getValue());
+           (AlignmentProb * Cost.getValue());
   }
 
   // Usually we should not get to this point, but the following is an attempt to
diff --git a/llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp b/llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
index 989e9d859d64f..aa8da1486faca 100644
--- a/llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
@@ -274,6 +274,7 @@ bool RISCVFoldMemOffset::runOnMachineFunction(MachineFunction &MF) {
         MemMI->getOperand(2).setImm(NewOffset);
 
       MRI.replaceRegWith(MI.getOperand(0).getReg(), MI.getOperand(1).getReg());
+      MRI.clearKillFlags(MI.getOperand(1).getReg());
       MI.eraseFromParent();
     }
   }
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 1fd1048bcebf8..f09e3cb20a665 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -1795,15 +1795,10 @@ bool RISCVFrameLowering::assignCalleeSavedSpillSlots(
     MFI.CreateFixedSpillStackObject(
         QCIInterruptPushAmount, -static_cast<int64_t>(QCIInterruptPushAmount));
   } else if (RVFI->isPushable(MF)) {
-    // Allocate a fixed object that covers all the registers that are pushed.
-    if (unsigned PushedRegs = RVFI->getRVPushRegs()) {
-      int64_t PushedRegsBytes =
-          static_cast<int64_t>(PushedRegs) * (STI.getXLen() / 8);
-      MFI.CreateFixedSpillStackObject(PushedRegsBytes, -PushedRegsBytes);
-    }
+    // Allocate a fixed object that covers the full push.
+    if (int64_t PushSize = RVFI->getRVPushStackSize())
+      MFI.CreateFixedSpillStackObject(PushSize, -PushSize);
   } else if (int LibCallRegs = getLibCallID(MF, CSI) + 1) {
-    // Allocate a fixed object that covers all of the stack allocated by the
-    // libcall.
     int64_t LibCallFrameSize =
         alignTo((STI.getXLen() / 8) * LibCallRegs, getStackAlign());
     MFI.CreateFixedSpillStackObject(LibCallFrameSize, -LibCallFrameSize);
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 4de93d5d5abde..ad77106d386c9 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2599,6 +2599,8 @@ static bool isWorthFoldingAdd(SDValue Add) {
     if (User->getOpcode() == ISD::ATOMIC_STORE &&
         cast<AtomicSDNode>(User)->getVal() == Add)
       return false;
+    if (isStrongerThanMonotonic(cast<MemSDNode>(User)->getSuccessOrdering()))
+      return false;
   }
 
   return true;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 11f2095ac9bce..c440df5a3e638 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -395,7 +395,14 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
     if (Subtarget.is64Bit())
       setOperationAction({ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF}, MVT::i32, Custom);
   } else {
-    setOperationAction({ISD::CTTZ, ISD::CTPOP}, XLenVT, Expand);
+    setOperationAction(ISD::CTTZ, XLenVT, Expand);
+    // TODO: These should be set to LibCall, but this currently breaks
+    //   the Linux kernel build. See #101786. Lacks i128 tests, too.
+    if (Subtarget.is64Bit())
+      setOperationAction(ISD::CTPOP, MVT::i128, Expand);
+    else
+      setOperationAction(ISD::CTPOP, MVT::i32, Expand);
+    setOperationAction(ISD::CTPOP, MVT::i64, Expand);
   }
 
   if (Subtarget.hasStdExtZbb() || Subtarget.hasVendorXTHeadBb() ||
@@ -2909,7 +2916,7 @@ InstructionCost RISCVTargetLowering::getVRGatherVVCost(MVT VT) const {
   bool Log2CostModel =
       Subtarget.getVRGatherCostModel() == llvm::RISCVSubtarget::NLog2N;
   if (Log2CostModel && LMULCost.isValid()) {
-    unsigned Log = Log2_64(*LMULCost.getValue());
+    unsigned Log = Log2_64(LMULCost.getValue());
     if (Log > 0)
       return LMULCost * Log;
   }
@@ -11543,6 +11550,8 @@ SDValue RISCVTargetLowering::lowerVECTOR_DEINTERLEAVE(SDValue Op,
       EVT NewVT = VT.getDoubleNumVectorElementsVT();
       SDValue ZeroIdx = DAG.getVectorIdxConstant(0, DL);
       Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NewVT, Src, ZeroIdx);
+      // Freeze the source so we can increase its use count.
+      Src = DAG.getFreeze(Src);
       SDValue Even = lowerVZIP(RISCVISD::RI_VUNZIP2A_VL, Src,
                                DAG.getUNDEF(NewVT), DL, DAG, Subtarget);
       SDValue Odd = lowerVZIP(RISCVISD::RI_VUNZIP2B_VL, Src,
@@ -11552,6 +11561,9 @@ SDValue RISCVTargetLowering::lowerVECTOR_DEINTERLEAVE(SDValue Op,
       return DAG.getMergeValues({Even, Odd}, DL);
     }
 
+    // Freeze the sources so we can increase their use count.
+    V1 = DAG.getFreeze(V1);
+    V2 = DAG.getFreeze(V2);
     SDValue Even =
         lowerVZIP(RISCVISD::RI_VUNZIP2A_VL, V1, V2, DL, DAG, Subtarget);
     SDValue Odd =
@@ -11793,8 +11805,9 @@ SDValue RISCVTargetLowering::lowerVECTOR_INTERLEAVE(SDValue Op,
   // TODO: Figure out the best lowering for the spread variants
   if (Subtarget.hasVendorXRivosVizip() && !Op.getOperand(0).isUndef() &&
       !Op.getOperand(1).isUndef()) {
-    SDValue V1 = Op->getOperand(0);
-    SDValue V2 = Op->getOperand(1);
+    // Freeze the sources so we can increase their use count.
+    SDValue V1 = DAG.getFreeze(Op->getOperand(0));
+    SDValue V2 = DAG.getFreeze(Op->getOperand(1));
     SDValue Lo = lowerVZIP(RISCVISD::RI_VZIP2A_VL, V1, V2, DL, DAG, Subtarget);
     SDValue Hi = lowerVZIP(RISCVISD::RI_VZIP2B_VL, V1, V2, DL, DAG, Subtarget);
     return DAG.getMergeValues({Lo, Hi}, DL);
@@ -16002,6 +16015,7 @@ struct NodeExtensionHelper {
     case RISCVISD::VWADD_W_VL:
     case RISCVISD::VWADDU_W_VL:
     case ISD::OR:
+    case RISCVISD::OR_VL:
       return RISCVISD::VWADD_VL;
     case ISD::SUB:
     case RISCVISD::SUB_VL:
@@ -16025,6 +16039,7 @@ struct NodeExtensionHelper {
     case RISCVISD::VWADD_W_VL:
     case RISCVISD::VWADDU_W_VL:
     case ISD::OR:
+    case RISCVISD::OR_VL:
       return RISCVISD::VWADDU_VL;
     case ISD::SUB:
     case RISCVISD::SUB_VL:
@@ -16082,6 +16097,7 @@ struct NodeExtensionHelper {
     case ISD::ADD:
     case RISCVISD::ADD_VL:
     case ISD::OR:
+    case RISCVISD::OR_VL:
       return SupportsExt == ExtKind::SExt ? RISCVISD::VWADD_W_VL
                                           : RISCVISD::VWADDU_W_VL;
     case ISD::SUB:
@@ -16272,6 +16288,8 @@ struct NodeExtensionHelper {
     case RISCVISD::VFWADD_W_VL:
     case RISCVISD::VFWSUB_W_VL:
       return true;
+    case RISCVISD::OR_VL:
+      return Root->getFlags().hasDisjoint();
     case ISD::SHL:
       return Root->getValueType(0).isScalableVector() &&
              Subtarget.hasStdExtZvbb();
@@ -16357,6 +16375,7 @@ struct NodeExtensionHelper {
     case ISD::OR:
     case RISCVISD::ADD_VL:
     case RISCVISD::MUL_VL:
+    case RISCVISD::OR_VL:
     case RISCVISD::VWADD_W_VL:
     case RISCVISD::VWADDU_W_VL:
     case RISCVISD::FADD_VL:
@@ -16573,6 +16592,7 @@ NodeExtensionHelper::getSupportedFoldings(const SDNode *Root) {
   case ISD::OR:
   case RISCVISD::ADD_VL:
   case RISCVISD::SUB_VL:
+  case RISCVISD::OR_VL:
   case RISCVISD::FADD_VL:
   case RISCVISD::FSUB_VL:
     // add|sub|fadd|fsub-> vwadd(u)|vwsub(u)|vfwadd|vfwsub
@@ -16623,7 +16643,7 @@ NodeExtensionHelper::getSupportedFoldings(const SDNode *Root) {
 
 /// Combine a binary or FMA operation to its equivalent VW or VW_W form.
 /// The supported combines are:
-/// add | add_vl | or disjoint -> vwadd(u) | vwadd(u)_w
+/// add | add_vl | or disjoint | or_vl disjoint -> vwadd(u) | vwadd(u)_w
 /// sub | sub_vl -> vwsub(u) | vwsub(u)_w
 /// mul | mul_vl -> vwmul(u) | vwmul_su
 /// shl | shl_vl -> vwsll
@@ -19459,6 +19479,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
   case RISCVISD::VWSUB_W_VL:
   case RISCVISD::VWSUBU_W_VL:
     return performVWADDSUBW_VLCombine(N, DCI, Subtarget);
+  case RISCVISD::OR_VL:
   case RISCVISD::SUB_VL:
   case RISCVISD::MUL_VL:
     return combineOp_VLToVWOp_VL(N, DCI, Subtarget);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
index 0575e17c72287..b348e774d50b8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
@@ -165,16 +165,20 @@ class seq_cst_store<PatFrag base>
 // any ordering. This is necessary because AtomicExpandPass has added fences to
 // atomic load/stores and changed them to unordered ones.
 let Predicates = [HasAtomicLdSt] in {
-  def : LdPat<relaxed_load<atomic_load_8>,  LB>;
-  def : LdPat<relaxed_load<atomic_load_16>, LH>;
-  def : LdPat<relaxed_load<atomic_load_32>, LW>;
+  def : LdPat<relaxed_load<atomic_load_asext_8>,  LB>;
+  def : LdPat<relaxed_load<atomic_load_asext_16>, LH>;
 
   def : StPat<relaxed_store<atomic_store_8>,  SB, GPR, XLenVT>;
   def : StPat<relaxed_store<atomic_store_16>, SH, GPR, XLenVT>;
   def : StPat<relaxed_store<atomic_store_32>, SW, GPR, XLenVT>;
 }
 
+let Predicates = [HasAtomicLdSt, IsRV32] in {
+  def : LdPat<relaxed_load<atomic_load_32>, LW>;
+}
+
 let Predicates = [HasAtomicLdSt, IsRV64] in {
+  def : LdPat<relaxed_load<atomic_load_asext_32>, LW>;
   def : LdPat<relaxed_load<atomic_load_64>, LD, i64>;
   def : StPat<relaxed_store<atomic_store_64>, SD, GPR, i64>;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index b2c5261ae6c2d..aea125c5348dd 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -912,6 +912,29 @@ defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, sext_oneuse, "PseudoVWADD">;
 defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, zext_oneuse, "PseudoVWADDU">;
 defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, anyext_oneuse, "PseudoVWADDU">;
 
+// DAGCombiner::hoistLogicOpWithSameOpcodeHands may hoist disjoint ors
+// to (ext (or disjoint (a, b)))
+multiclass VPatWidenOrDisjoint_VV_VX<SDNode extop, string instruction_name> {
+  foreach vtiToWti = AllWidenableIntVectors in {
+    defvar vti = vtiToWti.Vti;
+    defvar wti = vtiToWti.Wti;
+    let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
+                                 GetVTypePredicates<wti>.Predicates) in {
+      def : Pat<(wti.Vector (extop (vti.Vector (or_is_add vti.RegClass:$rs2, vti.RegClass:$rs1)))),
+                (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
+                   (wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
+                   vti.RegClass:$rs1, vti.AVL, vti.Log2SEW, TA_MA)>;
+      def : Pat<(wti.Vector (extop (vti.Vector (or_is_add vti.RegClass:$rs2, (SplatPat (XLenVT GPR:$rs1)))))),
+                (!cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX)
+                   (wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
+                   GPR:$rs1, vti.AVL, vti.Log2SEW, TA_MA)>;
+    }
+  }
+}
+defm : VPatWidenOrDisjoint_VV_VX<sext, "PseudoVWADD">;
+defm : VPatWidenOrDisjoint_VV_VX<zext, "PseudoVWADDU">;
+defm : VPatWidenOrDisjoint_VV_VX<anyext, "PseudoVWADDU">;
+
 defm : VPatWidenBinarySDNode_VV_VX_WV_WX<sub, sext_oneuse, "PseudoVWSUB">;
 defm : VPatWidenBinarySDNode_VV_VX_WV_WX<sub, zext_oneuse, "PseudoVWSUBU">;
 defm : VPatWidenBinarySDNode_VV_VX_WV_WX<sub, anyext_oneuse, "PseudoVWSUBU">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index f80cbc9e2fb5e..fe36def4fda2f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -497,6 +497,16 @@ let HasOneUse = 1 in {
                                          node:$E),
                                     (riscv_add_vl node:$A, node:$B, node:$C,
                                                   node:$D, node:$E)>;
+  def riscv_or_vl_is_add_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D,
+                                               node:$E),
+                                          (riscv_or_vl node:$A, node:$B, node:$C,
+                                                       node:$D, node:$E), [{
+    if (N->getFlags().hasDisjoint())
+      return true;
+    KnownBits Known0 = CurDAG->computeKnownBits(N->getOperand(0), 0);
+    KnownBits Known1 = CurDAG->computeKnownBits(N->getOperand(1), 0);
+    return KnownBits::haveNoCommonBitsSet(Known0, Known1);
+  }]>;
   def riscv_sub_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D,
                                          node:$E),
                                     (riscv_sub_vl node:$A, node:$B, node:$C,
@@ -2016,6 +2026,41 @@ foreach vtiToWti = AllWidenableIntVectors in {
   }
 }
 
+// DAGCombiner::hoistLogicOpWithSameOpcodeHands may hoist disjoint ors
+// to (ext (or disjoint (a, b)))
+multiclass VPatWidenOrDisjointVL_VV_VX<SDNode extop, string instruction_name> {
+  foreach vtiToWti = AllWidenableIntVectors in {
+    defvar vti = vtiToWti.Vti;
+    defvar wti = vtiToWti.Wti;
+    let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
+                                 GetVTypePredicates<wti>.Predicates) in {
+      def : Pat<(wti.Vector
+                  (extop
+                    (vti.Vector
+                      (riscv_or_vl_is_add_oneuse
+                        vti.RegClass:$rs2, vti.RegClass:$rs1,
+                        undef, srcvalue, srcvalue)),
+                    VMV0:$vm, VLOpFrag)),
+                (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_MASK")
+                 (wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
+                 vti.RegClass:$rs1, VMV0:$vm, GPR:$vl, vti.Log2SEW, TA_MA)>;
+       def : Pat<(wti.Vector
+                   (extop
+                     (vti.Vector
+                       (riscv_or_vl_is_add_oneuse
+                         vti.RegClass:$rs2, (SplatPat (XLenVT GPR:$rs1)),
+                         undef, srcvalue, srcvalue)),
+                     VMV0:$vm, VLOpFrag)),
+                (!cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX#"_MASK")
+                 (wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
+                 GPR:$rs1, VMV0:$vm, GPR:$vl, vti.Log2SEW, TA_MA)>;
+    }
+  }
+}
+
+defm : VPatWidenOrDisjointVL_VV_VX<riscv_sext_vl, "PseudoVWADD">;
+defm : VPatWidenOrDisjointVL_VV_VX<riscv_zext_vl, "PseudoVWADDU">;
+
 // 11.3. Vector Integer Extension
 defm : VPatExtendVL_V<riscv_zext_vl, "PseudoVZEXT", "VF2",
                       AllFractionableVF2IntVectors>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
index 085353ab88306..837aa7f1005af 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
@@ -70,25 +70,22 @@ class PatLAQ<SDPatternOperator OpNode, RVInst Inst, ValueType vt = XLenVT>
 //  while atomic_store has data, addr
 class PatSRL<SDPatternOperator OpNode, RVInst Inst, ValueType vt = XLenVT>
     : Pat<(OpNode (vt GPR:$rs2), (vt GPRMemZeroOffset:$rs1)),
-          (Inst GPRMemZeroOffset:$rs1, GPR:$rs2)>; 
-                              
+          (Inst GPRMemZeroOffset:$rs1, GPR:$rs2)>;
+
 
 let Predicates = [HasStdExtZalasr] in {
   // the sequentially consistent loads use
   //  .aq instead of .aqrl to match the psABI/A.7
-  def : PatLAQ<acquiring_load<atomic_load_8>, LB_AQ>;
-  def : PatLAQ<seq_cst_load<atomic_load_8>, LB_AQ>; 
+  def : PatLAQ<acquiring_load<atomic_load_asext_8>, LB_AQ>;
+  def : PatLAQ<seq_cst_load<atomic_load_asext_8>, LB_AQ>;
 
-  def : PatLAQ<acquiring_load<atomic_load_16>, LH_AQ>;
-  def : PatLAQ<seq_cst_load<atomic_load_16>, LH_AQ>;
-
-  def : PatLAQ<acquiring_load<atomic_load_32>, LW_AQ>;
-  def : PatLAQ<seq_cst_load<atomic_load_32>, LW_AQ>;
+  def : PatLAQ<acquiring_load<atomic_load_asext_16>, LH_AQ>;
+  def : PatLAQ<seq_cst_load<atomic_load_asext_16>, LH_AQ>;
 
   // the sequentially consistent stores use
   //  .rl instead of .aqrl to match the psABI/A.7
   def : PatSRL<releasing_store<atomic_store_8>, SB_RL>;
-  def : PatSRL<seq_cst_store<atomic_store_8>, SB_RL>; 
+  def : PatSRL<seq_cst_store<atomic_store_8>, SB_RL>;
 
   def : PatSRL<releasing_store<atomic_store_16>, SH_RL>;
   def : PatSRL<seq_cst_store<atomic_store_16>, SH_RL>;
@@ -97,7 +94,16 @@ let Predicates = [HasStdExtZalasr] in {
   def : PatSRL<seq_cst_store<atomic_store_32>, SW_RL>;
 } // Predicates = [HasStdExtZalasr]
 
+let Predicates = [HasStdExtZalasr, IsRV32] in {
+  def : PatLAQ<acquiring_load<atomic_load_32>, LW_AQ>;
+  def : PatLAQ<seq_cst_load<atomic_load_32>, LW_AQ>;
+
+} // Predicates = [HasStdExtZalasr, IsRV64]
+
 let Predicates = [HasStdExtZalasr, IsRV64] in {
+  def : PatLAQ<acquiring_load<atomic_load_asext_32>, LW_AQ>;
+  def : PatLAQ<seq_cst_load<atomic_load_asext_32>, LW_AQ>;
+
   def : PatLAQ<acquiring_load<atomic_load_64>, LD_AQ>;
   def : PatLAQ<seq_cst_load<atomic_load_64>, LD_AQ>;
 
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 4b288a9cfcb49..1ad94228bcbaa 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -625,3 +625,55 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
                                           FeatureStdExtZbkb,
                                           FeatureStdExtZcb,
                                           FeatureStdExtZcmp]>;
+
+def ANDES_N45 : RISCVProcessorModel<"andes-n45",
+                                    NoSchedModel,
+                                    [Feature32Bit,
+                                     FeatureStdExtI,
+                                     FeatureStdExtZicsr,
+                                     FeatureStdExtZifencei,
+                                     FeatureStdExtM,
+                                     FeatureStdExtA,
+                                     FeatureStdExtF,
+                                     FeatureStdExtD,
+                                     FeatureStdExtC,
+                                     FeatureStdExtB]>;
+
+def ANDES_NX45 : RISCVProcessorModel<"andes-nx45",
+                                     NoSchedModel,
+                                     [Feature64Bit,
+                                      FeatureStdExtI,
+                                      FeatureStdExtZicsr,
+                                      FeatureStdExtZifencei,
+                                      FeatureStdExtM,
+                                      FeatureStdExtA,
+                                      FeatureStdExtF,
+                                      FeatureStdExtD,
+                                      FeatureStdExtC,
+                                      FeatureStdExtB]>;
+
+def ANDES_A45 : RISCVProcessorModel<"andes-a45",
+                                    NoSchedModel,
+                                    [Feature32Bit,
+                                     FeatureStdExtI,
+                                     FeatureStdExtZicsr,
+                                     FeatureStdExtZifencei,
+                                     FeatureStdExtM,
+                                     FeatureStdExtA,
+                                     FeatureStdExtF,
+                                     FeatureStdExtD,
+                                     FeatureStdExtC,
+                                     FeatureStdExtB]>;
+
+def ANDES_AX45 : RISCVProcessorModel<"andes-ax45",
+                                     NoSchedModel,
+                                     [Feature64Bit,
+                                      FeatureStdExtI,
+                                      FeatureStdExtZicsr,
+                                      FeatureStdExtZifencei,
+                                      FeatureStdExtM,
+                                      FeatureStdExtA,
+                                      FeatureStdExtF,
+                                      FeatureStdExtD,
+                                      FeatureStdExtC,
+                                      FeatureStdExtB]>;
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 2cea601fb1a02..73ebd87cd0a94 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -483,7 +483,7 @@ costShuffleViaVRegSplitting(const RISCVTTIImpl &TTI, MVT LegalVT,
   auto *SingleOpTy = FixedVectorType::get(Tp->getElementType(),
                                           LegalVT.getVectorNumElements());
 
-  unsigned E = *NumOfDests.getValue();
+  unsigned E = NumOfDests.getValue();
   unsigned NormalizedVF =
       LegalVT.getVectorNumElements() * std::max(NumOfSrcs, E);
   unsigned NumOfSrcRegs = NormalizedVF / LegalVT.getVectorNumElements();
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 16364ab30f280..e090fb67b3231 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -1161,9 +1161,15 @@ static bool generateGroupInst(const SPIRV::IncomingCall *Call,
 
   MachineRegisterInfo *MRI = MIRBuilder.getMRI();
   if (Call->isSpirvOp()) {
-    if (GroupBuiltin->NoGroupOperation)
+    if (GroupBuiltin->NoGroupOperation) {
+      SmallVector<uint32_t, 1> ImmArgs;
+      if (GroupBuiltin->Opcode ==
+              SPIRV::OpSubgroupMatrixMultiplyAccumulateINTEL &&
+          Call->Arguments.size() > 4)
+        ImmArgs.push_back(getConstFromIntrinsic(Call->Arguments[4], MRI));
       return buildOpFromWrapper(MIRBuilder, GroupBuiltin->Opcode, Call,
-                                GR->getSPIRVTypeID(Call->ReturnType));
+                                GR->getSPIRVTypeID(Call->ReturnType), ImmArgs);
+    }
 
     // Group Operation is a literal
     Register GroupOpReg = Call->Arguments[1];
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
index b504e7b04d336..a3f27dde76b65 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
@@ -763,6 +763,7 @@ class GroupBuiltin<string name, Op operation> {
   bit NoGroupOperation = !or(IsElect, IsAllOrAny, IsAllEqual,
                              IsBallot, IsInverseBallot,
                              IsBallotBitExtract, IsBallotFindBit,
+                             !eq(operation, OpSubgroupMatrixMultiplyAccumulateINTEL),
                              !eq(operation, OpGroupNonUniformShuffle),
                              !eq(operation, OpGroupNonUniformShuffleXor),
                              !eq(operation, OpGroupNonUniformShuffleUp),
@@ -847,6 +848,9 @@ defm : DemangledGroupBuiltinWrapper<"__spirv_GroupNonUniformBallotFindLSB", 2, 2
 defm : DemangledGroupBuiltin<"group_ballot_find_msb", OnlySub, OpGroupNonUniformBallotFindMSB>;
 defm : DemangledGroupBuiltinWrapper<"__spirv_GroupNonUniformBallotFindMSB", 2, 2, OpGroupNonUniformBallotFindMSB>;
 
+// SPV_INTEL_subgroup_matrix_multiply_accumulate
+defm : DemangledGroupBuiltinWrapper<"__spirv_SubgroupMatrixMultiplyAccumulateINTEL", 4, 5, OpSubgroupMatrixMultiplyAccumulateINTEL>;
+
 // cl_khr_subgroup_shuffle
 defm : DemangledGroupBuiltin<"group_shuffle", OnlySub, OpGroupNonUniformShuffle>;
 defm : DemangledGroupBuiltinWrapper<"__spirv_GroupNonUniformShuffle", 3, 3, OpGroupNonUniformShuffle>;
diff --git a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
index 86702bbe58f09..56cbd9414c9ee 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
@@ -93,6 +93,9 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
          SPIRV::Extension::Extension::SPV_INTEL_long_composites},
         {"SPV_INTEL_fp_max_error",
          SPIRV::Extension::Extension::SPV_INTEL_fp_max_error},
+        {"SPV_INTEL_subgroup_matrix_multiply_accumulate",
+         SPIRV::Extension::Extension::
+             SPV_INTEL_subgroup_matrix_multiply_accumulate},
         {"SPV_INTEL_ternary_bitwise_function",
          SPIRV::Extension::Extension::SPV_INTEL_ternary_bitwise_function}};
 
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index 53064ebb51271..6d8c84945d7d4 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -736,6 +736,10 @@ def OpGroupFMax: OpGroup<"FMax", 269>;
 def OpGroupUMax: OpGroup<"UMax", 270>;
 def OpGroupSMax: OpGroup<"SMax", 271>;
 
+def OpSubgroupMatrixMultiplyAccumulateINTEL: Op<6237, (outs ID:$res),
+        (ins TYPE:$ty, ID:$KDim, ID:$A, ID:$B, ID:$C, variable_ops),
+                  "$res = OpSubgroupMatrixMultiplyAccumulateINTEL $ty $KDim $A $B $C">;
+
 // TODO: 3.42.22. Device-Side Enqueue Instructions
 def OpEnqueueKernel: Op<292, (outs ID:$res), (ins TYPE:$type, ID:$queue, ID:$flags, ID:$NDR, ID:$nevents, ID:$wevents,
                                               ID:$revent, ID:$invoke, ID:$param, ID:$psize, ID:$palign, variable_ops),
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index b1e5e4328cd32..a6482d9df2ccb 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -1799,6 +1799,20 @@ void addInstrRequirements(const MachineInstr &MI,
     Reqs.addCapability(SPIRV::Capability::LongCompositesINTEL);
     break;
   }
+  case SPIRV::OpSubgroupMatrixMultiplyAccumulateINTEL: {
+    if (!ST.canUseExtension(
+            SPIRV::Extension::SPV_INTEL_subgroup_matrix_multiply_accumulate))
+      report_fatal_error(
+          "OpSubgroupMatrixMultiplyAccumulateINTEL instruction requires the "
+          "following SPIR-V "
+          "extension: SPV_INTEL_subgroup_matrix_multiply_accumulate",
+          false);
+    Reqs.addExtension(
+        SPIRV::Extension::SPV_INTEL_subgroup_matrix_multiply_accumulate);
+    Reqs.addCapability(
+        SPIRV::Capability::SubgroupMatrixMultiplyAccumulateINTEL);
+    break;
+  }
   case SPIRV::OpBitwiseFunctionINTEL: {
     if (!ST.canUseExtension(
             SPIRV::Extension::SPV_INTEL_ternary_bitwise_function))
@@ -2015,6 +2029,8 @@ static void patchPhis(const Module &M, SPIRVGlobalRegistry *GR,
                   {MachineOperand::CreateReg(ResTypeReg, false)});
       }
     }
+
+    MF->getProperties().set(MachineFunctionProperties::Property::NoPHIs);
   }
 }
 
diff --git a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
index 0db8a37f8683c..afd3a5206926c 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
+++ b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
@@ -314,6 +314,7 @@ defm SPV_INTEL_long_composites : ExtensionOperand<117>;
 defm SPV_INTEL_memory_access_aliasing : ExtensionOperand<118>;
 defm SPV_INTEL_fp_max_error : ExtensionOperand<119>;
 defm SPV_INTEL_ternary_bitwise_function : ExtensionOperand<120>;
+defm SPV_INTEL_subgroup_matrix_multiply_accumulate : ExtensionOperand<121>;
 
 //===----------------------------------------------------------------------===//
 // Multiclass used to define Capabilities enum values and at the same time
@@ -515,6 +516,7 @@ defm BindlessImagesINTEL : CapabilityOperand<6528, 0, 0, [SPV_INTEL_bindless_ima
 defm MemoryAccessAliasingINTEL : CapabilityOperand<5910, 0, 0, [SPV_INTEL_memory_access_aliasing], []>;
 defm FPMaxErrorINTEL : CapabilityOperand<6169, 0, 0, [SPV_INTEL_fp_max_error], []>;
 defm TernaryBitwiseFunctionINTEL : CapabilityOperand<6241, 0, 0, [SPV_INTEL_ternary_bitwise_function], []>;
+defm SubgroupMatrixMultiplyAccumulateINTEL : CapabilityOperand<6236, 0, 0, [SPV_INTEL_subgroup_matrix_multiply_accumulate], []>;
 
 //===----------------------------------------------------------------------===//
 // Multiclass used to define SourceLanguage enum values and at the same time
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index c1c9c1a831f51..db8b2bdb62077 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -553,7 +553,8 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, LibCall);
     setOperationAction(ISD::BITCAST, MVT::i16, Custom);
     setOperationAction(ISD::IS_FPCLASS, MVT::f16, Custom);
-    setOperationAction(ISD::FCOPYSIGN, MVT::f16, Legal);
+    for (auto Op : {ISD::FNEG, ISD::FABS, ISD::FCOPYSIGN})
+      setOperationAction(Op, MVT::f16, Legal);
   }
 
   for (unsigned I = MVT::FIRST_FP_VALUETYPE;
@@ -791,6 +792,7 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
                        ISD::SINT_TO_FP,
                        ISD::UINT_TO_FP,
                        ISD::STRICT_FP_EXTEND,
+                       ISD::FCOPYSIGN,
                        ISD::BSWAP,
                        ISD::SETCC,
                        ISD::SRL,
@@ -8547,6 +8549,22 @@ SDValue SystemZTargetLowering::combineINT_TO_FP(
   return SDValue();
 }
 
+SDValue SystemZTargetLowering::combineFCOPYSIGN(
+    SDNode *N, DAGCombinerInfo &DCI) const {
+  SelectionDAG &DAG = DCI.DAG;
+  EVT VT = N->getValueType(0);
+  SDValue ValOp = N->getOperand(0);
+  SDValue SignOp = N->getOperand(1);
+
+  // Remove the rounding which is not needed.
+  if (SignOp.getOpcode() == ISD::FP_ROUND) {
+    SDValue WideOp = SignOp.getOperand(0);
+    return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, ValOp, WideOp);
+  }
+
+  return SDValue();
+}
+
 SDValue SystemZTargetLowering::combineBSWAP(
     SDNode *N, DAGCombinerInfo &DCI) const {
   SelectionDAG &DAG = DCI.DAG;
@@ -9136,6 +9154,7 @@ SDValue SystemZTargetLowering::PerformDAGCombine(SDNode *N,
   case ISD::FP_EXTEND:          return combineFP_EXTEND(N, DCI);
   case ISD::SINT_TO_FP:
   case ISD::UINT_TO_FP:         return combineINT_TO_FP(N, DCI);
+  case ISD::FCOPYSIGN:          return combineFCOPYSIGN(N, DCI);
   case ISD::BSWAP:              return combineBSWAP(N, DCI);
   case ISD::SETCC:              return combineSETCC(N, DCI);
   case SystemZISD::BR_CCMASK:   return combineBR_CCMASK(N, DCI);
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.h b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
index f438332c2dc4f..f3536a840fda8 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.h
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
@@ -777,6 +777,7 @@ class SystemZTargetLowering : public TargetLowering {
   SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const;
   SDValue combineFP_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
   SDValue combineINT_TO_FP(SDNode *N, DAGCombinerInfo &DCI) const;
+  SDValue combineFCOPYSIGN(SDNode *N, DAGCombinerInfo &DCI) const;
   SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const;
   SDValue combineSETCC(SDNode *N, DAGCombinerInfo &DCI) const;
   SDValue combineBR_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFP.td b/llvm/lib/Target/SystemZ/SystemZInstrFP.td
index 7775f456bbdc1..33f73bc658b25 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFP.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFP.td
@@ -109,10 +109,10 @@ let isCodeGenOnly = 1 in {
 
 // The sign of an FP128 is in the high register.
 let Predicates = [FeatureNoVectorEnhancements1] in
-  def : Pat<(fcopysign FP32:$src1, (f32 (fpround (f128 FP128:$src2)))),
+  def : Pat<(fcopysign FP32:$src1, (f128 FP128:$src2)),
             (CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
 let Predicates = [FeatureVectorEnhancements1] in
-  def : Pat<(fcopysign FP32:$src1, (f32 (fpround (f128 VR128:$src2)))),
+  def : Pat<(fcopysign FP32:$src1, (f128 VR128:$src2)),
             (CPSDRsd FP32:$src1, (EXTRACT_SUBREG VR128:$src2, subreg_h64))>;
 
 // fcopysign with an FP64 result.
@@ -124,10 +124,10 @@ def CPSDRdd : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP64, FP64, FP64>;
 
 // The sign of an FP128 is in the high register.
 let Predicates = [FeatureNoVectorEnhancements1] in
-  def : Pat<(fcopysign FP64:$src1, (f64 (fpround (f128 FP128:$src2)))),
+  def : Pat<(fcopysign FP64:$src1, (f128 FP128:$src2)),
             (CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
 let Predicates = [FeatureVectorEnhancements1] in
-  def : Pat<(fcopysign FP64:$src1, (f64 (fpround (f128 VR128:$src2)))),
+  def : Pat<(fcopysign FP64:$src1, (f128 VR128:$src2)),
             (CPSDRdd FP64:$src1, (EXTRACT_SUBREG VR128:$src2, subreg_h64))>;
 
 // fcopysign with an FP128 result.  Use "upper" as the high half and leave
@@ -378,8 +378,10 @@ let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
 }
 // Generic form, which does not set CC.
 def LPDFR : UnaryRRE<"lpdfr", 0xB370, fabs, FP64,  FP64>;
-let isCodeGenOnly = 1 in
+let isCodeGenOnly = 1 in {
+  def LPDFR_16 : UnaryRRE<"lpdfr", 0xB370, fabs, FP16,  FP16>;
   def LPDFR_32 : UnaryRRE<"lpdfr", 0xB370, fabs, FP32,  FP32>;
+}
 
 // Negative absolute value (Load Negative).
 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
@@ -389,8 +391,10 @@ let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
 }
 // Generic form, which does not set CC.
 def LNDFR : UnaryRRE<"lndfr", 0xB371, fnabs, FP64,  FP64>;
-let isCodeGenOnly = 1 in
+let isCodeGenOnly = 1 in {
+  def LNDFR_16 : UnaryRRE<"lndfr", 0xB371, fnabs, FP16,  FP16>;
   def LNDFR_32 : UnaryRRE<"lndfr", 0xB371, fnabs, FP32,  FP32>;
+}
 
 // Square root.
 let Uses = [FPC], mayRaiseFPException = 1 in {
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
index 53270ac096bb0..ee142ccd20e20 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
@@ -380,7 +380,7 @@ void SystemZTTIImpl::getUnrollingPreferences(
   // The z13 processor will run out of store tags if too many stores
   // are fed into it too quickly. Therefore make sure there are not
   // too many stores in the resulting unrolled loop.
-  unsigned const NumStoresVal = *NumStores.getValue();
+  unsigned const NumStoresVal = NumStores.getValue();
   unsigned const Max = (NumStoresVal ? (12 / NumStoresVal) : UINT_MAX);
 
   if (HasCall) {
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 993118c52564e..0fc50dc1a87b6 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -3258,9 +3258,9 @@ bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
   return false;
 }
 
-bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
-                                              ISD::LoadExtType ExtTy,
-                                              EVT NewVT) const {
+bool X86TargetLowering::shouldReduceLoadWidth(
+    SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT,
+    std::optional<unsigned> ByteOffset) const {
   assert(cast<LoadSDNode>(Load)->isSimple() && "illegal to narrow");
 
   // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
@@ -43786,7 +43786,7 @@ bool X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
       return TLO.CombineTo(Op, Insert);
     }
     case X86ISD::VPERMI: {
-      // Simplify PERMPD/PERMQ to extract_subvector.
+      // Simplify 256-bit PERMPD/PERMQ to extract_subvector.
       // TODO: This should be done in shuffle combining.
       if (VT == MVT::v4f64 || VT == MVT::v4i64) {
         SmallVector<int, 4> Mask;
@@ -43799,6 +43799,16 @@ bool X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
           return TLO.CombineTo(Op, Insert);
         }
       }
+      // Simplify 512-bit PERMPD/PERMQ to 256-bit variant on lower half.
+      if (VT == MVT::v8f64 || VT == MVT::v8i64) {
+        SDLoc DL(Op);
+        SDValue Ext0 = extractSubVector(Op.getOperand(0), 0, TLO.DAG, DL, 256);
+        SDValue ExtOp = TLO.DAG.getNode(Opc, DL, Ext0.getValueType(), Ext0,
+                                        Op.getOperand(1));
+        SDValue UndefVec = TLO.DAG.getUNDEF(VT);
+        SDValue Insert = insertSubVector(UndefVec, ExtOp, 0, TLO.DAG, DL, 256);
+        return TLO.CombineTo(Op, Insert);
+      }
       break;
     }
     case X86ISD::VPERMV: {
@@ -46258,7 +46268,8 @@ static SDValue combineExtractWithShuffle(SDNode *N, SelectionDAG &DAG,
 
   // If we're extracting a single element from a broadcast load and there are
   // no other users, just create a single load.
-  if (SrcBC.getOpcode() == X86ISD::VBROADCAST_LOAD && SrcBC.hasOneUse()) {
+  if (peekThroughOneUseBitcasts(Src).getOpcode() == X86ISD::VBROADCAST_LOAD &&
+      SrcBC.hasOneUse()) {
     auto *MemIntr = cast<MemIntrinsicSDNode>(SrcBC);
     unsigned SrcBCWidth = SrcBC.getScalarValueSizeInBits();
     if (MemIntr->getMemoryVT().getSizeInBits() == SrcBCWidth &&
@@ -52794,8 +52805,8 @@ static SDValue combineConstantPoolLoads(SDNode *N, const SDLoc &dl,
               getTargetConstantBitsFromNode(SDValue(User, 0), NumBits,
                                             UserUndefs, UserBits)) {
             if (MatchingBits(Undefs, UserUndefs, Bits, UserBits)) {
-              SDValue Extract = extractSubVector(
-                  SDValue(User, 0), 0, DAG, SDLoc(N), RegVT.getSizeInBits());
+              SDValue Extract = extractSubVector(SDValue(User, 0), 0, DAG, dl,
+                                                 RegVT.getSizeInBits());
               Extract = DAG.getBitcast(RegVT, Extract);
               return DCI.CombineTo(N, Extract, SDValue(User, 1));
             }
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index 4a2b35e9efe7c..7926292fc5bcf 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -1501,8 +1501,9 @@ namespace llvm {
 
     /// Return true if we believe it is correct and profitable to reduce the
     /// load node to a smaller type.
-    bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
-                               EVT NewVT) const override;
+    bool
+    shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT,
+                          std::optional<unsigned> ByteOffset) const override;
 
     /// Return true if the specified scalar FP type is computed in an SSE
     /// register, not on the X87 floating point stack.
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index 2375a8f992aa5..74bb25781b534 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -1748,7 +1748,7 @@ InstructionCost X86TTIImpl::getShuffleCost(
             getTypeLegalizationCost(
                 FixedVectorType::get(BaseTp->getElementType(), Mask.size()))
                 .first;
-        unsigned E = *NumOfDests.getValue();
+        unsigned E = NumOfDests.getValue();
         unsigned NormalizedVF =
             LegalVT.getVectorNumElements() * std::max(NumOfSrcs, E);
         unsigned NumOfSrcRegs = NormalizedVF / LegalVT.getVectorNumElements();
@@ -4931,7 +4931,7 @@ InstructionCost X86TTIImpl::getScalarizationOverhead(
           (LegalVectorBitWidth % LaneBitWidth) == 0) &&
          "Illegal vector");
 
-  const int NumLegalVectors = *LT.first.getValue();
+  const int NumLegalVectors = LT.first.getValue();
   assert(NumLegalVectors >= 0 && "Negative cost!");
 
   // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much
@@ -6164,7 +6164,7 @@ InstructionCost X86TTIImpl::getGSVectorCost(unsigned Opcode,
   std::pair<InstructionCost, MVT> IdxsLT = getTypeLegalizationCost(IndexVTy);
   std::pair<InstructionCost, MVT> SrcLT = getTypeLegalizationCost(SrcVTy);
   InstructionCost::CostType SplitFactor =
-      *std::max(IdxsLT.first, SrcLT.first).getValue();
+      std::max(IdxsLT.first, SrcLT.first).getValue();
   if (SplitFactor > 1) {
     // Handle splitting of vector of pointers
     auto *SplitSrcTy =
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index 1e7144ce6d22b..ff0174210f87f 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -643,7 +643,6 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension,
     for (const char *Ext : RISCVGImplications) {
       auto Version = findDefaultVersion(Ext);
       assert(Version && "Default extension version not found?");
-      // Postpone AddExtension until end of this function
       ISAInfo->Exts[std::string(Ext)] = {Version->Major, Version->Minor};
     }
     break;
diff --git a/llvm/lib/TargetParser/Triple.cpp b/llvm/lib/TargetParser/Triple.cpp
index e9e6f130f757c..74363f8d71b65 100644
--- a/llvm/lib/TargetParser/Triple.cpp
+++ b/llvm/lib/TargetParser/Triple.cpp
@@ -1150,7 +1150,8 @@ std::string Triple::normalize(StringRef Str, CanonicalForm Form) {
   OSType OS = UnknownOS;
   if (Components.size() > 2) {
     OS = parseOS(Components[2]);
-    IsCygwin = Components[2].starts_with("cygwin");
+    IsCygwin = Components[2].starts_with("cygwin") ||
+               Components[2].starts_with("msys");
     IsMinGW32 = Components[2].starts_with("mingw");
   }
   EnvironmentType Environment = UnknownEnvironment;
@@ -1195,7 +1196,7 @@ std::string Triple::normalize(StringRef Str, CanonicalForm Form) {
         break;
       case 2:
         OS = parseOS(Comp);
-        IsCygwin = Comp.starts_with("cygwin");
+        IsCygwin = Comp.starts_with("cygwin") || Comp.starts_with("msys");
         IsMinGW32 = Comp.starts_with("mingw");
         Valid = OS != UnknownOS || IsCygwin || IsMinGW32;
         break;
diff --git a/llvm/lib/Transforms/Coroutines/CoroElide.cpp b/llvm/lib/Transforms/Coroutines/CoroElide.cpp
index 598ef7779d771..c5131aa0787ed 100644
--- a/llvm/lib/Transforms/Coroutines/CoroElide.cpp
+++ b/llvm/lib/Transforms/Coroutines/CoroElide.cpp
@@ -81,22 +81,6 @@ class CoroIdElider {
 // provided constant.
 static void replaceWithConstant(Constant *Value,
                                 SmallVectorImpl<CoroSubFnInst *> &Users) {
-  if (Users.empty())
-    return;
-
-  // See if we need to bitcast the constant to match the type of the intrinsic
-  // being replaced. Note: All coro.subfn.addr intrinsics return the same type,
-  // so we only need to examine the type of the first one in the list.
-  Type *IntrTy = Users.front()->getType();
-  Type *ValueTy = Value->getType();
-  if (ValueTy != IntrTy) {
-    // May need to tweak the function type to match the type expected at the
-    // use site.
-    assert(ValueTy->isPointerTy() && IntrTy->isPointerTy());
-    Value = ConstantExpr::getBitCast(Value, IntrTy);
-  }
-
-  // Now the value type matches the type of the intrinsic. Replace them all!
   for (CoroSubFnInst *I : Users)
     replaceAndRecursivelySimplify(I, Value);
 }
@@ -104,7 +88,7 @@ static void replaceWithConstant(Constant *Value,
 // See if any operand of the call instruction references the coroutine frame.
 static bool operandReferences(CallInst *CI, AllocaInst *Frame, AAResults &AA) {
   for (Value *Op : CI->operand_values())
-    if (!AA.isNoAlias(Op, Frame))
+    if (Op->getType()->isPointerTy() && !AA.isNoAlias(Op, Frame))
       return true;
   return false;
 }
diff --git a/llvm/lib/Transforms/IPO/FunctionAttrs.cpp b/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
index bbfed2ac2c090..74e8a849803d2 100644
--- a/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
+++ b/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
@@ -661,8 +661,13 @@ ArgumentAccessInfo getArgumentAccessInfo(const Instruction *I,
     auto TypeSize = DL.getTypeStoreSize(Ty);
     if (!TypeSize.isScalable() && Offset) {
       int64_t Size = TypeSize.getFixedValue();
-      return ConstantRange(APInt(64, *Offset, true),
-                           APInt(64, *Offset + Size, true));
+      APInt Low(64, *Offset, true);
+      bool Overflow;
+      APInt High = Low.sadd_ov(APInt(64, Size, true), Overflow);
+      // Bail if the range overflows signed 64-bit int.
+      if (Overflow)
+        return std::nullopt;
+      return ConstantRange(Low, High);
     }
     return std::nullopt;
   };
diff --git a/llvm/lib/Transforms/IPO/FunctionSpecialization.cpp b/llvm/lib/Transforms/IPO/FunctionSpecialization.cpp
index c13305ce5056d..1034ce9582152 100644
--- a/llvm/lib/Transforms/IPO/FunctionSpecialization.cpp
+++ b/llvm/lib/Transforms/IPO/FunctionSpecialization.cpp
@@ -662,7 +662,7 @@ FunctionSpecializer::~FunctionSpecializer() {
 /// non-negative, which is true for both TCK_CodeSize and TCK_Latency, and
 /// always Valid.
 static unsigned getCostValue(const Cost &C) {
-  int64_t Value = *C.getValue();
+  int64_t Value = C.getValue();
 
   assert(Value >= 0 && "CodeSize and Latency cannot be negative");
   // It is safe to down cast since we know the arguments cannot be negative and
@@ -713,7 +713,7 @@ bool FunctionSpecializer::run() {
     if (!SpecializeLiteralConstant && !Inserted && !Metrics.isRecursive)
       continue;
 
-    int64_t Sz = *Metrics.NumInsts.getValue();
+    int64_t Sz = Metrics.NumInsts.getValue();
     assert(Sz > 0 && "CodeSize should be positive");
     // It is safe to down cast from int64_t, NumInsts is always positive.
     unsigned FuncSize = static_cast<unsigned>(Sz);
diff --git a/llvm/lib/Transforms/IPO/GlobalOpt.cpp b/llvm/lib/Transforms/IPO/GlobalOpt.cpp
index 83cc1e5f04f3d..3771cccbde17d 100644
--- a/llvm/lib/Transforms/IPO/GlobalOpt.cpp
+++ b/llvm/lib/Transforms/IPO/GlobalOpt.cpp
@@ -719,10 +719,14 @@ static bool allUsesOfLoadedValueWillTrapIfNull(const GlobalVariable *GV) {
     const Value *P = Worklist.pop_back_val();
     for (const auto *U : P->users()) {
       if (auto *LI = dyn_cast<LoadInst>(U)) {
+        if (!LI->isSimple())
+          return false;
         SmallPtrSet<const PHINode *, 8> PHIs;
         if (!AllUsesOfValueWillTrapIfNull(LI, PHIs))
           return false;
       } else if (auto *SI = dyn_cast<StoreInst>(U)) {
+        if (!SI->isSimple())
+          return false;
         // Ignore stores to the global.
         if (SI->getPointerOperand() != P)
           return false;
@@ -965,11 +969,12 @@ OptimizeGlobalAddressOfAllocation(GlobalVariable *GV, CallInst *CI,
     if (StoreInst *SI = dyn_cast<StoreInst>(U)) {
       // The global is initialized when the store to it occurs. If the stored
       // value is null value, the global bool is set to false, otherwise true.
-      new StoreInst(ConstantInt::getBool(
-                        GV->getContext(),
-                        !isa<ConstantPointerNull>(SI->getValueOperand())),
-                    InitBool, false, Align(1), SI->getOrdering(),
-                    SI->getSyncScopeID(), SI->getIterator());
+      auto *NewSI = new StoreInst(
+          ConstantInt::getBool(GV->getContext(), !isa<ConstantPointerNull>(
+                                                     SI->getValueOperand())),
+          InitBool, false, Align(1), SI->getOrdering(), SI->getSyncScopeID(),
+          SI->getIterator());
+      NewSI->setDebugLoc(SI->getDebugLoc());
       SI->eraseFromParent();
       continue;
     }
@@ -988,6 +993,11 @@ OptimizeGlobalAddressOfAllocation(GlobalVariable *GV, CallInst *CI,
                                InitBool->getName() + ".val", false, Align(1),
                                LI->getOrdering(), LI->getSyncScopeID(),
                                LI->getIterator());
+      // FIXME: Should we use the DebugLoc of the load used by the predicate, or
+      // the predicate? The load seems most appropriate, but there's an argument
+      // that the new load does not represent the old load, but is simply a
+      // component of recomputing the predicate.
+      cast<LoadInst>(LV)->setDebugLoc(LI->getDebugLoc());
       InitBoolUsed = true;
       switch (ICI->getPredicate()) {
       default: llvm_unreachable("Unknown ICmp Predicate!");
@@ -1000,6 +1010,7 @@ OptimizeGlobalAddressOfAllocation(GlobalVariable *GV, CallInst *CI,
       case ICmpInst::ICMP_ULE:
       case ICmpInst::ICMP_EQ:
         LV = BinaryOperator::CreateNot(LV, "notinit", ICI->getIterator());
+        cast<BinaryOperator>(LV)->setDebugLoc(ICI->getDebugLoc());
         break;
       case ICmpInst::ICMP_NE:
       case ICmpInst::ICMP_UGT:
@@ -1276,6 +1287,7 @@ static bool TryToShrinkGlobalToBoolean(GlobalVariable *GV, Constant *OtherVal) {
               new LoadInst(NewGV->getValueType(), NewGV, LI->getName() + ".b",
                            false, Align(1), LI->getOrdering(),
                            LI->getSyncScopeID(), LI->getIterator());
+          cast<LoadInst>(StoreVal)->setDebugLoc(LI->getDebugLoc());
         } else {
           assert((isa<CastInst>(StoredVal) || isa<SelectInst>(StoredVal)) &&
                  "This is not a form that we understand!");
diff --git a/llvm/lib/Transforms/IPO/PartialInlining.cpp b/llvm/lib/Transforms/IPO/PartialInlining.cpp
index e2df95ed23c10..b79fe83b23ec6 100644
--- a/llvm/lib/Transforms/IPO/PartialInlining.cpp
+++ b/llvm/lib/Transforms/IPO/PartialInlining.cpp
@@ -1320,7 +1320,7 @@ bool PartialInlinerImpl::tryPartialInline(FunctionCloner &Cloner) {
     RelativeToEntryFreq = BranchProbability(0, 1);
 
   BlockFrequency WeightedRcost =
-      BlockFrequency(*NonWeightedRcost.getValue()) * RelativeToEntryFreq;
+      BlockFrequency(NonWeightedRcost.getValue()) * RelativeToEntryFreq;
 
   // The call sequence(s) to the outlined function(s) are larger than the sum of
   // the original outlined region size(s), it does not increase the chances of
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
index f1b225c0f238a..979a9cbedf2ef 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
@@ -1480,7 +1480,9 @@ Value *InstCombinerImpl::foldLogicOfFCmps(FCmpInst *LHS, FCmpInst *RHS,
     }
   }
 
-  if (IsAnd && stripSignOnlyFPOps(LHS0) == stripSignOnlyFPOps(RHS0)) {
+  // This transform is not valid for a logical select.
+  if (!IsLogicalSelect && IsAnd &&
+      stripSignOnlyFPOps(LHS0) == stripSignOnlyFPOps(RHS0)) {
     // and (fcmp ord x, 0), (fcmp u* x, inf) -> fcmp o* x, inf
     // and (fcmp ord x, 0), (fcmp u* fabs(x), inf) -> fcmp o* x, inf
     if (Value *Left = matchIsFiniteTest(Builder, LHS, RHS))
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
index 38519d81fce8d..844e18dd7d8c5 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
@@ -1924,6 +1924,29 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
       }
     }
 
+    // smax(smin(X, MinC), MaxC) -> smin(smax(X, MaxC), MinC) if MinC s>= MaxC
+    // umax(umin(X, MinC), MaxC) -> umin(umax(X, MaxC), MinC) if MinC u>= MaxC
+    const APInt *MinC, *MaxC;
+    auto CreateCanonicalClampForm = [&](bool IsSigned) {
+      auto MaxIID = IsSigned ? Intrinsic::smax : Intrinsic::umax;
+      auto MinIID = IsSigned ? Intrinsic::smin : Intrinsic::umin;
+      Value *NewMax = Builder.CreateBinaryIntrinsic(
+          MaxIID, X, ConstantInt::get(X->getType(), *MaxC));
+      return replaceInstUsesWith(
+          *II, Builder.CreateBinaryIntrinsic(
+                   MinIID, NewMax, ConstantInt::get(X->getType(), *MinC)));
+    };
+    if (IID == Intrinsic::smax &&
+        match(I0, m_OneUse(m_Intrinsic<Intrinsic::smin>(m_Value(X),
+                                                        m_APInt(MinC)))) &&
+        match(I1, m_APInt(MaxC)) && MinC->sgt(*MaxC))
+      return CreateCanonicalClampForm(true);
+    if (IID == Intrinsic::umax &&
+        match(I0, m_OneUse(m_Intrinsic<Intrinsic::umin>(m_Value(X),
+                                                        m_APInt(MinC)))) &&
+        match(I1, m_APInt(MaxC)) && MinC->ugt(*MaxC))
+      return CreateCanonicalClampForm(false);
+
     // umin(i1 X, i1 Y) -> and i1 X, Y
     // smax(i1 X, i1 Y) -> and i1 X, Y
     if ((IID == Intrinsic::umin || IID == Intrinsic::smax) &&
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
index 55afe1258159a..b7b0bb7361359 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
@@ -5034,8 +5034,8 @@ static Instruction *foldICmpOrXX(ICmpInst &I, const SimplifyQuery &Q,
 
   if (ICmpInst::isEquality(Pred) && Op0->hasOneUse()) {
     // icmp (X | Y) eq/ne Y --> (X & ~Y) eq/ne 0 if Y is freely invertible
-    if (Value *NotOp1 =
-            IC.getFreelyInverted(Op1, !Op1->hasNUsesOrMore(3), &IC.Builder))
+    if (Value *NotOp1 = IC.getFreelyInverted(
+            Op1, !isa<Constant>(Op1) && !Op1->hasNUsesOrMore(3), &IC.Builder))
       return new ICmpInst(Pred, IC.Builder.CreateAnd(A, NotOp1),
                           Constant::getNullValue(Op1->getType()));
     // icmp (X | Y) eq/ne Y --> (~X | Y) eq/ne -1 if X  is freely invertible.
diff --git a/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp b/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
index 84bf4c62c7aad..b1d96db542ad2 100644
--- a/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
+++ b/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
@@ -1495,13 +1495,11 @@ static inline bool shouldRecordVTableAddr(GlobalVariable *GV) {
 // FIXME: Introduce an internal alias like what's done for functions to reduce
 // the number of relocation entries.
 static inline Constant *getVTableAddrForProfData(GlobalVariable *GV) {
-  auto *Int8PtrTy = PointerType::getUnqual(GV->getContext());
-
   // Store a nullptr in __profvt_ if a real address shouldn't be used.
   if (!shouldRecordVTableAddr(GV))
-    return ConstantPointerNull::get(Int8PtrTy);
+    return ConstantPointerNull::get(PointerType::getUnqual(GV->getContext()));
 
-  return ConstantExpr::getBitCast(GV, Int8PtrTy);
+  return GV;
 }
 
 void InstrLowerer::getOrCreateVTableProfData(GlobalVariable *GV) {
diff --git a/llvm/lib/Transforms/Instrumentation/MemProfiler.cpp b/llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
index 46b524d054493..67eba057c1791 100644
--- a/llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
+++ b/llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
@@ -818,6 +818,7 @@ static bool isAllocationWithHotColdVariant(const Function *Callee,
 
 struct AllocMatchInfo {
   uint64_t TotalSize = 0;
+  size_t NumFramesMatched = 0;
   AllocationType AllocType = AllocationType::None;
   bool Matched = false;
 };
@@ -1152,7 +1153,8 @@ readMemprof(Module &M, Function &F, IndexedInstrProfReader *MemProfReader,
             if (ClPrintMemProfMatchInfo) {
               assert(FullStackId != 0);
               FullStackIdToAllocMatchInfo[FullStackId] = {
-                  AllocInfo->Info.getTotalSize(), AllocType, /*Matched=*/true};
+                  AllocInfo->Info.getTotalSize(), InlinedCallStack.size(),
+                  AllocType, /*Matched=*/true};
             }
           }
         }
@@ -1285,7 +1287,7 @@ PreservedAnalyses MemProfUsePass::run(Module &M, ModuleAnalysisManager &AM) {
       errs() << "MemProf " << getAllocTypeAttributeString(Info.AllocType)
              << " context with id " << Id << " has total profiled size "
              << Info.TotalSize << (Info.Matched ? " is" : " not")
-             << " matched\n";
+             << " matched with " << Info.NumFramesMatched << " frames\n";
 
     for (const auto &CallStack : MatchedCallSites) {
       errs() << "MemProf callsite match for inline call stack";
diff --git a/llvm/lib/Transforms/Instrumentation/SanitizerBinaryMetadata.cpp b/llvm/lib/Transforms/Instrumentation/SanitizerBinaryMetadata.cpp
index b6787fd8cb21e..4801ac75f8572 100644
--- a/llvm/lib/Transforms/Instrumentation/SanitizerBinaryMetadata.cpp
+++ b/llvm/lib/Transforms/Instrumentation/SanitizerBinaryMetadata.cpp
@@ -393,7 +393,7 @@ bool maybeSharedMutable(const Value *Addr) {
     return true;
 
   const AllocaInst *AI = findAllocaForValue(Addr);
-  if (AI && !PointerMayBeCaptured(Addr, /*ReturnCaptures=*/true))
+  if (AI && !PointerMayBeCaptured(AI, /*ReturnCaptures=*/true))
     return false; // Object is on stack but does not escape.
 
   Addr = Addr->stripInBoundsOffsets();
diff --git a/llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp b/llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp
index 7f846d25b8133..ec9f78edfeb1c 100644
--- a/llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp
@@ -449,7 +449,8 @@ void ThreadSanitizer::chooseInstructionsToInstrument(
     }
 
     const AllocaInst *AI = findAllocaForValue(Addr);
-    if (AI && !PointerMayBeCaptured(Addr, /*ReturnCaptures=*/true)) {
+    // Instead of Addr, we should check whether its base pointer is captured.
+    if (AI && !PointerMayBeCaptured(AI, /*ReturnCaptures=*/true)) {
       // The variable is addressable but not captured, so it cannot be
       // referenced from a different thread and participate in a data race
       // (see llvm/Analysis/CaptureTracking.h for details).
diff --git a/llvm/lib/Transforms/Scalar/ConstantHoisting.cpp b/llvm/lib/Transforms/Scalar/ConstantHoisting.cpp
index 40c4c15b7120b..dd4d4efb7fecb 100644
--- a/llvm/lib/Transforms/Scalar/ConstantHoisting.cpp
+++ b/llvm/lib/Transforms/Scalar/ConstantHoisting.cpp
@@ -386,7 +386,7 @@ void ConstantHoistingPass::collectConstantCandidates(
       ConstIntCandVec.push_back(ConstantCandidate(ConstInt));
       Itr->second = ConstIntCandVec.size() - 1;
     }
-    ConstIntCandVec[Itr->second].addUser(Inst, Idx, *Cost.getValue());
+    ConstIntCandVec[Itr->second].addUser(Inst, Idx, Cost.getValue());
     LLVM_DEBUG(if (isa<ConstantInt>(Inst->getOperand(Idx))) dbgs()
                    << "Collect constant " << *ConstInt << " from " << *Inst
                    << " with cost " << Cost << '\n';
@@ -446,7 +446,7 @@ void ConstantHoistingPass::collectConstantCandidates(
         ConstExpr));
     Itr->second = ExprCandVec.size() - 1;
   }
-  ExprCandVec[Itr->second].addUser(Inst, Idx, *Cost.getValue());
+  ExprCandVec[Itr->second].addUser(Inst, Idx, Cost.getValue());
 }
 
 /// Check the operand for instruction Inst at index Idx.
diff --git a/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp b/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
index 141af344f0e16..0521df8b818cf 100644
--- a/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
+++ b/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
@@ -2334,6 +2334,10 @@ DSEState::getInitializesArgMemLoc(const Instruction *I) {
   // Collect aliasing arguments and their initializes ranges.
   SmallMapVector<Value *, SmallVector<ArgumentInitInfo, 2>, 2> Arguments;
   for (unsigned Idx = 0, Count = CB->arg_size(); Idx < Count; ++Idx) {
+    Value *CurArg = CB->getArgOperand(Idx);
+    if (!CurArg->getType()->isPointerTy())
+      continue;
+
     ConstantRangeList Inits;
     Attribute InitializesAttr = CB->getParamAttr(Idx, Attribute::Initializes);
     // initializes on byval arguments refers to the callee copy, not the
@@ -2341,7 +2345,6 @@ DSEState::getInitializesArgMemLoc(const Instruction *I) {
     if (InitializesAttr.isValid() && !CB->isByValArgument(Idx))
       Inits = InitializesAttr.getValueAsConstantRangeList();
 
-    Value *CurArg = CB->getArgOperand(Idx);
     // Check whether "CurArg" could alias with global variables. We require
     // either it's function local and isn't captured before or the "CB" only
     // accesses arg or inaccessible mem.
diff --git a/llvm/lib/Transforms/Scalar/LoopDataPrefetch.cpp b/llvm/lib/Transforms/Scalar/LoopDataPrefetch.cpp
index 838c7a1b7459d..61863bcf1337a 100644
--- a/llvm/lib/Transforms/Scalar/LoopDataPrefetch.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopDataPrefetch.cpp
@@ -304,7 +304,7 @@ bool LoopDataPrefetch::runOnLoop(Loop *L) {
   if (!Metrics.NumInsts.isValid())
     return MadeChange;
 
-  unsigned LoopSize = *Metrics.NumInsts.getValue();
+  unsigned LoopSize = Metrics.NumInsts.getValue();
   if (!LoopSize)
     LoopSize = 1;
 
diff --git a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
index fd16593b2e874..04719fb70552b 100644
--- a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
@@ -1535,7 +1535,7 @@ void Cost::RateFormula(const Formula &F,
   C.NumBaseAdds += (F.UnfoldedOffset.isNonZero());
 
   // Accumulate non-free scaling amounts.
-  C.ScaleCost += *getScalingFactorCost(*TTI, LU, F, *L).getValue();
+  C.ScaleCost += getScalingFactorCost(*TTI, LU, F, *L).getValue();
 
   // Tally up the non-zero immediates.
   for (const LSRFixup &Fixup : LU.Fixups) {
diff --git a/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp b/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
index be9b0e3244b65..d7080d6d76794 100644
--- a/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
@@ -677,8 +677,8 @@ static std::optional<EstimatedUnrollCost> analyzeLoopUnrollCost(
   LLVM_DEBUG(dbgs() << "Analysis finished:\n"
                     << "UnrolledCost: " << UnrolledCost << ", "
                     << "RolledDynamicCost: " << RolledDynamicCost << "\n");
-  return {{unsigned(*UnrolledCost.getValue()),
-           unsigned(*RolledDynamicCost.getValue())}};
+  return {{unsigned(UnrolledCost.getValue()),
+           unsigned(RolledDynamicCost.getValue())}};
 }
 
 UnrollCostEstimator::UnrollCostEstimator(
@@ -729,7 +729,7 @@ bool UnrollCostEstimator::canUnroll() const {
 uint64_t UnrollCostEstimator::getUnrolledLoopSize(
     const TargetTransformInfo::UnrollingPreferences &UP,
     unsigned CountOverwrite) const {
-  unsigned LS = *LoopSize.getValue();
+  unsigned LS = LoopSize.getValue();
   assert(LS >= UP.BEInsns && "LoopSize should not be less than BEInsns!");
   if (CountOverwrite)
     return static_cast<uint64_t>(LS - UP.BEInsns) * CountOverwrite + UP.BEInsns;
diff --git a/llvm/lib/Transforms/Scalar/NewGVN.cpp b/llvm/lib/Transforms/Scalar/NewGVN.cpp
index 58de4c0aab221..61ba3698a0340 100644
--- a/llvm/lib/Transforms/Scalar/NewGVN.cpp
+++ b/llvm/lib/Transforms/Scalar/NewGVN.cpp
@@ -1533,7 +1533,7 @@ NewGVN::performSymbolicLoadCoercion(Type *LoadType, Value *LoadPtr,
   // All of the below are only true if the loaded pointer is produced
   // by the dependent instruction.
   if (LoadPtr != lookupOperandLeader(DepInst) &&
-      !AA->isMustAlias(LoadPtr, DepInst))
+      DepInst->getType()->isPointerTy() && !AA->isMustAlias(LoadPtr, DepInst))
     return nullptr;
   // If this load really doesn't depend on anything, then we must be loading an
   // undef value.  This can happen when loading for a fresh allocation with no
diff --git a/llvm/lib/Transforms/Scalar/Reassociate.cpp b/llvm/lib/Transforms/Scalar/Reassociate.cpp
index 90b891ac87a18..8e478b37574f6 100644
--- a/llvm/lib/Transforms/Scalar/Reassociate.cpp
+++ b/llvm/lib/Transforms/Scalar/Reassociate.cpp
@@ -241,8 +241,10 @@ void ReassociatePass::canonicalizeOperands(Instruction *I) {
   Value *RHS = I->getOperand(1);
   if (LHS == RHS || isa<Constant>(RHS))
     return;
-  if (isa<Constant>(LHS) || getRank(RHS) < getRank(LHS))
+  if (isa<Constant>(LHS) || getRank(RHS) < getRank(LHS)) {
     cast<BinaryOperator>(I)->swapOperands();
+    MadeChange = true;
+  }
 }
 
 static BinaryOperator *CreateAdd(Value *S1, Value *S2, const Twine &Name,
diff --git a/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp b/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
index e048015298461..320b79203c0b3 100644
--- a/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
+++ b/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
@@ -235,8 +235,10 @@ class ConstantOffsetExtractor {
   /// \p GEP The given GEP
   /// \p UserChainTail Outputs the tail of UserChain so that we can
   ///                  garbage-collect unused instructions in UserChain.
+  /// \p PreservesNUW  Outputs whether the extraction allows preserving the
+  ///                  GEP's nuw flag, if it has one.
   static Value *Extract(Value *Idx, GetElementPtrInst *GEP,
-                        User *&UserChainTail);
+                        User *&UserChainTail, bool &PreservesNUW);
 
   /// Looks for a constant offset from the given GEP index without extracting
   /// it. It returns the numeric value of the extracted constant offset (0 if
@@ -778,8 +780,32 @@ Value *ConstantOffsetExtractor::removeConstOffset(unsigned ChainIndex) {
   return NewBO;
 }
 
+/// A helper function to check if reassociating through an entry in the user
+/// chain would invalidate the GEP's nuw flag.
+static bool allowsPreservingNUW(const User *U) {
+  if (const BinaryOperator *BO = dyn_cast<BinaryOperator>(U)) {
+    // Binary operations need to be effectively add nuw.
+    auto Opcode = BO->getOpcode();
+    if (Opcode == BinaryOperator::Or) {
+      // Ors are only considered here if they are disjoint. The addition that
+      // they represent in this case is NUW.
+      assert(cast<PossiblyDisjointInst>(BO)->isDisjoint());
+      return true;
+    }
+    return Opcode == BinaryOperator::Add && BO->hasNoUnsignedWrap();
+  }
+  // UserChain can only contain ConstantInt, CastInst, or BinaryOperator.
+  // Among the possible CastInsts, only trunc without nuw is a problem: If it
+  // is distributed through an add nuw, wrapping may occur:
+  // "add nuw trunc(a), trunc(b)" is more poisonous than "trunc(add nuw a, b)"
+  if (const TruncInst *TI = dyn_cast<TruncInst>(U))
+    return TI->hasNoUnsignedWrap();
+  return isa<CastInst>(U) || isa<ConstantInt>(U);
+}
+
 Value *ConstantOffsetExtractor::Extract(Value *Idx, GetElementPtrInst *GEP,
-                                        User *&UserChainTail) {
+                                        User *&UserChainTail,
+                                        bool &PreservesNUW) {
   ConstantOffsetExtractor Extractor(GEP->getIterator());
   // Find a non-zero constant offset first.
   APInt ConstantOffset =
@@ -787,8 +813,12 @@ Value *ConstantOffsetExtractor::Extract(Value *Idx, GetElementPtrInst *GEP,
                      GEP->isInBounds());
   if (ConstantOffset == 0) {
     UserChainTail = nullptr;
+    PreservesNUW = true;
     return nullptr;
   }
+
+  PreservesNUW = all_of(Extractor.UserChain, allowsPreservingNUW);
+
   // Separates the constant offset from the GEP index.
   Value *IdxWithoutConstOffset = Extractor.rebuildWithoutConstOffset();
   UserChainTail = Extractor.UserChain.back();
@@ -1052,6 +1082,10 @@ bool SeparateConstOffsetFromGEP::splitGEP(GetElementPtrInst *GEP) {
     }
   }
 
+  // Track information for preserving GEP flags.
+  bool AllOffsetsNonNegative = AccumulativeByteOffset >= 0;
+  bool AllNUWPreserved = true;
+
   // Remove the constant offset in each sequential index. The resultant GEP
   // computes the variadic base.
   // Notice that we don't remove struct field indices here. If LowerGEP is
@@ -1070,8 +1104,9 @@ bool SeparateConstOffsetFromGEP::splitGEP(GetElementPtrInst *GEP) {
       // uses the variadic part as the new index.
       Value *OldIdx = GEP->getOperand(I);
       User *UserChainTail;
-      Value *NewIdx =
-          ConstantOffsetExtractor::Extract(OldIdx, GEP, UserChainTail);
+      bool PreservesNUW;
+      Value *NewIdx = ConstantOffsetExtractor::Extract(
+          OldIdx, GEP, UserChainTail, PreservesNUW);
       if (NewIdx != nullptr) {
         // Switches to the index with the constant offset removed.
         GEP->setOperand(I, NewIdx);
@@ -1079,6 +1114,9 @@ bool SeparateConstOffsetFromGEP::splitGEP(GetElementPtrInst *GEP) {
         // and the old index if they are not used.
         RecursivelyDeleteTriviallyDeadInstructions(UserChainTail);
         RecursivelyDeleteTriviallyDeadInstructions(OldIdx);
+        AllOffsetsNonNegative =
+            AllOffsetsNonNegative && isKnownNonNegative(NewIdx, *DL);
+        AllNUWPreserved &= PreservesNUW;
       }
     }
   }
@@ -1099,12 +1137,35 @@ bool SeparateConstOffsetFromGEP::splitGEP(GetElementPtrInst *GEP) {
   // inbounds keyword is not present, the offsets are added to the base
   // address with silently-wrapping two's complement arithmetic".
   // Therefore, the final code will be a semantically equivalent.
-  //
-  // TODO(jingyue): do some range analysis to keep as many inbounds as
-  // possible. GEPs with inbounds are more friendly to alias analysis.
-  // TODO(gep_nowrap): Preserve nuw at least.
   GEPNoWrapFlags NewGEPFlags = GEPNoWrapFlags::none();
-  GEP->setNoWrapFlags(GEPNoWrapFlags::none());
+
+  // If the initial GEP was inbounds/nusw and all variable indices and the
+  // accumulated offsets are non-negative, they can be added in any order and
+  // the intermediate results are in bounds and don't overflow in a nusw sense.
+  // So, we can preserve the inbounds/nusw flag for both GEPs.
+  bool CanPreserveInBoundsNUSW = AllOffsetsNonNegative;
+
+  // If the initial GEP was NUW and all operations that we reassociate were NUW
+  // additions, the resulting GEPs are also NUW.
+  if (GEP->hasNoUnsignedWrap() && AllNUWPreserved) {
+    NewGEPFlags |= GEPNoWrapFlags::noUnsignedWrap();
+    // If the initial GEP additionally had NUSW (or inbounds, which implies
+    // NUSW), we know that the indices in the initial GEP must all have their
+    // signbit not set. For indices that are the result of NUW adds, the
+    // add-operands therefore also don't have their signbit set. Therefore, all
+    // indices of the resulting GEPs are non-negative -> we can preserve
+    // the inbounds/nusw flag.
+    CanPreserveInBoundsNUSW |= GEP->hasNoUnsignedSignedWrap();
+  }
+
+  if (CanPreserveInBoundsNUSW) {
+    if (GEP->isInBounds())
+      NewGEPFlags |= GEPNoWrapFlags::inBounds();
+    else if (GEP->hasNoUnsignedSignedWrap())
+      NewGEPFlags |= GEPNoWrapFlags::noUnsignedSignedWrap();
+  }
+
+  GEP->setNoWrapFlags(NewGEPFlags);
 
   // Lowers a GEP to either GEPs with a single index or arithmetic operations.
   if (LowerGEP) {
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 32c3435ccb38d..5945200a4e7b7 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -540,10 +540,6 @@ class InnerLoopVectorizer {
 protected:
   friend class LoopVectorizationPlanner;
 
-  /// Iteratively sink the scalarized operands of a predicated instruction into
-  /// the block that was created for it.
-  void sinkScalarOperands(Instruction *PredInst);
-
   /// Returns (and creates if needed) the trip count of the widened loop.
   Value *getOrCreateVectorTripCount(BasicBlock *InsertBlock);
 
@@ -628,9 +624,6 @@ class InnerLoopVectorizer {
   /// A list of all bypass blocks. The first block is the entry of the loop.
   SmallVector<BasicBlock *, 4> LoopBypassBlocks;
 
-  /// Store instructions that were predicated.
-  SmallVector<Instruction *, 4> PredicatedInstructions;
-
   /// Trip count of the original loop.
   Value *TripCount = nullptr;
 
@@ -2002,7 +1995,7 @@ class GeneratedRTChecks {
           InstructionCost NewMemCheckCost = MemCheckCost / BestTripCount;
 
           // Let's ensure the cost is always at least 1.
-          NewMemCheckCost = std::max(*NewMemCheckCost.getValue(),
+          NewMemCheckCost = std::max(NewMemCheckCost.getValue(),
                                      (InstructionCost::CostType)1);
 
           if (BestTripCount > 1)
@@ -2382,17 +2375,13 @@ void InnerLoopVectorizer::scalarizeInstruction(const Instruction *Instr,
   if (auto *II = dyn_cast<AssumeInst>(Cloned))
     AC->registerAssumption(II);
 
-  // End if-block.
-  VPRegionBlock *Parent = RepRecipe->getParent()->getParent();
-  bool IfPredicateInstr = Parent ? Parent->isReplicator() : false;
   assert(
-      (Parent || !RepRecipe->getParent()->getPlan()->getVectorLoopRegion() ||
+      (RepRecipe->getParent()->getParent() ||
+       !RepRecipe->getParent()->getPlan()->getVectorLoopRegion() ||
        all_of(RepRecipe->operands(),
               [](VPValue *Op) { return Op->isDefinedOutsideLoopRegions(); })) &&
       "Expected a recipe is either within a region or all of its operands "
       "are defined outside the vectorized region.");
-  if (IfPredicateInstr)
-    PredicatedInstructions.push_back(Cloned);
 }
 
 Value *
@@ -2866,9 +2855,6 @@ void InnerLoopVectorizer::fixVectorizedLoop(VPTransformState &State) {
   if (!State.Plan->getVectorLoopRegion())
     return;
 
-  for (Instruction *PI : PredicatedInstructions)
-    sinkScalarOperands(&*PI);
-
   VPRegionBlock *VectorRegion = State.Plan->getVectorLoopRegion();
   VPBasicBlock *HeaderVPBB = VectorRegion->getEntryBasicBlock();
   BasicBlock *HeaderBB = State.CFG.VPBB2IRBB[HeaderVPBB];
@@ -2894,82 +2880,6 @@ void InnerLoopVectorizer::fixVectorizedLoop(VPTransformState &State) {
                                VF.getKnownMinValue() * UF);
 }
 
-void InnerLoopVectorizer::sinkScalarOperands(Instruction *PredInst) {
-  // The basic block and loop containing the predicated instruction.
-  auto *PredBB = PredInst->getParent();
-  auto *VectorLoop = LI->getLoopFor(PredBB);
-
-  // Initialize a worklist with the operands of the predicated instruction.
-  SetVector<Value *> Worklist(PredInst->op_begin(), PredInst->op_end());
-
-  // Holds instructions that we need to analyze again. An instruction may be
-  // reanalyzed if we don't yet know if we can sink it or not.
-  SmallVector<Instruction *, 8> InstsToReanalyze;
-
-  // Returns true if a given use occurs in the predicated block. Phi nodes use
-  // their operands in their corresponding predecessor blocks.
-  auto IsBlockOfUsePredicated = [&](Use &U) -> bool {
-    auto *I = cast<Instruction>(U.getUser());
-    BasicBlock *BB = I->getParent();
-    if (auto *Phi = dyn_cast<PHINode>(I))
-      BB = Phi->getIncomingBlock(
-          PHINode::getIncomingValueNumForOperand(U.getOperandNo()));
-    return BB == PredBB;
-  };
-
-  // Iteratively sink the scalarized operands of the predicated instruction
-  // into the block we created for it. When an instruction is sunk, it's
-  // operands are then added to the worklist. The algorithm ends after one pass
-  // through the worklist doesn't sink a single instruction.
-  bool Changed;
-  do {
-    // Add the instructions that need to be reanalyzed to the worklist, and
-    // reset the changed indicator.
-    Worklist.insert_range(InstsToReanalyze);
-    InstsToReanalyze.clear();
-    Changed = false;
-
-    while (!Worklist.empty()) {
-      auto *I = dyn_cast<Instruction>(Worklist.pop_back_val());
-
-      // We can't sink an instruction if it is a phi node, is not in the loop,
-      // may have side effects or may read from memory.
-      // TODO: Could do more granular checking to allow sinking
-      // a load past non-store instructions.
-      if (!I || isa<PHINode>(I) || !VectorLoop->contains(I) ||
-          I->mayHaveSideEffects() || I->mayReadFromMemory())
-          continue;
-
-      // If the instruction is already in PredBB, check if we can sink its
-      // operands. In that case, VPlan's sinkScalarOperands() succeeded in
-      // sinking the scalar instruction I, hence it appears in PredBB; but it
-      // may have failed to sink I's operands (recursively), which we try
-      // (again) here.
-      if (I->getParent() == PredBB) {
-        Worklist.insert_range(I->operands());
-        continue;
-      }
-
-      // It's legal to sink the instruction if all its uses occur in the
-      // predicated block. Otherwise, there's nothing to do yet, and we may
-      // need to reanalyze the instruction.
-      if (!llvm::all_of(I->uses(), IsBlockOfUsePredicated)) {
-        InstsToReanalyze.push_back(I);
-        continue;
-      }
-
-      // Move the instruction to the beginning of the predicated block, and add
-      // it's operands to the worklist.
-      I->moveBefore(PredBB->getFirstInsertionPt());
-      Worklist.insert_range(I->operands());
-
-      // The sinking may have enabled other instructions to be sunk, so we will
-      // need to iterate.
-      Changed = true;
-    }
-  } while (Changed);
-}
-
 void InnerLoopVectorizer::fixNonInductionPHIs(VPTransformState &State) {
   auto Iter = vp_depth_first_deep(Plan.getEntry());
   for (VPBasicBlock *VPBB : VPBlockUtils::blocksOnly<VPBasicBlock>(Iter)) {
@@ -4460,6 +4370,7 @@ static bool willGenerateVectors(VPlan &Plan, ElementCount VF,
       case VPDef::VPWidenSelectSC:
       case VPDef::VPBlendSC:
       case VPDef::VPFirstOrderRecurrencePHISC:
+      case VPDef::VPHistogramSC:
       case VPDef::VPWidenPHISC:
       case VPDef::VPWidenIntOrFpInductionSC:
       case VPDef::VPWidenPointerInductionSC:
@@ -5314,7 +5225,7 @@ LoopVectorizationCostModel::selectInterleaveCount(VPlan &Plan, ElementCount VF,
     // to estimate the cost of the loop and interleave until the cost of the
     // loop overhead is about 5% of the cost of the loop.
     unsigned SmallIC = std::min(IC, (unsigned)llvm::bit_floor<uint64_t>(
-                                        SmallLoopCost / *LoopCost.getValue()));
+                                        SmallLoopCost / LoopCost.getValue()));
 
     // Interleave until store/load ports (estimated by max interleave count) are
     // saturated.
@@ -7659,7 +7570,7 @@ InstructionCost LoopVectorizationPlanner::cost(VPlan &Plan,
   LLVM_DEBUG(dbgs() << "Cost for VF " << VF << ": " << Cost
                     << " (Estimated cost per lane: ");
   if (Cost.isValid()) {
-    double CostPerLane = double(*Cost.getValue()) / EstimatedWidth;
+    double CostPerLane = double(Cost.getValue()) / EstimatedWidth;
     LLVM_DEBUG(dbgs() << format("%.1f", CostPerLane));
   } else /* No point dividing an invalid cost - it will still be invalid */
     LLVM_DEBUG(dbgs() << "Invalid");
@@ -9076,9 +8987,13 @@ bool VPRecipeBuilder::getScaledReductions(
 
   PartialReductionChain Chain(RdxExitInstr, ExtA, ExtB, BinOp);
 
-  unsigned TargetScaleFactor =
-      PHI->getType()->getPrimitiveSizeInBits().getKnownScalarFactor(
-          A->getType()->getPrimitiveSizeInBits());
+  TypeSize PHISize = PHI->getType()->getPrimitiveSizeInBits();
+  TypeSize ASize = A->getType()->getPrimitiveSizeInBits();
+
+  if (!PHISize.hasKnownScalarFactor(ASize))
+    return false;
+
+  unsigned TargetScaleFactor = PHISize.getKnownScalarFactor(ASize);
 
   if (LoopVectorizationPlanner::getDecisionAndClampRange(
           [&](ElementCount VF) {
@@ -9368,17 +9283,10 @@ static void addScalarResumePhis(VPRecipeBuilder &Builder, VPlan &Plan,
   }
 }
 
-// Collect VPIRInstructions for phis in the exit blocks that are modeled
-// in VPlan and add the exiting VPValue as operand.
-static SetVector<VPIRInstruction *>
-collectUsersInExitBlocks(Loop *OrigLoop, VPRecipeBuilder &Builder,
-                         VPlan &Plan) {
+// Collect VPIRInstructions for phis in the exit block from the latch only.
+static SetVector<VPIRInstruction *> collectUsersInLatchExitBlock(VPlan &Plan) {
   SetVector<VPIRInstruction *> ExitUsersToFix;
   for (VPIRBasicBlock *ExitVPBB : Plan.getExitBlocks()) {
-    // Nothing to do for unreachable exit blocks.
-    if (ExitVPBB->getNumPredecessors() == 0)
-      continue;
-
     for (VPRecipeBase &R : ExitVPBB->phis()) {
       auto *ExitIRI = cast<VPIRPhi>(&R);
       if (ExitVPBB->getSinglePredecessor() != Plan.getMiddleBlock()) {
@@ -9388,11 +9296,8 @@ collectUsersInExitBlocks(Loop *OrigLoop, VPRecipeBuilder &Builder,
         continue;
       }
 
-      PHINode &ExitPhi = ExitIRI->getIRPhi();
-      BasicBlock *ExitingBB = OrigLoop->getLoopLatch();
-      Value *IncomingValue = ExitPhi.getIncomingValueForBlock(ExitingBB);
-      VPValue *V = Builder.getVPValueOrAddLiveIn(IncomingValue);
-      ExitIRI->addOperand(V);
+      assert(ExitIRI->getNumOperands() == 1 && "must have a single operand");
+      VPValue *V = ExitIRI->getOperand(0);
       if (V->isLiveIn())
         continue;
       assert(V->getDefiningRecipe()->getParent()->getEnclosingLoopRegion() &&
@@ -9421,7 +9326,7 @@ addUsersInExitBlocks(VPlan &Plan,
            ExitIRI->getParent()->getSinglePredecessor() == MiddleVPBB &&
            "exit values from early exits must be fixed when branch to "
            "early-exit is added");
-    ExitIRI->extractLastLaneOfOperand(B);
+    ExitIRI->extractLastLaneOfFirstOperand(B);
   }
 }
 
@@ -9762,7 +9667,7 @@ LoopVectorizationPlanner::tryToBuildVPlanWithVPRecipes(VFRange &Range) {
   DenseMap<VPValue *, VPValue *> IVEndValues;
   addScalarResumePhis(RecipeBuilder, *Plan, IVEndValues);
   SetVector<VPIRInstruction *> ExitUsersToFix =
-      collectUsersInExitBlocks(OrigLoop, RecipeBuilder, *Plan);
+      collectUsersInLatchExitBlock(*Plan);
   addExitUsersForFirstOrderRecurrences(*Plan, ExitUsersToFix);
   addUsersInExitBlocks(*Plan, ExitUsersToFix);
 
@@ -10478,7 +10383,7 @@ static bool isOutsideLoopWorkProfitable(GeneratedRTChecks &Checks,
 
   // The scalar cost should only be 0 when vectorizing with a user specified
   // VF/IC. In those cases, runtime checks should always be generated.
-  uint64_t ScalarC = *VF.ScalarCost.getValue();
+  uint64_t ScalarC = VF.ScalarCost.getValue();
   if (ScalarC == 0)
     return true;
 
@@ -10513,8 +10418,8 @@ static bool isOutsideLoopWorkProfitable(GeneratedRTChecks &Checks,
   // the computations are performed on doubles, not integers and the result
   // is rounded up, hence we get an upper estimate of the TC.
   unsigned IntVF = getEstimatedRuntimeVF(VF.Width, VScale);
-  uint64_t RtC = *TotalCost.getValue();
-  uint64_t Div = ScalarC * IntVF - *VF.Cost.getValue();
+  uint64_t RtC = TotalCost.getValue();
+  uint64_t Div = ScalarC * IntVF - VF.Cost.getValue();
   uint64_t MinTC1 = Div == 0 ? 0 : divideCeil(RtC * IntVF, Div);
 
   // Second, compute a minimum iteration count so that the cost of the
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.cpp b/llvm/lib/Transforms/Vectorize/VPlan.cpp
index fa2d95a44609a..701e4bfe0623e 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlan.cpp
@@ -363,17 +363,6 @@ void VPTransformState::addNewMetadata(Instruction *To,
     LVer->annotateInstWithNoAlias(To, Orig);
 }
 
-void VPTransformState::addMetadata(Value *To, Instruction *From) {
-  // No source instruction to transfer metadata from?
-  if (!From)
-    return;
-
-  if (Instruction *ToI = dyn_cast<Instruction>(To)) {
-    propagateMetadata(ToI, From);
-    addNewMetadata(ToI, From);
-  }
-}
-
 void VPTransformState::setDebugLocFrom(DebugLoc DL) {
   const DILocation *DIL = DL;
   // When a FSDiscriminator is enabled, we don't need to add the multiply
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h
index 0f2aac146e7a6..bd6e15d3fb7a5 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.h
+++ b/llvm/lib/Transforms/Vectorize/VPlan.h
@@ -1161,10 +1161,10 @@ class VPIRInstruction : public VPRecipeBase {
     return true;
   }
 
-  /// Update the recipes single operand to the last lane of the operand using \p
-  /// Builder. Must only be used for single operand VPIRInstructions wrapping a
-  /// PHINode.
-  void extractLastLaneOfOperand(VPBuilder &Builder);
+  /// Update the recipes first operand to the last lane of the operand using \p
+  /// Builder. Must only be used for VPIRInstructions with at least one operand
+  /// wrapping a PHINode.
+  void extractLastLaneOfFirstOperand(VPBuilder &Builder);
 };
 
 /// An overlay for VPIRInstructions wrapping PHI nodes enabling convenient use
@@ -1190,18 +1190,33 @@ struct VPIRPhi : public VPIRInstruction {
 #endif
 };
 
+/// Helper to manage IR metadata for recipes. It filters out metadata that
+/// cannot be propagated.
+class VPIRMetadata {
+  SmallVector<std::pair<unsigned, MDNode *>> Metadata;
+
+protected:
+  VPIRMetadata() {}
+  VPIRMetadata(Instruction &I) { getMetadataToPropagate(&I, Metadata); }
+
+public:
+  /// Add all metadata to \p I.
+  void applyMetadata(Instruction &I) const;
+};
+
 /// VPWidenRecipe is a recipe for producing a widened instruction using the
 /// opcode and operands of the recipe. This recipe covers most of the
 /// traditional vectorization cases where each recipe transforms into a
 /// vectorized version of itself.
-class VPWidenRecipe : public VPRecipeWithIRFlags {
+class VPWidenRecipe : public VPRecipeWithIRFlags, public VPIRMetadata {
   unsigned Opcode;
 
 protected:
   template <typename IterT>
   VPWidenRecipe(unsigned VPDefOpcode, Instruction &I,
                 iterator_range<IterT> Operands)
-      : VPRecipeWithIRFlags(VPDefOpcode, Operands, I), Opcode(I.getOpcode()) {}
+      : VPRecipeWithIRFlags(VPDefOpcode, Operands, I), VPIRMetadata(I),
+        Opcode(I.getOpcode()) {}
 
 public:
   template <typename IterT>
@@ -1236,7 +1251,7 @@ class VPWidenRecipe : public VPRecipeWithIRFlags {
 };
 
 /// VPWidenCastRecipe is a recipe to create vector cast instructions.
-class VPWidenCastRecipe : public VPRecipeWithIRFlags {
+class VPWidenCastRecipe : public VPRecipeWithIRFlags, public VPIRMetadata {
   /// Cast instruction opcode.
   Instruction::CastOps Opcode;
 
@@ -1246,15 +1261,15 @@ class VPWidenCastRecipe : public VPRecipeWithIRFlags {
 public:
   VPWidenCastRecipe(Instruction::CastOps Opcode, VPValue *Op, Type *ResultTy,
                     CastInst &UI)
-      : VPRecipeWithIRFlags(VPDef::VPWidenCastSC, Op, UI), Opcode(Opcode),
-        ResultTy(ResultTy) {
+      : VPRecipeWithIRFlags(VPDef::VPWidenCastSC, Op, UI), VPIRMetadata(UI),
+        Opcode(Opcode), ResultTy(ResultTy) {
     assert(UI.getOpcode() == Opcode &&
            "opcode of underlying cast doesn't match");
   }
 
   VPWidenCastRecipe(Instruction::CastOps Opcode, VPValue *Op, Type *ResultTy)
-      : VPRecipeWithIRFlags(VPDef::VPWidenCastSC, Op), Opcode(Opcode),
-        ResultTy(ResultTy) {}
+      : VPRecipeWithIRFlags(VPDef::VPWidenCastSC, Op), VPIRMetadata(),
+        Opcode(Opcode), ResultTy(ResultTy) {}
 
   ~VPWidenCastRecipe() override = default;
 
@@ -1288,7 +1303,7 @@ class VPWidenCastRecipe : public VPRecipeWithIRFlags {
 };
 
 /// A recipe for widening vector intrinsics.
-class VPWidenIntrinsicRecipe : public VPRecipeWithIRFlags {
+class VPWidenIntrinsicRecipe : public VPRecipeWithIRFlags, public VPIRMetadata {
   /// ID of the vector intrinsic to widen.
   Intrinsic::ID VectorIntrinsicID;
 
@@ -1309,7 +1324,7 @@ class VPWidenIntrinsicRecipe : public VPRecipeWithIRFlags {
                          ArrayRef<VPValue *> CallArguments, Type *Ty,
                          DebugLoc DL = {})
       : VPRecipeWithIRFlags(VPDef::VPWidenIntrinsicSC, CallArguments, CI),
-        VectorIntrinsicID(VectorIntrinsicID), ResultTy(Ty),
+        VPIRMetadata(CI), VectorIntrinsicID(VectorIntrinsicID), ResultTy(Ty),
         MayReadFromMemory(CI.mayReadFromMemory()),
         MayWriteToMemory(CI.mayWriteToMemory()),
         MayHaveSideEffects(CI.mayHaveSideEffects()) {}
@@ -1318,7 +1333,7 @@ class VPWidenIntrinsicRecipe : public VPRecipeWithIRFlags {
                          ArrayRef<VPValue *> CallArguments, Type *Ty,
                          DebugLoc DL = {})
       : VPRecipeWithIRFlags(VPDef::VPWidenIntrinsicSC, CallArguments, DL),
-        VectorIntrinsicID(VectorIntrinsicID), ResultTy(Ty) {
+        VPIRMetadata(), VectorIntrinsicID(VectorIntrinsicID), ResultTy(Ty) {
     LLVMContext &Ctx = Ty->getContext();
     AttributeSet Attrs = Intrinsic::getFnAttributes(Ctx, VectorIntrinsicID);
     MemoryEffects ME = Attrs.getMemoryEffects();
@@ -1374,7 +1389,7 @@ class VPWidenIntrinsicRecipe : public VPRecipeWithIRFlags {
 };
 
 /// A recipe for widening Call instructions using library calls.
-class VPWidenCallRecipe : public VPRecipeWithIRFlags {
+class VPWidenCallRecipe : public VPRecipeWithIRFlags, public VPIRMetadata {
   /// Variant stores a pointer to the chosen function. There is a 1:1 mapping
   /// between a given VF and the chosen vectorized variant, so there will be a
   /// different VPlan for each VF with a valid variant.
@@ -1385,7 +1400,7 @@ class VPWidenCallRecipe : public VPRecipeWithIRFlags {
                     ArrayRef<VPValue *> CallArguments, DebugLoc DL = {})
       : VPRecipeWithIRFlags(VPDef::VPWidenCallSC, CallArguments,
                             *cast<Instruction>(UV)),
-        Variant(Variant) {
+        VPIRMetadata(*cast<Instruction>(UV)), Variant(Variant) {
     assert(
         isa<Function>(getOperand(getNumOperands() - 1)->getLiveInIRValue()) &&
         "last operand must be the called function");
@@ -1471,10 +1486,11 @@ class VPHistogramRecipe : public VPRecipeBase {
 };
 
 /// A recipe for widening select instructions.
-struct VPWidenSelectRecipe : public VPRecipeWithIRFlags {
+struct VPWidenSelectRecipe : public VPRecipeWithIRFlags, public VPIRMetadata {
   template <typename IterT>
   VPWidenSelectRecipe(SelectInst &I, iterator_range<IterT> Operands)
-      : VPRecipeWithIRFlags(VPDef::VPWidenSelectSC, Operands, I) {}
+      : VPRecipeWithIRFlags(VPDef::VPWidenSelectSC, Operands, I),
+        VPIRMetadata(I) {}
 
   ~VPWidenSelectRecipe() override = default;
 
@@ -2602,7 +2618,7 @@ class VPPredInstPHIRecipe : public VPSingleDefRecipe {
 
 /// A common base class for widening memory operations. An optional mask can be
 /// provided as the last operand.
-class VPWidenMemoryRecipe : public VPRecipeBase {
+class VPWidenMemoryRecipe : public VPRecipeBase, public VPIRMetadata {
 protected:
   Instruction &Ingredient;
 
@@ -2626,8 +2642,8 @@ class VPWidenMemoryRecipe : public VPRecipeBase {
   VPWidenMemoryRecipe(const char unsigned SC, Instruction &I,
                       std::initializer_list<VPValue *> Operands,
                       bool Consecutive, bool Reverse, DebugLoc DL)
-      : VPRecipeBase(SC, Operands, DL), Ingredient(I), Consecutive(Consecutive),
-        Reverse(Reverse) {
+      : VPRecipeBase(SC, Operands, DL), VPIRMetadata(I), Ingredient(I),
+        Consecutive(Consecutive), Reverse(Reverse) {
     assert((Consecutive || !Reverse) && "Reverse implies consecutive");
   }
 
diff --git a/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp b/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
index 9fcccfcf8117f..f24d42256caef 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
@@ -352,6 +352,23 @@ std::unique_ptr<VPlan> PlainCFGBuilder::buildPlainCFG(
   Plan->getEntry()->setOneSuccessor(getOrCreateVPBB(TheLoop->getHeader()));
   Plan->getEntry()->setPlan(&*Plan);
 
+  // Fix VPlan loop-closed-ssa exit phi's by adding incoming operands to the
+  // VPIRInstructions wrapping them.
+  // // Note that the operand order corresponds to IR predecessor order, and may
+  // need adjusting when VPlan predecessors are added, if an exit block has
+  // multiple predecessor.
+  for (auto *EB : Plan->getExitBlocks()) {
+    for (VPRecipeBase &R : EB->phis()) {
+      auto *PhiR = cast<VPIRPhi>(&R);
+      PHINode &Phi = PhiR->getIRPhi();
+      assert(PhiR->getNumOperands() == 0 &&
+             "no phi operands should be added yet");
+      for (BasicBlock *Pred : predecessors(EB->getIRBasicBlock()))
+        PhiR->addOperand(
+            getOrCreateVPOperand(Phi.getIncomingValueForBlock(Pred)));
+    }
+  }
+
   for (const auto &[IRBB, VPB] : BB2VPBB)
     VPB2IRBB[VPB] = IRBB;
 
@@ -413,7 +430,6 @@ static void createLoopRegion(VPlan &Plan, VPBlockBase *HeaderVPB) {
 
   auto *R = Plan.createVPRegionBlock(HeaderVPB, LatchVPBB, "",
                                      false /*isReplicator*/);
-  R->setParent(HeaderVPB->getParent());
   // All VPBB's reachable shallowly from HeaderVPB belong to top level loop,
   // because VPlan is expected to end at top level latch disconnected above.
   for (VPBlockBase *VPBB : vp_depth_first_shallow(HeaderVPB))
@@ -462,19 +478,28 @@ void VPlanTransforms::createLoopRegions(VPlan &Plan, Type *InductionTy,
 
   VPBasicBlock *ScalarPH = Plan.createVPBasicBlock("scalar.ph");
   VPBlockUtils::connectBlocks(ScalarPH, Plan.getScalarHeader());
-  if (!RequiresScalarEpilogueCheck) {
-    VPBlockUtils::connectBlocks(MiddleVPBB, ScalarPH);
-    return;
-  }
 
   // If needed, add a check in the middle block to see if we have completed
   // all of the iterations in the first vector loop.  Three cases:
-  // 1) If (N - N%VF) == N, then we *don't* need to run the remainder.
+  // 1) If we require a scalar epilogue, there is no conditional branch as
+  //    we unconditionally branch to the scalar preheader.  Remove the recipes
+  //    from the exit blocks.
+  // 2) If (N - N%VF) == N, then we *don't* need to run the remainder.
   //    Thus if tail is to be folded, we know we don't need to run the
   //    remainder and we can set the condition to true.
-  // 2) If we require a scalar epilogue, there is no conditional branch as
-  //    we unconditionally branch to the scalar preheader.  Do nothing.
   // 3) Otherwise, construct a runtime check.
+
+  if (!RequiresScalarEpilogueCheck) {
+    VPBlockUtils::connectBlocks(MiddleVPBB, ScalarPH);
+    // The exit blocks are unreachable, remove their recipes to make sure no
+    // users remain that may pessimize transforms.
+    for (auto *EB : Plan.getExitBlocks()) {
+      for (VPRecipeBase &R : make_early_inc_range(*EB))
+        R.eraseFromParent();
+    }
+    return;
+  }
+
   BasicBlock *IRExitBlock = TheLoop->getUniqueLatchExitBlock();
   auto *VPExitBlock = Plan.getExitBlock(IRExitBlock);
   // The connection order corresponds to the operands of the conditional branch.
diff --git a/llvm/lib/Transforms/Vectorize/VPlanHelpers.h b/llvm/lib/Transforms/Vectorize/VPlanHelpers.h
index bebea1915690f..e860595b473a0 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanHelpers.h
+++ b/llvm/lib/Transforms/Vectorize/VPlanHelpers.h
@@ -290,13 +290,6 @@ struct VPTransformState {
   /// vector loop.
   void addNewMetadata(Instruction *To, const Instruction *Orig);
 
-  /// Add metadata from one instruction to another.
-  ///
-  /// This includes both the original MDs from \p From and additional ones (\see
-  /// addNewMetadata).  Use this for *newly created* instructions in the vector
-  /// loop.
-  void addMetadata(Value *To, Instruction *From);
-
   /// Set the debug location in the builder using the debug location \p DL.
   void setDebugLocFrom(DebugLoc DL);
 
diff --git a/llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h b/llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
index f38eb3cc8d43f..58865c296ed8a 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
+++ b/llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
@@ -222,7 +222,8 @@ struct Recipe_match {
       return false;
 
     assert(R->getNumOperands() == std::tuple_size<Ops_t>::value &&
-           "recipe with matched opcode the expected number of operands");
+           "recipe with matched opcode does not have the expected number of "
+           "operands");
 
     auto IdxSeq = std::make_index_sequence<std::tuple_size<Ops_t>::value>();
     if (all_of_tuple_elements(IdxSeq, [R](auto Op, unsigned Idx) {
diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
index a342d5182c974..8ec092ce9a905 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
@@ -1137,19 +1137,19 @@ InstructionCost VPIRInstruction::computeCost(ElementCount VF,
   return 0;
 }
 
-void VPIRInstruction::extractLastLaneOfOperand(VPBuilder &Builder) {
+void VPIRInstruction::extractLastLaneOfFirstOperand(VPBuilder &Builder) {
   assert(isa<PHINode>(getInstruction()) &&
-         "can only add exiting operands to phi nodes");
-  assert(getNumOperands() == 1 && "must have a single operand");
+         "can only update exiting operands to phi nodes");
+  assert(getNumOperands() > 0 && "must have at least one operand");
   VPValue *Exiting = getOperand(0);
-  if (!Exiting->isLiveIn()) {
-    LLVMContext &Ctx = getInstruction().getContext();
-    auto &Plan = *getParent()->getPlan();
-    Exiting = Builder.createNaryOp(
-        VPInstruction::ExtractFromEnd,
-        {Exiting,
-         Plan.getOrAddLiveIn(ConstantInt::get(IntegerType::get(Ctx, 32), 1))});
-  }
+  if (Exiting->isLiveIn())
+    return;
+
+  LLVMContext &Ctx = getInstruction().getContext();
+  auto &Plan = *getParent()->getPlan();
+  Exiting = Builder.createNaryOp(VPInstruction::ExtractFromEnd,
+                                 {Exiting, Plan.getOrAddLiveIn(ConstantInt::get(
+                                               IntegerType::get(Ctx, 32), 1))});
   setOperand(0, Exiting);
 }
 
@@ -1205,6 +1205,11 @@ void VPIRPhi::print(raw_ostream &O, const Twine &Indent,
 }
 #endif
 
+void VPIRMetadata::applyMetadata(Instruction &I) const {
+  for (const auto &[Kind, Node] : Metadata)
+    I.setMetadata(Kind, Node);
+}
+
 void VPWidenCallRecipe::execute(VPTransformState &State) {
   assert(State.VF.isVector() && "not widening");
   assert(Variant != nullptr && "Can't create vector function.");
@@ -1231,11 +1236,11 @@ void VPWidenCallRecipe::execute(VPTransformState &State) {
 
   CallInst *V = State.Builder.CreateCall(Variant, Args, OpBundles);
   applyFlags(*V);
+  applyMetadata(*V);
   V->setCallingConv(Variant->getCallingConv());
 
   if (!V->getType()->isVoidTy())
     State.set(this, V);
-  State.addMetadata(V, CI);
 }
 
 InstructionCost VPWidenCallRecipe::computeCost(ElementCount VF,
@@ -1311,10 +1316,10 @@ void VPWidenIntrinsicRecipe::execute(VPTransformState &State) {
   CallInst *V = State.Builder.CreateCall(VectorF, Args, OpBundles);
 
   applyFlags(*V);
+  applyMetadata(*V);
 
   if (!V->getType()->isVoidTy())
     State.set(this, V);
-  State.addMetadata(V, CI);
 }
 
 InstructionCost VPWidenIntrinsicRecipe::computeCost(ElementCount VF,
@@ -1509,9 +1514,11 @@ void VPWidenSelectRecipe::execute(VPTransformState &State) {
   Value *Op1 = State.get(getOperand(2));
   Value *Sel = State.Builder.CreateSelect(Cond, Op0, Op1);
   State.set(this, Sel);
-  if (isa<FPMathOperator>(Sel))
-    applyFlags(*cast<Instruction>(Sel));
-  State.addMetadata(Sel, dyn_cast_or_null<Instruction>(getUnderlyingValue()));
+  if (auto *I = dyn_cast<Instruction>(Sel)) {
+    if (isa<FPMathOperator>(I))
+      applyFlags(*I);
+    applyMetadata(*I);
+  }
 }
 
 InstructionCost VPWidenSelectRecipe::computeCost(ElementCount VF,
@@ -1642,12 +1649,13 @@ void VPWidenRecipe::execute(VPTransformState &State) {
 
     Value *V = Builder.CreateNAryOp(Opcode, Ops);
 
-    if (auto *VecOp = dyn_cast<Instruction>(V))
+    if (auto *VecOp = dyn_cast<Instruction>(V)) {
       applyFlags(*VecOp);
+      applyMetadata(*VecOp);
+    }
 
     // Use this vector value for all users of the original instruction.
     State.set(this, V);
-    State.addMetadata(V, dyn_cast_or_null<Instruction>(getUnderlyingValue()));
     break;
   }
   case Instruction::ExtractValue: {
@@ -1679,8 +1687,9 @@ void VPWidenRecipe::execute(VPTransformState &State) {
     } else {
       C = Builder.CreateICmp(getPredicate(), A, B);
     }
+    if (auto *I = dyn_cast<Instruction>(C))
+      applyMetadata(*I);
     State.set(this, C);
-    State.addMetadata(C, dyn_cast_or_null<Instruction>(getUnderlyingValue()));
     break;
   }
   default:
@@ -1796,9 +1805,10 @@ void VPWidenCastRecipe::execute(VPTransformState &State) {
   Value *A = State.get(Op);
   Value *Cast = Builder.CreateCast(Instruction::CastOps(Opcode), A, DestTy);
   State.set(this, Cast);
-  State.addMetadata(Cast, cast_or_null<Instruction>(getUnderlyingValue()));
-  if (auto *CastOp = dyn_cast<Instruction>(Cast))
+  if (auto *CastOp = dyn_cast<Instruction>(Cast)) {
     applyFlags(*CastOp);
+    applyMetadata(*CastOp);
+  }
 }
 
 InstructionCost VPWidenCastRecipe::computeCost(ElementCount VF,
@@ -2750,8 +2760,10 @@ void VPWidenLoadRecipe::execute(VPTransformState &State) {
   } else {
     NewLI = Builder.CreateAlignedLoad(DataTy, Addr, Alignment, "wide.load");
   }
-  // Add metadata to the load, but setVectorValue to the reverse shuffle.
-  State.addMetadata(NewLI, cast<LoadInst>(&Ingredient));
+  // Add metadata to the load, but set the result to the reverse shuffle, if
+  // needed.
+  State.addNewMetadata(cast<Instruction>(NewLI), &Ingredient);
+  applyMetadata(*cast<Instruction>(NewLI));
   if (Reverse)
     NewLI = Builder.CreateVectorReverse(NewLI, "reverse");
   State.set(this, NewLI);
@@ -2810,7 +2822,8 @@ void VPWidenLoadEVLRecipe::execute(VPTransformState &State) {
   }
   NewLI->addParamAttr(
       0, Attribute::getWithAlignment(NewLI->getContext(), Alignment));
-  State.addMetadata(NewLI, cast<LoadInst>(&Ingredient));
+  State.addNewMetadata(NewLI, &Ingredient);
+  applyMetadata(*NewLI);
   Instruction *Res = NewLI;
   if (isReverse())
     Res = createReverseEVL(Builder, Res, EVL, "vp.reverse");
@@ -2884,7 +2897,8 @@ void VPWidenStoreRecipe::execute(VPTransformState &State) {
     NewSI = Builder.CreateMaskedStore(StoredVal, Addr, Alignment, Mask);
   else
     NewSI = Builder.CreateAlignedStore(StoredVal, Addr, Alignment);
-  State.addMetadata(NewSI, cast<StoreInst>(&Ingredient));
+  State.addNewMetadata(NewSI, &Ingredient);
+  applyMetadata(*NewSI);
 }
 
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
@@ -2930,7 +2944,8 @@ void VPWidenStoreEVLRecipe::execute(VPTransformState &State) {
   }
   NewSI->addParamAttr(
       1, Attribute::getWithAlignment(NewSI->getContext(), Alignment));
-  State.addMetadata(NewSI, cast<StoreInst>(&Ingredient));
+  State.addNewMetadata(NewSI, &Ingredient);
+  applyMetadata(*NewSI);
 }
 
 InstructionCost VPWidenStoreEVLRecipe::computeCost(ElementCount VF,
diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
index f2dc68b2ea8b6..10cd7d85ba41c 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
@@ -2505,20 +2505,29 @@ void VPlanTransforms::handleUncountableEarlyExit(
   VPBuilder EarlyExitB(VectorEarlyExitVPBB);
   for (VPRecipeBase &R : VPEarlyExitBlock->phis()) {
     auto *ExitIRI = cast<VPIRPhi>(&R);
-    PHINode &ExitPhi = ExitIRI->getIRPhi();
-    VPValue *IncomingFromEarlyExit = RecipeBuilder.getVPValueOrAddLiveIn(
-        ExitPhi.getIncomingValueForBlock(UncountableExitingBlock));
-
-    if (OrigLoop->getUniqueExitBlock()) {
-      // If there's a unique exit block, VPEarlyExitBlock has 2 predecessors
-      // (MiddleVPBB and NewMiddle). Add the incoming value from MiddleVPBB
-      // which is coming from the original latch.
-      VPValue *IncomingFromLatch = RecipeBuilder.getVPValueOrAddLiveIn(
-          ExitPhi.getIncomingValueForBlock(OrigLoop->getLoopLatch()));
-      ExitIRI->addOperand(IncomingFromLatch);
-      ExitIRI->extractLastLaneOfOperand(MiddleBuilder);
+    // Early exit operand should always be last, i.e., 0 if VPEarlyExitBlock has
+    // a single predecessor and 1 if it has two.
+    unsigned EarlyExitIdx = ExitIRI->getNumOperands() - 1;
+    if (!VPEarlyExitBlock->getSinglePredecessor()) {
+      // If VPEarlyExitBlock has two predecessors, they are already ordered such
+      // that early exit is second (and latch exit is first), by construction.
+      // But its underlying IRBB (EarlyExitIRBB) may have its predecessors
+      // ordered the other way around, and it is the order of the latter which
+      // corresponds to the order of operands of VPEarlyExitBlock's phi recipes.
+      // Therefore, if early exit (UncountableExitingBlock) is the first
+      // predecessor of EarlyExitIRBB, we swap the operands of phi recipes,
+      // thereby bringing them to match VPEarlyExitBlock's predecessor order,
+      // with early exit being last (second). Otherwise they already match.
+      if (*pred_begin(VPEarlyExitBlock->getIRBasicBlock()) ==
+          UncountableExitingBlock)
+        ExitIRI->swapOperands();
+
+      // The first of two operands corresponds to the latch exit, via MiddleVPBB
+      // predecessor. Extract its last lane.
+      ExitIRI->extractLastLaneOfFirstOperand(MiddleBuilder);
     }
 
+    VPValue *IncomingFromEarlyExit = ExitIRI->getOperand(EarlyExitIdx);
     auto IsVector = [](ElementCount VF) { return VF.isVector(); };
     // When the VFs are vectors, need to add `extract` to get the incoming value
     // from early exit. When the range contains scalar VF, limit the range to
@@ -2526,14 +2535,15 @@ void VPlanTransforms::handleUncountableEarlyExit(
     // and vector VFs.
     if (!IncomingFromEarlyExit->isLiveIn() &&
         LoopVectorizationPlanner::getDecisionAndClampRange(IsVector, Range)) {
+      // Update the incoming value from the early exit.
       VPValue *FirstActiveLane = EarlyExitB.createNaryOp(
           VPInstruction::FirstActiveLane, {EarlyExitTakenCond}, nullptr,
           "first.active.lane");
       IncomingFromEarlyExit = EarlyExitB.createNaryOp(
           Instruction::ExtractElement, {IncomingFromEarlyExit, FirstActiveLane},
           nullptr, "early.exit.value");
+      ExitIRI->setOperand(EarlyExitIdx, IncomingFromEarlyExit);
     }
-    ExitIRI->addOperand(IncomingFromEarlyExit);
   }
   MiddleBuilder.createNaryOp(VPInstruction::BranchOnCond, {IsEarlyExitTaken});
 
diff --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
index bd225bcc0635e..04c084ffdda97 100644
--- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
@@ -1438,6 +1438,7 @@ static ScalarizationResult canScalarizeAccess(VectorType *VecTy, Value *Idx,
   // This is the number of elements of fixed vector types,
   // or the minimum number of elements of scalable vector types.
   uint64_t NumElements = VecTy->getElementCount().getKnownMinValue();
+  unsigned IntWidth = Idx->getType()->getScalarSizeInBits();
 
   if (auto *C = dyn_cast<ConstantInt>(Idx)) {
     if (C->getValue().ult(NumElements))
@@ -1445,7 +1446,10 @@ static ScalarizationResult canScalarizeAccess(VectorType *VecTy, Value *Idx,
     return ScalarizationResult::unsafe();
   }
 
-  unsigned IntWidth = Idx->getType()->getScalarSizeInBits();
+  // Always unsafe if the index type can't handle all inbound values.
+  if (!llvm::isUIntN(IntWidth, NumElements))
+    return ScalarizationResult::unsafe();
+
   APInt Zero(IntWidth, 0);
   APInt MaxElts(IntWidth, NumElements);
   ConstantRange ValidIndices(Zero, MaxElts);
diff --git a/llvm/runtimes/CMakeLists.txt b/llvm/runtimes/CMakeLists.txt
index 51433d1ec9831..670e3ae84870a 100644
--- a/llvm/runtimes/CMakeLists.txt
+++ b/llvm/runtimes/CMakeLists.txt
@@ -514,7 +514,8 @@ if(build_runtimes)
     list(APPEND extra_cmake_args "-DCMAKE_PROGRAM_PATH=${CMAKE_PROGRAM_PATH}")
   endif()
 
-  if("openmp" IN_LIST LLVM_ENABLE_RUNTIMES)
+  # TODO: We need to consider passing it as '-DRUNTIMES_x86_64_LLVM_ENABLE_RUNTIMES'.
+  if("openmp" IN_LIST LLVM_ENABLE_RUNTIMES OR "offload" IN_LIST LLVM_ENABLE_RUNTIMES)
     if (${LLVM_TOOL_FLANG_BUILD})
       message(STATUS "Configuring build of omp_lib.mod and omp_lib_kinds.mod via flang")
       set(LIBOMP_FORTRAN_MODULES_COMPILER "${CMAKE_BINARY_DIR}/bin/flang")
@@ -526,7 +527,7 @@ if(build_runtimes)
       # that all .mod files are also properly build.
       list(APPEND extra_deps "flang" "module_files")
     endif()
-    foreach(dep opt llvm-link llvm-extract clang clang-offload-packager)
+    foreach(dep opt llvm-link llvm-extract clang clang-offload-packager clang-nvlink-wrapper)
       if(TARGET ${dep})
         list(APPEND extra_deps ${dep})
       endif()
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector.mir
new file mode 100644
index 0000000000000..221980ff2c42e
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector.mir
@@ -0,0 +1,282 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -O0 -mtriple=aarch64 -verify-machineinstrs -run-pass=legalizer -global-isel-abort=0 -pass-remarks-missed='gisel.*' -o - %s 2> %t.err | FileCheck %s
+# RUN: FileCheck -check-prefix=ERR %s < %t.err
+
+# ERR: remark: <unknown>:0:0: unable to legalize instruction: %{{[0-9]+}}:_(s128) = G_LOAD %{{[0-9]+}}:_(p0) :: (load (<2 x s63>)) (in function: load-narrow-scalar-high-bits)
+
+# FIXME: Scalarized stores for non-byte-sized vector elements store incorrect partial values.
+---
+name:            store-narrow-non-byte-sized
+tracksRegLiveness: true
+body:             |
+  bb.1:
+    liveins: $x8
+    ; CHECK-LABEL: name: store-narrow-non-byte-sized
+    ; CHECK: liveins: $x8
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x8
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 511
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
+    ; CHECK-NEXT: G_STORE [[TRUNC]](s16), [[COPY]](p0) :: (store (s16), align 16)
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
+    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 257
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
+    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND1]](s32)
+    ; CHECK-NEXT: G_STORE [[TRUNC1]](s16), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 1, align 1)
+    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+    ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C4]](s64)
+    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[COPY5]]
+    ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[AND2]](s32)
+    ; CHECK-NEXT: G_STORE [[TRUNC2]](s16), [[PTR_ADD1]](p0) :: (store (s16) into unknown-address + 2)
+    ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
+    ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C5]](s64)
+    ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[COPY7]]
+    ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[AND3]](s32)
+    ; CHECK-NEXT: G_STORE [[TRUNC3]](s16), [[PTR_ADD2]](p0) :: (store (s16) into unknown-address + 3, align 1)
+    ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+    ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C6]](s64)
+    ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[COPY9]]
+    ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[AND4]](s32)
+    ; CHECK-NEXT: G_STORE [[TRUNC4]](s16), [[PTR_ADD3]](p0) :: (store (s16) into unknown-address + 4, align 4)
+    ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
+    ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C7]](s64)
+    ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[COPY11]]
+    ; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[AND5]](s32)
+    ; CHECK-NEXT: G_STORE [[TRUNC5]](s16), [[PTR_ADD4]](p0) :: (store (s16) into unknown-address + 5, align 1)
+    ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
+    ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C8]](s64)
+    ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[C]], [[COPY12]]
+    ; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[AND6]](s32)
+    ; CHECK-NEXT: G_STORE [[TRUNC6]](s16), [[PTR_ADD5]](p0) :: (store (s16) into unknown-address + 6)
+    ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
+    ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C9]](s64)
+    ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[C3]], [[COPY13]]
+    ; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[AND7]](s32)
+    ; CHECK-NEXT: G_STORE [[TRUNC7]](s16), [[PTR_ADD6]](p0) :: (store (s16) into unknown-address + 7, align 1)
+    ; CHECK-NEXT: RET_ReallyLR
+    %0:_(p0) = COPY $x8
+    %1:_(s9) = G_CONSTANT i9 256
+    %2:_(s9) = G_CONSTANT i9 257
+    %3:_(<8 x s9>) = G_BUILD_VECTOR %1(s9), %2(s9), %1(s9), %2(s9), %1(s9), %2(s9), %1(s9), %2(s9)
+    G_STORE %3(<8 x s9>), %0(p0) :: (store (<8 x s9>), align 16)
+    RET_ReallyLR
+...
+
+# FIXME: Vector stores only sometimes act as per-lane truncating stores (see e.g. PR#121169).
+---
+name:            store-narrow-per-lane-trunc
+tracksRegLiveness: true
+body:             |
+  bb.1:
+    liveins: $x8
+    ; CHECK-LABEL: name: store-narrow-per-lane-trunc
+    ; CHECK: liveins: $x8
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x8
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
+    ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
+    ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>))
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64)
+    ; CHECK-NEXT: G_STORE [[BUILD_VECTOR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
+    ; CHECK-NEXT: RET_ReallyLR
+    %0:_(p0) = COPY $x8
+    %1:_(s64) = G_CONSTANT i64 42
+    %2:_(<4 x s64>) = G_BUILD_VECTOR %1(s64), %1(s64), %1(s64), %1(s64)
+    G_STORE %2(<4 x s64>), %0(p0) :: (store (<4 x s63>), align 16)
+    RET_ReallyLR
+...
+
+# FIXME: Clarify behavior of stores between scalar and vector types in documentation. Should we consider this malformed?
+---
+name:            store-narrow-vector-high-bits
+tracksRegLiveness: true
+body:             |
+  bb.1:
+    liveins: $x8
+    ; CHECK-LABEL: name: store-narrow-vector-high-bits
+    ; CHECK: liveins: $x8
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x8
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
+    ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
+    ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>))
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64)
+    ; CHECK-NEXT: G_STORE [[BUILD_VECTOR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
+    ; CHECK-NEXT: RET_ReallyLR
+    %0:_(p0) = COPY $x8
+    %1:_(s64) = G_CONSTANT i64 42
+    %2:_(<4 x s64>) = G_BUILD_VECTOR %1(s64), %1(s64), %1(s64), %1(s64)
+    G_STORE %2(<4 x s64>), %0(p0) :: (store (s252), align 16)
+    RET_ReallyLR
+...
+---
+name:            store-narrow-scalar-high-bits
+tracksRegLiveness: true
+body:             |
+  bb.1:
+    liveins: $x8
+    ; CHECK-LABEL: name: store-narrow-scalar-high-bits
+    ; CHECK: liveins: $x8
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x8
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+    ; CHECK-NEXT: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s64), align 16)
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
+    ; CHECK-NEXT: G_STORE [[C1]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
+    ; CHECK-NEXT: RET_ReallyLR
+    %0:_(p0) = COPY $x8
+    %1:_(s128) = G_CONSTANT i128 42
+    G_STORE %1(s128), %0(p0) :: (store (<2 x s63>), align 16)
+    RET_ReallyLR
+...
+
+
+# FIXME: Scalarized loads for non-byte-sized vector elements load incorrect partial values.
+---
+name:            load-narrow-non-byte-sized
+tracksRegLiveness: true
+body:             |
+  bb.1:
+    liveins: $x8
+    ; CHECK-LABEL: name: load-narrow-non-byte-sized
+    ; CHECK: liveins: $x8
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x8
+    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16), align 16)
+    ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s16) = G_ASSERT_ZEXT [[LOAD]], 9
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
+    ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 1, align 1)
+    ; CHECK-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s16) = G_ASSERT_ZEXT [[LOAD1]], 9
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+    ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64)
+    ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD1]](p0) :: (load (s16) from unknown-address + 2)
+    ; CHECK-NEXT: [[ASSERT_ZEXT2:%[0-9]+]]:_(s16) = G_ASSERT_ZEXT [[LOAD2]], 9
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
+    ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
+    ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD2]](p0) :: (load (s16) from unknown-address + 3, align 1)
+    ; CHECK-NEXT: [[ASSERT_ZEXT3:%[0-9]+]]:_(s16) = G_ASSERT_ZEXT [[LOAD3]], 9
+    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+    ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C3]](s64)
+    ; CHECK-NEXT: [[LOAD4:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD3]](p0) :: (load (s16) from unknown-address + 4, align 4)
+    ; CHECK-NEXT: [[ASSERT_ZEXT4:%[0-9]+]]:_(s16) = G_ASSERT_ZEXT [[LOAD4]], 9
+    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
+    ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C4]](s64)
+    ; CHECK-NEXT: [[LOAD5:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD4]](p0) :: (load (s16) from unknown-address + 5, align 1)
+    ; CHECK-NEXT: [[ASSERT_ZEXT5:%[0-9]+]]:_(s16) = G_ASSERT_ZEXT [[LOAD5]], 9
+    ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
+    ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C5]](s64)
+    ; CHECK-NEXT: [[LOAD6:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD5]](p0) :: (load (s16) from unknown-address + 6)
+    ; CHECK-NEXT: [[ASSERT_ZEXT6:%[0-9]+]]:_(s16) = G_ASSERT_ZEXT [[LOAD6]], 9
+    ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
+    ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C6]](s64)
+    ; CHECK-NEXT: [[LOAD7:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD6]](p0) :: (load (s16) from unknown-address + 7, align 1)
+    ; CHECK-NEXT: [[ASSERT_ZEXT7:%[0-9]+]]:_(s16) = G_ASSERT_ZEXT [[LOAD7]], 9
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[ASSERT_ZEXT]](s16), [[ASSERT_ZEXT1]](s16), [[ASSERT_ZEXT2]](s16), [[ASSERT_ZEXT3]](s16), [[ASSERT_ZEXT4]](s16), [[ASSERT_ZEXT5]](s16), [[ASSERT_ZEXT6]](s16), [[ASSERT_ZEXT7]](s16)
+    ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 511
+    ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C7]](s16), [[C7]](s16), [[C7]](s16), [[C7]](s16), [[C7]](s16), [[C7]](s16), [[C7]](s16), [[C7]](s16)
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<8 x s16>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR1]]
+    ; CHECK-NEXT: $q0 = COPY [[AND]](<8 x s16>)
+    ; CHECK-NEXT: RET_ReallyLR implicit $q0
+    %0:_(p0) = COPY $x8
+    %2:_(<8 x s9>) = G_LOAD %0(p0) :: (load (<8 x s9>), align 16)
+    %3:_(<8 x s16>) = G_ZEXT %2(<8 x s9>)
+    $q0 = COPY %3(<8 x s16>)
+    RET_ReallyLR implicit $q0
+...
+
+# FIXME: Vector stores sometimes act as per-lane truncating stores (see PR#121169). If we want to keep these semantics we should change the semantics of G_LOAD to behave as a per-lane extending load.
+---
+name:            load-narrow-per-lane-ext
+tracksRegLiveness: true
+body:             |
+  bb.1:
+    liveins: $x8
+    ; CHECK-LABEL: name: load-narrow-per-lane-ext
+    ; CHECK: liveins: $x8
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x8
+    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>))
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
+    ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
+    ; CHECK-NEXT: $q0 = COPY [[LOAD]](<2 x s64>)
+    ; CHECK-NEXT: $q1 = COPY [[LOAD1]](<2 x s64>)
+    ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
+    %0:_(p0) = COPY $x8
+    %2:_(<4 x s64>) = G_LOAD %0(p0) :: (load (<4 x s63>), align 16)
+    %3:_(<2 x s64>), %4:_(<2 x s64>) = G_UNMERGE_VALUES %2(<4 x s64>)
+    $q0 = COPY %3(<2 x s64>)
+    $q1 = COPY %4(<2 x s64>)
+    RET_ReallyLR implicit $q0, implicit $q1
+...
+
+# FIXME: Clarify behavior of loads between scalar and vector types in documentation. Should we consider this malformed?
+---
+name:            load-narrow-vector-high-bits
+tracksRegLiveness: true
+body:             |
+  bb.1:
+    liveins: $x8
+    ; CHECK-LABEL: name: load-narrow-vector-high-bits
+    ; CHECK: liveins: $x8
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x8
+    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>))
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
+    ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[PTR_ADD]](p0) :: (load (<2 x s64>) from unknown-address + 16)
+    ; CHECK-NEXT: $q0 = COPY [[LOAD]](<2 x s64>)
+    ; CHECK-NEXT: $q1 = COPY [[LOAD1]](<2 x s64>)
+    ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
+    %0:_(p0) = COPY $x8
+    %2:_(<4 x s64>) = G_LOAD %0(p0) :: (load (s252), align 16)
+    %3:_(<2 x s64>), %4:_(<2 x s64>) = G_UNMERGE_VALUES %2(<4 x s64>)
+    $q0 = COPY %3(<2 x s64>)
+    $q1 = COPY %4(<2 x s64>)
+    RET_ReallyLR implicit $q0, implicit $q1
+...
+---
+name:            load-narrow-scalar-high-bits
+tracksRegLiveness: true
+body:             |
+  bb.1:
+    liveins: $x8
+    ; CHECK-LABEL: name: load-narrow-scalar-high-bits
+    ; CHECK: liveins: $x8
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x8
+    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load (<2 x s63>))
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)
+    ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
+    ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
+    ; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
+    %0:_(p0) = COPY $x8
+    %2:_(s128) = G_LOAD %0(p0) :: (load (<2 x s63>), align 16)
+    %3:_(s64), %4:_(s64) = G_UNMERGE_VALUES %2(s128)
+    $x0 = COPY %3(s64)
+    $x1 = COPY %4(s64)
+    RET_ReallyLR implicit $x0, implicit $x1
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/lower-neon-vector-fcmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/lower-neon-vector-fcmp.mir
index 1f5fb892df582..591dafc1ad098 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/lower-neon-vector-fcmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/lower-neon-vector-fcmp.mir
@@ -37,8 +37,10 @@ body:             |
     ; CHECK: liveins: $q0, $q1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
-    ; CHECK-NEXT: [[FCMEQZ:%[0-9]+]]:_(<2 x s64>) = G_FCMEQZ %lhs
-    ; CHECK-NEXT: $q0 = COPY [[FCMEQZ]](<2 x s64>)
+    ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
+    ; CHECK-NEXT: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
+    ; CHECK-NEXT: [[FCMEQ:%[0-9]+]]:_(<2 x s64>) = G_FCMEQ %lhs, %zero_vec(<2 x s64>)
+    ; CHECK-NEXT: $q0 = COPY [[FCMEQ]](<2 x s64>)
     ; CHECK-NEXT: RET_ReallyLR implicit $q0
     %lhs:_(<2 x s64>) = COPY $q0
     %zero:_(s64) = G_CONSTANT i64 0
@@ -82,8 +84,10 @@ body:             |
     ; CHECK: liveins: $q0, $q1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
-    ; CHECK-NEXT: [[FCMGTZ:%[0-9]+]]:_(<2 x s64>) = G_FCMGTZ %lhs
-    ; CHECK-NEXT: $q0 = COPY [[FCMGTZ]](<2 x s64>)
+    ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
+    ; CHECK-NEXT: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
+    ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %lhs, %zero_vec(<2 x s64>)
+    ; CHECK-NEXT: $q0 = COPY [[FCMGT]](<2 x s64>)
     ; CHECK-NEXT: RET_ReallyLR implicit $q0
     %lhs:_(<2 x s64>) = COPY $q0
     %zero:_(s64) = G_CONSTANT i64 0
@@ -129,8 +133,10 @@ body:             |
     ; CHECK: liveins: $q0, $q1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
-    ; CHECK-NEXT: [[FCMGEZ:%[0-9]+]]:_(<2 x s64>) = G_FCMGEZ %lhs
-    ; CHECK-NEXT: $q0 = COPY [[FCMGEZ]](<2 x s64>)
+    ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
+    ; CHECK-NEXT: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
+    ; CHECK-NEXT: [[FCMGE:%[0-9]+]]:_(<2 x s64>) = G_FCMGE %lhs, %zero_vec(<2 x s64>)
+    ; CHECK-NEXT: $q0 = COPY [[FCMGE]](<2 x s64>)
     ; CHECK-NEXT: RET_ReallyLR implicit $q0
     %lhs:_(<2 x s64>) = COPY $q0
     %zero:_(s64) = G_CONSTANT i64 0
@@ -174,8 +180,10 @@ body:             |
     ; CHECK: liveins: $q0, $q1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
-    ; CHECK-NEXT: [[FCMLTZ:%[0-9]+]]:_(<2 x s64>) = G_FCMLTZ %lhs
-    ; CHECK-NEXT: $q0 = COPY [[FCMLTZ]](<2 x s64>)
+    ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
+    ; CHECK-NEXT: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
+    ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %zero_vec, %lhs(<2 x s64>)
+    ; CHECK-NEXT: $q0 = COPY [[FCMGT]](<2 x s64>)
     ; CHECK-NEXT: RET_ReallyLR implicit $q0
     %lhs:_(<2 x s64>) = COPY $q0
     %zero:_(s64) = G_CONSTANT i64 0
@@ -218,8 +226,10 @@ body:             |
     ; CHECK: liveins: $q0, $q1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
-    ; CHECK-NEXT: [[FCMLEZ:%[0-9]+]]:_(<2 x s64>) = G_FCMLEZ %lhs
-    ; CHECK-NEXT: $q0 = COPY [[FCMLEZ]](<2 x s64>)
+    ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
+    ; CHECK-NEXT: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
+    ; CHECK-NEXT: [[FCMGE:%[0-9]+]]:_(<2 x s64>) = G_FCMGE %zero_vec, %lhs(<2 x s64>)
+    ; CHECK-NEXT: $q0 = COPY [[FCMGE]](<2 x s64>)
     ; CHECK-NEXT: RET_ReallyLR implicit $q0
     %lhs:_(<2 x s64>) = COPY $q0
     %zero:_(s64) = G_CONSTANT i64 0
@@ -270,9 +280,11 @@ body:             |
     ; CHECK: liveins: $q0, $q1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
-    ; CHECK-NEXT: [[FCMGTZ:%[0-9]+]]:_(<2 x s64>) = G_FCMGTZ %lhs
-    ; CHECK-NEXT: [[FCMLTZ:%[0-9]+]]:_(<2 x s64>) = G_FCMLTZ %lhs
-    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[FCMLTZ]], [[FCMGTZ]]
+    ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
+    ; CHECK-NEXT: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
+    ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %lhs, %zero_vec(<2 x s64>)
+    ; CHECK-NEXT: [[FCMGT1:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %zero_vec, %lhs(<2 x s64>)
+    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[FCMGT1]], [[FCMGT]]
     ; CHECK-NEXT: $q0 = COPY [[OR]](<2 x s64>)
     ; CHECK-NEXT: RET_ReallyLR implicit $q0
     %lhs:_(<2 x s64>) = COPY $q0
@@ -434,10 +446,12 @@ body:             |
     ; CHECK: liveins: $q0, $q1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
-    ; CHECK-NEXT: [[FCMGEZ:%[0-9]+]]:_(<2 x s64>) = G_FCMGEZ %lhs
+    ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
+    ; CHECK-NEXT: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
+    ; CHECK-NEXT: [[FCMGE:%[0-9]+]]:_(<2 x s64>) = G_FCMGE %lhs, %zero_vec(<2 x s64>)
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
     ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
-    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMGEZ]], [[BUILD_VECTOR]]
+    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMGE]], [[BUILD_VECTOR]]
     ; CHECK-NEXT: $q0 = COPY [[XOR]](<2 x s64>)
     ; CHECK-NEXT: RET_ReallyLR implicit $q0
     %lhs:_(<2 x s64>) = COPY $q0
@@ -490,10 +504,12 @@ body:             |
     ; CHECK: liveins: $q0, $q1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
-    ; CHECK-NEXT: [[FCMGTZ:%[0-9]+]]:_(<2 x s64>) = G_FCMGTZ %lhs
+    ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
+    ; CHECK-NEXT: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
+    ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %lhs, %zero_vec(<2 x s64>)
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
     ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
-    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMGTZ]], [[BUILD_VECTOR]]
+    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMGT]], [[BUILD_VECTOR]]
     ; CHECK-NEXT: $q0 = COPY [[XOR]](<2 x s64>)
     ; CHECK-NEXT: RET_ReallyLR implicit $q0
     %lhs:_(<2 x s64>) = COPY $q0
@@ -546,10 +562,12 @@ body:             |
     ; CHECK: liveins: $q0, $q1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
-    ; CHECK-NEXT: [[FCMLEZ:%[0-9]+]]:_(<2 x s64>) = G_FCMLEZ %lhs
+    ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
+    ; CHECK-NEXT: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
+    ; CHECK-NEXT: [[FCMGE:%[0-9]+]]:_(<2 x s64>) = G_FCMGE %zero_vec, %lhs(<2 x s64>)
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
     ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
-    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMLEZ]], [[BUILD_VECTOR]]
+    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMGE]], [[BUILD_VECTOR]]
     ; CHECK-NEXT: $q0 = COPY [[XOR]](<2 x s64>)
     ; CHECK-NEXT: RET_ReallyLR implicit $q0
     %lhs:_(<2 x s64>) = COPY $q0
@@ -602,10 +620,12 @@ body:             |
     ; CHECK: liveins: $q0, $q1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
-    ; CHECK-NEXT: [[FCMLTZ:%[0-9]+]]:_(<2 x s64>) = G_FCMLTZ %lhs
+    ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
+    ; CHECK-NEXT: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
+    ; CHECK-NEXT: [[FCMGT:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %zero_vec, %lhs(<2 x s64>)
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
     ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
-    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMLTZ]], [[BUILD_VECTOR]]
+    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMGT]], [[BUILD_VECTOR]]
     ; CHECK-NEXT: $q0 = COPY [[XOR]](<2 x s64>)
     ; CHECK-NEXT: RET_ReallyLR implicit $q0
     %lhs:_(<2 x s64>) = COPY $q0
@@ -658,10 +678,12 @@ body:             |
     ; CHECK: liveins: $q0, $q1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %lhs:_(<2 x s64>) = COPY $q0
-    ; CHECK-NEXT: [[FCMEQZ:%[0-9]+]]:_(<2 x s64>) = G_FCMEQZ %lhs
+    ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
+    ; CHECK-NEXT: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
+    ; CHECK-NEXT: [[FCMEQ:%[0-9]+]]:_(<2 x s64>) = G_FCMEQ %lhs, %zero_vec(<2 x s64>)
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
     ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
-    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMEQZ]], [[BUILD_VECTOR]]
+    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMEQ]], [[BUILD_VECTOR]]
     ; CHECK-NEXT: $q0 = COPY [[XOR]](<2 x s64>)
     ; CHECK-NEXT: RET_ReallyLR implicit $q0
     %lhs:_(<2 x s64>) = COPY $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-const-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-const-vector.mir
index 038c214a268d8..34ac115640814 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-const-vector.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-const-vector.mir
@@ -17,11 +17,12 @@ body:             |
 
     ; CHECK-LABEL: name: test_constant_vec_pool_v2f64
     ; CHECK: liveins: $x0
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
-    ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
-    ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
-    ; CHECK: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<2 x s64>))
-    ; CHECK: RET_ReallyLR
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
+    ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool)
+    ; CHECK-NEXT: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<2 x s64>))
+    ; CHECK-NEXT: RET_ReallyLR
     %0:gpr(p0) = COPY $x0
     %3:fpr(s64) = G_FCONSTANT double 5.000000e-01
     %2:fpr(s64) = G_FCONSTANT double 1.600000e+01
@@ -46,11 +47,12 @@ body:             |
 
     ; CHECK-LABEL: name: test_constant_vec_pool_v4f32
     ; CHECK: liveins: $x0
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
-    ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
-    ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
-    ; CHECK: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<4 x s32>))
-    ; CHECK: RET_ReallyLR
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
+    ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool)
+    ; CHECK-NEXT: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<4 x s32>))
+    ; CHECK-NEXT: RET_ReallyLR
     %0:gpr(p0) = COPY $x0
     %3:fpr(s32) = G_FCONSTANT float 5.000000e-01
     %2:fpr(s32) = G_FCONSTANT float 1.600000e+01
@@ -75,11 +77,12 @@ body:             |
 
     ; CHECK-LABEL: name: test_constant_vec_pool_v2i64
     ; CHECK: liveins: $x0
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
-    ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
-    ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
-    ; CHECK: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<2 x s64>))
-    ; CHECK: RET_ReallyLR
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
+    ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool)
+    ; CHECK-NEXT: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<2 x s64>))
+    ; CHECK-NEXT: RET_ReallyLR
     %0:gpr(p0) = COPY $x0
     %3:gpr(s64) = G_CONSTANT i64 67839
     %2:gpr(s64) = G_CONSTANT i64 12375
@@ -104,11 +107,12 @@ body:             |
 
     ; CHECK-LABEL: name: test_constant_vec_pool_v4i32
     ; CHECK: liveins: $x0
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
-    ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
-    ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
-    ; CHECK: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<4 x s32>))
-    ; CHECK: RET_ReallyLR
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
+    ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool)
+    ; CHECK-NEXT: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<4 x s32>))
+    ; CHECK-NEXT: RET_ReallyLR
     %0:gpr(p0) = COPY $x0
     %3:gpr(s32) = G_CONSTANT i32 67839
     %2:gpr(s32) = G_CONSTANT i32 12375
@@ -134,11 +138,12 @@ body:             |
 
     ; CHECK-LABEL: name: test_constant_vec_pool_v2i32
     ; CHECK: liveins: $x0
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
-    ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
-    ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
-    ; CHECK: STRDui [[LDRDui]], [[COPY]], 0 :: (store (<2 x s32>))
-    ; CHECK: RET_ReallyLR
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
+    ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s64) from constant-pool)
+    ; CHECK-NEXT: STRDui [[LDRDui]], [[COPY]], 0 :: (store (<2 x s32>))
+    ; CHECK-NEXT: RET_ReallyLR
     %0:gpr(p0) = COPY $x0
     %3:gpr(s32) = G_CONSTANT i32 67839
     %2:gpr(s32) = G_CONSTANT i32 12375
@@ -147,3 +152,59 @@ body:             |
     RET_ReallyLR
 
 ...
+---
+name:            test_constant_all_zeros_v4f32
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+liveins:
+  - { reg: '$x0' }
+frameInfo:
+  maxAlignment:    1
+body:             |
+  bb.1:
+    liveins: $x0
+
+    ; CHECK-LABEL: name: test_constant_all_zeros_v4f32
+    ; CHECK: liveins: $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0
+    ; CHECK-NEXT: STRQui [[MOVIv2d_ns]], [[COPY]], 0 :: (store (<4 x s32>))
+    ; CHECK-NEXT: RET_ReallyLR
+    %0:gpr(p0) = COPY $x0
+    %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
+    %1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %2(s32), %2(s32), %2(s32)
+    G_STORE %1(<4 x s32>), %0(p0) :: (store (<4 x s32>))
+    RET_ReallyLR
+
+...
+---
+name:            test_constant_all_ones_v4f32
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+liveins:
+  - { reg: '$x0' }
+frameInfo:
+  maxAlignment:    1
+body:             |
+  bb.1:
+    liveins: $x0
+
+    ; CHECK-LABEL: name: test_constant_all_ones_v4f32
+    ; CHECK: liveins: $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 255
+    ; CHECK-NEXT: STRQui [[MOVIv2d_ns]], [[COPY]], 0 :: (store (<4 x s32>))
+    ; CHECK-NEXT: RET_ReallyLR
+    %0:gpr(p0) = COPY $x0
+    %2:fpr(s32) = G_FCONSTANT float 0xFFFFFFFFE0000000
+    %1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %2(s32), %2(s32), %2(s32)
+    G_STORE %1(<4 x s32>), %0(p0) :: (store (<4 x s32>))
+    RET_ReallyLR
+
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir
index 0b0c3ed763abc..daf84b5cf07e9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir
@@ -77,7 +77,7 @@ body:             |
     %lhs:fpr(<2 x s64>) = COPY $q0
     %zero:gpr(s64) = G_CONSTANT i64 0
     %zero_vec:fpr(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
-    %fcmp:fpr(<2 x s64>) = G_FCMEQZ %lhs
+    %fcmp:fpr(<2 x s64>) = G_FCMEQ %lhs, %zero_vec(<2 x s64>)
     $q0 = COPY %fcmp(<2 x s64>)
     RET_ReallyLR implicit $q0
 
@@ -97,7 +97,7 @@ body:             |
     %lhs:fpr(<2 x s64>) = COPY $q0
     %zero:gpr(s64) = G_CONSTANT i64 0
     %zero_vec:fpr(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
-    %fcmp:fpr(<2 x s64>) = G_FCMGEZ %lhs
+    %fcmp:fpr(<2 x s64>) = G_FCMGE %lhs, %zero_vec(<2 x s64>)
     $q0 = COPY %fcmp(<2 x s64>)
     RET_ReallyLR implicit $q0
 
@@ -117,7 +117,7 @@ body:             |
     %lhs:fpr(<2 x s64>) = COPY $q0
     %zero:gpr(s64) = G_CONSTANT i64 0
     %zero_vec:fpr(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
-    %fcmp:fpr(<2 x s64>) = G_FCMGTZ %lhs
+    %fcmp:fpr(<2 x s64>) = G_FCMGT %lhs, %zero_vec(<2 x s64>)
     $q0 = COPY %fcmp(<2 x s64>)
     RET_ReallyLR implicit $q0
 
@@ -137,7 +137,7 @@ body:             |
     %lhs:fpr(<2 x s64>) = COPY $q0
     %zero:gpr(s64) = G_CONSTANT i64 0
     %zero_vec:fpr(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
-    %fcmp:fpr(<2 x s64>) = G_FCMLEZ %lhs
+    %fcmp:fpr(<2 x s64>) = G_FCMGE %zero_vec(<2 x s64>), %lhs
     $q0 = COPY %fcmp(<2 x s64>)
     RET_ReallyLR implicit $q0
 
@@ -157,6 +157,6 @@ body:             |
     %lhs:fpr(<2 x s64>) = COPY $q0
     %zero:gpr(s64) = G_CONSTANT i64 0
     %zero_vec:fpr(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
-    %fcmp:fpr(<2 x s64>) = G_FCMLTZ %lhs
+    %fcmp:fpr(<2 x s64>) = G_FCMGT %zero_vec(<2 x s64>), %lhs
     $q0 = COPY %fcmp(<2 x s64>)
     RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/arm64-tbl.ll b/llvm/test/CodeGen/AArch64/arm64-tbl.ll
index a854cb7fec991..fe5a6f12a49c3 100644
--- a/llvm/test/CodeGen/AArch64/arm64-tbl.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-tbl.ll
@@ -1254,6 +1254,36 @@ define <16 x i8> @tbx4_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %
   ret <16 x i8> %tmp3
 }
 
+define <16 x i8> @pr135950(<16 x i8> %A, <16 x i8> %B, <16 x i8> %M) {
+; CHECK-SD-LABEL: pr135950:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov.16b v3, v1
+; CHECK-SD-NEXT:    movi.2d v1, #0000000000000000
+; CHECK-SD-NEXT:    mov.16b v4, v0
+; CHECK-SD-NEXT:    mov.16b v5, v3
+; CHECK-SD-NEXT:    tbl.16b v1, { v3, v4 }, v1
+; CHECK-SD-NEXT:    tbl.16b v0, { v4, v5 }, v2
+; CHECK-SD-NEXT:    zip1.16b v0, v0, v1
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: pr135950:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    // kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2
+; CHECK-GI-NEXT:    mov.16b v3, v2
+; CHECK-GI-NEXT:    movi.2d v4, #0000000000000000
+; CHECK-GI-NEXT:    // kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2
+; CHECK-GI-NEXT:    tbl.16b v3, { v0, v1 }, v3
+; CHECK-GI-NEXT:    mov.16b v2, v0
+; CHECK-GI-NEXT:    tbl.16b v0, { v1, v2 }, v4
+; CHECK-GI-NEXT:    zip1.16b v0, v3, v0
+; CHECK-GI-NEXT:    ret
+  %t1 = call <16 x i8> @llvm.aarch64.neon.tbl2.v16i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %M)
+  %t2 = call <16 x i8> @llvm.aarch64.neon.tbl2.v16i8(<16 x i8> %B, <16 x i8> %A, <16 x i8> zeroinitializer)
+  %s = shufflevector <16 x i8> %t1, <16 x i8> %t2, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
+  ret <16 x i8> %s
+}
+
+
 declare <8 x i8> @llvm.aarch64.neon.tbx1.v8i8(<8 x i8>, <16 x i8>, <8 x i8>) nounwind readnone
 declare <16 x i8> @llvm.aarch64.neon.tbx1.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
 declare <8 x i8> @llvm.aarch64.neon.tbx2.v8i8(<8 x i8>, <16 x i8>, <16 x i8>, <8 x i8>) nounwind readnone
diff --git a/llvm/test/CodeGen/AArch64/arm64-zip.ll b/llvm/test/CodeGen/AArch64/arm64-zip.ll
index 9955b253f563e..b24e54a68fb42 100644
--- a/llvm/test/CodeGen/AArch64/arm64-zip.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-zip.ll
@@ -405,8 +405,7 @@ define <16 x i8> @combine_v8i16_8firstundef(<8 x i8> %0, <8 x i8> %1) {
 define <4 x float> @shuffle_zip1(<4 x float> %arg) {
 ; CHECK-LABEL: shuffle_zip1:
 ; CHECK:       // %bb.0: // %bb
-; CHECK-NEXT:    movi.2d v1, #0000000000000000
-; CHECK-NEXT:    fcmgt.4s v0, v0, v1
+; CHECK-NEXT:    fcmgt.4s v0, v0, #0.0
 ; CHECK-NEXT:    uzp1.8h v1, v0, v0
 ; CHECK-NEXT:    xtn.4h v0, v0
 ; CHECK-NEXT:    xtn.4h v1, v1
diff --git a/llvm/test/CodeGen/AArch64/fsh.ll b/llvm/test/CodeGen/AArch64/fsh.ll
index 2cee2f2b2686c..e29f35cfc2173 100644
--- a/llvm/test/CodeGen/AArch64/fsh.ll
+++ b/llvm/test/CodeGen/AArch64/fsh.ll
@@ -4506,3 +4506,53 @@ entry:
   %d = call <2 x i128> @llvm.fshr(<2 x i128> %a, <2 x i128> %b, <2 x i128> <i128 3, i128 3>)
   ret <2 x i128> %d
 }
+
+
+
+define <2 x i64> @fshl_to_rev2i64(<2 x i64> %r) {
+; CHECK-SD-LABEL: fshl_to_rev2i64:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    rev64 v0.4s, v0.4s
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: fshl_to_rev2i64:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    shl v1.2d, v0.2d, #32
+; CHECK-GI-NEXT:    ushr v0.2d, v0.2d, #32
+; CHECK-GI-NEXT:    orr v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT:    ret
+    %or = tail call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %r, <2 x i64> %r, <2 x i64> splat (i64 32))
+    ret <2 x i64> %or
+}
+
+define <4 x i32> @fshl_to_rev4i32(<4 x i32> %r) {
+; CHECK-SD-LABEL: fshl_to_rev4i32:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    rev32 v0.8h, v0.8h
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: fshl_to_rev4i32:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    shl v1.4s, v0.4s, #16
+; CHECK-GI-NEXT:    ushr v0.4s, v0.4s, #16
+; CHECK-GI-NEXT:    orr v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT:    ret
+    %or = tail call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %r, <4 x i32> %r, <4 x i32> splat (i32 16))
+    ret <4 x i32> %or
+}
+
+define <2 x i32> @fshl_to_rev2i32(<2 x i32> %r) {
+; CHECK-SD-LABEL: fshl_to_rev2i32:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    rev32 v0.4h, v0.4h
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: fshl_to_rev2i32:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    shl v1.2s, v0.2s, #16
+; CHECK-GI-NEXT:    ushr v0.2s, v0.2s, #16
+; CHECK-GI-NEXT:    orr v0.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT:    ret
+    %or = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %r, <2 x i32> %r, <2 x i32> splat (i32 16))
+    ret <2 x i32> %or
+}
diff --git a/llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll b/llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
index c48ebbad4fe21..9e305056abce2 100644
--- a/llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
+++ b/llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
@@ -12,15 +12,13 @@ define <4 x i32> @udot(<4 x i32> %acc, <16 x i8> %u, <16 x i8> %s) {
 ;
 ; CHECK-NODOT-LABEL: udot:
 ; CHECK-NODOT:       // %bb.0:
-; CHECK-NODOT-NEXT:    ushll v3.8h, v1.8b, #0
-; CHECK-NODOT-NEXT:    ushll v4.8h, v2.8b, #0
-; CHECK-NODOT-NEXT:    ushll2 v1.8h, v1.16b, #0
-; CHECK-NODOT-NEXT:    ushll2 v2.8h, v2.16b, #0
-; CHECK-NODOT-NEXT:    umlal v0.4s, v4.4h, v3.4h
-; CHECK-NODOT-NEXT:    umull v5.4s, v2.4h, v1.4h
-; CHECK-NODOT-NEXT:    umlal2 v0.4s, v2.8h, v1.8h
-; CHECK-NODOT-NEXT:    umlal2 v5.4s, v4.8h, v3.8h
-; CHECK-NODOT-NEXT:    add v0.4s, v5.4s, v0.4s
+; CHECK-NODOT-NEXT:    umull v3.8h, v2.8b, v1.8b
+; CHECK-NODOT-NEXT:    umull2 v1.8h, v2.16b, v1.16b
+; CHECK-NODOT-NEXT:    ushll v2.4s, v1.4h, #0
+; CHECK-NODOT-NEXT:    uaddw v0.4s, v0.4s, v3.4h
+; CHECK-NODOT-NEXT:    uaddw2 v2.4s, v2.4s, v3.8h
+; CHECK-NODOT-NEXT:    uaddw2 v0.4s, v0.4s, v1.8h
+; CHECK-NODOT-NEXT:    add v0.4s, v2.4s, v0.4s
 ; CHECK-NODOT-NEXT:    ret
   %u.wide = zext <16 x i8> %u to <16 x i32>
   %s.wide = zext <16 x i8> %s to <16 x i32>
@@ -52,20 +50,18 @@ define <4 x i32> @udot_in_loop(ptr %p1, ptr %p2){
 ; CHECK-NODOT-NEXT:    mov x8, xzr
 ; CHECK-NODOT-NEXT:  .LBB1_1: // %vector.body
 ; CHECK-NODOT-NEXT:    // =>This Inner Loop Header: Depth=1
-; CHECK-NODOT-NEXT:    ldr q0, [x1, x8]
-; CHECK-NODOT-NEXT:    ldr q2, [x0, x8]
+; CHECK-NODOT-NEXT:    ldr q0, [x0, x8]
+; CHECK-NODOT-NEXT:    ldr q2, [x1, x8]
 ; CHECK-NODOT-NEXT:    add x8, x8, #16
 ; CHECK-NODOT-NEXT:    cmp x8, #16
-; CHECK-NODOT-NEXT:    ushll2 v3.8h, v0.16b, #0
-; CHECK-NODOT-NEXT:    ushll2 v4.8h, v2.16b, #0
-; CHECK-NODOT-NEXT:    ushll v5.8h, v0.8b, #0
-; CHECK-NODOT-NEXT:    ushll v2.8h, v2.8b, #0
+; CHECK-NODOT-NEXT:    umull v3.8h, v0.8b, v2.8b
+; CHECK-NODOT-NEXT:    umull2 v2.8h, v0.16b, v2.16b
 ; CHECK-NODOT-NEXT:    mov v0.16b, v1.16b
-; CHECK-NODOT-NEXT:    umull v6.4s, v4.4h, v3.4h
-; CHECK-NODOT-NEXT:    umlal v1.4s, v2.4h, v5.4h
-; CHECK-NODOT-NEXT:    umlal2 v6.4s, v2.8h, v5.8h
-; CHECK-NODOT-NEXT:    umlal2 v1.4s, v4.8h, v3.8h
-; CHECK-NODOT-NEXT:    add v1.4s, v6.4s, v1.4s
+; CHECK-NODOT-NEXT:    ushll v1.4s, v2.4h, #0
+; CHECK-NODOT-NEXT:    uaddw v4.4s, v0.4s, v3.4h
+; CHECK-NODOT-NEXT:    uaddw2 v1.4s, v1.4s, v3.8h
+; CHECK-NODOT-NEXT:    uaddw2 v2.4s, v4.4s, v2.8h
+; CHECK-NODOT-NEXT:    add v1.4s, v1.4s, v2.4s
 ; CHECK-NODOT-NEXT:    b.ne .LBB1_1
 ; CHECK-NODOT-NEXT:  // %bb.2: // %end
 ; CHECK-NODOT-NEXT:    ret
@@ -99,19 +95,17 @@ define <2 x i32> @udot_narrow(<2 x i32> %acc, <8 x i8> %u, <8 x i8> %s) {
 ;
 ; CHECK-NODOT-LABEL: udot_narrow:
 ; CHECK-NODOT:       // %bb.0:
-; CHECK-NODOT-NEXT:    ushll v1.8h, v1.8b, #0
-; CHECK-NODOT-NEXT:    ushll v2.8h, v2.8b, #0
+; CHECK-NODOT-NEXT:    umull v1.8h, v2.8b, v1.8b
 ; CHECK-NODOT-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NODOT-NEXT:    umull v3.4s, v2.4h, v1.4h
-; CHECK-NODOT-NEXT:    umull2 v4.4s, v2.8h, v1.8h
-; CHECK-NODOT-NEXT:    ext v5.16b, v1.16b, v1.16b, #8
-; CHECK-NODOT-NEXT:    ext v6.16b, v2.16b, v2.16b, #8
-; CHECK-NODOT-NEXT:    umlal v0.4s, v2.4h, v1.4h
+; CHECK-NODOT-NEXT:    ushll v2.4s, v1.4h, #0
+; CHECK-NODOT-NEXT:    ushll2 v3.4s, v1.8h, #0
+; CHECK-NODOT-NEXT:    ext v4.16b, v1.16b, v1.16b, #8
+; CHECK-NODOT-NEXT:    uaddw v0.4s, v0.4s, v1.4h
 ; CHECK-NODOT-NEXT:    ext v3.16b, v3.16b, v3.16b, #8
-; CHECK-NODOT-NEXT:    ext v1.16b, v4.16b, v4.16b, #8
-; CHECK-NODOT-NEXT:    umlal v3.4s, v6.4h, v5.4h
-; CHECK-NODOT-NEXT:    add v0.2s, v1.2s, v0.2s
+; CHECK-NODOT-NEXT:    ext v2.16b, v2.16b, v2.16b, #8
 ; CHECK-NODOT-NEXT:    add v0.2s, v3.2s, v0.2s
+; CHECK-NODOT-NEXT:    uaddw v1.4s, v2.4s, v4.4h
+; CHECK-NODOT-NEXT:    add v0.2s, v1.2s, v0.2s
 ; CHECK-NODOT-NEXT:    ret
   %u.wide = zext <8 x i8> %u to <8 x i32>
   %s.wide = zext <8 x i8> %s to <8 x i32>
@@ -128,15 +122,13 @@ define <4 x i32> @sdot(<4 x i32> %acc, <16 x i8> %u, <16 x i8> %s) {
 ;
 ; CHECK-NODOT-LABEL: sdot:
 ; CHECK-NODOT:       // %bb.0:
-; CHECK-NODOT-NEXT:    sshll v3.8h, v1.8b, #0
-; CHECK-NODOT-NEXT:    sshll v4.8h, v2.8b, #0
-; CHECK-NODOT-NEXT:    sshll2 v1.8h, v1.16b, #0
-; CHECK-NODOT-NEXT:    sshll2 v2.8h, v2.16b, #0
-; CHECK-NODOT-NEXT:    smlal v0.4s, v4.4h, v3.4h
-; CHECK-NODOT-NEXT:    smull v5.4s, v2.4h, v1.4h
-; CHECK-NODOT-NEXT:    smlal2 v0.4s, v2.8h, v1.8h
-; CHECK-NODOT-NEXT:    smlal2 v5.4s, v4.8h, v3.8h
-; CHECK-NODOT-NEXT:    add v0.4s, v5.4s, v0.4s
+; CHECK-NODOT-NEXT:    smull v3.8h, v2.8b, v1.8b
+; CHECK-NODOT-NEXT:    smull2 v1.8h, v2.16b, v1.16b
+; CHECK-NODOT-NEXT:    sshll v2.4s, v1.4h, #0
+; CHECK-NODOT-NEXT:    saddw v0.4s, v0.4s, v3.4h
+; CHECK-NODOT-NEXT:    saddw2 v2.4s, v2.4s, v3.8h
+; CHECK-NODOT-NEXT:    saddw2 v0.4s, v0.4s, v1.8h
+; CHECK-NODOT-NEXT:    add v0.4s, v2.4s, v0.4s
 ; CHECK-NODOT-NEXT:    ret
   %u.wide = sext <16 x i8> %u to <16 x i32>
   %s.wide = sext <16 x i8> %s to <16 x i32>
@@ -153,19 +145,17 @@ define <2 x i32> @sdot_narrow(<2 x i32> %acc, <8 x i8> %u, <8 x i8> %s) {
 ;
 ; CHECK-NODOT-LABEL: sdot_narrow:
 ; CHECK-NODOT:       // %bb.0:
-; CHECK-NODOT-NEXT:    sshll v1.8h, v1.8b, #0
-; CHECK-NODOT-NEXT:    sshll v2.8h, v2.8b, #0
+; CHECK-NODOT-NEXT:    smull v1.8h, v2.8b, v1.8b
 ; CHECK-NODOT-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NODOT-NEXT:    smull v3.4s, v2.4h, v1.4h
-; CHECK-NODOT-NEXT:    smull2 v4.4s, v2.8h, v1.8h
-; CHECK-NODOT-NEXT:    ext v5.16b, v1.16b, v1.16b, #8
-; CHECK-NODOT-NEXT:    ext v6.16b, v2.16b, v2.16b, #8
-; CHECK-NODOT-NEXT:    smlal v0.4s, v2.4h, v1.4h
+; CHECK-NODOT-NEXT:    sshll v2.4s, v1.4h, #0
+; CHECK-NODOT-NEXT:    sshll2 v3.4s, v1.8h, #0
+; CHECK-NODOT-NEXT:    ext v4.16b, v1.16b, v1.16b, #8
+; CHECK-NODOT-NEXT:    saddw v0.4s, v0.4s, v1.4h
 ; CHECK-NODOT-NEXT:    ext v3.16b, v3.16b, v3.16b, #8
-; CHECK-NODOT-NEXT:    ext v1.16b, v4.16b, v4.16b, #8
-; CHECK-NODOT-NEXT:    smlal v3.4s, v6.4h, v5.4h
-; CHECK-NODOT-NEXT:    add v0.2s, v1.2s, v0.2s
+; CHECK-NODOT-NEXT:    ext v2.16b, v2.16b, v2.16b, #8
 ; CHECK-NODOT-NEXT:    add v0.2s, v3.2s, v0.2s
+; CHECK-NODOT-NEXT:    saddw v1.4s, v2.4s, v4.4h
+; CHECK-NODOT-NEXT:    add v0.2s, v1.2s, v0.2s
 ; CHECK-NODOT-NEXT:    ret
   %u.wide = sext <8 x i8> %u to <8 x i32>
   %s.wide = sext <8 x i8> %s to <8 x i32>
@@ -417,27 +407,19 @@ define <4 x i64> @udot_8to64(<4 x i64> %acc, <16 x i8> %a, <16 x i8> %b) {
 ;
 ; CHECK-NODOT-LABEL: udot_8to64:
 ; CHECK-NODOT:       // %bb.0: // %entry
-; CHECK-NODOT-NEXT:    ushll v4.8h, v3.8b, #0
-; CHECK-NODOT-NEXT:    ushll v5.8h, v2.8b, #0
-; CHECK-NODOT-NEXT:    ushll2 v3.8h, v3.16b, #0
-; CHECK-NODOT-NEXT:    ushll2 v2.8h, v2.16b, #0
-; CHECK-NODOT-NEXT:    ushll v6.4s, v4.4h, #0
-; CHECK-NODOT-NEXT:    ushll v7.4s, v5.4h, #0
+; CHECK-NODOT-NEXT:    umull v4.8h, v2.8b, v3.8b
+; CHECK-NODOT-NEXT:    umull2 v2.8h, v2.16b, v3.16b
+; CHECK-NODOT-NEXT:    ushll v3.4s, v4.4h, #0
+; CHECK-NODOT-NEXT:    ushll v5.4s, v2.4h, #0
 ; CHECK-NODOT-NEXT:    ushll2 v4.4s, v4.8h, #0
-; CHECK-NODOT-NEXT:    ushll2 v5.4s, v5.8h, #0
-; CHECK-NODOT-NEXT:    ushll2 v16.4s, v3.8h, #0
-; CHECK-NODOT-NEXT:    ushll2 v17.4s, v2.8h, #0
-; CHECK-NODOT-NEXT:    ushll v3.4s, v3.4h, #0
-; CHECK-NODOT-NEXT:    ushll v2.4s, v2.4h, #0
-; CHECK-NODOT-NEXT:    umlal2 v1.2d, v7.4s, v6.4s
-; CHECK-NODOT-NEXT:    umlal v0.2d, v7.2s, v6.2s
-; CHECK-NODOT-NEXT:    umull2 v18.2d, v5.4s, v4.4s
-; CHECK-NODOT-NEXT:    umull v4.2d, v5.2s, v4.2s
-; CHECK-NODOT-NEXT:    umlal2 v1.2d, v17.4s, v16.4s
-; CHECK-NODOT-NEXT:    umlal v0.2d, v17.2s, v16.2s
-; CHECK-NODOT-NEXT:    umlal2 v18.2d, v2.4s, v3.4s
-; CHECK-NODOT-NEXT:    umlal v4.2d, v2.2s, v3.2s
-; CHECK-NODOT-NEXT:    add v1.2d, v18.2d, v1.2d
+; CHECK-NODOT-NEXT:    ushll2 v2.4s, v2.8h, #0
+; CHECK-NODOT-NEXT:    uaddw2 v1.2d, v1.2d, v3.4s
+; CHECK-NODOT-NEXT:    uaddw v0.2d, v0.2d, v3.2s
+; CHECK-NODOT-NEXT:    uaddl2 v3.2d, v4.4s, v5.4s
+; CHECK-NODOT-NEXT:    uaddl v4.2d, v4.2s, v5.2s
+; CHECK-NODOT-NEXT:    uaddw2 v1.2d, v1.2d, v2.4s
+; CHECK-NODOT-NEXT:    uaddw v0.2d, v0.2d, v2.2s
+; CHECK-NODOT-NEXT:    add v1.2d, v3.2d, v1.2d
 ; CHECK-NODOT-NEXT:    add v0.2d, v4.2d, v0.2d
 ; CHECK-NODOT-NEXT:    ret
 entry:
@@ -460,27 +442,19 @@ define <4 x i64> @sdot_8to64(<4 x i64> %acc, <16 x i8> %a, <16 x i8> %b){
 ;
 ; CHECK-NODOT-LABEL: sdot_8to64:
 ; CHECK-NODOT:       // %bb.0: // %entry
-; CHECK-NODOT-NEXT:    sshll v4.8h, v3.8b, #0
-; CHECK-NODOT-NEXT:    sshll v5.8h, v2.8b, #0
-; CHECK-NODOT-NEXT:    sshll2 v3.8h, v3.16b, #0
-; CHECK-NODOT-NEXT:    sshll2 v2.8h, v2.16b, #0
-; CHECK-NODOT-NEXT:    sshll v6.4s, v4.4h, #0
-; CHECK-NODOT-NEXT:    sshll v7.4s, v5.4h, #0
+; CHECK-NODOT-NEXT:    smull v4.8h, v2.8b, v3.8b
+; CHECK-NODOT-NEXT:    smull2 v2.8h, v2.16b, v3.16b
+; CHECK-NODOT-NEXT:    sshll v3.4s, v4.4h, #0
+; CHECK-NODOT-NEXT:    sshll v5.4s, v2.4h, #0
 ; CHECK-NODOT-NEXT:    sshll2 v4.4s, v4.8h, #0
-; CHECK-NODOT-NEXT:    sshll2 v5.4s, v5.8h, #0
-; CHECK-NODOT-NEXT:    sshll2 v16.4s, v3.8h, #0
-; CHECK-NODOT-NEXT:    sshll2 v17.4s, v2.8h, #0
-; CHECK-NODOT-NEXT:    sshll v3.4s, v3.4h, #0
-; CHECK-NODOT-NEXT:    sshll v2.4s, v2.4h, #0
-; CHECK-NODOT-NEXT:    smlal2 v1.2d, v7.4s, v6.4s
-; CHECK-NODOT-NEXT:    smlal v0.2d, v7.2s, v6.2s
-; CHECK-NODOT-NEXT:    smull2 v18.2d, v5.4s, v4.4s
-; CHECK-NODOT-NEXT:    smull v4.2d, v5.2s, v4.2s
-; CHECK-NODOT-NEXT:    smlal2 v1.2d, v17.4s, v16.4s
-; CHECK-NODOT-NEXT:    smlal v0.2d, v17.2s, v16.2s
-; CHECK-NODOT-NEXT:    smlal2 v18.2d, v2.4s, v3.4s
-; CHECK-NODOT-NEXT:    smlal v4.2d, v2.2s, v3.2s
-; CHECK-NODOT-NEXT:    add v1.2d, v18.2d, v1.2d
+; CHECK-NODOT-NEXT:    sshll2 v2.4s, v2.8h, #0
+; CHECK-NODOT-NEXT:    saddw2 v1.2d, v1.2d, v3.4s
+; CHECK-NODOT-NEXT:    saddw v0.2d, v0.2d, v3.2s
+; CHECK-NODOT-NEXT:    saddl2 v3.2d, v4.4s, v5.4s
+; CHECK-NODOT-NEXT:    saddl v4.2d, v4.2s, v5.2s
+; CHECK-NODOT-NEXT:    saddw2 v1.2d, v1.2d, v2.4s
+; CHECK-NODOT-NEXT:    saddw v0.2d, v0.2d, v2.2s
+; CHECK-NODOT-NEXT:    add v1.2d, v3.2d, v1.2d
 ; CHECK-NODOT-NEXT:    add v0.2d, v4.2d, v0.2d
 ; CHECK-NODOT-NEXT:    ret
 entry:
@@ -797,10 +771,9 @@ define <4 x i64> @sdot_no_bin_op_8to64(<4 x i64> %acc, <16 x i8> %a){
 define <4 x i32> @not_udot(<4 x i32> %acc, <8 x i8> %u, <8 x i8> %s) #0{
 ; CHECK-LABEL: not_udot:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ushll v1.8h, v1.8b, #0
-; CHECK-NEXT:    ushll v2.8h, v2.8b, #0
-; CHECK-NEXT:    umlal v0.4s, v2.4h, v1.4h
-; CHECK-NEXT:    umlal2 v0.4s, v2.8h, v1.8h
+; CHECK-NEXT:    umull v1.8h, v2.8b, v1.8b
+; CHECK-NEXT:    uaddw v0.4s, v0.4s, v1.4h
+; CHECK-NEXT:    uaddw2 v0.4s, v0.4s, v1.8h
 ; CHECK-NEXT:    ret
   %u.wide = zext <8 x i8> %u to <8 x i32>
   %s.wide = zext <8 x i8> %s to <8 x i32>
diff --git a/llvm/test/CodeGen/AArch64/select_cc.ll b/llvm/test/CodeGen/AArch64/select_cc.ll
index 6feaabe85d9ba..66dbd4ed5a4dc 100644
--- a/llvm/test/CodeGen/AArch64/select_cc.ll
+++ b/llvm/test/CodeGen/AArch64/select_cc.ll
@@ -85,9 +85,8 @@ entry:
 define <2 x double> @select_olt_load_cmp(<2 x double> %a, ptr %src) {
 ; CHECK-SD-LABEL: select_olt_load_cmp:
 ; CHECK-SD:       // %bb.0: // %entry
-; CHECK-SD-NEXT:    movi d1, #0000000000000000
-; CHECK-SD-NEXT:    ldr d2, [x0]
-; CHECK-SD-NEXT:    fcmgt v1.2s, v2.2s, v1.2s
+; CHECK-SD-NEXT:    ldr d1, [x0]
+; CHECK-SD-NEXT:    fcmgt v1.2s, v1.2s, #0.0
 ; CHECK-SD-NEXT:    sshll v1.2d, v1.2s, #0
 ; CHECK-SD-NEXT:    and v0.16b, v0.16b, v1.16b
 ; CHECK-SD-NEXT:    ret
diff --git a/llvm/test/CodeGen/AArch64/sme2-intrinsics-mop4-fp8.ll b/llvm/test/CodeGen/AArch64/sme2-intrinsics-mop4-fp8.ll
new file mode 100644
index 0000000000000..5a0cf8e57904b
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sme2-intrinsics-mop4-fp8.ll
@@ -0,0 +1,98 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -force-streaming -verify-machineinstrs < %s | FileCheck %s
+
+target triple = "aarch64-linux"
+
+define void @mop4a_za16_fp8_1x1(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
+; CHECK-LABEL: mop4a_za16_fp8_1x1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z24.d, z1.d
+; CHECK-NEXT:    fmop4a za0.h, z0.b, z24.b
+; CHECK-NEXT:    ret
+  call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x1(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)
+  ret void
+}
+
+define void @mop4a_za16_fp8_1x2(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {
+; CHECK-LABEL: mop4a_za16_fp8_1x2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z25.d, z2.d
+; CHECK-NEXT:    mov z24.d, z1.d
+; CHECK-NEXT:    fmop4a za0.h, z0.b, { z24.b, z25.b }
+; CHECK-NEXT:    ret
+  call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x2(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)
+  ret void
+}
+
+define void @mop4a_za16_fp8_2x1(<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm) #0 {
+; CHECK-LABEL: mop4a_za16_fp8_2x1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z24.d, z2.d
+; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
+; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
+; CHECK-NEXT:    fmop4a za0.h, { z0.b, z1.b }, z24.b
+; CHECK-NEXT:    ret
+  call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x1(i32 0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm)
+  ret void
+}
+
+define void @mop4a_za16_fp8_2x2(<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {
+; CHECK-LABEL: mop4a_za16_fp8_2x2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z25.d, z3.d
+; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
+; CHECK-NEXT:    mov z24.d, z2.d
+; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
+; CHECK-NEXT:    fmop4a za0.h, { z0.b, z1.b }, { z24.b, z25.b }
+; CHECK-NEXT:    ret
+  call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x2(i32 0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)
+  ret void
+}
+
+define void @mop4a_za32_fp8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
+; CHECK-LABEL: mop4a_za32_fp8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z24.d, z1.d
+; CHECK-NEXT:    fmop4a za0.s, z0.b, z24.b
+; CHECK-NEXT:    ret
+  call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x1(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)
+  ret void
+}
+
+define void @mop4a_za32_fp8_1x2(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {
+; CHECK-LABEL: mop4a_za32_fp8_1x2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z25.d, z2.d
+; CHECK-NEXT:    mov z24.d, z1.d
+; CHECK-NEXT:    fmop4a za0.s, z0.b, { z24.b, z25.b }
+; CHECK-NEXT:    ret
+  call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x2(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)
+  ret void
+}
+
+define void @mop4a_za32_fp8_2x1(<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm) #0 {
+; CHECK-LABEL: mop4a_za32_fp8_2x1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z24.d, z2.d
+; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
+; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
+; CHECK-NEXT:    fmop4a za0.s, { z0.b, z1.b }, z24.b
+; CHECK-NEXT:    ret
+  call void @llvm.aarch64.sme.fp8.fmop4a.za32.2x1(i32 0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm)
+  ret void
+}
+
+define void @mop4a_za32_fp8_2x2(<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {
+; CHECK-LABEL: mop4a_za32_fp8_2x2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov z25.d, z3.d
+; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
+; CHECK-NEXT:    mov z24.d, z2.d
+; CHECK-NEXT:    // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
+; CHECK-NEXT:    fmop4a za0.s, { z0.b, z1.b }, { z24.b, z25.b }
+; CHECK-NEXT:    ret
+  call void @llvm.aarch64.sme.fp8.fmop4a.za32.2x2(i32 0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)
+  ret void
+}
+
+attributes #0 = {nounwind "target-features" = "+sme-f8f16,+sme-f8f32,+sme2p1,+sme-mop4" }
diff --git a/llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll b/llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
index 8d3b12e359f3f..ed27f40aba774 100644
--- a/llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
+++ b/llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
@@ -11,24 +11,7 @@ define <vscale x 4 x i32> @udot(<vscale x 4 x i32> %acc, <vscale x 16 x i8> %a,
 ;
 ; CHECK-NEWLOWERING-LABEL: udot:
 ; CHECK-NEWLOWERING:       // %bb.0: // %entry
-; CHECK-NEWLOWERING-NEXT:    uunpklo z3.h, z2.b
-; CHECK-NEWLOWERING-NEXT:    uunpklo z4.h, z1.b
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z2.h, z2.b
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z1.h, z1.b
-; CHECK-NEWLOWERING-NEXT:    ptrue p0.s
-; CHECK-NEWLOWERING-NEXT:    uunpklo z5.s, z3.h
-; CHECK-NEWLOWERING-NEXT:    uunpklo z6.s, z4.h
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z3.s, z3.h
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z4.s, z4.h
-; CHECK-NEWLOWERING-NEXT:    mla z0.s, p0/m, z6.s, z5.s
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z5.s, z2.h
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z6.s, z1.h
-; CHECK-NEWLOWERING-NEXT:    mul z3.s, z4.s, z3.s
-; CHECK-NEWLOWERING-NEXT:    uunpklo z2.s, z2.h
-; CHECK-NEWLOWERING-NEXT:    uunpklo z1.s, z1.h
-; CHECK-NEWLOWERING-NEXT:    mla z0.s, p0/m, z6.s, z5.s
-; CHECK-NEWLOWERING-NEXT:    mad z1.s, p0/m, z2.s, z3.s
-; CHECK-NEWLOWERING-NEXT:    add z0.s, z1.s, z0.s
+; CHECK-NEWLOWERING-NEXT:    udot z0.s, z1.b, z2.b
 ; CHECK-NEWLOWERING-NEXT:    ret
 entry:
   %a.wide = zext <vscale x 16 x i8> %a to <vscale x 16 x i32>
@@ -46,24 +29,7 @@ define <vscale x 2 x i64> @udot_wide(<vscale x 2 x i64> %acc, <vscale x 8 x i16>
 ;
 ; CHECK-NEWLOWERING-LABEL: udot_wide:
 ; CHECK-NEWLOWERING:       // %bb.0: // %entry
-; CHECK-NEWLOWERING-NEXT:    uunpklo z3.s, z2.h
-; CHECK-NEWLOWERING-NEXT:    uunpklo z4.s, z1.h
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z2.s, z2.h
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z1.s, z1.h
-; CHECK-NEWLOWERING-NEXT:    ptrue p0.d
-; CHECK-NEWLOWERING-NEXT:    uunpklo z5.d, z3.s
-; CHECK-NEWLOWERING-NEXT:    uunpklo z6.d, z4.s
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z3.d, z3.s
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z4.d, z4.s
-; CHECK-NEWLOWERING-NEXT:    mla z0.d, p0/m, z6.d, z5.d
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z5.d, z2.s
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z6.d, z1.s
-; CHECK-NEWLOWERING-NEXT:    mul z3.d, z4.d, z3.d
-; CHECK-NEWLOWERING-NEXT:    uunpklo z2.d, z2.s
-; CHECK-NEWLOWERING-NEXT:    uunpklo z1.d, z1.s
-; CHECK-NEWLOWERING-NEXT:    mla z0.d, p0/m, z6.d, z5.d
-; CHECK-NEWLOWERING-NEXT:    mad z1.d, p0/m, z2.d, z3.d
-; CHECK-NEWLOWERING-NEXT:    add z0.d, z1.d, z0.d
+; CHECK-NEWLOWERING-NEXT:    udot z0.d, z1.h, z2.h
 ; CHECK-NEWLOWERING-NEXT:    ret
 entry:
   %a.wide = zext <vscale x 8 x i16> %a to <vscale x 8 x i64>
@@ -81,24 +47,7 @@ define <vscale x 4 x i32> @sdot(<vscale x 4 x i32> %accc, <vscale x 16 x i8> %a,
 ;
 ; CHECK-NEWLOWERING-LABEL: sdot:
 ; CHECK-NEWLOWERING:       // %bb.0: // %entry
-; CHECK-NEWLOWERING-NEXT:    sunpklo z3.h, z2.b
-; CHECK-NEWLOWERING-NEXT:    sunpklo z4.h, z1.b
-; CHECK-NEWLOWERING-NEXT:    sunpkhi z2.h, z2.b
-; CHECK-NEWLOWERING-NEXT:    sunpkhi z1.h, z1.b
-; CHECK-NEWLOWERING-NEXT:    ptrue p0.s
-; CHECK-NEWLOWERING-NEXT:    sunpklo z5.s, z3.h
-; CHECK-NEWLOWERING-NEXT:    sunpklo z6.s, z4.h
-; CHECK-NEWLOWERING-NEXT:    sunpkhi z3.s, z3.h
-; CHECK-NEWLOWERING-NEXT:    sunpkhi z4.s, z4.h
-; CHECK-NEWLOWERING-NEXT:    mla z0.s, p0/m, z6.s, z5.s
-; CHECK-NEWLOWERING-NEXT:    sunpkhi z5.s, z2.h
-; CHECK-NEWLOWERING-NEXT:    sunpkhi z6.s, z1.h
-; CHECK-NEWLOWERING-NEXT:    mul z3.s, z4.s, z3.s
-; CHECK-NEWLOWERING-NEXT:    sunpklo z2.s, z2.h
-; CHECK-NEWLOWERING-NEXT:    sunpklo z1.s, z1.h
-; CHECK-NEWLOWERING-NEXT:    mla z0.s, p0/m, z6.s, z5.s
-; CHECK-NEWLOWERING-NEXT:    mad z1.s, p0/m, z2.s, z3.s
-; CHECK-NEWLOWERING-NEXT:    add z0.s, z1.s, z0.s
+; CHECK-NEWLOWERING-NEXT:    sdot z0.s, z1.b, z2.b
 ; CHECK-NEWLOWERING-NEXT:    ret
 entry:
   %a.wide = sext <vscale x 16 x i8> %a to <vscale x 16 x i32>
@@ -116,24 +65,7 @@ define <vscale x 2 x i64> @sdot_wide(<vscale x 2 x i64> %acc, <vscale x 8 x i16>
 ;
 ; CHECK-NEWLOWERING-LABEL: sdot_wide:
 ; CHECK-NEWLOWERING:       // %bb.0: // %entry
-; CHECK-NEWLOWERING-NEXT:    sunpklo z3.s, z2.h
-; CHECK-NEWLOWERING-NEXT:    sunpklo z4.s, z1.h
-; CHECK-NEWLOWERING-NEXT:    sunpkhi z2.s, z2.h
-; CHECK-NEWLOWERING-NEXT:    sunpkhi z1.s, z1.h
-; CHECK-NEWLOWERING-NEXT:    ptrue p0.d
-; CHECK-NEWLOWERING-NEXT:    sunpklo z5.d, z3.s
-; CHECK-NEWLOWERING-NEXT:    sunpklo z6.d, z4.s
-; CHECK-NEWLOWERING-NEXT:    sunpkhi z3.d, z3.s
-; CHECK-NEWLOWERING-NEXT:    sunpkhi z4.d, z4.s
-; CHECK-NEWLOWERING-NEXT:    mla z0.d, p0/m, z6.d, z5.d
-; CHECK-NEWLOWERING-NEXT:    sunpkhi z5.d, z2.s
-; CHECK-NEWLOWERING-NEXT:    sunpkhi z6.d, z1.s
-; CHECK-NEWLOWERING-NEXT:    mul z3.d, z4.d, z3.d
-; CHECK-NEWLOWERING-NEXT:    sunpklo z2.d, z2.s
-; CHECK-NEWLOWERING-NEXT:    sunpklo z1.d, z1.s
-; CHECK-NEWLOWERING-NEXT:    mla z0.d, p0/m, z6.d, z5.d
-; CHECK-NEWLOWERING-NEXT:    mad z1.d, p0/m, z2.d, z3.d
-; CHECK-NEWLOWERING-NEXT:    add z0.d, z1.d, z0.d
+; CHECK-NEWLOWERING-NEXT:    sdot z0.d, z1.h, z2.h
 ; CHECK-NEWLOWERING-NEXT:    ret
 entry:
   %a.wide = sext <vscale x 8 x i16> %a to <vscale x 8 x i64>
@@ -274,46 +206,59 @@ define <vscale x 4 x i64> @udot_8to64(<vscale x 4 x i64> %acc, <vscale x 16 x i8
 ;
 ; CHECK-NEWLOWERING-LABEL: udot_8to64:
 ; CHECK-NEWLOWERING:       // %bb.0: // %entry
-; CHECK-NEWLOWERING-NEXT:    uunpklo z4.h, z3.b
-; CHECK-NEWLOWERING-NEXT:    uunpklo z5.h, z2.b
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z3.h, z3.b
+; CHECK-NEWLOWERING-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEWLOWERING-NEXT:    addvl sp, sp, #-2
+; CHECK-NEWLOWERING-NEXT:    str z9, [sp] // 16-byte Folded Spill
+; CHECK-NEWLOWERING-NEXT:    str z8, [sp, #1, mul vl] // 16-byte Folded Spill
+; CHECK-NEWLOWERING-NEXT:    .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
+; CHECK-NEWLOWERING-NEXT:    .cfi_offset w29, -16
+; CHECK-NEWLOWERING-NEXT:    .cfi_escape 0x10, 0x48, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x78, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d8 @ cfa - 16 - 8 * VG
+; CHECK-NEWLOWERING-NEXT:    .cfi_escape 0x10, 0x49, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x70, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d9 @ cfa - 16 - 16 * VG
+; CHECK-NEWLOWERING-NEXT:    uunpklo z4.h, z2.b
+; CHECK-NEWLOWERING-NEXT:    uunpklo z5.h, z3.b
 ; CHECK-NEWLOWERING-NEXT:    uunpkhi z2.h, z2.b
+; CHECK-NEWLOWERING-NEXT:    uunpkhi z3.h, z3.b
 ; CHECK-NEWLOWERING-NEXT:    ptrue p0.d
 ; CHECK-NEWLOWERING-NEXT:    uunpklo z6.s, z4.h
-; CHECK-NEWLOWERING-NEXT:    uunpklo z7.s, z5.h
 ; CHECK-NEWLOWERING-NEXT:    uunpkhi z4.s, z4.h
+; CHECK-NEWLOWERING-NEXT:    uunpklo z7.s, z5.h
 ; CHECK-NEWLOWERING-NEXT:    uunpkhi z5.s, z5.h
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z24.s, z3.h
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z25.s, z2.h
-; CHECK-NEWLOWERING-NEXT:    uunpklo z3.s, z3.h
-; CHECK-NEWLOWERING-NEXT:    uunpklo z2.s, z2.h
-; CHECK-NEWLOWERING-NEXT:    uunpklo z26.d, z6.s
-; CHECK-NEWLOWERING-NEXT:    uunpklo z27.d, z7.s
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z6.d, z6.s
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z7.d, z7.s
-; CHECK-NEWLOWERING-NEXT:    uunpklo z28.d, z4.s
+; CHECK-NEWLOWERING-NEXT:    uunpklo z24.s, z2.h
+; CHECK-NEWLOWERING-NEXT:    uunpkhi z2.s, z2.h
+; CHECK-NEWLOWERING-NEXT:    uunpklo z25.s, z3.h
+; CHECK-NEWLOWERING-NEXT:    uunpkhi z3.s, z3.h
+; CHECK-NEWLOWERING-NEXT:    uunpkhi z26.d, z6.s
+; CHECK-NEWLOWERING-NEXT:    uunpklo z6.d, z6.s
+; CHECK-NEWLOWERING-NEXT:    uunpklo z27.d, z4.s
+; CHECK-NEWLOWERING-NEXT:    uunpklo z28.d, z7.s
 ; CHECK-NEWLOWERING-NEXT:    uunpklo z29.d, z5.s
 ; CHECK-NEWLOWERING-NEXT:    uunpkhi z4.d, z4.s
+; CHECK-NEWLOWERING-NEXT:    uunpkhi z7.d, z7.s
 ; CHECK-NEWLOWERING-NEXT:    uunpkhi z5.d, z5.s
-; CHECK-NEWLOWERING-NEXT:    mla z0.d, p0/m, z27.d, z26.d
-; CHECK-NEWLOWERING-NEXT:    uunpklo z26.d, z24.s
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z24.d, z24.s
-; CHECK-NEWLOWERING-NEXT:    mla z1.d, p0/m, z7.d, z6.d
-; CHECK-NEWLOWERING-NEXT:    uunpklo z6.d, z25.s
-; CHECK-NEWLOWERING-NEXT:    uunpklo z7.d, z3.s
-; CHECK-NEWLOWERING-NEXT:    mul z27.d, z29.d, z28.d
-; CHECK-NEWLOWERING-NEXT:    uunpklo z28.d, z2.s
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z25.d, z25.s
+; CHECK-NEWLOWERING-NEXT:    uunpkhi z30.d, z24.s
+; CHECK-NEWLOWERING-NEXT:    uunpkhi z31.d, z2.s
+; CHECK-NEWLOWERING-NEXT:    uunpklo z24.d, z24.s
+; CHECK-NEWLOWERING-NEXT:    uunpklo z2.d, z2.s
+; CHECK-NEWLOWERING-NEXT:    uunpkhi z8.d, z25.s
+; CHECK-NEWLOWERING-NEXT:    uunpklo z25.d, z25.s
+; CHECK-NEWLOWERING-NEXT:    uunpklo z9.d, z3.s
+; CHECK-NEWLOWERING-NEXT:    mul z27.d, z27.d, z29.d
+; CHECK-NEWLOWERING-NEXT:    mla z0.d, p0/m, z6.d, z28.d
 ; CHECK-NEWLOWERING-NEXT:    uunpkhi z3.d, z3.s
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z2.d, z2.s
-; CHECK-NEWLOWERING-NEXT:    mul z4.d, z5.d, z4.d
-; CHECK-NEWLOWERING-NEXT:    mla z0.d, p0/m, z6.d, z26.d
-; CHECK-NEWLOWERING-NEXT:    movprfx z5, z27
-; CHECK-NEWLOWERING-NEXT:    mla z5.d, p0/m, z28.d, z7.d
-; CHECK-NEWLOWERING-NEXT:    mla z1.d, p0/m, z25.d, z24.d
-; CHECK-NEWLOWERING-NEXT:    mad z2.d, p0/m, z3.d, z4.d
-; CHECK-NEWLOWERING-NEXT:    add z0.d, z5.d, z0.d
-; CHECK-NEWLOWERING-NEXT:    add z1.d, z2.d, z1.d
+; CHECK-NEWLOWERING-NEXT:    mul z4.d, z4.d, z5.d
+; CHECK-NEWLOWERING-NEXT:    mla z1.d, p0/m, z26.d, z7.d
+; CHECK-NEWLOWERING-NEXT:    mla z0.d, p0/m, z2.d, z9.d
+; CHECK-NEWLOWERING-NEXT:    movprfx z2, z27
+; CHECK-NEWLOWERING-NEXT:    mla z2.d, p0/m, z24.d, z25.d
+; CHECK-NEWLOWERING-NEXT:    ldr z9, [sp] // 16-byte Folded Reload
+; CHECK-NEWLOWERING-NEXT:    mla z1.d, p0/m, z31.d, z3.d
+; CHECK-NEWLOWERING-NEXT:    movprfx z3, z4
+; CHECK-NEWLOWERING-NEXT:    mla z3.d, p0/m, z30.d, z8.d
+; CHECK-NEWLOWERING-NEXT:    ldr z8, [sp, #1, mul vl] // 16-byte Folded Reload
+; CHECK-NEWLOWERING-NEXT:    add z0.d, z2.d, z0.d
+; CHECK-NEWLOWERING-NEXT:    add z1.d, z3.d, z1.d
+; CHECK-NEWLOWERING-NEXT:    addvl sp, sp, #2
+; CHECK-NEWLOWERING-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEWLOWERING-NEXT:    ret
 entry:
   %a.wide = zext <vscale x 16 x i8> %a to <vscale x 16 x i64>
@@ -337,46 +282,59 @@ define <vscale x 4 x i64> @sdot_8to64(<vscale x 4 x i64> %acc, <vscale x 16 x i8
 ;
 ; CHECK-NEWLOWERING-LABEL: sdot_8to64:
 ; CHECK-NEWLOWERING:       // %bb.0: // %entry
-; CHECK-NEWLOWERING-NEXT:    sunpklo z4.h, z3.b
-; CHECK-NEWLOWERING-NEXT:    sunpklo z5.h, z2.b
-; CHECK-NEWLOWERING-NEXT:    sunpkhi z3.h, z3.b
+; CHECK-NEWLOWERING-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEWLOWERING-NEXT:    addvl sp, sp, #-2
+; CHECK-NEWLOWERING-NEXT:    str z9, [sp] // 16-byte Folded Spill
+; CHECK-NEWLOWERING-NEXT:    str z8, [sp, #1, mul vl] // 16-byte Folded Spill
+; CHECK-NEWLOWERING-NEXT:    .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
+; CHECK-NEWLOWERING-NEXT:    .cfi_offset w29, -16
+; CHECK-NEWLOWERING-NEXT:    .cfi_escape 0x10, 0x48, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x78, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d8 @ cfa - 16 - 8 * VG
+; CHECK-NEWLOWERING-NEXT:    .cfi_escape 0x10, 0x49, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x70, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d9 @ cfa - 16 - 16 * VG
+; CHECK-NEWLOWERING-NEXT:    sunpklo z4.h, z2.b
+; CHECK-NEWLOWERING-NEXT:    sunpklo z5.h, z3.b
 ; CHECK-NEWLOWERING-NEXT:    sunpkhi z2.h, z2.b
+; CHECK-NEWLOWERING-NEXT:    sunpkhi z3.h, z3.b
 ; CHECK-NEWLOWERING-NEXT:    ptrue p0.d
 ; CHECK-NEWLOWERING-NEXT:    sunpklo z6.s, z4.h
-; CHECK-NEWLOWERING-NEXT:    sunpklo z7.s, z5.h
 ; CHECK-NEWLOWERING-NEXT:    sunpkhi z4.s, z4.h
+; CHECK-NEWLOWERING-NEXT:    sunpklo z7.s, z5.h
 ; CHECK-NEWLOWERING-NEXT:    sunpkhi z5.s, z5.h
-; CHECK-NEWLOWERING-NEXT:    sunpkhi z24.s, z3.h
-; CHECK-NEWLOWERING-NEXT:    sunpkhi z25.s, z2.h
-; CHECK-NEWLOWERING-NEXT:    sunpklo z3.s, z3.h
-; CHECK-NEWLOWERING-NEXT:    sunpklo z2.s, z2.h
-; CHECK-NEWLOWERING-NEXT:    sunpklo z26.d, z6.s
-; CHECK-NEWLOWERING-NEXT:    sunpklo z27.d, z7.s
-; CHECK-NEWLOWERING-NEXT:    sunpkhi z6.d, z6.s
-; CHECK-NEWLOWERING-NEXT:    sunpkhi z7.d, z7.s
-; CHECK-NEWLOWERING-NEXT:    sunpklo z28.d, z4.s
+; CHECK-NEWLOWERING-NEXT:    sunpklo z24.s, z2.h
+; CHECK-NEWLOWERING-NEXT:    sunpkhi z2.s, z2.h
+; CHECK-NEWLOWERING-NEXT:    sunpklo z25.s, z3.h
+; CHECK-NEWLOWERING-NEXT:    sunpkhi z3.s, z3.h
+; CHECK-NEWLOWERING-NEXT:    sunpkhi z26.d, z6.s
+; CHECK-NEWLOWERING-NEXT:    sunpklo z6.d, z6.s
+; CHECK-NEWLOWERING-NEXT:    sunpklo z27.d, z4.s
+; CHECK-NEWLOWERING-NEXT:    sunpklo z28.d, z7.s
 ; CHECK-NEWLOWERING-NEXT:    sunpklo z29.d, z5.s
 ; CHECK-NEWLOWERING-NEXT:    sunpkhi z4.d, z4.s
+; CHECK-NEWLOWERING-NEXT:    sunpkhi z7.d, z7.s
 ; CHECK-NEWLOWERING-NEXT:    sunpkhi z5.d, z5.s
-; CHECK-NEWLOWERING-NEXT:    mla z0.d, p0/m, z27.d, z26.d
-; CHECK-NEWLOWERING-NEXT:    sunpklo z26.d, z24.s
-; CHECK-NEWLOWERING-NEXT:    sunpkhi z24.d, z24.s
-; CHECK-NEWLOWERING-NEXT:    mla z1.d, p0/m, z7.d, z6.d
-; CHECK-NEWLOWERING-NEXT:    sunpklo z6.d, z25.s
-; CHECK-NEWLOWERING-NEXT:    sunpklo z7.d, z3.s
-; CHECK-NEWLOWERING-NEXT:    mul z27.d, z29.d, z28.d
-; CHECK-NEWLOWERING-NEXT:    sunpklo z28.d, z2.s
-; CHECK-NEWLOWERING-NEXT:    sunpkhi z25.d, z25.s
+; CHECK-NEWLOWERING-NEXT:    sunpkhi z30.d, z24.s
+; CHECK-NEWLOWERING-NEXT:    sunpkhi z31.d, z2.s
+; CHECK-NEWLOWERING-NEXT:    sunpklo z24.d, z24.s
+; CHECK-NEWLOWERING-NEXT:    sunpklo z2.d, z2.s
+; CHECK-NEWLOWERING-NEXT:    sunpkhi z8.d, z25.s
+; CHECK-NEWLOWERING-NEXT:    sunpklo z25.d, z25.s
+; CHECK-NEWLOWERING-NEXT:    sunpklo z9.d, z3.s
+; CHECK-NEWLOWERING-NEXT:    mul z27.d, z27.d, z29.d
+; CHECK-NEWLOWERING-NEXT:    mla z0.d, p0/m, z6.d, z28.d
 ; CHECK-NEWLOWERING-NEXT:    sunpkhi z3.d, z3.s
-; CHECK-NEWLOWERING-NEXT:    sunpkhi z2.d, z2.s
-; CHECK-NEWLOWERING-NEXT:    mul z4.d, z5.d, z4.d
-; CHECK-NEWLOWERING-NEXT:    mla z0.d, p0/m, z6.d, z26.d
-; CHECK-NEWLOWERING-NEXT:    movprfx z5, z27
-; CHECK-NEWLOWERING-NEXT:    mla z5.d, p0/m, z28.d, z7.d
-; CHECK-NEWLOWERING-NEXT:    mla z1.d, p0/m, z25.d, z24.d
-; CHECK-NEWLOWERING-NEXT:    mad z2.d, p0/m, z3.d, z4.d
-; CHECK-NEWLOWERING-NEXT:    add z0.d, z5.d, z0.d
-; CHECK-NEWLOWERING-NEXT:    add z1.d, z2.d, z1.d
+; CHECK-NEWLOWERING-NEXT:    mul z4.d, z4.d, z5.d
+; CHECK-NEWLOWERING-NEXT:    mla z1.d, p0/m, z26.d, z7.d
+; CHECK-NEWLOWERING-NEXT:    mla z0.d, p0/m, z2.d, z9.d
+; CHECK-NEWLOWERING-NEXT:    movprfx z2, z27
+; CHECK-NEWLOWERING-NEXT:    mla z2.d, p0/m, z24.d, z25.d
+; CHECK-NEWLOWERING-NEXT:    ldr z9, [sp] // 16-byte Folded Reload
+; CHECK-NEWLOWERING-NEXT:    mla z1.d, p0/m, z31.d, z3.d
+; CHECK-NEWLOWERING-NEXT:    movprfx z3, z4
+; CHECK-NEWLOWERING-NEXT:    mla z3.d, p0/m, z30.d, z8.d
+; CHECK-NEWLOWERING-NEXT:    ldr z8, [sp, #1, mul vl] // 16-byte Folded Reload
+; CHECK-NEWLOWERING-NEXT:    add z0.d, z2.d, z0.d
+; CHECK-NEWLOWERING-NEXT:    add z1.d, z3.d, z1.d
+; CHECK-NEWLOWERING-NEXT:    addvl sp, sp, #2
+; CHECK-NEWLOWERING-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEWLOWERING-NEXT:    ret
 entry:
   %a.wide = sext <vscale x 16 x i8> %a to <vscale x 16 x i64>
@@ -845,11 +803,11 @@ define <vscale x 4 x i32> @not_udot(<vscale x 4 x i32> %acc, <vscale x 8 x i8> %
 ; CHECK-NEXT:    and z1.h, z1.h, #0xff
 ; CHECK-NEXT:    and z2.h, z2.h, #0xff
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    uunpklo z3.s, z2.h
-; CHECK-NEXT:    uunpklo z4.s, z1.h
-; CHECK-NEXT:    uunpkhi z2.s, z2.h
+; CHECK-NEXT:    uunpklo z3.s, z1.h
+; CHECK-NEXT:    uunpklo z4.s, z2.h
 ; CHECK-NEXT:    uunpkhi z1.s, z1.h
-; CHECK-NEXT:    mla z0.s, p0/m, z4.s, z3.s
+; CHECK-NEXT:    uunpkhi z2.s, z2.h
+; CHECK-NEXT:    mla z0.s, p0/m, z3.s, z4.s
 ; CHECK-NEXT:    mla z0.s, p0/m, z1.s, z2.s
 ; CHECK-NEXT:    ret
 ;
@@ -858,11 +816,11 @@ define <vscale x 4 x i32> @not_udot(<vscale x 4 x i32> %acc, <vscale x 8 x i8> %
 ; CHECK-NEWLOWERING-NEXT:    and z1.h, z1.h, #0xff
 ; CHECK-NEWLOWERING-NEXT:    and z2.h, z2.h, #0xff
 ; CHECK-NEWLOWERING-NEXT:    ptrue p0.s
-; CHECK-NEWLOWERING-NEXT:    uunpklo z3.s, z2.h
-; CHECK-NEWLOWERING-NEXT:    uunpklo z4.s, z1.h
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z2.s, z2.h
+; CHECK-NEWLOWERING-NEXT:    uunpklo z3.s, z1.h
+; CHECK-NEWLOWERING-NEXT:    uunpklo z4.s, z2.h
 ; CHECK-NEWLOWERING-NEXT:    uunpkhi z1.s, z1.h
-; CHECK-NEWLOWERING-NEXT:    mla z0.s, p0/m, z4.s, z3.s
+; CHECK-NEWLOWERING-NEXT:    uunpkhi z2.s, z2.h
+; CHECK-NEWLOWERING-NEXT:    mla z0.s, p0/m, z3.s, z4.s
 ; CHECK-NEWLOWERING-NEXT:    mla z0.s, p0/m, z1.s, z2.s
 ; CHECK-NEWLOWERING-NEXT:    ret
 entry:
@@ -879,11 +837,11 @@ define <vscale x 2 x i64> @not_udot_wide(<vscale x 2 x i64> %acc, <vscale x 4 x
 ; CHECK-NEXT:    and z1.s, z1.s, #0xffff
 ; CHECK-NEXT:    and z2.s, z2.s, #0xffff
 ; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    uunpklo z3.d, z2.s
-; CHECK-NEXT:    uunpklo z4.d, z1.s
-; CHECK-NEXT:    uunpkhi z2.d, z2.s
+; CHECK-NEXT:    uunpklo z3.d, z1.s
+; CHECK-NEXT:    uunpklo z4.d, z2.s
 ; CHECK-NEXT:    uunpkhi z1.d, z1.s
-; CHECK-NEXT:    mla z0.d, p0/m, z4.d, z3.d
+; CHECK-NEXT:    uunpkhi z2.d, z2.s
+; CHECK-NEXT:    mla z0.d, p0/m, z3.d, z4.d
 ; CHECK-NEXT:    mla z0.d, p0/m, z1.d, z2.d
 ; CHECK-NEXT:    ret
 ;
@@ -892,11 +850,11 @@ define <vscale x 2 x i64> @not_udot_wide(<vscale x 2 x i64> %acc, <vscale x 4 x
 ; CHECK-NEWLOWERING-NEXT:    and z1.s, z1.s, #0xffff
 ; CHECK-NEWLOWERING-NEXT:    and z2.s, z2.s, #0xffff
 ; CHECK-NEWLOWERING-NEXT:    ptrue p0.d
-; CHECK-NEWLOWERING-NEXT:    uunpklo z3.d, z2.s
-; CHECK-NEWLOWERING-NEXT:    uunpklo z4.d, z1.s
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z2.d, z2.s
+; CHECK-NEWLOWERING-NEXT:    uunpklo z3.d, z1.s
+; CHECK-NEWLOWERING-NEXT:    uunpklo z4.d, z2.s
 ; CHECK-NEWLOWERING-NEXT:    uunpkhi z1.d, z1.s
-; CHECK-NEWLOWERING-NEXT:    mla z0.d, p0/m, z4.d, z3.d
+; CHECK-NEWLOWERING-NEXT:    uunpkhi z2.d, z2.s
+; CHECK-NEWLOWERING-NEXT:    mla z0.d, p0/m, z3.d, z4.d
 ; CHECK-NEWLOWERING-NEXT:    mla z0.d, p0/m, z1.d, z2.d
 ; CHECK-NEWLOWERING-NEXT:    ret
 entry:
@@ -1248,48 +1206,24 @@ define <vscale x 2 x i16> @udot_nxv8i8_promote (<vscale x 2 x i16> %acc, <vscale
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    and z1.h, z1.h, #0xff
 ; CHECK-NEXT:    and z2.h, z2.h, #0xff
-; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    uunpklo z3.s, z2.h
-; CHECK-NEXT:    uunpklo z4.s, z1.h
-; CHECK-NEXT:    uunpkhi z2.s, z2.h
+; CHECK-NEXT:    mul z1.h, z1.h, z2.h
+; CHECK-NEXT:    uunpklo z2.s, z1.h
 ; CHECK-NEXT:    uunpkhi z1.s, z1.h
-; CHECK-NEXT:    uunpklo z5.d, z3.s
-; CHECK-NEXT:    uunpklo z6.d, z4.s
-; CHECK-NEXT:    uunpkhi z3.d, z3.s
-; CHECK-NEXT:    uunpkhi z4.d, z4.s
-; CHECK-NEXT:    mla z0.d, p0/m, z6.d, z5.d
-; CHECK-NEXT:    uunpkhi z5.d, z2.s
-; CHECK-NEXT:    uunpkhi z6.d, z1.s
-; CHECK-NEXT:    mul z3.d, z4.d, z3.d
-; CHECK-NEXT:    uunpklo z2.d, z2.s
-; CHECK-NEXT:    uunpklo z1.d, z1.s
-; CHECK-NEXT:    mla z0.d, p0/m, z6.d, z5.d
-; CHECK-NEXT:    mad z1.d, p0/m, z2.d, z3.d
+; CHECK-NEXT:    uunpklo z3.d, z2.s
+; CHECK-NEXT:    uunpklo z4.d, z1.s
+; CHECK-NEXT:    uunpkhi z2.d, z2.s
+; CHECK-NEXT:    uunpkhi z1.d, z1.s
+; CHECK-NEXT:    add z0.d, z0.d, z3.d
+; CHECK-NEXT:    add z2.d, z2.d, z4.d
 ; CHECK-NEXT:    add z0.d, z1.d, z0.d
+; CHECK-NEXT:    add z0.d, z2.d, z0.d
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-NEWLOWERING-LABEL: udot_nxv8i8_promote:
 ; CHECK-NEWLOWERING:       // %bb.0: // %entry
-; CHECK-NEWLOWERING-NEXT:    and z1.h, z1.h, #0xff
 ; CHECK-NEWLOWERING-NEXT:    and z2.h, z2.h, #0xff
-; CHECK-NEWLOWERING-NEXT:    ptrue p0.d
-; CHECK-NEWLOWERING-NEXT:    uunpklo z3.s, z2.h
-; CHECK-NEWLOWERING-NEXT:    uunpklo z4.s, z1.h
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z2.s, z2.h
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z1.s, z1.h
-; CHECK-NEWLOWERING-NEXT:    uunpklo z5.d, z3.s
-; CHECK-NEWLOWERING-NEXT:    uunpklo z6.d, z4.s
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z3.d, z3.s
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z4.d, z4.s
-; CHECK-NEWLOWERING-NEXT:    mla z0.d, p0/m, z6.d, z5.d
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z5.d, z2.s
-; CHECK-NEWLOWERING-NEXT:    uunpkhi z6.d, z1.s
-; CHECK-NEWLOWERING-NEXT:    mul z3.d, z4.d, z3.d
-; CHECK-NEWLOWERING-NEXT:    uunpklo z2.d, z2.s
-; CHECK-NEWLOWERING-NEXT:    uunpklo z1.d, z1.s
-; CHECK-NEWLOWERING-NEXT:    mla z0.d, p0/m, z6.d, z5.d
-; CHECK-NEWLOWERING-NEXT:    mad z1.d, p0/m, z2.d, z3.d
-; CHECK-NEWLOWERING-NEXT:    add z0.d, z1.d, z0.d
+; CHECK-NEWLOWERING-NEXT:    and z1.h, z1.h, #0xff
+; CHECK-NEWLOWERING-NEXT:    udot z0.d, z1.h, z2.h
 ; CHECK-NEWLOWERING-NEXT:    ret
 entry:
   %a.wide = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>
@@ -1305,49 +1239,25 @@ define <vscale x 2 x i16> @sdot_nxv8i8_promote (<vscale x 2 x i16> %acc, <vscale
 ; CHECK-NEXT:    ptrue p0.h
 ; CHECK-NEXT:    sxtb z1.h, p0/m, z1.h
 ; CHECK-NEXT:    sxtb z2.h, p0/m, z2.h
-; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    sunpklo z3.s, z2.h
-; CHECK-NEXT:    sunpklo z4.s, z1.h
-; CHECK-NEXT:    sunpkhi z2.s, z2.h
-; CHECK-NEXT:    sunpkhi z1.s, z1.h
-; CHECK-NEXT:    sunpklo z5.d, z3.s
-; CHECK-NEXT:    sunpklo z6.d, z4.s
-; CHECK-NEXT:    sunpkhi z3.d, z3.s
-; CHECK-NEXT:    sunpkhi z4.d, z4.s
-; CHECK-NEXT:    mla z0.d, p0/m, z6.d, z5.d
-; CHECK-NEXT:    sunpkhi z5.d, z2.s
-; CHECK-NEXT:    sunpkhi z6.d, z1.s
-; CHECK-NEXT:    mul z3.d, z4.d, z3.d
-; CHECK-NEXT:    sunpklo z2.d, z2.s
-; CHECK-NEXT:    sunpklo z1.d, z1.s
-; CHECK-NEXT:    mla z0.d, p0/m, z6.d, z5.d
-; CHECK-NEXT:    mad z1.d, p0/m, z2.d, z3.d
+; CHECK-NEXT:    mul z1.h, z1.h, z2.h
+; CHECK-NEXT:    uunpklo z2.s, z1.h
+; CHECK-NEXT:    uunpkhi z1.s, z1.h
+; CHECK-NEXT:    uunpklo z3.d, z2.s
+; CHECK-NEXT:    uunpklo z4.d, z1.s
+; CHECK-NEXT:    uunpkhi z2.d, z2.s
+; CHECK-NEXT:    uunpkhi z1.d, z1.s
+; CHECK-NEXT:    add z0.d, z0.d, z3.d
+; CHECK-NEXT:    add z2.d, z2.d, z4.d
 ; CHECK-NEXT:    add z0.d, z1.d, z0.d
+; CHECK-NEXT:    add z0.d, z2.d, z0.d
 ; CHECK-NEXT:    ret
 ;
 ; CHECK-NEWLOWERING-LABEL: sdot_nxv8i8_promote:
 ; CHECK-NEWLOWERING:       // %bb.0: // %entry
 ; CHECK-NEWLOWERING-NEXT:    ptrue p0.h
-; CHECK-NEWLOWERING-NEXT:    sxtb z1.h, p0/m, z1.h
 ; CHECK-NEWLOWERING-NEXT:    sxtb z2.h, p0/m, z2.h
-; CHECK-NEWLOWERING-NEXT:    ptrue p0.d
-; CHECK-NEWLOWERING-NEXT:    sunpklo z3.s, z2.h
-; CHECK-NEWLOWERING-NEXT:    sunpklo z4.s, z1.h
-; CHECK-NEWLOWERING-NEXT:    sunpkhi z2.s, z2.h
-; CHECK-NEWLOWERING-NEXT:    sunpkhi z1.s, z1.h
-; CHECK-NEWLOWERING-NEXT:    sunpklo z5.d, z3.s
-; CHECK-NEWLOWERING-NEXT:    sunpklo z6.d, z4.s
-; CHECK-NEWLOWERING-NEXT:    sunpkhi z3.d, z3.s
-; CHECK-NEWLOWERING-NEXT:    sunpkhi z4.d, z4.s
-; CHECK-NEWLOWERING-NEXT:    mla z0.d, p0/m, z6.d, z5.d
-; CHECK-NEWLOWERING-NEXT:    sunpkhi z5.d, z2.s
-; CHECK-NEWLOWERING-NEXT:    sunpkhi z6.d, z1.s
-; CHECK-NEWLOWERING-NEXT:    mul z3.d, z4.d, z3.d
-; CHECK-NEWLOWERING-NEXT:    sunpklo z2.d, z2.s
-; CHECK-NEWLOWERING-NEXT:    sunpklo z1.d, z1.s
-; CHECK-NEWLOWERING-NEXT:    mla z0.d, p0/m, z6.d, z5.d
-; CHECK-NEWLOWERING-NEXT:    mad z1.d, p0/m, z2.d, z3.d
-; CHECK-NEWLOWERING-NEXT:    add z0.d, z1.d, z0.d
+; CHECK-NEWLOWERING-NEXT:    sxtb z1.h, p0/m, z1.h
+; CHECK-NEWLOWERING-NEXT:    sdot z0.d, z1.h, z2.h
 ; CHECK-NEWLOWERING-NEXT:    ret
 entry:
   %a.wide = sext <vscale x 8 x i8> %a to <vscale x 8 x i16>
diff --git a/llvm/test/CodeGen/AArch64/sve-varargs-caller-broken.ll b/llvm/test/CodeGen/AArch64/sve-varargs-caller-broken.ll
index 1ecdd2ff43781..b90c02fa1c032 100644
--- a/llvm/test/CodeGen/AArch64/sve-varargs-caller-broken.ll
+++ b/llvm/test/CodeGen/AArch64/sve-varargs-caller-broken.ll
@@ -1,11 +1,24 @@
-; RUN: not --crash llc -mtriple aarch64-linux-gnu -mattr=+sve <%s 2>&1 | FileCheck %s
+; RUN: split-file %s %t
 
-declare i32 @sve_printf(ptr, <vscale x 4 x i32>, ...)
+; RUN: not --crash llc -mtriple aarch64-linux-gnu -mattr=+sve < %t/test-non-tailcall.ll 2>&1 | FileCheck %s --check-prefix=CHECKNONTAIL
+; RUN: not --crash llc -mtriple aarch64-linux-gnu -mattr=+sve < %t/test-tailcall.ll 2>&1 | FileCheck %s --check-prefix=CHECKTAIL
 
+;--- test-non-tailcall.ll
+declare i32 @sve_printf(ptr, <vscale x 4 x i32>, ...)
 @.str_1 = internal constant [6 x i8] c"boo!\0A\00"
 
-; CHECK: Passing SVE types to variadic functions is currently not supported
-define void @foo(<vscale x 4 x i32> %x) {
+; CHECKTAIL: Passing SVE types to variadic functions is currently not supported
+define void @foo_nontail(<vscale x 4 x i32> %x) {
   call i32 (ptr, <vscale x 4 x i32>, ...) @sve_printf(ptr @.str_1, <vscale x 4 x i32> %x, <vscale x 4 x i32> %x)
   ret void
 }
+
+;--- test-tailcall.ll
+declare i32 @sve_printf(ptr, <vscale x 4 x i32>, ...)
+@.str_1 = internal constant [6 x i8] c"boo!\0A\00"
+
+; CHECKNONTAIL: Passing SVE types to variadic functions is currently not supported
+define void @foo_tail(<vscale x 4 x i32> %x) {
+  tail call i32 (ptr, <vscale x 4 x i32>, ...) @sve_printf(ptr @.str_1, <vscale x 4 x i32> %x, <vscale x 4 x i32> %x)
+  ret void
+}
diff --git a/llvm/test/CodeGen/AArch64/sve-varargs.ll b/llvm/test/CodeGen/AArch64/sve-varargs.ll
index c63491f445b9c..4ae92f0c8a41b 100644
--- a/llvm/test/CodeGen/AArch64/sve-varargs.ll
+++ b/llvm/test/CodeGen/AArch64/sve-varargs.ll
@@ -5,8 +5,8 @@ declare i32 @sve_printf(ptr, <vscale x 4 x i32>, ...)
 
 @.str_1 = internal constant [6 x i8] c"boo!\0A\00"
 
-define void @foo(<vscale x 4 x i32> %x) uwtable {
-; CHECK-LABEL: foo:
+define void @foo_nontail(<vscale x 4 x i32> %x) uwtable {
+; CHECK-LABEL: foo_nontail:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
@@ -21,3 +21,13 @@ define void @foo(<vscale x 4 x i32> %x) uwtable {
   call i32 (ptr, <vscale x 4 x i32>, ...) @sve_printf(ptr @.str_1, <vscale x 4 x i32> %x)
   ret void
 }
+
+define void @foo_tail(<vscale x 4 x i32> %x) uwtable {
+; CHECK-LABEL: foo_tail:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    adrp x0, .str_1
+; CHECK-NEXT:    add x0, x0, :lo12:.str_1
+; CHECK-NEXT:    b sve_printf
+  tail call i32 (ptr, <vscale x 4 x i32>, ...) @sve_printf(ptr @.str_1, <vscale x 4 x i32> %x)
+  ret void
+}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
index 515b9f8955d59..8efe711c9267c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
@@ -26,5 +26,3 @@ entry:
   ret void
 }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
index fc3eb19e98524..a81ce316081d4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
@@ -210,5 +210,3 @@ entry:
   ret ptr addrspace(1) %call
 }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
index 4ee658666a1b7..a439226fbc5fb 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
@@ -178,5 +178,3 @@ define <2 x half> @test_atomicrmw_fmax_vector(ptr addrspace(3) %addr) {
   ret <2 x half> %oldval
 }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
index 31c08a3479bb3..a12ee14aee427 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
@@ -227,5 +227,3 @@ define void @func_call_no_other_sgprs() {
   ret void
 }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
index 7c54d303e91a3..0b6fe90b90654 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
@@ -3013,5 +3013,3 @@ attributes #0 = { nounwind }
 attributes #1 = { nounwind readnone }
 attributes #2 = { nounwind noinline }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
index c13c6e96d7e7d..2910d35e3e495 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
@@ -90,5 +90,3 @@ define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval
   ret void
 }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
index 4e7688539423b..92106d7e1d60d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
@@ -6124,5 +6124,3 @@ attributes #0 = { nounwind }
 attributes #1 = { nounwind readnone }
 attributes #2 = { nounwind noinline }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
index 2ba0979c72533..1e033f24994b2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
@@ -23,5 +23,3 @@ entry:
   ret void
 }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
index 951be00a124c7..ac0d5ee78666e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
@@ -74,5 +74,3 @@ define amdgpu_gfx void @test_gfx_indirect_call_sgpr_ptr(ptr %fptr) {
   ret void
 }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
index 8813462652efd..c18c96d9c50c7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
@@ -1488,5 +1488,3 @@ entry:
 attributes #0 = { nounwind }
 attributes #1 = { nounwind noinline "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
index 7be77f403a214..d3a6f70287ca5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
@@ -43,5 +43,3 @@ define void @tail_call_void_func_void() {
   ret void
 }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
index 76066e3b4bf52..8bb060fc4ed54 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
@@ -273,8 +273,6 @@ declare i32 @llvm.amdgcn.workitem.id.x() #0
 
 attributes #0 = { nounwind readnone speculatable }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; ASSUME1024: {{.*}}
 ; DEFAULTSIZE: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll b/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
index c78f0a4eb61e9..3194581fa4213 100644
--- a/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
+++ b/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
@@ -418,5 +418,3 @@ declare void @llvm.debugtrap()
 
 attributes #0 = { "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-queue-ptr" "amdgpu-no-work-group-id-x" "amdgpu-no-work-group-id-y" "amdgpu-no-work-group-id-z" "amdgpu-no-work-item-id-x" "amdgpu-no-work-item-id-y" "amdgpu-no-work-item-id-z" }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll
index 26b3c98e85cde..42c7b90da63d3 100644
--- a/llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll
@@ -167,12 +167,8 @@ define ptr addrspace(3) @ret_constant_cast_group_gv_gep_to_flat_to_group() #1 {
 attributes #0 = { argmemonly nounwind }
 attributes #1 = { nounwind }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
 ;.
 ; HSA: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
 ; HSA: attributes #[[ATTR1]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
 ; HSA: attributes #[[ATTR2]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
 ;.
-; HSA: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 500}
-;.
diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast.gfx6.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast.gfx6.ll
index 4e0fc580afdd0..35d0214a6d48d 100644
--- a/llvm/test/CodeGen/AMDGPU/addrspacecast.gfx6.ll
+++ b/llvm/test/CodeGen/AMDGPU/addrspacecast.gfx6.ll
@@ -207,5 +207,3 @@ define ptr addrspace(6) @addrspacecast_flat_null_to_constant32bit() {
 
 attributes #0 = { "amdgpu-32bit-address-high-bits"="0xffff8000" }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
index 56edb29281944..2d19f9702e6ba 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
@@ -3,7 +3,8 @@
 ; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define <32 x float> @bitcast_v32i32_to_v32f32(<32 x i32> %a, i32 %b) {
 ; GCN-LABEL: bitcast_v32i32_to_v32f32:
@@ -4447,693 +4448,1258 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v32i32_to_v128i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x13
-; GFX11-NEXT:    scratch_store_b32 off, v40, s32 offset:88
-; GFX11-NEXT:    scratch_store_b32 off, v41, s32 offset:84
-; GFX11-NEXT:    scratch_store_b32 off, v42, s32 offset:80
-; GFX11-NEXT:    scratch_store_b32 off, v43, s32 offset:76
-; GFX11-NEXT:    scratch_store_b32 off, v44, s32 offset:72
-; GFX11-NEXT:    scratch_store_b32 off, v45, s32 offset:68
-; GFX11-NEXT:    scratch_store_b32 off, v46, s32 offset:64
-; GFX11-NEXT:    scratch_store_b32 off, v47, s32 offset:60
-; GFX11-NEXT:    scratch_store_b32 off, v56, s32 offset:56
-; GFX11-NEXT:    scratch_store_b32 off, v57, s32 offset:52
-; GFX11-NEXT:    scratch_store_b32 off, v58, s32 offset:48
-; GFX11-NEXT:    scratch_store_b32 off, v59, s32 offset:44
-; GFX11-NEXT:    scratch_store_b32 off, v60, s32 offset:40
-; GFX11-NEXT:    scratch_store_b32 off, v61, s32 offset:36
-; GFX11-NEXT:    scratch_store_b32 off, v62, s32 offset:32
-; GFX11-NEXT:    scratch_store_b32 off, v63, s32 offset:28
-; GFX11-NEXT:    scratch_store_b32 off, v72, s32 offset:24
-; GFX11-NEXT:    scratch_store_b32 off, v73, s32 offset:20
-; GFX11-NEXT:    scratch_store_b32 off, v74, s32 offset:16
-; GFX11-NEXT:    scratch_store_b32 off, v75, s32 offset:12
-; GFX11-NEXT:    s_clause 0x2
-; GFX11-NEXT:    scratch_load_b32 v33, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_b32 v32, off, s32 offset:4
-; GFX11-NEXT:    scratch_load_b32 v31, off, s32
-; GFX11-NEXT:    ; implicit-def: $vgpr75
-; GFX11-NEXT:    ; implicit-def: $vgpr74
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr73
-; GFX11-NEXT:    ; implicit-def: $vgpr72
-; GFX11-NEXT:    ; implicit-def: $vgpr63
-; GFX11-NEXT:    ; implicit-def: $vgpr62
-; GFX11-NEXT:    ; implicit-def: $vgpr61
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr60
-; GFX11-NEXT:    ; implicit-def: $vgpr59
-; GFX11-NEXT:    ; implicit-def: $vgpr58
-; GFX11-NEXT:    ; implicit-def: $vgpr57
-; GFX11-NEXT:    ; implicit-def: $vgpr56
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr47
-; GFX11-NEXT:    ; implicit-def: $vgpr46
-; GFX11-NEXT:    ; implicit-def: $vgpr45
-; GFX11-NEXT:    ; implicit-def: $vgpr44
-; GFX11-NEXT:    ; implicit-def: $vgpr43
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr42
-; GFX11-NEXT:    ; implicit-def: $vgpr41
-; GFX11-NEXT:    ; implicit-def: $vgpr40
-; GFX11-NEXT:    ; implicit-def: $vgpr183
-; GFX11-NEXT:    ; implicit-def: $vgpr182
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr181
-; GFX11-NEXT:    ; implicit-def: $vgpr180
-; GFX11-NEXT:    ; implicit-def: $vgpr179
-; GFX11-NEXT:    ; implicit-def: $vgpr178
-; GFX11-NEXT:    ; implicit-def: $vgpr177
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr176
-; GFX11-NEXT:    ; implicit-def: $vgpr167
-; GFX11-NEXT:    ; implicit-def: $vgpr166
-; GFX11-NEXT:    ; implicit-def: $vgpr165
-; GFX11-NEXT:    ; implicit-def: $vgpr164
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr163
-; GFX11-NEXT:    ; implicit-def: $vgpr162
-; GFX11-NEXT:    ; implicit-def: $vgpr161
-; GFX11-NEXT:    ; implicit-def: $vgpr160
-; GFX11-NEXT:    ; implicit-def: $vgpr151
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr150
-; GFX11-NEXT:    ; implicit-def: $vgpr149
-; GFX11-NEXT:    ; implicit-def: $vgpr148
-; GFX11-NEXT:    ; implicit-def: $vgpr147
-; GFX11-NEXT:    ; implicit-def: $vgpr146
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr145
-; GFX11-NEXT:    ; implicit-def: $vgpr144
-; GFX11-NEXT:    ; implicit-def: $vgpr135
-; GFX11-NEXT:    ; implicit-def: $vgpr134
-; GFX11-NEXT:    ; implicit-def: $vgpr133
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr132
-; GFX11-NEXT:    ; implicit-def: $vgpr131
-; GFX11-NEXT:    ; implicit-def: $vgpr130
-; GFX11-NEXT:    ; implicit-def: $vgpr129
-; GFX11-NEXT:    ; implicit-def: $vgpr128
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr119
-; GFX11-NEXT:    ; implicit-def: $vgpr118
-; GFX11-NEXT:    ; implicit-def: $vgpr117
-; GFX11-NEXT:    ; implicit-def: $vgpr116
-; GFX11-NEXT:    ; implicit-def: $vgpr115
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr114
-; GFX11-NEXT:    ; implicit-def: $vgpr113
-; GFX11-NEXT:    ; implicit-def: $vgpr112
-; GFX11-NEXT:    ; implicit-def: $vgpr103
-; GFX11-NEXT:    ; implicit-def: $vgpr102
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr101
-; GFX11-NEXT:    ; implicit-def: $vgpr100
-; GFX11-NEXT:    ; implicit-def: $vgpr99
-; GFX11-NEXT:    ; implicit-def: $vgpr98
-; GFX11-NEXT:    ; implicit-def: $vgpr97
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    s_waitcnt vmcnt(2)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v33
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB6_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b64 v[48:49], 24, v[19:20]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
-; GFX11-NEXT:    v_lshrrev_b64 v[49:50], 24, v[17:18]
-; GFX11-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
-; GFX11-NEXT:    v_lshrrev_b64 v[50:51], 24, v[15:16]
-; GFX11-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
-; GFX11-NEXT:    v_lshrrev_b64 v[51:52], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
-; GFX11-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
-; GFX11-NEXT:    v_lshrrev_b64 v[64:65], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
-; GFX11-NEXT:    v_lshrrev_b64 v[53:54], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[65:66], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v68, 24, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v69, 16, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v70, 8, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v71, 16, v31
-; GFX11-NEXT:    v_lshrrev_b32_e32 v80, 8, v31
-; GFX11-NEXT:    v_lshrrev_b32_e32 v81, 24, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v82, 16, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v83, 8, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v84, 16, v29
-; GFX11-NEXT:    v_lshrrev_b32_e32 v85, 8, v29
-; GFX11-NEXT:    v_lshrrev_b32_e32 v86, 24, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v87, 16, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v96, 8, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v97, 16, v27
-; GFX11-NEXT:    v_lshrrev_b32_e32 v98, 8, v27
-; GFX11-NEXT:    v_lshrrev_b32_e32 v99, 24, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v100, 16, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v101, 8, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v102, 16, v25
-; GFX11-NEXT:    v_lshrrev_b32_e32 v103, 8, v25
-; GFX11-NEXT:    v_lshrrev_b32_e32 v112, 24, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v113, 16, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v114, 8, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v115, 16, v23
-; GFX11-NEXT:    v_lshrrev_b32_e32 v116, 8, v23
-; GFX11-NEXT:    v_lshrrev_b32_e32 v117, 24, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v118, 16, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v119, 8, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v128, 16, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v129, 8, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v130, 24, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v131, 16, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v132, 8, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v133, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v134, 8, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v135, 24, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v144, 16, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v145, 8, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v146, 16, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v147, 8, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v148, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v149, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v150, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v151, 16, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v160, 8, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v161, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v162, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v163, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v164, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v165, 8, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v166, 24, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v167, 16, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v176, 8, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v177, 16, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v178, 8, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v179, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v180, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v181, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v182, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v183, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v40, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v41, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v42, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v43, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v44, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v45, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v46, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v47, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v56, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v57, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v58, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v59, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v60, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v61, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v62, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v63, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v72, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v73, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v74, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v75, 8, v1
-; GFX11-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
-; GFX11-NEXT:    v_lshrrev_b64 v[54:55], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[66:67], 24, v[1:2]
-; GFX11-NEXT:  .LBB6_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB6_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u32_e32 v20, 3, v20
-; GFX11-NEXT:    v_add_nc_u32_e32 v19, 3, v19
-; GFX11-NEXT:    v_add_nc_u32_e32 v18, 3, v18
-; GFX11-NEXT:    v_add_nc_u32_e32 v17, 3, v17
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_add_nc_u32_e32 v32, 3, v32
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_nc_u32_e32 v31, 3, v31
-; GFX11-NEXT:    v_add_nc_u32_e32 v16, 3, v16
-; GFX11-NEXT:    v_add_nc_u32_e32 v15, 3, v15
-; GFX11-NEXT:    v_add_nc_u32_e32 v30, 3, v30
-; GFX11-NEXT:    v_add_nc_u32_e32 v29, 3, v29
-; GFX11-NEXT:    v_add_nc_u32_e32 v14, 3, v14
-; GFX11-NEXT:    v_add_nc_u32_e32 v13, 3, v13
-; GFX11-NEXT:    v_add_nc_u32_e32 v28, 3, v28
-; GFX11-NEXT:    v_add_nc_u32_e32 v27, 3, v27
-; GFX11-NEXT:    v_add_nc_u32_e32 v6, 3, v6
-; GFX11-NEXT:    v_add_nc_u32_e32 v5, 3, v5
-; GFX11-NEXT:    v_add_nc_u32_e32 v12, 3, v12
-; GFX11-NEXT:    v_add_nc_u32_e32 v11, 3, v11
-; GFX11-NEXT:    v_add_nc_u32_e32 v26, 3, v26
-; GFX11-NEXT:    v_add_nc_u32_e32 v25, 3, v25
-; GFX11-NEXT:    v_add_nc_u32_e32 v4, 3, v4
-; GFX11-NEXT:    v_add_nc_u32_e32 v3, 3, v3
-; GFX11-NEXT:    v_add_nc_u32_e32 v10, 3, v10
-; GFX11-NEXT:    v_add_nc_u32_e32 v9, 3, v9
-; GFX11-NEXT:    v_add_nc_u32_e32 v24, 3, v24
-; GFX11-NEXT:    v_add_nc_u32_e32 v23, 3, v23
-; GFX11-NEXT:    v_lshrrev_b64 v[48:49], 24, v[19:20]
-; GFX11-NEXT:    v_add_nc_u32_e32 v2, 3, v2
-; GFX11-NEXT:    v_add_nc_u32_e32 v1, 3, v1
-; GFX11-NEXT:    v_add_nc_u32_e32 v8, 3, v8
-; GFX11-NEXT:    v_add_nc_u32_e32 v7, 3, v7
-; GFX11-NEXT:    v_add_nc_u32_e32 v22, 3, v22
-; GFX11-NEXT:    v_add_nc_u32_e32 v21, 3, v21
-; GFX11-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
-; GFX11-NEXT:    v_lshrrev_b64 v[49:50], 24, v[17:18]
-; GFX11-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
-; GFX11-NEXT:    v_lshrrev_b64 v[50:51], 24, v[15:16]
-; GFX11-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
-; GFX11-NEXT:    v_lshrrev_b64 v[51:52], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
-; GFX11-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
-; GFX11-NEXT:    v_lshrrev_b64 v[64:65], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
-; GFX11-NEXT:    v_lshrrev_b64 v[53:54], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[65:66], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
-; GFX11-NEXT:    v_lshrrev_b64 v[54:55], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[66:67], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v68, 24, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v69, 16, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v70, 8, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v71, 16, v31
-; GFX11-NEXT:    v_lshrrev_b32_e32 v80, 8, v31
-; GFX11-NEXT:    v_lshrrev_b32_e32 v81, 24, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v82, 16, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v83, 8, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v84, 16, v29
-; GFX11-NEXT:    v_lshrrev_b32_e32 v85, 8, v29
-; GFX11-NEXT:    v_lshrrev_b32_e32 v86, 24, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v87, 16, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v96, 8, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v97, 16, v27
-; GFX11-NEXT:    v_lshrrev_b32_e32 v98, 8, v27
-; GFX11-NEXT:    v_lshrrev_b32_e32 v99, 24, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v100, 16, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v101, 8, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v102, 16, v25
-; GFX11-NEXT:    v_lshrrev_b32_e32 v103, 8, v25
-; GFX11-NEXT:    v_lshrrev_b32_e32 v112, 24, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v113, 16, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v114, 8, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v115, 16, v23
-; GFX11-NEXT:    v_lshrrev_b32_e32 v116, 8, v23
-; GFX11-NEXT:    v_lshrrev_b32_e32 v117, 24, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v118, 16, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v119, 8, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v128, 16, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v129, 8, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v130, 24, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v131, 16, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v132, 8, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v133, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v134, 8, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v135, 24, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v144, 16, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v145, 8, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v146, 16, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v147, 8, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v148, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v149, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v150, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v151, 16, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v160, 8, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v161, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v162, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v163, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v164, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v165, 8, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v166, 24, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v167, 16, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v176, 8, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v177, 16, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v178, 8, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v179, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v180, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v181, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v182, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v183, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v40, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v41, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v42, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v43, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v44, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v45, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v46, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v47, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v56, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v57, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v58, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v59, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v60, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v61, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v62, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v63, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v72, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v73, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v74, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v75, 8, v1
-; GFX11-NEXT:  .LBB6_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v75
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v66
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_lshlrev_b16 v66, 8, v63
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v65
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v55
-; GFX11-NEXT:    v_and_b32_e32 v55, 0xff, v74
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v67, 0xff, v61
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_or_b32_e32 v39, v55, v39
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v73
-; GFX11-NEXT:    v_or_b32_e32 v65, v67, v65
-; GFX11-NEXT:    v_lshlrev_b16 v67, 8, v58
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v39
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v55
-; GFX11-NEXT:    v_and_b32_e32 v55, 0xff, v72
-; GFX11-NEXT:    v_lshlrev_b16 v64, 8, v64
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v39
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_or_b32_e32 v55, v55, v66
-; GFX11-NEXT:    v_lshlrev_b16 v66, 8, v62
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v54
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v66
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v60
-; GFX11-NEXT:    v_and_b32_e32 v66, 0xff, v59
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v53
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v39
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v65
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v55
-; GFX11-NEXT:    v_or_b32_e32 v55, v66, v67
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v57
-; GFX11-NEXT:    v_and_b32_e32 v66, 0xff, v56
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v39
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v65
-; GFX11-NEXT:    v_or_b32_e32 v55, v66, v64
-; GFX11-NEXT:    v_lshlrev_b16 v64, 8, v47
-; GFX11-NEXT:    v_and_b32_e32 v65, 0xff, v46
-; GFX11-NEXT:    v_lshlrev_b16 v66, 8, v45
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v39
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v64
-; GFX11-NEXT:    v_or_b32_e32 v55, v65, v66
-; GFX11-NEXT:    v_lshlrev_b16 v64, 8, v44
-; GFX11-NEXT:    v_and_b32_e32 v65, 0xff, v43
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v39
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v64
-; GFX11-NEXT:    v_or_b32_e32 v54, v65, v54
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v42
-; GFX11-NEXT:    v_and_b32_e32 v64, 0xff, v41
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v40
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v39
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v54
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v55
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_or_b32_e32 v54, v64, v65
-; GFX11-NEXT:    v_and_b32_e32 v64, 0xff, v182
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v183
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v181
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v54, 16, v54
-; GFX11-NEXT:    v_or_b32_e32 v53, v64, v53
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v55
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v65
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v39
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v54
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v53
-; GFX11-NEXT:    v_and_b32_e32 v53, 0xff, v180
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v179
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v178
-; GFX11-NEXT:    v_and_b32_e32 v64, 0xff, v177
-; GFX11-NEXT:    v_lshlrev_b16 v52, 8, v52
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v176
-; GFX11-NEXT:    v_and_b32_e32 v66, 0xff, v167
-; GFX11-NEXT:    v_lshlrev_b16 v67, 8, v166
-; GFX11-NEXT:    v_or_b32_e32 v53, v53, v54
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v55
-; GFX11-NEXT:    v_or_b32_e32 v52, v64, v52
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v65
-; GFX11-NEXT:    v_or_b32_e32 v54, v66, v67
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v53, 16, v53
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v52, 16, v52
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v54, 16, v54
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off
-; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
-; GFX11-NEXT:    v_or_b32_e32 v1, v9, v39
-; GFX11-NEXT:    v_or_b32_e32 v2, v10, v53
-; GFX11-NEXT:    v_or_b32_e32 v3, v11, v52
-; GFX11-NEXT:    v_or_b32_e32 v4, v12, v54
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v13
-; GFX11-NEXT:    v_lshlrev_b16 v6, 8, v165
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v164
-; GFX11-NEXT:    v_lshlrev_b16 v8, 8, v51
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v14
-; GFX11-NEXT:    v_lshlrev_b16 v10, 8, v163
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v162
-; GFX11-NEXT:    v_lshlrev_b16 v12, 8, v161
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v15
-; GFX11-NEXT:    v_lshlrev_b16 v14, 8, v160
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v8, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v9, v13, v14
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v151
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v50
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v16
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v150
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v149
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v148
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v17
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v147
-; GFX11-NEXT:    v_and_b32_e32 v39, 0xff, v146
-; GFX11-NEXT:    v_lshlrev_b16 v49, 8, v49
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v11, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v12, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v13, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v14, v39, v49
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v8, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v9, v13, v14
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v18
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v145
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v144
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v135
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v19
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v134
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v133
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v48
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v20
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v132
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v11, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v12, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v13, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v14, v18, v19
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v131
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v130
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v21
-; GFX11-NEXT:    v_lshlrev_b16 v18, 8, v129
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v128
-; GFX11-NEXT:    v_lshlrev_b16 v20, 8, v38
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v22
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v119
-; GFX11-NEXT:    v_and_b32_e32 v38, 0xff, v118
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v117
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v16
-; GFX11-NEXT:    v_or_b32_e32 v16, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v17, v19, v20
-; GFX11-NEXT:    v_or_b32_e32 v18, v21, v22
-; GFX11-NEXT:    v_or_b32_e32 v19, v38, v39
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xffff, v18
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v11, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v12, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v13, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v14, v18, v19
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v23
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v116
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v115
-; GFX11-NEXT:    v_lshlrev_b16 v18, 8, v37
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v24
-; GFX11-NEXT:    v_lshlrev_b16 v20, 8, v114
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v113
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v112
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v25
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v103
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v16
-; GFX11-NEXT:    v_or_b32_e32 v16, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v17, v19, v20
-; GFX11-NEXT:    v_or_b32_e32 v18, v21, v22
-; GFX11-NEXT:    v_or_b32_e32 v19, v23, v24
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v102
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v36
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v26
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v101
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v100
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v99
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v27
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v98
-; GFX11-NEXT:    v_and_b32_e32 v36, 0xff, v97
-; GFX11-NEXT:    v_lshlrev_b16 v35, 8, v35
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v21, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v22, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v23, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v24, v36, v35
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff, v19
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xffff, v21
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xffff, v23
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v16
-; GFX11-NEXT:    v_or_b32_e32 v16, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v17, v19, v20
-; GFX11-NEXT:    v_or_b32_e32 v18, v21, v22
-; GFX11-NEXT:    v_or_b32_e32 v19, v23, v24
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v28
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v96
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v87
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v86
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v29
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v85
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v84
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v34
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v30
-; GFX11-NEXT:    v_lshlrev_b16 v29, 8, v83
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v21, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v22, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v23, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v24, v28, v29
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v82
-; GFX11-NEXT:    v_lshlrev_b16 v26, 8, v81
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v31
-; GFX11-NEXT:    v_lshlrev_b16 v28, 8, v80
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v71
-; GFX11-NEXT:    v_lshlrev_b16 v30, 8, v33
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v32
-; GFX11-NEXT:    v_lshlrev_b16 v32, 8, v70
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xff, v69
-; GFX11-NEXT:    v_lshlrev_b16 v34, 8, v68
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v26
-; GFX11-NEXT:    v_or_b32_e32 v26, v27, v28
-; GFX11-NEXT:    v_or_b32_e32 v27, v29, v30
-; GFX11-NEXT:    v_or_b32_e32 v28, v31, v32
-; GFX11-NEXT:    v_or_b32_e32 v29, v33, v34
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xffff, v20
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xffff, v22
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xffff, v24
-; GFX11-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xffff, v26
-; GFX11-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xffff, v28
-; GFX11-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v21, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v22, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v23, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v24, v28, v29
-; GFX11-NEXT:    s_clause 0x5
-; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off offset:32
-; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:48
-; GFX11-NEXT:    scratch_store_b128 v0, v[9:12], off offset:64
-; GFX11-NEXT:    scratch_store_b128 v0, v[13:16], off offset:80
-; GFX11-NEXT:    scratch_store_b128 v0, v[17:20], off offset:96
-; GFX11-NEXT:    scratch_store_b128 v0, v[21:24], off offset:112
-; GFX11-NEXT:    s_clause 0x13
-; GFX11-NEXT:    scratch_load_b32 v75, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_b32 v74, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_b32 v73, off, s32 offset:20
-; GFX11-NEXT:    scratch_load_b32 v72, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_b32 v63, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_b32 v62, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_b32 v61, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_b32 v60, off, s32 offset:40
-; GFX11-NEXT:    scratch_load_b32 v59, off, s32 offset:44
-; GFX11-NEXT:    scratch_load_b32 v58, off, s32 offset:48
-; GFX11-NEXT:    scratch_load_b32 v57, off, s32 offset:52
-; GFX11-NEXT:    scratch_load_b32 v56, off, s32 offset:56
-; GFX11-NEXT:    scratch_load_b32 v47, off, s32 offset:60
-; GFX11-NEXT:    scratch_load_b32 v46, off, s32 offset:64
-; GFX11-NEXT:    scratch_load_b32 v45, off, s32 offset:68
-; GFX11-NEXT:    scratch_load_b32 v44, off, s32 offset:72
-; GFX11-NEXT:    scratch_load_b32 v43, off, s32 offset:76
-; GFX11-NEXT:    scratch_load_b32 v42, off, s32 offset:80
-; GFX11-NEXT:    scratch_load_b32 v41, off, s32 offset:84
-; GFX11-NEXT:    scratch_load_b32 v40, off, s32 offset:88
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v32i32_to_v128i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x2
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v33, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr162_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr161_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr160_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr151_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr150_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr149_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr148_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr147_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr145_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr144_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr134_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr133_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr132_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr131_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr130_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr128_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr119_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr118_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr117_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr116_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr115_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr114_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr113_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr103_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr101_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr100_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr99_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr97_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr86_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr85_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr83_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr71_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr70_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr68_lo16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v33
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB6_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[48:49], 24, v[19:20]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[49:50], 24, v[17:18]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[50:51], 24, v[15:16]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[51:52], 24, v[13:14]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[64:65], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[53:54], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[65:66], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v68, 24, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v69, 8, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v70, 8, v31
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v71, 24, v30
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v80, 8, v30
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v81, 8, v29
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v82, 24, v28
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v83, 8, v28
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v84, 8, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v85, 24, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v86, 8, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v87, 8, v25
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v96, 24, v24
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v97, 8, v24
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v98, 8, v23
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v99, 24, v22
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v100, 8, v22
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v101, 8, v21
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v102, 24, v20
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v103, 8, v20
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v112, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v113, 24, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v114, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v115, 8, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v116, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v117, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v118, 8, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v119, 24, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v128, 8, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v129, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v130, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v131, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v132, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v133, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v134, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v135, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v144, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v145, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v146, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v147, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v148, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v149, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v150, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v151, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v160, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v161, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v162, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[54:55], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[66:67], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB6_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB6_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v20, 3, v20
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v19, 3, v19
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v18, 3, v18
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v17, 3, v17
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v32, 3, v32
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v31, 3, v31
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v16, 3, v16
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v15, 3, v15
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v30, 3, v30
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v29, 3, v29
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v14, 3, v14
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v13, 3, v13
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v28, 3, v28
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v27, 3, v27
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, 3, v6
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v5, 3, v5
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v12, 3, v12
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v11, 3, v11
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v26, 3, v26
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v25, 3, v25
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v4, 3, v4
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 3, v3
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v10, 3, v10
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v9, 3, v9
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v24, 3, v24
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v23, 3, v23
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[48:49], 24, v[19:20]
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 3, v2
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v1, 3, v1
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, 3, v8
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v7, 3, v7
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v22, 3, v22
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v21, 3, v21
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[49:50], 24, v[17:18]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[50:51], 24, v[15:16]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[51:52], 24, v[13:14]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[64:65], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[53:54], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[65:66], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[54:55], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[66:67], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v68, 24, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v69, 8, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v70, 8, v31
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v71, 24, v30
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v80, 8, v30
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v81, 8, v29
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v82, 24, v28
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v83, 8, v28
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v84, 8, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v85, 24, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v86, 8, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v87, 8, v25
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v96, 24, v24
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v97, 8, v24
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v98, 8, v23
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v99, 24, v22
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v100, 8, v22
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v101, 8, v21
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v102, 24, v20
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v103, 8, v20
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v112, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v113, 24, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v114, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v115, 8, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v116, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v117, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v118, 8, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v119, 24, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v128, 8, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v129, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v130, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v131, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v132, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v133, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v134, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v135, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v144, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v145, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v146, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v147, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v148, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v149, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v150, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v151, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v160, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v161, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v162, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB6_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v39.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v34.h, 8, v66.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v33.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v161.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v39.l, v1.h, v34.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v162.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v39
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.h, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v55, 0xffff, v55
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v160.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v150.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v66.l, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v67.l, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v65.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v55, v39
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v55, 0xffff, v66
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v65, 16, v67
+; GFX11-TRUE16-NEXT:    v_or_b16 v39.l, v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 8, v151.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v55, v65
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v39
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.h, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.h, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v149.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v55, 16, v55
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.l, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v66.l, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v64.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v3.h, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v39, v55
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v65
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v55, 16, v66
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v4.h, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.l, 8, v148.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v147.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v39, v55
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.h, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.h, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v54.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v64
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v146.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v55
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v5.h, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v39, v54
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v64
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v145.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v144.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v55
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v39, v54
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v55
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v53.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v134.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.l, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v8.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v135.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v10.l, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v53, 0xffff, v53
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v55, 16, v55
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v64
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.h, v8.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.l, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v11.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v53, v55
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v55, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v10.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v132.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v52.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v39, v54
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v133.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v11.h
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v129.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v131.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v34.h, 8, v130.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v51.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v33.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v39.l, v12.h, v34.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v10, v11
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v128.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v15.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v50.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v39
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v55, v9
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v14.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v119.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v118.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v6
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v12, v39
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v16.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v117.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v16.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v116.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v10, v11
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v114.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v115.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v18.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v113.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v12, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v14, v15
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v19.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v112.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v19.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v48.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v20.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v102.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v16, v17
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v20.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v103.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v11
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v21.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v101.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v14.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v21.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v38.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v15, v16
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.l, 0xff, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v98.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v14
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v100.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v17, v18
+; GFX11-TRUE16-NEXT:    v_and_b16 v16.l, 0xff, v23.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v37.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v97.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v15.l, v15.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v19, v20
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v24.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v96.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v25.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v87.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v16.l, v16.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v17.l, v17.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.l, 0xff, v25.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v36.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v21, v22
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v18.l, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v19.l, v19.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v16
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff, v17
+; GFX11-TRUE16-NEXT:    v_and_b16 v16.l, 0xff, v26.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v86.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v26.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v85.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v15.l, v15.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff, v19
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v16.l, v16.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v17.l, v17.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v15
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v27.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v84.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v27.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v16
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v20, v21
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, v22, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, v24, v25
+; GFX11-TRUE16-NEXT:    v_and_b16 v20.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v83.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v21.l, 0xff, v28.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.h, 8, v82.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v29.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v22.h, 8, v81.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v29.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.h, 8, v34.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v30.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v24.h, 8, v80.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v18.l, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v20.l, v20.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v21.l, v21.l, v21.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v22.l, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v23.l, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v24.l, v24.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v49.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v99.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v35.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v35, 0xffff, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v18, v26, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v20
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v21
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v27, 0xffff, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v23
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v29, 0xffff, v24
+; GFX11-TRUE16-NEXT:    v_and_b16 v20.l, 0xff, v30.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v71.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v21.l, 0xff, v31.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.h, 8, v70.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v31.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v22.h, 8, v33.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v32.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.h, 8, v69.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v32.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v24.h, 8, v68.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v14.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v19.l, v19.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v53, 0xffff, v64
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v65
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v20.l, v20.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v21.l, v21.l, v21.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v22.l, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v23.l, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v24.l, v24.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v53, v54
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v20
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff, v21
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v22
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v33, 0xffff, v23
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v39, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v38, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v19, v35, v19
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, v25, v26
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, v27, v28
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, v29, v30
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, v31, v32
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, v33, v24
+; GFX11-TRUE16-NEXT:    s_clause 0x5
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off offset:32
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:48
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[9:12], off offset:64
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[13:16], off offset:80
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[17:20], off offset:96
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[21:24], off offset:112
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v32i32_to_v128i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x13
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s32 offset:88
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v41, s32 offset:84
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v42, s32 offset:80
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v43, s32 offset:76
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v44, s32 offset:72
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v45, s32 offset:68
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v46, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v47, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v56, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v57, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v58, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v59, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v60, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v61, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v62, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v63, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v72, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v73, s32 offset:20
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v74, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v75, s32 offset:12
+; GFX11-FAKE16-NEXT:    s_clause 0x2
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v33, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr75
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr74
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr73
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr72
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr63
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr62
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr61
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr60
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr59
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr58
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr57
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr56
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr47
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr46
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr45
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr44
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr43
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr42
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr41
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr40
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr183
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr182
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr181
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr180
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr179
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr178
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr177
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr176
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr167
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr166
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr165
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr164
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr163
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr162
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr161
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr160
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr151
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr150
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr149
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr148
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr147
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr144
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr135
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB6_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[48:49], 24, v[19:20]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[49:50], 24, v[17:18]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[50:51], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[51:52], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[64:65], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[53:54], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[65:66], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v68, 24, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v69, 16, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v70, 8, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 16, v31
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 8, v31
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v81, 24, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v82, 16, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 8, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 16, v29
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v85, 8, v29
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v86, 24, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 16, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 8, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v97, 16, v27
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v98, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v99, 24, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v100, 16, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v101, 8, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v102, 16, v25
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v103, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v112, 24, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v113, 16, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v114, 8, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v115, 16, v23
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v116, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v117, 24, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v118, 16, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v119, 8, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v128, 16, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v129, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v130, 24, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v131, 16, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v132, 8, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v133, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v134, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v135, 24, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v144, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v145, 8, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v146, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v147, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v148, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v149, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v150, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v151, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v160, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v161, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v162, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v163, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v164, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v165, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v166, 24, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v167, 16, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v176, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v177, 16, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v178, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v179, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v180, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v181, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v182, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v183, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v40, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v41, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v42, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v43, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v44, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v45, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v46, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v47, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v56, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v57, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v58, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v59, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v60, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v61, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v62, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v63, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v72, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v73, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v74, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v75, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[54:55], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[66:67], 24, v[1:2]
+; GFX11-FAKE16-NEXT:  .LBB6_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB6_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v20, 3, v20
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v19, 3, v19
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v18, 3, v18
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v17, 3, v17
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v32, 3, v32
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v31, 3, v31
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v16, 3, v16
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v15, 3, v15
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v30, 3, v30
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v29, 3, v29
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v14, 3, v14
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v13, 3, v13
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v28, 3, v28
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v27, 3, v27
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, 3, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v5, 3, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v12, 3, v12
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v11, 3, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v26, 3, v26
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v25, 3, v25
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 3, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, 3, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v10, 3, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v9, 3, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v24, 3, v24
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v23, 3, v23
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[48:49], 24, v[19:20]
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, 3, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v1, 3, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, 3, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v7, 3, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v22, 3, v22
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v21, 3, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[49:50], 24, v[17:18]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[50:51], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[51:52], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[64:65], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[53:54], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[65:66], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[54:55], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[66:67], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v68, 24, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v69, 16, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v70, 8, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 16, v31
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 8, v31
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v81, 24, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v82, 16, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 8, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 16, v29
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v85, 8, v29
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v86, 24, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 16, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 8, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v97, 16, v27
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v98, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v99, 24, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v100, 16, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v101, 8, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v102, 16, v25
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v103, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v112, 24, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v113, 16, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v114, 8, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v115, 16, v23
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v116, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v117, 24, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v118, 16, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v119, 8, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v128, 16, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v129, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v130, 24, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v131, 16, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v132, 8, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v133, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v134, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v135, 24, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v144, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v145, 8, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v146, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v147, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v148, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v149, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v150, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v151, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v160, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v161, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v162, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v163, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v164, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v165, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v166, 24, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v167, 16, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v176, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v177, 16, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v178, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v179, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v180, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v181, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v182, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v183, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v40, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v41, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v42, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v43, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v44, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v45, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v46, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v47, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v56, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v57, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v58, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v59, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v60, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v61, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v62, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v63, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v72, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v73, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v74, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v75, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB6_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v75
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v66
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v66, 8, v63
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v55, 0xff, v74
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v67, 0xff, v61
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v39, v55, v39
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v73
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v65, v67, v65
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v67, 8, v58
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v55, 0xff, v72
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v64, 8, v64
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, v55, v66
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v66, 8, v62
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v66
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v60
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v66, 0xff, v59
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v53, 8, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, v66, v67
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v57
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v66, 0xff, v56
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, v66, v64
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v64, 8, v47
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v65, 0xff, v46
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v66, 8, v45
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v64
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, v65, v66
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v64, 8, v44
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v65, 0xff, v43
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v64
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v54, v65, v54
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v42
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v64, 0xff, v41
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v40
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v39
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v54, v64, v65
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v64, 0xff, v182
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v183
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v181
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v53, v64, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v54
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v53
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v53, 0xff, v180
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v179
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v178
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v64, 0xff, v177
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v52, 8, v52
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v176
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v66, 0xff, v167
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v67, 8, v166
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v53, v53, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v52, v64, v52
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v54, v66, v67
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v53, 16, v53
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v52, 16, v52
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v54
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v9, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v10, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v11, v52
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v12, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v6, 8, v165
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v164
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v51
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v10, 8, v163
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v162
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v12, 8, v161
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v14, 8, v160
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v13, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v151
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v50
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v150
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v149
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v148
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v147
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v39, 0xff, v146
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v49, 8, v49
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v39, v49
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v13, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v145
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v144
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v135
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v134
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v133
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v48
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v132
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v18, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v131
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v130
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v18, 8, v129
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v128
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v38
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v119
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v38, 0xff, v118
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v117
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v19, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v21, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v38, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xffff, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v18, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v116
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v115
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v18, 8, v37
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v114
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v113
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v112
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v103
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v19, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v21, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v23, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v102
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v101
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v100
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v99
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v98
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v36, 0xff, v97
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v35, 8, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v36, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xffff, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v19, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v21, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v23, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v96
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v87
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v86
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v29
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v84
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v29, 8, v83
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v28, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v82
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v26, 8, v81
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v28, 8, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v71
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v30, 8, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v32, 8, v70
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xff, v69
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v34, 8, v68
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v27, v28
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v29, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v31, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v33, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xffff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xffff, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xffff, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xffff, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xffff, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v28, v29
+; GFX11-FAKE16-NEXT:    s_clause 0x5
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off offset:32
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:48
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[9:12], off offset:64
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[13:16], off offset:80
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[17:20], off offset:96
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[21:24], off offset:112
+; GFX11-FAKE16-NEXT:    s_clause 0x13
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v75, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v74, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v73, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v72, off, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v63, off, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v62, off, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v61, off, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v60, off, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v59, off, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v58, off, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v57, off, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v56, off, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v47, off, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v46, off, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v45, off, s32 offset:68
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v44, off, s32 offset:72
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v43, off, s32 offset:76
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v42, off, s32 offset:80
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v41, off, s32 offset:84
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s32 offset:88
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -9225,1038 +9791,1985 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v128i8_to_v32i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_store_b32 off, v40, s32 offset:592
-; GFX11-NEXT:    scratch_store_b32 off, v41, s32 offset:588
-; GFX11-NEXT:    scratch_store_b32 off, v42, s32 offset:584
-; GFX11-NEXT:    scratch_store_b32 off, v43, s32 offset:580
-; GFX11-NEXT:    scratch_store_b32 off, v44, s32 offset:576
-; GFX11-NEXT:    scratch_store_b32 off, v45, s32 offset:572
-; GFX11-NEXT:    scratch_store_b32 off, v46, s32 offset:568
-; GFX11-NEXT:    scratch_store_b32 off, v47, s32 offset:564
-; GFX11-NEXT:    scratch_store_b32 off, v56, s32 offset:560
-; GFX11-NEXT:    scratch_store_b32 off, v57, s32 offset:556
-; GFX11-NEXT:    scratch_store_b32 off, v58, s32 offset:552
-; GFX11-NEXT:    scratch_store_b32 off, v59, s32 offset:548
-; GFX11-NEXT:    scratch_store_b32 off, v60, s32 offset:544
-; GFX11-NEXT:    scratch_store_b32 off, v61, s32 offset:540
-; GFX11-NEXT:    scratch_store_b32 off, v62, s32 offset:536
-; GFX11-NEXT:    scratch_store_b32 off, v63, s32 offset:532
-; GFX11-NEXT:    scratch_store_b32 off, v72, s32 offset:528
-; GFX11-NEXT:    scratch_store_b32 off, v73, s32 offset:524
-; GFX11-NEXT:    scratch_store_b32 off, v74, s32 offset:520
-; GFX11-NEXT:    scratch_store_b32 off, v75, s32 offset:516
-; GFX11-NEXT:    scratch_store_b32 off, v76, s32 offset:512
-; GFX11-NEXT:    scratch_store_b32 off, v77, s32 offset:508
-; GFX11-NEXT:    scratch_store_b32 off, v78, s32 offset:504
-; GFX11-NEXT:    scratch_store_b32 off, v79, s32 offset:500
-; GFX11-NEXT:    scratch_store_b32 off, v88, s32 offset:496
-; GFX11-NEXT:    scratch_store_b32 off, v89, s32 offset:492
-; GFX11-NEXT:    scratch_store_b32 off, v90, s32 offset:488
-; GFX11-NEXT:    scratch_store_b32 off, v91, s32 offset:484
-; GFX11-NEXT:    scratch_store_b32 off, v92, s32 offset:480
-; GFX11-NEXT:    scratch_store_b32 off, v93, s32 offset:476
-; GFX11-NEXT:    scratch_store_b32 off, v94, s32 offset:472
-; GFX11-NEXT:    scratch_store_b32 off, v95, s32 offset:468
-; GFX11-NEXT:    s_clause 0x12
-; GFX11-NEXT:    scratch_store_b32 off, v104, s32 offset:464
-; GFX11-NEXT:    scratch_store_b32 off, v105, s32 offset:460
-; GFX11-NEXT:    scratch_store_b32 off, v106, s32 offset:456
-; GFX11-NEXT:    scratch_store_b32 off, v107, s32 offset:452
-; GFX11-NEXT:    scratch_store_b32 off, v108, s32 offset:448
-; GFX11-NEXT:    scratch_store_b32 off, v109, s32 offset:444
-; GFX11-NEXT:    scratch_store_b32 off, v110, s32 offset:440
-; GFX11-NEXT:    scratch_store_b32 off, v111, s32 offset:436
-; GFX11-NEXT:    scratch_store_b32 off, v120, s32 offset:432
-; GFX11-NEXT:    scratch_store_b32 off, v121, s32 offset:428
-; GFX11-NEXT:    scratch_store_b32 off, v122, s32 offset:424
-; GFX11-NEXT:    scratch_store_b32 off, v123, s32 offset:420
-; GFX11-NEXT:    scratch_store_b32 off, v124, s32 offset:416
-; GFX11-NEXT:    scratch_store_b32 off, v125, s32 offset:412
-; GFX11-NEXT:    scratch_store_b32 off, v126, s32 offset:408
-; GFX11-NEXT:    scratch_store_b32 off, v127, s32 offset:404
-; GFX11-NEXT:    scratch_store_b32 off, v136, s32 offset:400
-; GFX11-NEXT:    scratch_store_b32 off, v137, s32 offset:396
-; GFX11-NEXT:    scratch_store_b32 off, v138, s32 offset:392
-; GFX11-NEXT:    v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28
-; GFX11-NEXT:    v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24
-; GFX11-NEXT:    v_dual_mov_b32 v36, v22 :: v_dual_mov_b32 v37, v20
-; GFX11-NEXT:    v_dual_mov_b32 v38, v18 :: v_dual_mov_b32 v39, v16
-; GFX11-NEXT:    v_dual_mov_b32 v48, v14 :: v_dual_mov_b32 v49, v12
-; GFX11-NEXT:    v_dual_mov_b32 v50, v10 :: v_dual_mov_b32 v51, v8
-; GFX11-NEXT:    v_dual_mov_b32 v52, v6 :: v_dual_mov_b32 v53, v4
-; GFX11-NEXT:    v_dual_mov_b32 v54, v2 :: v_dual_mov_b32 v55, v0
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v0, off, s32 offset:384
-; GFX11-NEXT:    scratch_load_u16 v64, off, s32 offset:380
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32 offset:376
-; GFX11-NEXT:    scratch_load_u16 v65, off, s32 offset:372
-; GFX11-NEXT:    scratch_load_u16 v4, off, s32 offset:368
-; GFX11-NEXT:    scratch_load_u16 v66, off, s32 offset:364
-; GFX11-NEXT:    scratch_load_u16 v6, off, s32 offset:360
-; GFX11-NEXT:    scratch_load_u16 v67, off, s32 offset:356
-; GFX11-NEXT:    scratch_load_u16 v8, off, s32 offset:352
-; GFX11-NEXT:    scratch_load_u16 v68, off, s32 offset:348
-; GFX11-NEXT:    scratch_load_u16 v10, off, s32 offset:344
-; GFX11-NEXT:    scratch_load_u16 v69, off, s32 offset:340
-; GFX11-NEXT:    scratch_load_u16 v12, off, s32 offset:336
-; GFX11-NEXT:    scratch_load_u16 v70, off, s32 offset:332
-; GFX11-NEXT:    scratch_load_u16 v14, off, s32 offset:328
-; GFX11-NEXT:    scratch_load_u16 v71, off, s32 offset:324
-; GFX11-NEXT:    scratch_load_u16 v16, off, s32 offset:320
-; GFX11-NEXT:    scratch_load_u16 v80, off, s32 offset:316
-; GFX11-NEXT:    scratch_load_u16 v18, off, s32 offset:312
-; GFX11-NEXT:    scratch_load_u16 v81, off, s32 offset:308
-; GFX11-NEXT:    scratch_load_u16 v20, off, s32 offset:304
-; GFX11-NEXT:    scratch_load_u16 v82, off, s32 offset:300
-; GFX11-NEXT:    scratch_load_u16 v22, off, s32 offset:296
-; GFX11-NEXT:    scratch_load_u16 v83, off, s32 offset:292
-; GFX11-NEXT:    scratch_load_u16 v24, off, s32 offset:288
-; GFX11-NEXT:    scratch_load_u16 v84, off, s32 offset:284
-; GFX11-NEXT:    scratch_load_u16 v26, off, s32 offset:280
-; GFX11-NEXT:    scratch_load_u16 v85, off, s32 offset:276
-; GFX11-NEXT:    scratch_load_u16 v28, off, s32 offset:272
-; GFX11-NEXT:    scratch_load_u16 v86, off, s32 offset:268
-; GFX11-NEXT:    scratch_load_u16 v30, off, s32 offset:264
-; GFX11-NEXT:    scratch_load_u16 v87, off, s32 offset:260
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v31, off, s32 offset:256
-; GFX11-NEXT:    scratch_load_u16 v96, off, s32 offset:252
-; GFX11-NEXT:    scratch_load_u16 v99, off, s32 offset:248
-; GFX11-NEXT:    scratch_load_u16 v97, off, s32 offset:244
-; GFX11-NEXT:    scratch_load_u16 v100, off, s32 offset:240
-; GFX11-NEXT:    scratch_load_u16 v98, off, s32 offset:236
-; GFX11-NEXT:    scratch_load_u16 v101, off, s32 offset:232
-; GFX11-NEXT:    scratch_load_u16 v112, off, s32 offset:228
-; GFX11-NEXT:    scratch_load_u16 v102, off, s32 offset:224
-; GFX11-NEXT:    scratch_load_u16 v113, off, s32 offset:220
-; GFX11-NEXT:    scratch_load_u16 v103, off, s32 offset:216
-; GFX11-NEXT:    scratch_load_b32 v114, off, s32 offset:388
-; GFX11-NEXT:    scratch_load_u16 v115, off, s32
-; GFX11-NEXT:    scratch_load_u16 v116, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_u16 v117, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_u16 v118, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_u16 v119, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_u16 v128, off, s32 offset:40
-; GFX11-NEXT:    scratch_load_u16 v129, off, s32 offset:48
-; GFX11-NEXT:    scratch_load_u16 v130, off, s32 offset:56
-; GFX11-NEXT:    scratch_load_u16 v131, off, s32 offset:64
-; GFX11-NEXT:    scratch_load_u16 v144, off, s32 offset:72
-; GFX11-NEXT:    scratch_load_u16 v145, off, s32 offset:80
-; GFX11-NEXT:    scratch_load_u16 v146, off, s32 offset:88
-; GFX11-NEXT:    scratch_load_u16 v147, off, s32 offset:96
-; GFX11-NEXT:    scratch_load_u16 v148, off, s32 offset:104
-; GFX11-NEXT:    scratch_load_u16 v162, off, s32 offset:112
-; GFX11-NEXT:    scratch_load_u16 v163, off, s32 offset:120
-; GFX11-NEXT:    scratch_load_u16 v164, off, s32 offset:128
-; GFX11-NEXT:    scratch_load_u16 v165, off, s32 offset:136
-; GFX11-NEXT:    scratch_load_u16 v166, off, s32 offset:144
-; GFX11-NEXT:    scratch_load_u16 v179, off, s32 offset:152
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v180, off, s32 offset:160
-; GFX11-NEXT:    scratch_load_u16 v181, off, s32 offset:168
-; GFX11-NEXT:    scratch_load_u16 v182, off, s32 offset:176
-; GFX11-NEXT:    scratch_load_u16 v183, off, s32 offset:184
-; GFX11-NEXT:    scratch_load_u16 v136, off, s32 offset:192
-; GFX11-NEXT:    scratch_load_u16 v137, off, s32 offset:200
-; GFX11-NEXT:    scratch_load_u16 v138, off, s32 offset:208
-; GFX11-NEXT:    scratch_load_u16 v132, off, s32 offset:212
-; GFX11-NEXT:    scratch_load_u16 v133, off, s32 offset:204
-; GFX11-NEXT:    scratch_load_u16 v134, off, s32 offset:196
-; GFX11-NEXT:    scratch_load_u16 v135, off, s32 offset:188
-; GFX11-NEXT:    scratch_load_u16 v149, off, s32 offset:180
-; GFX11-NEXT:    scratch_load_u16 v150, off, s32 offset:172
-; GFX11-NEXT:    scratch_load_u16 v151, off, s32 offset:164
-; GFX11-NEXT:    scratch_load_u16 v160, off, s32 offset:156
-; GFX11-NEXT:    scratch_load_u16 v161, off, s32 offset:148
-; GFX11-NEXT:    scratch_load_u16 v167, off, s32 offset:140
-; GFX11-NEXT:    scratch_load_u16 v176, off, s32 offset:132
-; GFX11-NEXT:    scratch_load_u16 v177, off, s32 offset:124
-; GFX11-NEXT:    scratch_load_u16 v178, off, s32 offset:116
-; GFX11-NEXT:    scratch_load_u16 v40, off, s32 offset:108
-; GFX11-NEXT:    scratch_load_u16 v41, off, s32 offset:100
-; GFX11-NEXT:    scratch_load_u16 v42, off, s32 offset:92
-; GFX11-NEXT:    scratch_load_u16 v43, off, s32 offset:84
-; GFX11-NEXT:    scratch_load_u16 v44, off, s32 offset:76
-; GFX11-NEXT:    scratch_load_u16 v58, off, s32 offset:68
-; GFX11-NEXT:    scratch_load_u16 v59, off, s32 offset:60
-; GFX11-NEXT:    scratch_load_u16 v60, off, s32 offset:52
-; GFX11-NEXT:    scratch_load_u16 v74, off, s32 offset:44
-; GFX11-NEXT:    scratch_load_u16 v75, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_u16 v76, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_u16 v77, off, s32 offset:20
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_u16 v78, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_u16 v92, off, s32 offset:4
-; GFX11-NEXT:    v_lshlrev_b16 v124, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v125, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v126, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v127, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v111, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v120, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v121, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v122, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v123, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v106, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v107, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v108, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v109, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v110, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v93, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(54)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v114
-; GFX11-NEXT:    s_waitcnt vmcnt(53)
-; GFX11-NEXT:    v_lshlrev_b16 v94, 8, v115
-; GFX11-NEXT:    s_waitcnt vmcnt(52)
-; GFX11-NEXT:    v_lshlrev_b16 v95, 8, v116
-; GFX11-NEXT:    s_waitcnt vmcnt(51)
-; GFX11-NEXT:    v_lshlrev_b16 v104, 8, v117
-; GFX11-NEXT:    s_waitcnt vmcnt(50)
-; GFX11-NEXT:    v_lshlrev_b16 v105, 8, v118
-; GFX11-NEXT:    s_waitcnt vmcnt(49)
-; GFX11-NEXT:    v_lshlrev_b16 v79, 8, v119
-; GFX11-NEXT:    s_waitcnt vmcnt(48)
-; GFX11-NEXT:    v_lshlrev_b16 v88, 8, v128
-; GFX11-NEXT:    s_waitcnt vmcnt(47)
-; GFX11-NEXT:    v_lshlrev_b16 v89, 8, v129
-; GFX11-NEXT:    s_waitcnt vmcnt(46)
-; GFX11-NEXT:    v_lshlrev_b16 v90, 8, v130
-; GFX11-NEXT:    s_waitcnt vmcnt(45)
-; GFX11-NEXT:    v_lshlrev_b16 v91, 8, v131
-; GFX11-NEXT:    s_waitcnt vmcnt(44)
-; GFX11-NEXT:    v_lshlrev_b16 v61, 8, v144
-; GFX11-NEXT:    s_waitcnt vmcnt(43)
-; GFX11-NEXT:    v_lshlrev_b16 v62, 8, v145
-; GFX11-NEXT:    s_waitcnt vmcnt(42)
-; GFX11-NEXT:    v_lshlrev_b16 v63, 8, v146
-; GFX11-NEXT:    s_waitcnt vmcnt(41)
-; GFX11-NEXT:    v_lshlrev_b16 v72, 8, v147
-; GFX11-NEXT:    s_waitcnt vmcnt(40)
-; GFX11-NEXT:    v_lshlrev_b16 v73, 8, v148
-; GFX11-NEXT:    s_waitcnt vmcnt(39)
-; GFX11-NEXT:    v_lshlrev_b16 v45, 8, v162
-; GFX11-NEXT:    s_waitcnt vmcnt(38)
-; GFX11-NEXT:    v_lshlrev_b16 v46, 8, v163
-; GFX11-NEXT:    s_waitcnt vmcnt(37)
-; GFX11-NEXT:    v_lshlrev_b16 v47, 8, v164
-; GFX11-NEXT:    s_waitcnt vmcnt(36)
-; GFX11-NEXT:    v_lshlrev_b16 v56, 8, v165
-; GFX11-NEXT:    s_waitcnt vmcnt(35)
-; GFX11-NEXT:    v_lshlrev_b16 v57, 8, v166
-; GFX11-NEXT:    s_waitcnt vmcnt(34)
-; GFX11-NEXT:    v_lshlrev_b16 v179, 8, v179
-; GFX11-NEXT:    s_waitcnt vmcnt(33)
-; GFX11-NEXT:    v_lshlrev_b16 v180, 8, v180
-; GFX11-NEXT:    s_waitcnt vmcnt(32)
-; GFX11-NEXT:    v_lshlrev_b16 v181, 8, v181
-; GFX11-NEXT:    s_waitcnt vmcnt(31)
-; GFX11-NEXT:    v_lshlrev_b16 v182, 8, v182
-; GFX11-NEXT:    s_waitcnt vmcnt(30)
-; GFX11-NEXT:    v_lshlrev_b16 v183, 8, v183
-; GFX11-NEXT:    s_waitcnt vmcnt(29)
-; GFX11-NEXT:    v_lshlrev_b16 v162, 8, v136
-; GFX11-NEXT:    s_waitcnt vmcnt(28)
-; GFX11-NEXT:    v_lshlrev_b16 v163, 8, v137
-; GFX11-NEXT:    s_waitcnt vmcnt(27)
-; GFX11-NEXT:    v_lshlrev_b16 v164, 8, v138
-; GFX11-NEXT:    v_lshlrev_b16 v165, 8, v103
-; GFX11-NEXT:    v_lshlrev_b16 v166, 8, v102
-; GFX11-NEXT:    v_lshlrev_b16 v144, 8, v101
-; GFX11-NEXT:    v_lshlrev_b16 v145, 8, v100
-; GFX11-NEXT:    v_lshlrev_b16 v146, 8, v99
-; GFX11-NEXT:    v_lshlrev_b16 v147, 8, v31
-; GFX11-NEXT:    v_lshlrev_b16 v148, 8, v30
-; GFX11-NEXT:    v_lshlrev_b16 v119, 8, v28
-; GFX11-NEXT:    v_lshlrev_b16 v128, 8, v26
-; GFX11-NEXT:    v_lshlrev_b16 v129, 8, v24
-; GFX11-NEXT:    v_lshlrev_b16 v130, 8, v22
-; GFX11-NEXT:    v_lshlrev_b16 v131, 8, v20
-; GFX11-NEXT:    v_lshlrev_b16 v114, 8, v18
-; GFX11-NEXT:    v_lshlrev_b16 v115, 8, v16
-; GFX11-NEXT:    v_lshlrev_b16 v116, 8, v14
-; GFX11-NEXT:    v_lshlrev_b16 v117, 8, v12
-; GFX11-NEXT:    v_lshlrev_b16 v118, 8, v10
-; GFX11-NEXT:    v_lshlrev_b16 v99, 8, v8
-; GFX11-NEXT:    v_lshlrev_b16 v100, 8, v6
-; GFX11-NEXT:    v_lshlrev_b16 v101, 8, v4
-; GFX11-NEXT:    v_lshlrev_b16 v102, 8, v2
-; GFX11-NEXT:    v_lshlrev_b16 v103, 8, v0
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB7_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v55
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v54
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v53
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v52
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v51
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v124
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v125
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v126
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v127
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v50
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v39
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v37
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v36
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v49
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v48
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v35
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v34
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v111
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v121
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v120
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v122
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v123
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v107
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v2
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v38
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v108
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v109
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v110
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v106
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v3, v7, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v6, v12
-; GFX11-NEXT:    v_or_b32_e32 v5, v8, v9
-; GFX11-NEXT:    v_or_b32_e32 v6, v10, v11
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v32
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v92
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v78
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v77
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v76
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v75
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v74
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v60
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v59
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v93
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v94
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v95
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v104
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v105
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v79
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v88
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v89
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v90
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v91
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v8, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v9, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v10, v13, v14
-; GFX11-NEXT:    v_or_b32_e32 v11, v15, v16
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v58
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v44
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v43
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v42
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v41
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v40
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v178
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v177
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v176
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v167
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v61
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v62
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v63
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v72
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v73
-; GFX11-NEXT:    v_or_b32_e32 v17, v17, v45
-; GFX11-NEXT:    v_or_b32_e32 v18, v18, v46
-; GFX11-NEXT:    v_or_b32_e32 v19, v19, v47
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v56
-; GFX11-NEXT:    v_or_b32_e32 v21, v21, v57
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xffff, v18
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xffff, v20
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v13, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v14, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v15, v18, v19
-; GFX11-NEXT:    v_or_b32_e32 v16, v20, v21
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v161
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v160
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v151
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v150
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v149
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v135
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v134
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v133
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v132
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v113
-; GFX11-NEXT:    v_or_b32_e32 v17, v17, v179
-; GFX11-NEXT:    v_or_b32_e32 v18, v18, v180
-; GFX11-NEXT:    v_or_b32_e32 v19, v19, v181
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v182
-; GFX11-NEXT:    v_or_b32_e32 v21, v21, v183
-; GFX11-NEXT:    v_or_b32_e32 v22, v22, v162
-; GFX11-NEXT:    v_or_b32_e32 v23, v23, v163
-; GFX11-NEXT:    v_or_b32_e32 v24, v24, v164
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v165
-; GFX11-NEXT:    v_or_b32_e32 v26, v26, v166
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff, v19
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xffff, v21
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xffff, v23
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xffff, v25
-; GFX11-NEXT:    v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-NEXT:    v_or_b32_e32 v17, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v18, v19, v20
-; GFX11-NEXT:    v_or_b32_e32 v19, v21, v22
-; GFX11-NEXT:    v_or_b32_e32 v20, v23, v24
-; GFX11-NEXT:    v_or_b32_e32 v21, v25, v26
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v112
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v98
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v97
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v96
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v87
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v86
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v85
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v84
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v83
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v82
-; GFX11-NEXT:    v_or_b32_e32 v22, v22, v144
-; GFX11-NEXT:    v_or_b32_e32 v23, v23, v145
-; GFX11-NEXT:    v_or_b32_e32 v24, v24, v146
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v147
-; GFX11-NEXT:    v_or_b32_e32 v26, v26, v148
-; GFX11-NEXT:    v_or_b32_e32 v27, v27, v119
-; GFX11-NEXT:    v_or_b32_e32 v28, v28, v128
-; GFX11-NEXT:    v_or_b32_e32 v29, v29, v129
-; GFX11-NEXT:    v_or_b32_e32 v30, v30, v130
-; GFX11-NEXT:    v_or_b32_e32 v31, v31, v131
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xffff, v22
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xffff, v24
-; GFX11-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xffff, v26
-; GFX11-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xffff, v28
-; GFX11-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xffff, v30
-; GFX11-NEXT:    v_lshlrev_b32_e32 v31, 16, v31
-; GFX11-NEXT:    v_or_b32_e32 v22, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v23, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v24, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v25, v28, v29
-; GFX11-NEXT:    v_or_b32_e32 v26, v30, v31
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v81
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v80
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v71
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v70
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v69
-; GFX11-NEXT:    v_and_b32_e32 v32, 0xff, v68
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xff, v67
-; GFX11-NEXT:    v_and_b32_e32 v34, 0xff, v66
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xff, v65
-; GFX11-NEXT:    v_and_b32_e32 v36, 0xff, v64
-; GFX11-NEXT:    v_or_b32_e32 v27, v27, v114
-; GFX11-NEXT:    v_or_b32_e32 v28, v28, v115
-; GFX11-NEXT:    v_or_b32_e32 v29, v29, v116
-; GFX11-NEXT:    v_or_b32_e32 v30, v30, v117
-; GFX11-NEXT:    v_or_b32_e32 v31, v31, v118
-; GFX11-NEXT:    v_or_b32_e32 v32, v32, v99
-; GFX11-NEXT:    v_or_b32_e32 v33, v33, v100
-; GFX11-NEXT:    v_or_b32_e32 v34, v34, v101
-; GFX11-NEXT:    v_or_b32_e32 v35, v35, v102
-; GFX11-NEXT:    v_or_b32_e32 v36, v36, v103
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xffff, v27
-; GFX11-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xffff, v29
-; GFX11-NEXT:    v_lshlrev_b32_e32 v30, 16, v30
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xffff, v31
-; GFX11-NEXT:    v_lshlrev_b32_e32 v32, 16, v32
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xffff, v33
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v34
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xffff, v35
-; GFX11-NEXT:    v_lshlrev_b32_e32 v36, 16, v36
-; GFX11-NEXT:    v_or_b32_e32 v27, v27, v28
-; GFX11-NEXT:    v_or_b32_e32 v28, v29, v30
-; GFX11-NEXT:    v_or_b32_e32 v29, v31, v32
-; GFX11-NEXT:    v_or_b32_e32 v30, v33, v34
-; GFX11-NEXT:    v_or_b32_e32 v31, v35, v36
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr92
-; GFX11-NEXT:    ; implicit-def: $vgpr78
-; GFX11-NEXT:    ; implicit-def: $vgpr77
-; GFX11-NEXT:    ; implicit-def: $vgpr76
-; GFX11-NEXT:    ; implicit-def: $vgpr75
-; GFX11-NEXT:    ; implicit-def: $vgpr74
-; GFX11-NEXT:    ; implicit-def: $vgpr60
-; GFX11-NEXT:    ; implicit-def: $vgpr59
-; GFX11-NEXT:    ; implicit-def: $vgpr58
-; GFX11-NEXT:    ; implicit-def: $vgpr44
-; GFX11-NEXT:    ; implicit-def: $vgpr43
-; GFX11-NEXT:    ; implicit-def: $vgpr42
-; GFX11-NEXT:    ; implicit-def: $vgpr41
-; GFX11-NEXT:    ; implicit-def: $vgpr40
-; GFX11-NEXT:    ; implicit-def: $vgpr178
-; GFX11-NEXT:    ; implicit-def: $vgpr177
-; GFX11-NEXT:    ; implicit-def: $vgpr176
-; GFX11-NEXT:    ; implicit-def: $vgpr167
-; GFX11-NEXT:    ; implicit-def: $vgpr161
-; GFX11-NEXT:    ; implicit-def: $vgpr160
-; GFX11-NEXT:    ; implicit-def: $vgpr151
-; GFX11-NEXT:    ; implicit-def: $vgpr150
-; GFX11-NEXT:    ; implicit-def: $vgpr149
-; GFX11-NEXT:    ; implicit-def: $vgpr135
-; GFX11-NEXT:    ; implicit-def: $vgpr134
-; GFX11-NEXT:    ; implicit-def: $vgpr133
-; GFX11-NEXT:    ; implicit-def: $vgpr132
-; GFX11-NEXT:    ; implicit-def: $vgpr113
-; GFX11-NEXT:    ; implicit-def: $vgpr112
-; GFX11-NEXT:    ; implicit-def: $vgpr98
-; GFX11-NEXT:    ; implicit-def: $vgpr97
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr67
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr124
-; GFX11-NEXT:    ; implicit-def: $vgpr125
-; GFX11-NEXT:    ; implicit-def: $vgpr126
-; GFX11-NEXT:    ; implicit-def: $vgpr127
-; GFX11-NEXT:    ; implicit-def: $vgpr111
-; GFX11-NEXT:    ; implicit-def: $vgpr120
-; GFX11-NEXT:    ; implicit-def: $vgpr121
-; GFX11-NEXT:    ; implicit-def: $vgpr122
-; GFX11-NEXT:    ; implicit-def: $vgpr123
-; GFX11-NEXT:    ; implicit-def: $vgpr106
-; GFX11-NEXT:    ; implicit-def: $vgpr107
-; GFX11-NEXT:    ; implicit-def: $vgpr108
-; GFX11-NEXT:    ; implicit-def: $vgpr109
-; GFX11-NEXT:    ; implicit-def: $vgpr110
-; GFX11-NEXT:    ; implicit-def: $vgpr93
-; GFX11-NEXT:    ; implicit-def: $vgpr94
-; GFX11-NEXT:    ; implicit-def: $vgpr95
-; GFX11-NEXT:    ; implicit-def: $vgpr104
-; GFX11-NEXT:    ; implicit-def: $vgpr105
-; GFX11-NEXT:    ; implicit-def: $vgpr79
-; GFX11-NEXT:    ; implicit-def: $vgpr88
-; GFX11-NEXT:    ; implicit-def: $vgpr89
-; GFX11-NEXT:    ; implicit-def: $vgpr90
-; GFX11-NEXT:    ; implicit-def: $vgpr91
-; GFX11-NEXT:    ; implicit-def: $vgpr61
-; GFX11-NEXT:    ; implicit-def: $vgpr62
-; GFX11-NEXT:    ; implicit-def: $vgpr63
-; GFX11-NEXT:    ; implicit-def: $vgpr72
-; GFX11-NEXT:    ; implicit-def: $vgpr73
-; GFX11-NEXT:    ; implicit-def: $vgpr45
-; GFX11-NEXT:    ; implicit-def: $vgpr46
-; GFX11-NEXT:    ; implicit-def: $vgpr47
-; GFX11-NEXT:    ; implicit-def: $vgpr56
-; GFX11-NEXT:    ; implicit-def: $vgpr57
-; GFX11-NEXT:    ; implicit-def: $vgpr179
-; GFX11-NEXT:    ; implicit-def: $vgpr180
-; GFX11-NEXT:    ; implicit-def: $vgpr181
-; GFX11-NEXT:    ; implicit-def: $vgpr182
-; GFX11-NEXT:    ; implicit-def: $vgpr183
-; GFX11-NEXT:    ; implicit-def: $vgpr162
-; GFX11-NEXT:    ; implicit-def: $vgpr163
-; GFX11-NEXT:    ; implicit-def: $vgpr164
-; GFX11-NEXT:    ; implicit-def: $vgpr165
-; GFX11-NEXT:    ; implicit-def: $vgpr166
-; GFX11-NEXT:    ; implicit-def: $vgpr144
-; GFX11-NEXT:    ; implicit-def: $vgpr145
-; GFX11-NEXT:    ; implicit-def: $vgpr146
-; GFX11-NEXT:    ; implicit-def: $vgpr147
-; GFX11-NEXT:    ; implicit-def: $vgpr148
-; GFX11-NEXT:    ; implicit-def: $vgpr119
-; GFX11-NEXT:    ; implicit-def: $vgpr128
-; GFX11-NEXT:    ; implicit-def: $vgpr129
-; GFX11-NEXT:    ; implicit-def: $vgpr130
-; GFX11-NEXT:    ; implicit-def: $vgpr131
-; GFX11-NEXT:    ; implicit-def: $vgpr114
-; GFX11-NEXT:    ; implicit-def: $vgpr115
-; GFX11-NEXT:    ; implicit-def: $vgpr116
-; GFX11-NEXT:    ; implicit-def: $vgpr117
-; GFX11-NEXT:    ; implicit-def: $vgpr118
-; GFX11-NEXT:    ; implicit-def: $vgpr99
-; GFX11-NEXT:    ; implicit-def: $vgpr100
-; GFX11-NEXT:    ; implicit-def: $vgpr101
-; GFX11-NEXT:    ; implicit-def: $vgpr102
-; GFX11-NEXT:    ; implicit-def: $vgpr103
-; GFX11-NEXT:  .LBB7_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB7_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v55, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v54, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v53, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v52, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v51, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_add_nc_u16 v5, v50, 3
-; GFX11-NEXT:    v_or_b32_e32 v0, v124, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v125, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v126, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v127, v3
-; GFX11-NEXT:    v_add_nc_u16 v6, v49, 3
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v7, v48, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_add_nc_u16 v8, v37, 3
-; GFX11-NEXT:    v_add_nc_u16 v9, v36, 3
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_add_nc_u16 v10, v35, 3
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_add_nc_u16 v2, v39, 3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v5
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v11, v34, 3
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v2, v123, v2
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_or_b32_e32 v3, v111, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v120, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v121, v5
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v6, v122, v6
-; GFX11-NEXT:    v_or_b32_e32 v8, v107, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v108, v9
-; GFX11-NEXT:    v_or_b32_e32 v10, v109, v10
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v38, 3
-; GFX11-NEXT:    v_or_b32_e32 v11, v110, v11
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v10
-; GFX11-NEXT:    v_or_b32_e32 v2, v106, v2
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v11
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_or_b32_e32 v2, v3, v4
-; GFX11-NEXT:    v_or_b32_e32 v3, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v5, v8, v9
-; GFX11-NEXT:    v_or_b32_e32 v4, v7, v12
-; GFX11-NEXT:    v_or_b32_e32 v6, v10, v11
-; GFX11-NEXT:    v_add_nc_u16 v7, v33, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v32, 3
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_nc_u16 v9, v92, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, v78, 3
-; GFX11-NEXT:    v_add_nc_u16 v11, v77, 3
-; GFX11-NEXT:    v_add_nc_u16 v12, v76, 3
-; GFX11-NEXT:    v_add_nc_u16 v13, v75, 3
-; GFX11-NEXT:    v_add_nc_u16 v14, v74, 3
-; GFX11-NEXT:    v_add_nc_u16 v15, v60, 3
-; GFX11-NEXT:    v_add_nc_u16 v16, v59, 3
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_or_b32_e32 v7, v93, v7
-; GFX11-NEXT:    v_or_b32_e32 v8, v94, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v95, v9
-; GFX11-NEXT:    v_or_b32_e32 v10, v104, v10
-; GFX11-NEXT:    v_or_b32_e32 v11, v105, v11
-; GFX11-NEXT:    v_or_b32_e32 v12, v79, v12
-; GFX11-NEXT:    v_or_b32_e32 v13, v88, v13
-; GFX11-NEXT:    v_or_b32_e32 v14, v89, v14
-; GFX11-NEXT:    v_or_b32_e32 v15, v90, v15
-; GFX11-NEXT:    v_or_b32_e32 v16, v91, v16
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v10
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v11
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v12
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v13
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v14
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v15
-; GFX11-NEXT:    v_add_nc_u16 v16, 0x300, v16
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v8, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v9, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v10, v13, v14
-; GFX11-NEXT:    v_or_b32_e32 v11, v15, v16
-; GFX11-NEXT:    v_add_nc_u16 v12, v58, 3
-; GFX11-NEXT:    v_add_nc_u16 v13, v44, 3
-; GFX11-NEXT:    v_add_nc_u16 v14, v43, 3
-; GFX11-NEXT:    v_add_nc_u16 v15, v42, 3
-; GFX11-NEXT:    v_add_nc_u16 v16, v41, 3
-; GFX11-NEXT:    v_add_nc_u16 v17, v40, 3
-; GFX11-NEXT:    v_add_nc_u16 v18, v178, 3
-; GFX11-NEXT:    v_add_nc_u16 v19, v177, 3
-; GFX11-NEXT:    v_add_nc_u16 v20, v176, 3
-; GFX11-NEXT:    v_add_nc_u16 v21, v167, 3
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v17
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v19
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v21
-; GFX11-NEXT:    v_or_b32_e32 v12, v61, v12
-; GFX11-NEXT:    v_or_b32_e32 v13, v62, v13
-; GFX11-NEXT:    v_or_b32_e32 v14, v63, v14
-; GFX11-NEXT:    v_or_b32_e32 v15, v72, v15
-; GFX11-NEXT:    v_or_b32_e32 v16, v73, v16
-; GFX11-NEXT:    v_or_b32_e32 v17, v45, v17
-; GFX11-NEXT:    v_or_b32_e32 v18, v46, v18
-; GFX11-NEXT:    v_or_b32_e32 v19, v47, v19
-; GFX11-NEXT:    v_or_b32_e32 v20, v56, v20
-; GFX11-NEXT:    v_or_b32_e32 v21, v57, v21
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v12
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v13
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v14
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v15
-; GFX11-NEXT:    v_add_nc_u16 v16, 0x300, v16
-; GFX11-NEXT:    v_add_nc_u16 v17, 0x300, v17
-; GFX11-NEXT:    v_add_nc_u16 v18, 0x300, v18
-; GFX11-NEXT:    v_add_nc_u16 v19, 0x300, v19
-; GFX11-NEXT:    v_add_nc_u16 v20, 0x300, v20
-; GFX11-NEXT:    v_add_nc_u16 v21, 0x300, v21
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xffff, v18
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xffff, v20
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v13, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v14, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v15, v18, v19
-; GFX11-NEXT:    v_or_b32_e32 v16, v20, v21
-; GFX11-NEXT:    v_add_nc_u16 v17, v161, 3
-; GFX11-NEXT:    v_add_nc_u16 v18, v160, 3
-; GFX11-NEXT:    v_add_nc_u16 v19, v151, 3
-; GFX11-NEXT:    v_add_nc_u16 v20, v150, 3
-; GFX11-NEXT:    v_add_nc_u16 v21, v149, 3
-; GFX11-NEXT:    v_add_nc_u16 v22, v135, 3
-; GFX11-NEXT:    v_add_nc_u16 v23, v134, 3
-; GFX11-NEXT:    v_add_nc_u16 v24, v133, 3
-; GFX11-NEXT:    v_add_nc_u16 v25, v132, 3
-; GFX11-NEXT:    v_add_nc_u16 v26, v113, 3
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v17
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v19
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v21
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v23
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v24
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v25
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v26
-; GFX11-NEXT:    v_or_b32_e32 v17, v179, v17
-; GFX11-NEXT:    v_or_b32_e32 v18, v180, v18
-; GFX11-NEXT:    v_or_b32_e32 v19, v181, v19
-; GFX11-NEXT:    v_or_b32_e32 v20, v182, v20
-; GFX11-NEXT:    v_or_b32_e32 v21, v183, v21
-; GFX11-NEXT:    v_or_b32_e32 v22, v162, v22
-; GFX11-NEXT:    v_or_b32_e32 v23, v163, v23
-; GFX11-NEXT:    v_or_b32_e32 v24, v164, v24
-; GFX11-NEXT:    v_or_b32_e32 v25, v165, v25
-; GFX11-NEXT:    v_or_b32_e32 v26, v166, v26
-; GFX11-NEXT:    v_add_nc_u16 v17, 0x300, v17
-; GFX11-NEXT:    v_add_nc_u16 v18, 0x300, v18
-; GFX11-NEXT:    v_add_nc_u16 v19, 0x300, v19
-; GFX11-NEXT:    v_add_nc_u16 v20, 0x300, v20
-; GFX11-NEXT:    v_add_nc_u16 v21, 0x300, v21
-; GFX11-NEXT:    v_add_nc_u16 v22, 0x300, v22
-; GFX11-NEXT:    v_add_nc_u16 v23, 0x300, v23
-; GFX11-NEXT:    v_add_nc_u16 v24, 0x300, v24
-; GFX11-NEXT:    v_add_nc_u16 v25, 0x300, v25
-; GFX11-NEXT:    v_add_nc_u16 v26, 0x300, v26
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff, v19
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xffff, v21
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xffff, v23
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xffff, v25
-; GFX11-NEXT:    v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-NEXT:    v_or_b32_e32 v17, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v18, v19, v20
-; GFX11-NEXT:    v_or_b32_e32 v19, v21, v22
-; GFX11-NEXT:    v_or_b32_e32 v20, v23, v24
-; GFX11-NEXT:    v_or_b32_e32 v21, v25, v26
-; GFX11-NEXT:    v_add_nc_u16 v22, v112, 3
-; GFX11-NEXT:    v_add_nc_u16 v23, v98, 3
-; GFX11-NEXT:    v_add_nc_u16 v24, v97, 3
-; GFX11-NEXT:    v_add_nc_u16 v25, v96, 3
-; GFX11-NEXT:    v_add_nc_u16 v26, v87, 3
-; GFX11-NEXT:    v_add_nc_u16 v27, v86, 3
-; GFX11-NEXT:    v_add_nc_u16 v28, v85, 3
-; GFX11-NEXT:    v_add_nc_u16 v29, v84, 3
-; GFX11-NEXT:    v_add_nc_u16 v30, v83, 3
-; GFX11-NEXT:    v_add_nc_u16 v31, v82, 3
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v23
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v24
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v25
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v26
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v27
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v29
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v30
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v31
-; GFX11-NEXT:    v_or_b32_e32 v22, v144, v22
-; GFX11-NEXT:    v_or_b32_e32 v23, v145, v23
-; GFX11-NEXT:    v_or_b32_e32 v24, v146, v24
-; GFX11-NEXT:    v_or_b32_e32 v25, v147, v25
-; GFX11-NEXT:    v_or_b32_e32 v26, v148, v26
-; GFX11-NEXT:    v_or_b32_e32 v27, v119, v27
-; GFX11-NEXT:    v_or_b32_e32 v28, v128, v28
-; GFX11-NEXT:    v_or_b32_e32 v29, v129, v29
-; GFX11-NEXT:    v_or_b32_e32 v30, v130, v30
-; GFX11-NEXT:    v_or_b32_e32 v31, v131, v31
-; GFX11-NEXT:    v_add_nc_u16 v22, 0x300, v22
-; GFX11-NEXT:    v_add_nc_u16 v23, 0x300, v23
-; GFX11-NEXT:    v_add_nc_u16 v24, 0x300, v24
-; GFX11-NEXT:    v_add_nc_u16 v25, 0x300, v25
-; GFX11-NEXT:    v_add_nc_u16 v26, 0x300, v26
-; GFX11-NEXT:    v_add_nc_u16 v27, 0x300, v27
-; GFX11-NEXT:    v_add_nc_u16 v28, 0x300, v28
-; GFX11-NEXT:    v_add_nc_u16 v29, 0x300, v29
-; GFX11-NEXT:    v_add_nc_u16 v30, 0x300, v30
-; GFX11-NEXT:    v_add_nc_u16 v31, 0x300, v31
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xffff, v22
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xffff, v24
-; GFX11-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xffff, v26
-; GFX11-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xffff, v28
-; GFX11-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xffff, v30
-; GFX11-NEXT:    v_lshlrev_b32_e32 v31, 16, v31
-; GFX11-NEXT:    v_or_b32_e32 v22, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v23, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v24, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v25, v28, v29
-; GFX11-NEXT:    v_or_b32_e32 v26, v30, v31
-; GFX11-NEXT:    v_add_nc_u16 v27, v81, 3
-; GFX11-NEXT:    v_add_nc_u16 v28, v80, 3
-; GFX11-NEXT:    v_add_nc_u16 v29, v71, 3
-; GFX11-NEXT:    v_add_nc_u16 v30, v70, 3
-; GFX11-NEXT:    v_add_nc_u16 v31, v69, 3
-; GFX11-NEXT:    v_add_nc_u16 v32, v68, 3
-; GFX11-NEXT:    v_add_nc_u16 v33, v67, 3
-; GFX11-NEXT:    v_add_nc_u16 v34, v66, 3
-; GFX11-NEXT:    v_add_nc_u16 v35, v65, 3
-; GFX11-NEXT:    v_add_nc_u16 v36, v64, 3
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v27
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v29
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v30
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v31
-; GFX11-NEXT:    v_and_b32_e32 v32, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v34, 0xff, v34
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xff, v35
-; GFX11-NEXT:    v_and_b32_e32 v36, 0xff, v36
-; GFX11-NEXT:    v_or_b32_e32 v27, v114, v27
-; GFX11-NEXT:    v_or_b32_e32 v28, v115, v28
-; GFX11-NEXT:    v_or_b32_e32 v29, v116, v29
-; GFX11-NEXT:    v_or_b32_e32 v30, v117, v30
-; GFX11-NEXT:    v_or_b32_e32 v31, v118, v31
-; GFX11-NEXT:    v_or_b32_e32 v32, v99, v32
-; GFX11-NEXT:    v_or_b32_e32 v33, v100, v33
-; GFX11-NEXT:    v_or_b32_e32 v34, v101, v34
-; GFX11-NEXT:    v_or_b32_e32 v35, v102, v35
-; GFX11-NEXT:    v_or_b32_e32 v36, v103, v36
-; GFX11-NEXT:    v_add_nc_u16 v27, 0x300, v27
-; GFX11-NEXT:    v_add_nc_u16 v28, 0x300, v28
-; GFX11-NEXT:    v_add_nc_u16 v29, 0x300, v29
-; GFX11-NEXT:    v_add_nc_u16 v30, 0x300, v30
-; GFX11-NEXT:    v_add_nc_u16 v31, 0x300, v31
-; GFX11-NEXT:    v_add_nc_u16 v32, 0x300, v32
-; GFX11-NEXT:    v_add_nc_u16 v33, 0x300, v33
-; GFX11-NEXT:    v_add_nc_u16 v34, 0x300, v34
-; GFX11-NEXT:    v_add_nc_u16 v35, 0x300, v35
-; GFX11-NEXT:    v_add_nc_u16 v36, 0x300, v36
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xffff, v27
-; GFX11-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xffff, v29
-; GFX11-NEXT:    v_lshlrev_b32_e32 v30, 16, v30
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xffff, v31
-; GFX11-NEXT:    v_lshlrev_b32_e32 v32, 16, v32
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xffff, v33
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v34
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xffff, v35
-; GFX11-NEXT:    v_lshlrev_b32_e32 v36, 16, v36
-; GFX11-NEXT:    v_or_b32_e32 v27, v27, v28
-; GFX11-NEXT:    v_or_b32_e32 v28, v29, v30
-; GFX11-NEXT:    v_or_b32_e32 v29, v31, v32
-; GFX11-NEXT:    v_or_b32_e32 v30, v33, v34
-; GFX11-NEXT:    v_or_b32_e32 v31, v35, v36
-; GFX11-NEXT:  .LBB7_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_b32 v138, off, s32 offset:392
-; GFX11-NEXT:    scratch_load_b32 v137, off, s32 offset:396
-; GFX11-NEXT:    scratch_load_b32 v136, off, s32 offset:400
-; GFX11-NEXT:    scratch_load_b32 v127, off, s32 offset:404
-; GFX11-NEXT:    scratch_load_b32 v126, off, s32 offset:408
-; GFX11-NEXT:    scratch_load_b32 v125, off, s32 offset:412
-; GFX11-NEXT:    scratch_load_b32 v124, off, s32 offset:416
-; GFX11-NEXT:    scratch_load_b32 v123, off, s32 offset:420
-; GFX11-NEXT:    scratch_load_b32 v122, off, s32 offset:424
-; GFX11-NEXT:    scratch_load_b32 v121, off, s32 offset:428
-; GFX11-NEXT:    scratch_load_b32 v120, off, s32 offset:432
-; GFX11-NEXT:    scratch_load_b32 v111, off, s32 offset:436
-; GFX11-NEXT:    scratch_load_b32 v110, off, s32 offset:440
-; GFX11-NEXT:    scratch_load_b32 v109, off, s32 offset:444
-; GFX11-NEXT:    scratch_load_b32 v108, off, s32 offset:448
-; GFX11-NEXT:    scratch_load_b32 v107, off, s32 offset:452
-; GFX11-NEXT:    scratch_load_b32 v106, off, s32 offset:456
-; GFX11-NEXT:    scratch_load_b32 v105, off, s32 offset:460
-; GFX11-NEXT:    scratch_load_b32 v104, off, s32 offset:464
-; GFX11-NEXT:    scratch_load_b32 v95, off, s32 offset:468
-; GFX11-NEXT:    scratch_load_b32 v94, off, s32 offset:472
-; GFX11-NEXT:    scratch_load_b32 v93, off, s32 offset:476
-; GFX11-NEXT:    scratch_load_b32 v92, off, s32 offset:480
-; GFX11-NEXT:    scratch_load_b32 v91, off, s32 offset:484
-; GFX11-NEXT:    scratch_load_b32 v90, off, s32 offset:488
-; GFX11-NEXT:    scratch_load_b32 v89, off, s32 offset:492
-; GFX11-NEXT:    scratch_load_b32 v88, off, s32 offset:496
-; GFX11-NEXT:    scratch_load_b32 v79, off, s32 offset:500
-; GFX11-NEXT:    scratch_load_b32 v78, off, s32 offset:504
-; GFX11-NEXT:    scratch_load_b32 v77, off, s32 offset:508
-; GFX11-NEXT:    scratch_load_b32 v76, off, s32 offset:512
-; GFX11-NEXT:    scratch_load_b32 v75, off, s32 offset:516
-; GFX11-NEXT:    s_clause 0x12
-; GFX11-NEXT:    scratch_load_b32 v74, off, s32 offset:520
-; GFX11-NEXT:    scratch_load_b32 v73, off, s32 offset:524
-; GFX11-NEXT:    scratch_load_b32 v72, off, s32 offset:528
-; GFX11-NEXT:    scratch_load_b32 v63, off, s32 offset:532
-; GFX11-NEXT:    scratch_load_b32 v62, off, s32 offset:536
-; GFX11-NEXT:    scratch_load_b32 v61, off, s32 offset:540
-; GFX11-NEXT:    scratch_load_b32 v60, off, s32 offset:544
-; GFX11-NEXT:    scratch_load_b32 v59, off, s32 offset:548
-; GFX11-NEXT:    scratch_load_b32 v58, off, s32 offset:552
-; GFX11-NEXT:    scratch_load_b32 v57, off, s32 offset:556
-; GFX11-NEXT:    scratch_load_b32 v56, off, s32 offset:560
-; GFX11-NEXT:    scratch_load_b32 v47, off, s32 offset:564
-; GFX11-NEXT:    scratch_load_b32 v46, off, s32 offset:568
-; GFX11-NEXT:    scratch_load_b32 v45, off, s32 offset:572
-; GFX11-NEXT:    scratch_load_b32 v44, off, s32 offset:576
-; GFX11-NEXT:    scratch_load_b32 v43, off, s32 offset:580
-; GFX11-NEXT:    scratch_load_b32 v42, off, s32 offset:584
-; GFX11-NEXT:    scratch_load_b32 v41, off, s32 offset:588
-; GFX11-NEXT:    scratch_load_b32 v40, off, s32 offset:592
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v128i8_to_v32i32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32 offset:384
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v32, off, s32 offset:380
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v31, off, s32 offset:376
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v32, off, s32 offset:372
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v50, off, s32 offset:368
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v33, off, s32 offset:364
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v50, off, s32 offset:360
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v33, off, s32 offset:356
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v49, off, s32 offset:352
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v34, off, s32 offset:348
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v51, off, s32 offset:344
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v34, off, s32 offset:340
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v51, off, s32 offset:336
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v35, off, s32 offset:332
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v54, off, s32 offset:328
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v35, off, s32 offset:324
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v53, off, s32 offset:320
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v36, off, s32 offset:316
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v53, off, s32 offset:312
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v36, off, s32 offset:308
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v54, off, s32 offset:304
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v37, off, s32 offset:300
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v55, off, s32 offset:296
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v37, off, s32 offset:292
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v64, off, s32 offset:288
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v38, off, s32 offset:284
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v64, off, s32 offset:280
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v38, off, s32 offset:276
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v55, off, s32 offset:272
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v39, off, s32 offset:268
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v65, off, s32 offset:264
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v39, off, s32 offset:260
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v65, off, s32 offset:256
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v48, off, s32 offset:252
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v69, off, s32 offset:248
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v48, off, s32 offset:244
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v68, off, s32 offset:240
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v49, off, s32 offset:236
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v68, off, s32 offset:232
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v52, off, s32 offset:228
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v69, off, s32 offset:224
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v52, off, s32 offset:220
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v70, off, s32 offset:216
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v103, off, s32 offset:388
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v81, off, s32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v81, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v82, off, s32 offset:16
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v82, off, s32 offset:24
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v83, off, s32 offset:32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v86, off, s32 offset:40
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v86, off, s32 offset:48
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v87, off, s32 offset:56
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v87, off, s32 offset:64
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v96, off, s32 offset:72
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v99, off, s32 offset:80
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v99, off, s32 offset:88
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v100, off, s32 offset:96
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v100, off, s32 offset:104
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v101, off, s32 offset:112
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v160, off, s32 offset:120
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v160, off, s32 offset:128
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v161, off, s32 offset:136
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v161, off, s32 offset:144
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v162, off, s32 offset:152
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v162, off, s32 offset:160
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v163, off, s32 offset:168
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v163, off, s32 offset:176
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v164, off, s32 offset:184
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v164, off, s32 offset:192
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v165, off, s32 offset:200
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v165, off, s32 offset:208
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v66, off, s32 offset:212
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v66, off, s32 offset:204
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v67, off, s32 offset:196
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v67, off, s32 offset:188
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v70, off, s32 offset:180
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v71, off, s32 offset:172
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v71, off, s32 offset:164
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v80, off, s32 offset:156
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v80, off, s32 offset:148
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v83, off, s32 offset:140
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v84, off, s32 offset:132
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v84, off, s32 offset:124
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v85, off, s32 offset:116
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v85, off, s32 offset:108
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v96, off, s32 offset:100
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v97, off, s32 offset:92
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v97, off, s32 offset:84
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v98, off, s32 offset:76
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v98, off, s32 offset:68
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v101, off, s32 offset:60
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v102, off, s32 offset:52
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v102, off, s32 offset:44
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v113, off, s32 offset:36
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v114, off, s32 offset:28
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v114, off, s32 offset:20
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v115, off, s32 offset:12
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v115, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v118.h, v30.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v119.l, v28.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v119.h, v26.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v130.h, v24.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v131.l, v22.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v131.h, v20.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v132.l, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v135.l, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v135.h, v14.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v144.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v144.h, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v145.l, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v148.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v148.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v149.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v149.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v150.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v150.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v151.l, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v151.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v145.h, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v146.l, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v146.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v147.l, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v147.h, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v132.h, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v133.l, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v133.h, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v134.l, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v134.h, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v128.l, 8, v29.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(62)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v50.h, 8, v50.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v50.l, 8, v50.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v49.h, 8, v49.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v54.l, 8, v54.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v53.h, 8, v53.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v53.l, 8, v53.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v64.h, 8, v64.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v64.l, 8, v64.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v55.h, 8, v55.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v69.l, 8, v69.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(61)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v68.h, 8, v68.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(59)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v68.l, 8, v68.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(54)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v103
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(53)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v128.h, 8, v81.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(52)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v129.l, 8, v81.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(51)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v129.h, 8, v82.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(50)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v130.l, 8, v82.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(49)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v116.l, 8, v83.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(48)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v116.h, 8, v86.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(47)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v117.l, 8, v86.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(46)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v117.h, 8, v87.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(45)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v118.l, 8, v87.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(44)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v103.l, 8, v96.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(43)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v103.h, 8, v99.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(42)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v112.l, 8, v99.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(41)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v112.h, 8, v100.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(40)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v113.l, 8, v100.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(39)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v99.l, 8, v101.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(38)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v99.h, 8, v160.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(37)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v100.l, 8, v160.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(36)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v100.h, 8, v161.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(35)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v101.l, 8, v161.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(34)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v86.l, 8, v162.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v86.h, 8, v162.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(32)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v87.l, 8, v163.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v87.h, 8, v163.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(30)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v96.l, 8, v164.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(29)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v81.l, 8, v164.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(28)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v81.h, 8, v165.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(27)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v82.l, 8, v165.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v82.h, 8, v70.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v83.l, 8, v69.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v69.h, 8, v65.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v70.l, 8, v65.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v65.l, 8, v55.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v65.h, 8, v54.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v54.h, 8, v51.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v55.l, 8, v51.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v51.l, 8, v31.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v51.h, 8, v31.l
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB7_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB7_4
+; GFX11-TRUE16-NEXT:  .LBB7_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB7_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v149.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v149.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v148.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v148.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v0.h, v150.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v150.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v151.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v1.h, v151.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v145.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v144.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v145.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v144.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v5
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v135.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v2.h, v146.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v132.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v135.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v146.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v147.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v5
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v131.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v132.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v3.h, v147.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v131.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v119.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v2.h, v133.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v7, v8
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v119.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v6
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v130.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v133.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v134.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v118.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v128.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v3.h, v134.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v9, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v11, v12
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v115.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v114.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v7.h, v128.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v114.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v115.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v129.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v130.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v10
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v113.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v116.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v6, v14
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v8.h, v129.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v102.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v102.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v101.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v7.h, v116.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v12, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v98.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v11
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v117.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v8.h, v117.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v118.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v98.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v97.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v103.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v14, v15
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v16, v17
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v97.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v96.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v12.h, v103.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v112.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v85.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v10, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v11, v19
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v13.h, v112.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v113.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v15
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v85.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v84.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v99.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v16
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v14
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v84.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v83.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v12.h, v99.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v100.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v17, v18
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v80.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v13.h, v100.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v101.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v19, v20
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.h, 0xff, v80.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v71.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v70.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v17.l, v86.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v21, v22
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.h, 0xff, v71.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v17.h, v86.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v18.l, v87.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v19.l, v96.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff, v17
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v67.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v15, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, v16, v24
+; GFX11-TRUE16-NEXT:    v_or_b16 v21.l, v18.h, v87.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v20
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v19
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.h, 0xff, v67.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v66.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.h, 0xff, v66.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v52.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v17.l, v81.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v21
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v17.h, v81.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v18.l, v82.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v21.l, v18.h, v82.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v19.l, v83.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, v22, v23
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v52.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v48.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v19
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v18, v24, v25
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.h, 0xff, v49.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.h, 0xff, v48.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v39.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v22.l, v68.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v23.l, v69.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v19, v26, v27
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, v21, v29
+; GFX11-TRUE16-NEXT:    v_or_b16 v25.l, v22.h, v68.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v26.l, v23.h, v69.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v24.l, v70.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v27, 0xffff, v22
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v29, 0xffff, v23
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v39.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v38.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, v20, v28
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v25
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v26
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff, v24
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.h, 0xff, v38.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.h, 0xff, v37.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v37.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v22.l, v55.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v23.l, v64.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v25.l, v22.h, v64.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v26.l, v23.h, v65.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v24.l, v65.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, v27, v28
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, v29, v30
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.l, 0xff, v36.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.l, 0xff, v35.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v29.l, 0xff, v34.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v26
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v24
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.h, 0xff, v36.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.h, 0xff, v35.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.l, v27.l, v53.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.l, v28.l, v54.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v29.l, v29.l, v55.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v25
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, v31, v37
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v26, v26, v39
+; GFX11-TRUE16-NEXT:    v_or_b16 v30.l, v27.h, v53.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v31.l, v28.h, v54.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v35, 0xffff, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v37, 0xffff, v28
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v29
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.l, 0xff, v34.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.h, 0xff, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.l, 0xff, v33.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.h, 0xff, v32.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v29.l, 0xff, v32.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v25, v25, v38
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v36, 16, v30
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v31
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.l, v27.l, v49.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v30.l, v27.h, v50.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.l, v28.l, v50.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v31.l, v28.h, v51.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v29.l, v29.l, v51.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v30, 0xffff, v30
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v33, 16, v28
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff, v31
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v29
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v27, v35, v36
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v28, v37, v38
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v29, v39, v32
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v30, v30, v33
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v31, v31, v34
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr149_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr148_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr148_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr145_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr144_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr144_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr135_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr132_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr131_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr131_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr130_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr119_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr118_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr115_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr114_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr114_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr97_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr85_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr71_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr67_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr150_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr150_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr151_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr145_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr146_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr147_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr147_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr132_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr133_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr133_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr134_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr134_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr128_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr128_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr129_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr130_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr116_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr116_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr117_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr118_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr103_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr112_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr113_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr99_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr100_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr101_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr86_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr83_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr68_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr70_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB7_2
+; GFX11-TRUE16-NEXT:  .LBB7_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v149.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v149.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v148.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v145.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v148.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v150.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v150.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v151.h, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v145.h, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v151.l, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v144.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v144.l, 3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, v135.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, v135.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v5
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v146.l, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v146.h, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v147.h, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v147.l, v3.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v2
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v132.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v131.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v131.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, v119.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v132.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v133.l, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v6
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v3.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, v130.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v7, v8
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v119.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, v118.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v133.h, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v134.h, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v6
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v134.l, v3.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v128.l, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v128.h, v7.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v4
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v9, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v11, v12
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, v115.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, v114.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v114.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.h, v115.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.l, 0x300, v7.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, v113.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v129.l, v8.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v130.l, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v116.l, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.h, v129.h, v8.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v8.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v10
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v116.h, v7.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v6, v14
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, v102.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, v101.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.l, 0x300, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v12, v13
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, v98.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, 0x300, v8.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.h, v102.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.h, v98.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v117.l, v8.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v118.l, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v103.l, v12.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v11
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.h, v117.h, v8.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v8.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v9.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, v97.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.h, v103.h, v12.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, 0x300, v12.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, 0x300, v8.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v14, v15
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v16, v17
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.h, v97.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, v96.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, v85.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v112.l, v13.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.l, 0x300, v12.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.h, v85.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.h, v112.h, v13.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v113.l, v14.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, 0x300, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v99.l, v12.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v10, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v11, v19
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, 0x300, v14.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v15
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, v84.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.h, v99.h, v12.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, 0x300, v12.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v16.l, 0x300, v13.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v14
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.h, v84.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, v83.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.l, 0x300, v12.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v17, v18
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.l, v80.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v100.l, v13.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.h, v80.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v16
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.h, v100.h, v13.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v101.l, v14.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, 0x300, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.h, 0xff, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v86.l, v17.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v16.l, 0x300, v13.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, 0x300, v14.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v19, v20
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.l, v71.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v19.l, v70.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.h, v86.h, v17.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.l, 0x300, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v21, v22
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.h, v71.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff, v17
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.l, v67.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.h, 0xff, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v87.l, v18.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v96.l, v19.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v20.l, 0x300, v17.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.h, v67.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v17.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.h, v87.h, v18.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.l, 0x300, v18.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v19.l, 0x300, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.h, 0xff, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v81.l, v17.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v15, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, v16, v24
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v21.l, 0x300, v18.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v20
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v19
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.l, v66.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.h, v66.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v19.l, v52.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.h, v81.h, v17.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.l, 0x300, v17.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.h, 0xff, v18.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v19.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v20.l, 0x300, v17.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, v22, v23
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.l, v52.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.l, v48.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v82.l, v18.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.h, v82.h, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v83.l, v19.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.h, v49.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.h, v48.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v21
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.l, 0x300, v18.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v21.l, 0x300, v18.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v19.l, 0x300, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.h, 0xff, v22.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.h, 0xff, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v68.l, v22.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v69.l, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v19
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v18, v24, v25
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v24.l, v39.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.h, v68.h, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.h, v69.h, v23.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.l, 0x300, v22.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.l, 0x300, v23.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v19, v26, v27
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, v21, v29
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v27, 0xffff, v22
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v29, 0xffff, v23
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.l, v39.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.l, v38.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v70.l, v24.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v25.l, 0x300, v22.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v26.l, 0x300, v23.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.h, v38.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.h, v37.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v23.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff, v20
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v24.l, 0x300, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.h, 0xff, v22.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.h, 0xff, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v55.h, v22.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v64.h, v23.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, v20, v28
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v25
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v26
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff, v24
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v24.l, v37.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.h, v64.l, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.h, v65.l, v23.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.l, 0x300, v22.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.l, 0x300, v23.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v25.l, 0x300, v22.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v26.l, 0x300, v23.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, v27, v28
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, v29, v30
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.l, v36.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.l, v35.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v29.l, v34.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v65.h, v24.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.h, v36.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.h, v35.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.l, 0xff, v27.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v29.l, 0xff, v29.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v24.l, 0x300, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.h, 0xff, v27.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.h, 0xff, v28.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.l, v53.l, v27.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.l, v54.l, v28.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v29.l, v55.l, v29.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v26
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v24
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.h, v53.h, v27.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.h, v54.h, v28.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.l, 0x300, v27.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.l, 0x300, v28.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v29.l, 0x300, v29.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, v31, v37
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v26, v26, v39
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v30.l, 0x300, v27.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v31.l, 0x300, v28.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v35, 0xffff, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v37, 0xffff, v28
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v29
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.l, v34.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.h, v33.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.l, v33.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.h, v32.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v29.l, v32.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.l, 0xff, v27.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.h, 0xff, v27.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.h, 0xff, v28.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v29.l, 0xff, v29.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v25
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.l, v49.h, v27.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.h, v50.l, v27.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.l, v50.h, v28.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.h, v51.l, v28.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v29.l, v51.h, v29.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v25, v25, v38
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v36, 16, v30
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v31
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.l, 0x300, v27.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v30.l, 0x300, v27.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.l, 0x300, v28.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v31.l, 0x300, v28.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v29.l, 0x300, v29.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v30, 0xffff, v30
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v33, 16, v28
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff, v31
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v29
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v27, v35, v36
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v28, v37, v38
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v29, v39, v32
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v30, v30, v33
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v31, v31, v34
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v128i8_to_v32i32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s32 offset:592
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v41, s32 offset:588
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v42, s32 offset:584
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v43, s32 offset:580
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v44, s32 offset:576
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v45, s32 offset:572
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v46, s32 offset:568
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v47, s32 offset:564
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v56, s32 offset:560
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v57, s32 offset:556
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v58, s32 offset:552
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v59, s32 offset:548
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v60, s32 offset:544
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v61, s32 offset:540
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v62, s32 offset:536
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v63, s32 offset:532
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v72, s32 offset:528
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v73, s32 offset:524
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v74, s32 offset:520
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v75, s32 offset:516
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v76, s32 offset:512
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v77, s32 offset:508
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v78, s32 offset:504
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v79, s32 offset:500
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v88, s32 offset:496
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v89, s32 offset:492
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v90, s32 offset:488
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v91, s32 offset:484
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v92, s32 offset:480
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v93, s32 offset:476
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v94, s32 offset:472
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v95, s32 offset:468
+; GFX11-FAKE16-NEXT:    s_clause 0x12
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v104, s32 offset:464
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v105, s32 offset:460
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v106, s32 offset:456
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v107, s32 offset:452
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v108, s32 offset:448
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v109, s32 offset:444
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v110, s32 offset:440
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v111, s32 offset:436
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v120, s32 offset:432
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v121, s32 offset:428
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v122, s32 offset:424
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v123, s32 offset:420
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v124, s32 offset:416
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v125, s32 offset:412
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v126, s32 offset:408
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v127, s32 offset:404
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v136, s32 offset:400
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v137, s32 offset:396
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v138, s32 offset:392
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v36, v22 :: v_dual_mov_b32 v37, v20
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v38, v18 :: v_dual_mov_b32 v39, v16
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v48, v14 :: v_dual_mov_b32 v49, v12
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v50, v10 :: v_dual_mov_b32 v51, v8
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v52, v6 :: v_dual_mov_b32 v53, v4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v54, v2 :: v_dual_mov_b32 v55, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v0, off, s32 offset:384
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v64, off, s32 offset:380
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32 offset:376
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v65, off, s32 offset:372
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v4, off, s32 offset:368
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v66, off, s32 offset:364
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v6, off, s32 offset:360
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v67, off, s32 offset:356
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v8, off, s32 offset:352
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v68, off, s32 offset:348
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v10, off, s32 offset:344
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v69, off, s32 offset:340
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v12, off, s32 offset:336
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v70, off, s32 offset:332
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v14, off, s32 offset:328
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v71, off, s32 offset:324
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v16, off, s32 offset:320
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v80, off, s32 offset:316
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v18, off, s32 offset:312
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v81, off, s32 offset:308
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v20, off, s32 offset:304
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v82, off, s32 offset:300
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v22, off, s32 offset:296
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v83, off, s32 offset:292
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v24, off, s32 offset:288
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v84, off, s32 offset:284
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v26, off, s32 offset:280
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v85, off, s32 offset:276
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v28, off, s32 offset:272
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v86, off, s32 offset:268
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v30, off, s32 offset:264
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v87, off, s32 offset:260
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v31, off, s32 offset:256
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v96, off, s32 offset:252
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v99, off, s32 offset:248
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v97, off, s32 offset:244
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v100, off, s32 offset:240
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v98, off, s32 offset:236
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v101, off, s32 offset:232
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v112, off, s32 offset:228
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v102, off, s32 offset:224
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v113, off, s32 offset:220
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v103, off, s32 offset:216
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v114, off, s32 offset:388
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v115, off, s32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v116, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v117, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v118, off, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v119, off, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v128, off, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v129, off, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v130, off, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v131, off, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v144, off, s32 offset:72
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v145, off, s32 offset:80
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v146, off, s32 offset:88
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v147, off, s32 offset:96
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v148, off, s32 offset:104
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v162, off, s32 offset:112
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v163, off, s32 offset:120
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v164, off, s32 offset:128
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v165, off, s32 offset:136
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v166, off, s32 offset:144
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v179, off, s32 offset:152
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v180, off, s32 offset:160
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v181, off, s32 offset:168
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v182, off, s32 offset:176
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v183, off, s32 offset:184
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v136, off, s32 offset:192
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v137, off, s32 offset:200
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v138, off, s32 offset:208
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v132, off, s32 offset:212
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v133, off, s32 offset:204
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v134, off, s32 offset:196
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v135, off, s32 offset:188
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v149, off, s32 offset:180
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v150, off, s32 offset:172
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v151, off, s32 offset:164
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v160, off, s32 offset:156
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v161, off, s32 offset:148
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v167, off, s32 offset:140
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v176, off, s32 offset:132
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v177, off, s32 offset:124
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v178, off, s32 offset:116
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v40, off, s32 offset:108
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v41, off, s32 offset:100
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v42, off, s32 offset:92
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v43, off, s32 offset:84
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v44, off, s32 offset:76
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v58, off, s32 offset:68
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v59, off, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v60, off, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v74, off, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v75, off, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v76, off, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v77, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v78, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v92, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v124, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v125, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v126, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v127, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v111, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v120, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v121, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v122, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v123, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v106, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v107, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v108, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v109, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v110, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v93, 8, v29
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(54)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v114
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(53)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v94, 8, v115
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(52)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v95, 8, v116
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(51)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v104, 8, v117
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(50)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v105, 8, v118
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(49)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v79, 8, v119
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(48)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v88, 8, v128
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(47)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v89, 8, v129
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(46)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v90, 8, v130
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(45)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v91, 8, v131
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(44)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v61, 8, v144
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(43)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v62, 8, v145
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(42)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v63, 8, v146
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(41)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v72, 8, v147
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(40)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v73, 8, v148
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(39)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v45, 8, v162
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(38)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v46, 8, v163
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(37)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v47, 8, v164
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(36)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v56, 8, v165
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(35)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v57, 8, v166
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(34)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v179, 8, v179
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v180, 8, v180
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(32)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v181, 8, v181
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v182, 8, v182
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(30)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v183, 8, v183
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(29)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v162, 8, v136
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(28)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v163, 8, v137
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(27)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v164, 8, v138
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v165, 8, v103
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v166, 8, v102
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v144, 8, v101
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v145, 8, v100
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v146, 8, v99
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v147, 8, v31
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v148, 8, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v119, 8, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v128, 8, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v129, 8, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v130, 8, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v131, 8, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v114, 8, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v115, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v116, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v117, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v118, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v99, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v100, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v101, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v102, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v103, 8, v0
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB7_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v53
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v52
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v51
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v124
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v125
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v126
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v127
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v50
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v37
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v49
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v48
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v111
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v121
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v120
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v122
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v123
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v107
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v38
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v108
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v109
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v110
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v106
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v6, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v8, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v10, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v32
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v92
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v78
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v77
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v76
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v75
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v74
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v60
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v59
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v93
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v94
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v95
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v104
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v105
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v79
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v88
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v89
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v90
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v91
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v13, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v15, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v58
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v44
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v43
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v42
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v41
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v40
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v178
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v177
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v176
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v167
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v61
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v62
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v63
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v72
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v73
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v17, v45
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v18, v46
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v19, v47
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v56
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v21, v57
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xffff, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xffff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v18, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v20, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v161
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v160
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v151
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v150
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v149
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v135
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v134
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v133
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v132
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v113
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v17, v179
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v18, v180
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v19, v181
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v182
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v21, v183
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v22, v162
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v23, v163
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v24, v164
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v165
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v26, v166
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xffff, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xffff, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v19, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v21, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v23, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v25, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v112
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v98
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v97
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v96
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v87
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v86
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v84
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v83
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v82
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v22, v144
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v23, v145
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v24, v146
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v147
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v26, v148
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v27, v119
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v28, v128
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v29, v129
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v30, v130
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v31, v131
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xffff, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xffff, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xffff, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xffff, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xffff, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v31
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v28, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v30, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v81
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v71
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v70
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v69
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v32, 0xff, v68
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xff, v67
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v34, 0xff, v66
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xff, v65
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v36, 0xff, v64
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v27, v114
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v28, v115
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v29, v116
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v30, v117
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v31, v118
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v32, v32, v99
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v33, v33, v100
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v34, v34, v101
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, v35, v102
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, v36, v103
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xffff, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xffff, v29
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xffff, v31
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xffff, v33
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xffff, v35
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v36, 16, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v27, v28
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v29, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v31, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v33, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v35, v36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr92
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr78
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr77
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr76
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr75
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr74
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr60
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr59
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr58
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr44
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr43
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr42
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr41
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr40
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr178
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr177
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr176
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr167
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr161
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr160
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr151
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr150
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr149
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr135
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr124
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr125
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr126
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr127
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr111
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr120
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr121
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr122
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr123
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr106
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr107
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr108
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr109
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr110
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr93
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr94
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr95
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr104
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr105
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr79
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr88
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr89
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr90
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr91
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr61
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr62
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr63
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr72
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr73
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr45
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr46
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr47
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr56
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr57
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr179
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr180
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr181
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr182
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr183
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr162
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr163
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr164
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr165
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr166
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr144
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr147
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr148
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT:  .LBB7_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB7_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v55, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v54, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v53, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v52, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v51, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v50, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v124, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v125, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v126, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v127, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v49, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v48, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v37, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v36, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v35, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v39, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, v34, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v123, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v111, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v120, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v121, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v122, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v107, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v108, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v109, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v38, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v110, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v106, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v3, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v8, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v10, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v33, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v32, 3
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v92, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v78, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, v77, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v76, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v75, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v74, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, v60, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, v59, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v93, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v94, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v95, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v104, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v105, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v79, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v88, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v89, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v90, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v91, v16
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v13
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, 0x300, v15
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, 0x300, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v13, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v15, v16
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v58, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v44, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v43, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, v42, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, v41, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, v40, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, v178, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, v177, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, v176, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, v167, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v61, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v62, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v63, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v72, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v73, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v45, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v46, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v47, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v56, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v57, v21
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v13
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, 0x300, v15
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, 0x300, v16
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, 0x300, v17
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, 0x300, v18
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, 0x300, v19
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, 0x300, v20
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, 0x300, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xffff, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xffff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v18, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v20, v21
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, v161, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, v160, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, v151, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, v150, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, v149, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, v135, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v23, v134, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v24, v133, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v25, v132, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v26, v113, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v179, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v180, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v181, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v182, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v183, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v162, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v163, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v164, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v165, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v166, v26
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, 0x300, v17
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, 0x300, v18
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, 0x300, v19
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, 0x300, v20
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, 0x300, v21
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, 0x300, v22
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v23, 0x300, v23
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v24, 0x300, v24
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v25, 0x300, v25
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v26, 0x300, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xffff, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xffff, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v19, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v21, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v23, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v25, v26
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, v112, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v23, v98, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v24, v97, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v25, v96, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v26, v87, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v27, v86, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v28, v85, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v29, v84, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v30, v83, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v31, v82, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v144, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v145, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v146, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v147, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v148, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v119, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v128, v28
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v129, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v130, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v131, v31
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, 0x300, v22
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v23, 0x300, v23
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v24, 0x300, v24
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v25, 0x300, v25
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v26, 0x300, v26
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v27, 0x300, v27
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v28, 0x300, v28
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v29, 0x300, v29
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v30, 0x300, v30
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v31, 0x300, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xffff, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xffff, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xffff, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xffff, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xffff, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v31
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v28, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v30, v31
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v27, v81, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v28, v80, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v29, v71, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v30, v70, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v31, v69, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v32, v68, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v33, v67, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v34, v66, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v35, v65, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v36, v64, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v32, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v34, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v36, 0xff, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v114, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v115, v28
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v116, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v117, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v118, v31
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v32, v99, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v33, v100, v33
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v34, v101, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, v102, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, v103, v36
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v27, 0x300, v27
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v28, 0x300, v28
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v29, 0x300, v29
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v30, 0x300, v30
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v31, 0x300, v31
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v32, 0x300, v32
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v33, 0x300, v33
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v34, 0x300, v34
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v35, 0x300, v35
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v36, 0x300, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xffff, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xffff, v29
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xffff, v31
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xffff, v33
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xffff, v35
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v36, 16, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v27, v28
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v29, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v31, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v33, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v35, v36
+; GFX11-FAKE16-NEXT:  .LBB7_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v138, off, s32 offset:392
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v137, off, s32 offset:396
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v136, off, s32 offset:400
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v127, off, s32 offset:404
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v126, off, s32 offset:408
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v125, off, s32 offset:412
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v124, off, s32 offset:416
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v123, off, s32 offset:420
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v122, off, s32 offset:424
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v121, off, s32 offset:428
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v120, off, s32 offset:432
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v111, off, s32 offset:436
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v110, off, s32 offset:440
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v109, off, s32 offset:444
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v108, off, s32 offset:448
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v107, off, s32 offset:452
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v106, off, s32 offset:456
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v105, off, s32 offset:460
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v104, off, s32 offset:464
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v95, off, s32 offset:468
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v94, off, s32 offset:472
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v93, off, s32 offset:476
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v92, off, s32 offset:480
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v91, off, s32 offset:484
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v90, off, s32 offset:488
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v89, off, s32 offset:492
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v88, off, s32 offset:496
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v79, off, s32 offset:500
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v78, off, s32 offset:504
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v77, off, s32 offset:508
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v76, off, s32 offset:512
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v75, off, s32 offset:516
+; GFX11-FAKE16-NEXT:    s_clause 0x12
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v74, off, s32 offset:520
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v73, off, s32 offset:524
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v72, off, s32 offset:528
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v63, off, s32 offset:532
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v62, off, s32 offset:536
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v61, off, s32 offset:540
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v60, off, s32 offset:544
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v59, off, s32 offset:548
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v58, off, s32 offset:552
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v57, off, s32 offset:556
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v56, off, s32 offset:560
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v47, off, s32 offset:564
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v46, off, s32 offset:568
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v45, off, s32 offset:572
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v44, off, s32 offset:576
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v43, off, s32 offset:580
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v42, off, s32 offset:584
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v41, off, s32 offset:588
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s32 offset:592
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -12941,550 +14454,1113 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v64bf16_to_v32i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_b32 v32, off, s32 offset:4
-; GFX11-NEXT:    scratch_load_b32 v31, off, s32
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v32
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB9_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v33, 16, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v32, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
-; GFX11-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v37, v33, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v34, v32, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v35, 0x400000, v32
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_bfe_u32 v39, v14, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-NEXT:    v_add3_u32 v37, v37, v33, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v34, v34, v32, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v34, v35, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v35, v39, v14, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-NEXT:    v_or_b32_e32 v34, 0x400000, v33
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-NEXT:    v_bfe_u32 v36, v15, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v15
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v36, v36, v15, 0x7fff
-; GFX11-NEXT:    v_dual_cndmask_b32 v15, v36, v38 :: v_dual_lshlrev_b32 v36, 16, v13
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v15, v15, v32, 0x7060302
-; GFX11-NEXT:    v_dual_cndmask_b32 v33, v37, v34 :: v_dual_add_f32 v34, 0x40c00000, v36
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v32, v34, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v14
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_cndmask_b32 v14, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v12
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_perm_b32 v14, v14, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v13, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_cndmask_b32 v32, v32, v36
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-NEXT:    v_add3_u32 v33, v33, v13, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cndmask_b32_e32 v13, v33, v37, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v11
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_perm_b32 v13, v13, v32, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v32, v35, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-NEXT:    v_bfe_u32 v34, v12, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v12
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v34, v34, v12, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v12, v34, v38, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v12, v12, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v11, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_add3_u32 v33, v33, v11, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v35, v10, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v35, v35, v10, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v11, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v10
-; GFX11-NEXT:    v_perm_b32 v11, v11, v32, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    v_dual_cndmask_b32 v10, v35, v38 :: v_dual_lshlrev_b32 v37, 16, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_lshlrev_b32 v35, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-NEXT:    v_perm_b32 v10, v10, v33, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v32, v34, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v8, 0x40c00000, v8
-; GFX11-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v34, v8, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v9, 0x40c00000, v9
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_add3_u32 v34, v34, v8, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v33, v9, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v9
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    v_add3_u32 v33, v33, v9, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v9, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v8
-; GFX11-NEXT:    v_perm_b32 v9, v9, v32, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-NEXT:    v_cndmask_b32_e32 v8, v34, v38, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v8, v8, v33, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_add_f32 v35, 0x40c00000, v37
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v32, v35, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-NEXT:    v_bfe_u32 v35, v6, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v7, 0x40c00000, v7
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_add3_u32 v35, v35, v6, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v33, v7, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v7
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    v_add3_u32 v33, v33, v7, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v7, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v6
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v6, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v5
-; GFX11-NEXT:    v_perm_b32 v7, v7, v32, 0x7060302
-; GFX11-NEXT:    v_perm_b32 v6, v6, v33, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v4, 0x40c00000, v4
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v37
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v32, v34, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT:    v_bfe_u32 v34, v4, 16, 1
-; GFX11-NEXT:    v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v5, 0x40c00000, v5
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add3_u32 v34, v34, v4, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v33, v5, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v5
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v33, v33, v5, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v5, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v3
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v4
-; GFX11-NEXT:    v_perm_b32 v5, v5, v32, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_cndmask_b32 v4, v34, v38
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v2
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT:    v_bfe_u32 v32, v35, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_perm_b32 v4, v4, v33, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v35, v2, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_add3_u32 v35, v35, v2, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-NEXT:    v_bfe_u32 v33, v3, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v3
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v33, v33, v3, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v1
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v37
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v2, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v0
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    v_perm_b32 v3, v3, v32, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v32, v34, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_perm_b32 v2, v2, v33, 0x7060302
-; GFX11-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v34, v0, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_add3_u32 v34, v34, v0, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-NEXT:    v_bfe_u32 v33, v1, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v33, v33, v1, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v31
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v0
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xffff0000, v31
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_add_f32_e32 v31, 0x40c00000, v31
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v34, v38, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v30
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xffff0000, v30
-; GFX11-NEXT:    v_perm_b32 v1, v1, v32, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v32, v35, 16, 1
-; GFX11-NEXT:    v_perm_b32 v0, v0, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v31, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v30, 0x40c00000, v30
-; GFX11-NEXT:    v_add3_u32 v33, v33, v31, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v31
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-NEXT:    v_bfe_u32 v35, v30, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_cndmask_b32_e32 v31, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v29
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add3_u32 v35, v35, v30, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v30
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xffff0000, v29
-; GFX11-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add_f32_e32 v29, 0x40c00000, v29
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_dual_cndmask_b32 v30, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v28
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xffff0000, v28
-; GFX11-NEXT:    v_perm_b32 v31, v31, v32, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v32, v34, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v30, v30, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v29, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v28, 0x40c00000, v28
-; GFX11-NEXT:    v_add3_u32 v33, v33, v29, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v29
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11-NEXT:    v_bfe_u32 v34, v28, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cndmask_b32_e32 v29, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v27
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_add3_u32 v34, v34, v28, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v28
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xffff0000, v27
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v27, 0x40c00000, v27
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cndmask_b32_e32 v28, v34, v38, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v26
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xffff0000, v26
-; GFX11-NEXT:    v_perm_b32 v29, v29, v32, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v32, v35, 16, 1
-; GFX11-NEXT:    v_perm_b32 v28, v28, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v27, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v26, 0x40c00000, v26
-; GFX11-NEXT:    v_add3_u32 v33, v33, v27, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v27
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11-NEXT:    v_bfe_u32 v35, v26, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_cndmask_b32_e32 v27, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v25
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add3_u32 v35, v35, v26, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v26
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xffff0000, v25
-; GFX11-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add_f32_e32 v25, 0x40c00000, v25
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_dual_cndmask_b32 v26, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v24
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xffff0000, v24
-; GFX11-NEXT:    v_perm_b32 v27, v27, v32, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v32, v34, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v26, v26, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v25, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v24, 0x40c00000, v24
-; GFX11-NEXT:    v_add3_u32 v33, v33, v25, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v25
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-NEXT:    v_bfe_u32 v34, v24, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cndmask_b32_e32 v25, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v23
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_add3_u32 v34, v34, v24, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v24
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-NEXT:    v_perm_b32 v25, v25, v32, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v23, 0x40c00000, v23
-; GFX11-NEXT:    v_bfe_u32 v32, v35, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cndmask_b32_e32 v24, v34, v38, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xffff0000, v22
-; GFX11-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_perm_b32 v24, v24, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v23, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-NEXT:    v_add_f32_e32 v22, 0x40c00000, v22
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v23
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v33, v23, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-NEXT:    v_bfe_u32 v35, v22, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_cndmask_b32_e32 v23, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v21
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add3_u32 v35, v35, v22, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xffff0000, v21
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v22
-; GFX11-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v21, 0x40c00000, v21
-; GFX11-NEXT:    v_perm_b32 v23, v23, v32, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v36, v34, 16, 1
-; GFX11-NEXT:    v_dual_cndmask_b32 v22, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v20
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v32, v21, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v21
-; GFX11-NEXT:    v_perm_b32 v22, v22, v33, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v33, 0x40c00000, v35
-; GFX11-NEXT:    v_add3_u32 v35, v36, v34, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_add3_u32 v32, v32, v21, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xffff0000, v20
-; GFX11-NEXT:    v_bfe_u32 v38, v33, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v34, v35, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-NEXT:    v_add_f32_e32 v20, 0x40c00000, v20
-; GFX11-NEXT:    v_or_b32_e32 v35, 0x400000, v33
-; GFX11-NEXT:    v_lshlrev_b32_e32 v36, 16, v19
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff0000, v19
-; GFX11-NEXT:    v_cndmask_b32_e32 v21, v32, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v32, v38, v33, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-NEXT:    v_dual_add_f32 v33, 0x40c00000, v36 :: v_dual_lshlrev_b32 v36, 16, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v21, v21, v34, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v34, v20, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v35, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v35, 0x400000, v20
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-NEXT:    v_bfe_u32 v37, v33, 16, 1
-; GFX11-NEXT:    v_add3_u32 v34, v34, v20, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v19, 0x40c00000, v19
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xffff0000, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v20, v34, v35, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v36
-; GFX11-NEXT:    v_add3_u32 v35, v37, v33, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v33
-; GFX11-NEXT:    v_bfe_u32 v37, v19, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-NEXT:    v_or_b32_e32 v39, 0x400000, v34
-; GFX11-NEXT:    v_perm_b32 v20, v20, v32, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v35, v36, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v35, v37, v19, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v19
-; GFX11-NEXT:    v_add3_u32 v37, v38, v34, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v38, 16, v17
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-NEXT:    v_bfe_u32 v48, v18, 16, 1
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff0000, v17
-; GFX11-NEXT:    v_cndmask_b32_e32 v19, v35, v36, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add3_u32 v36, v48, v18, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v17, 0x40c00000, v17
-; GFX11-NEXT:    v_perm_b32 v19, v19, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v34, v37, v39, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v18
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v16
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff0000, v16
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v18, v36, v37, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v16, 0x40c00000, v16
-; GFX11-NEXT:    v_add_f32_e32 v36, 0x40c00000, v39
-; GFX11-NEXT:    v_add3_u32 v37, v38, v35, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v35
-; GFX11-NEXT:    v_bfe_u32 v39, v17, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_bfe_u32 v48, v36, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v49, 0x400000, v36
-; GFX11-NEXT:    v_or_b32_e32 v50, 0x400000, v16
-; GFX11-NEXT:    v_perm_b32 v18, v18, v34, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v35, v37, v38, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v38, v39, v17, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v39, 0x400000, v17
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-NEXT:    v_bfe_u32 v37, v16, 16, 1
-; GFX11-NEXT:    v_add3_u32 v48, v48, v36, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v17, v38, v39, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-NEXT:    v_add3_u32 v37, v37, v16, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v17, v17, v35, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v36, v48, v49, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-NEXT:    v_cndmask_b32_e32 v16, v37, v50, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v16, v16, v36, 0x7060302
-; GFX11-NEXT:  .LBB9_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v64bf16_to_v32i32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v32
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB9_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v33, 0xffff0000, v14
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_lshlrev_b32 v32, 16, v15
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v32, 0x40c00000, v32
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v39, v33, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v32, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v32
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v32
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v32, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v32, v35, v38 :: v_dual_and_b32 v15, 0xffff0000, v15
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v15, 0x40c00000, v15 :: v_dual_lshlrev_b32 v14, 16, v14
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v39, v33, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v32.l, v32.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v15, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v15
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT:    v_add3_u32 v36, v36, v15, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v15, v36, v37
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v48, v14, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v49, 0x400000, v14
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v33
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v15, 0xffff, v32, v15
+; GFX11-TRUE16-NEXT:    v_add3_u32 v38, v48, v14, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v14, v38, v49, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v13
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v14.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v33, v35, v36 :: v_dual_add_f32 v34, 0x40c00000, v34
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v14, 0xffff, v14, v33
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v34, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v38, v13, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v36, v38, v13, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v13
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v13, v36, v37 :: v_dual_and_b32 v38, 0xffff0000, v12
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v35, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v13, 0xffff, v13, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v36
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v12, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v35, 0x400000, v12
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v12, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v12, v32, v35, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v11, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v10
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v11, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v11
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v36
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v11, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v33, v33, v38 :: v_dual_and_b32 v38, 0xffff0000, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v11, 0xffff, v11, v33
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v10, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v10, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v10, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v12, 0xffff, v12, v32
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v9, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v10, 0xffff, v10, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v9, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_cndmask_b32 v9, v32, v36
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v9.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v9, 0xffff, v9, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v8, 0xffff, v8, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v7, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v6, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v7, 0xffff, v7, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v6, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v32, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v4, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v6, 0xffff, v6, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v5, 0xffff, v5, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v4, 0xffff, v4, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_cndmask_b32 v3, v32, v36
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v3, 0xffff, v3, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v2, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v35, 0x40c00000, v38 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v34
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v31
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v31
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v31, 0x40c00000, v31
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v32, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v31, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v30
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v30
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v31, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v31
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v30, 0x40c00000, v30
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v31, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v30, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v0, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v31.l, v31.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v30, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v30
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v29
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v31, 0xffff, v31, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v30, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v29, 0x40c00000, v29
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.l, v30.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v29, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v30, 0xffff, v30, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v28
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v29, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v29
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v28, 0x40c00000, v28
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v29, v32, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v28, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v27
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v28, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v28
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v27, 0x40c00000, v27
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.l, v29.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v28, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v27, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v29, 0xffff, v29, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.l, v28.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v27, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v27
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v26
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v26
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v28, 0xffff, v28, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v27, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v26, 0x40c00000, v26
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.l, v27.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v26, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v27, 0xffff, v27, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v25
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v26, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v26
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v25, 0x40c00000, v25
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v26, v32, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v25, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v24
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v25, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v25
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v24, 0x40c00000, v24
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v26.l, v26.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v25, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v24, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v26, 0xffff, v26, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v25.l, v25.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v24, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v24
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v23
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v25, 0xffff, v25, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v24, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v23, 0x40c00000, v23
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v24.l, v24.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v23, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v24, 0xffff, v24, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v23, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v23
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff0000, v20
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v23, v32, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v22, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v21
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v22, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v22
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v21, 0x40c00000, v21
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v23.l, v23.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v22, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v21, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v23, 0xffff, v23, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.l, v22.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v21, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v21
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v36
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v22, 0xffff, v22, v33
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v20, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v21, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v39
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v20
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v20, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.l, v21.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v18
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v21, 0xffff, v21, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v19
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v20, v33, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v19, 0x40c00000, v19
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v32, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v19
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v36, v36, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v39, v35, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.l, v20.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v19, v36, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v39, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v18, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v19.h
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v33, v33, v38 :: v_dual_and_b32 v38, 0xffff0000, v17
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v20, 0xffff, v20, v32
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v37, 0x40c00000, v38 :: v_dual_cndmask_b32 v34, v34, v36
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v17, 0x40c00000, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v18
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v16
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v49, 0x400000, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v48, 0x400000, v37
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v19, 0xffff, v19, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v18, v35, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v38, v17, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v37, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v16, 0x40c00000, v16
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v39, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v38, v38, v17, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v51, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v37, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v50, v16, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v39, v39, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v17, v38, v49, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v49, 0x400000, v16
+; GFX11-TRUE16-NEXT:    v_add3_u32 v38, v50, v16, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v18.l, v18.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v17.l, v17.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v36, v39, v51, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v18, 0xffff, v18, v34
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.l, v36.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v35, v35, v48, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v17, 0xffff, v17, v35
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v16, v38, v49, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v16, 0xffff, v36, v16
+; GFX11-TRUE16-NEXT:  .LBB9_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v64bf16_to_v32i32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v32
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB9_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v33, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v33, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v32, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, 0x400000, v32
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v39, v14, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v32
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v37, v33, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v32, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v34, v35, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v39, v14, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v34, 0x400000, v33
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v36, v15, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v15
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v36, v36, v15, 0x7fff
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v15, v36, v38 :: v_dual_lshlrev_b32 v36, 16, v13
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v15, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v33, v37, v34 :: v_dual_add_f32 v34, 0x40c00000, v36
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v14
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v14, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v12
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v14, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v13, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_cndmask_b32 v32, v32, v36
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v13, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v13, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v13, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v12, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v12
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v12, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v34, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v12, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v11, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v11, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v10, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v10
+; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v11, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v35, v38 :: v_dual_lshlrev_b32 v37, 16, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_lshlrev_b32 v35, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v10, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v8, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v8, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v8
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v9, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v34, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v8, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_add_f32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v6, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v7, 0x40c00000, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v6, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v5
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v6, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v5
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v5, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_cndmask_b32 v4, v34, v38
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v4, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v3, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v31
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xffff0000, v31
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v31, 0x40c00000, v31
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v34, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xffff0000, v30
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v31, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v30, 0x40c00000, v30
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v31, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v31
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v30, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v31, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v29
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v30, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xffff0000, v29
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v29, 0x40c00000, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v30, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xffff0000, v28
+; GFX11-FAKE16-NEXT:    v_perm_b32 v31, v31, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v30, v30, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v29, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v28, 0x40c00000, v28
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v29, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v29
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v28, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v29, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v27
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v28, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xffff0000, v27
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v27, 0x40c00000, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v28, v34, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xffff0000, v26
+; GFX11-FAKE16-NEXT:    v_perm_b32 v29, v29, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v28, v28, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v27, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v26, 0x40c00000, v26
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v27, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v27
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v26, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v27, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v25
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v26, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xffff0000, v25
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v25, 0x40c00000, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v26, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xffff0000, v24
+; GFX11-FAKE16-NEXT:    v_perm_b32 v27, v27, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v26, v26, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v25, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v24, 0x40c00000, v24
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v25, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v25
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v24, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v25, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v23
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v24, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xffff0000, v23
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-FAKE16-NEXT:    v_perm_b32 v25, v25, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v23, 0x40c00000, v23
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v24, v34, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_perm_b32 v24, v24, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v23, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v23
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v23, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v22, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v23, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v21
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v22, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xffff0000, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v22
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v21, 0x40c00000, v21
+; GFX11-FAKE16-NEXT:    v_perm_b32 v23, v23, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v36, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v22, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v20
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v21, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v21
+; GFX11-FAKE16-NEXT:    v_perm_b32 v22, v22, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v33, 0x40c00000, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v36, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v21, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v33, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v34, v35, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, 0x400000, v33
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v36, 16, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff0000, v19
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v21, v32, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v38, v33, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v33, 0x40c00000, v36 :: v_dual_lshlrev_b32 v36, 16, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v21, v21, v34, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v20, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v35, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, 0x400000, v20
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v33, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v20, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v20, v34, v35, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v36
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v37, v33, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v33
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v19, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v39, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_perm_b32 v20, v20, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v35, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v37, v19, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v19
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v17
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v48, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff0000, v17
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v19, v35, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v36, v48, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v17, 0x40c00000, v17
+; GFX11-FAKE16-NEXT:    v_perm_b32 v19, v19, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v34, v37, v39, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v16
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v36, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v16, 0x40c00000, v16
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v39
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v39, v17, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v48, v36, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v49, 0x400000, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v50, 0x400000, v16
+; GFX11-FAKE16-NEXT:    v_perm_b32 v18, v18, v34, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v35, v37, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v38, v39, v17, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v39, 0x400000, v17
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v16, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v48, v48, v36, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v38, v39, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v37, v16, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v17, v17, v35, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v36, v48, v49, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v37, v50, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v16, v16, v36, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB9_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -20801,676 +22877,1224 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v32f32_to_v128i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x13
-; GFX11-NEXT:    scratch_store_b32 off, v40, s32 offset:88
-; GFX11-NEXT:    scratch_store_b32 off, v41, s32 offset:84
-; GFX11-NEXT:    scratch_store_b32 off, v42, s32 offset:80
-; GFX11-NEXT:    scratch_store_b32 off, v43, s32 offset:76
-; GFX11-NEXT:    scratch_store_b32 off, v44, s32 offset:72
-; GFX11-NEXT:    scratch_store_b32 off, v45, s32 offset:68
-; GFX11-NEXT:    scratch_store_b32 off, v46, s32 offset:64
-; GFX11-NEXT:    scratch_store_b32 off, v47, s32 offset:60
-; GFX11-NEXT:    scratch_store_b32 off, v56, s32 offset:56
-; GFX11-NEXT:    scratch_store_b32 off, v57, s32 offset:52
-; GFX11-NEXT:    scratch_store_b32 off, v58, s32 offset:48
-; GFX11-NEXT:    scratch_store_b32 off, v59, s32 offset:44
-; GFX11-NEXT:    scratch_store_b32 off, v60, s32 offset:40
-; GFX11-NEXT:    scratch_store_b32 off, v61, s32 offset:36
-; GFX11-NEXT:    scratch_store_b32 off, v62, s32 offset:32
-; GFX11-NEXT:    scratch_store_b32 off, v63, s32 offset:28
-; GFX11-NEXT:    scratch_store_b32 off, v72, s32 offset:24
-; GFX11-NEXT:    scratch_store_b32 off, v73, s32 offset:20
-; GFX11-NEXT:    scratch_store_b32 off, v74, s32 offset:16
-; GFX11-NEXT:    scratch_store_b32 off, v75, s32 offset:12
-; GFX11-NEXT:    s_clause 0x2
-; GFX11-NEXT:    scratch_load_b32 v33, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_b32 v32, off, s32 offset:4
-; GFX11-NEXT:    scratch_load_b32 v31, off, s32
-; GFX11-NEXT:    ; implicit-def: $vgpr75
-; GFX11-NEXT:    ; implicit-def: $vgpr74
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr73
-; GFX11-NEXT:    ; implicit-def: $vgpr72
-; GFX11-NEXT:    ; implicit-def: $vgpr63
-; GFX11-NEXT:    ; implicit-def: $vgpr62
-; GFX11-NEXT:    ; implicit-def: $vgpr61
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr60
-; GFX11-NEXT:    ; implicit-def: $vgpr59
-; GFX11-NEXT:    ; implicit-def: $vgpr58
-; GFX11-NEXT:    ; implicit-def: $vgpr57
-; GFX11-NEXT:    ; implicit-def: $vgpr56
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr47
-; GFX11-NEXT:    ; implicit-def: $vgpr46
-; GFX11-NEXT:    ; implicit-def: $vgpr45
-; GFX11-NEXT:    ; implicit-def: $vgpr44
-; GFX11-NEXT:    ; implicit-def: $vgpr43
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr42
-; GFX11-NEXT:    ; implicit-def: $vgpr41
-; GFX11-NEXT:    ; implicit-def: $vgpr40
-; GFX11-NEXT:    ; implicit-def: $vgpr183
-; GFX11-NEXT:    ; implicit-def: $vgpr182
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr181
-; GFX11-NEXT:    ; implicit-def: $vgpr180
-; GFX11-NEXT:    ; implicit-def: $vgpr179
-; GFX11-NEXT:    ; implicit-def: $vgpr178
-; GFX11-NEXT:    ; implicit-def: $vgpr177
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr176
-; GFX11-NEXT:    ; implicit-def: $vgpr167
-; GFX11-NEXT:    ; implicit-def: $vgpr166
-; GFX11-NEXT:    ; implicit-def: $vgpr165
-; GFX11-NEXT:    ; implicit-def: $vgpr164
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr163
-; GFX11-NEXT:    ; implicit-def: $vgpr162
-; GFX11-NEXT:    ; implicit-def: $vgpr161
-; GFX11-NEXT:    ; implicit-def: $vgpr160
-; GFX11-NEXT:    ; implicit-def: $vgpr151
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr150
-; GFX11-NEXT:    ; implicit-def: $vgpr149
-; GFX11-NEXT:    ; implicit-def: $vgpr148
-; GFX11-NEXT:    ; implicit-def: $vgpr147
-; GFX11-NEXT:    ; implicit-def: $vgpr146
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr145
-; GFX11-NEXT:    ; implicit-def: $vgpr144
-; GFX11-NEXT:    ; implicit-def: $vgpr135
-; GFX11-NEXT:    ; implicit-def: $vgpr134
-; GFX11-NEXT:    ; implicit-def: $vgpr133
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr132
-; GFX11-NEXT:    ; implicit-def: $vgpr131
-; GFX11-NEXT:    ; implicit-def: $vgpr130
-; GFX11-NEXT:    ; implicit-def: $vgpr129
-; GFX11-NEXT:    ; implicit-def: $vgpr128
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr119
-; GFX11-NEXT:    ; implicit-def: $vgpr118
-; GFX11-NEXT:    ; implicit-def: $vgpr117
-; GFX11-NEXT:    ; implicit-def: $vgpr116
-; GFX11-NEXT:    ; implicit-def: $vgpr115
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr114
-; GFX11-NEXT:    ; implicit-def: $vgpr113
-; GFX11-NEXT:    ; implicit-def: $vgpr112
-; GFX11-NEXT:    ; implicit-def: $vgpr103
-; GFX11-NEXT:    ; implicit-def: $vgpr102
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr101
-; GFX11-NEXT:    ; implicit-def: $vgpr100
-; GFX11-NEXT:    ; implicit-def: $vgpr99
-; GFX11-NEXT:    ; implicit-def: $vgpr98
-; GFX11-NEXT:    ; implicit-def: $vgpr97
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    s_waitcnt vmcnt(2)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v33
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB18_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b64 v[48:49], 24, v[19:20]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
-; GFX11-NEXT:    v_lshrrev_b64 v[49:50], 24, v[17:18]
-; GFX11-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
-; GFX11-NEXT:    v_lshrrev_b64 v[50:51], 24, v[15:16]
-; GFX11-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
-; GFX11-NEXT:    v_lshrrev_b64 v[51:52], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
-; GFX11-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
-; GFX11-NEXT:    v_lshrrev_b64 v[64:65], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
-; GFX11-NEXT:    v_lshrrev_b64 v[53:54], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[65:66], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v68, 24, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v69, 16, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v70, 8, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v71, 16, v31
-; GFX11-NEXT:    v_lshrrev_b32_e32 v80, 8, v31
-; GFX11-NEXT:    v_lshrrev_b32_e32 v81, 24, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v82, 16, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v83, 8, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v84, 16, v29
-; GFX11-NEXT:    v_lshrrev_b32_e32 v85, 8, v29
-; GFX11-NEXT:    v_lshrrev_b32_e32 v86, 24, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v87, 16, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v96, 8, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v97, 16, v27
-; GFX11-NEXT:    v_lshrrev_b32_e32 v98, 8, v27
-; GFX11-NEXT:    v_lshrrev_b32_e32 v99, 24, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v100, 16, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v101, 8, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v102, 16, v25
-; GFX11-NEXT:    v_lshrrev_b32_e32 v103, 8, v25
-; GFX11-NEXT:    v_lshrrev_b32_e32 v112, 24, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v113, 16, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v114, 8, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v115, 16, v23
-; GFX11-NEXT:    v_lshrrev_b32_e32 v116, 8, v23
-; GFX11-NEXT:    v_lshrrev_b32_e32 v117, 24, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v118, 16, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v119, 8, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v128, 16, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v129, 8, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v130, 24, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v131, 16, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v132, 8, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v133, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v134, 8, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v135, 24, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v144, 16, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v145, 8, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v146, 16, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v147, 8, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v148, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v149, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v150, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v151, 16, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v160, 8, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v161, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v162, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v163, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v164, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v165, 8, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v166, 24, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v167, 16, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v176, 8, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v177, 16, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v178, 8, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v179, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v180, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v181, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v182, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v183, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v40, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v41, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v42, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v43, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v44, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v45, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v46, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v47, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v56, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v57, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v58, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v59, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v60, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v61, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v62, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v63, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v72, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v73, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v74, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v75, 8, v1
-; GFX11-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
-; GFX11-NEXT:    v_lshrrev_b64 v[54:55], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[66:67], 24, v[1:2]
-; GFX11-NEXT:  .LBB18_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB18_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_dual_add_f32 v20, 1.0, v20 :: v_dual_add_f32 v19, 1.0, v19
-; GFX11-NEXT:    v_dual_add_f32 v18, 1.0, v18 :: v_dual_add_f32 v17, 1.0, v17
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_dual_add_f32 v24, 1.0, v24 :: v_dual_add_f32 v31, 1.0, v31
-; GFX11-NEXT:    v_dual_add_f32 v32, 1.0, v32 :: v_dual_add_f32 v23, 1.0, v23
-; GFX11-NEXT:    v_dual_add_f32 v16, 1.0, v16 :: v_dual_add_f32 v15, 1.0, v15
-; GFX11-NEXT:    v_dual_add_f32 v26, 1.0, v26 :: v_dual_add_f32 v29, 1.0, v29
-; GFX11-NEXT:    v_dual_add_f32 v30, 1.0, v30 :: v_dual_add_f32 v25, 1.0, v25
-; GFX11-NEXT:    v_dual_add_f32 v14, 1.0, v14 :: v_dual_add_f32 v13, 1.0, v13
-; GFX11-NEXT:    v_dual_add_f32 v28, 1.0, v28 :: v_dual_add_f32 v27, 1.0, v27
-; GFX11-NEXT:    v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v5
-; GFX11-NEXT:    v_dual_add_f32 v12, 1.0, v12 :: v_dual_add_f32 v11, 1.0, v11
-; GFX11-NEXT:    v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v3
-; GFX11-NEXT:    v_dual_add_f32 v10, 1.0, v10 :: v_dual_add_f32 v9, 1.0, v9
-; GFX11-NEXT:    v_lshrrev_b64 v[48:49], 24, v[19:20]
-; GFX11-NEXT:    v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1
-; GFX11-NEXT:    v_dual_add_f32 v8, 1.0, v8 :: v_dual_add_f32 v7, 1.0, v7
-; GFX11-NEXT:    v_dual_add_f32 v22, 1.0, v22 :: v_dual_add_f32 v21, 1.0, v21
-; GFX11-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
-; GFX11-NEXT:    v_lshrrev_b64 v[49:50], 24, v[17:18]
-; GFX11-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
-; GFX11-NEXT:    v_lshrrev_b64 v[50:51], 24, v[15:16]
-; GFX11-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
-; GFX11-NEXT:    v_lshrrev_b64 v[51:52], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
-; GFX11-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
-; GFX11-NEXT:    v_lshrrev_b64 v[64:65], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
-; GFX11-NEXT:    v_lshrrev_b64 v[53:54], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[65:66], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
-; GFX11-NEXT:    v_lshrrev_b64 v[54:55], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[66:67], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v68, 24, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v69, 16, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v70, 8, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v71, 16, v31
-; GFX11-NEXT:    v_lshrrev_b32_e32 v80, 8, v31
-; GFX11-NEXT:    v_lshrrev_b32_e32 v81, 24, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v82, 16, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v83, 8, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v84, 16, v29
-; GFX11-NEXT:    v_lshrrev_b32_e32 v85, 8, v29
-; GFX11-NEXT:    v_lshrrev_b32_e32 v86, 24, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v87, 16, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v96, 8, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v97, 16, v27
-; GFX11-NEXT:    v_lshrrev_b32_e32 v98, 8, v27
-; GFX11-NEXT:    v_lshrrev_b32_e32 v99, 24, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v100, 16, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v101, 8, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v102, 16, v25
-; GFX11-NEXT:    v_lshrrev_b32_e32 v103, 8, v25
-; GFX11-NEXT:    v_lshrrev_b32_e32 v112, 24, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v113, 16, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v114, 8, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v115, 16, v23
-; GFX11-NEXT:    v_lshrrev_b32_e32 v116, 8, v23
-; GFX11-NEXT:    v_lshrrev_b32_e32 v117, 24, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v118, 16, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v119, 8, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v128, 16, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v129, 8, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v130, 24, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v131, 16, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v132, 8, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v133, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v134, 8, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v135, 24, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v144, 16, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v145, 8, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v146, 16, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v147, 8, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v148, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v149, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v150, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v151, 16, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v160, 8, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v161, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v162, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v163, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v164, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v165, 8, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v166, 24, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v167, 16, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v176, 8, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v177, 16, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v178, 8, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v179, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v180, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v181, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v182, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v183, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v40, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v41, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v42, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v43, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v44, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v45, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v46, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v47, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v56, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v57, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v58, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v59, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v60, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v61, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v62, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v63, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v72, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v73, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v74, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v75, 8, v1
-; GFX11-NEXT:  .LBB18_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v75
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v66
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_lshlrev_b16 v66, 8, v63
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v65
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v55
-; GFX11-NEXT:    v_and_b32_e32 v55, 0xff, v74
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v67, 0xff, v61
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_or_b32_e32 v39, v55, v39
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v73
-; GFX11-NEXT:    v_or_b32_e32 v65, v67, v65
-; GFX11-NEXT:    v_lshlrev_b16 v67, 8, v58
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v39
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v55
-; GFX11-NEXT:    v_and_b32_e32 v55, 0xff, v72
-; GFX11-NEXT:    v_lshlrev_b16 v64, 8, v64
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v39
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_or_b32_e32 v55, v55, v66
-; GFX11-NEXT:    v_lshlrev_b16 v66, 8, v62
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v54
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v66
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v60
-; GFX11-NEXT:    v_and_b32_e32 v66, 0xff, v59
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v53
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v39
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v65
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v55
-; GFX11-NEXT:    v_or_b32_e32 v55, v66, v67
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v57
-; GFX11-NEXT:    v_and_b32_e32 v66, 0xff, v56
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v39
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v65
-; GFX11-NEXT:    v_or_b32_e32 v55, v66, v64
-; GFX11-NEXT:    v_lshlrev_b16 v64, 8, v47
-; GFX11-NEXT:    v_and_b32_e32 v65, 0xff, v46
-; GFX11-NEXT:    v_lshlrev_b16 v66, 8, v45
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v39
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v64
-; GFX11-NEXT:    v_or_b32_e32 v55, v65, v66
-; GFX11-NEXT:    v_lshlrev_b16 v64, 8, v44
-; GFX11-NEXT:    v_and_b32_e32 v65, 0xff, v43
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v39
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v64
-; GFX11-NEXT:    v_or_b32_e32 v54, v65, v54
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v42
-; GFX11-NEXT:    v_and_b32_e32 v64, 0xff, v41
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v40
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v39
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v54
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v55
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_or_b32_e32 v54, v64, v65
-; GFX11-NEXT:    v_and_b32_e32 v64, 0xff, v182
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v183
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v181
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v54, 16, v54
-; GFX11-NEXT:    v_or_b32_e32 v53, v64, v53
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v55
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v65
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v39
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v54
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v53
-; GFX11-NEXT:    v_and_b32_e32 v53, 0xff, v180
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v179
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v178
-; GFX11-NEXT:    v_and_b32_e32 v64, 0xff, v177
-; GFX11-NEXT:    v_lshlrev_b16 v52, 8, v52
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v176
-; GFX11-NEXT:    v_and_b32_e32 v66, 0xff, v167
-; GFX11-NEXT:    v_lshlrev_b16 v67, 8, v166
-; GFX11-NEXT:    v_or_b32_e32 v53, v53, v54
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v55
-; GFX11-NEXT:    v_or_b32_e32 v52, v64, v52
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v65
-; GFX11-NEXT:    v_or_b32_e32 v54, v66, v67
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v53, 16, v53
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v52, 16, v52
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v54, 16, v54
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off
-; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
-; GFX11-NEXT:    v_or_b32_e32 v1, v9, v39
-; GFX11-NEXT:    v_or_b32_e32 v2, v10, v53
-; GFX11-NEXT:    v_or_b32_e32 v3, v11, v52
-; GFX11-NEXT:    v_or_b32_e32 v4, v12, v54
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v13
-; GFX11-NEXT:    v_lshlrev_b16 v6, 8, v165
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v164
-; GFX11-NEXT:    v_lshlrev_b16 v8, 8, v51
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v14
-; GFX11-NEXT:    v_lshlrev_b16 v10, 8, v163
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v162
-; GFX11-NEXT:    v_lshlrev_b16 v12, 8, v161
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v15
-; GFX11-NEXT:    v_lshlrev_b16 v14, 8, v160
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v8, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v9, v13, v14
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v151
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v50
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v16
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v150
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v149
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v148
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v17
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v147
-; GFX11-NEXT:    v_and_b32_e32 v39, 0xff, v146
-; GFX11-NEXT:    v_lshlrev_b16 v49, 8, v49
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v11, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v12, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v13, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v14, v39, v49
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v8, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v9, v13, v14
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v18
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v145
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v144
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v135
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v19
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v134
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v133
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v48
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v20
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v132
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v11, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v12, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v13, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v14, v18, v19
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v131
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v130
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v21
-; GFX11-NEXT:    v_lshlrev_b16 v18, 8, v129
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v128
-; GFX11-NEXT:    v_lshlrev_b16 v20, 8, v38
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v22
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v119
-; GFX11-NEXT:    v_and_b32_e32 v38, 0xff, v118
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v117
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v16
-; GFX11-NEXT:    v_or_b32_e32 v16, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v17, v19, v20
-; GFX11-NEXT:    v_or_b32_e32 v18, v21, v22
-; GFX11-NEXT:    v_or_b32_e32 v19, v38, v39
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xffff, v18
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v11, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v12, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v13, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v14, v18, v19
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v23
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v116
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v115
-; GFX11-NEXT:    v_lshlrev_b16 v18, 8, v37
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v24
-; GFX11-NEXT:    v_lshlrev_b16 v20, 8, v114
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v113
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v112
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v25
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v103
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v16
-; GFX11-NEXT:    v_or_b32_e32 v16, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v17, v19, v20
-; GFX11-NEXT:    v_or_b32_e32 v18, v21, v22
-; GFX11-NEXT:    v_or_b32_e32 v19, v23, v24
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v102
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v36
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v26
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v101
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v100
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v99
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v27
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v98
-; GFX11-NEXT:    v_and_b32_e32 v36, 0xff, v97
-; GFX11-NEXT:    v_lshlrev_b16 v35, 8, v35
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v21, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v22, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v23, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v24, v36, v35
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff, v19
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xffff, v21
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xffff, v23
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v16
-; GFX11-NEXT:    v_or_b32_e32 v16, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v17, v19, v20
-; GFX11-NEXT:    v_or_b32_e32 v18, v21, v22
-; GFX11-NEXT:    v_or_b32_e32 v19, v23, v24
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v28
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v96
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v87
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v86
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v29
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v85
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v84
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v34
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v30
-; GFX11-NEXT:    v_lshlrev_b16 v29, 8, v83
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v21, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v22, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v23, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v24, v28, v29
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v82
-; GFX11-NEXT:    v_lshlrev_b16 v26, 8, v81
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v31
-; GFX11-NEXT:    v_lshlrev_b16 v28, 8, v80
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v71
-; GFX11-NEXT:    v_lshlrev_b16 v30, 8, v33
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v32
-; GFX11-NEXT:    v_lshlrev_b16 v32, 8, v70
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xff, v69
-; GFX11-NEXT:    v_lshlrev_b16 v34, 8, v68
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v26
-; GFX11-NEXT:    v_or_b32_e32 v26, v27, v28
-; GFX11-NEXT:    v_or_b32_e32 v27, v29, v30
-; GFX11-NEXT:    v_or_b32_e32 v28, v31, v32
-; GFX11-NEXT:    v_or_b32_e32 v29, v33, v34
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xffff, v20
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xffff, v22
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xffff, v24
-; GFX11-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xffff, v26
-; GFX11-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xffff, v28
-; GFX11-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v21, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v22, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v23, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v24, v28, v29
-; GFX11-NEXT:    s_clause 0x5
-; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off offset:32
-; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:48
-; GFX11-NEXT:    scratch_store_b128 v0, v[9:12], off offset:64
-; GFX11-NEXT:    scratch_store_b128 v0, v[13:16], off offset:80
-; GFX11-NEXT:    scratch_store_b128 v0, v[17:20], off offset:96
-; GFX11-NEXT:    scratch_store_b128 v0, v[21:24], off offset:112
-; GFX11-NEXT:    s_clause 0x13
-; GFX11-NEXT:    scratch_load_b32 v75, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_b32 v74, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_b32 v73, off, s32 offset:20
-; GFX11-NEXT:    scratch_load_b32 v72, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_b32 v63, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_b32 v62, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_b32 v61, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_b32 v60, off, s32 offset:40
-; GFX11-NEXT:    scratch_load_b32 v59, off, s32 offset:44
-; GFX11-NEXT:    scratch_load_b32 v58, off, s32 offset:48
-; GFX11-NEXT:    scratch_load_b32 v57, off, s32 offset:52
-; GFX11-NEXT:    scratch_load_b32 v56, off, s32 offset:56
-; GFX11-NEXT:    scratch_load_b32 v47, off, s32 offset:60
-; GFX11-NEXT:    scratch_load_b32 v46, off, s32 offset:64
-; GFX11-NEXT:    scratch_load_b32 v45, off, s32 offset:68
-; GFX11-NEXT:    scratch_load_b32 v44, off, s32 offset:72
-; GFX11-NEXT:    scratch_load_b32 v43, off, s32 offset:76
-; GFX11-NEXT:    scratch_load_b32 v42, off, s32 offset:80
-; GFX11-NEXT:    scratch_load_b32 v41, off, s32 offset:84
-; GFX11-NEXT:    scratch_load_b32 v40, off, s32 offset:88
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v32f32_to_v128i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x2
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v33, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr162_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr161_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr160_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr151_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr150_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr149_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr148_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr147_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr145_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr144_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr134_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr133_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr132_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr131_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr130_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr128_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr119_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr118_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr117_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr116_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr115_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr114_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr113_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr103_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr101_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr100_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr99_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr97_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr86_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr85_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr83_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr71_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr70_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr68_lo16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v33
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB18_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[48:49], 24, v[19:20]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[49:50], 24, v[17:18]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[50:51], 24, v[15:16]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[51:52], 24, v[13:14]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[64:65], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[53:54], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[65:66], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v68, 24, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v69, 8, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v70, 8, v31
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v71, 24, v30
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v80, 8, v30
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v81, 8, v29
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v82, 24, v28
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v83, 8, v28
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v84, 8, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v85, 24, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v86, 8, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v87, 8, v25
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v96, 24, v24
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v97, 8, v24
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v98, 8, v23
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v99, 24, v22
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v100, 8, v22
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v101, 8, v21
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v102, 24, v20
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v103, 8, v20
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v112, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v113, 24, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v114, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v115, 8, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v116, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v117, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v118, 8, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v119, 24, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v128, 8, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v129, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v130, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v131, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v132, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v133, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v134, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v135, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v144, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v145, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v146, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v147, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v148, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v149, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v150, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v151, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v160, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v161, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v162, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[54:55], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[66:67], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB18_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB18_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v20, 1.0, v20 :: v_dual_add_f32 v19, 1.0, v19
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v18, 1.0, v18 :: v_dual_add_f32 v17, 1.0, v17
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v24, 1.0, v24 :: v_dual_add_f32 v31, 1.0, v31
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v32, 1.0, v32 :: v_dual_add_f32 v23, 1.0, v23
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v16, 1.0, v16 :: v_dual_add_f32 v15, 1.0, v15
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v26, 1.0, v26 :: v_dual_add_f32 v29, 1.0, v29
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v30, 1.0, v30 :: v_dual_add_f32 v25, 1.0, v25
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v14, 1.0, v14 :: v_dual_add_f32 v13, 1.0, v13
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v28, 1.0, v28 :: v_dual_add_f32 v27, 1.0, v27
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v5
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v12, 1.0, v12 :: v_dual_add_f32 v11, 1.0, v11
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v3
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v10, 1.0, v10 :: v_dual_add_f32 v9, 1.0, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[48:49], 24, v[19:20]
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v8, 1.0, v8 :: v_dual_add_f32 v7, 1.0, v7
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v22, 1.0, v22 :: v_dual_add_f32 v21, 1.0, v21
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[49:50], 24, v[17:18]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[50:51], 24, v[15:16]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[51:52], 24, v[13:14]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[64:65], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[53:54], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[65:66], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[54:55], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[66:67], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v68, 24, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v69, 8, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v70, 8, v31
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v71, 24, v30
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v80, 8, v30
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v81, 8, v29
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v82, 24, v28
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v83, 8, v28
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v84, 8, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v85, 24, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v86, 8, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v87, 8, v25
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v96, 24, v24
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v97, 8, v24
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v98, 8, v23
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v99, 24, v22
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v100, 8, v22
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v101, 8, v21
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v102, 24, v20
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v103, 8, v20
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v112, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v113, 24, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v114, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v115, 8, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v116, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v117, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v118, 8, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v119, 24, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v128, 8, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v129, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v130, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v131, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v132, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v133, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v134, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v135, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v144, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v145, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v146, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v147, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v148, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v149, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v150, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v151, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v160, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v161, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v162, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB18_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v39.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v34.h, 8, v66.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v33.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v161.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v39.l, v1.h, v34.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v162.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v39
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.h, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v55, 0xffff, v55
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v160.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v150.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v66.l, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v67.l, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v65.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v55, v39
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v55, 0xffff, v66
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v65, 16, v67
+; GFX11-TRUE16-NEXT:    v_or_b16 v39.l, v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 8, v151.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v55, v65
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v39
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.h, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.h, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v149.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v55, 16, v55
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.l, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v66.l, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v64.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v3.h, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v39, v55
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v65
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v55, 16, v66
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v4.h, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.l, 8, v148.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v147.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v39, v55
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.h, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.h, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v54.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v64
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v146.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v55
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v5.h, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v39, v54
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v64
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v145.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v144.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v55
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v39, v54
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v55
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v53.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v134.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.l, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v8.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v135.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v10.l, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v53, 0xffff, v53
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v55, 16, v55
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v64
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.h, v8.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.l, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v11.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v53, v55
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v55, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v10.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v132.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v52.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v39, v54
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v133.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v11.h
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v129.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v131.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v34.h, 8, v130.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v51.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v33.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v39.l, v12.h, v34.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v10, v11
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v128.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v15.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v50.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v39
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v55, v9
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v14.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v119.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v118.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v6
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v12, v39
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v16.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v117.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v16.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v116.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v10, v11
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v114.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v115.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v18.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v113.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v12, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v14, v15
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v19.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v112.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v19.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v48.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v20.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v102.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v16, v17
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v20.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v103.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v11
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v21.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v101.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v14.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v21.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v38.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v15, v16
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.l, 0xff, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v98.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v14
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v100.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v17, v18
+; GFX11-TRUE16-NEXT:    v_and_b16 v16.l, 0xff, v23.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v37.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v97.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v15.l, v15.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v19, v20
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v24.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v96.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v25.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v87.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v16.l, v16.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v17.l, v17.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.l, 0xff, v25.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v36.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v21, v22
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v18.l, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v19.l, v19.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v16
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff, v17
+; GFX11-TRUE16-NEXT:    v_and_b16 v16.l, 0xff, v26.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v86.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v26.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v85.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v15.l, v15.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff, v19
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v16.l, v16.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v17.l, v17.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v15
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v27.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v84.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v27.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v16
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v20, v21
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, v22, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, v24, v25
+; GFX11-TRUE16-NEXT:    v_and_b16 v20.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v83.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v21.l, 0xff, v28.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.h, 8, v82.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v29.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v22.h, 8, v81.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v29.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.h, 8, v34.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v30.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v24.h, 8, v80.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v18.l, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v20.l, v20.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v21.l, v21.l, v21.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v22.l, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v23.l, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v24.l, v24.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v49.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v99.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v35.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v35, 0xffff, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v18, v26, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v20
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v21
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v27, 0xffff, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v23
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v29, 0xffff, v24
+; GFX11-TRUE16-NEXT:    v_and_b16 v20.l, 0xff, v30.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v71.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v21.l, 0xff, v31.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.h, 8, v70.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v31.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v22.h, 8, v33.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v32.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.h, 8, v69.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v32.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v24.h, 8, v68.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v14.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v19.l, v19.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v53, 0xffff, v64
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v65
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v20.l, v20.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v21.l, v21.l, v21.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v22.l, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v23.l, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v24.l, v24.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v53, v54
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v20
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff, v21
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v22
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v33, 0xffff, v23
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v39, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v38, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v19, v35, v19
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, v25, v26
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, v27, v28
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, v29, v30
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, v31, v32
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, v33, v24
+; GFX11-TRUE16-NEXT:    s_clause 0x5
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off offset:32
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:48
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[9:12], off offset:64
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[13:16], off offset:80
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[17:20], off offset:96
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[21:24], off offset:112
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v32f32_to_v128i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x13
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s32 offset:88
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v41, s32 offset:84
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v42, s32 offset:80
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v43, s32 offset:76
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v44, s32 offset:72
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v45, s32 offset:68
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v46, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v47, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v56, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v57, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v58, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v59, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v60, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v61, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v62, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v63, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v72, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v73, s32 offset:20
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v74, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v75, s32 offset:12
+; GFX11-FAKE16-NEXT:    s_clause 0x2
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v33, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr75
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr74
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr73
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr72
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr63
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr62
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr61
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr60
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr59
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr58
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr57
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr56
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr47
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr46
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr45
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr44
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr43
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr42
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr41
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr40
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr183
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr182
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr181
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr180
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr179
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr178
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr177
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr176
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr167
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr166
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr165
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr164
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr163
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr162
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr161
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr160
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr151
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr150
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr149
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr148
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr147
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr144
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr135
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB18_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[48:49], 24, v[19:20]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[49:50], 24, v[17:18]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[50:51], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[51:52], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[64:65], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[53:54], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[65:66], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v68, 24, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v69, 16, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v70, 8, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 16, v31
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 8, v31
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v81, 24, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v82, 16, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 8, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 16, v29
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v85, 8, v29
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v86, 24, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 16, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 8, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v97, 16, v27
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v98, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v99, 24, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v100, 16, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v101, 8, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v102, 16, v25
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v103, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v112, 24, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v113, 16, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v114, 8, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v115, 16, v23
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v116, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v117, 24, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v118, 16, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v119, 8, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v128, 16, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v129, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v130, 24, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v131, 16, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v132, 8, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v133, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v134, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v135, 24, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v144, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v145, 8, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v146, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v147, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v148, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v149, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v150, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v151, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v160, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v161, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v162, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v163, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v164, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v165, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v166, 24, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v167, 16, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v176, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v177, 16, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v178, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v179, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v180, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v181, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v182, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v183, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v40, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v41, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v42, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v43, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v44, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v45, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v46, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v47, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v56, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v57, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v58, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v59, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v60, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v61, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v62, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v63, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v72, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v73, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v74, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v75, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[54:55], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[66:67], 24, v[1:2]
+; GFX11-FAKE16-NEXT:  .LBB18_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB18_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v20, 1.0, v20 :: v_dual_add_f32 v19, 1.0, v19
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v18, 1.0, v18 :: v_dual_add_f32 v17, 1.0, v17
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v24, 1.0, v24 :: v_dual_add_f32 v31, 1.0, v31
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v32, 1.0, v32 :: v_dual_add_f32 v23, 1.0, v23
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v16, 1.0, v16 :: v_dual_add_f32 v15, 1.0, v15
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v26, 1.0, v26 :: v_dual_add_f32 v29, 1.0, v29
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v30, 1.0, v30 :: v_dual_add_f32 v25, 1.0, v25
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v14, 1.0, v14 :: v_dual_add_f32 v13, 1.0, v13
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v28, 1.0, v28 :: v_dual_add_f32 v27, 1.0, v27
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v5
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v12, 1.0, v12 :: v_dual_add_f32 v11, 1.0, v11
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v3
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v10, 1.0, v10 :: v_dual_add_f32 v9, 1.0, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[48:49], 24, v[19:20]
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v8, 1.0, v8 :: v_dual_add_f32 v7, 1.0, v7
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v22, 1.0, v22 :: v_dual_add_f32 v21, 1.0, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[49:50], 24, v[17:18]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[50:51], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[51:52], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[64:65], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[53:54], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[65:66], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[54:55], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[66:67], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v68, 24, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v69, 16, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v70, 8, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 16, v31
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 8, v31
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v81, 24, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v82, 16, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 8, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 16, v29
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v85, 8, v29
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v86, 24, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 16, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 8, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v97, 16, v27
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v98, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v99, 24, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v100, 16, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v101, 8, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v102, 16, v25
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v103, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v112, 24, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v113, 16, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v114, 8, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v115, 16, v23
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v116, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v117, 24, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v118, 16, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v119, 8, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v128, 16, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v129, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v130, 24, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v131, 16, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v132, 8, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v133, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v134, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v135, 24, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v144, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v145, 8, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v146, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v147, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v148, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v149, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v150, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v151, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v160, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v161, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v162, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v163, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v164, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v165, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v166, 24, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v167, 16, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v176, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v177, 16, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v178, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v179, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v180, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v181, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v182, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v183, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v40, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v41, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v42, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v43, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v44, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v45, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v46, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v47, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v56, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v57, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v58, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v59, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v60, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v61, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v62, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v63, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v72, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v73, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v74, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v75, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB18_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v75
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v66
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v66, 8, v63
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v55, 0xff, v74
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v67, 0xff, v61
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v39, v55, v39
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v73
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v65, v67, v65
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v67, 8, v58
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v55, 0xff, v72
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v64, 8, v64
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, v55, v66
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v66, 8, v62
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v66
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v60
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v66, 0xff, v59
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v53, 8, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, v66, v67
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v57
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v66, 0xff, v56
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, v66, v64
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v64, 8, v47
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v65, 0xff, v46
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v66, 8, v45
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v64
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, v65, v66
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v64, 8, v44
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v65, 0xff, v43
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v64
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v54, v65, v54
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v42
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v64, 0xff, v41
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v40
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v39
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v54, v64, v65
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v64, 0xff, v182
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v183
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v181
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v53, v64, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v54
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v53
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v53, 0xff, v180
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v179
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v178
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v64, 0xff, v177
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v52, 8, v52
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v176
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v66, 0xff, v167
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v67, 8, v166
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v53, v53, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v52, v64, v52
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v54, v66, v67
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v53, 16, v53
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v52, 16, v52
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v54
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v9, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v10, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v11, v52
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v12, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v6, 8, v165
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v164
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v51
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v10, 8, v163
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v162
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v12, 8, v161
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v14, 8, v160
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v13, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v151
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v50
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v150
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v149
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v148
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v147
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v39, 0xff, v146
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v49, 8, v49
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v39, v49
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v13, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v145
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v144
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v135
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v134
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v133
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v48
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v132
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v18, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v131
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v130
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v18, 8, v129
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v128
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v38
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v119
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v38, 0xff, v118
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v117
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v19, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v21, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v38, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xffff, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v18, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v116
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v115
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v18, 8, v37
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v114
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v113
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v112
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v103
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v19, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v21, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v23, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v102
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v101
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v100
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v99
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v98
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v36, 0xff, v97
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v35, 8, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v36, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xffff, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v19, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v21, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v23, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v96
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v87
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v86
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v29
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v84
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v29, 8, v83
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v28, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v82
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v26, 8, v81
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v28, 8, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v71
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v30, 8, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v32, 8, v70
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xff, v69
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v34, 8, v68
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v27, v28
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v29, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v31, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v33, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xffff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xffff, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xffff, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xffff, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xffff, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v28, v29
+; GFX11-FAKE16-NEXT:    s_clause 0x5
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off offset:32
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:48
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[9:12], off offset:64
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[13:16], off offset:80
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[17:20], off offset:96
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[21:24], off offset:112
+; GFX11-FAKE16-NEXT:    s_clause 0x13
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v75, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v74, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v73, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v72, off, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v63, off, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v62, off, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v61, off, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v60, off, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v59, off, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v58, off, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v57, off, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v56, off, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v47, off, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v46, off, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v45, off, s32 offset:68
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v44, off, s32 offset:72
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v43, off, s32 offset:76
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v42, off, s32 offset:80
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v41, off, s32 offset:84
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s32 offset:88
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -25562,1038 +28186,1985 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v128i8_to_v32f32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_store_b32 off, v40, s32 offset:592
-; GFX11-NEXT:    scratch_store_b32 off, v41, s32 offset:588
-; GFX11-NEXT:    scratch_store_b32 off, v42, s32 offset:584
-; GFX11-NEXT:    scratch_store_b32 off, v43, s32 offset:580
-; GFX11-NEXT:    scratch_store_b32 off, v44, s32 offset:576
-; GFX11-NEXT:    scratch_store_b32 off, v45, s32 offset:572
-; GFX11-NEXT:    scratch_store_b32 off, v46, s32 offset:568
-; GFX11-NEXT:    scratch_store_b32 off, v47, s32 offset:564
-; GFX11-NEXT:    scratch_store_b32 off, v56, s32 offset:560
-; GFX11-NEXT:    scratch_store_b32 off, v57, s32 offset:556
-; GFX11-NEXT:    scratch_store_b32 off, v58, s32 offset:552
-; GFX11-NEXT:    scratch_store_b32 off, v59, s32 offset:548
-; GFX11-NEXT:    scratch_store_b32 off, v60, s32 offset:544
-; GFX11-NEXT:    scratch_store_b32 off, v61, s32 offset:540
-; GFX11-NEXT:    scratch_store_b32 off, v62, s32 offset:536
-; GFX11-NEXT:    scratch_store_b32 off, v63, s32 offset:532
-; GFX11-NEXT:    scratch_store_b32 off, v72, s32 offset:528
-; GFX11-NEXT:    scratch_store_b32 off, v73, s32 offset:524
-; GFX11-NEXT:    scratch_store_b32 off, v74, s32 offset:520
-; GFX11-NEXT:    scratch_store_b32 off, v75, s32 offset:516
-; GFX11-NEXT:    scratch_store_b32 off, v76, s32 offset:512
-; GFX11-NEXT:    scratch_store_b32 off, v77, s32 offset:508
-; GFX11-NEXT:    scratch_store_b32 off, v78, s32 offset:504
-; GFX11-NEXT:    scratch_store_b32 off, v79, s32 offset:500
-; GFX11-NEXT:    scratch_store_b32 off, v88, s32 offset:496
-; GFX11-NEXT:    scratch_store_b32 off, v89, s32 offset:492
-; GFX11-NEXT:    scratch_store_b32 off, v90, s32 offset:488
-; GFX11-NEXT:    scratch_store_b32 off, v91, s32 offset:484
-; GFX11-NEXT:    scratch_store_b32 off, v92, s32 offset:480
-; GFX11-NEXT:    scratch_store_b32 off, v93, s32 offset:476
-; GFX11-NEXT:    scratch_store_b32 off, v94, s32 offset:472
-; GFX11-NEXT:    scratch_store_b32 off, v95, s32 offset:468
-; GFX11-NEXT:    s_clause 0x12
-; GFX11-NEXT:    scratch_store_b32 off, v104, s32 offset:464
-; GFX11-NEXT:    scratch_store_b32 off, v105, s32 offset:460
-; GFX11-NEXT:    scratch_store_b32 off, v106, s32 offset:456
-; GFX11-NEXT:    scratch_store_b32 off, v107, s32 offset:452
-; GFX11-NEXT:    scratch_store_b32 off, v108, s32 offset:448
-; GFX11-NEXT:    scratch_store_b32 off, v109, s32 offset:444
-; GFX11-NEXT:    scratch_store_b32 off, v110, s32 offset:440
-; GFX11-NEXT:    scratch_store_b32 off, v111, s32 offset:436
-; GFX11-NEXT:    scratch_store_b32 off, v120, s32 offset:432
-; GFX11-NEXT:    scratch_store_b32 off, v121, s32 offset:428
-; GFX11-NEXT:    scratch_store_b32 off, v122, s32 offset:424
-; GFX11-NEXT:    scratch_store_b32 off, v123, s32 offset:420
-; GFX11-NEXT:    scratch_store_b32 off, v124, s32 offset:416
-; GFX11-NEXT:    scratch_store_b32 off, v125, s32 offset:412
-; GFX11-NEXT:    scratch_store_b32 off, v126, s32 offset:408
-; GFX11-NEXT:    scratch_store_b32 off, v127, s32 offset:404
-; GFX11-NEXT:    scratch_store_b32 off, v136, s32 offset:400
-; GFX11-NEXT:    scratch_store_b32 off, v137, s32 offset:396
-; GFX11-NEXT:    scratch_store_b32 off, v138, s32 offset:392
-; GFX11-NEXT:    v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28
-; GFX11-NEXT:    v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24
-; GFX11-NEXT:    v_dual_mov_b32 v36, v22 :: v_dual_mov_b32 v37, v20
-; GFX11-NEXT:    v_dual_mov_b32 v38, v18 :: v_dual_mov_b32 v39, v16
-; GFX11-NEXT:    v_dual_mov_b32 v48, v14 :: v_dual_mov_b32 v49, v12
-; GFX11-NEXT:    v_dual_mov_b32 v50, v10 :: v_dual_mov_b32 v51, v8
-; GFX11-NEXT:    v_dual_mov_b32 v52, v6 :: v_dual_mov_b32 v53, v4
-; GFX11-NEXT:    v_dual_mov_b32 v54, v2 :: v_dual_mov_b32 v55, v0
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v0, off, s32 offset:384
-; GFX11-NEXT:    scratch_load_u16 v64, off, s32 offset:380
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32 offset:376
-; GFX11-NEXT:    scratch_load_u16 v65, off, s32 offset:372
-; GFX11-NEXT:    scratch_load_u16 v4, off, s32 offset:368
-; GFX11-NEXT:    scratch_load_u16 v66, off, s32 offset:364
-; GFX11-NEXT:    scratch_load_u16 v6, off, s32 offset:360
-; GFX11-NEXT:    scratch_load_u16 v67, off, s32 offset:356
-; GFX11-NEXT:    scratch_load_u16 v8, off, s32 offset:352
-; GFX11-NEXT:    scratch_load_u16 v68, off, s32 offset:348
-; GFX11-NEXT:    scratch_load_u16 v10, off, s32 offset:344
-; GFX11-NEXT:    scratch_load_u16 v69, off, s32 offset:340
-; GFX11-NEXT:    scratch_load_u16 v12, off, s32 offset:336
-; GFX11-NEXT:    scratch_load_u16 v70, off, s32 offset:332
-; GFX11-NEXT:    scratch_load_u16 v14, off, s32 offset:328
-; GFX11-NEXT:    scratch_load_u16 v71, off, s32 offset:324
-; GFX11-NEXT:    scratch_load_u16 v16, off, s32 offset:320
-; GFX11-NEXT:    scratch_load_u16 v80, off, s32 offset:316
-; GFX11-NEXT:    scratch_load_u16 v18, off, s32 offset:312
-; GFX11-NEXT:    scratch_load_u16 v81, off, s32 offset:308
-; GFX11-NEXT:    scratch_load_u16 v20, off, s32 offset:304
-; GFX11-NEXT:    scratch_load_u16 v82, off, s32 offset:300
-; GFX11-NEXT:    scratch_load_u16 v22, off, s32 offset:296
-; GFX11-NEXT:    scratch_load_u16 v83, off, s32 offset:292
-; GFX11-NEXT:    scratch_load_u16 v24, off, s32 offset:288
-; GFX11-NEXT:    scratch_load_u16 v84, off, s32 offset:284
-; GFX11-NEXT:    scratch_load_u16 v26, off, s32 offset:280
-; GFX11-NEXT:    scratch_load_u16 v85, off, s32 offset:276
-; GFX11-NEXT:    scratch_load_u16 v28, off, s32 offset:272
-; GFX11-NEXT:    scratch_load_u16 v86, off, s32 offset:268
-; GFX11-NEXT:    scratch_load_u16 v30, off, s32 offset:264
-; GFX11-NEXT:    scratch_load_u16 v87, off, s32 offset:260
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v31, off, s32 offset:256
-; GFX11-NEXT:    scratch_load_u16 v96, off, s32 offset:252
-; GFX11-NEXT:    scratch_load_u16 v99, off, s32 offset:248
-; GFX11-NEXT:    scratch_load_u16 v97, off, s32 offset:244
-; GFX11-NEXT:    scratch_load_u16 v100, off, s32 offset:240
-; GFX11-NEXT:    scratch_load_u16 v98, off, s32 offset:236
-; GFX11-NEXT:    scratch_load_u16 v101, off, s32 offset:232
-; GFX11-NEXT:    scratch_load_u16 v112, off, s32 offset:228
-; GFX11-NEXT:    scratch_load_u16 v102, off, s32 offset:224
-; GFX11-NEXT:    scratch_load_u16 v113, off, s32 offset:220
-; GFX11-NEXT:    scratch_load_u16 v103, off, s32 offset:216
-; GFX11-NEXT:    scratch_load_b32 v114, off, s32 offset:388
-; GFX11-NEXT:    scratch_load_u16 v115, off, s32
-; GFX11-NEXT:    scratch_load_u16 v116, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_u16 v117, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_u16 v118, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_u16 v119, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_u16 v128, off, s32 offset:40
-; GFX11-NEXT:    scratch_load_u16 v129, off, s32 offset:48
-; GFX11-NEXT:    scratch_load_u16 v130, off, s32 offset:56
-; GFX11-NEXT:    scratch_load_u16 v131, off, s32 offset:64
-; GFX11-NEXT:    scratch_load_u16 v144, off, s32 offset:72
-; GFX11-NEXT:    scratch_load_u16 v145, off, s32 offset:80
-; GFX11-NEXT:    scratch_load_u16 v146, off, s32 offset:88
-; GFX11-NEXT:    scratch_load_u16 v147, off, s32 offset:96
-; GFX11-NEXT:    scratch_load_u16 v148, off, s32 offset:104
-; GFX11-NEXT:    scratch_load_u16 v162, off, s32 offset:112
-; GFX11-NEXT:    scratch_load_u16 v163, off, s32 offset:120
-; GFX11-NEXT:    scratch_load_u16 v164, off, s32 offset:128
-; GFX11-NEXT:    scratch_load_u16 v165, off, s32 offset:136
-; GFX11-NEXT:    scratch_load_u16 v166, off, s32 offset:144
-; GFX11-NEXT:    scratch_load_u16 v179, off, s32 offset:152
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v180, off, s32 offset:160
-; GFX11-NEXT:    scratch_load_u16 v181, off, s32 offset:168
-; GFX11-NEXT:    scratch_load_u16 v182, off, s32 offset:176
-; GFX11-NEXT:    scratch_load_u16 v183, off, s32 offset:184
-; GFX11-NEXT:    scratch_load_u16 v136, off, s32 offset:192
-; GFX11-NEXT:    scratch_load_u16 v137, off, s32 offset:200
-; GFX11-NEXT:    scratch_load_u16 v138, off, s32 offset:208
-; GFX11-NEXT:    scratch_load_u16 v132, off, s32 offset:212
-; GFX11-NEXT:    scratch_load_u16 v133, off, s32 offset:204
-; GFX11-NEXT:    scratch_load_u16 v134, off, s32 offset:196
-; GFX11-NEXT:    scratch_load_u16 v135, off, s32 offset:188
-; GFX11-NEXT:    scratch_load_u16 v149, off, s32 offset:180
-; GFX11-NEXT:    scratch_load_u16 v150, off, s32 offset:172
-; GFX11-NEXT:    scratch_load_u16 v151, off, s32 offset:164
-; GFX11-NEXT:    scratch_load_u16 v160, off, s32 offset:156
-; GFX11-NEXT:    scratch_load_u16 v161, off, s32 offset:148
-; GFX11-NEXT:    scratch_load_u16 v167, off, s32 offset:140
-; GFX11-NEXT:    scratch_load_u16 v176, off, s32 offset:132
-; GFX11-NEXT:    scratch_load_u16 v177, off, s32 offset:124
-; GFX11-NEXT:    scratch_load_u16 v178, off, s32 offset:116
-; GFX11-NEXT:    scratch_load_u16 v40, off, s32 offset:108
-; GFX11-NEXT:    scratch_load_u16 v41, off, s32 offset:100
-; GFX11-NEXT:    scratch_load_u16 v42, off, s32 offset:92
-; GFX11-NEXT:    scratch_load_u16 v43, off, s32 offset:84
-; GFX11-NEXT:    scratch_load_u16 v44, off, s32 offset:76
-; GFX11-NEXT:    scratch_load_u16 v58, off, s32 offset:68
-; GFX11-NEXT:    scratch_load_u16 v59, off, s32 offset:60
-; GFX11-NEXT:    scratch_load_u16 v60, off, s32 offset:52
-; GFX11-NEXT:    scratch_load_u16 v74, off, s32 offset:44
-; GFX11-NEXT:    scratch_load_u16 v75, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_u16 v76, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_u16 v77, off, s32 offset:20
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_u16 v78, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_u16 v92, off, s32 offset:4
-; GFX11-NEXT:    v_lshlrev_b16 v124, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v125, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v126, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v127, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v111, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v120, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v121, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v122, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v123, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v106, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v107, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v108, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v109, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v110, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v93, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(54)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v114
-; GFX11-NEXT:    s_waitcnt vmcnt(53)
-; GFX11-NEXT:    v_lshlrev_b16 v94, 8, v115
-; GFX11-NEXT:    s_waitcnt vmcnt(52)
-; GFX11-NEXT:    v_lshlrev_b16 v95, 8, v116
-; GFX11-NEXT:    s_waitcnt vmcnt(51)
-; GFX11-NEXT:    v_lshlrev_b16 v104, 8, v117
-; GFX11-NEXT:    s_waitcnt vmcnt(50)
-; GFX11-NEXT:    v_lshlrev_b16 v105, 8, v118
-; GFX11-NEXT:    s_waitcnt vmcnt(49)
-; GFX11-NEXT:    v_lshlrev_b16 v79, 8, v119
-; GFX11-NEXT:    s_waitcnt vmcnt(48)
-; GFX11-NEXT:    v_lshlrev_b16 v88, 8, v128
-; GFX11-NEXT:    s_waitcnt vmcnt(47)
-; GFX11-NEXT:    v_lshlrev_b16 v89, 8, v129
-; GFX11-NEXT:    s_waitcnt vmcnt(46)
-; GFX11-NEXT:    v_lshlrev_b16 v90, 8, v130
-; GFX11-NEXT:    s_waitcnt vmcnt(45)
-; GFX11-NEXT:    v_lshlrev_b16 v91, 8, v131
-; GFX11-NEXT:    s_waitcnt vmcnt(44)
-; GFX11-NEXT:    v_lshlrev_b16 v61, 8, v144
-; GFX11-NEXT:    s_waitcnt vmcnt(43)
-; GFX11-NEXT:    v_lshlrev_b16 v62, 8, v145
-; GFX11-NEXT:    s_waitcnt vmcnt(42)
-; GFX11-NEXT:    v_lshlrev_b16 v63, 8, v146
-; GFX11-NEXT:    s_waitcnt vmcnt(41)
-; GFX11-NEXT:    v_lshlrev_b16 v72, 8, v147
-; GFX11-NEXT:    s_waitcnt vmcnt(40)
-; GFX11-NEXT:    v_lshlrev_b16 v73, 8, v148
-; GFX11-NEXT:    s_waitcnt vmcnt(39)
-; GFX11-NEXT:    v_lshlrev_b16 v45, 8, v162
-; GFX11-NEXT:    s_waitcnt vmcnt(38)
-; GFX11-NEXT:    v_lshlrev_b16 v46, 8, v163
-; GFX11-NEXT:    s_waitcnt vmcnt(37)
-; GFX11-NEXT:    v_lshlrev_b16 v47, 8, v164
-; GFX11-NEXT:    s_waitcnt vmcnt(36)
-; GFX11-NEXT:    v_lshlrev_b16 v56, 8, v165
-; GFX11-NEXT:    s_waitcnt vmcnt(35)
-; GFX11-NEXT:    v_lshlrev_b16 v57, 8, v166
-; GFX11-NEXT:    s_waitcnt vmcnt(34)
-; GFX11-NEXT:    v_lshlrev_b16 v179, 8, v179
-; GFX11-NEXT:    s_waitcnt vmcnt(33)
-; GFX11-NEXT:    v_lshlrev_b16 v180, 8, v180
-; GFX11-NEXT:    s_waitcnt vmcnt(32)
-; GFX11-NEXT:    v_lshlrev_b16 v181, 8, v181
-; GFX11-NEXT:    s_waitcnt vmcnt(31)
-; GFX11-NEXT:    v_lshlrev_b16 v182, 8, v182
-; GFX11-NEXT:    s_waitcnt vmcnt(30)
-; GFX11-NEXT:    v_lshlrev_b16 v183, 8, v183
-; GFX11-NEXT:    s_waitcnt vmcnt(29)
-; GFX11-NEXT:    v_lshlrev_b16 v162, 8, v136
-; GFX11-NEXT:    s_waitcnt vmcnt(28)
-; GFX11-NEXT:    v_lshlrev_b16 v163, 8, v137
-; GFX11-NEXT:    s_waitcnt vmcnt(27)
-; GFX11-NEXT:    v_lshlrev_b16 v164, 8, v138
-; GFX11-NEXT:    v_lshlrev_b16 v165, 8, v103
-; GFX11-NEXT:    v_lshlrev_b16 v166, 8, v102
-; GFX11-NEXT:    v_lshlrev_b16 v144, 8, v101
-; GFX11-NEXT:    v_lshlrev_b16 v145, 8, v100
-; GFX11-NEXT:    v_lshlrev_b16 v146, 8, v99
-; GFX11-NEXT:    v_lshlrev_b16 v147, 8, v31
-; GFX11-NEXT:    v_lshlrev_b16 v148, 8, v30
-; GFX11-NEXT:    v_lshlrev_b16 v119, 8, v28
-; GFX11-NEXT:    v_lshlrev_b16 v128, 8, v26
-; GFX11-NEXT:    v_lshlrev_b16 v129, 8, v24
-; GFX11-NEXT:    v_lshlrev_b16 v130, 8, v22
-; GFX11-NEXT:    v_lshlrev_b16 v131, 8, v20
-; GFX11-NEXT:    v_lshlrev_b16 v114, 8, v18
-; GFX11-NEXT:    v_lshlrev_b16 v115, 8, v16
-; GFX11-NEXT:    v_lshlrev_b16 v116, 8, v14
-; GFX11-NEXT:    v_lshlrev_b16 v117, 8, v12
-; GFX11-NEXT:    v_lshlrev_b16 v118, 8, v10
-; GFX11-NEXT:    v_lshlrev_b16 v99, 8, v8
-; GFX11-NEXT:    v_lshlrev_b16 v100, 8, v6
-; GFX11-NEXT:    v_lshlrev_b16 v101, 8, v4
-; GFX11-NEXT:    v_lshlrev_b16 v102, 8, v2
-; GFX11-NEXT:    v_lshlrev_b16 v103, 8, v0
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB19_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v55
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v54
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v53
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v52
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v51
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v124
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v125
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v126
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v127
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v50
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v39
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v37
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v36
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v49
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v48
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v35
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v34
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v111
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v121
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v120
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v122
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v123
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v107
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v2
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v38
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v108
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v109
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v110
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v106
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v3, v7, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v6, v12
-; GFX11-NEXT:    v_or_b32_e32 v5, v8, v9
-; GFX11-NEXT:    v_or_b32_e32 v6, v10, v11
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v32
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v92
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v78
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v77
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v76
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v75
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v74
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v60
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v59
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v93
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v94
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v95
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v104
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v105
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v79
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v88
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v89
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v90
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v91
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v8, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v9, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v10, v13, v14
-; GFX11-NEXT:    v_or_b32_e32 v11, v15, v16
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v58
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v44
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v43
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v42
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v41
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v40
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v178
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v177
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v176
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v167
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v61
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v62
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v63
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v72
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v73
-; GFX11-NEXT:    v_or_b32_e32 v17, v17, v45
-; GFX11-NEXT:    v_or_b32_e32 v18, v18, v46
-; GFX11-NEXT:    v_or_b32_e32 v19, v19, v47
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v56
-; GFX11-NEXT:    v_or_b32_e32 v21, v21, v57
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xffff, v18
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xffff, v20
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v13, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v14, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v15, v18, v19
-; GFX11-NEXT:    v_or_b32_e32 v16, v20, v21
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v161
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v160
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v151
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v150
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v149
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v135
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v134
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v133
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v132
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v113
-; GFX11-NEXT:    v_or_b32_e32 v17, v17, v179
-; GFX11-NEXT:    v_or_b32_e32 v18, v18, v180
-; GFX11-NEXT:    v_or_b32_e32 v19, v19, v181
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v182
-; GFX11-NEXT:    v_or_b32_e32 v21, v21, v183
-; GFX11-NEXT:    v_or_b32_e32 v22, v22, v162
-; GFX11-NEXT:    v_or_b32_e32 v23, v23, v163
-; GFX11-NEXT:    v_or_b32_e32 v24, v24, v164
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v165
-; GFX11-NEXT:    v_or_b32_e32 v26, v26, v166
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff, v19
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xffff, v21
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xffff, v23
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xffff, v25
-; GFX11-NEXT:    v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-NEXT:    v_or_b32_e32 v17, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v18, v19, v20
-; GFX11-NEXT:    v_or_b32_e32 v19, v21, v22
-; GFX11-NEXT:    v_or_b32_e32 v20, v23, v24
-; GFX11-NEXT:    v_or_b32_e32 v21, v25, v26
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v112
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v98
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v97
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v96
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v87
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v86
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v85
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v84
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v83
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v82
-; GFX11-NEXT:    v_or_b32_e32 v22, v22, v144
-; GFX11-NEXT:    v_or_b32_e32 v23, v23, v145
-; GFX11-NEXT:    v_or_b32_e32 v24, v24, v146
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v147
-; GFX11-NEXT:    v_or_b32_e32 v26, v26, v148
-; GFX11-NEXT:    v_or_b32_e32 v27, v27, v119
-; GFX11-NEXT:    v_or_b32_e32 v28, v28, v128
-; GFX11-NEXT:    v_or_b32_e32 v29, v29, v129
-; GFX11-NEXT:    v_or_b32_e32 v30, v30, v130
-; GFX11-NEXT:    v_or_b32_e32 v31, v31, v131
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xffff, v22
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xffff, v24
-; GFX11-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xffff, v26
-; GFX11-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xffff, v28
-; GFX11-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xffff, v30
-; GFX11-NEXT:    v_lshlrev_b32_e32 v31, 16, v31
-; GFX11-NEXT:    v_or_b32_e32 v22, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v23, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v24, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v25, v28, v29
-; GFX11-NEXT:    v_or_b32_e32 v26, v30, v31
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v81
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v80
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v71
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v70
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v69
-; GFX11-NEXT:    v_and_b32_e32 v32, 0xff, v68
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xff, v67
-; GFX11-NEXT:    v_and_b32_e32 v34, 0xff, v66
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xff, v65
-; GFX11-NEXT:    v_and_b32_e32 v36, 0xff, v64
-; GFX11-NEXT:    v_or_b32_e32 v27, v27, v114
-; GFX11-NEXT:    v_or_b32_e32 v28, v28, v115
-; GFX11-NEXT:    v_or_b32_e32 v29, v29, v116
-; GFX11-NEXT:    v_or_b32_e32 v30, v30, v117
-; GFX11-NEXT:    v_or_b32_e32 v31, v31, v118
-; GFX11-NEXT:    v_or_b32_e32 v32, v32, v99
-; GFX11-NEXT:    v_or_b32_e32 v33, v33, v100
-; GFX11-NEXT:    v_or_b32_e32 v34, v34, v101
-; GFX11-NEXT:    v_or_b32_e32 v35, v35, v102
-; GFX11-NEXT:    v_or_b32_e32 v36, v36, v103
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xffff, v27
-; GFX11-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xffff, v29
-; GFX11-NEXT:    v_lshlrev_b32_e32 v30, 16, v30
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xffff, v31
-; GFX11-NEXT:    v_lshlrev_b32_e32 v32, 16, v32
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xffff, v33
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v34
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xffff, v35
-; GFX11-NEXT:    v_lshlrev_b32_e32 v36, 16, v36
-; GFX11-NEXT:    v_or_b32_e32 v27, v27, v28
-; GFX11-NEXT:    v_or_b32_e32 v28, v29, v30
-; GFX11-NEXT:    v_or_b32_e32 v29, v31, v32
-; GFX11-NEXT:    v_or_b32_e32 v30, v33, v34
-; GFX11-NEXT:    v_or_b32_e32 v31, v35, v36
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr92
-; GFX11-NEXT:    ; implicit-def: $vgpr78
-; GFX11-NEXT:    ; implicit-def: $vgpr77
-; GFX11-NEXT:    ; implicit-def: $vgpr76
-; GFX11-NEXT:    ; implicit-def: $vgpr75
-; GFX11-NEXT:    ; implicit-def: $vgpr74
-; GFX11-NEXT:    ; implicit-def: $vgpr60
-; GFX11-NEXT:    ; implicit-def: $vgpr59
-; GFX11-NEXT:    ; implicit-def: $vgpr58
-; GFX11-NEXT:    ; implicit-def: $vgpr44
-; GFX11-NEXT:    ; implicit-def: $vgpr43
-; GFX11-NEXT:    ; implicit-def: $vgpr42
-; GFX11-NEXT:    ; implicit-def: $vgpr41
-; GFX11-NEXT:    ; implicit-def: $vgpr40
-; GFX11-NEXT:    ; implicit-def: $vgpr178
-; GFX11-NEXT:    ; implicit-def: $vgpr177
-; GFX11-NEXT:    ; implicit-def: $vgpr176
-; GFX11-NEXT:    ; implicit-def: $vgpr167
-; GFX11-NEXT:    ; implicit-def: $vgpr161
-; GFX11-NEXT:    ; implicit-def: $vgpr160
-; GFX11-NEXT:    ; implicit-def: $vgpr151
-; GFX11-NEXT:    ; implicit-def: $vgpr150
-; GFX11-NEXT:    ; implicit-def: $vgpr149
-; GFX11-NEXT:    ; implicit-def: $vgpr135
-; GFX11-NEXT:    ; implicit-def: $vgpr134
-; GFX11-NEXT:    ; implicit-def: $vgpr133
-; GFX11-NEXT:    ; implicit-def: $vgpr132
-; GFX11-NEXT:    ; implicit-def: $vgpr113
-; GFX11-NEXT:    ; implicit-def: $vgpr112
-; GFX11-NEXT:    ; implicit-def: $vgpr98
-; GFX11-NEXT:    ; implicit-def: $vgpr97
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr67
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr124
-; GFX11-NEXT:    ; implicit-def: $vgpr125
-; GFX11-NEXT:    ; implicit-def: $vgpr126
-; GFX11-NEXT:    ; implicit-def: $vgpr127
-; GFX11-NEXT:    ; implicit-def: $vgpr111
-; GFX11-NEXT:    ; implicit-def: $vgpr120
-; GFX11-NEXT:    ; implicit-def: $vgpr121
-; GFX11-NEXT:    ; implicit-def: $vgpr122
-; GFX11-NEXT:    ; implicit-def: $vgpr123
-; GFX11-NEXT:    ; implicit-def: $vgpr106
-; GFX11-NEXT:    ; implicit-def: $vgpr107
-; GFX11-NEXT:    ; implicit-def: $vgpr108
-; GFX11-NEXT:    ; implicit-def: $vgpr109
-; GFX11-NEXT:    ; implicit-def: $vgpr110
-; GFX11-NEXT:    ; implicit-def: $vgpr93
-; GFX11-NEXT:    ; implicit-def: $vgpr94
-; GFX11-NEXT:    ; implicit-def: $vgpr95
-; GFX11-NEXT:    ; implicit-def: $vgpr104
-; GFX11-NEXT:    ; implicit-def: $vgpr105
-; GFX11-NEXT:    ; implicit-def: $vgpr79
-; GFX11-NEXT:    ; implicit-def: $vgpr88
-; GFX11-NEXT:    ; implicit-def: $vgpr89
-; GFX11-NEXT:    ; implicit-def: $vgpr90
-; GFX11-NEXT:    ; implicit-def: $vgpr91
-; GFX11-NEXT:    ; implicit-def: $vgpr61
-; GFX11-NEXT:    ; implicit-def: $vgpr62
-; GFX11-NEXT:    ; implicit-def: $vgpr63
-; GFX11-NEXT:    ; implicit-def: $vgpr72
-; GFX11-NEXT:    ; implicit-def: $vgpr73
-; GFX11-NEXT:    ; implicit-def: $vgpr45
-; GFX11-NEXT:    ; implicit-def: $vgpr46
-; GFX11-NEXT:    ; implicit-def: $vgpr47
-; GFX11-NEXT:    ; implicit-def: $vgpr56
-; GFX11-NEXT:    ; implicit-def: $vgpr57
-; GFX11-NEXT:    ; implicit-def: $vgpr179
-; GFX11-NEXT:    ; implicit-def: $vgpr180
-; GFX11-NEXT:    ; implicit-def: $vgpr181
-; GFX11-NEXT:    ; implicit-def: $vgpr182
-; GFX11-NEXT:    ; implicit-def: $vgpr183
-; GFX11-NEXT:    ; implicit-def: $vgpr162
-; GFX11-NEXT:    ; implicit-def: $vgpr163
-; GFX11-NEXT:    ; implicit-def: $vgpr164
-; GFX11-NEXT:    ; implicit-def: $vgpr165
-; GFX11-NEXT:    ; implicit-def: $vgpr166
-; GFX11-NEXT:    ; implicit-def: $vgpr144
-; GFX11-NEXT:    ; implicit-def: $vgpr145
-; GFX11-NEXT:    ; implicit-def: $vgpr146
-; GFX11-NEXT:    ; implicit-def: $vgpr147
-; GFX11-NEXT:    ; implicit-def: $vgpr148
-; GFX11-NEXT:    ; implicit-def: $vgpr119
-; GFX11-NEXT:    ; implicit-def: $vgpr128
-; GFX11-NEXT:    ; implicit-def: $vgpr129
-; GFX11-NEXT:    ; implicit-def: $vgpr130
-; GFX11-NEXT:    ; implicit-def: $vgpr131
-; GFX11-NEXT:    ; implicit-def: $vgpr114
-; GFX11-NEXT:    ; implicit-def: $vgpr115
-; GFX11-NEXT:    ; implicit-def: $vgpr116
-; GFX11-NEXT:    ; implicit-def: $vgpr117
-; GFX11-NEXT:    ; implicit-def: $vgpr118
-; GFX11-NEXT:    ; implicit-def: $vgpr99
-; GFX11-NEXT:    ; implicit-def: $vgpr100
-; GFX11-NEXT:    ; implicit-def: $vgpr101
-; GFX11-NEXT:    ; implicit-def: $vgpr102
-; GFX11-NEXT:    ; implicit-def: $vgpr103
-; GFX11-NEXT:  .LBB19_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB19_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v55, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v54, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v53, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v52, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v51, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_add_nc_u16 v5, v50, 3
-; GFX11-NEXT:    v_or_b32_e32 v0, v124, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v125, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v126, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v127, v3
-; GFX11-NEXT:    v_add_nc_u16 v6, v49, 3
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v7, v48, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_add_nc_u16 v8, v37, 3
-; GFX11-NEXT:    v_add_nc_u16 v9, v36, 3
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_add_nc_u16 v10, v35, 3
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_add_nc_u16 v2, v39, 3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v5
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v11, v34, 3
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v2, v123, v2
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_or_b32_e32 v3, v111, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v120, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v121, v5
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v6, v122, v6
-; GFX11-NEXT:    v_or_b32_e32 v8, v107, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v108, v9
-; GFX11-NEXT:    v_or_b32_e32 v10, v109, v10
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v38, 3
-; GFX11-NEXT:    v_or_b32_e32 v11, v110, v11
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v10
-; GFX11-NEXT:    v_or_b32_e32 v2, v106, v2
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v11
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_or_b32_e32 v2, v3, v4
-; GFX11-NEXT:    v_or_b32_e32 v3, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v5, v8, v9
-; GFX11-NEXT:    v_or_b32_e32 v4, v7, v12
-; GFX11-NEXT:    v_or_b32_e32 v6, v10, v11
-; GFX11-NEXT:    v_add_nc_u16 v7, v33, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v32, 3
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_nc_u16 v9, v92, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, v78, 3
-; GFX11-NEXT:    v_add_nc_u16 v11, v77, 3
-; GFX11-NEXT:    v_add_nc_u16 v12, v76, 3
-; GFX11-NEXT:    v_add_nc_u16 v13, v75, 3
-; GFX11-NEXT:    v_add_nc_u16 v14, v74, 3
-; GFX11-NEXT:    v_add_nc_u16 v15, v60, 3
-; GFX11-NEXT:    v_add_nc_u16 v16, v59, 3
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_or_b32_e32 v7, v93, v7
-; GFX11-NEXT:    v_or_b32_e32 v8, v94, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v95, v9
-; GFX11-NEXT:    v_or_b32_e32 v10, v104, v10
-; GFX11-NEXT:    v_or_b32_e32 v11, v105, v11
-; GFX11-NEXT:    v_or_b32_e32 v12, v79, v12
-; GFX11-NEXT:    v_or_b32_e32 v13, v88, v13
-; GFX11-NEXT:    v_or_b32_e32 v14, v89, v14
-; GFX11-NEXT:    v_or_b32_e32 v15, v90, v15
-; GFX11-NEXT:    v_or_b32_e32 v16, v91, v16
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v10
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v11
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v12
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v13
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v14
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v15
-; GFX11-NEXT:    v_add_nc_u16 v16, 0x300, v16
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v8, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v9, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v10, v13, v14
-; GFX11-NEXT:    v_or_b32_e32 v11, v15, v16
-; GFX11-NEXT:    v_add_nc_u16 v12, v58, 3
-; GFX11-NEXT:    v_add_nc_u16 v13, v44, 3
-; GFX11-NEXT:    v_add_nc_u16 v14, v43, 3
-; GFX11-NEXT:    v_add_nc_u16 v15, v42, 3
-; GFX11-NEXT:    v_add_nc_u16 v16, v41, 3
-; GFX11-NEXT:    v_add_nc_u16 v17, v40, 3
-; GFX11-NEXT:    v_add_nc_u16 v18, v178, 3
-; GFX11-NEXT:    v_add_nc_u16 v19, v177, 3
-; GFX11-NEXT:    v_add_nc_u16 v20, v176, 3
-; GFX11-NEXT:    v_add_nc_u16 v21, v167, 3
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v17
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v19
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v21
-; GFX11-NEXT:    v_or_b32_e32 v12, v61, v12
-; GFX11-NEXT:    v_or_b32_e32 v13, v62, v13
-; GFX11-NEXT:    v_or_b32_e32 v14, v63, v14
-; GFX11-NEXT:    v_or_b32_e32 v15, v72, v15
-; GFX11-NEXT:    v_or_b32_e32 v16, v73, v16
-; GFX11-NEXT:    v_or_b32_e32 v17, v45, v17
-; GFX11-NEXT:    v_or_b32_e32 v18, v46, v18
-; GFX11-NEXT:    v_or_b32_e32 v19, v47, v19
-; GFX11-NEXT:    v_or_b32_e32 v20, v56, v20
-; GFX11-NEXT:    v_or_b32_e32 v21, v57, v21
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v12
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v13
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v14
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v15
-; GFX11-NEXT:    v_add_nc_u16 v16, 0x300, v16
-; GFX11-NEXT:    v_add_nc_u16 v17, 0x300, v17
-; GFX11-NEXT:    v_add_nc_u16 v18, 0x300, v18
-; GFX11-NEXT:    v_add_nc_u16 v19, 0x300, v19
-; GFX11-NEXT:    v_add_nc_u16 v20, 0x300, v20
-; GFX11-NEXT:    v_add_nc_u16 v21, 0x300, v21
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xffff, v18
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xffff, v20
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v13, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v14, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v15, v18, v19
-; GFX11-NEXT:    v_or_b32_e32 v16, v20, v21
-; GFX11-NEXT:    v_add_nc_u16 v17, v161, 3
-; GFX11-NEXT:    v_add_nc_u16 v18, v160, 3
-; GFX11-NEXT:    v_add_nc_u16 v19, v151, 3
-; GFX11-NEXT:    v_add_nc_u16 v20, v150, 3
-; GFX11-NEXT:    v_add_nc_u16 v21, v149, 3
-; GFX11-NEXT:    v_add_nc_u16 v22, v135, 3
-; GFX11-NEXT:    v_add_nc_u16 v23, v134, 3
-; GFX11-NEXT:    v_add_nc_u16 v24, v133, 3
-; GFX11-NEXT:    v_add_nc_u16 v25, v132, 3
-; GFX11-NEXT:    v_add_nc_u16 v26, v113, 3
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v17
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v19
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v21
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v23
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v24
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v25
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v26
-; GFX11-NEXT:    v_or_b32_e32 v17, v179, v17
-; GFX11-NEXT:    v_or_b32_e32 v18, v180, v18
-; GFX11-NEXT:    v_or_b32_e32 v19, v181, v19
-; GFX11-NEXT:    v_or_b32_e32 v20, v182, v20
-; GFX11-NEXT:    v_or_b32_e32 v21, v183, v21
-; GFX11-NEXT:    v_or_b32_e32 v22, v162, v22
-; GFX11-NEXT:    v_or_b32_e32 v23, v163, v23
-; GFX11-NEXT:    v_or_b32_e32 v24, v164, v24
-; GFX11-NEXT:    v_or_b32_e32 v25, v165, v25
-; GFX11-NEXT:    v_or_b32_e32 v26, v166, v26
-; GFX11-NEXT:    v_add_nc_u16 v17, 0x300, v17
-; GFX11-NEXT:    v_add_nc_u16 v18, 0x300, v18
-; GFX11-NEXT:    v_add_nc_u16 v19, 0x300, v19
-; GFX11-NEXT:    v_add_nc_u16 v20, 0x300, v20
-; GFX11-NEXT:    v_add_nc_u16 v21, 0x300, v21
-; GFX11-NEXT:    v_add_nc_u16 v22, 0x300, v22
-; GFX11-NEXT:    v_add_nc_u16 v23, 0x300, v23
-; GFX11-NEXT:    v_add_nc_u16 v24, 0x300, v24
-; GFX11-NEXT:    v_add_nc_u16 v25, 0x300, v25
-; GFX11-NEXT:    v_add_nc_u16 v26, 0x300, v26
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff, v19
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xffff, v21
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xffff, v23
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xffff, v25
-; GFX11-NEXT:    v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-NEXT:    v_or_b32_e32 v17, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v18, v19, v20
-; GFX11-NEXT:    v_or_b32_e32 v19, v21, v22
-; GFX11-NEXT:    v_or_b32_e32 v20, v23, v24
-; GFX11-NEXT:    v_or_b32_e32 v21, v25, v26
-; GFX11-NEXT:    v_add_nc_u16 v22, v112, 3
-; GFX11-NEXT:    v_add_nc_u16 v23, v98, 3
-; GFX11-NEXT:    v_add_nc_u16 v24, v97, 3
-; GFX11-NEXT:    v_add_nc_u16 v25, v96, 3
-; GFX11-NEXT:    v_add_nc_u16 v26, v87, 3
-; GFX11-NEXT:    v_add_nc_u16 v27, v86, 3
-; GFX11-NEXT:    v_add_nc_u16 v28, v85, 3
-; GFX11-NEXT:    v_add_nc_u16 v29, v84, 3
-; GFX11-NEXT:    v_add_nc_u16 v30, v83, 3
-; GFX11-NEXT:    v_add_nc_u16 v31, v82, 3
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v23
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v24
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v25
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v26
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v27
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v29
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v30
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v31
-; GFX11-NEXT:    v_or_b32_e32 v22, v144, v22
-; GFX11-NEXT:    v_or_b32_e32 v23, v145, v23
-; GFX11-NEXT:    v_or_b32_e32 v24, v146, v24
-; GFX11-NEXT:    v_or_b32_e32 v25, v147, v25
-; GFX11-NEXT:    v_or_b32_e32 v26, v148, v26
-; GFX11-NEXT:    v_or_b32_e32 v27, v119, v27
-; GFX11-NEXT:    v_or_b32_e32 v28, v128, v28
-; GFX11-NEXT:    v_or_b32_e32 v29, v129, v29
-; GFX11-NEXT:    v_or_b32_e32 v30, v130, v30
-; GFX11-NEXT:    v_or_b32_e32 v31, v131, v31
-; GFX11-NEXT:    v_add_nc_u16 v22, 0x300, v22
-; GFX11-NEXT:    v_add_nc_u16 v23, 0x300, v23
-; GFX11-NEXT:    v_add_nc_u16 v24, 0x300, v24
-; GFX11-NEXT:    v_add_nc_u16 v25, 0x300, v25
-; GFX11-NEXT:    v_add_nc_u16 v26, 0x300, v26
-; GFX11-NEXT:    v_add_nc_u16 v27, 0x300, v27
-; GFX11-NEXT:    v_add_nc_u16 v28, 0x300, v28
-; GFX11-NEXT:    v_add_nc_u16 v29, 0x300, v29
-; GFX11-NEXT:    v_add_nc_u16 v30, 0x300, v30
-; GFX11-NEXT:    v_add_nc_u16 v31, 0x300, v31
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xffff, v22
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xffff, v24
-; GFX11-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xffff, v26
-; GFX11-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xffff, v28
-; GFX11-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xffff, v30
-; GFX11-NEXT:    v_lshlrev_b32_e32 v31, 16, v31
-; GFX11-NEXT:    v_or_b32_e32 v22, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v23, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v24, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v25, v28, v29
-; GFX11-NEXT:    v_or_b32_e32 v26, v30, v31
-; GFX11-NEXT:    v_add_nc_u16 v27, v81, 3
-; GFX11-NEXT:    v_add_nc_u16 v28, v80, 3
-; GFX11-NEXT:    v_add_nc_u16 v29, v71, 3
-; GFX11-NEXT:    v_add_nc_u16 v30, v70, 3
-; GFX11-NEXT:    v_add_nc_u16 v31, v69, 3
-; GFX11-NEXT:    v_add_nc_u16 v32, v68, 3
-; GFX11-NEXT:    v_add_nc_u16 v33, v67, 3
-; GFX11-NEXT:    v_add_nc_u16 v34, v66, 3
-; GFX11-NEXT:    v_add_nc_u16 v35, v65, 3
-; GFX11-NEXT:    v_add_nc_u16 v36, v64, 3
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v27
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v29
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v30
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v31
-; GFX11-NEXT:    v_and_b32_e32 v32, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v34, 0xff, v34
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xff, v35
-; GFX11-NEXT:    v_and_b32_e32 v36, 0xff, v36
-; GFX11-NEXT:    v_or_b32_e32 v27, v114, v27
-; GFX11-NEXT:    v_or_b32_e32 v28, v115, v28
-; GFX11-NEXT:    v_or_b32_e32 v29, v116, v29
-; GFX11-NEXT:    v_or_b32_e32 v30, v117, v30
-; GFX11-NEXT:    v_or_b32_e32 v31, v118, v31
-; GFX11-NEXT:    v_or_b32_e32 v32, v99, v32
-; GFX11-NEXT:    v_or_b32_e32 v33, v100, v33
-; GFX11-NEXT:    v_or_b32_e32 v34, v101, v34
-; GFX11-NEXT:    v_or_b32_e32 v35, v102, v35
-; GFX11-NEXT:    v_or_b32_e32 v36, v103, v36
-; GFX11-NEXT:    v_add_nc_u16 v27, 0x300, v27
-; GFX11-NEXT:    v_add_nc_u16 v28, 0x300, v28
-; GFX11-NEXT:    v_add_nc_u16 v29, 0x300, v29
-; GFX11-NEXT:    v_add_nc_u16 v30, 0x300, v30
-; GFX11-NEXT:    v_add_nc_u16 v31, 0x300, v31
-; GFX11-NEXT:    v_add_nc_u16 v32, 0x300, v32
-; GFX11-NEXT:    v_add_nc_u16 v33, 0x300, v33
-; GFX11-NEXT:    v_add_nc_u16 v34, 0x300, v34
-; GFX11-NEXT:    v_add_nc_u16 v35, 0x300, v35
-; GFX11-NEXT:    v_add_nc_u16 v36, 0x300, v36
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xffff, v27
-; GFX11-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xffff, v29
-; GFX11-NEXT:    v_lshlrev_b32_e32 v30, 16, v30
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xffff, v31
-; GFX11-NEXT:    v_lshlrev_b32_e32 v32, 16, v32
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xffff, v33
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v34
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xffff, v35
-; GFX11-NEXT:    v_lshlrev_b32_e32 v36, 16, v36
-; GFX11-NEXT:    v_or_b32_e32 v27, v27, v28
-; GFX11-NEXT:    v_or_b32_e32 v28, v29, v30
-; GFX11-NEXT:    v_or_b32_e32 v29, v31, v32
-; GFX11-NEXT:    v_or_b32_e32 v30, v33, v34
-; GFX11-NEXT:    v_or_b32_e32 v31, v35, v36
-; GFX11-NEXT:  .LBB19_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_b32 v138, off, s32 offset:392
-; GFX11-NEXT:    scratch_load_b32 v137, off, s32 offset:396
-; GFX11-NEXT:    scratch_load_b32 v136, off, s32 offset:400
-; GFX11-NEXT:    scratch_load_b32 v127, off, s32 offset:404
-; GFX11-NEXT:    scratch_load_b32 v126, off, s32 offset:408
-; GFX11-NEXT:    scratch_load_b32 v125, off, s32 offset:412
-; GFX11-NEXT:    scratch_load_b32 v124, off, s32 offset:416
-; GFX11-NEXT:    scratch_load_b32 v123, off, s32 offset:420
-; GFX11-NEXT:    scratch_load_b32 v122, off, s32 offset:424
-; GFX11-NEXT:    scratch_load_b32 v121, off, s32 offset:428
-; GFX11-NEXT:    scratch_load_b32 v120, off, s32 offset:432
-; GFX11-NEXT:    scratch_load_b32 v111, off, s32 offset:436
-; GFX11-NEXT:    scratch_load_b32 v110, off, s32 offset:440
-; GFX11-NEXT:    scratch_load_b32 v109, off, s32 offset:444
-; GFX11-NEXT:    scratch_load_b32 v108, off, s32 offset:448
-; GFX11-NEXT:    scratch_load_b32 v107, off, s32 offset:452
-; GFX11-NEXT:    scratch_load_b32 v106, off, s32 offset:456
-; GFX11-NEXT:    scratch_load_b32 v105, off, s32 offset:460
-; GFX11-NEXT:    scratch_load_b32 v104, off, s32 offset:464
-; GFX11-NEXT:    scratch_load_b32 v95, off, s32 offset:468
-; GFX11-NEXT:    scratch_load_b32 v94, off, s32 offset:472
-; GFX11-NEXT:    scratch_load_b32 v93, off, s32 offset:476
-; GFX11-NEXT:    scratch_load_b32 v92, off, s32 offset:480
-; GFX11-NEXT:    scratch_load_b32 v91, off, s32 offset:484
-; GFX11-NEXT:    scratch_load_b32 v90, off, s32 offset:488
-; GFX11-NEXT:    scratch_load_b32 v89, off, s32 offset:492
-; GFX11-NEXT:    scratch_load_b32 v88, off, s32 offset:496
-; GFX11-NEXT:    scratch_load_b32 v79, off, s32 offset:500
-; GFX11-NEXT:    scratch_load_b32 v78, off, s32 offset:504
-; GFX11-NEXT:    scratch_load_b32 v77, off, s32 offset:508
-; GFX11-NEXT:    scratch_load_b32 v76, off, s32 offset:512
-; GFX11-NEXT:    scratch_load_b32 v75, off, s32 offset:516
-; GFX11-NEXT:    s_clause 0x12
-; GFX11-NEXT:    scratch_load_b32 v74, off, s32 offset:520
-; GFX11-NEXT:    scratch_load_b32 v73, off, s32 offset:524
-; GFX11-NEXT:    scratch_load_b32 v72, off, s32 offset:528
-; GFX11-NEXT:    scratch_load_b32 v63, off, s32 offset:532
-; GFX11-NEXT:    scratch_load_b32 v62, off, s32 offset:536
-; GFX11-NEXT:    scratch_load_b32 v61, off, s32 offset:540
-; GFX11-NEXT:    scratch_load_b32 v60, off, s32 offset:544
-; GFX11-NEXT:    scratch_load_b32 v59, off, s32 offset:548
-; GFX11-NEXT:    scratch_load_b32 v58, off, s32 offset:552
-; GFX11-NEXT:    scratch_load_b32 v57, off, s32 offset:556
-; GFX11-NEXT:    scratch_load_b32 v56, off, s32 offset:560
-; GFX11-NEXT:    scratch_load_b32 v47, off, s32 offset:564
-; GFX11-NEXT:    scratch_load_b32 v46, off, s32 offset:568
-; GFX11-NEXT:    scratch_load_b32 v45, off, s32 offset:572
-; GFX11-NEXT:    scratch_load_b32 v44, off, s32 offset:576
-; GFX11-NEXT:    scratch_load_b32 v43, off, s32 offset:580
-; GFX11-NEXT:    scratch_load_b32 v42, off, s32 offset:584
-; GFX11-NEXT:    scratch_load_b32 v41, off, s32 offset:588
-; GFX11-NEXT:    scratch_load_b32 v40, off, s32 offset:592
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v128i8_to_v32f32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32 offset:384
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v32, off, s32 offset:380
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v31, off, s32 offset:376
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v32, off, s32 offset:372
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v50, off, s32 offset:368
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v33, off, s32 offset:364
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v50, off, s32 offset:360
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v33, off, s32 offset:356
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v49, off, s32 offset:352
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v34, off, s32 offset:348
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v51, off, s32 offset:344
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v34, off, s32 offset:340
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v51, off, s32 offset:336
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v35, off, s32 offset:332
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v54, off, s32 offset:328
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v35, off, s32 offset:324
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v53, off, s32 offset:320
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v36, off, s32 offset:316
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v53, off, s32 offset:312
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v36, off, s32 offset:308
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v54, off, s32 offset:304
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v37, off, s32 offset:300
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v55, off, s32 offset:296
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v37, off, s32 offset:292
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v64, off, s32 offset:288
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v38, off, s32 offset:284
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v64, off, s32 offset:280
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v38, off, s32 offset:276
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v55, off, s32 offset:272
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v39, off, s32 offset:268
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v65, off, s32 offset:264
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v39, off, s32 offset:260
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v65, off, s32 offset:256
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v48, off, s32 offset:252
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v69, off, s32 offset:248
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v48, off, s32 offset:244
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v68, off, s32 offset:240
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v49, off, s32 offset:236
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v68, off, s32 offset:232
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v52, off, s32 offset:228
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v69, off, s32 offset:224
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v52, off, s32 offset:220
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v70, off, s32 offset:216
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v103, off, s32 offset:388
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v81, off, s32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v81, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v82, off, s32 offset:16
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v82, off, s32 offset:24
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v83, off, s32 offset:32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v86, off, s32 offset:40
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v86, off, s32 offset:48
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v87, off, s32 offset:56
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v87, off, s32 offset:64
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v96, off, s32 offset:72
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v99, off, s32 offset:80
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v99, off, s32 offset:88
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v100, off, s32 offset:96
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v100, off, s32 offset:104
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v101, off, s32 offset:112
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v160, off, s32 offset:120
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v160, off, s32 offset:128
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v161, off, s32 offset:136
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v161, off, s32 offset:144
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v162, off, s32 offset:152
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v162, off, s32 offset:160
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v163, off, s32 offset:168
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v163, off, s32 offset:176
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v164, off, s32 offset:184
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v164, off, s32 offset:192
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v165, off, s32 offset:200
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v165, off, s32 offset:208
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v66, off, s32 offset:212
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v66, off, s32 offset:204
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v67, off, s32 offset:196
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v67, off, s32 offset:188
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v70, off, s32 offset:180
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v71, off, s32 offset:172
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v71, off, s32 offset:164
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v80, off, s32 offset:156
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v80, off, s32 offset:148
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v83, off, s32 offset:140
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v84, off, s32 offset:132
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v84, off, s32 offset:124
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v85, off, s32 offset:116
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v85, off, s32 offset:108
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v96, off, s32 offset:100
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v97, off, s32 offset:92
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v97, off, s32 offset:84
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v98, off, s32 offset:76
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v98, off, s32 offset:68
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v101, off, s32 offset:60
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v102, off, s32 offset:52
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v102, off, s32 offset:44
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v113, off, s32 offset:36
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v114, off, s32 offset:28
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v114, off, s32 offset:20
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v115, off, s32 offset:12
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v115, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v118.h, v30.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v119.l, v28.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v119.h, v26.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v130.h, v24.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v131.l, v22.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v131.h, v20.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v132.l, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v135.l, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v135.h, v14.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v144.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v144.h, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v145.l, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v148.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v148.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v149.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v149.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v150.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v150.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v151.l, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v151.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v145.h, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v146.l, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v146.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v147.l, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v147.h, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v132.h, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v133.l, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v133.h, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v134.l, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v134.h, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v128.l, 8, v29.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(62)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v50.h, 8, v50.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v50.l, 8, v50.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v49.h, 8, v49.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v54.l, 8, v54.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v53.h, 8, v53.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v53.l, 8, v53.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v64.h, 8, v64.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v64.l, 8, v64.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v55.h, 8, v55.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v69.l, 8, v69.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(61)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v68.h, 8, v68.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(59)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v68.l, 8, v68.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(54)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v103
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(53)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v128.h, 8, v81.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(52)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v129.l, 8, v81.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(51)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v129.h, 8, v82.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(50)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v130.l, 8, v82.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(49)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v116.l, 8, v83.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(48)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v116.h, 8, v86.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(47)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v117.l, 8, v86.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(46)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v117.h, 8, v87.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(45)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v118.l, 8, v87.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(44)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v103.l, 8, v96.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(43)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v103.h, 8, v99.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(42)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v112.l, 8, v99.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(41)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v112.h, 8, v100.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(40)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v113.l, 8, v100.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(39)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v99.l, 8, v101.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(38)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v99.h, 8, v160.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(37)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v100.l, 8, v160.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(36)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v100.h, 8, v161.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(35)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v101.l, 8, v161.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(34)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v86.l, 8, v162.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v86.h, 8, v162.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(32)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v87.l, 8, v163.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v87.h, 8, v163.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(30)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v96.l, 8, v164.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(29)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v81.l, 8, v164.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(28)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v81.h, 8, v165.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(27)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v82.l, 8, v165.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v82.h, 8, v70.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v83.l, 8, v69.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v69.h, 8, v65.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v70.l, 8, v65.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v65.l, 8, v55.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v65.h, 8, v54.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v54.h, 8, v51.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v55.l, 8, v51.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v51.l, 8, v31.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v51.h, 8, v31.l
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB19_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB19_4
+; GFX11-TRUE16-NEXT:  .LBB19_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB19_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v149.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v149.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v148.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v148.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v0.h, v150.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v150.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v151.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v1.h, v151.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v145.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v144.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v145.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v144.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v5
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v135.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v2.h, v146.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v132.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v135.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v146.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v147.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v5
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v131.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v132.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v3.h, v147.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v131.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v119.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v2.h, v133.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v7, v8
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v119.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v6
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v130.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v133.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v134.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v118.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v128.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v3.h, v134.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v9, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v11, v12
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v115.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v114.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v7.h, v128.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v114.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v115.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v129.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v130.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v10
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v113.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v116.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v6, v14
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v8.h, v129.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v102.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v102.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v101.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v7.h, v116.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v12, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v98.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v11
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v117.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v8.h, v117.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v118.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v98.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v97.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v103.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v14, v15
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v16, v17
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v97.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v96.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v12.h, v103.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v112.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v85.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v10, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v11, v19
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v13.h, v112.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v113.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v15
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v85.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v84.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v99.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v16
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v14
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v84.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v83.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v12.h, v99.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v100.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v17, v18
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v80.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v13.h, v100.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v101.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v19, v20
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.h, 0xff, v80.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v71.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v70.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v17.l, v86.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v21, v22
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.h, 0xff, v71.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v17.h, v86.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v18.l, v87.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v19.l, v96.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff, v17
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v67.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v15, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, v16, v24
+; GFX11-TRUE16-NEXT:    v_or_b16 v21.l, v18.h, v87.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v20
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v19
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.h, 0xff, v67.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v66.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.h, 0xff, v66.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v52.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v17.l, v81.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v21
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v17.h, v81.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v18.l, v82.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v21.l, v18.h, v82.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v19.l, v83.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, v22, v23
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v52.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v48.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v19
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v18, v24, v25
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.h, 0xff, v49.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.h, 0xff, v48.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v39.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v22.l, v68.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v23.l, v69.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v19, v26, v27
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, v21, v29
+; GFX11-TRUE16-NEXT:    v_or_b16 v25.l, v22.h, v68.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v26.l, v23.h, v69.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v24.l, v70.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v27, 0xffff, v22
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v29, 0xffff, v23
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v39.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v38.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, v20, v28
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v25
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v26
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff, v24
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.h, 0xff, v38.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.h, 0xff, v37.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v37.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v22.l, v55.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v23.l, v64.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v25.l, v22.h, v64.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v26.l, v23.h, v65.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v24.l, v65.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, v27, v28
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, v29, v30
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.l, 0xff, v36.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.l, 0xff, v35.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v29.l, 0xff, v34.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v26
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v24
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.h, 0xff, v36.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.h, 0xff, v35.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.l, v27.l, v53.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.l, v28.l, v54.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v29.l, v29.l, v55.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v25
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, v31, v37
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v26, v26, v39
+; GFX11-TRUE16-NEXT:    v_or_b16 v30.l, v27.h, v53.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v31.l, v28.h, v54.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v35, 0xffff, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v37, 0xffff, v28
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v29
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.l, 0xff, v34.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.h, 0xff, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.l, 0xff, v33.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.h, 0xff, v32.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v29.l, 0xff, v32.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v25, v25, v38
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v36, 16, v30
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v31
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.l, v27.l, v49.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v30.l, v27.h, v50.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.l, v28.l, v50.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v31.l, v28.h, v51.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v29.l, v29.l, v51.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v30, 0xffff, v30
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v33, 16, v28
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff, v31
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v29
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v27, v35, v36
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v28, v37, v38
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v29, v39, v32
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v30, v30, v33
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v31, v31, v34
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr149_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr148_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr148_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr145_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr144_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr144_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr135_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr132_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr131_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr131_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr130_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr119_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr118_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr115_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr114_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr114_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr97_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr85_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr71_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr67_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr150_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr150_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr151_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr145_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr146_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr147_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr147_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr132_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr133_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr133_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr134_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr134_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr128_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr128_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr129_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr130_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr116_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr116_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr117_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr118_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr103_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr112_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr113_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr99_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr100_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr101_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr86_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr83_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr68_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr70_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB19_2
+; GFX11-TRUE16-NEXT:  .LBB19_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v149.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v149.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v148.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v145.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v148.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v150.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v150.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v151.h, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v145.h, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v151.l, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v144.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v144.l, 3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, v135.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, v135.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v5
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v146.l, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v146.h, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v147.h, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v147.l, v3.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v2
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v132.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v131.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v131.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, v119.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v132.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v133.l, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v6
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v3.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, v130.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v7, v8
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v119.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, v118.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v133.h, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v134.h, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v6
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v134.l, v3.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v128.l, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v128.h, v7.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v4
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v9, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v11, v12
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, v115.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, v114.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v114.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.h, v115.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.l, 0x300, v7.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, v113.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v129.l, v8.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v130.l, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v116.l, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.h, v129.h, v8.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v8.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v10
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v116.h, v7.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v6, v14
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, v102.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, v101.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.l, 0x300, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v12, v13
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, v98.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, 0x300, v8.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.h, v102.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.h, v98.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v117.l, v8.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v118.l, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v103.l, v12.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v11
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.h, v117.h, v8.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v8.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v9.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, v97.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.h, v103.h, v12.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, 0x300, v12.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, 0x300, v8.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v14, v15
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v16, v17
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.h, v97.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, v96.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, v85.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v112.l, v13.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.l, 0x300, v12.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.h, v85.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.h, v112.h, v13.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v113.l, v14.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, 0x300, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v99.l, v12.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v10, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v11, v19
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, 0x300, v14.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v15
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, v84.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.h, v99.h, v12.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, 0x300, v12.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v16.l, 0x300, v13.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v14
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.h, v84.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, v83.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.l, 0x300, v12.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v17, v18
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.l, v80.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v100.l, v13.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.h, v80.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v16
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.h, v100.h, v13.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v101.l, v14.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, 0x300, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.h, 0xff, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v86.l, v17.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v16.l, 0x300, v13.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, 0x300, v14.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v19, v20
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.l, v71.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v19.l, v70.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.h, v86.h, v17.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.l, 0x300, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v21, v22
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.h, v71.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff, v17
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.l, v67.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.h, 0xff, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v87.l, v18.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v96.l, v19.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v20.l, 0x300, v17.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.h, v67.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v17.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.h, v87.h, v18.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.l, 0x300, v18.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v19.l, 0x300, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.h, 0xff, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v81.l, v17.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v15, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, v16, v24
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v21.l, 0x300, v18.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v20
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v19
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.l, v66.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.h, v66.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v19.l, v52.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.h, v81.h, v17.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.l, 0x300, v17.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.h, 0xff, v18.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v19.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v20.l, 0x300, v17.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, v22, v23
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.l, v52.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.l, v48.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v82.l, v18.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.h, v82.h, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v83.l, v19.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.h, v49.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.h, v48.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v21
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.l, 0x300, v18.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v21.l, 0x300, v18.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v19.l, 0x300, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.h, 0xff, v22.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.h, 0xff, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v68.l, v22.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v69.l, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v19
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v18, v24, v25
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v24.l, v39.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.h, v68.h, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.h, v69.h, v23.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.l, 0x300, v22.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.l, 0x300, v23.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v19, v26, v27
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, v21, v29
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v27, 0xffff, v22
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v29, 0xffff, v23
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.l, v39.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.l, v38.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v70.l, v24.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v25.l, 0x300, v22.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v26.l, 0x300, v23.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.h, v38.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.h, v37.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v23.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff, v20
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v24.l, 0x300, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.h, 0xff, v22.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.h, 0xff, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v55.h, v22.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v64.h, v23.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, v20, v28
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v25
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v26
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff, v24
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v24.l, v37.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.h, v64.l, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.h, v65.l, v23.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.l, 0x300, v22.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.l, 0x300, v23.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v25.l, 0x300, v22.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v26.l, 0x300, v23.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, v27, v28
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, v29, v30
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.l, v36.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.l, v35.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v29.l, v34.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v65.h, v24.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.h, v36.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.h, v35.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.l, 0xff, v27.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v29.l, 0xff, v29.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v24.l, 0x300, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.h, 0xff, v27.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.h, 0xff, v28.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.l, v53.l, v27.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.l, v54.l, v28.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v29.l, v55.l, v29.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v26
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v24
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.h, v53.h, v27.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.h, v54.h, v28.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.l, 0x300, v27.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.l, 0x300, v28.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v29.l, 0x300, v29.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, v31, v37
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v26, v26, v39
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v30.l, 0x300, v27.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v31.l, 0x300, v28.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v35, 0xffff, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v37, 0xffff, v28
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v29
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.l, v34.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.h, v33.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.l, v33.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.h, v32.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v29.l, v32.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.l, 0xff, v27.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.h, 0xff, v27.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.h, 0xff, v28.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v29.l, 0xff, v29.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v25
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.l, v49.h, v27.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.h, v50.l, v27.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.l, v50.h, v28.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.h, v51.l, v28.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v29.l, v51.h, v29.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v25, v25, v38
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v36, 16, v30
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v31
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.l, 0x300, v27.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v30.l, 0x300, v27.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.l, 0x300, v28.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v31.l, 0x300, v28.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v29.l, 0x300, v29.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v30, 0xffff, v30
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v33, 16, v28
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff, v31
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v29
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v27, v35, v36
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v28, v37, v38
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v29, v39, v32
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v30, v30, v33
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v31, v31, v34
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v128i8_to_v32f32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s32 offset:592
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v41, s32 offset:588
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v42, s32 offset:584
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v43, s32 offset:580
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v44, s32 offset:576
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v45, s32 offset:572
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v46, s32 offset:568
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v47, s32 offset:564
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v56, s32 offset:560
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v57, s32 offset:556
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v58, s32 offset:552
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v59, s32 offset:548
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v60, s32 offset:544
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v61, s32 offset:540
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v62, s32 offset:536
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v63, s32 offset:532
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v72, s32 offset:528
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v73, s32 offset:524
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v74, s32 offset:520
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v75, s32 offset:516
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v76, s32 offset:512
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v77, s32 offset:508
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v78, s32 offset:504
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v79, s32 offset:500
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v88, s32 offset:496
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v89, s32 offset:492
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v90, s32 offset:488
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v91, s32 offset:484
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v92, s32 offset:480
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v93, s32 offset:476
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v94, s32 offset:472
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v95, s32 offset:468
+; GFX11-FAKE16-NEXT:    s_clause 0x12
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v104, s32 offset:464
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v105, s32 offset:460
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v106, s32 offset:456
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v107, s32 offset:452
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v108, s32 offset:448
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v109, s32 offset:444
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v110, s32 offset:440
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v111, s32 offset:436
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v120, s32 offset:432
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v121, s32 offset:428
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v122, s32 offset:424
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v123, s32 offset:420
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v124, s32 offset:416
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v125, s32 offset:412
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v126, s32 offset:408
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v127, s32 offset:404
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v136, s32 offset:400
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v137, s32 offset:396
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v138, s32 offset:392
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v36, v22 :: v_dual_mov_b32 v37, v20
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v38, v18 :: v_dual_mov_b32 v39, v16
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v48, v14 :: v_dual_mov_b32 v49, v12
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v50, v10 :: v_dual_mov_b32 v51, v8
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v52, v6 :: v_dual_mov_b32 v53, v4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v54, v2 :: v_dual_mov_b32 v55, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v0, off, s32 offset:384
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v64, off, s32 offset:380
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32 offset:376
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v65, off, s32 offset:372
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v4, off, s32 offset:368
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v66, off, s32 offset:364
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v6, off, s32 offset:360
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v67, off, s32 offset:356
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v8, off, s32 offset:352
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v68, off, s32 offset:348
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v10, off, s32 offset:344
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v69, off, s32 offset:340
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v12, off, s32 offset:336
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v70, off, s32 offset:332
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v14, off, s32 offset:328
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v71, off, s32 offset:324
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v16, off, s32 offset:320
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v80, off, s32 offset:316
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v18, off, s32 offset:312
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v81, off, s32 offset:308
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v20, off, s32 offset:304
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v82, off, s32 offset:300
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v22, off, s32 offset:296
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v83, off, s32 offset:292
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v24, off, s32 offset:288
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v84, off, s32 offset:284
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v26, off, s32 offset:280
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v85, off, s32 offset:276
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v28, off, s32 offset:272
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v86, off, s32 offset:268
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v30, off, s32 offset:264
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v87, off, s32 offset:260
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v31, off, s32 offset:256
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v96, off, s32 offset:252
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v99, off, s32 offset:248
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v97, off, s32 offset:244
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v100, off, s32 offset:240
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v98, off, s32 offset:236
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v101, off, s32 offset:232
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v112, off, s32 offset:228
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v102, off, s32 offset:224
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v113, off, s32 offset:220
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v103, off, s32 offset:216
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v114, off, s32 offset:388
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v115, off, s32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v116, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v117, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v118, off, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v119, off, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v128, off, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v129, off, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v130, off, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v131, off, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v144, off, s32 offset:72
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v145, off, s32 offset:80
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v146, off, s32 offset:88
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v147, off, s32 offset:96
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v148, off, s32 offset:104
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v162, off, s32 offset:112
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v163, off, s32 offset:120
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v164, off, s32 offset:128
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v165, off, s32 offset:136
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v166, off, s32 offset:144
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v179, off, s32 offset:152
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v180, off, s32 offset:160
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v181, off, s32 offset:168
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v182, off, s32 offset:176
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v183, off, s32 offset:184
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v136, off, s32 offset:192
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v137, off, s32 offset:200
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v138, off, s32 offset:208
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v132, off, s32 offset:212
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v133, off, s32 offset:204
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v134, off, s32 offset:196
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v135, off, s32 offset:188
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v149, off, s32 offset:180
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v150, off, s32 offset:172
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v151, off, s32 offset:164
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v160, off, s32 offset:156
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v161, off, s32 offset:148
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v167, off, s32 offset:140
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v176, off, s32 offset:132
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v177, off, s32 offset:124
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v178, off, s32 offset:116
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v40, off, s32 offset:108
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v41, off, s32 offset:100
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v42, off, s32 offset:92
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v43, off, s32 offset:84
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v44, off, s32 offset:76
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v58, off, s32 offset:68
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v59, off, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v60, off, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v74, off, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v75, off, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v76, off, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v77, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v78, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v92, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v124, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v125, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v126, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v127, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v111, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v120, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v121, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v122, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v123, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v106, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v107, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v108, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v109, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v110, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v93, 8, v29
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(54)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v114
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(53)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v94, 8, v115
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(52)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v95, 8, v116
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(51)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v104, 8, v117
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(50)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v105, 8, v118
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(49)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v79, 8, v119
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(48)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v88, 8, v128
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(47)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v89, 8, v129
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(46)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v90, 8, v130
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(45)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v91, 8, v131
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(44)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v61, 8, v144
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(43)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v62, 8, v145
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(42)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v63, 8, v146
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(41)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v72, 8, v147
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(40)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v73, 8, v148
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(39)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v45, 8, v162
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(38)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v46, 8, v163
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(37)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v47, 8, v164
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(36)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v56, 8, v165
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(35)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v57, 8, v166
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(34)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v179, 8, v179
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v180, 8, v180
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(32)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v181, 8, v181
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v182, 8, v182
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(30)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v183, 8, v183
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(29)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v162, 8, v136
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(28)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v163, 8, v137
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(27)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v164, 8, v138
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v165, 8, v103
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v166, 8, v102
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v144, 8, v101
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v145, 8, v100
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v146, 8, v99
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v147, 8, v31
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v148, 8, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v119, 8, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v128, 8, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v129, 8, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v130, 8, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v131, 8, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v114, 8, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v115, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v116, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v117, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v118, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v99, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v100, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v101, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v102, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v103, 8, v0
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB19_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v53
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v52
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v51
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v124
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v125
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v126
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v127
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v50
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v37
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v49
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v48
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v111
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v121
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v120
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v122
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v123
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v107
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v38
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v108
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v109
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v110
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v106
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v6, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v8, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v10, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v32
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v92
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v78
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v77
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v76
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v75
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v74
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v60
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v59
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v93
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v94
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v95
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v104
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v105
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v79
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v88
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v89
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v90
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v91
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v13, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v15, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v58
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v44
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v43
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v42
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v41
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v40
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v178
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v177
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v176
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v167
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v61
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v62
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v63
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v72
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v73
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v17, v45
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v18, v46
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v19, v47
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v56
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v21, v57
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xffff, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xffff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v18, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v20, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v161
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v160
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v151
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v150
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v149
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v135
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v134
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v133
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v132
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v113
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v17, v179
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v18, v180
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v19, v181
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v182
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v21, v183
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v22, v162
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v23, v163
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v24, v164
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v165
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v26, v166
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xffff, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xffff, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v19, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v21, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v23, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v25, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v112
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v98
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v97
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v96
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v87
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v86
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v84
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v83
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v82
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v22, v144
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v23, v145
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v24, v146
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v147
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v26, v148
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v27, v119
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v28, v128
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v29, v129
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v30, v130
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v31, v131
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xffff, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xffff, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xffff, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xffff, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xffff, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v31
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v28, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v30, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v81
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v71
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v70
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v69
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v32, 0xff, v68
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xff, v67
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v34, 0xff, v66
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xff, v65
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v36, 0xff, v64
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v27, v114
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v28, v115
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v29, v116
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v30, v117
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v31, v118
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v32, v32, v99
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v33, v33, v100
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v34, v34, v101
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, v35, v102
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, v36, v103
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xffff, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xffff, v29
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xffff, v31
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xffff, v33
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xffff, v35
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v36, 16, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v27, v28
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v29, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v31, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v33, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v35, v36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr92
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr78
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr77
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr76
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr75
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr74
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr60
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr59
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr58
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr44
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr43
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr42
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr41
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr40
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr178
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr177
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr176
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr167
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr161
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr160
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr151
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr150
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr149
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr135
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr124
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr125
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr126
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr127
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr111
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr120
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr121
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr122
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr123
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr106
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr107
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr108
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr109
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr110
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr93
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr94
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr95
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr104
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr105
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr79
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr88
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr89
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr90
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr91
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr61
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr62
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr63
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr72
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr73
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr45
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr46
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr47
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr56
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr57
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr179
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr180
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr181
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr182
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr183
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr162
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr163
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr164
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr165
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr166
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr144
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr147
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr148
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT:  .LBB19_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB19_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v55, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v54, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v53, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v52, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v51, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v50, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v124, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v125, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v126, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v127, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v49, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v48, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v37, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v36, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v35, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v39, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, v34, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v123, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v111, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v120, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v121, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v122, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v107, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v108, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v109, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v38, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v110, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v106, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v3, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v8, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v10, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v33, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v32, 3
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v92, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v78, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, v77, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v76, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v75, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v74, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, v60, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, v59, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v93, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v94, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v95, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v104, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v105, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v79, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v88, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v89, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v90, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v91, v16
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v13
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, 0x300, v15
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, 0x300, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v13, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v15, v16
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v58, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v44, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v43, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, v42, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, v41, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, v40, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, v178, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, v177, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, v176, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, v167, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v61, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v62, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v63, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v72, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v73, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v45, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v46, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v47, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v56, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v57, v21
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v13
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, 0x300, v15
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, 0x300, v16
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, 0x300, v17
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, 0x300, v18
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, 0x300, v19
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, 0x300, v20
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, 0x300, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xffff, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xffff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v18, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v20, v21
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, v161, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, v160, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, v151, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, v150, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, v149, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, v135, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v23, v134, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v24, v133, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v25, v132, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v26, v113, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v179, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v180, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v181, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v182, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v183, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v162, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v163, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v164, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v165, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v166, v26
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, 0x300, v17
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, 0x300, v18
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, 0x300, v19
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, 0x300, v20
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, 0x300, v21
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, 0x300, v22
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v23, 0x300, v23
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v24, 0x300, v24
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v25, 0x300, v25
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v26, 0x300, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xffff, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xffff, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v19, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v21, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v23, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v25, v26
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, v112, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v23, v98, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v24, v97, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v25, v96, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v26, v87, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v27, v86, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v28, v85, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v29, v84, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v30, v83, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v31, v82, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v144, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v145, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v146, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v147, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v148, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v119, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v128, v28
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v129, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v130, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v131, v31
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, 0x300, v22
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v23, 0x300, v23
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v24, 0x300, v24
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v25, 0x300, v25
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v26, 0x300, v26
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v27, 0x300, v27
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v28, 0x300, v28
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v29, 0x300, v29
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v30, 0x300, v30
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v31, 0x300, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xffff, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xffff, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xffff, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xffff, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xffff, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v31
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v28, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v30, v31
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v27, v81, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v28, v80, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v29, v71, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v30, v70, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v31, v69, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v32, v68, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v33, v67, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v34, v66, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v35, v65, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v36, v64, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v32, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v34, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v36, 0xff, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v114, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v115, v28
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v116, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v117, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v118, v31
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v32, v99, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v33, v100, v33
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v34, v101, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, v102, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, v103, v36
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v27, 0x300, v27
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v28, 0x300, v28
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v29, 0x300, v29
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v30, 0x300, v30
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v31, 0x300, v31
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v32, 0x300, v32
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v33, 0x300, v33
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v34, 0x300, v34
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v35, 0x300, v35
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v36, 0x300, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xffff, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xffff, v29
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xffff, v31
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xffff, v33
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xffff, v35
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v36, 16, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v27, v28
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v29, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v31, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v33, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v35, v36
+; GFX11-FAKE16-NEXT:  .LBB19_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v138, off, s32 offset:392
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v137, off, s32 offset:396
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v136, off, s32 offset:400
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v127, off, s32 offset:404
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v126, off, s32 offset:408
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v125, off, s32 offset:412
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v124, off, s32 offset:416
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v123, off, s32 offset:420
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v122, off, s32 offset:424
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v121, off, s32 offset:428
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v120, off, s32 offset:432
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v111, off, s32 offset:436
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v110, off, s32 offset:440
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v109, off, s32 offset:444
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v108, off, s32 offset:448
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v107, off, s32 offset:452
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v106, off, s32 offset:456
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v105, off, s32 offset:460
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v104, off, s32 offset:464
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v95, off, s32 offset:468
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v94, off, s32 offset:472
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v93, off, s32 offset:476
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v92, off, s32 offset:480
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v91, off, s32 offset:484
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v90, off, s32 offset:488
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v89, off, s32 offset:492
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v88, off, s32 offset:496
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v79, off, s32 offset:500
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v78, off, s32 offset:504
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v77, off, s32 offset:508
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v76, off, s32 offset:512
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v75, off, s32 offset:516
+; GFX11-FAKE16-NEXT:    s_clause 0x12
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v74, off, s32 offset:520
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v73, off, s32 offset:524
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v72, off, s32 offset:528
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v63, off, s32 offset:532
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v62, off, s32 offset:536
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v61, off, s32 offset:540
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v60, off, s32 offset:544
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v59, off, s32 offset:548
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v58, off, s32 offset:552
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v57, off, s32 offset:556
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v56, off, s32 offset:560
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v47, off, s32 offset:564
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v46, off, s32 offset:568
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v45, off, s32 offset:572
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v44, off, s32 offset:576
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v43, off, s32 offset:580
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v42, off, s32 offset:584
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v41, off, s32 offset:588
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s32 offset:592
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -29262,550 +32833,1113 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v64bf16_to_v32f32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_b32 v32, off, s32 offset:4
-; GFX11-NEXT:    scratch_load_b32 v31, off, s32
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v32
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB21_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v33, 16, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v32, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
-; GFX11-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v37, v33, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v34, v32, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v35, 0x400000, v32
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_bfe_u32 v39, v14, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-NEXT:    v_add3_u32 v37, v37, v33, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v34, v34, v32, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v34, v35, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v35, v39, v14, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-NEXT:    v_or_b32_e32 v34, 0x400000, v33
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-NEXT:    v_bfe_u32 v36, v15, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v15
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v36, v36, v15, 0x7fff
-; GFX11-NEXT:    v_dual_cndmask_b32 v15, v36, v38 :: v_dual_lshlrev_b32 v36, 16, v13
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v15, v15, v32, 0x7060302
-; GFX11-NEXT:    v_dual_cndmask_b32 v33, v37, v34 :: v_dual_add_f32 v34, 0x40c00000, v36
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v32, v34, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v14
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_cndmask_b32 v14, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v12
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_perm_b32 v14, v14, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v13, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_cndmask_b32 v32, v32, v36
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-NEXT:    v_add3_u32 v33, v33, v13, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cndmask_b32_e32 v13, v33, v37, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v11
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_perm_b32 v13, v13, v32, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v32, v35, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-NEXT:    v_bfe_u32 v34, v12, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v12
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v34, v34, v12, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v12, v34, v38, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v12, v12, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v11, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_add3_u32 v33, v33, v11, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v35, v10, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v35, v35, v10, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v11, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v10
-; GFX11-NEXT:    v_perm_b32 v11, v11, v32, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    v_dual_cndmask_b32 v10, v35, v38 :: v_dual_lshlrev_b32 v37, 16, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_lshlrev_b32 v35, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-NEXT:    v_perm_b32 v10, v10, v33, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v32, v34, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v8, 0x40c00000, v8
-; GFX11-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v34, v8, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v9, 0x40c00000, v9
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_add3_u32 v34, v34, v8, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v33, v9, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v9
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    v_add3_u32 v33, v33, v9, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v9, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v8
-; GFX11-NEXT:    v_perm_b32 v9, v9, v32, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-NEXT:    v_cndmask_b32_e32 v8, v34, v38, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v8, v8, v33, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_add_f32 v35, 0x40c00000, v37
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v32, v35, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-NEXT:    v_bfe_u32 v35, v6, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v7, 0x40c00000, v7
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_add3_u32 v35, v35, v6, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v33, v7, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v7
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    v_add3_u32 v33, v33, v7, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v7, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v6
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v6, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v5
-; GFX11-NEXT:    v_perm_b32 v7, v7, v32, 0x7060302
-; GFX11-NEXT:    v_perm_b32 v6, v6, v33, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v4, 0x40c00000, v4
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v37
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v32, v34, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT:    v_bfe_u32 v34, v4, 16, 1
-; GFX11-NEXT:    v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v5, 0x40c00000, v5
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add3_u32 v34, v34, v4, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v33, v5, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v5
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v33, v33, v5, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v5, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v3
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v4
-; GFX11-NEXT:    v_perm_b32 v5, v5, v32, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_cndmask_b32 v4, v34, v38
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v2
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT:    v_bfe_u32 v32, v35, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_perm_b32 v4, v4, v33, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v35, v2, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_add3_u32 v35, v35, v2, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-NEXT:    v_bfe_u32 v33, v3, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v3
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v33, v33, v3, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v1
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v37
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v2, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v0
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    v_perm_b32 v3, v3, v32, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v32, v34, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_perm_b32 v2, v2, v33, 0x7060302
-; GFX11-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v34, v0, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_add3_u32 v34, v34, v0, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-NEXT:    v_bfe_u32 v33, v1, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v33, v33, v1, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v31
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v0
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xffff0000, v31
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_add_f32_e32 v31, 0x40c00000, v31
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v34, v38, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v30
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xffff0000, v30
-; GFX11-NEXT:    v_perm_b32 v1, v1, v32, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v32, v35, 16, 1
-; GFX11-NEXT:    v_perm_b32 v0, v0, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v31, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v30, 0x40c00000, v30
-; GFX11-NEXT:    v_add3_u32 v33, v33, v31, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v31
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-NEXT:    v_bfe_u32 v35, v30, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_cndmask_b32_e32 v31, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v29
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add3_u32 v35, v35, v30, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v30
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xffff0000, v29
-; GFX11-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add_f32_e32 v29, 0x40c00000, v29
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_dual_cndmask_b32 v30, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v28
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xffff0000, v28
-; GFX11-NEXT:    v_perm_b32 v31, v31, v32, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v32, v34, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v30, v30, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v29, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v28, 0x40c00000, v28
-; GFX11-NEXT:    v_add3_u32 v33, v33, v29, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v29
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11-NEXT:    v_bfe_u32 v34, v28, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cndmask_b32_e32 v29, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v27
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_add3_u32 v34, v34, v28, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v28
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xffff0000, v27
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v27, 0x40c00000, v27
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cndmask_b32_e32 v28, v34, v38, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v26
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xffff0000, v26
-; GFX11-NEXT:    v_perm_b32 v29, v29, v32, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v32, v35, 16, 1
-; GFX11-NEXT:    v_perm_b32 v28, v28, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v27, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v26, 0x40c00000, v26
-; GFX11-NEXT:    v_add3_u32 v33, v33, v27, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v27
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11-NEXT:    v_bfe_u32 v35, v26, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_cndmask_b32_e32 v27, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v25
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add3_u32 v35, v35, v26, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v26
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xffff0000, v25
-; GFX11-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add_f32_e32 v25, 0x40c00000, v25
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_dual_cndmask_b32 v26, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v24
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xffff0000, v24
-; GFX11-NEXT:    v_perm_b32 v27, v27, v32, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v32, v34, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v26, v26, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v25, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v24, 0x40c00000, v24
-; GFX11-NEXT:    v_add3_u32 v33, v33, v25, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v25
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-NEXT:    v_bfe_u32 v34, v24, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cndmask_b32_e32 v25, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v23
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_add3_u32 v34, v34, v24, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v24
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-NEXT:    v_perm_b32 v25, v25, v32, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v23, 0x40c00000, v23
-; GFX11-NEXT:    v_bfe_u32 v32, v35, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cndmask_b32_e32 v24, v34, v38, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xffff0000, v22
-; GFX11-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_perm_b32 v24, v24, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v23, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-NEXT:    v_add_f32_e32 v22, 0x40c00000, v22
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v23
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v33, v23, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-NEXT:    v_bfe_u32 v35, v22, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_cndmask_b32_e32 v23, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v21
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add3_u32 v35, v35, v22, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xffff0000, v21
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v22
-; GFX11-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v21, 0x40c00000, v21
-; GFX11-NEXT:    v_perm_b32 v23, v23, v32, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v36, v34, 16, 1
-; GFX11-NEXT:    v_dual_cndmask_b32 v22, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v20
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v32, v21, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v21
-; GFX11-NEXT:    v_perm_b32 v22, v22, v33, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v33, 0x40c00000, v35
-; GFX11-NEXT:    v_add3_u32 v35, v36, v34, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_add3_u32 v32, v32, v21, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xffff0000, v20
-; GFX11-NEXT:    v_bfe_u32 v38, v33, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v34, v35, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-NEXT:    v_add_f32_e32 v20, 0x40c00000, v20
-; GFX11-NEXT:    v_or_b32_e32 v35, 0x400000, v33
-; GFX11-NEXT:    v_lshlrev_b32_e32 v36, 16, v19
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff0000, v19
-; GFX11-NEXT:    v_cndmask_b32_e32 v21, v32, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v32, v38, v33, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-NEXT:    v_dual_add_f32 v33, 0x40c00000, v36 :: v_dual_lshlrev_b32 v36, 16, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v21, v21, v34, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v34, v20, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v35, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v35, 0x400000, v20
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-NEXT:    v_bfe_u32 v37, v33, 16, 1
-; GFX11-NEXT:    v_add3_u32 v34, v34, v20, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v19, 0x40c00000, v19
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xffff0000, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v20, v34, v35, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v36
-; GFX11-NEXT:    v_add3_u32 v35, v37, v33, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v33
-; GFX11-NEXT:    v_bfe_u32 v37, v19, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-NEXT:    v_or_b32_e32 v39, 0x400000, v34
-; GFX11-NEXT:    v_perm_b32 v20, v20, v32, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v35, v36, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v35, v37, v19, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v19
-; GFX11-NEXT:    v_add3_u32 v37, v38, v34, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v38, 16, v17
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-NEXT:    v_bfe_u32 v48, v18, 16, 1
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff0000, v17
-; GFX11-NEXT:    v_cndmask_b32_e32 v19, v35, v36, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add3_u32 v36, v48, v18, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v17, 0x40c00000, v17
-; GFX11-NEXT:    v_perm_b32 v19, v19, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v34, v37, v39, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v18
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v16
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff0000, v16
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v18, v36, v37, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v16, 0x40c00000, v16
-; GFX11-NEXT:    v_add_f32_e32 v36, 0x40c00000, v39
-; GFX11-NEXT:    v_add3_u32 v37, v38, v35, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v35
-; GFX11-NEXT:    v_bfe_u32 v39, v17, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_bfe_u32 v48, v36, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v49, 0x400000, v36
-; GFX11-NEXT:    v_or_b32_e32 v50, 0x400000, v16
-; GFX11-NEXT:    v_perm_b32 v18, v18, v34, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v35, v37, v38, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v38, v39, v17, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v39, 0x400000, v17
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-NEXT:    v_bfe_u32 v37, v16, 16, 1
-; GFX11-NEXT:    v_add3_u32 v48, v48, v36, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v17, v38, v39, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-NEXT:    v_add3_u32 v37, v37, v16, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v17, v17, v35, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v36, v48, v49, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-NEXT:    v_cndmask_b32_e32 v16, v37, v50, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v16, v16, v36, 0x7060302
-; GFX11-NEXT:  .LBB21_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v64bf16_to_v32f32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v32
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB21_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v33, 0xffff0000, v14
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_lshlrev_b32 v32, 16, v15
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v32, 0x40c00000, v32
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v39, v33, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v32, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v32
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v32
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v32, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v32, v35, v38 :: v_dual_and_b32 v15, 0xffff0000, v15
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v15, 0x40c00000, v15 :: v_dual_lshlrev_b32 v14, 16, v14
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v39, v33, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v32.l, v32.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v15, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v15
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT:    v_add3_u32 v36, v36, v15, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v15, v36, v37
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v48, v14, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v49, 0x400000, v14
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v33
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v15, 0xffff, v32, v15
+; GFX11-TRUE16-NEXT:    v_add3_u32 v38, v48, v14, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v14, v38, v49, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v13
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v14.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v33, v35, v36 :: v_dual_add_f32 v34, 0x40c00000, v34
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v14, 0xffff, v14, v33
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v34, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v38, v13, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v36, v38, v13, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v13
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v13, v36, v37 :: v_dual_and_b32 v38, 0xffff0000, v12
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v35, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v13, 0xffff, v13, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v36
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v12, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v35, 0x400000, v12
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v12, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v12, v32, v35, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v11, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v10
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v11, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v11
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v36
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v11, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v33, v33, v38 :: v_dual_and_b32 v38, 0xffff0000, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v11, 0xffff, v11, v33
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v10, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v10, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v10, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v12, 0xffff, v12, v32
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v9, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v10, 0xffff, v10, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v9, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_cndmask_b32 v9, v32, v36
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v9.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v9, 0xffff, v9, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v8, 0xffff, v8, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v7, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v6, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v7, 0xffff, v7, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v6, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v32, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v4, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v6, 0xffff, v6, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v5, 0xffff, v5, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v4, 0xffff, v4, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_cndmask_b32 v3, v32, v36
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v3, 0xffff, v3, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v2, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v35, 0x40c00000, v38 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v34
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v31
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v31
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v31, 0x40c00000, v31
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v32, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v31, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v30
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v30
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v31, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v31
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v30, 0x40c00000, v30
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v31, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v30, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v0, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v31.l, v31.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v30, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v30
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v29
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v31, 0xffff, v31, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v30, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v29, 0x40c00000, v29
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.l, v30.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v29, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v30, 0xffff, v30, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v28
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v29, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v29
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v28, 0x40c00000, v28
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v29, v32, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v28, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v27
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v28, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v28
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v27, 0x40c00000, v27
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.l, v29.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v28, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v27, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v29, 0xffff, v29, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.l, v28.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v27, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v27
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v26
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v26
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v28, 0xffff, v28, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v27, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v26, 0x40c00000, v26
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.l, v27.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v26, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v27, 0xffff, v27, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v25
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v26, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v26
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v25, 0x40c00000, v25
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v26, v32, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v25, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v24
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v25, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v25
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v24, 0x40c00000, v24
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v26.l, v26.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v25, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v24, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v26, 0xffff, v26, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v25.l, v25.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v24, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v24
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v23
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v25, 0xffff, v25, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v24, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v23, 0x40c00000, v23
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v24.l, v24.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v23, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v24, 0xffff, v24, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v23, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v23
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff0000, v20
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v23, v32, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v22, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v21
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v22, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v22
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v21, 0x40c00000, v21
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v23.l, v23.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v22, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v21, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v23, 0xffff, v23, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.l, v22.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v21, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v21
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v36
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v22, 0xffff, v22, v33
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v20, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v21, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v39
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v20
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v20, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.l, v21.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v18
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v21, 0xffff, v21, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v19
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v20, v33, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v19, 0x40c00000, v19
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v32, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v19
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v36, v36, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v39, v35, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.l, v20.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v19, v36, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v39, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v18, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v19.h
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v33, v33, v38 :: v_dual_and_b32 v38, 0xffff0000, v17
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v20, 0xffff, v20, v32
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v37, 0x40c00000, v38 :: v_dual_cndmask_b32 v34, v34, v36
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v17, 0x40c00000, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v18
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v16
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v49, 0x400000, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v48, 0x400000, v37
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v19, 0xffff, v19, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v18, v35, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v38, v17, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v37, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v16, 0x40c00000, v16
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v39, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v38, v38, v17, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v51, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v37, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v50, v16, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v39, v39, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v17, v38, v49, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v49, 0x400000, v16
+; GFX11-TRUE16-NEXT:    v_add3_u32 v38, v50, v16, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v18.l, v18.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v17.l, v17.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v36, v39, v51, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v18, 0xffff, v18, v34
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.l, v36.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v35, v35, v48, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v17, 0xffff, v17, v35
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v16, v38, v49, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v16, 0xffff, v36, v16
+; GFX11-TRUE16-NEXT:  .LBB21_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v64bf16_to_v32f32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v32
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB21_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v33, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v33, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v32, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, 0x400000, v32
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v39, v14, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v32
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v37, v33, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v32, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v34, v35, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v39, v14, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v34, 0x400000, v33
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v36, v15, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v15
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v36, v36, v15, 0x7fff
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v15, v36, v38 :: v_dual_lshlrev_b32 v36, 16, v13
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v15, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v33, v37, v34 :: v_dual_add_f32 v34, 0x40c00000, v36
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v14
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v14, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v12
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v14, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v13, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_cndmask_b32 v32, v32, v36
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v13, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v13, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v13, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v12, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v12
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v12, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v34, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v12, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v11, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v11, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v10, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v10
+; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v11, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v35, v38 :: v_dual_lshlrev_b32 v37, 16, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_lshlrev_b32 v35, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v10, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v8, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v8, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v8
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v9, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v34, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v8, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_add_f32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v6, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v7, 0x40c00000, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v6, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v5
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v6, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v5
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v5, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_cndmask_b32 v4, v34, v38
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v4, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v3, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v31
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xffff0000, v31
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v31, 0x40c00000, v31
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v34, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xffff0000, v30
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v31, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v30, 0x40c00000, v30
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v31, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v31
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v30, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v31, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v29
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v30, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xffff0000, v29
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v29, 0x40c00000, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v30, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xffff0000, v28
+; GFX11-FAKE16-NEXT:    v_perm_b32 v31, v31, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v30, v30, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v29, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v28, 0x40c00000, v28
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v29, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v29
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v28, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v29, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v27
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v28, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xffff0000, v27
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v27, 0x40c00000, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v28, v34, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xffff0000, v26
+; GFX11-FAKE16-NEXT:    v_perm_b32 v29, v29, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v28, v28, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v27, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v26, 0x40c00000, v26
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v27, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v27
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v26, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v27, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v25
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v26, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xffff0000, v25
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v25, 0x40c00000, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v26, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xffff0000, v24
+; GFX11-FAKE16-NEXT:    v_perm_b32 v27, v27, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v26, v26, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v25, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v24, 0x40c00000, v24
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v25, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v25
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v24, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v25, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v23
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v24, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xffff0000, v23
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-FAKE16-NEXT:    v_perm_b32 v25, v25, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v23, 0x40c00000, v23
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v24, v34, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_perm_b32 v24, v24, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v23, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v23
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v23, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v22, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v23, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v21
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v22, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xffff0000, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v22
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v21, 0x40c00000, v21
+; GFX11-FAKE16-NEXT:    v_perm_b32 v23, v23, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v36, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v22, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v20
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v21, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v21
+; GFX11-FAKE16-NEXT:    v_perm_b32 v22, v22, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v33, 0x40c00000, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v36, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v21, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v33, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v34, v35, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, 0x400000, v33
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v36, 16, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff0000, v19
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v21, v32, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v38, v33, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v33, 0x40c00000, v36 :: v_dual_lshlrev_b32 v36, 16, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v21, v21, v34, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v20, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v35, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, 0x400000, v20
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v33, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v20, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v20, v34, v35, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v36
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v37, v33, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v33
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v19, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v39, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_perm_b32 v20, v20, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v35, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v37, v19, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v19
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v17
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v48, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff0000, v17
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v19, v35, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v36, v48, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v17, 0x40c00000, v17
+; GFX11-FAKE16-NEXT:    v_perm_b32 v19, v19, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v34, v37, v39, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v16
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v36, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v16, 0x40c00000, v16
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v39
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v39, v17, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v48, v36, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v49, 0x400000, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v50, 0x400000, v16
+; GFX11-FAKE16-NEXT:    v_perm_b32 v18, v18, v34, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v35, v37, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v38, v39, v17, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v39, 0x400000, v17
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v16, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v48, v48, v36, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v38, v39, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v37, v16, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v17, v17, v35, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v36, v48, v49, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v37, v50, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v16, v16, v36, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB21_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -36682,701 +40816,1274 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v16i64_to_v128i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x13
-; GFX11-NEXT:    scratch_store_b32 off, v40, s32 offset:88
-; GFX11-NEXT:    scratch_store_b32 off, v41, s32 offset:84
-; GFX11-NEXT:    scratch_store_b32 off, v42, s32 offset:80
-; GFX11-NEXT:    scratch_store_b32 off, v43, s32 offset:76
-; GFX11-NEXT:    scratch_store_b32 off, v44, s32 offset:72
-; GFX11-NEXT:    scratch_store_b32 off, v45, s32 offset:68
-; GFX11-NEXT:    scratch_store_b32 off, v46, s32 offset:64
-; GFX11-NEXT:    scratch_store_b32 off, v47, s32 offset:60
-; GFX11-NEXT:    scratch_store_b32 off, v56, s32 offset:56
-; GFX11-NEXT:    scratch_store_b32 off, v57, s32 offset:52
-; GFX11-NEXT:    scratch_store_b32 off, v58, s32 offset:48
-; GFX11-NEXT:    scratch_store_b32 off, v59, s32 offset:44
-; GFX11-NEXT:    scratch_store_b32 off, v60, s32 offset:40
-; GFX11-NEXT:    scratch_store_b32 off, v61, s32 offset:36
-; GFX11-NEXT:    scratch_store_b32 off, v62, s32 offset:32
-; GFX11-NEXT:    scratch_store_b32 off, v63, s32 offset:28
-; GFX11-NEXT:    scratch_store_b32 off, v72, s32 offset:24
-; GFX11-NEXT:    scratch_store_b32 off, v73, s32 offset:20
-; GFX11-NEXT:    scratch_store_b32 off, v74, s32 offset:16
-; GFX11-NEXT:    scratch_store_b32 off, v75, s32 offset:12
-; GFX11-NEXT:    s_clause 0x2
-; GFX11-NEXT:    scratch_load_b32 v33, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_b32 v32, off, s32 offset:4
-; GFX11-NEXT:    scratch_load_b32 v31, off, s32
-; GFX11-NEXT:    ; implicit-def: $vgpr75
-; GFX11-NEXT:    ; implicit-def: $vgpr74
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr73
-; GFX11-NEXT:    ; implicit-def: $vgpr72
-; GFX11-NEXT:    ; implicit-def: $vgpr63
-; GFX11-NEXT:    ; implicit-def: $vgpr62
-; GFX11-NEXT:    ; implicit-def: $vgpr61
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr60
-; GFX11-NEXT:    ; implicit-def: $vgpr59
-; GFX11-NEXT:    ; implicit-def: $vgpr58
-; GFX11-NEXT:    ; implicit-def: $vgpr57
-; GFX11-NEXT:    ; implicit-def: $vgpr56
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr47
-; GFX11-NEXT:    ; implicit-def: $vgpr46
-; GFX11-NEXT:    ; implicit-def: $vgpr45
-; GFX11-NEXT:    ; implicit-def: $vgpr44
-; GFX11-NEXT:    ; implicit-def: $vgpr43
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr42
-; GFX11-NEXT:    ; implicit-def: $vgpr41
-; GFX11-NEXT:    ; implicit-def: $vgpr40
-; GFX11-NEXT:    ; implicit-def: $vgpr183
-; GFX11-NEXT:    ; implicit-def: $vgpr182
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr181
-; GFX11-NEXT:    ; implicit-def: $vgpr180
-; GFX11-NEXT:    ; implicit-def: $vgpr179
-; GFX11-NEXT:    ; implicit-def: $vgpr178
-; GFX11-NEXT:    ; implicit-def: $vgpr177
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr176
-; GFX11-NEXT:    ; implicit-def: $vgpr167
-; GFX11-NEXT:    ; implicit-def: $vgpr166
-; GFX11-NEXT:    ; implicit-def: $vgpr165
-; GFX11-NEXT:    ; implicit-def: $vgpr164
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr163
-; GFX11-NEXT:    ; implicit-def: $vgpr162
-; GFX11-NEXT:    ; implicit-def: $vgpr161
-; GFX11-NEXT:    ; implicit-def: $vgpr160
-; GFX11-NEXT:    ; implicit-def: $vgpr151
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr150
-; GFX11-NEXT:    ; implicit-def: $vgpr149
-; GFX11-NEXT:    ; implicit-def: $vgpr148
-; GFX11-NEXT:    ; implicit-def: $vgpr147
-; GFX11-NEXT:    ; implicit-def: $vgpr146
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr145
-; GFX11-NEXT:    ; implicit-def: $vgpr144
-; GFX11-NEXT:    ; implicit-def: $vgpr135
-; GFX11-NEXT:    ; implicit-def: $vgpr134
-; GFX11-NEXT:    ; implicit-def: $vgpr133
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr132
-; GFX11-NEXT:    ; implicit-def: $vgpr131
-; GFX11-NEXT:    ; implicit-def: $vgpr130
-; GFX11-NEXT:    ; implicit-def: $vgpr129
-; GFX11-NEXT:    ; implicit-def: $vgpr128
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr119
-; GFX11-NEXT:    ; implicit-def: $vgpr118
-; GFX11-NEXT:    ; implicit-def: $vgpr117
-; GFX11-NEXT:    ; implicit-def: $vgpr116
-; GFX11-NEXT:    ; implicit-def: $vgpr115
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr114
-; GFX11-NEXT:    ; implicit-def: $vgpr113
-; GFX11-NEXT:    ; implicit-def: $vgpr112
-; GFX11-NEXT:    ; implicit-def: $vgpr103
-; GFX11-NEXT:    ; implicit-def: $vgpr102
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr101
-; GFX11-NEXT:    ; implicit-def: $vgpr100
-; GFX11-NEXT:    ; implicit-def: $vgpr99
-; GFX11-NEXT:    ; implicit-def: $vgpr98
-; GFX11-NEXT:    ; implicit-def: $vgpr97
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    s_waitcnt vmcnt(2)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v33
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB28_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b64 v[48:49], 24, v[19:20]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
-; GFX11-NEXT:    v_lshrrev_b64 v[49:50], 24, v[17:18]
-; GFX11-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
-; GFX11-NEXT:    v_lshrrev_b64 v[50:51], 24, v[15:16]
-; GFX11-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
-; GFX11-NEXT:    v_lshrrev_b64 v[51:52], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
-; GFX11-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
-; GFX11-NEXT:    v_lshrrev_b64 v[64:65], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
-; GFX11-NEXT:    v_lshrrev_b64 v[53:54], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[65:66], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v68, 24, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v69, 16, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v70, 8, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v71, 16, v31
-; GFX11-NEXT:    v_lshrrev_b32_e32 v80, 8, v31
-; GFX11-NEXT:    v_lshrrev_b32_e32 v81, 24, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v82, 16, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v83, 8, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v84, 16, v29
-; GFX11-NEXT:    v_lshrrev_b32_e32 v85, 8, v29
-; GFX11-NEXT:    v_lshrrev_b32_e32 v86, 24, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v87, 16, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v96, 8, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v97, 16, v27
-; GFX11-NEXT:    v_lshrrev_b32_e32 v98, 8, v27
-; GFX11-NEXT:    v_lshrrev_b32_e32 v99, 24, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v100, 16, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v101, 8, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v102, 16, v25
-; GFX11-NEXT:    v_lshrrev_b32_e32 v103, 8, v25
-; GFX11-NEXT:    v_lshrrev_b32_e32 v112, 24, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v113, 16, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v114, 8, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v115, 16, v23
-; GFX11-NEXT:    v_lshrrev_b32_e32 v116, 8, v23
-; GFX11-NEXT:    v_lshrrev_b32_e32 v117, 24, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v118, 16, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v119, 8, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v128, 16, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v129, 8, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v130, 24, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v131, 16, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v132, 8, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v133, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v134, 8, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v135, 24, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v144, 16, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v145, 8, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v146, 16, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v147, 8, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v148, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v149, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v150, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v151, 16, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v160, 8, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v161, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v162, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v163, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v164, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v165, 8, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v166, 24, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v167, 16, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v176, 8, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v177, 16, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v178, 8, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v179, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v180, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v181, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v182, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v183, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v40, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v41, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v42, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v43, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v44, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v45, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v46, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v47, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v56, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v57, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v58, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v59, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v60, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v61, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v62, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v63, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v72, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v73, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v74, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v75, 8, v1
-; GFX11-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
-; GFX11-NEXT:    v_lshrrev_b64 v[54:55], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[66:67], 24, v[1:2]
-; GFX11-NEXT:  .LBB28_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB28_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_co_u32 v1, vcc_lo, v1, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v2, null, 0, v2, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v3, vcc_lo, v3, 3
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v4, null, 0, v4, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v5, vcc_lo, v5, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v6, null, 0, v6, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v7, vcc_lo, v7, 3
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v8, null, 0, v8, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v9, vcc_lo, v9, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v10, null, 0, v10, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v11, vcc_lo, v11, 3
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v12, null, 0, v12, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v13, vcc_lo, v13, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v14, null, 0, v14, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v15, vcc_lo, v15, 3
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v16, null, 0, v16, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v17, vcc_lo, v17, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v18, null, 0, v18, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v19, vcc_lo, v19, 3
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v20, null, 0, v20, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v21, vcc_lo, v21, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v22, null, 0, v22, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v25, vcc_lo, v25, 3
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v26, null, 0, v26, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v27, vcc_lo, v27, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v28, null, 0, v28, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v29, vcc_lo, v29, 3
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v30, null, 0, v30, vcc_lo
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_co_u32 v31, vcc_lo, v31, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v32, null, 0, v32, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v23, vcc_lo, v23, 3
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v24, null, 0, v24, vcc_lo
-; GFX11-NEXT:    v_lshrrev_b64 v[48:49], 24, v[19:20]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
-; GFX11-NEXT:    v_lshrrev_b64 v[49:50], 24, v[17:18]
-; GFX11-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
-; GFX11-NEXT:    v_lshrrev_b64 v[50:51], 24, v[15:16]
-; GFX11-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
-; GFX11-NEXT:    v_lshrrev_b64 v[51:52], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
-; GFX11-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
-; GFX11-NEXT:    v_lshrrev_b64 v[64:65], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
-; GFX11-NEXT:    v_lshrrev_b64 v[53:54], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[65:66], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
-; GFX11-NEXT:    v_lshrrev_b64 v[54:55], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[66:67], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v68, 24, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v69, 16, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v70, 8, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v71, 16, v31
-; GFX11-NEXT:    v_lshrrev_b32_e32 v80, 8, v31
-; GFX11-NEXT:    v_lshrrev_b32_e32 v81, 24, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v82, 16, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v83, 8, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v84, 16, v29
-; GFX11-NEXT:    v_lshrrev_b32_e32 v85, 8, v29
-; GFX11-NEXT:    v_lshrrev_b32_e32 v86, 24, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v87, 16, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v96, 8, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v97, 16, v27
-; GFX11-NEXT:    v_lshrrev_b32_e32 v98, 8, v27
-; GFX11-NEXT:    v_lshrrev_b32_e32 v99, 24, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v100, 16, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v101, 8, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v102, 16, v25
-; GFX11-NEXT:    v_lshrrev_b32_e32 v103, 8, v25
-; GFX11-NEXT:    v_lshrrev_b32_e32 v112, 24, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v113, 16, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v114, 8, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v115, 16, v23
-; GFX11-NEXT:    v_lshrrev_b32_e32 v116, 8, v23
-; GFX11-NEXT:    v_lshrrev_b32_e32 v117, 24, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v118, 16, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v119, 8, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v128, 16, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v129, 8, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v130, 24, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v131, 16, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v132, 8, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v133, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v134, 8, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v135, 24, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v144, 16, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v145, 8, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v146, 16, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v147, 8, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v148, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v149, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v150, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v151, 16, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v160, 8, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v161, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v162, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v163, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v164, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v165, 8, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v166, 24, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v167, 16, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v176, 8, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v177, 16, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v178, 8, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v179, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v180, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v181, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v182, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v183, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v40, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v41, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v42, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v43, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v44, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v45, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v46, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v47, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v56, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v57, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v58, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v59, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v60, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v61, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v62, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v63, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v72, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v73, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v74, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v75, 8, v1
-; GFX11-NEXT:  .LBB28_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v75
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v66
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_lshlrev_b16 v66, 8, v63
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v65
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v55
-; GFX11-NEXT:    v_and_b32_e32 v55, 0xff, v74
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v67, 0xff, v61
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_or_b32_e32 v39, v55, v39
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v73
-; GFX11-NEXT:    v_or_b32_e32 v65, v67, v65
-; GFX11-NEXT:    v_lshlrev_b16 v67, 8, v58
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v39
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v55
-; GFX11-NEXT:    v_and_b32_e32 v55, 0xff, v72
-; GFX11-NEXT:    v_lshlrev_b16 v64, 8, v64
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v39
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_or_b32_e32 v55, v55, v66
-; GFX11-NEXT:    v_lshlrev_b16 v66, 8, v62
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v54
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v66
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v60
-; GFX11-NEXT:    v_and_b32_e32 v66, 0xff, v59
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v53
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v39
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v65
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v55
-; GFX11-NEXT:    v_or_b32_e32 v55, v66, v67
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v57
-; GFX11-NEXT:    v_and_b32_e32 v66, 0xff, v56
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v39
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v65
-; GFX11-NEXT:    v_or_b32_e32 v55, v66, v64
-; GFX11-NEXT:    v_lshlrev_b16 v64, 8, v47
-; GFX11-NEXT:    v_and_b32_e32 v65, 0xff, v46
-; GFX11-NEXT:    v_lshlrev_b16 v66, 8, v45
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v39
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v64
-; GFX11-NEXT:    v_or_b32_e32 v55, v65, v66
-; GFX11-NEXT:    v_lshlrev_b16 v64, 8, v44
-; GFX11-NEXT:    v_and_b32_e32 v65, 0xff, v43
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v39
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v64
-; GFX11-NEXT:    v_or_b32_e32 v54, v65, v54
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v42
-; GFX11-NEXT:    v_and_b32_e32 v64, 0xff, v41
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v40
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v39
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v54
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v55
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_or_b32_e32 v54, v64, v65
-; GFX11-NEXT:    v_and_b32_e32 v64, 0xff, v182
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v183
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v181
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v54, 16, v54
-; GFX11-NEXT:    v_or_b32_e32 v53, v64, v53
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v55
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v65
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v39
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v54
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v53
-; GFX11-NEXT:    v_and_b32_e32 v53, 0xff, v180
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v179
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v178
-; GFX11-NEXT:    v_and_b32_e32 v64, 0xff, v177
-; GFX11-NEXT:    v_lshlrev_b16 v52, 8, v52
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v176
-; GFX11-NEXT:    v_and_b32_e32 v66, 0xff, v167
-; GFX11-NEXT:    v_lshlrev_b16 v67, 8, v166
-; GFX11-NEXT:    v_or_b32_e32 v53, v53, v54
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v55
-; GFX11-NEXT:    v_or_b32_e32 v52, v64, v52
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v65
-; GFX11-NEXT:    v_or_b32_e32 v54, v66, v67
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v53, 16, v53
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v52, 16, v52
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v54, 16, v54
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off
-; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
-; GFX11-NEXT:    v_or_b32_e32 v1, v9, v39
-; GFX11-NEXT:    v_or_b32_e32 v2, v10, v53
-; GFX11-NEXT:    v_or_b32_e32 v3, v11, v52
-; GFX11-NEXT:    v_or_b32_e32 v4, v12, v54
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v13
-; GFX11-NEXT:    v_lshlrev_b16 v6, 8, v165
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v164
-; GFX11-NEXT:    v_lshlrev_b16 v8, 8, v51
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v14
-; GFX11-NEXT:    v_lshlrev_b16 v10, 8, v163
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v162
-; GFX11-NEXT:    v_lshlrev_b16 v12, 8, v161
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v15
-; GFX11-NEXT:    v_lshlrev_b16 v14, 8, v160
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v8, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v9, v13, v14
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v151
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v50
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v16
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v150
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v149
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v148
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v17
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v147
-; GFX11-NEXT:    v_and_b32_e32 v39, 0xff, v146
-; GFX11-NEXT:    v_lshlrev_b16 v49, 8, v49
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v11, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v12, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v13, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v14, v39, v49
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v8, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v9, v13, v14
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v18
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v145
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v144
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v135
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v19
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v134
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v133
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v48
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v20
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v132
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v11, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v12, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v13, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v14, v18, v19
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v131
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v130
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v21
-; GFX11-NEXT:    v_lshlrev_b16 v18, 8, v129
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v128
-; GFX11-NEXT:    v_lshlrev_b16 v20, 8, v38
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v22
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v119
-; GFX11-NEXT:    v_and_b32_e32 v38, 0xff, v118
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v117
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v16
-; GFX11-NEXT:    v_or_b32_e32 v16, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v17, v19, v20
-; GFX11-NEXT:    v_or_b32_e32 v18, v21, v22
-; GFX11-NEXT:    v_or_b32_e32 v19, v38, v39
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xffff, v18
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v11, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v12, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v13, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v14, v18, v19
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v23
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v116
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v115
-; GFX11-NEXT:    v_lshlrev_b16 v18, 8, v37
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v24
-; GFX11-NEXT:    v_lshlrev_b16 v20, 8, v114
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v113
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v112
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v25
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v103
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v16
-; GFX11-NEXT:    v_or_b32_e32 v16, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v17, v19, v20
-; GFX11-NEXT:    v_or_b32_e32 v18, v21, v22
-; GFX11-NEXT:    v_or_b32_e32 v19, v23, v24
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v102
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v36
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v26
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v101
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v100
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v99
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v27
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v98
-; GFX11-NEXT:    v_and_b32_e32 v36, 0xff, v97
-; GFX11-NEXT:    v_lshlrev_b16 v35, 8, v35
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v21, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v22, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v23, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v24, v36, v35
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff, v19
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xffff, v21
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xffff, v23
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v16
-; GFX11-NEXT:    v_or_b32_e32 v16, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v17, v19, v20
-; GFX11-NEXT:    v_or_b32_e32 v18, v21, v22
-; GFX11-NEXT:    v_or_b32_e32 v19, v23, v24
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v28
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v96
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v87
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v86
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v29
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v85
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v84
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v34
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v30
-; GFX11-NEXT:    v_lshlrev_b16 v29, 8, v83
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v21, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v22, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v23, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v24, v28, v29
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v82
-; GFX11-NEXT:    v_lshlrev_b16 v26, 8, v81
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v31
-; GFX11-NEXT:    v_lshlrev_b16 v28, 8, v80
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v71
-; GFX11-NEXT:    v_lshlrev_b16 v30, 8, v33
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v32
-; GFX11-NEXT:    v_lshlrev_b16 v32, 8, v70
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xff, v69
-; GFX11-NEXT:    v_lshlrev_b16 v34, 8, v68
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v26
-; GFX11-NEXT:    v_or_b32_e32 v26, v27, v28
-; GFX11-NEXT:    v_or_b32_e32 v27, v29, v30
-; GFX11-NEXT:    v_or_b32_e32 v28, v31, v32
-; GFX11-NEXT:    v_or_b32_e32 v29, v33, v34
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xffff, v20
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xffff, v22
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xffff, v24
-; GFX11-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xffff, v26
-; GFX11-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xffff, v28
-; GFX11-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v21, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v22, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v23, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v24, v28, v29
-; GFX11-NEXT:    s_clause 0x5
-; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off offset:32
-; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:48
-; GFX11-NEXT:    scratch_store_b128 v0, v[9:12], off offset:64
-; GFX11-NEXT:    scratch_store_b128 v0, v[13:16], off offset:80
-; GFX11-NEXT:    scratch_store_b128 v0, v[17:20], off offset:96
-; GFX11-NEXT:    scratch_store_b128 v0, v[21:24], off offset:112
-; GFX11-NEXT:    s_clause 0x13
-; GFX11-NEXT:    scratch_load_b32 v75, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_b32 v74, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_b32 v73, off, s32 offset:20
-; GFX11-NEXT:    scratch_load_b32 v72, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_b32 v63, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_b32 v62, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_b32 v61, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_b32 v60, off, s32 offset:40
-; GFX11-NEXT:    scratch_load_b32 v59, off, s32 offset:44
-; GFX11-NEXT:    scratch_load_b32 v58, off, s32 offset:48
-; GFX11-NEXT:    scratch_load_b32 v57, off, s32 offset:52
-; GFX11-NEXT:    scratch_load_b32 v56, off, s32 offset:56
-; GFX11-NEXT:    scratch_load_b32 v47, off, s32 offset:60
-; GFX11-NEXT:    scratch_load_b32 v46, off, s32 offset:64
-; GFX11-NEXT:    scratch_load_b32 v45, off, s32 offset:68
-; GFX11-NEXT:    scratch_load_b32 v44, off, s32 offset:72
-; GFX11-NEXT:    scratch_load_b32 v43, off, s32 offset:76
-; GFX11-NEXT:    scratch_load_b32 v42, off, s32 offset:80
-; GFX11-NEXT:    scratch_load_b32 v41, off, s32 offset:84
-; GFX11-NEXT:    scratch_load_b32 v40, off, s32 offset:88
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v16i64_to_v128i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x2
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v33, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr162_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr161_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr160_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr151_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr150_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr149_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr148_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr147_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr145_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr144_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr134_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr133_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr132_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr131_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr130_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr128_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr119_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr118_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr117_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr116_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr115_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr114_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr113_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr103_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr101_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr100_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr99_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr97_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr86_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr85_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr83_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr71_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr70_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr68_lo16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v33
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB28_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[48:49], 24, v[19:20]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[49:50], 24, v[17:18]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[50:51], 24, v[15:16]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[51:52], 24, v[13:14]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[64:65], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[53:54], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[65:66], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v68, 24, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v69, 8, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v70, 8, v31
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v71, 24, v30
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v80, 8, v30
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v81, 8, v29
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v82, 24, v28
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v83, 8, v28
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v84, 8, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v85, 24, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v86, 8, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v87, 8, v25
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v96, 24, v24
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v97, 8, v24
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v98, 8, v23
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v99, 24, v22
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v100, 8, v22
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v101, 8, v21
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v102, 24, v20
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v103, 8, v20
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v112, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v113, 24, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v114, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v115, 8, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v116, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v117, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v118, 8, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v119, 24, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v128, 8, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v129, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v130, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v131, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v132, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v133, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v134, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v135, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v144, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v145, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v146, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v147, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v148, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v149, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v150, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v151, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v160, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v161, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v162, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[54:55], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[66:67], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB28_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB28_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v1, vcc_lo, v1, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v2, null, 0, v2, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v3, vcc_lo, v3, 3
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v4, null, 0, v4, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v5, vcc_lo, v5, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v6, null, 0, v6, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v7, vcc_lo, v7, 3
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v8, null, 0, v8, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v9, vcc_lo, v9, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v10, null, 0, v10, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v11, vcc_lo, v11, 3
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v12, null, 0, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v13, vcc_lo, v13, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v14, null, 0, v14, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v15, vcc_lo, v15, 3
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v16, null, 0, v16, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v17, vcc_lo, v17, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v18, null, 0, v18, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v19, vcc_lo, v19, 3
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v20, null, 0, v20, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v21, vcc_lo, v21, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v22, null, 0, v22, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v25, vcc_lo, v25, 3
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v26, null, 0, v26, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v27, vcc_lo, v27, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v28, null, 0, v28, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v29, vcc_lo, v29, 3
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v30, null, 0, v30, vcc_lo
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v31, vcc_lo, v31, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v32, null, 0, v32, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v23, vcc_lo, v23, 3
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v24, null, 0, v24, vcc_lo
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[48:49], 24, v[19:20]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[49:50], 24, v[17:18]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[50:51], 24, v[15:16]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[51:52], 24, v[13:14]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[64:65], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[53:54], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[65:66], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[54:55], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[66:67], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v68, 24, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v69, 8, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v70, 8, v31
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v71, 24, v30
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v80, 8, v30
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v81, 8, v29
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v82, 24, v28
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v83, 8, v28
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v84, 8, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v85, 24, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v86, 8, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v87, 8, v25
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v96, 24, v24
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v97, 8, v24
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v98, 8, v23
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v99, 24, v22
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v100, 8, v22
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v101, 8, v21
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v102, 24, v20
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v103, 8, v20
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v112, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v113, 24, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v114, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v115, 8, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v116, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v117, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v118, 8, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v119, 24, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v128, 8, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v129, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v130, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v131, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v132, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v133, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v134, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v135, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v144, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v145, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v146, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v147, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v148, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v149, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v150, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v151, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v160, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v161, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v162, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB28_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v39.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v34.h, 8, v66.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v33.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v161.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v39.l, v1.h, v34.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v162.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v39
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.h, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v55, 0xffff, v55
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v160.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v150.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v66.l, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v67.l, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v65.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v55, v39
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v55, 0xffff, v66
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v65, 16, v67
+; GFX11-TRUE16-NEXT:    v_or_b16 v39.l, v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 8, v151.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v55, v65
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v39
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.h, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.h, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v149.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v55, 16, v55
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.l, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v66.l, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v64.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v3.h, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v39, v55
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v65
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v55, 16, v66
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v4.h, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.l, 8, v148.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v147.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v39, v55
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.h, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.h, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v54.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v64
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v146.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v55
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v5.h, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v39, v54
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v64
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v145.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v144.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v55
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v39, v54
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v55
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v53.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v134.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.l, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v8.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v135.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v10.l, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v53, 0xffff, v53
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v55, 16, v55
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v64
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.h, v8.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.l, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v11.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v53, v55
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v55, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v10.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v132.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v52.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v39, v54
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v133.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v11.h
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v129.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v131.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v34.h, 8, v130.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v51.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v33.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v39.l, v12.h, v34.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v10, v11
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v128.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v15.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v50.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v39
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v55, v9
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v14.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v119.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v118.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v6
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v12, v39
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v16.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v117.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v16.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v116.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v10, v11
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v114.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v115.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v18.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v113.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v12, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v14, v15
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v19.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v112.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v19.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v48.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v20.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v102.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v16, v17
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v20.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v103.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v11
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v21.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v101.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v14.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v21.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v38.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v15, v16
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.l, 0xff, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v98.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v14
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v100.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v17, v18
+; GFX11-TRUE16-NEXT:    v_and_b16 v16.l, 0xff, v23.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v37.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v97.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v15.l, v15.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v19, v20
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v24.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v96.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v25.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v87.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v16.l, v16.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v17.l, v17.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.l, 0xff, v25.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v36.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v21, v22
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v18.l, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v19.l, v19.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v16
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff, v17
+; GFX11-TRUE16-NEXT:    v_and_b16 v16.l, 0xff, v26.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v86.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v26.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v85.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v15.l, v15.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff, v19
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v16.l, v16.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v17.l, v17.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v15
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v27.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v84.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v27.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v16
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v20, v21
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, v22, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, v24, v25
+; GFX11-TRUE16-NEXT:    v_and_b16 v20.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v83.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v21.l, 0xff, v28.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.h, 8, v82.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v29.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v22.h, 8, v81.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v29.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.h, 8, v34.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v30.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v24.h, 8, v80.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v18.l, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v20.l, v20.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v21.l, v21.l, v21.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v22.l, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v23.l, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v24.l, v24.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v49.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v99.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v35.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v35, 0xffff, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v18, v26, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v20
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v21
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v27, 0xffff, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v23
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v29, 0xffff, v24
+; GFX11-TRUE16-NEXT:    v_and_b16 v20.l, 0xff, v30.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v71.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v21.l, 0xff, v31.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.h, 8, v70.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v31.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v22.h, 8, v33.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v32.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.h, 8, v69.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v32.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v24.h, 8, v68.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v14.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v19.l, v19.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v53, 0xffff, v64
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v65
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v20.l, v20.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v21.l, v21.l, v21.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v22.l, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v23.l, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v24.l, v24.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v53, v54
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v20
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff, v21
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v22
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v33, 0xffff, v23
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v39, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v38, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v19, v35, v19
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, v25, v26
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, v27, v28
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, v29, v30
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, v31, v32
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, v33, v24
+; GFX11-TRUE16-NEXT:    s_clause 0x5
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off offset:32
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:48
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[9:12], off offset:64
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[13:16], off offset:80
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[17:20], off offset:96
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[21:24], off offset:112
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v16i64_to_v128i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x13
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s32 offset:88
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v41, s32 offset:84
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v42, s32 offset:80
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v43, s32 offset:76
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v44, s32 offset:72
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v45, s32 offset:68
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v46, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v47, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v56, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v57, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v58, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v59, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v60, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v61, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v62, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v63, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v72, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v73, s32 offset:20
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v74, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v75, s32 offset:12
+; GFX11-FAKE16-NEXT:    s_clause 0x2
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v33, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr75
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr74
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr73
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr72
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr63
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr62
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr61
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr60
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr59
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr58
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr57
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr56
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr47
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr46
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr45
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr44
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr43
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr42
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr41
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr40
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr183
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr182
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr181
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr180
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr179
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr178
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr177
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr176
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr167
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr166
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr165
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr164
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr163
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr162
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr161
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr160
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr151
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr150
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr149
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr148
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr147
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr144
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr135
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB28_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[48:49], 24, v[19:20]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[49:50], 24, v[17:18]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[50:51], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[51:52], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[64:65], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[53:54], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[65:66], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v68, 24, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v69, 16, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v70, 8, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 16, v31
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 8, v31
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v81, 24, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v82, 16, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 8, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 16, v29
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v85, 8, v29
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v86, 24, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 16, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 8, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v97, 16, v27
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v98, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v99, 24, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v100, 16, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v101, 8, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v102, 16, v25
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v103, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v112, 24, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v113, 16, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v114, 8, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v115, 16, v23
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v116, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v117, 24, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v118, 16, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v119, 8, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v128, 16, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v129, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v130, 24, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v131, 16, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v132, 8, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v133, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v134, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v135, 24, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v144, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v145, 8, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v146, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v147, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v148, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v149, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v150, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v151, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v160, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v161, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v162, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v163, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v164, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v165, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v166, 24, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v167, 16, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v176, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v177, 16, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v178, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v179, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v180, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v181, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v182, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v183, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v40, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v41, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v42, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v43, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v44, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v45, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v46, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v47, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v56, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v57, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v58, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v59, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v60, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v61, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v62, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v63, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v72, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v73, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v74, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v75, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[54:55], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[66:67], 24, v[1:2]
+; GFX11-FAKE16-NEXT:  .LBB28_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB28_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v1, vcc_lo, v1, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v2, null, 0, v2, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v3, vcc_lo, v3, 3
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v4, null, 0, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v5, vcc_lo, v5, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v6, null, 0, v6, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v7, vcc_lo, v7, 3
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v8, null, 0, v8, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v9, vcc_lo, v9, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v10, null, 0, v10, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v11, vcc_lo, v11, 3
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v12, null, 0, v12, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v13, vcc_lo, v13, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v14, null, 0, v14, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v15, vcc_lo, v15, 3
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v16, null, 0, v16, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v17, vcc_lo, v17, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v18, null, 0, v18, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v19, vcc_lo, v19, 3
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v20, null, 0, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v21, vcc_lo, v21, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v22, null, 0, v22, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v25, vcc_lo, v25, 3
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v26, null, 0, v26, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v27, vcc_lo, v27, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v28, null, 0, v28, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v29, vcc_lo, v29, 3
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v30, null, 0, v30, vcc_lo
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v31, vcc_lo, v31, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v32, null, 0, v32, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v23, vcc_lo, v23, 3
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v24, null, 0, v24, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[48:49], 24, v[19:20]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[49:50], 24, v[17:18]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[50:51], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[51:52], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[64:65], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[53:54], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[65:66], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[54:55], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[66:67], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v68, 24, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v69, 16, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v70, 8, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 16, v31
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 8, v31
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v81, 24, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v82, 16, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 8, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 16, v29
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v85, 8, v29
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v86, 24, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 16, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 8, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v97, 16, v27
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v98, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v99, 24, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v100, 16, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v101, 8, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v102, 16, v25
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v103, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v112, 24, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v113, 16, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v114, 8, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v115, 16, v23
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v116, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v117, 24, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v118, 16, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v119, 8, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v128, 16, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v129, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v130, 24, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v131, 16, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v132, 8, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v133, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v134, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v135, 24, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v144, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v145, 8, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v146, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v147, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v148, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v149, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v150, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v151, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v160, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v161, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v162, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v163, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v164, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v165, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v166, 24, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v167, 16, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v176, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v177, 16, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v178, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v179, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v180, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v181, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v182, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v183, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v40, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v41, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v42, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v43, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v44, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v45, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v46, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v47, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v56, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v57, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v58, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v59, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v60, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v61, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v62, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v63, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v72, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v73, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v74, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v75, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB28_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v75
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v66
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v66, 8, v63
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v55, 0xff, v74
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v67, 0xff, v61
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v39, v55, v39
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v73
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v65, v67, v65
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v67, 8, v58
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v55, 0xff, v72
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v64, 8, v64
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, v55, v66
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v66, 8, v62
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v66
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v60
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v66, 0xff, v59
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v53, 8, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, v66, v67
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v57
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v66, 0xff, v56
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, v66, v64
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v64, 8, v47
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v65, 0xff, v46
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v66, 8, v45
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v64
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, v65, v66
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v64, 8, v44
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v65, 0xff, v43
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v64
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v54, v65, v54
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v42
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v64, 0xff, v41
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v40
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v39
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v54, v64, v65
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v64, 0xff, v182
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v183
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v181
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v53, v64, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v54
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v53
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v53, 0xff, v180
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v179
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v178
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v64, 0xff, v177
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v52, 8, v52
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v176
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v66, 0xff, v167
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v67, 8, v166
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v53, v53, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v52, v64, v52
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v54, v66, v67
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v53, 16, v53
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v52, 16, v52
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v54
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v9, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v10, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v11, v52
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v12, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v6, 8, v165
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v164
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v51
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v10, 8, v163
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v162
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v12, 8, v161
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v14, 8, v160
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v13, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v151
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v50
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v150
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v149
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v148
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v147
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v39, 0xff, v146
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v49, 8, v49
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v39, v49
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v13, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v145
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v144
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v135
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v134
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v133
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v48
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v132
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v18, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v131
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v130
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v18, 8, v129
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v128
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v38
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v119
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v38, 0xff, v118
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v117
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v19, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v21, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v38, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xffff, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v18, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v116
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v115
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v18, 8, v37
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v114
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v113
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v112
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v103
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v19, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v21, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v23, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v102
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v101
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v100
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v99
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v98
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v36, 0xff, v97
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v35, 8, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v36, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xffff, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v19, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v21, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v23, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v96
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v87
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v86
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v29
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v84
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v29, 8, v83
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v28, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v82
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v26, 8, v81
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v28, 8, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v71
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v30, 8, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v32, 8, v70
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xff, v69
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v34, 8, v68
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v27, v28
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v29, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v31, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v33, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xffff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xffff, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xffff, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xffff, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xffff, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v28, v29
+; GFX11-FAKE16-NEXT:    s_clause 0x5
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off offset:32
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:48
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[9:12], off offset:64
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[13:16], off offset:80
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[17:20], off offset:96
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[21:24], off offset:112
+; GFX11-FAKE16-NEXT:    s_clause 0x13
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v75, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v74, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v73, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v72, off, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v63, off, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v62, off, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v61, off, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v60, off, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v59, off, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v58, off, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v57, off, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v56, off, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v47, off, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v46, off, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v45, off, s32 offset:68
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v44, off, s32 offset:72
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v43, off, s32 offset:76
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v42, off, s32 offset:80
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v41, off, s32 offset:84
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s32 offset:88
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -41468,1038 +46175,1985 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v128i8_to_v16i64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_store_b32 off, v40, s32 offset:592
-; GFX11-NEXT:    scratch_store_b32 off, v41, s32 offset:588
-; GFX11-NEXT:    scratch_store_b32 off, v42, s32 offset:584
-; GFX11-NEXT:    scratch_store_b32 off, v43, s32 offset:580
-; GFX11-NEXT:    scratch_store_b32 off, v44, s32 offset:576
-; GFX11-NEXT:    scratch_store_b32 off, v45, s32 offset:572
-; GFX11-NEXT:    scratch_store_b32 off, v46, s32 offset:568
-; GFX11-NEXT:    scratch_store_b32 off, v47, s32 offset:564
-; GFX11-NEXT:    scratch_store_b32 off, v56, s32 offset:560
-; GFX11-NEXT:    scratch_store_b32 off, v57, s32 offset:556
-; GFX11-NEXT:    scratch_store_b32 off, v58, s32 offset:552
-; GFX11-NEXT:    scratch_store_b32 off, v59, s32 offset:548
-; GFX11-NEXT:    scratch_store_b32 off, v60, s32 offset:544
-; GFX11-NEXT:    scratch_store_b32 off, v61, s32 offset:540
-; GFX11-NEXT:    scratch_store_b32 off, v62, s32 offset:536
-; GFX11-NEXT:    scratch_store_b32 off, v63, s32 offset:532
-; GFX11-NEXT:    scratch_store_b32 off, v72, s32 offset:528
-; GFX11-NEXT:    scratch_store_b32 off, v73, s32 offset:524
-; GFX11-NEXT:    scratch_store_b32 off, v74, s32 offset:520
-; GFX11-NEXT:    scratch_store_b32 off, v75, s32 offset:516
-; GFX11-NEXT:    scratch_store_b32 off, v76, s32 offset:512
-; GFX11-NEXT:    scratch_store_b32 off, v77, s32 offset:508
-; GFX11-NEXT:    scratch_store_b32 off, v78, s32 offset:504
-; GFX11-NEXT:    scratch_store_b32 off, v79, s32 offset:500
-; GFX11-NEXT:    scratch_store_b32 off, v88, s32 offset:496
-; GFX11-NEXT:    scratch_store_b32 off, v89, s32 offset:492
-; GFX11-NEXT:    scratch_store_b32 off, v90, s32 offset:488
-; GFX11-NEXT:    scratch_store_b32 off, v91, s32 offset:484
-; GFX11-NEXT:    scratch_store_b32 off, v92, s32 offset:480
-; GFX11-NEXT:    scratch_store_b32 off, v93, s32 offset:476
-; GFX11-NEXT:    scratch_store_b32 off, v94, s32 offset:472
-; GFX11-NEXT:    scratch_store_b32 off, v95, s32 offset:468
-; GFX11-NEXT:    s_clause 0x12
-; GFX11-NEXT:    scratch_store_b32 off, v104, s32 offset:464
-; GFX11-NEXT:    scratch_store_b32 off, v105, s32 offset:460
-; GFX11-NEXT:    scratch_store_b32 off, v106, s32 offset:456
-; GFX11-NEXT:    scratch_store_b32 off, v107, s32 offset:452
-; GFX11-NEXT:    scratch_store_b32 off, v108, s32 offset:448
-; GFX11-NEXT:    scratch_store_b32 off, v109, s32 offset:444
-; GFX11-NEXT:    scratch_store_b32 off, v110, s32 offset:440
-; GFX11-NEXT:    scratch_store_b32 off, v111, s32 offset:436
-; GFX11-NEXT:    scratch_store_b32 off, v120, s32 offset:432
-; GFX11-NEXT:    scratch_store_b32 off, v121, s32 offset:428
-; GFX11-NEXT:    scratch_store_b32 off, v122, s32 offset:424
-; GFX11-NEXT:    scratch_store_b32 off, v123, s32 offset:420
-; GFX11-NEXT:    scratch_store_b32 off, v124, s32 offset:416
-; GFX11-NEXT:    scratch_store_b32 off, v125, s32 offset:412
-; GFX11-NEXT:    scratch_store_b32 off, v126, s32 offset:408
-; GFX11-NEXT:    scratch_store_b32 off, v127, s32 offset:404
-; GFX11-NEXT:    scratch_store_b32 off, v136, s32 offset:400
-; GFX11-NEXT:    scratch_store_b32 off, v137, s32 offset:396
-; GFX11-NEXT:    scratch_store_b32 off, v138, s32 offset:392
-; GFX11-NEXT:    v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28
-; GFX11-NEXT:    v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24
-; GFX11-NEXT:    v_dual_mov_b32 v36, v22 :: v_dual_mov_b32 v37, v20
-; GFX11-NEXT:    v_dual_mov_b32 v38, v18 :: v_dual_mov_b32 v39, v16
-; GFX11-NEXT:    v_dual_mov_b32 v48, v14 :: v_dual_mov_b32 v49, v12
-; GFX11-NEXT:    v_dual_mov_b32 v50, v10 :: v_dual_mov_b32 v51, v8
-; GFX11-NEXT:    v_dual_mov_b32 v52, v6 :: v_dual_mov_b32 v53, v4
-; GFX11-NEXT:    v_dual_mov_b32 v54, v2 :: v_dual_mov_b32 v55, v0
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v0, off, s32 offset:384
-; GFX11-NEXT:    scratch_load_u16 v64, off, s32 offset:380
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32 offset:376
-; GFX11-NEXT:    scratch_load_u16 v65, off, s32 offset:372
-; GFX11-NEXT:    scratch_load_u16 v4, off, s32 offset:368
-; GFX11-NEXT:    scratch_load_u16 v66, off, s32 offset:364
-; GFX11-NEXT:    scratch_load_u16 v6, off, s32 offset:360
-; GFX11-NEXT:    scratch_load_u16 v67, off, s32 offset:356
-; GFX11-NEXT:    scratch_load_u16 v8, off, s32 offset:352
-; GFX11-NEXT:    scratch_load_u16 v68, off, s32 offset:348
-; GFX11-NEXT:    scratch_load_u16 v10, off, s32 offset:344
-; GFX11-NEXT:    scratch_load_u16 v69, off, s32 offset:340
-; GFX11-NEXT:    scratch_load_u16 v12, off, s32 offset:336
-; GFX11-NEXT:    scratch_load_u16 v70, off, s32 offset:332
-; GFX11-NEXT:    scratch_load_u16 v14, off, s32 offset:328
-; GFX11-NEXT:    scratch_load_u16 v71, off, s32 offset:324
-; GFX11-NEXT:    scratch_load_u16 v16, off, s32 offset:320
-; GFX11-NEXT:    scratch_load_u16 v80, off, s32 offset:316
-; GFX11-NEXT:    scratch_load_u16 v18, off, s32 offset:312
-; GFX11-NEXT:    scratch_load_u16 v81, off, s32 offset:308
-; GFX11-NEXT:    scratch_load_u16 v20, off, s32 offset:304
-; GFX11-NEXT:    scratch_load_u16 v82, off, s32 offset:300
-; GFX11-NEXT:    scratch_load_u16 v22, off, s32 offset:296
-; GFX11-NEXT:    scratch_load_u16 v83, off, s32 offset:292
-; GFX11-NEXT:    scratch_load_u16 v24, off, s32 offset:288
-; GFX11-NEXT:    scratch_load_u16 v84, off, s32 offset:284
-; GFX11-NEXT:    scratch_load_u16 v26, off, s32 offset:280
-; GFX11-NEXT:    scratch_load_u16 v85, off, s32 offset:276
-; GFX11-NEXT:    scratch_load_u16 v28, off, s32 offset:272
-; GFX11-NEXT:    scratch_load_u16 v86, off, s32 offset:268
-; GFX11-NEXT:    scratch_load_u16 v30, off, s32 offset:264
-; GFX11-NEXT:    scratch_load_u16 v87, off, s32 offset:260
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v31, off, s32 offset:256
-; GFX11-NEXT:    scratch_load_u16 v96, off, s32 offset:252
-; GFX11-NEXT:    scratch_load_u16 v99, off, s32 offset:248
-; GFX11-NEXT:    scratch_load_u16 v97, off, s32 offset:244
-; GFX11-NEXT:    scratch_load_u16 v100, off, s32 offset:240
-; GFX11-NEXT:    scratch_load_u16 v98, off, s32 offset:236
-; GFX11-NEXT:    scratch_load_u16 v101, off, s32 offset:232
-; GFX11-NEXT:    scratch_load_u16 v112, off, s32 offset:228
-; GFX11-NEXT:    scratch_load_u16 v102, off, s32 offset:224
-; GFX11-NEXT:    scratch_load_u16 v113, off, s32 offset:220
-; GFX11-NEXT:    scratch_load_u16 v103, off, s32 offset:216
-; GFX11-NEXT:    scratch_load_b32 v114, off, s32 offset:388
-; GFX11-NEXT:    scratch_load_u16 v115, off, s32
-; GFX11-NEXT:    scratch_load_u16 v116, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_u16 v117, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_u16 v118, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_u16 v119, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_u16 v128, off, s32 offset:40
-; GFX11-NEXT:    scratch_load_u16 v129, off, s32 offset:48
-; GFX11-NEXT:    scratch_load_u16 v130, off, s32 offset:56
-; GFX11-NEXT:    scratch_load_u16 v131, off, s32 offset:64
-; GFX11-NEXT:    scratch_load_u16 v144, off, s32 offset:72
-; GFX11-NEXT:    scratch_load_u16 v145, off, s32 offset:80
-; GFX11-NEXT:    scratch_load_u16 v146, off, s32 offset:88
-; GFX11-NEXT:    scratch_load_u16 v147, off, s32 offset:96
-; GFX11-NEXT:    scratch_load_u16 v148, off, s32 offset:104
-; GFX11-NEXT:    scratch_load_u16 v162, off, s32 offset:112
-; GFX11-NEXT:    scratch_load_u16 v163, off, s32 offset:120
-; GFX11-NEXT:    scratch_load_u16 v164, off, s32 offset:128
-; GFX11-NEXT:    scratch_load_u16 v165, off, s32 offset:136
-; GFX11-NEXT:    scratch_load_u16 v166, off, s32 offset:144
-; GFX11-NEXT:    scratch_load_u16 v179, off, s32 offset:152
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v180, off, s32 offset:160
-; GFX11-NEXT:    scratch_load_u16 v181, off, s32 offset:168
-; GFX11-NEXT:    scratch_load_u16 v182, off, s32 offset:176
-; GFX11-NEXT:    scratch_load_u16 v183, off, s32 offset:184
-; GFX11-NEXT:    scratch_load_u16 v136, off, s32 offset:192
-; GFX11-NEXT:    scratch_load_u16 v137, off, s32 offset:200
-; GFX11-NEXT:    scratch_load_u16 v138, off, s32 offset:208
-; GFX11-NEXT:    scratch_load_u16 v132, off, s32 offset:212
-; GFX11-NEXT:    scratch_load_u16 v133, off, s32 offset:204
-; GFX11-NEXT:    scratch_load_u16 v134, off, s32 offset:196
-; GFX11-NEXT:    scratch_load_u16 v135, off, s32 offset:188
-; GFX11-NEXT:    scratch_load_u16 v149, off, s32 offset:180
-; GFX11-NEXT:    scratch_load_u16 v150, off, s32 offset:172
-; GFX11-NEXT:    scratch_load_u16 v151, off, s32 offset:164
-; GFX11-NEXT:    scratch_load_u16 v160, off, s32 offset:156
-; GFX11-NEXT:    scratch_load_u16 v161, off, s32 offset:148
-; GFX11-NEXT:    scratch_load_u16 v167, off, s32 offset:140
-; GFX11-NEXT:    scratch_load_u16 v176, off, s32 offset:132
-; GFX11-NEXT:    scratch_load_u16 v177, off, s32 offset:124
-; GFX11-NEXT:    scratch_load_u16 v178, off, s32 offset:116
-; GFX11-NEXT:    scratch_load_u16 v40, off, s32 offset:108
-; GFX11-NEXT:    scratch_load_u16 v41, off, s32 offset:100
-; GFX11-NEXT:    scratch_load_u16 v42, off, s32 offset:92
-; GFX11-NEXT:    scratch_load_u16 v43, off, s32 offset:84
-; GFX11-NEXT:    scratch_load_u16 v44, off, s32 offset:76
-; GFX11-NEXT:    scratch_load_u16 v58, off, s32 offset:68
-; GFX11-NEXT:    scratch_load_u16 v59, off, s32 offset:60
-; GFX11-NEXT:    scratch_load_u16 v60, off, s32 offset:52
-; GFX11-NEXT:    scratch_load_u16 v74, off, s32 offset:44
-; GFX11-NEXT:    scratch_load_u16 v75, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_u16 v76, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_u16 v77, off, s32 offset:20
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_u16 v78, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_u16 v92, off, s32 offset:4
-; GFX11-NEXT:    v_lshlrev_b16 v124, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v125, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v126, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v127, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v111, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v120, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v121, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v122, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v123, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v106, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v107, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v108, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v109, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v110, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v93, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(54)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v114
-; GFX11-NEXT:    s_waitcnt vmcnt(53)
-; GFX11-NEXT:    v_lshlrev_b16 v94, 8, v115
-; GFX11-NEXT:    s_waitcnt vmcnt(52)
-; GFX11-NEXT:    v_lshlrev_b16 v95, 8, v116
-; GFX11-NEXT:    s_waitcnt vmcnt(51)
-; GFX11-NEXT:    v_lshlrev_b16 v104, 8, v117
-; GFX11-NEXT:    s_waitcnt vmcnt(50)
-; GFX11-NEXT:    v_lshlrev_b16 v105, 8, v118
-; GFX11-NEXT:    s_waitcnt vmcnt(49)
-; GFX11-NEXT:    v_lshlrev_b16 v79, 8, v119
-; GFX11-NEXT:    s_waitcnt vmcnt(48)
-; GFX11-NEXT:    v_lshlrev_b16 v88, 8, v128
-; GFX11-NEXT:    s_waitcnt vmcnt(47)
-; GFX11-NEXT:    v_lshlrev_b16 v89, 8, v129
-; GFX11-NEXT:    s_waitcnt vmcnt(46)
-; GFX11-NEXT:    v_lshlrev_b16 v90, 8, v130
-; GFX11-NEXT:    s_waitcnt vmcnt(45)
-; GFX11-NEXT:    v_lshlrev_b16 v91, 8, v131
-; GFX11-NEXT:    s_waitcnt vmcnt(44)
-; GFX11-NEXT:    v_lshlrev_b16 v61, 8, v144
-; GFX11-NEXT:    s_waitcnt vmcnt(43)
-; GFX11-NEXT:    v_lshlrev_b16 v62, 8, v145
-; GFX11-NEXT:    s_waitcnt vmcnt(42)
-; GFX11-NEXT:    v_lshlrev_b16 v63, 8, v146
-; GFX11-NEXT:    s_waitcnt vmcnt(41)
-; GFX11-NEXT:    v_lshlrev_b16 v72, 8, v147
-; GFX11-NEXT:    s_waitcnt vmcnt(40)
-; GFX11-NEXT:    v_lshlrev_b16 v73, 8, v148
-; GFX11-NEXT:    s_waitcnt vmcnt(39)
-; GFX11-NEXT:    v_lshlrev_b16 v45, 8, v162
-; GFX11-NEXT:    s_waitcnt vmcnt(38)
-; GFX11-NEXT:    v_lshlrev_b16 v46, 8, v163
-; GFX11-NEXT:    s_waitcnt vmcnt(37)
-; GFX11-NEXT:    v_lshlrev_b16 v47, 8, v164
-; GFX11-NEXT:    s_waitcnt vmcnt(36)
-; GFX11-NEXT:    v_lshlrev_b16 v56, 8, v165
-; GFX11-NEXT:    s_waitcnt vmcnt(35)
-; GFX11-NEXT:    v_lshlrev_b16 v57, 8, v166
-; GFX11-NEXT:    s_waitcnt vmcnt(34)
-; GFX11-NEXT:    v_lshlrev_b16 v179, 8, v179
-; GFX11-NEXT:    s_waitcnt vmcnt(33)
-; GFX11-NEXT:    v_lshlrev_b16 v180, 8, v180
-; GFX11-NEXT:    s_waitcnt vmcnt(32)
-; GFX11-NEXT:    v_lshlrev_b16 v181, 8, v181
-; GFX11-NEXT:    s_waitcnt vmcnt(31)
-; GFX11-NEXT:    v_lshlrev_b16 v182, 8, v182
-; GFX11-NEXT:    s_waitcnt vmcnt(30)
-; GFX11-NEXT:    v_lshlrev_b16 v183, 8, v183
-; GFX11-NEXT:    s_waitcnt vmcnt(29)
-; GFX11-NEXT:    v_lshlrev_b16 v162, 8, v136
-; GFX11-NEXT:    s_waitcnt vmcnt(28)
-; GFX11-NEXT:    v_lshlrev_b16 v163, 8, v137
-; GFX11-NEXT:    s_waitcnt vmcnt(27)
-; GFX11-NEXT:    v_lshlrev_b16 v164, 8, v138
-; GFX11-NEXT:    v_lshlrev_b16 v165, 8, v103
-; GFX11-NEXT:    v_lshlrev_b16 v166, 8, v102
-; GFX11-NEXT:    v_lshlrev_b16 v144, 8, v101
-; GFX11-NEXT:    v_lshlrev_b16 v145, 8, v100
-; GFX11-NEXT:    v_lshlrev_b16 v146, 8, v99
-; GFX11-NEXT:    v_lshlrev_b16 v147, 8, v31
-; GFX11-NEXT:    v_lshlrev_b16 v148, 8, v30
-; GFX11-NEXT:    v_lshlrev_b16 v119, 8, v28
-; GFX11-NEXT:    v_lshlrev_b16 v128, 8, v26
-; GFX11-NEXT:    v_lshlrev_b16 v129, 8, v24
-; GFX11-NEXT:    v_lshlrev_b16 v130, 8, v22
-; GFX11-NEXT:    v_lshlrev_b16 v131, 8, v20
-; GFX11-NEXT:    v_lshlrev_b16 v114, 8, v18
-; GFX11-NEXT:    v_lshlrev_b16 v115, 8, v16
-; GFX11-NEXT:    v_lshlrev_b16 v116, 8, v14
-; GFX11-NEXT:    v_lshlrev_b16 v117, 8, v12
-; GFX11-NEXT:    v_lshlrev_b16 v118, 8, v10
-; GFX11-NEXT:    v_lshlrev_b16 v99, 8, v8
-; GFX11-NEXT:    v_lshlrev_b16 v100, 8, v6
-; GFX11-NEXT:    v_lshlrev_b16 v101, 8, v4
-; GFX11-NEXT:    v_lshlrev_b16 v102, 8, v2
-; GFX11-NEXT:    v_lshlrev_b16 v103, 8, v0
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB29_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v55
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v54
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v53
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v52
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v51
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v124
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v125
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v126
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v127
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v50
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v39
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v37
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v36
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v49
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v48
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v35
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v34
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v111
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v121
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v120
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v122
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v123
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v107
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v2
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v38
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v108
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v109
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v110
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v106
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v3, v7, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v6, v12
-; GFX11-NEXT:    v_or_b32_e32 v5, v8, v9
-; GFX11-NEXT:    v_or_b32_e32 v6, v10, v11
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v32
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v92
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v78
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v77
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v76
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v75
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v74
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v60
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v59
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v93
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v94
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v95
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v104
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v105
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v79
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v88
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v89
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v90
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v91
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v8, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v9, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v10, v13, v14
-; GFX11-NEXT:    v_or_b32_e32 v11, v15, v16
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v58
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v44
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v43
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v42
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v41
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v40
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v178
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v177
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v176
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v167
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v61
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v62
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v63
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v72
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v73
-; GFX11-NEXT:    v_or_b32_e32 v17, v17, v45
-; GFX11-NEXT:    v_or_b32_e32 v18, v18, v46
-; GFX11-NEXT:    v_or_b32_e32 v19, v19, v47
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v56
-; GFX11-NEXT:    v_or_b32_e32 v21, v21, v57
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xffff, v18
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xffff, v20
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v13, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v14, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v15, v18, v19
-; GFX11-NEXT:    v_or_b32_e32 v16, v20, v21
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v161
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v160
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v151
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v150
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v149
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v135
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v134
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v133
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v132
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v113
-; GFX11-NEXT:    v_or_b32_e32 v17, v17, v179
-; GFX11-NEXT:    v_or_b32_e32 v18, v18, v180
-; GFX11-NEXT:    v_or_b32_e32 v19, v19, v181
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v182
-; GFX11-NEXT:    v_or_b32_e32 v21, v21, v183
-; GFX11-NEXT:    v_or_b32_e32 v22, v22, v162
-; GFX11-NEXT:    v_or_b32_e32 v23, v23, v163
-; GFX11-NEXT:    v_or_b32_e32 v24, v24, v164
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v165
-; GFX11-NEXT:    v_or_b32_e32 v26, v26, v166
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff, v19
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xffff, v21
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xffff, v23
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xffff, v25
-; GFX11-NEXT:    v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-NEXT:    v_or_b32_e32 v17, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v18, v19, v20
-; GFX11-NEXT:    v_or_b32_e32 v19, v21, v22
-; GFX11-NEXT:    v_or_b32_e32 v20, v23, v24
-; GFX11-NEXT:    v_or_b32_e32 v21, v25, v26
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v112
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v98
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v97
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v96
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v87
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v86
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v85
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v84
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v83
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v82
-; GFX11-NEXT:    v_or_b32_e32 v22, v22, v144
-; GFX11-NEXT:    v_or_b32_e32 v23, v23, v145
-; GFX11-NEXT:    v_or_b32_e32 v24, v24, v146
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v147
-; GFX11-NEXT:    v_or_b32_e32 v26, v26, v148
-; GFX11-NEXT:    v_or_b32_e32 v27, v27, v119
-; GFX11-NEXT:    v_or_b32_e32 v28, v28, v128
-; GFX11-NEXT:    v_or_b32_e32 v29, v29, v129
-; GFX11-NEXT:    v_or_b32_e32 v30, v30, v130
-; GFX11-NEXT:    v_or_b32_e32 v31, v31, v131
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xffff, v22
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xffff, v24
-; GFX11-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xffff, v26
-; GFX11-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xffff, v28
-; GFX11-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xffff, v30
-; GFX11-NEXT:    v_lshlrev_b32_e32 v31, 16, v31
-; GFX11-NEXT:    v_or_b32_e32 v22, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v23, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v24, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v25, v28, v29
-; GFX11-NEXT:    v_or_b32_e32 v26, v30, v31
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v81
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v80
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v71
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v70
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v69
-; GFX11-NEXT:    v_and_b32_e32 v32, 0xff, v68
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xff, v67
-; GFX11-NEXT:    v_and_b32_e32 v34, 0xff, v66
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xff, v65
-; GFX11-NEXT:    v_and_b32_e32 v36, 0xff, v64
-; GFX11-NEXT:    v_or_b32_e32 v27, v27, v114
-; GFX11-NEXT:    v_or_b32_e32 v28, v28, v115
-; GFX11-NEXT:    v_or_b32_e32 v29, v29, v116
-; GFX11-NEXT:    v_or_b32_e32 v30, v30, v117
-; GFX11-NEXT:    v_or_b32_e32 v31, v31, v118
-; GFX11-NEXT:    v_or_b32_e32 v32, v32, v99
-; GFX11-NEXT:    v_or_b32_e32 v33, v33, v100
-; GFX11-NEXT:    v_or_b32_e32 v34, v34, v101
-; GFX11-NEXT:    v_or_b32_e32 v35, v35, v102
-; GFX11-NEXT:    v_or_b32_e32 v36, v36, v103
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xffff, v27
-; GFX11-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xffff, v29
-; GFX11-NEXT:    v_lshlrev_b32_e32 v30, 16, v30
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xffff, v31
-; GFX11-NEXT:    v_lshlrev_b32_e32 v32, 16, v32
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xffff, v33
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v34
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xffff, v35
-; GFX11-NEXT:    v_lshlrev_b32_e32 v36, 16, v36
-; GFX11-NEXT:    v_or_b32_e32 v27, v27, v28
-; GFX11-NEXT:    v_or_b32_e32 v28, v29, v30
-; GFX11-NEXT:    v_or_b32_e32 v29, v31, v32
-; GFX11-NEXT:    v_or_b32_e32 v30, v33, v34
-; GFX11-NEXT:    v_or_b32_e32 v31, v35, v36
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr92
-; GFX11-NEXT:    ; implicit-def: $vgpr78
-; GFX11-NEXT:    ; implicit-def: $vgpr77
-; GFX11-NEXT:    ; implicit-def: $vgpr76
-; GFX11-NEXT:    ; implicit-def: $vgpr75
-; GFX11-NEXT:    ; implicit-def: $vgpr74
-; GFX11-NEXT:    ; implicit-def: $vgpr60
-; GFX11-NEXT:    ; implicit-def: $vgpr59
-; GFX11-NEXT:    ; implicit-def: $vgpr58
-; GFX11-NEXT:    ; implicit-def: $vgpr44
-; GFX11-NEXT:    ; implicit-def: $vgpr43
-; GFX11-NEXT:    ; implicit-def: $vgpr42
-; GFX11-NEXT:    ; implicit-def: $vgpr41
-; GFX11-NEXT:    ; implicit-def: $vgpr40
-; GFX11-NEXT:    ; implicit-def: $vgpr178
-; GFX11-NEXT:    ; implicit-def: $vgpr177
-; GFX11-NEXT:    ; implicit-def: $vgpr176
-; GFX11-NEXT:    ; implicit-def: $vgpr167
-; GFX11-NEXT:    ; implicit-def: $vgpr161
-; GFX11-NEXT:    ; implicit-def: $vgpr160
-; GFX11-NEXT:    ; implicit-def: $vgpr151
-; GFX11-NEXT:    ; implicit-def: $vgpr150
-; GFX11-NEXT:    ; implicit-def: $vgpr149
-; GFX11-NEXT:    ; implicit-def: $vgpr135
-; GFX11-NEXT:    ; implicit-def: $vgpr134
-; GFX11-NEXT:    ; implicit-def: $vgpr133
-; GFX11-NEXT:    ; implicit-def: $vgpr132
-; GFX11-NEXT:    ; implicit-def: $vgpr113
-; GFX11-NEXT:    ; implicit-def: $vgpr112
-; GFX11-NEXT:    ; implicit-def: $vgpr98
-; GFX11-NEXT:    ; implicit-def: $vgpr97
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr67
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr124
-; GFX11-NEXT:    ; implicit-def: $vgpr125
-; GFX11-NEXT:    ; implicit-def: $vgpr126
-; GFX11-NEXT:    ; implicit-def: $vgpr127
-; GFX11-NEXT:    ; implicit-def: $vgpr111
-; GFX11-NEXT:    ; implicit-def: $vgpr120
-; GFX11-NEXT:    ; implicit-def: $vgpr121
-; GFX11-NEXT:    ; implicit-def: $vgpr122
-; GFX11-NEXT:    ; implicit-def: $vgpr123
-; GFX11-NEXT:    ; implicit-def: $vgpr106
-; GFX11-NEXT:    ; implicit-def: $vgpr107
-; GFX11-NEXT:    ; implicit-def: $vgpr108
-; GFX11-NEXT:    ; implicit-def: $vgpr109
-; GFX11-NEXT:    ; implicit-def: $vgpr110
-; GFX11-NEXT:    ; implicit-def: $vgpr93
-; GFX11-NEXT:    ; implicit-def: $vgpr94
-; GFX11-NEXT:    ; implicit-def: $vgpr95
-; GFX11-NEXT:    ; implicit-def: $vgpr104
-; GFX11-NEXT:    ; implicit-def: $vgpr105
-; GFX11-NEXT:    ; implicit-def: $vgpr79
-; GFX11-NEXT:    ; implicit-def: $vgpr88
-; GFX11-NEXT:    ; implicit-def: $vgpr89
-; GFX11-NEXT:    ; implicit-def: $vgpr90
-; GFX11-NEXT:    ; implicit-def: $vgpr91
-; GFX11-NEXT:    ; implicit-def: $vgpr61
-; GFX11-NEXT:    ; implicit-def: $vgpr62
-; GFX11-NEXT:    ; implicit-def: $vgpr63
-; GFX11-NEXT:    ; implicit-def: $vgpr72
-; GFX11-NEXT:    ; implicit-def: $vgpr73
-; GFX11-NEXT:    ; implicit-def: $vgpr45
-; GFX11-NEXT:    ; implicit-def: $vgpr46
-; GFX11-NEXT:    ; implicit-def: $vgpr47
-; GFX11-NEXT:    ; implicit-def: $vgpr56
-; GFX11-NEXT:    ; implicit-def: $vgpr57
-; GFX11-NEXT:    ; implicit-def: $vgpr179
-; GFX11-NEXT:    ; implicit-def: $vgpr180
-; GFX11-NEXT:    ; implicit-def: $vgpr181
-; GFX11-NEXT:    ; implicit-def: $vgpr182
-; GFX11-NEXT:    ; implicit-def: $vgpr183
-; GFX11-NEXT:    ; implicit-def: $vgpr162
-; GFX11-NEXT:    ; implicit-def: $vgpr163
-; GFX11-NEXT:    ; implicit-def: $vgpr164
-; GFX11-NEXT:    ; implicit-def: $vgpr165
-; GFX11-NEXT:    ; implicit-def: $vgpr166
-; GFX11-NEXT:    ; implicit-def: $vgpr144
-; GFX11-NEXT:    ; implicit-def: $vgpr145
-; GFX11-NEXT:    ; implicit-def: $vgpr146
-; GFX11-NEXT:    ; implicit-def: $vgpr147
-; GFX11-NEXT:    ; implicit-def: $vgpr148
-; GFX11-NEXT:    ; implicit-def: $vgpr119
-; GFX11-NEXT:    ; implicit-def: $vgpr128
-; GFX11-NEXT:    ; implicit-def: $vgpr129
-; GFX11-NEXT:    ; implicit-def: $vgpr130
-; GFX11-NEXT:    ; implicit-def: $vgpr131
-; GFX11-NEXT:    ; implicit-def: $vgpr114
-; GFX11-NEXT:    ; implicit-def: $vgpr115
-; GFX11-NEXT:    ; implicit-def: $vgpr116
-; GFX11-NEXT:    ; implicit-def: $vgpr117
-; GFX11-NEXT:    ; implicit-def: $vgpr118
-; GFX11-NEXT:    ; implicit-def: $vgpr99
-; GFX11-NEXT:    ; implicit-def: $vgpr100
-; GFX11-NEXT:    ; implicit-def: $vgpr101
-; GFX11-NEXT:    ; implicit-def: $vgpr102
-; GFX11-NEXT:    ; implicit-def: $vgpr103
-; GFX11-NEXT:  .LBB29_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB29_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v55, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v54, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v53, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v52, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v51, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_add_nc_u16 v5, v50, 3
-; GFX11-NEXT:    v_or_b32_e32 v0, v124, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v125, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v126, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v127, v3
-; GFX11-NEXT:    v_add_nc_u16 v6, v49, 3
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v7, v48, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_add_nc_u16 v8, v37, 3
-; GFX11-NEXT:    v_add_nc_u16 v9, v36, 3
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_add_nc_u16 v10, v35, 3
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_add_nc_u16 v2, v39, 3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v5
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v11, v34, 3
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v2, v123, v2
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_or_b32_e32 v3, v111, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v120, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v121, v5
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v6, v122, v6
-; GFX11-NEXT:    v_or_b32_e32 v8, v107, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v108, v9
-; GFX11-NEXT:    v_or_b32_e32 v10, v109, v10
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v38, 3
-; GFX11-NEXT:    v_or_b32_e32 v11, v110, v11
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v10
-; GFX11-NEXT:    v_or_b32_e32 v2, v106, v2
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v11
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_or_b32_e32 v2, v3, v4
-; GFX11-NEXT:    v_or_b32_e32 v3, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v5, v8, v9
-; GFX11-NEXT:    v_or_b32_e32 v4, v7, v12
-; GFX11-NEXT:    v_or_b32_e32 v6, v10, v11
-; GFX11-NEXT:    v_add_nc_u16 v7, v33, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v32, 3
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_nc_u16 v9, v92, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, v78, 3
-; GFX11-NEXT:    v_add_nc_u16 v11, v77, 3
-; GFX11-NEXT:    v_add_nc_u16 v12, v76, 3
-; GFX11-NEXT:    v_add_nc_u16 v13, v75, 3
-; GFX11-NEXT:    v_add_nc_u16 v14, v74, 3
-; GFX11-NEXT:    v_add_nc_u16 v15, v60, 3
-; GFX11-NEXT:    v_add_nc_u16 v16, v59, 3
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_or_b32_e32 v7, v93, v7
-; GFX11-NEXT:    v_or_b32_e32 v8, v94, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v95, v9
-; GFX11-NEXT:    v_or_b32_e32 v10, v104, v10
-; GFX11-NEXT:    v_or_b32_e32 v11, v105, v11
-; GFX11-NEXT:    v_or_b32_e32 v12, v79, v12
-; GFX11-NEXT:    v_or_b32_e32 v13, v88, v13
-; GFX11-NEXT:    v_or_b32_e32 v14, v89, v14
-; GFX11-NEXT:    v_or_b32_e32 v15, v90, v15
-; GFX11-NEXT:    v_or_b32_e32 v16, v91, v16
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v10
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v11
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v12
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v13
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v14
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v15
-; GFX11-NEXT:    v_add_nc_u16 v16, 0x300, v16
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v8, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v9, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v10, v13, v14
-; GFX11-NEXT:    v_or_b32_e32 v11, v15, v16
-; GFX11-NEXT:    v_add_nc_u16 v12, v58, 3
-; GFX11-NEXT:    v_add_nc_u16 v13, v44, 3
-; GFX11-NEXT:    v_add_nc_u16 v14, v43, 3
-; GFX11-NEXT:    v_add_nc_u16 v15, v42, 3
-; GFX11-NEXT:    v_add_nc_u16 v16, v41, 3
-; GFX11-NEXT:    v_add_nc_u16 v17, v40, 3
-; GFX11-NEXT:    v_add_nc_u16 v18, v178, 3
-; GFX11-NEXT:    v_add_nc_u16 v19, v177, 3
-; GFX11-NEXT:    v_add_nc_u16 v20, v176, 3
-; GFX11-NEXT:    v_add_nc_u16 v21, v167, 3
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v17
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v19
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v21
-; GFX11-NEXT:    v_or_b32_e32 v12, v61, v12
-; GFX11-NEXT:    v_or_b32_e32 v13, v62, v13
-; GFX11-NEXT:    v_or_b32_e32 v14, v63, v14
-; GFX11-NEXT:    v_or_b32_e32 v15, v72, v15
-; GFX11-NEXT:    v_or_b32_e32 v16, v73, v16
-; GFX11-NEXT:    v_or_b32_e32 v17, v45, v17
-; GFX11-NEXT:    v_or_b32_e32 v18, v46, v18
-; GFX11-NEXT:    v_or_b32_e32 v19, v47, v19
-; GFX11-NEXT:    v_or_b32_e32 v20, v56, v20
-; GFX11-NEXT:    v_or_b32_e32 v21, v57, v21
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v12
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v13
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v14
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v15
-; GFX11-NEXT:    v_add_nc_u16 v16, 0x300, v16
-; GFX11-NEXT:    v_add_nc_u16 v17, 0x300, v17
-; GFX11-NEXT:    v_add_nc_u16 v18, 0x300, v18
-; GFX11-NEXT:    v_add_nc_u16 v19, 0x300, v19
-; GFX11-NEXT:    v_add_nc_u16 v20, 0x300, v20
-; GFX11-NEXT:    v_add_nc_u16 v21, 0x300, v21
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xffff, v18
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xffff, v20
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v13, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v14, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v15, v18, v19
-; GFX11-NEXT:    v_or_b32_e32 v16, v20, v21
-; GFX11-NEXT:    v_add_nc_u16 v17, v161, 3
-; GFX11-NEXT:    v_add_nc_u16 v18, v160, 3
-; GFX11-NEXT:    v_add_nc_u16 v19, v151, 3
-; GFX11-NEXT:    v_add_nc_u16 v20, v150, 3
-; GFX11-NEXT:    v_add_nc_u16 v21, v149, 3
-; GFX11-NEXT:    v_add_nc_u16 v22, v135, 3
-; GFX11-NEXT:    v_add_nc_u16 v23, v134, 3
-; GFX11-NEXT:    v_add_nc_u16 v24, v133, 3
-; GFX11-NEXT:    v_add_nc_u16 v25, v132, 3
-; GFX11-NEXT:    v_add_nc_u16 v26, v113, 3
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v17
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v19
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v21
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v23
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v24
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v25
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v26
-; GFX11-NEXT:    v_or_b32_e32 v17, v179, v17
-; GFX11-NEXT:    v_or_b32_e32 v18, v180, v18
-; GFX11-NEXT:    v_or_b32_e32 v19, v181, v19
-; GFX11-NEXT:    v_or_b32_e32 v20, v182, v20
-; GFX11-NEXT:    v_or_b32_e32 v21, v183, v21
-; GFX11-NEXT:    v_or_b32_e32 v22, v162, v22
-; GFX11-NEXT:    v_or_b32_e32 v23, v163, v23
-; GFX11-NEXT:    v_or_b32_e32 v24, v164, v24
-; GFX11-NEXT:    v_or_b32_e32 v25, v165, v25
-; GFX11-NEXT:    v_or_b32_e32 v26, v166, v26
-; GFX11-NEXT:    v_add_nc_u16 v17, 0x300, v17
-; GFX11-NEXT:    v_add_nc_u16 v18, 0x300, v18
-; GFX11-NEXT:    v_add_nc_u16 v19, 0x300, v19
-; GFX11-NEXT:    v_add_nc_u16 v20, 0x300, v20
-; GFX11-NEXT:    v_add_nc_u16 v21, 0x300, v21
-; GFX11-NEXT:    v_add_nc_u16 v22, 0x300, v22
-; GFX11-NEXT:    v_add_nc_u16 v23, 0x300, v23
-; GFX11-NEXT:    v_add_nc_u16 v24, 0x300, v24
-; GFX11-NEXT:    v_add_nc_u16 v25, 0x300, v25
-; GFX11-NEXT:    v_add_nc_u16 v26, 0x300, v26
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff, v19
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xffff, v21
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xffff, v23
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xffff, v25
-; GFX11-NEXT:    v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-NEXT:    v_or_b32_e32 v17, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v18, v19, v20
-; GFX11-NEXT:    v_or_b32_e32 v19, v21, v22
-; GFX11-NEXT:    v_or_b32_e32 v20, v23, v24
-; GFX11-NEXT:    v_or_b32_e32 v21, v25, v26
-; GFX11-NEXT:    v_add_nc_u16 v22, v112, 3
-; GFX11-NEXT:    v_add_nc_u16 v23, v98, 3
-; GFX11-NEXT:    v_add_nc_u16 v24, v97, 3
-; GFX11-NEXT:    v_add_nc_u16 v25, v96, 3
-; GFX11-NEXT:    v_add_nc_u16 v26, v87, 3
-; GFX11-NEXT:    v_add_nc_u16 v27, v86, 3
-; GFX11-NEXT:    v_add_nc_u16 v28, v85, 3
-; GFX11-NEXT:    v_add_nc_u16 v29, v84, 3
-; GFX11-NEXT:    v_add_nc_u16 v30, v83, 3
-; GFX11-NEXT:    v_add_nc_u16 v31, v82, 3
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v23
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v24
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v25
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v26
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v27
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v29
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v30
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v31
-; GFX11-NEXT:    v_or_b32_e32 v22, v144, v22
-; GFX11-NEXT:    v_or_b32_e32 v23, v145, v23
-; GFX11-NEXT:    v_or_b32_e32 v24, v146, v24
-; GFX11-NEXT:    v_or_b32_e32 v25, v147, v25
-; GFX11-NEXT:    v_or_b32_e32 v26, v148, v26
-; GFX11-NEXT:    v_or_b32_e32 v27, v119, v27
-; GFX11-NEXT:    v_or_b32_e32 v28, v128, v28
-; GFX11-NEXT:    v_or_b32_e32 v29, v129, v29
-; GFX11-NEXT:    v_or_b32_e32 v30, v130, v30
-; GFX11-NEXT:    v_or_b32_e32 v31, v131, v31
-; GFX11-NEXT:    v_add_nc_u16 v22, 0x300, v22
-; GFX11-NEXT:    v_add_nc_u16 v23, 0x300, v23
-; GFX11-NEXT:    v_add_nc_u16 v24, 0x300, v24
-; GFX11-NEXT:    v_add_nc_u16 v25, 0x300, v25
-; GFX11-NEXT:    v_add_nc_u16 v26, 0x300, v26
-; GFX11-NEXT:    v_add_nc_u16 v27, 0x300, v27
-; GFX11-NEXT:    v_add_nc_u16 v28, 0x300, v28
-; GFX11-NEXT:    v_add_nc_u16 v29, 0x300, v29
-; GFX11-NEXT:    v_add_nc_u16 v30, 0x300, v30
-; GFX11-NEXT:    v_add_nc_u16 v31, 0x300, v31
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xffff, v22
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xffff, v24
-; GFX11-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xffff, v26
-; GFX11-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xffff, v28
-; GFX11-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xffff, v30
-; GFX11-NEXT:    v_lshlrev_b32_e32 v31, 16, v31
-; GFX11-NEXT:    v_or_b32_e32 v22, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v23, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v24, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v25, v28, v29
-; GFX11-NEXT:    v_or_b32_e32 v26, v30, v31
-; GFX11-NEXT:    v_add_nc_u16 v27, v81, 3
-; GFX11-NEXT:    v_add_nc_u16 v28, v80, 3
-; GFX11-NEXT:    v_add_nc_u16 v29, v71, 3
-; GFX11-NEXT:    v_add_nc_u16 v30, v70, 3
-; GFX11-NEXT:    v_add_nc_u16 v31, v69, 3
-; GFX11-NEXT:    v_add_nc_u16 v32, v68, 3
-; GFX11-NEXT:    v_add_nc_u16 v33, v67, 3
-; GFX11-NEXT:    v_add_nc_u16 v34, v66, 3
-; GFX11-NEXT:    v_add_nc_u16 v35, v65, 3
-; GFX11-NEXT:    v_add_nc_u16 v36, v64, 3
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v27
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v29
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v30
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v31
-; GFX11-NEXT:    v_and_b32_e32 v32, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v34, 0xff, v34
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xff, v35
-; GFX11-NEXT:    v_and_b32_e32 v36, 0xff, v36
-; GFX11-NEXT:    v_or_b32_e32 v27, v114, v27
-; GFX11-NEXT:    v_or_b32_e32 v28, v115, v28
-; GFX11-NEXT:    v_or_b32_e32 v29, v116, v29
-; GFX11-NEXT:    v_or_b32_e32 v30, v117, v30
-; GFX11-NEXT:    v_or_b32_e32 v31, v118, v31
-; GFX11-NEXT:    v_or_b32_e32 v32, v99, v32
-; GFX11-NEXT:    v_or_b32_e32 v33, v100, v33
-; GFX11-NEXT:    v_or_b32_e32 v34, v101, v34
-; GFX11-NEXT:    v_or_b32_e32 v35, v102, v35
-; GFX11-NEXT:    v_or_b32_e32 v36, v103, v36
-; GFX11-NEXT:    v_add_nc_u16 v27, 0x300, v27
-; GFX11-NEXT:    v_add_nc_u16 v28, 0x300, v28
-; GFX11-NEXT:    v_add_nc_u16 v29, 0x300, v29
-; GFX11-NEXT:    v_add_nc_u16 v30, 0x300, v30
-; GFX11-NEXT:    v_add_nc_u16 v31, 0x300, v31
-; GFX11-NEXT:    v_add_nc_u16 v32, 0x300, v32
-; GFX11-NEXT:    v_add_nc_u16 v33, 0x300, v33
-; GFX11-NEXT:    v_add_nc_u16 v34, 0x300, v34
-; GFX11-NEXT:    v_add_nc_u16 v35, 0x300, v35
-; GFX11-NEXT:    v_add_nc_u16 v36, 0x300, v36
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xffff, v27
-; GFX11-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xffff, v29
-; GFX11-NEXT:    v_lshlrev_b32_e32 v30, 16, v30
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xffff, v31
-; GFX11-NEXT:    v_lshlrev_b32_e32 v32, 16, v32
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xffff, v33
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v34
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xffff, v35
-; GFX11-NEXT:    v_lshlrev_b32_e32 v36, 16, v36
-; GFX11-NEXT:    v_or_b32_e32 v27, v27, v28
-; GFX11-NEXT:    v_or_b32_e32 v28, v29, v30
-; GFX11-NEXT:    v_or_b32_e32 v29, v31, v32
-; GFX11-NEXT:    v_or_b32_e32 v30, v33, v34
-; GFX11-NEXT:    v_or_b32_e32 v31, v35, v36
-; GFX11-NEXT:  .LBB29_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_b32 v138, off, s32 offset:392
-; GFX11-NEXT:    scratch_load_b32 v137, off, s32 offset:396
-; GFX11-NEXT:    scratch_load_b32 v136, off, s32 offset:400
-; GFX11-NEXT:    scratch_load_b32 v127, off, s32 offset:404
-; GFX11-NEXT:    scratch_load_b32 v126, off, s32 offset:408
-; GFX11-NEXT:    scratch_load_b32 v125, off, s32 offset:412
-; GFX11-NEXT:    scratch_load_b32 v124, off, s32 offset:416
-; GFX11-NEXT:    scratch_load_b32 v123, off, s32 offset:420
-; GFX11-NEXT:    scratch_load_b32 v122, off, s32 offset:424
-; GFX11-NEXT:    scratch_load_b32 v121, off, s32 offset:428
-; GFX11-NEXT:    scratch_load_b32 v120, off, s32 offset:432
-; GFX11-NEXT:    scratch_load_b32 v111, off, s32 offset:436
-; GFX11-NEXT:    scratch_load_b32 v110, off, s32 offset:440
-; GFX11-NEXT:    scratch_load_b32 v109, off, s32 offset:444
-; GFX11-NEXT:    scratch_load_b32 v108, off, s32 offset:448
-; GFX11-NEXT:    scratch_load_b32 v107, off, s32 offset:452
-; GFX11-NEXT:    scratch_load_b32 v106, off, s32 offset:456
-; GFX11-NEXT:    scratch_load_b32 v105, off, s32 offset:460
-; GFX11-NEXT:    scratch_load_b32 v104, off, s32 offset:464
-; GFX11-NEXT:    scratch_load_b32 v95, off, s32 offset:468
-; GFX11-NEXT:    scratch_load_b32 v94, off, s32 offset:472
-; GFX11-NEXT:    scratch_load_b32 v93, off, s32 offset:476
-; GFX11-NEXT:    scratch_load_b32 v92, off, s32 offset:480
-; GFX11-NEXT:    scratch_load_b32 v91, off, s32 offset:484
-; GFX11-NEXT:    scratch_load_b32 v90, off, s32 offset:488
-; GFX11-NEXT:    scratch_load_b32 v89, off, s32 offset:492
-; GFX11-NEXT:    scratch_load_b32 v88, off, s32 offset:496
-; GFX11-NEXT:    scratch_load_b32 v79, off, s32 offset:500
-; GFX11-NEXT:    scratch_load_b32 v78, off, s32 offset:504
-; GFX11-NEXT:    scratch_load_b32 v77, off, s32 offset:508
-; GFX11-NEXT:    scratch_load_b32 v76, off, s32 offset:512
-; GFX11-NEXT:    scratch_load_b32 v75, off, s32 offset:516
-; GFX11-NEXT:    s_clause 0x12
-; GFX11-NEXT:    scratch_load_b32 v74, off, s32 offset:520
-; GFX11-NEXT:    scratch_load_b32 v73, off, s32 offset:524
-; GFX11-NEXT:    scratch_load_b32 v72, off, s32 offset:528
-; GFX11-NEXT:    scratch_load_b32 v63, off, s32 offset:532
-; GFX11-NEXT:    scratch_load_b32 v62, off, s32 offset:536
-; GFX11-NEXT:    scratch_load_b32 v61, off, s32 offset:540
-; GFX11-NEXT:    scratch_load_b32 v60, off, s32 offset:544
-; GFX11-NEXT:    scratch_load_b32 v59, off, s32 offset:548
-; GFX11-NEXT:    scratch_load_b32 v58, off, s32 offset:552
-; GFX11-NEXT:    scratch_load_b32 v57, off, s32 offset:556
-; GFX11-NEXT:    scratch_load_b32 v56, off, s32 offset:560
-; GFX11-NEXT:    scratch_load_b32 v47, off, s32 offset:564
-; GFX11-NEXT:    scratch_load_b32 v46, off, s32 offset:568
-; GFX11-NEXT:    scratch_load_b32 v45, off, s32 offset:572
-; GFX11-NEXT:    scratch_load_b32 v44, off, s32 offset:576
-; GFX11-NEXT:    scratch_load_b32 v43, off, s32 offset:580
-; GFX11-NEXT:    scratch_load_b32 v42, off, s32 offset:584
-; GFX11-NEXT:    scratch_load_b32 v41, off, s32 offset:588
-; GFX11-NEXT:    scratch_load_b32 v40, off, s32 offset:592
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v128i8_to_v16i64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32 offset:384
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v32, off, s32 offset:380
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v31, off, s32 offset:376
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v32, off, s32 offset:372
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v50, off, s32 offset:368
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v33, off, s32 offset:364
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v50, off, s32 offset:360
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v33, off, s32 offset:356
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v49, off, s32 offset:352
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v34, off, s32 offset:348
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v51, off, s32 offset:344
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v34, off, s32 offset:340
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v51, off, s32 offset:336
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v35, off, s32 offset:332
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v54, off, s32 offset:328
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v35, off, s32 offset:324
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v53, off, s32 offset:320
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v36, off, s32 offset:316
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v53, off, s32 offset:312
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v36, off, s32 offset:308
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v54, off, s32 offset:304
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v37, off, s32 offset:300
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v55, off, s32 offset:296
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v37, off, s32 offset:292
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v64, off, s32 offset:288
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v38, off, s32 offset:284
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v64, off, s32 offset:280
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v38, off, s32 offset:276
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v55, off, s32 offset:272
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v39, off, s32 offset:268
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v65, off, s32 offset:264
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v39, off, s32 offset:260
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v65, off, s32 offset:256
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v48, off, s32 offset:252
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v69, off, s32 offset:248
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v48, off, s32 offset:244
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v68, off, s32 offset:240
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v49, off, s32 offset:236
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v68, off, s32 offset:232
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v52, off, s32 offset:228
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v69, off, s32 offset:224
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v52, off, s32 offset:220
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v70, off, s32 offset:216
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v103, off, s32 offset:388
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v81, off, s32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v81, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v82, off, s32 offset:16
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v82, off, s32 offset:24
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v83, off, s32 offset:32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v86, off, s32 offset:40
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v86, off, s32 offset:48
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v87, off, s32 offset:56
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v87, off, s32 offset:64
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v96, off, s32 offset:72
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v99, off, s32 offset:80
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v99, off, s32 offset:88
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v100, off, s32 offset:96
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v100, off, s32 offset:104
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v101, off, s32 offset:112
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v160, off, s32 offset:120
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v160, off, s32 offset:128
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v161, off, s32 offset:136
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v161, off, s32 offset:144
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v162, off, s32 offset:152
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v162, off, s32 offset:160
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v163, off, s32 offset:168
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v163, off, s32 offset:176
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v164, off, s32 offset:184
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v164, off, s32 offset:192
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v165, off, s32 offset:200
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v165, off, s32 offset:208
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v66, off, s32 offset:212
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v66, off, s32 offset:204
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v67, off, s32 offset:196
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v67, off, s32 offset:188
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v70, off, s32 offset:180
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v71, off, s32 offset:172
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v71, off, s32 offset:164
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v80, off, s32 offset:156
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v80, off, s32 offset:148
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v83, off, s32 offset:140
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v84, off, s32 offset:132
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v84, off, s32 offset:124
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v85, off, s32 offset:116
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v85, off, s32 offset:108
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v96, off, s32 offset:100
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v97, off, s32 offset:92
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v97, off, s32 offset:84
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v98, off, s32 offset:76
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v98, off, s32 offset:68
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v101, off, s32 offset:60
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v102, off, s32 offset:52
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v102, off, s32 offset:44
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v113, off, s32 offset:36
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v114, off, s32 offset:28
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v114, off, s32 offset:20
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v115, off, s32 offset:12
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v115, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v118.h, v30.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v119.l, v28.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v119.h, v26.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v130.h, v24.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v131.l, v22.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v131.h, v20.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v132.l, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v135.l, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v135.h, v14.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v144.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v144.h, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v145.l, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v148.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v148.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v149.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v149.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v150.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v150.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v151.l, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v151.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v145.h, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v146.l, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v146.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v147.l, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v147.h, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v132.h, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v133.l, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v133.h, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v134.l, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v134.h, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v128.l, 8, v29.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(62)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v50.h, 8, v50.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v50.l, 8, v50.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v49.h, 8, v49.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v54.l, 8, v54.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v53.h, 8, v53.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v53.l, 8, v53.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v64.h, 8, v64.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v64.l, 8, v64.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v55.h, 8, v55.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v69.l, 8, v69.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(61)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v68.h, 8, v68.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(59)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v68.l, 8, v68.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(54)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v103
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(53)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v128.h, 8, v81.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(52)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v129.l, 8, v81.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(51)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v129.h, 8, v82.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(50)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v130.l, 8, v82.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(49)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v116.l, 8, v83.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(48)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v116.h, 8, v86.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(47)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v117.l, 8, v86.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(46)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v117.h, 8, v87.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(45)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v118.l, 8, v87.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(44)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v103.l, 8, v96.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(43)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v103.h, 8, v99.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(42)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v112.l, 8, v99.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(41)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v112.h, 8, v100.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(40)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v113.l, 8, v100.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(39)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v99.l, 8, v101.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(38)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v99.h, 8, v160.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(37)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v100.l, 8, v160.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(36)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v100.h, 8, v161.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(35)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v101.l, 8, v161.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(34)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v86.l, 8, v162.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v86.h, 8, v162.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(32)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v87.l, 8, v163.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v87.h, 8, v163.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(30)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v96.l, 8, v164.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(29)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v81.l, 8, v164.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(28)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v81.h, 8, v165.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(27)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v82.l, 8, v165.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v82.h, 8, v70.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v83.l, 8, v69.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v69.h, 8, v65.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v70.l, 8, v65.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v65.l, 8, v55.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v65.h, 8, v54.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v54.h, 8, v51.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v55.l, 8, v51.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v51.l, 8, v31.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v51.h, 8, v31.l
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB29_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB29_4
+; GFX11-TRUE16-NEXT:  .LBB29_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB29_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v149.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v149.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v148.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v148.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v0.h, v150.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v150.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v151.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v1.h, v151.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v145.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v144.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v145.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v144.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v5
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v135.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v2.h, v146.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v132.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v135.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v146.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v147.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v5
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v131.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v132.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v3.h, v147.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v131.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v119.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v2.h, v133.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v7, v8
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v119.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v6
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v130.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v133.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v134.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v118.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v128.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v3.h, v134.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v9, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v11, v12
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v115.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v114.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v7.h, v128.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v114.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v115.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v129.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v130.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v10
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v113.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v116.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v6, v14
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v8.h, v129.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v102.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v102.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v101.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v7.h, v116.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v12, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v98.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v11
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v117.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v8.h, v117.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v118.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v98.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v97.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v103.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v14, v15
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v16, v17
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v97.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v96.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v12.h, v103.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v112.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v85.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v10, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v11, v19
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v13.h, v112.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v113.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v15
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v85.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v84.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v99.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v16
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v14
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v84.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v83.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v12.h, v99.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v100.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v17, v18
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v80.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v13.h, v100.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v101.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v19, v20
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.h, 0xff, v80.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v71.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v70.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v17.l, v86.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v21, v22
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.h, 0xff, v71.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v17.h, v86.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v18.l, v87.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v19.l, v96.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff, v17
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v67.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v15, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, v16, v24
+; GFX11-TRUE16-NEXT:    v_or_b16 v21.l, v18.h, v87.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v20
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v19
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.h, 0xff, v67.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v66.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.h, 0xff, v66.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v52.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v17.l, v81.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v21
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v17.h, v81.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v18.l, v82.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v21.l, v18.h, v82.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v19.l, v83.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, v22, v23
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v52.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v48.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v19
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v18, v24, v25
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.h, 0xff, v49.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.h, 0xff, v48.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v39.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v22.l, v68.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v23.l, v69.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v19, v26, v27
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, v21, v29
+; GFX11-TRUE16-NEXT:    v_or_b16 v25.l, v22.h, v68.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v26.l, v23.h, v69.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v24.l, v70.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v27, 0xffff, v22
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v29, 0xffff, v23
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v39.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v38.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, v20, v28
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v25
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v26
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff, v24
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.h, 0xff, v38.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.h, 0xff, v37.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v37.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v22.l, v55.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v23.l, v64.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v25.l, v22.h, v64.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v26.l, v23.h, v65.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v24.l, v65.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, v27, v28
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, v29, v30
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.l, 0xff, v36.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.l, 0xff, v35.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v29.l, 0xff, v34.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v26
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v24
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.h, 0xff, v36.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.h, 0xff, v35.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.l, v27.l, v53.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.l, v28.l, v54.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v29.l, v29.l, v55.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v25
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, v31, v37
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v26, v26, v39
+; GFX11-TRUE16-NEXT:    v_or_b16 v30.l, v27.h, v53.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v31.l, v28.h, v54.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v35, 0xffff, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v37, 0xffff, v28
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v29
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.l, 0xff, v34.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.h, 0xff, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.l, 0xff, v33.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.h, 0xff, v32.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v29.l, 0xff, v32.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v25, v25, v38
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v36, 16, v30
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v31
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.l, v27.l, v49.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v30.l, v27.h, v50.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.l, v28.l, v50.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v31.l, v28.h, v51.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v29.l, v29.l, v51.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v30, 0xffff, v30
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v33, 16, v28
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff, v31
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v29
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v27, v35, v36
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v28, v37, v38
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v29, v39, v32
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v30, v30, v33
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v31, v31, v34
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr149_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr148_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr148_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr145_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr144_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr144_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr135_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr132_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr131_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr131_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr130_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr119_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr118_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr115_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr114_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr114_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr97_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr85_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr71_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr67_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr150_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr150_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr151_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr145_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr146_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr147_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr147_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr132_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr133_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr133_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr134_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr134_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr128_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr128_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr129_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr130_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr116_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr116_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr117_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr118_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr103_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr112_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr113_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr99_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr100_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr101_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr86_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr83_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr68_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr70_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB29_2
+; GFX11-TRUE16-NEXT:  .LBB29_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v149.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v149.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v148.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v145.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v148.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v150.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v150.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v151.h, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v145.h, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v151.l, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v144.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v144.l, 3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, v135.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, v135.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v5
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v146.l, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v146.h, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v147.h, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v147.l, v3.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v2
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v132.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v131.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v131.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, v119.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v132.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v133.l, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v6
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v3.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, v130.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v7, v8
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v119.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, v118.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v133.h, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v134.h, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v6
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v134.l, v3.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v128.l, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v128.h, v7.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v4
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v9, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v11, v12
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, v115.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, v114.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v114.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.h, v115.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.l, 0x300, v7.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, v113.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v129.l, v8.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v130.l, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v116.l, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.h, v129.h, v8.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v8.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v10
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v116.h, v7.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v6, v14
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, v102.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, v101.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.l, 0x300, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v12, v13
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, v98.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, 0x300, v8.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.h, v102.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.h, v98.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v117.l, v8.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v118.l, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v103.l, v12.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v11
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.h, v117.h, v8.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v8.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v9.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, v97.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.h, v103.h, v12.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, 0x300, v12.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, 0x300, v8.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v14, v15
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v16, v17
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.h, v97.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, v96.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, v85.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v112.l, v13.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.l, 0x300, v12.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.h, v85.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.h, v112.h, v13.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v113.l, v14.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, 0x300, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v99.l, v12.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v10, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v11, v19
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, 0x300, v14.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v15
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, v84.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.h, v99.h, v12.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, 0x300, v12.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v16.l, 0x300, v13.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v14
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.h, v84.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, v83.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.l, 0x300, v12.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v17, v18
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.l, v80.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v100.l, v13.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.h, v80.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v16
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.h, v100.h, v13.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v101.l, v14.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, 0x300, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.h, 0xff, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v86.l, v17.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v16.l, 0x300, v13.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, 0x300, v14.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v19, v20
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.l, v71.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v19.l, v70.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.h, v86.h, v17.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.l, 0x300, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v21, v22
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.h, v71.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff, v17
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.l, v67.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.h, 0xff, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v87.l, v18.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v96.l, v19.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v20.l, 0x300, v17.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.h, v67.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v17.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.h, v87.h, v18.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.l, 0x300, v18.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v19.l, 0x300, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.h, 0xff, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v81.l, v17.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v15, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, v16, v24
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v21.l, 0x300, v18.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v20
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v19
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.l, v66.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.h, v66.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v19.l, v52.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.h, v81.h, v17.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.l, 0x300, v17.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.h, 0xff, v18.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v19.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v20.l, 0x300, v17.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, v22, v23
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.l, v52.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.l, v48.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v82.l, v18.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.h, v82.h, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v83.l, v19.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.h, v49.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.h, v48.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v21
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.l, 0x300, v18.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v21.l, 0x300, v18.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v19.l, 0x300, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.h, 0xff, v22.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.h, 0xff, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v68.l, v22.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v69.l, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v19
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v18, v24, v25
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v24.l, v39.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.h, v68.h, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.h, v69.h, v23.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.l, 0x300, v22.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.l, 0x300, v23.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v19, v26, v27
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, v21, v29
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v27, 0xffff, v22
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v29, 0xffff, v23
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.l, v39.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.l, v38.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v70.l, v24.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v25.l, 0x300, v22.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v26.l, 0x300, v23.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.h, v38.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.h, v37.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v23.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff, v20
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v24.l, 0x300, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.h, 0xff, v22.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.h, 0xff, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v55.h, v22.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v64.h, v23.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, v20, v28
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v25
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v26
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff, v24
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v24.l, v37.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.h, v64.l, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.h, v65.l, v23.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.l, 0x300, v22.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.l, 0x300, v23.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v25.l, 0x300, v22.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v26.l, 0x300, v23.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, v27, v28
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, v29, v30
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.l, v36.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.l, v35.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v29.l, v34.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v65.h, v24.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.h, v36.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.h, v35.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.l, 0xff, v27.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v29.l, 0xff, v29.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v24.l, 0x300, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.h, 0xff, v27.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.h, 0xff, v28.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.l, v53.l, v27.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.l, v54.l, v28.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v29.l, v55.l, v29.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v26
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v24
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.h, v53.h, v27.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.h, v54.h, v28.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.l, 0x300, v27.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.l, 0x300, v28.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v29.l, 0x300, v29.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, v31, v37
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v26, v26, v39
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v30.l, 0x300, v27.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v31.l, 0x300, v28.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v35, 0xffff, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v37, 0xffff, v28
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v29
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.l, v34.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.h, v33.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.l, v33.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.h, v32.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v29.l, v32.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.l, 0xff, v27.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.h, 0xff, v27.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.h, 0xff, v28.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v29.l, 0xff, v29.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v25
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.l, v49.h, v27.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.h, v50.l, v27.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.l, v50.h, v28.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.h, v51.l, v28.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v29.l, v51.h, v29.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v25, v25, v38
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v36, 16, v30
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v31
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.l, 0x300, v27.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v30.l, 0x300, v27.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.l, 0x300, v28.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v31.l, 0x300, v28.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v29.l, 0x300, v29.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v30, 0xffff, v30
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v33, 16, v28
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff, v31
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v29
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v27, v35, v36
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v28, v37, v38
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v29, v39, v32
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v30, v30, v33
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v31, v31, v34
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v128i8_to_v16i64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s32 offset:592
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v41, s32 offset:588
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v42, s32 offset:584
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v43, s32 offset:580
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v44, s32 offset:576
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v45, s32 offset:572
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v46, s32 offset:568
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v47, s32 offset:564
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v56, s32 offset:560
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v57, s32 offset:556
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v58, s32 offset:552
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v59, s32 offset:548
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v60, s32 offset:544
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v61, s32 offset:540
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v62, s32 offset:536
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v63, s32 offset:532
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v72, s32 offset:528
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v73, s32 offset:524
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v74, s32 offset:520
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v75, s32 offset:516
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v76, s32 offset:512
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v77, s32 offset:508
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v78, s32 offset:504
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v79, s32 offset:500
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v88, s32 offset:496
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v89, s32 offset:492
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v90, s32 offset:488
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v91, s32 offset:484
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v92, s32 offset:480
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v93, s32 offset:476
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v94, s32 offset:472
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v95, s32 offset:468
+; GFX11-FAKE16-NEXT:    s_clause 0x12
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v104, s32 offset:464
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v105, s32 offset:460
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v106, s32 offset:456
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v107, s32 offset:452
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v108, s32 offset:448
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v109, s32 offset:444
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v110, s32 offset:440
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v111, s32 offset:436
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v120, s32 offset:432
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v121, s32 offset:428
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v122, s32 offset:424
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v123, s32 offset:420
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v124, s32 offset:416
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v125, s32 offset:412
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v126, s32 offset:408
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v127, s32 offset:404
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v136, s32 offset:400
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v137, s32 offset:396
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v138, s32 offset:392
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v36, v22 :: v_dual_mov_b32 v37, v20
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v38, v18 :: v_dual_mov_b32 v39, v16
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v48, v14 :: v_dual_mov_b32 v49, v12
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v50, v10 :: v_dual_mov_b32 v51, v8
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v52, v6 :: v_dual_mov_b32 v53, v4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v54, v2 :: v_dual_mov_b32 v55, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v0, off, s32 offset:384
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v64, off, s32 offset:380
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32 offset:376
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v65, off, s32 offset:372
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v4, off, s32 offset:368
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v66, off, s32 offset:364
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v6, off, s32 offset:360
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v67, off, s32 offset:356
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v8, off, s32 offset:352
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v68, off, s32 offset:348
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v10, off, s32 offset:344
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v69, off, s32 offset:340
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v12, off, s32 offset:336
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v70, off, s32 offset:332
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v14, off, s32 offset:328
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v71, off, s32 offset:324
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v16, off, s32 offset:320
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v80, off, s32 offset:316
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v18, off, s32 offset:312
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v81, off, s32 offset:308
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v20, off, s32 offset:304
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v82, off, s32 offset:300
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v22, off, s32 offset:296
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v83, off, s32 offset:292
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v24, off, s32 offset:288
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v84, off, s32 offset:284
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v26, off, s32 offset:280
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v85, off, s32 offset:276
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v28, off, s32 offset:272
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v86, off, s32 offset:268
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v30, off, s32 offset:264
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v87, off, s32 offset:260
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v31, off, s32 offset:256
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v96, off, s32 offset:252
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v99, off, s32 offset:248
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v97, off, s32 offset:244
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v100, off, s32 offset:240
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v98, off, s32 offset:236
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v101, off, s32 offset:232
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v112, off, s32 offset:228
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v102, off, s32 offset:224
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v113, off, s32 offset:220
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v103, off, s32 offset:216
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v114, off, s32 offset:388
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v115, off, s32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v116, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v117, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v118, off, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v119, off, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v128, off, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v129, off, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v130, off, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v131, off, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v144, off, s32 offset:72
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v145, off, s32 offset:80
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v146, off, s32 offset:88
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v147, off, s32 offset:96
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v148, off, s32 offset:104
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v162, off, s32 offset:112
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v163, off, s32 offset:120
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v164, off, s32 offset:128
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v165, off, s32 offset:136
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v166, off, s32 offset:144
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v179, off, s32 offset:152
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v180, off, s32 offset:160
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v181, off, s32 offset:168
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v182, off, s32 offset:176
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v183, off, s32 offset:184
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v136, off, s32 offset:192
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v137, off, s32 offset:200
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v138, off, s32 offset:208
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v132, off, s32 offset:212
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v133, off, s32 offset:204
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v134, off, s32 offset:196
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v135, off, s32 offset:188
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v149, off, s32 offset:180
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v150, off, s32 offset:172
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v151, off, s32 offset:164
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v160, off, s32 offset:156
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v161, off, s32 offset:148
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v167, off, s32 offset:140
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v176, off, s32 offset:132
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v177, off, s32 offset:124
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v178, off, s32 offset:116
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v40, off, s32 offset:108
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v41, off, s32 offset:100
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v42, off, s32 offset:92
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v43, off, s32 offset:84
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v44, off, s32 offset:76
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v58, off, s32 offset:68
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v59, off, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v60, off, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v74, off, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v75, off, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v76, off, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v77, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v78, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v92, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v124, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v125, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v126, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v127, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v111, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v120, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v121, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v122, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v123, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v106, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v107, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v108, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v109, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v110, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v93, 8, v29
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(54)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v114
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(53)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v94, 8, v115
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(52)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v95, 8, v116
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(51)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v104, 8, v117
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(50)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v105, 8, v118
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(49)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v79, 8, v119
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(48)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v88, 8, v128
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(47)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v89, 8, v129
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(46)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v90, 8, v130
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(45)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v91, 8, v131
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(44)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v61, 8, v144
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(43)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v62, 8, v145
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(42)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v63, 8, v146
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(41)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v72, 8, v147
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(40)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v73, 8, v148
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(39)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v45, 8, v162
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(38)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v46, 8, v163
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(37)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v47, 8, v164
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(36)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v56, 8, v165
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(35)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v57, 8, v166
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(34)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v179, 8, v179
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v180, 8, v180
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(32)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v181, 8, v181
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v182, 8, v182
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(30)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v183, 8, v183
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(29)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v162, 8, v136
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(28)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v163, 8, v137
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(27)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v164, 8, v138
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v165, 8, v103
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v166, 8, v102
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v144, 8, v101
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v145, 8, v100
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v146, 8, v99
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v147, 8, v31
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v148, 8, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v119, 8, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v128, 8, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v129, 8, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v130, 8, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v131, 8, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v114, 8, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v115, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v116, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v117, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v118, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v99, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v100, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v101, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v102, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v103, 8, v0
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB29_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v53
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v52
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v51
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v124
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v125
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v126
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v127
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v50
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v37
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v49
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v48
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v111
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v121
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v120
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v122
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v123
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v107
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v38
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v108
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v109
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v110
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v106
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v6, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v8, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v10, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v32
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v92
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v78
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v77
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v76
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v75
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v74
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v60
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v59
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v93
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v94
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v95
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v104
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v105
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v79
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v88
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v89
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v90
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v91
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v13, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v15, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v58
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v44
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v43
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v42
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v41
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v40
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v178
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v177
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v176
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v167
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v61
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v62
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v63
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v72
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v73
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v17, v45
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v18, v46
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v19, v47
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v56
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v21, v57
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xffff, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xffff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v18, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v20, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v161
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v160
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v151
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v150
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v149
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v135
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v134
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v133
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v132
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v113
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v17, v179
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v18, v180
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v19, v181
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v182
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v21, v183
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v22, v162
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v23, v163
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v24, v164
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v165
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v26, v166
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xffff, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xffff, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v19, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v21, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v23, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v25, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v112
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v98
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v97
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v96
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v87
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v86
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v84
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v83
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v82
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v22, v144
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v23, v145
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v24, v146
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v147
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v26, v148
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v27, v119
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v28, v128
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v29, v129
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v30, v130
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v31, v131
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xffff, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xffff, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xffff, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xffff, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xffff, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v31
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v28, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v30, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v81
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v71
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v70
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v69
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v32, 0xff, v68
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xff, v67
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v34, 0xff, v66
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xff, v65
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v36, 0xff, v64
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v27, v114
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v28, v115
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v29, v116
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v30, v117
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v31, v118
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v32, v32, v99
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v33, v33, v100
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v34, v34, v101
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, v35, v102
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, v36, v103
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xffff, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xffff, v29
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xffff, v31
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xffff, v33
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xffff, v35
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v36, 16, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v27, v28
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v29, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v31, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v33, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v35, v36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr92
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr78
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr77
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr76
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr75
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr74
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr60
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr59
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr58
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr44
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr43
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr42
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr41
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr40
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr178
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr177
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr176
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr167
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr161
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr160
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr151
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr150
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr149
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr135
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr124
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr125
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr126
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr127
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr111
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr120
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr121
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr122
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr123
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr106
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr107
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr108
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr109
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr110
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr93
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr94
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr95
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr104
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr105
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr79
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr88
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr89
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr90
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr91
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr61
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr62
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr63
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr72
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr73
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr45
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr46
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr47
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr56
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr57
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr179
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr180
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr181
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr182
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr183
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr162
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr163
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr164
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr165
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr166
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr144
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr147
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr148
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT:  .LBB29_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB29_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v55, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v54, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v53, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v52, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v51, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v50, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v124, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v125, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v126, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v127, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v49, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v48, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v37, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v36, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v35, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v39, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, v34, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v123, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v111, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v120, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v121, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v122, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v107, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v108, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v109, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v38, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v110, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v106, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v3, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v8, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v10, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v33, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v32, 3
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v92, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v78, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, v77, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v76, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v75, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v74, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, v60, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, v59, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v93, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v94, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v95, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v104, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v105, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v79, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v88, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v89, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v90, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v91, v16
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v13
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, 0x300, v15
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, 0x300, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v13, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v15, v16
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v58, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v44, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v43, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, v42, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, v41, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, v40, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, v178, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, v177, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, v176, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, v167, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v61, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v62, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v63, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v72, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v73, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v45, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v46, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v47, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v56, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v57, v21
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v13
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, 0x300, v15
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, 0x300, v16
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, 0x300, v17
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, 0x300, v18
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, 0x300, v19
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, 0x300, v20
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, 0x300, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xffff, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xffff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v18, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v20, v21
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, v161, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, v160, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, v151, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, v150, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, v149, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, v135, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v23, v134, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v24, v133, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v25, v132, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v26, v113, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v179, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v180, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v181, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v182, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v183, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v162, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v163, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v164, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v165, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v166, v26
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, 0x300, v17
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, 0x300, v18
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, 0x300, v19
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, 0x300, v20
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, 0x300, v21
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, 0x300, v22
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v23, 0x300, v23
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v24, 0x300, v24
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v25, 0x300, v25
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v26, 0x300, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xffff, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xffff, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v19, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v21, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v23, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v25, v26
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, v112, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v23, v98, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v24, v97, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v25, v96, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v26, v87, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v27, v86, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v28, v85, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v29, v84, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v30, v83, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v31, v82, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v144, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v145, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v146, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v147, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v148, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v119, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v128, v28
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v129, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v130, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v131, v31
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, 0x300, v22
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v23, 0x300, v23
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v24, 0x300, v24
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v25, 0x300, v25
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v26, 0x300, v26
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v27, 0x300, v27
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v28, 0x300, v28
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v29, 0x300, v29
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v30, 0x300, v30
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v31, 0x300, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xffff, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xffff, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xffff, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xffff, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xffff, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v31
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v28, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v30, v31
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v27, v81, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v28, v80, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v29, v71, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v30, v70, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v31, v69, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v32, v68, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v33, v67, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v34, v66, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v35, v65, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v36, v64, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v32, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v34, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v36, 0xff, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v114, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v115, v28
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v116, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v117, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v118, v31
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v32, v99, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v33, v100, v33
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v34, v101, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, v102, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, v103, v36
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v27, 0x300, v27
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v28, 0x300, v28
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v29, 0x300, v29
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v30, 0x300, v30
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v31, 0x300, v31
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v32, 0x300, v32
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v33, 0x300, v33
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v34, 0x300, v34
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v35, 0x300, v35
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v36, 0x300, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xffff, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xffff, v29
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xffff, v31
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xffff, v33
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xffff, v35
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v36, 16, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v27, v28
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v29, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v31, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v33, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v35, v36
+; GFX11-FAKE16-NEXT:  .LBB29_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v138, off, s32 offset:392
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v137, off, s32 offset:396
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v136, off, s32 offset:400
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v127, off, s32 offset:404
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v126, off, s32 offset:408
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v125, off, s32 offset:412
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v124, off, s32 offset:416
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v123, off, s32 offset:420
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v122, off, s32 offset:424
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v121, off, s32 offset:428
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v120, off, s32 offset:432
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v111, off, s32 offset:436
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v110, off, s32 offset:440
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v109, off, s32 offset:444
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v108, off, s32 offset:448
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v107, off, s32 offset:452
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v106, off, s32 offset:456
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v105, off, s32 offset:460
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v104, off, s32 offset:464
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v95, off, s32 offset:468
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v94, off, s32 offset:472
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v93, off, s32 offset:476
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v92, off, s32 offset:480
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v91, off, s32 offset:484
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v90, off, s32 offset:488
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v89, off, s32 offset:492
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v88, off, s32 offset:496
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v79, off, s32 offset:500
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v78, off, s32 offset:504
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v77, off, s32 offset:508
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v76, off, s32 offset:512
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v75, off, s32 offset:516
+; GFX11-FAKE16-NEXT:    s_clause 0x12
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v74, off, s32 offset:520
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v73, off, s32 offset:524
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v72, off, s32 offset:528
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v63, off, s32 offset:532
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v62, off, s32 offset:536
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v61, off, s32 offset:540
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v60, off, s32 offset:544
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v59, off, s32 offset:548
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v58, off, s32 offset:552
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v57, off, s32 offset:556
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v56, off, s32 offset:560
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v47, off, s32 offset:564
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v46, off, s32 offset:568
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v45, off, s32 offset:572
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v44, off, s32 offset:576
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v43, off, s32 offset:580
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v42, off, s32 offset:584
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v41, off, s32 offset:588
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s32 offset:592
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -45192,550 +50846,1113 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v64bf16_to_v16i64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_b32 v32, off, s32 offset:4
-; GFX11-NEXT:    scratch_load_b32 v31, off, s32
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v32
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB31_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v33, 16, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v32, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
-; GFX11-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v37, v33, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v34, v32, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v35, 0x400000, v32
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_bfe_u32 v39, v14, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-NEXT:    v_add3_u32 v37, v37, v33, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v34, v34, v32, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v34, v35, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v35, v39, v14, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-NEXT:    v_or_b32_e32 v34, 0x400000, v33
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-NEXT:    v_bfe_u32 v36, v15, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v15
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v36, v36, v15, 0x7fff
-; GFX11-NEXT:    v_dual_cndmask_b32 v15, v36, v38 :: v_dual_lshlrev_b32 v36, 16, v13
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v15, v15, v32, 0x7060302
-; GFX11-NEXT:    v_dual_cndmask_b32 v33, v37, v34 :: v_dual_add_f32 v34, 0x40c00000, v36
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v32, v34, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v14
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_cndmask_b32 v14, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v12
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_perm_b32 v14, v14, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v13, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_cndmask_b32 v32, v32, v36
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-NEXT:    v_add3_u32 v33, v33, v13, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cndmask_b32_e32 v13, v33, v37, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v11
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_perm_b32 v13, v13, v32, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v32, v35, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-NEXT:    v_bfe_u32 v34, v12, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v12
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v34, v34, v12, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v12, v34, v38, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v12, v12, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v11, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_add3_u32 v33, v33, v11, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v35, v10, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v35, v35, v10, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v11, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v10
-; GFX11-NEXT:    v_perm_b32 v11, v11, v32, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    v_dual_cndmask_b32 v10, v35, v38 :: v_dual_lshlrev_b32 v37, 16, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_lshlrev_b32 v35, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-NEXT:    v_perm_b32 v10, v10, v33, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v32, v34, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v8, 0x40c00000, v8
-; GFX11-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v34, v8, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v9, 0x40c00000, v9
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_add3_u32 v34, v34, v8, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v33, v9, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v9
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    v_add3_u32 v33, v33, v9, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v9, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v8
-; GFX11-NEXT:    v_perm_b32 v9, v9, v32, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-NEXT:    v_cndmask_b32_e32 v8, v34, v38, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v8, v8, v33, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_add_f32 v35, 0x40c00000, v37
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v32, v35, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-NEXT:    v_bfe_u32 v35, v6, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v7, 0x40c00000, v7
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_add3_u32 v35, v35, v6, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v33, v7, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v7
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    v_add3_u32 v33, v33, v7, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v7, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v6
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v6, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v5
-; GFX11-NEXT:    v_perm_b32 v7, v7, v32, 0x7060302
-; GFX11-NEXT:    v_perm_b32 v6, v6, v33, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v4, 0x40c00000, v4
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v37
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v32, v34, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT:    v_bfe_u32 v34, v4, 16, 1
-; GFX11-NEXT:    v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v5, 0x40c00000, v5
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add3_u32 v34, v34, v4, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v33, v5, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v5
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v33, v33, v5, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v5, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v3
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v4
-; GFX11-NEXT:    v_perm_b32 v5, v5, v32, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_cndmask_b32 v4, v34, v38
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v2
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT:    v_bfe_u32 v32, v35, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_perm_b32 v4, v4, v33, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v35, v2, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_add3_u32 v35, v35, v2, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-NEXT:    v_bfe_u32 v33, v3, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v3
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v33, v33, v3, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v1
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v37
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v2, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v0
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    v_perm_b32 v3, v3, v32, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v32, v34, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_perm_b32 v2, v2, v33, 0x7060302
-; GFX11-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v34, v0, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_add3_u32 v34, v34, v0, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-NEXT:    v_bfe_u32 v33, v1, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v33, v33, v1, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v31
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v0
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xffff0000, v31
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_add_f32_e32 v31, 0x40c00000, v31
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v34, v38, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v30
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xffff0000, v30
-; GFX11-NEXT:    v_perm_b32 v1, v1, v32, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v32, v35, 16, 1
-; GFX11-NEXT:    v_perm_b32 v0, v0, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v31, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v30, 0x40c00000, v30
-; GFX11-NEXT:    v_add3_u32 v33, v33, v31, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v31
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-NEXT:    v_bfe_u32 v35, v30, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_cndmask_b32_e32 v31, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v29
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add3_u32 v35, v35, v30, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v30
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xffff0000, v29
-; GFX11-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add_f32_e32 v29, 0x40c00000, v29
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_dual_cndmask_b32 v30, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v28
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xffff0000, v28
-; GFX11-NEXT:    v_perm_b32 v31, v31, v32, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v32, v34, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v30, v30, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v29, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v28, 0x40c00000, v28
-; GFX11-NEXT:    v_add3_u32 v33, v33, v29, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v29
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11-NEXT:    v_bfe_u32 v34, v28, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cndmask_b32_e32 v29, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v27
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_add3_u32 v34, v34, v28, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v28
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xffff0000, v27
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v27, 0x40c00000, v27
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cndmask_b32_e32 v28, v34, v38, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v26
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xffff0000, v26
-; GFX11-NEXT:    v_perm_b32 v29, v29, v32, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v32, v35, 16, 1
-; GFX11-NEXT:    v_perm_b32 v28, v28, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v27, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v26, 0x40c00000, v26
-; GFX11-NEXT:    v_add3_u32 v33, v33, v27, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v27
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11-NEXT:    v_bfe_u32 v35, v26, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_cndmask_b32_e32 v27, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v25
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add3_u32 v35, v35, v26, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v26
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xffff0000, v25
-; GFX11-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add_f32_e32 v25, 0x40c00000, v25
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_dual_cndmask_b32 v26, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v24
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xffff0000, v24
-; GFX11-NEXT:    v_perm_b32 v27, v27, v32, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v32, v34, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v26, v26, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v25, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v24, 0x40c00000, v24
-; GFX11-NEXT:    v_add3_u32 v33, v33, v25, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v25
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-NEXT:    v_bfe_u32 v34, v24, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cndmask_b32_e32 v25, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v23
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_add3_u32 v34, v34, v24, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v24
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-NEXT:    v_perm_b32 v25, v25, v32, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v23, 0x40c00000, v23
-; GFX11-NEXT:    v_bfe_u32 v32, v35, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cndmask_b32_e32 v24, v34, v38, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xffff0000, v22
-; GFX11-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_perm_b32 v24, v24, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v23, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-NEXT:    v_add_f32_e32 v22, 0x40c00000, v22
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v23
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v33, v23, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-NEXT:    v_bfe_u32 v35, v22, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_cndmask_b32_e32 v23, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v21
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add3_u32 v35, v35, v22, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xffff0000, v21
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v22
-; GFX11-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v21, 0x40c00000, v21
-; GFX11-NEXT:    v_perm_b32 v23, v23, v32, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v36, v34, 16, 1
-; GFX11-NEXT:    v_dual_cndmask_b32 v22, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v20
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v32, v21, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v21
-; GFX11-NEXT:    v_perm_b32 v22, v22, v33, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v33, 0x40c00000, v35
-; GFX11-NEXT:    v_add3_u32 v35, v36, v34, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_add3_u32 v32, v32, v21, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xffff0000, v20
-; GFX11-NEXT:    v_bfe_u32 v38, v33, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v34, v35, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-NEXT:    v_add_f32_e32 v20, 0x40c00000, v20
-; GFX11-NEXT:    v_or_b32_e32 v35, 0x400000, v33
-; GFX11-NEXT:    v_lshlrev_b32_e32 v36, 16, v19
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff0000, v19
-; GFX11-NEXT:    v_cndmask_b32_e32 v21, v32, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v32, v38, v33, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-NEXT:    v_dual_add_f32 v33, 0x40c00000, v36 :: v_dual_lshlrev_b32 v36, 16, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v21, v21, v34, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v34, v20, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v35, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v35, 0x400000, v20
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-NEXT:    v_bfe_u32 v37, v33, 16, 1
-; GFX11-NEXT:    v_add3_u32 v34, v34, v20, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v19, 0x40c00000, v19
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xffff0000, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v20, v34, v35, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v36
-; GFX11-NEXT:    v_add3_u32 v35, v37, v33, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v33
-; GFX11-NEXT:    v_bfe_u32 v37, v19, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-NEXT:    v_or_b32_e32 v39, 0x400000, v34
-; GFX11-NEXT:    v_perm_b32 v20, v20, v32, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v35, v36, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v35, v37, v19, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v19
-; GFX11-NEXT:    v_add3_u32 v37, v38, v34, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v38, 16, v17
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-NEXT:    v_bfe_u32 v48, v18, 16, 1
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff0000, v17
-; GFX11-NEXT:    v_cndmask_b32_e32 v19, v35, v36, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add3_u32 v36, v48, v18, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v17, 0x40c00000, v17
-; GFX11-NEXT:    v_perm_b32 v19, v19, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v34, v37, v39, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v18
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v16
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff0000, v16
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v18, v36, v37, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v16, 0x40c00000, v16
-; GFX11-NEXT:    v_add_f32_e32 v36, 0x40c00000, v39
-; GFX11-NEXT:    v_add3_u32 v37, v38, v35, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v35
-; GFX11-NEXT:    v_bfe_u32 v39, v17, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_bfe_u32 v48, v36, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v49, 0x400000, v36
-; GFX11-NEXT:    v_or_b32_e32 v50, 0x400000, v16
-; GFX11-NEXT:    v_perm_b32 v18, v18, v34, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v35, v37, v38, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v38, v39, v17, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v39, 0x400000, v17
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-NEXT:    v_bfe_u32 v37, v16, 16, 1
-; GFX11-NEXT:    v_add3_u32 v48, v48, v36, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v17, v38, v39, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-NEXT:    v_add3_u32 v37, v37, v16, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v17, v17, v35, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v36, v48, v49, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-NEXT:    v_cndmask_b32_e32 v16, v37, v50, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v16, v16, v36, 0x7060302
-; GFX11-NEXT:  .LBB31_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v64bf16_to_v16i64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v32
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB31_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v33, 0xffff0000, v14
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_lshlrev_b32 v32, 16, v15
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v32, 0x40c00000, v32
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v39, v33, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v32, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v32
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v32
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v32, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v32, v35, v38 :: v_dual_and_b32 v15, 0xffff0000, v15
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v15, 0x40c00000, v15 :: v_dual_lshlrev_b32 v14, 16, v14
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v39, v33, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v32.l, v32.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v15, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v15
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT:    v_add3_u32 v36, v36, v15, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v15, v36, v37
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v48, v14, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v49, 0x400000, v14
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v33
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v15, 0xffff, v32, v15
+; GFX11-TRUE16-NEXT:    v_add3_u32 v38, v48, v14, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v14, v38, v49, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v13
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v14.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v33, v35, v36 :: v_dual_add_f32 v34, 0x40c00000, v34
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v14, 0xffff, v14, v33
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v34, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v38, v13, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v36, v38, v13, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v13
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v13, v36, v37 :: v_dual_and_b32 v38, 0xffff0000, v12
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v35, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v13, 0xffff, v13, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v36
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v12, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v35, 0x400000, v12
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v12, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v12, v32, v35, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v11, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v10
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v11, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v11
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v36
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v11, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v33, v33, v38 :: v_dual_and_b32 v38, 0xffff0000, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v11, 0xffff, v11, v33
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v10, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v10, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v10, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v12, 0xffff, v12, v32
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v9, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v10, 0xffff, v10, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v9, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_cndmask_b32 v9, v32, v36
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v9.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v9, 0xffff, v9, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v8, 0xffff, v8, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v7, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v6, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v7, 0xffff, v7, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v6, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v32, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v4, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v6, 0xffff, v6, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v5, 0xffff, v5, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v4, 0xffff, v4, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_cndmask_b32 v3, v32, v36
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v3, 0xffff, v3, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v2, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v35, 0x40c00000, v38 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v34
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v31
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v31
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v31, 0x40c00000, v31
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v32, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v31, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v30
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v30
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v31, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v31
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v30, 0x40c00000, v30
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v31, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v30, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v0, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v31.l, v31.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v30, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v30
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v29
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v31, 0xffff, v31, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v30, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v29, 0x40c00000, v29
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.l, v30.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v29, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v30, 0xffff, v30, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v28
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v29, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v29
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v28, 0x40c00000, v28
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v29, v32, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v28, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v27
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v28, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v28
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v27, 0x40c00000, v27
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.l, v29.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v28, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v27, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v29, 0xffff, v29, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.l, v28.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v27, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v27
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v26
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v26
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v28, 0xffff, v28, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v27, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v26, 0x40c00000, v26
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.l, v27.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v26, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v27, 0xffff, v27, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v25
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v26, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v26
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v25, 0x40c00000, v25
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v26, v32, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v25, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v24
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v25, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v25
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v24, 0x40c00000, v24
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v26.l, v26.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v25, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v24, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v26, 0xffff, v26, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v25.l, v25.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v24, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v24
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v23
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v25, 0xffff, v25, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v24, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v23, 0x40c00000, v23
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v24.l, v24.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v23, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v24, 0xffff, v24, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v23, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v23
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff0000, v20
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v23, v32, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v22, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v21
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v22, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v22
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v21, 0x40c00000, v21
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v23.l, v23.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v22, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v21, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v23, 0xffff, v23, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.l, v22.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v21, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v21
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v36
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v22, 0xffff, v22, v33
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v20, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v21, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v39
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v20
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v20, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.l, v21.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v18
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v21, 0xffff, v21, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v19
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v20, v33, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v19, 0x40c00000, v19
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v32, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v19
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v36, v36, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v39, v35, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.l, v20.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v19, v36, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v39, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v18, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v19.h
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v33, v33, v38 :: v_dual_and_b32 v38, 0xffff0000, v17
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v20, 0xffff, v20, v32
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v37, 0x40c00000, v38 :: v_dual_cndmask_b32 v34, v34, v36
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v17, 0x40c00000, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v18
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v16
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v49, 0x400000, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v48, 0x400000, v37
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v19, 0xffff, v19, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v18, v35, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v38, v17, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v37, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v16, 0x40c00000, v16
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v39, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v38, v38, v17, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v51, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v37, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v50, v16, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v39, v39, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v17, v38, v49, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v49, 0x400000, v16
+; GFX11-TRUE16-NEXT:    v_add3_u32 v38, v50, v16, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v18.l, v18.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v17.l, v17.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v36, v39, v51, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v18, 0xffff, v18, v34
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.l, v36.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v35, v35, v48, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v17, 0xffff, v17, v35
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v16, v38, v49, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v16, 0xffff, v36, v16
+; GFX11-TRUE16-NEXT:  .LBB31_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v64bf16_to_v16i64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v32
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB31_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v33, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v33, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v32, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, 0x400000, v32
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v39, v14, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v32
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v37, v33, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v32, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v34, v35, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v39, v14, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v34, 0x400000, v33
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v36, v15, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v15
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v36, v36, v15, 0x7fff
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v15, v36, v38 :: v_dual_lshlrev_b32 v36, 16, v13
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v15, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v33, v37, v34 :: v_dual_add_f32 v34, 0x40c00000, v36
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v14
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v14, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v12
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v14, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v13, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_cndmask_b32 v32, v32, v36
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v13, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v13, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v13, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v12, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v12
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v12, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v34, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v12, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v11, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v11, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v10, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v10
+; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v11, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v35, v38 :: v_dual_lshlrev_b32 v37, 16, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_lshlrev_b32 v35, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v10, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v8, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v8, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v8
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v9, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v34, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v8, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_add_f32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v6, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v7, 0x40c00000, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v6, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v5
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v6, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v5
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v5, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_cndmask_b32 v4, v34, v38
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v4, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v3, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v31
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xffff0000, v31
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v31, 0x40c00000, v31
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v34, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xffff0000, v30
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v31, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v30, 0x40c00000, v30
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v31, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v31
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v30, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v31, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v29
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v30, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xffff0000, v29
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v29, 0x40c00000, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v30, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xffff0000, v28
+; GFX11-FAKE16-NEXT:    v_perm_b32 v31, v31, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v30, v30, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v29, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v28, 0x40c00000, v28
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v29, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v29
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v28, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v29, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v27
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v28, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xffff0000, v27
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v27, 0x40c00000, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v28, v34, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xffff0000, v26
+; GFX11-FAKE16-NEXT:    v_perm_b32 v29, v29, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v28, v28, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v27, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v26, 0x40c00000, v26
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v27, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v27
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v26, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v27, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v25
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v26, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xffff0000, v25
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v25, 0x40c00000, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v26, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xffff0000, v24
+; GFX11-FAKE16-NEXT:    v_perm_b32 v27, v27, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v26, v26, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v25, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v24, 0x40c00000, v24
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v25, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v25
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v24, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v25, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v23
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v24, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xffff0000, v23
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-FAKE16-NEXT:    v_perm_b32 v25, v25, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v23, 0x40c00000, v23
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v24, v34, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_perm_b32 v24, v24, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v23, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v23
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v23, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v22, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v23, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v21
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v22, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xffff0000, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v22
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v21, 0x40c00000, v21
+; GFX11-FAKE16-NEXT:    v_perm_b32 v23, v23, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v36, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v22, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v20
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v21, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v21
+; GFX11-FAKE16-NEXT:    v_perm_b32 v22, v22, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v33, 0x40c00000, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v36, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v21, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v33, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v34, v35, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, 0x400000, v33
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v36, 16, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff0000, v19
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v21, v32, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v38, v33, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v33, 0x40c00000, v36 :: v_dual_lshlrev_b32 v36, 16, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v21, v21, v34, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v20, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v35, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, 0x400000, v20
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v33, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v20, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v20, v34, v35, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v36
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v37, v33, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v33
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v19, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v39, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_perm_b32 v20, v20, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v35, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v37, v19, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v19
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v17
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v48, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff0000, v17
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v19, v35, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v36, v48, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v17, 0x40c00000, v17
+; GFX11-FAKE16-NEXT:    v_perm_b32 v19, v19, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v34, v37, v39, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v16
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v36, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v16, 0x40c00000, v16
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v39
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v39, v17, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v48, v36, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v49, 0x400000, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v50, 0x400000, v16
+; GFX11-FAKE16-NEXT:    v_perm_b32 v18, v18, v34, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v35, v37, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v38, v39, v17, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v39, 0x400000, v17
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v16, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v48, v48, v36, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v38, v39, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v37, v16, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v17, v17, v35, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v36, v48, v49, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v37, v50, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v16, v16, v36, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB31_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -52277,676 +58494,1224 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v16f64_to_v128i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x13
-; GFX11-NEXT:    scratch_store_b32 off, v40, s32 offset:88
-; GFX11-NEXT:    scratch_store_b32 off, v41, s32 offset:84
-; GFX11-NEXT:    scratch_store_b32 off, v42, s32 offset:80
-; GFX11-NEXT:    scratch_store_b32 off, v43, s32 offset:76
-; GFX11-NEXT:    scratch_store_b32 off, v44, s32 offset:72
-; GFX11-NEXT:    scratch_store_b32 off, v45, s32 offset:68
-; GFX11-NEXT:    scratch_store_b32 off, v46, s32 offset:64
-; GFX11-NEXT:    scratch_store_b32 off, v47, s32 offset:60
-; GFX11-NEXT:    scratch_store_b32 off, v56, s32 offset:56
-; GFX11-NEXT:    scratch_store_b32 off, v57, s32 offset:52
-; GFX11-NEXT:    scratch_store_b32 off, v58, s32 offset:48
-; GFX11-NEXT:    scratch_store_b32 off, v59, s32 offset:44
-; GFX11-NEXT:    scratch_store_b32 off, v60, s32 offset:40
-; GFX11-NEXT:    scratch_store_b32 off, v61, s32 offset:36
-; GFX11-NEXT:    scratch_store_b32 off, v62, s32 offset:32
-; GFX11-NEXT:    scratch_store_b32 off, v63, s32 offset:28
-; GFX11-NEXT:    scratch_store_b32 off, v72, s32 offset:24
-; GFX11-NEXT:    scratch_store_b32 off, v73, s32 offset:20
-; GFX11-NEXT:    scratch_store_b32 off, v74, s32 offset:16
-; GFX11-NEXT:    scratch_store_b32 off, v75, s32 offset:12
-; GFX11-NEXT:    s_clause 0x2
-; GFX11-NEXT:    scratch_load_b32 v33, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_b32 v32, off, s32 offset:4
-; GFX11-NEXT:    scratch_load_b32 v31, off, s32
-; GFX11-NEXT:    ; implicit-def: $vgpr75
-; GFX11-NEXT:    ; implicit-def: $vgpr74
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr73
-; GFX11-NEXT:    ; implicit-def: $vgpr72
-; GFX11-NEXT:    ; implicit-def: $vgpr63
-; GFX11-NEXT:    ; implicit-def: $vgpr62
-; GFX11-NEXT:    ; implicit-def: $vgpr61
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr60
-; GFX11-NEXT:    ; implicit-def: $vgpr59
-; GFX11-NEXT:    ; implicit-def: $vgpr58
-; GFX11-NEXT:    ; implicit-def: $vgpr57
-; GFX11-NEXT:    ; implicit-def: $vgpr56
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr47
-; GFX11-NEXT:    ; implicit-def: $vgpr46
-; GFX11-NEXT:    ; implicit-def: $vgpr45
-; GFX11-NEXT:    ; implicit-def: $vgpr44
-; GFX11-NEXT:    ; implicit-def: $vgpr43
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr42
-; GFX11-NEXT:    ; implicit-def: $vgpr41
-; GFX11-NEXT:    ; implicit-def: $vgpr40
-; GFX11-NEXT:    ; implicit-def: $vgpr183
-; GFX11-NEXT:    ; implicit-def: $vgpr182
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr181
-; GFX11-NEXT:    ; implicit-def: $vgpr180
-; GFX11-NEXT:    ; implicit-def: $vgpr179
-; GFX11-NEXT:    ; implicit-def: $vgpr178
-; GFX11-NEXT:    ; implicit-def: $vgpr177
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr176
-; GFX11-NEXT:    ; implicit-def: $vgpr167
-; GFX11-NEXT:    ; implicit-def: $vgpr166
-; GFX11-NEXT:    ; implicit-def: $vgpr165
-; GFX11-NEXT:    ; implicit-def: $vgpr164
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr163
-; GFX11-NEXT:    ; implicit-def: $vgpr162
-; GFX11-NEXT:    ; implicit-def: $vgpr161
-; GFX11-NEXT:    ; implicit-def: $vgpr160
-; GFX11-NEXT:    ; implicit-def: $vgpr151
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr150
-; GFX11-NEXT:    ; implicit-def: $vgpr149
-; GFX11-NEXT:    ; implicit-def: $vgpr148
-; GFX11-NEXT:    ; implicit-def: $vgpr147
-; GFX11-NEXT:    ; implicit-def: $vgpr146
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr145
-; GFX11-NEXT:    ; implicit-def: $vgpr144
-; GFX11-NEXT:    ; implicit-def: $vgpr135
-; GFX11-NEXT:    ; implicit-def: $vgpr134
-; GFX11-NEXT:    ; implicit-def: $vgpr133
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr132
-; GFX11-NEXT:    ; implicit-def: $vgpr131
-; GFX11-NEXT:    ; implicit-def: $vgpr130
-; GFX11-NEXT:    ; implicit-def: $vgpr129
-; GFX11-NEXT:    ; implicit-def: $vgpr128
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr119
-; GFX11-NEXT:    ; implicit-def: $vgpr118
-; GFX11-NEXT:    ; implicit-def: $vgpr117
-; GFX11-NEXT:    ; implicit-def: $vgpr116
-; GFX11-NEXT:    ; implicit-def: $vgpr115
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr114
-; GFX11-NEXT:    ; implicit-def: $vgpr113
-; GFX11-NEXT:    ; implicit-def: $vgpr112
-; GFX11-NEXT:    ; implicit-def: $vgpr103
-; GFX11-NEXT:    ; implicit-def: $vgpr102
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr101
-; GFX11-NEXT:    ; implicit-def: $vgpr100
-; GFX11-NEXT:    ; implicit-def: $vgpr99
-; GFX11-NEXT:    ; implicit-def: $vgpr98
-; GFX11-NEXT:    ; implicit-def: $vgpr97
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    s_waitcnt vmcnt(2)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v33
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB36_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b64 v[48:49], 24, v[19:20]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
-; GFX11-NEXT:    v_lshrrev_b64 v[49:50], 24, v[17:18]
-; GFX11-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
-; GFX11-NEXT:    v_lshrrev_b64 v[50:51], 24, v[15:16]
-; GFX11-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
-; GFX11-NEXT:    v_lshrrev_b64 v[51:52], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
-; GFX11-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
-; GFX11-NEXT:    v_lshrrev_b64 v[64:65], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
-; GFX11-NEXT:    v_lshrrev_b64 v[53:54], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[65:66], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v68, 24, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v69, 16, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v70, 8, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v71, 16, v31
-; GFX11-NEXT:    v_lshrrev_b32_e32 v80, 8, v31
-; GFX11-NEXT:    v_lshrrev_b32_e32 v81, 24, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v82, 16, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v83, 8, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v84, 16, v29
-; GFX11-NEXT:    v_lshrrev_b32_e32 v85, 8, v29
-; GFX11-NEXT:    v_lshrrev_b32_e32 v86, 24, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v87, 16, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v96, 8, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v97, 16, v27
-; GFX11-NEXT:    v_lshrrev_b32_e32 v98, 8, v27
-; GFX11-NEXT:    v_lshrrev_b32_e32 v99, 24, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v100, 16, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v101, 8, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v102, 16, v25
-; GFX11-NEXT:    v_lshrrev_b32_e32 v103, 8, v25
-; GFX11-NEXT:    v_lshrrev_b32_e32 v112, 24, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v113, 16, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v114, 8, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v115, 16, v23
-; GFX11-NEXT:    v_lshrrev_b32_e32 v116, 8, v23
-; GFX11-NEXT:    v_lshrrev_b32_e32 v117, 24, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v118, 16, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v119, 8, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v128, 16, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v129, 8, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v130, 24, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v131, 16, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v132, 8, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v133, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v134, 8, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v135, 24, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v144, 16, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v145, 8, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v146, 16, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v147, 8, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v148, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v149, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v150, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v151, 16, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v160, 8, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v161, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v162, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v163, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v164, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v165, 8, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v166, 24, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v167, 16, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v176, 8, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v177, 16, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v178, 8, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v179, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v180, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v181, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v182, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v183, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v40, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v41, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v42, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v43, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v44, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v45, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v46, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v47, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v56, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v57, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v58, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v59, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v60, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v61, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v62, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v63, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v72, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v73, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v74, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v75, 8, v1
-; GFX11-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
-; GFX11-NEXT:    v_lshrrev_b64 v[54:55], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[66:67], 24, v[1:2]
-; GFX11-NEXT:  .LBB36_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB36_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_f64 v[19:20], v[19:20], 1.0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_f64 v[31:32], v[31:32], 1.0
-; GFX11-NEXT:    v_add_f64 v[17:18], v[17:18], 1.0
-; GFX11-NEXT:    v_add_f64 v[29:30], v[29:30], 1.0
-; GFX11-NEXT:    v_add_f64 v[15:16], v[15:16], 1.0
-; GFX11-NEXT:    v_add_f64 v[27:28], v[27:28], 1.0
-; GFX11-NEXT:    v_add_f64 v[13:14], v[13:14], 1.0
-; GFX11-NEXT:    v_add_f64 v[25:26], v[25:26], 1.0
-; GFX11-NEXT:    v_add_f64 v[11:12], v[11:12], 1.0
-; GFX11-NEXT:    v_add_f64 v[5:6], v[5:6], 1.0
-; GFX11-NEXT:    v_add_f64 v[23:24], v[23:24], 1.0
-; GFX11-NEXT:    v_add_f64 v[9:10], v[9:10], 1.0
-; GFX11-NEXT:    v_add_f64 v[3:4], v[3:4], 1.0
-; GFX11-NEXT:    v_add_f64 v[21:22], v[21:22], 1.0
-; GFX11-NEXT:    v_add_f64 v[7:8], v[7:8], 1.0
-; GFX11-NEXT:    v_add_f64 v[1:2], v[1:2], 1.0
-; GFX11-NEXT:    v_lshrrev_b64 v[48:49], 24, v[19:20]
-; GFX11-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
-; GFX11-NEXT:    v_lshrrev_b64 v[49:50], 24, v[17:18]
-; GFX11-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
-; GFX11-NEXT:    v_lshrrev_b64 v[50:51], 24, v[15:16]
-; GFX11-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
-; GFX11-NEXT:    v_lshrrev_b64 v[51:52], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
-; GFX11-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
-; GFX11-NEXT:    v_lshrrev_b64 v[64:65], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
-; GFX11-NEXT:    v_lshrrev_b64 v[53:54], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[65:66], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
-; GFX11-NEXT:    v_lshrrev_b64 v[54:55], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[66:67], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v68, 24, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v69, 16, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v70, 8, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v71, 16, v31
-; GFX11-NEXT:    v_lshrrev_b32_e32 v80, 8, v31
-; GFX11-NEXT:    v_lshrrev_b32_e32 v81, 24, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v82, 16, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v83, 8, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v84, 16, v29
-; GFX11-NEXT:    v_lshrrev_b32_e32 v85, 8, v29
-; GFX11-NEXT:    v_lshrrev_b32_e32 v86, 24, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v87, 16, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v96, 8, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v97, 16, v27
-; GFX11-NEXT:    v_lshrrev_b32_e32 v98, 8, v27
-; GFX11-NEXT:    v_lshrrev_b32_e32 v99, 24, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v100, 16, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v101, 8, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v102, 16, v25
-; GFX11-NEXT:    v_lshrrev_b32_e32 v103, 8, v25
-; GFX11-NEXT:    v_lshrrev_b32_e32 v112, 24, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v113, 16, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v114, 8, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v115, 16, v23
-; GFX11-NEXT:    v_lshrrev_b32_e32 v116, 8, v23
-; GFX11-NEXT:    v_lshrrev_b32_e32 v117, 24, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v118, 16, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v119, 8, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v128, 16, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v129, 8, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v130, 24, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v131, 16, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v132, 8, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v133, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v134, 8, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v135, 24, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v144, 16, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v145, 8, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v146, 16, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v147, 8, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v148, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v149, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v150, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v151, 16, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v160, 8, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v161, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v162, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v163, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v164, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v165, 8, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v166, 24, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v167, 16, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v176, 8, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v177, 16, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v178, 8, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v179, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v180, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v181, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v182, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v183, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v40, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v41, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v42, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v43, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v44, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v45, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v46, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v47, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v56, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v57, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v58, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v59, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v60, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v61, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v62, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v63, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v72, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v73, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v74, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v75, 8, v1
-; GFX11-NEXT:  .LBB36_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v75
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v66
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_lshlrev_b16 v66, 8, v63
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v65
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v55
-; GFX11-NEXT:    v_and_b32_e32 v55, 0xff, v74
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v67, 0xff, v61
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_or_b32_e32 v39, v55, v39
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v73
-; GFX11-NEXT:    v_or_b32_e32 v65, v67, v65
-; GFX11-NEXT:    v_lshlrev_b16 v67, 8, v58
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v39
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v55
-; GFX11-NEXT:    v_and_b32_e32 v55, 0xff, v72
-; GFX11-NEXT:    v_lshlrev_b16 v64, 8, v64
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v39
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_or_b32_e32 v55, v55, v66
-; GFX11-NEXT:    v_lshlrev_b16 v66, 8, v62
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v54
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v66
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v60
-; GFX11-NEXT:    v_and_b32_e32 v66, 0xff, v59
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v53
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v39
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v65
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v55
-; GFX11-NEXT:    v_or_b32_e32 v55, v66, v67
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v57
-; GFX11-NEXT:    v_and_b32_e32 v66, 0xff, v56
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v39
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v65
-; GFX11-NEXT:    v_or_b32_e32 v55, v66, v64
-; GFX11-NEXT:    v_lshlrev_b16 v64, 8, v47
-; GFX11-NEXT:    v_and_b32_e32 v65, 0xff, v46
-; GFX11-NEXT:    v_lshlrev_b16 v66, 8, v45
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v39
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v64
-; GFX11-NEXT:    v_or_b32_e32 v55, v65, v66
-; GFX11-NEXT:    v_lshlrev_b16 v64, 8, v44
-; GFX11-NEXT:    v_and_b32_e32 v65, 0xff, v43
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v39
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v64
-; GFX11-NEXT:    v_or_b32_e32 v54, v65, v54
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v42
-; GFX11-NEXT:    v_and_b32_e32 v64, 0xff, v41
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v40
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v39
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v54
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v55
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_or_b32_e32 v54, v64, v65
-; GFX11-NEXT:    v_and_b32_e32 v64, 0xff, v182
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v183
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v181
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v54, 16, v54
-; GFX11-NEXT:    v_or_b32_e32 v53, v64, v53
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v55
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v65
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v39
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v54
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v53
-; GFX11-NEXT:    v_and_b32_e32 v53, 0xff, v180
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v179
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v178
-; GFX11-NEXT:    v_and_b32_e32 v64, 0xff, v177
-; GFX11-NEXT:    v_lshlrev_b16 v52, 8, v52
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v176
-; GFX11-NEXT:    v_and_b32_e32 v66, 0xff, v167
-; GFX11-NEXT:    v_lshlrev_b16 v67, 8, v166
-; GFX11-NEXT:    v_or_b32_e32 v53, v53, v54
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v55
-; GFX11-NEXT:    v_or_b32_e32 v52, v64, v52
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v65
-; GFX11-NEXT:    v_or_b32_e32 v54, v66, v67
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v53, 16, v53
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v52, 16, v52
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v54, 16, v54
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off
-; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
-; GFX11-NEXT:    v_or_b32_e32 v1, v9, v39
-; GFX11-NEXT:    v_or_b32_e32 v2, v10, v53
-; GFX11-NEXT:    v_or_b32_e32 v3, v11, v52
-; GFX11-NEXT:    v_or_b32_e32 v4, v12, v54
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v13
-; GFX11-NEXT:    v_lshlrev_b16 v6, 8, v165
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v164
-; GFX11-NEXT:    v_lshlrev_b16 v8, 8, v51
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v14
-; GFX11-NEXT:    v_lshlrev_b16 v10, 8, v163
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v162
-; GFX11-NEXT:    v_lshlrev_b16 v12, 8, v161
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v15
-; GFX11-NEXT:    v_lshlrev_b16 v14, 8, v160
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v8, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v9, v13, v14
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v151
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v50
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v16
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v150
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v149
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v148
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v17
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v147
-; GFX11-NEXT:    v_and_b32_e32 v39, 0xff, v146
-; GFX11-NEXT:    v_lshlrev_b16 v49, 8, v49
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v11, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v12, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v13, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v14, v39, v49
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v8, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v9, v13, v14
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v18
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v145
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v144
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v135
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v19
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v134
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v133
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v48
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v20
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v132
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v11, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v12, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v13, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v14, v18, v19
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v131
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v130
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v21
-; GFX11-NEXT:    v_lshlrev_b16 v18, 8, v129
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v128
-; GFX11-NEXT:    v_lshlrev_b16 v20, 8, v38
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v22
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v119
-; GFX11-NEXT:    v_and_b32_e32 v38, 0xff, v118
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v117
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v16
-; GFX11-NEXT:    v_or_b32_e32 v16, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v17, v19, v20
-; GFX11-NEXT:    v_or_b32_e32 v18, v21, v22
-; GFX11-NEXT:    v_or_b32_e32 v19, v38, v39
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xffff, v18
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v11, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v12, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v13, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v14, v18, v19
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v23
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v116
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v115
-; GFX11-NEXT:    v_lshlrev_b16 v18, 8, v37
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v24
-; GFX11-NEXT:    v_lshlrev_b16 v20, 8, v114
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v113
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v112
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v25
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v103
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v16
-; GFX11-NEXT:    v_or_b32_e32 v16, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v17, v19, v20
-; GFX11-NEXT:    v_or_b32_e32 v18, v21, v22
-; GFX11-NEXT:    v_or_b32_e32 v19, v23, v24
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v102
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v36
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v26
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v101
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v100
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v99
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v27
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v98
-; GFX11-NEXT:    v_and_b32_e32 v36, 0xff, v97
-; GFX11-NEXT:    v_lshlrev_b16 v35, 8, v35
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v21, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v22, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v23, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v24, v36, v35
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff, v19
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xffff, v21
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xffff, v23
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v16
-; GFX11-NEXT:    v_or_b32_e32 v16, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v17, v19, v20
-; GFX11-NEXT:    v_or_b32_e32 v18, v21, v22
-; GFX11-NEXT:    v_or_b32_e32 v19, v23, v24
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v28
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v96
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v87
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v86
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v29
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v85
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v84
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v34
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v30
-; GFX11-NEXT:    v_lshlrev_b16 v29, 8, v83
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v21, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v22, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v23, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v24, v28, v29
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v82
-; GFX11-NEXT:    v_lshlrev_b16 v26, 8, v81
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v31
-; GFX11-NEXT:    v_lshlrev_b16 v28, 8, v80
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v71
-; GFX11-NEXT:    v_lshlrev_b16 v30, 8, v33
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v32
-; GFX11-NEXT:    v_lshlrev_b16 v32, 8, v70
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xff, v69
-; GFX11-NEXT:    v_lshlrev_b16 v34, 8, v68
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v26
-; GFX11-NEXT:    v_or_b32_e32 v26, v27, v28
-; GFX11-NEXT:    v_or_b32_e32 v27, v29, v30
-; GFX11-NEXT:    v_or_b32_e32 v28, v31, v32
-; GFX11-NEXT:    v_or_b32_e32 v29, v33, v34
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xffff, v20
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xffff, v22
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xffff, v24
-; GFX11-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xffff, v26
-; GFX11-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xffff, v28
-; GFX11-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v21, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v22, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v23, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v24, v28, v29
-; GFX11-NEXT:    s_clause 0x5
-; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off offset:32
-; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:48
-; GFX11-NEXT:    scratch_store_b128 v0, v[9:12], off offset:64
-; GFX11-NEXT:    scratch_store_b128 v0, v[13:16], off offset:80
-; GFX11-NEXT:    scratch_store_b128 v0, v[17:20], off offset:96
-; GFX11-NEXT:    scratch_store_b128 v0, v[21:24], off offset:112
-; GFX11-NEXT:    s_clause 0x13
-; GFX11-NEXT:    scratch_load_b32 v75, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_b32 v74, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_b32 v73, off, s32 offset:20
-; GFX11-NEXT:    scratch_load_b32 v72, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_b32 v63, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_b32 v62, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_b32 v61, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_b32 v60, off, s32 offset:40
-; GFX11-NEXT:    scratch_load_b32 v59, off, s32 offset:44
-; GFX11-NEXT:    scratch_load_b32 v58, off, s32 offset:48
-; GFX11-NEXT:    scratch_load_b32 v57, off, s32 offset:52
-; GFX11-NEXT:    scratch_load_b32 v56, off, s32 offset:56
-; GFX11-NEXT:    scratch_load_b32 v47, off, s32 offset:60
-; GFX11-NEXT:    scratch_load_b32 v46, off, s32 offset:64
-; GFX11-NEXT:    scratch_load_b32 v45, off, s32 offset:68
-; GFX11-NEXT:    scratch_load_b32 v44, off, s32 offset:72
-; GFX11-NEXT:    scratch_load_b32 v43, off, s32 offset:76
-; GFX11-NEXT:    scratch_load_b32 v42, off, s32 offset:80
-; GFX11-NEXT:    scratch_load_b32 v41, off, s32 offset:84
-; GFX11-NEXT:    scratch_load_b32 v40, off, s32 offset:88
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v16f64_to_v128i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x2
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v33, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr162_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr161_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr160_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr151_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr150_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr149_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr148_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr147_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr145_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr144_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr134_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr133_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr132_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr131_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr130_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr128_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr119_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr118_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr117_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr116_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr115_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr114_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr113_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr103_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr101_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr100_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr99_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr97_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr86_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr85_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr83_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr71_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr70_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr68_lo16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v33
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB36_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[48:49], 24, v[19:20]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[49:50], 24, v[17:18]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[50:51], 24, v[15:16]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[51:52], 24, v[13:14]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[64:65], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[53:54], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[65:66], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v68, 24, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v69, 8, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v70, 8, v31
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v71, 24, v30
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v80, 8, v30
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v81, 8, v29
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v82, 24, v28
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v83, 8, v28
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v84, 8, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v85, 24, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v86, 8, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v87, 8, v25
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v96, 24, v24
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v97, 8, v24
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v98, 8, v23
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v99, 24, v22
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v100, 8, v22
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v101, 8, v21
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v102, 24, v20
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v103, 8, v20
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v112, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v113, 24, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v114, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v115, 8, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v116, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v117, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v118, 8, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v119, 24, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v128, 8, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v129, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v130, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v131, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v132, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v133, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v134, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v135, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v144, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v145, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v146, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v147, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v148, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v149, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v150, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v151, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v160, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v161, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v162, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[54:55], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[66:67], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB36_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB36_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_f64 v[19:20], v[19:20], 1.0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_f64 v[31:32], v[31:32], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[17:18], v[17:18], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[29:30], v[29:30], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[15:16], v[15:16], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[27:28], v[27:28], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[13:14], v[13:14], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[25:26], v[25:26], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[11:12], v[11:12], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[5:6], v[5:6], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[23:24], v[23:24], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[9:10], v[9:10], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[3:4], v[3:4], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[21:22], v[21:22], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[7:8], v[7:8], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[1:2], v[1:2], 1.0
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[48:49], 24, v[19:20]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[49:50], 24, v[17:18]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[50:51], 24, v[15:16]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[51:52], 24, v[13:14]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[64:65], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[53:54], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[65:66], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[54:55], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[66:67], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v68, 24, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v69, 8, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v70, 8, v31
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v71, 24, v30
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v80, 8, v30
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v81, 8, v29
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v82, 24, v28
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v83, 8, v28
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v84, 8, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v85, 24, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v86, 8, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v87, 8, v25
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v96, 24, v24
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v97, 8, v24
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v98, 8, v23
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v99, 24, v22
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v100, 8, v22
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v101, 8, v21
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v102, 24, v20
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v103, 8, v20
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v112, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v113, 24, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v114, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v115, 8, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v116, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v117, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v118, 8, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v119, 24, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v128, 8, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v129, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v130, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v131, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v132, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v133, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v134, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v135, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v144, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v145, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v146, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v147, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v148, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v149, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v150, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v151, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v160, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v161, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v162, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB36_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v39.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v34.h, 8, v66.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v33.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v161.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v39.l, v1.h, v34.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v162.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v39
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.h, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v55, 0xffff, v55
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v160.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v150.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v66.l, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v67.l, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v65.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v55, v39
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v55, 0xffff, v66
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v65, 16, v67
+; GFX11-TRUE16-NEXT:    v_or_b16 v39.l, v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 8, v151.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v55, v65
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v39
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.h, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.h, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v149.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v55, 16, v55
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.l, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v66.l, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v64.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v3.h, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v39, v55
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v65
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v55, 16, v66
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v4.h, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.l, 8, v148.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v147.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v39, v55
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.h, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.h, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v54.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v64
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v146.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v55
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v5.h, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v39, v54
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v64
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v145.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v144.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v55
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v39, v54
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v55
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v53.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v134.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.l, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v8.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v135.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v10.l, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v53, 0xffff, v53
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v55, 16, v55
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v64
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.h, v8.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.l, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v11.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v53, v55
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v55, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v10.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v132.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v52.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v39, v54
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v133.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v11.h
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v129.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v131.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v34.h, 8, v130.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v51.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v33.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v39.l, v12.h, v34.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v10, v11
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v128.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v15.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v50.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v39
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v55, v9
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v14.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v119.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v118.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v6
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v12, v39
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v16.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v117.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v16.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v116.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v10, v11
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v114.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v115.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v18.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v113.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v12, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v14, v15
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v19.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v112.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v19.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v48.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v20.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v102.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v16, v17
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v20.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v103.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v11
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v21.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v101.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v14.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v21.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v38.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v15, v16
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.l, 0xff, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v98.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v14
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v100.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v17, v18
+; GFX11-TRUE16-NEXT:    v_and_b16 v16.l, 0xff, v23.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v37.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v97.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v15.l, v15.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v19, v20
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v24.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v96.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v25.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v87.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v16.l, v16.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v17.l, v17.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.l, 0xff, v25.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v36.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v21, v22
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v18.l, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v19.l, v19.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v16
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff, v17
+; GFX11-TRUE16-NEXT:    v_and_b16 v16.l, 0xff, v26.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v86.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v26.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v85.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v15.l, v15.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff, v19
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v16.l, v16.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v17.l, v17.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v15
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v27.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v84.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v27.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v16
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v20, v21
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, v22, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, v24, v25
+; GFX11-TRUE16-NEXT:    v_and_b16 v20.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v83.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v21.l, 0xff, v28.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.h, 8, v82.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v29.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v22.h, 8, v81.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v29.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.h, 8, v34.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v30.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v24.h, 8, v80.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v18.l, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v20.l, v20.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v21.l, v21.l, v21.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v22.l, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v23.l, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v24.l, v24.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v49.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v99.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v35.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v35, 0xffff, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v18, v26, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v20
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v21
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v27, 0xffff, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v23
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v29, 0xffff, v24
+; GFX11-TRUE16-NEXT:    v_and_b16 v20.l, 0xff, v30.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v71.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v21.l, 0xff, v31.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.h, 8, v70.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v31.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v22.h, 8, v33.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v32.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.h, 8, v69.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v32.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v24.h, 8, v68.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v14.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v19.l, v19.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v53, 0xffff, v64
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v65
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v20.l, v20.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v21.l, v21.l, v21.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v22.l, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v23.l, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v24.l, v24.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v53, v54
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v20
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff, v21
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v22
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v33, 0xffff, v23
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v39, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v38, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v19, v35, v19
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, v25, v26
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, v27, v28
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, v29, v30
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, v31, v32
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, v33, v24
+; GFX11-TRUE16-NEXT:    s_clause 0x5
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off offset:32
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:48
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[9:12], off offset:64
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[13:16], off offset:80
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[17:20], off offset:96
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[21:24], off offset:112
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v16f64_to_v128i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x13
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s32 offset:88
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v41, s32 offset:84
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v42, s32 offset:80
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v43, s32 offset:76
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v44, s32 offset:72
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v45, s32 offset:68
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v46, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v47, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v56, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v57, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v58, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v59, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v60, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v61, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v62, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v63, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v72, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v73, s32 offset:20
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v74, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v75, s32 offset:12
+; GFX11-FAKE16-NEXT:    s_clause 0x2
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v33, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr75
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr74
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr73
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr72
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr63
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr62
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr61
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr60
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr59
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr58
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr57
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr56
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr47
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr46
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr45
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr44
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr43
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr42
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr41
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr40
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr183
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr182
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr181
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr180
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr179
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr178
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr177
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr176
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr167
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr166
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr165
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr164
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr163
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr162
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr161
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr160
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr151
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr150
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr149
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr148
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr147
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr144
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr135
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB36_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[48:49], 24, v[19:20]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[49:50], 24, v[17:18]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[50:51], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[51:52], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[64:65], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[53:54], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[65:66], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v68, 24, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v69, 16, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v70, 8, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 16, v31
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 8, v31
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v81, 24, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v82, 16, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 8, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 16, v29
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v85, 8, v29
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v86, 24, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 16, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 8, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v97, 16, v27
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v98, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v99, 24, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v100, 16, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v101, 8, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v102, 16, v25
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v103, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v112, 24, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v113, 16, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v114, 8, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v115, 16, v23
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v116, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v117, 24, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v118, 16, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v119, 8, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v128, 16, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v129, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v130, 24, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v131, 16, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v132, 8, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v133, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v134, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v135, 24, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v144, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v145, 8, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v146, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v147, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v148, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v149, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v150, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v151, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v160, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v161, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v162, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v163, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v164, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v165, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v166, 24, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v167, 16, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v176, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v177, 16, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v178, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v179, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v180, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v181, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v182, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v183, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v40, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v41, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v42, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v43, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v44, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v45, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v46, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v47, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v56, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v57, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v58, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v59, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v60, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v61, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v62, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v63, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v72, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v73, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v74, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v75, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[54:55], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[66:67], 24, v[1:2]
+; GFX11-FAKE16-NEXT:  .LBB36_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB36_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_f64 v[19:20], v[19:20], 1.0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_f64 v[31:32], v[31:32], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[17:18], v[17:18], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[29:30], v[29:30], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[15:16], v[15:16], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[27:28], v[27:28], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[13:14], v[13:14], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[25:26], v[25:26], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[11:12], v[11:12], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[5:6], v[5:6], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[23:24], v[23:24], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[9:10], v[9:10], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[3:4], v[3:4], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[21:22], v[21:22], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[7:8], v[7:8], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[1:2], v[1:2], 1.0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[48:49], 24, v[19:20]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[49:50], 24, v[17:18]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[50:51], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[51:52], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[64:65], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[53:54], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[65:66], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[54:55], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[66:67], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v68, 24, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v69, 16, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v70, 8, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 16, v31
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 8, v31
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v81, 24, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v82, 16, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 8, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 16, v29
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v85, 8, v29
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v86, 24, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 16, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 8, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v97, 16, v27
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v98, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v99, 24, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v100, 16, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v101, 8, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v102, 16, v25
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v103, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v112, 24, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v113, 16, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v114, 8, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v115, 16, v23
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v116, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v117, 24, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v118, 16, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v119, 8, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v128, 16, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v129, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v130, 24, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v131, 16, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v132, 8, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v133, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v134, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v135, 24, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v144, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v145, 8, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v146, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v147, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v148, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v149, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v150, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v151, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v160, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v161, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v162, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v163, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v164, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v165, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v166, 24, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v167, 16, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v176, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v177, 16, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v178, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v179, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v180, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v181, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v182, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v183, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v40, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v41, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v42, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v43, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v44, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v45, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v46, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v47, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v56, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v57, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v58, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v59, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v60, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v61, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v62, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v63, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v72, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v73, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v74, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v75, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB36_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v75
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v66
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v66, 8, v63
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v55, 0xff, v74
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v67, 0xff, v61
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v39, v55, v39
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v73
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v65, v67, v65
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v67, 8, v58
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v55, 0xff, v72
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v64, 8, v64
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, v55, v66
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v66, 8, v62
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v66
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v60
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v66, 0xff, v59
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v53, 8, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, v66, v67
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v57
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v66, 0xff, v56
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, v66, v64
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v64, 8, v47
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v65, 0xff, v46
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v66, 8, v45
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v64
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, v65, v66
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v64, 8, v44
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v65, 0xff, v43
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v64
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v54, v65, v54
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v42
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v64, 0xff, v41
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v40
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v39
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v54, v64, v65
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v64, 0xff, v182
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v183
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v181
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v53, v64, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v54
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v53
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v53, 0xff, v180
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v179
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v178
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v64, 0xff, v177
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v52, 8, v52
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v176
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v66, 0xff, v167
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v67, 8, v166
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v53, v53, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v52, v64, v52
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v54, v66, v67
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v53, 16, v53
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v52, 16, v52
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v54
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v9, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v10, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v11, v52
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v12, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v6, 8, v165
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v164
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v51
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v10, 8, v163
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v162
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v12, 8, v161
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v14, 8, v160
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v13, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v151
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v50
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v150
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v149
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v148
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v147
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v39, 0xff, v146
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v49, 8, v49
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v39, v49
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v13, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v145
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v144
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v135
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v134
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v133
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v48
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v132
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v18, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v131
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v130
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v18, 8, v129
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v128
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v38
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v119
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v38, 0xff, v118
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v117
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v19, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v21, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v38, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xffff, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v18, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v116
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v115
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v18, 8, v37
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v114
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v113
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v112
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v103
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v19, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v21, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v23, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v102
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v101
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v100
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v99
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v98
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v36, 0xff, v97
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v35, 8, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v36, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xffff, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v19, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v21, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v23, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v96
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v87
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v86
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v29
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v84
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v29, 8, v83
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v28, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v82
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v26, 8, v81
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v28, 8, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v71
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v30, 8, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v32, 8, v70
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xff, v69
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v34, 8, v68
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v27, v28
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v29, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v31, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v33, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xffff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xffff, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xffff, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xffff, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xffff, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v28, v29
+; GFX11-FAKE16-NEXT:    s_clause 0x5
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off offset:32
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:48
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[9:12], off offset:64
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[13:16], off offset:80
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[17:20], off offset:96
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[21:24], off offset:112
+; GFX11-FAKE16-NEXT:    s_clause 0x13
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v75, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v74, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v73, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v72, off, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v63, off, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v62, off, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v61, off, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v60, off, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v59, off, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v58, off, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v57, off, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v56, off, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v47, off, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v46, off, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v45, off, s32 offset:68
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v44, off, s32 offset:72
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v43, off, s32 offset:76
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v42, off, s32 offset:80
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v41, off, s32 offset:84
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s32 offset:88
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -57038,1038 +63803,1985 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v128i8_to_v16f64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_store_b32 off, v40, s32 offset:592
-; GFX11-NEXT:    scratch_store_b32 off, v41, s32 offset:588
-; GFX11-NEXT:    scratch_store_b32 off, v42, s32 offset:584
-; GFX11-NEXT:    scratch_store_b32 off, v43, s32 offset:580
-; GFX11-NEXT:    scratch_store_b32 off, v44, s32 offset:576
-; GFX11-NEXT:    scratch_store_b32 off, v45, s32 offset:572
-; GFX11-NEXT:    scratch_store_b32 off, v46, s32 offset:568
-; GFX11-NEXT:    scratch_store_b32 off, v47, s32 offset:564
-; GFX11-NEXT:    scratch_store_b32 off, v56, s32 offset:560
-; GFX11-NEXT:    scratch_store_b32 off, v57, s32 offset:556
-; GFX11-NEXT:    scratch_store_b32 off, v58, s32 offset:552
-; GFX11-NEXT:    scratch_store_b32 off, v59, s32 offset:548
-; GFX11-NEXT:    scratch_store_b32 off, v60, s32 offset:544
-; GFX11-NEXT:    scratch_store_b32 off, v61, s32 offset:540
-; GFX11-NEXT:    scratch_store_b32 off, v62, s32 offset:536
-; GFX11-NEXT:    scratch_store_b32 off, v63, s32 offset:532
-; GFX11-NEXT:    scratch_store_b32 off, v72, s32 offset:528
-; GFX11-NEXT:    scratch_store_b32 off, v73, s32 offset:524
-; GFX11-NEXT:    scratch_store_b32 off, v74, s32 offset:520
-; GFX11-NEXT:    scratch_store_b32 off, v75, s32 offset:516
-; GFX11-NEXT:    scratch_store_b32 off, v76, s32 offset:512
-; GFX11-NEXT:    scratch_store_b32 off, v77, s32 offset:508
-; GFX11-NEXT:    scratch_store_b32 off, v78, s32 offset:504
-; GFX11-NEXT:    scratch_store_b32 off, v79, s32 offset:500
-; GFX11-NEXT:    scratch_store_b32 off, v88, s32 offset:496
-; GFX11-NEXT:    scratch_store_b32 off, v89, s32 offset:492
-; GFX11-NEXT:    scratch_store_b32 off, v90, s32 offset:488
-; GFX11-NEXT:    scratch_store_b32 off, v91, s32 offset:484
-; GFX11-NEXT:    scratch_store_b32 off, v92, s32 offset:480
-; GFX11-NEXT:    scratch_store_b32 off, v93, s32 offset:476
-; GFX11-NEXT:    scratch_store_b32 off, v94, s32 offset:472
-; GFX11-NEXT:    scratch_store_b32 off, v95, s32 offset:468
-; GFX11-NEXT:    s_clause 0x12
-; GFX11-NEXT:    scratch_store_b32 off, v104, s32 offset:464
-; GFX11-NEXT:    scratch_store_b32 off, v105, s32 offset:460
-; GFX11-NEXT:    scratch_store_b32 off, v106, s32 offset:456
-; GFX11-NEXT:    scratch_store_b32 off, v107, s32 offset:452
-; GFX11-NEXT:    scratch_store_b32 off, v108, s32 offset:448
-; GFX11-NEXT:    scratch_store_b32 off, v109, s32 offset:444
-; GFX11-NEXT:    scratch_store_b32 off, v110, s32 offset:440
-; GFX11-NEXT:    scratch_store_b32 off, v111, s32 offset:436
-; GFX11-NEXT:    scratch_store_b32 off, v120, s32 offset:432
-; GFX11-NEXT:    scratch_store_b32 off, v121, s32 offset:428
-; GFX11-NEXT:    scratch_store_b32 off, v122, s32 offset:424
-; GFX11-NEXT:    scratch_store_b32 off, v123, s32 offset:420
-; GFX11-NEXT:    scratch_store_b32 off, v124, s32 offset:416
-; GFX11-NEXT:    scratch_store_b32 off, v125, s32 offset:412
-; GFX11-NEXT:    scratch_store_b32 off, v126, s32 offset:408
-; GFX11-NEXT:    scratch_store_b32 off, v127, s32 offset:404
-; GFX11-NEXT:    scratch_store_b32 off, v136, s32 offset:400
-; GFX11-NEXT:    scratch_store_b32 off, v137, s32 offset:396
-; GFX11-NEXT:    scratch_store_b32 off, v138, s32 offset:392
-; GFX11-NEXT:    v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28
-; GFX11-NEXT:    v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24
-; GFX11-NEXT:    v_dual_mov_b32 v36, v22 :: v_dual_mov_b32 v37, v20
-; GFX11-NEXT:    v_dual_mov_b32 v38, v18 :: v_dual_mov_b32 v39, v16
-; GFX11-NEXT:    v_dual_mov_b32 v48, v14 :: v_dual_mov_b32 v49, v12
-; GFX11-NEXT:    v_dual_mov_b32 v50, v10 :: v_dual_mov_b32 v51, v8
-; GFX11-NEXT:    v_dual_mov_b32 v52, v6 :: v_dual_mov_b32 v53, v4
-; GFX11-NEXT:    v_dual_mov_b32 v54, v2 :: v_dual_mov_b32 v55, v0
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v0, off, s32 offset:384
-; GFX11-NEXT:    scratch_load_u16 v64, off, s32 offset:380
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32 offset:376
-; GFX11-NEXT:    scratch_load_u16 v65, off, s32 offset:372
-; GFX11-NEXT:    scratch_load_u16 v4, off, s32 offset:368
-; GFX11-NEXT:    scratch_load_u16 v66, off, s32 offset:364
-; GFX11-NEXT:    scratch_load_u16 v6, off, s32 offset:360
-; GFX11-NEXT:    scratch_load_u16 v67, off, s32 offset:356
-; GFX11-NEXT:    scratch_load_u16 v8, off, s32 offset:352
-; GFX11-NEXT:    scratch_load_u16 v68, off, s32 offset:348
-; GFX11-NEXT:    scratch_load_u16 v10, off, s32 offset:344
-; GFX11-NEXT:    scratch_load_u16 v69, off, s32 offset:340
-; GFX11-NEXT:    scratch_load_u16 v12, off, s32 offset:336
-; GFX11-NEXT:    scratch_load_u16 v70, off, s32 offset:332
-; GFX11-NEXT:    scratch_load_u16 v14, off, s32 offset:328
-; GFX11-NEXT:    scratch_load_u16 v71, off, s32 offset:324
-; GFX11-NEXT:    scratch_load_u16 v16, off, s32 offset:320
-; GFX11-NEXT:    scratch_load_u16 v80, off, s32 offset:316
-; GFX11-NEXT:    scratch_load_u16 v18, off, s32 offset:312
-; GFX11-NEXT:    scratch_load_u16 v81, off, s32 offset:308
-; GFX11-NEXT:    scratch_load_u16 v20, off, s32 offset:304
-; GFX11-NEXT:    scratch_load_u16 v82, off, s32 offset:300
-; GFX11-NEXT:    scratch_load_u16 v22, off, s32 offset:296
-; GFX11-NEXT:    scratch_load_u16 v83, off, s32 offset:292
-; GFX11-NEXT:    scratch_load_u16 v24, off, s32 offset:288
-; GFX11-NEXT:    scratch_load_u16 v84, off, s32 offset:284
-; GFX11-NEXT:    scratch_load_u16 v26, off, s32 offset:280
-; GFX11-NEXT:    scratch_load_u16 v85, off, s32 offset:276
-; GFX11-NEXT:    scratch_load_u16 v28, off, s32 offset:272
-; GFX11-NEXT:    scratch_load_u16 v86, off, s32 offset:268
-; GFX11-NEXT:    scratch_load_u16 v30, off, s32 offset:264
-; GFX11-NEXT:    scratch_load_u16 v87, off, s32 offset:260
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v31, off, s32 offset:256
-; GFX11-NEXT:    scratch_load_u16 v96, off, s32 offset:252
-; GFX11-NEXT:    scratch_load_u16 v99, off, s32 offset:248
-; GFX11-NEXT:    scratch_load_u16 v97, off, s32 offset:244
-; GFX11-NEXT:    scratch_load_u16 v100, off, s32 offset:240
-; GFX11-NEXT:    scratch_load_u16 v98, off, s32 offset:236
-; GFX11-NEXT:    scratch_load_u16 v101, off, s32 offset:232
-; GFX11-NEXT:    scratch_load_u16 v112, off, s32 offset:228
-; GFX11-NEXT:    scratch_load_u16 v102, off, s32 offset:224
-; GFX11-NEXT:    scratch_load_u16 v113, off, s32 offset:220
-; GFX11-NEXT:    scratch_load_u16 v103, off, s32 offset:216
-; GFX11-NEXT:    scratch_load_b32 v114, off, s32 offset:388
-; GFX11-NEXT:    scratch_load_u16 v115, off, s32
-; GFX11-NEXT:    scratch_load_u16 v116, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_u16 v117, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_u16 v118, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_u16 v119, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_u16 v128, off, s32 offset:40
-; GFX11-NEXT:    scratch_load_u16 v129, off, s32 offset:48
-; GFX11-NEXT:    scratch_load_u16 v130, off, s32 offset:56
-; GFX11-NEXT:    scratch_load_u16 v131, off, s32 offset:64
-; GFX11-NEXT:    scratch_load_u16 v144, off, s32 offset:72
-; GFX11-NEXT:    scratch_load_u16 v145, off, s32 offset:80
-; GFX11-NEXT:    scratch_load_u16 v146, off, s32 offset:88
-; GFX11-NEXT:    scratch_load_u16 v147, off, s32 offset:96
-; GFX11-NEXT:    scratch_load_u16 v148, off, s32 offset:104
-; GFX11-NEXT:    scratch_load_u16 v162, off, s32 offset:112
-; GFX11-NEXT:    scratch_load_u16 v163, off, s32 offset:120
-; GFX11-NEXT:    scratch_load_u16 v164, off, s32 offset:128
-; GFX11-NEXT:    scratch_load_u16 v165, off, s32 offset:136
-; GFX11-NEXT:    scratch_load_u16 v166, off, s32 offset:144
-; GFX11-NEXT:    scratch_load_u16 v179, off, s32 offset:152
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v180, off, s32 offset:160
-; GFX11-NEXT:    scratch_load_u16 v181, off, s32 offset:168
-; GFX11-NEXT:    scratch_load_u16 v182, off, s32 offset:176
-; GFX11-NEXT:    scratch_load_u16 v183, off, s32 offset:184
-; GFX11-NEXT:    scratch_load_u16 v136, off, s32 offset:192
-; GFX11-NEXT:    scratch_load_u16 v137, off, s32 offset:200
-; GFX11-NEXT:    scratch_load_u16 v138, off, s32 offset:208
-; GFX11-NEXT:    scratch_load_u16 v132, off, s32 offset:212
-; GFX11-NEXT:    scratch_load_u16 v133, off, s32 offset:204
-; GFX11-NEXT:    scratch_load_u16 v134, off, s32 offset:196
-; GFX11-NEXT:    scratch_load_u16 v135, off, s32 offset:188
-; GFX11-NEXT:    scratch_load_u16 v149, off, s32 offset:180
-; GFX11-NEXT:    scratch_load_u16 v150, off, s32 offset:172
-; GFX11-NEXT:    scratch_load_u16 v151, off, s32 offset:164
-; GFX11-NEXT:    scratch_load_u16 v160, off, s32 offset:156
-; GFX11-NEXT:    scratch_load_u16 v161, off, s32 offset:148
-; GFX11-NEXT:    scratch_load_u16 v167, off, s32 offset:140
-; GFX11-NEXT:    scratch_load_u16 v176, off, s32 offset:132
-; GFX11-NEXT:    scratch_load_u16 v177, off, s32 offset:124
-; GFX11-NEXT:    scratch_load_u16 v178, off, s32 offset:116
-; GFX11-NEXT:    scratch_load_u16 v40, off, s32 offset:108
-; GFX11-NEXT:    scratch_load_u16 v41, off, s32 offset:100
-; GFX11-NEXT:    scratch_load_u16 v42, off, s32 offset:92
-; GFX11-NEXT:    scratch_load_u16 v43, off, s32 offset:84
-; GFX11-NEXT:    scratch_load_u16 v44, off, s32 offset:76
-; GFX11-NEXT:    scratch_load_u16 v58, off, s32 offset:68
-; GFX11-NEXT:    scratch_load_u16 v59, off, s32 offset:60
-; GFX11-NEXT:    scratch_load_u16 v60, off, s32 offset:52
-; GFX11-NEXT:    scratch_load_u16 v74, off, s32 offset:44
-; GFX11-NEXT:    scratch_load_u16 v75, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_u16 v76, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_u16 v77, off, s32 offset:20
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_u16 v78, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_u16 v92, off, s32 offset:4
-; GFX11-NEXT:    v_lshlrev_b16 v124, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v125, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v126, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v127, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v111, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v120, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v121, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v122, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v123, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v106, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v107, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v108, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v109, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v110, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v93, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(54)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v114
-; GFX11-NEXT:    s_waitcnt vmcnt(53)
-; GFX11-NEXT:    v_lshlrev_b16 v94, 8, v115
-; GFX11-NEXT:    s_waitcnt vmcnt(52)
-; GFX11-NEXT:    v_lshlrev_b16 v95, 8, v116
-; GFX11-NEXT:    s_waitcnt vmcnt(51)
-; GFX11-NEXT:    v_lshlrev_b16 v104, 8, v117
-; GFX11-NEXT:    s_waitcnt vmcnt(50)
-; GFX11-NEXT:    v_lshlrev_b16 v105, 8, v118
-; GFX11-NEXT:    s_waitcnt vmcnt(49)
-; GFX11-NEXT:    v_lshlrev_b16 v79, 8, v119
-; GFX11-NEXT:    s_waitcnt vmcnt(48)
-; GFX11-NEXT:    v_lshlrev_b16 v88, 8, v128
-; GFX11-NEXT:    s_waitcnt vmcnt(47)
-; GFX11-NEXT:    v_lshlrev_b16 v89, 8, v129
-; GFX11-NEXT:    s_waitcnt vmcnt(46)
-; GFX11-NEXT:    v_lshlrev_b16 v90, 8, v130
-; GFX11-NEXT:    s_waitcnt vmcnt(45)
-; GFX11-NEXT:    v_lshlrev_b16 v91, 8, v131
-; GFX11-NEXT:    s_waitcnt vmcnt(44)
-; GFX11-NEXT:    v_lshlrev_b16 v61, 8, v144
-; GFX11-NEXT:    s_waitcnt vmcnt(43)
-; GFX11-NEXT:    v_lshlrev_b16 v62, 8, v145
-; GFX11-NEXT:    s_waitcnt vmcnt(42)
-; GFX11-NEXT:    v_lshlrev_b16 v63, 8, v146
-; GFX11-NEXT:    s_waitcnt vmcnt(41)
-; GFX11-NEXT:    v_lshlrev_b16 v72, 8, v147
-; GFX11-NEXT:    s_waitcnt vmcnt(40)
-; GFX11-NEXT:    v_lshlrev_b16 v73, 8, v148
-; GFX11-NEXT:    s_waitcnt vmcnt(39)
-; GFX11-NEXT:    v_lshlrev_b16 v45, 8, v162
-; GFX11-NEXT:    s_waitcnt vmcnt(38)
-; GFX11-NEXT:    v_lshlrev_b16 v46, 8, v163
-; GFX11-NEXT:    s_waitcnt vmcnt(37)
-; GFX11-NEXT:    v_lshlrev_b16 v47, 8, v164
-; GFX11-NEXT:    s_waitcnt vmcnt(36)
-; GFX11-NEXT:    v_lshlrev_b16 v56, 8, v165
-; GFX11-NEXT:    s_waitcnt vmcnt(35)
-; GFX11-NEXT:    v_lshlrev_b16 v57, 8, v166
-; GFX11-NEXT:    s_waitcnt vmcnt(34)
-; GFX11-NEXT:    v_lshlrev_b16 v179, 8, v179
-; GFX11-NEXT:    s_waitcnt vmcnt(33)
-; GFX11-NEXT:    v_lshlrev_b16 v180, 8, v180
-; GFX11-NEXT:    s_waitcnt vmcnt(32)
-; GFX11-NEXT:    v_lshlrev_b16 v181, 8, v181
-; GFX11-NEXT:    s_waitcnt vmcnt(31)
-; GFX11-NEXT:    v_lshlrev_b16 v182, 8, v182
-; GFX11-NEXT:    s_waitcnt vmcnt(30)
-; GFX11-NEXT:    v_lshlrev_b16 v183, 8, v183
-; GFX11-NEXT:    s_waitcnt vmcnt(29)
-; GFX11-NEXT:    v_lshlrev_b16 v162, 8, v136
-; GFX11-NEXT:    s_waitcnt vmcnt(28)
-; GFX11-NEXT:    v_lshlrev_b16 v163, 8, v137
-; GFX11-NEXT:    s_waitcnt vmcnt(27)
-; GFX11-NEXT:    v_lshlrev_b16 v164, 8, v138
-; GFX11-NEXT:    v_lshlrev_b16 v165, 8, v103
-; GFX11-NEXT:    v_lshlrev_b16 v166, 8, v102
-; GFX11-NEXT:    v_lshlrev_b16 v144, 8, v101
-; GFX11-NEXT:    v_lshlrev_b16 v145, 8, v100
-; GFX11-NEXT:    v_lshlrev_b16 v146, 8, v99
-; GFX11-NEXT:    v_lshlrev_b16 v147, 8, v31
-; GFX11-NEXT:    v_lshlrev_b16 v148, 8, v30
-; GFX11-NEXT:    v_lshlrev_b16 v119, 8, v28
-; GFX11-NEXT:    v_lshlrev_b16 v128, 8, v26
-; GFX11-NEXT:    v_lshlrev_b16 v129, 8, v24
-; GFX11-NEXT:    v_lshlrev_b16 v130, 8, v22
-; GFX11-NEXT:    v_lshlrev_b16 v131, 8, v20
-; GFX11-NEXT:    v_lshlrev_b16 v114, 8, v18
-; GFX11-NEXT:    v_lshlrev_b16 v115, 8, v16
-; GFX11-NEXT:    v_lshlrev_b16 v116, 8, v14
-; GFX11-NEXT:    v_lshlrev_b16 v117, 8, v12
-; GFX11-NEXT:    v_lshlrev_b16 v118, 8, v10
-; GFX11-NEXT:    v_lshlrev_b16 v99, 8, v8
-; GFX11-NEXT:    v_lshlrev_b16 v100, 8, v6
-; GFX11-NEXT:    v_lshlrev_b16 v101, 8, v4
-; GFX11-NEXT:    v_lshlrev_b16 v102, 8, v2
-; GFX11-NEXT:    v_lshlrev_b16 v103, 8, v0
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB37_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v55
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v54
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v53
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v52
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v51
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v124
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v125
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v126
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v127
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v50
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v39
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v37
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v36
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v49
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v48
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v35
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v34
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v111
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v121
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v120
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v122
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v123
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v107
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v2
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v38
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v108
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v109
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v110
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v106
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v3, v7, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v6, v12
-; GFX11-NEXT:    v_or_b32_e32 v5, v8, v9
-; GFX11-NEXT:    v_or_b32_e32 v6, v10, v11
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v32
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v92
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v78
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v77
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v76
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v75
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v74
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v60
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v59
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v93
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v94
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v95
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v104
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v105
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v79
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v88
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v89
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v90
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v91
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v8, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v9, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v10, v13, v14
-; GFX11-NEXT:    v_or_b32_e32 v11, v15, v16
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v58
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v44
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v43
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v42
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v41
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v40
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v178
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v177
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v176
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v167
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v61
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v62
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v63
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v72
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v73
-; GFX11-NEXT:    v_or_b32_e32 v17, v17, v45
-; GFX11-NEXT:    v_or_b32_e32 v18, v18, v46
-; GFX11-NEXT:    v_or_b32_e32 v19, v19, v47
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v56
-; GFX11-NEXT:    v_or_b32_e32 v21, v21, v57
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xffff, v18
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xffff, v20
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v13, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v14, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v15, v18, v19
-; GFX11-NEXT:    v_or_b32_e32 v16, v20, v21
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v161
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v160
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v151
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v150
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v149
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v135
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v134
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v133
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v132
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v113
-; GFX11-NEXT:    v_or_b32_e32 v17, v17, v179
-; GFX11-NEXT:    v_or_b32_e32 v18, v18, v180
-; GFX11-NEXT:    v_or_b32_e32 v19, v19, v181
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v182
-; GFX11-NEXT:    v_or_b32_e32 v21, v21, v183
-; GFX11-NEXT:    v_or_b32_e32 v22, v22, v162
-; GFX11-NEXT:    v_or_b32_e32 v23, v23, v163
-; GFX11-NEXT:    v_or_b32_e32 v24, v24, v164
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v165
-; GFX11-NEXT:    v_or_b32_e32 v26, v26, v166
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff, v19
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xffff, v21
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xffff, v23
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xffff, v25
-; GFX11-NEXT:    v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-NEXT:    v_or_b32_e32 v17, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v18, v19, v20
-; GFX11-NEXT:    v_or_b32_e32 v19, v21, v22
-; GFX11-NEXT:    v_or_b32_e32 v20, v23, v24
-; GFX11-NEXT:    v_or_b32_e32 v21, v25, v26
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v112
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v98
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v97
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v96
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v87
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v86
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v85
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v84
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v83
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v82
-; GFX11-NEXT:    v_or_b32_e32 v22, v22, v144
-; GFX11-NEXT:    v_or_b32_e32 v23, v23, v145
-; GFX11-NEXT:    v_or_b32_e32 v24, v24, v146
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v147
-; GFX11-NEXT:    v_or_b32_e32 v26, v26, v148
-; GFX11-NEXT:    v_or_b32_e32 v27, v27, v119
-; GFX11-NEXT:    v_or_b32_e32 v28, v28, v128
-; GFX11-NEXT:    v_or_b32_e32 v29, v29, v129
-; GFX11-NEXT:    v_or_b32_e32 v30, v30, v130
-; GFX11-NEXT:    v_or_b32_e32 v31, v31, v131
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xffff, v22
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xffff, v24
-; GFX11-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xffff, v26
-; GFX11-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xffff, v28
-; GFX11-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xffff, v30
-; GFX11-NEXT:    v_lshlrev_b32_e32 v31, 16, v31
-; GFX11-NEXT:    v_or_b32_e32 v22, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v23, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v24, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v25, v28, v29
-; GFX11-NEXT:    v_or_b32_e32 v26, v30, v31
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v81
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v80
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v71
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v70
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v69
-; GFX11-NEXT:    v_and_b32_e32 v32, 0xff, v68
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xff, v67
-; GFX11-NEXT:    v_and_b32_e32 v34, 0xff, v66
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xff, v65
-; GFX11-NEXT:    v_and_b32_e32 v36, 0xff, v64
-; GFX11-NEXT:    v_or_b32_e32 v27, v27, v114
-; GFX11-NEXT:    v_or_b32_e32 v28, v28, v115
-; GFX11-NEXT:    v_or_b32_e32 v29, v29, v116
-; GFX11-NEXT:    v_or_b32_e32 v30, v30, v117
-; GFX11-NEXT:    v_or_b32_e32 v31, v31, v118
-; GFX11-NEXT:    v_or_b32_e32 v32, v32, v99
-; GFX11-NEXT:    v_or_b32_e32 v33, v33, v100
-; GFX11-NEXT:    v_or_b32_e32 v34, v34, v101
-; GFX11-NEXT:    v_or_b32_e32 v35, v35, v102
-; GFX11-NEXT:    v_or_b32_e32 v36, v36, v103
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xffff, v27
-; GFX11-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xffff, v29
-; GFX11-NEXT:    v_lshlrev_b32_e32 v30, 16, v30
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xffff, v31
-; GFX11-NEXT:    v_lshlrev_b32_e32 v32, 16, v32
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xffff, v33
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v34
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xffff, v35
-; GFX11-NEXT:    v_lshlrev_b32_e32 v36, 16, v36
-; GFX11-NEXT:    v_or_b32_e32 v27, v27, v28
-; GFX11-NEXT:    v_or_b32_e32 v28, v29, v30
-; GFX11-NEXT:    v_or_b32_e32 v29, v31, v32
-; GFX11-NEXT:    v_or_b32_e32 v30, v33, v34
-; GFX11-NEXT:    v_or_b32_e32 v31, v35, v36
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr92
-; GFX11-NEXT:    ; implicit-def: $vgpr78
-; GFX11-NEXT:    ; implicit-def: $vgpr77
-; GFX11-NEXT:    ; implicit-def: $vgpr76
-; GFX11-NEXT:    ; implicit-def: $vgpr75
-; GFX11-NEXT:    ; implicit-def: $vgpr74
-; GFX11-NEXT:    ; implicit-def: $vgpr60
-; GFX11-NEXT:    ; implicit-def: $vgpr59
-; GFX11-NEXT:    ; implicit-def: $vgpr58
-; GFX11-NEXT:    ; implicit-def: $vgpr44
-; GFX11-NEXT:    ; implicit-def: $vgpr43
-; GFX11-NEXT:    ; implicit-def: $vgpr42
-; GFX11-NEXT:    ; implicit-def: $vgpr41
-; GFX11-NEXT:    ; implicit-def: $vgpr40
-; GFX11-NEXT:    ; implicit-def: $vgpr178
-; GFX11-NEXT:    ; implicit-def: $vgpr177
-; GFX11-NEXT:    ; implicit-def: $vgpr176
-; GFX11-NEXT:    ; implicit-def: $vgpr167
-; GFX11-NEXT:    ; implicit-def: $vgpr161
-; GFX11-NEXT:    ; implicit-def: $vgpr160
-; GFX11-NEXT:    ; implicit-def: $vgpr151
-; GFX11-NEXT:    ; implicit-def: $vgpr150
-; GFX11-NEXT:    ; implicit-def: $vgpr149
-; GFX11-NEXT:    ; implicit-def: $vgpr135
-; GFX11-NEXT:    ; implicit-def: $vgpr134
-; GFX11-NEXT:    ; implicit-def: $vgpr133
-; GFX11-NEXT:    ; implicit-def: $vgpr132
-; GFX11-NEXT:    ; implicit-def: $vgpr113
-; GFX11-NEXT:    ; implicit-def: $vgpr112
-; GFX11-NEXT:    ; implicit-def: $vgpr98
-; GFX11-NEXT:    ; implicit-def: $vgpr97
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr67
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr124
-; GFX11-NEXT:    ; implicit-def: $vgpr125
-; GFX11-NEXT:    ; implicit-def: $vgpr126
-; GFX11-NEXT:    ; implicit-def: $vgpr127
-; GFX11-NEXT:    ; implicit-def: $vgpr111
-; GFX11-NEXT:    ; implicit-def: $vgpr120
-; GFX11-NEXT:    ; implicit-def: $vgpr121
-; GFX11-NEXT:    ; implicit-def: $vgpr122
-; GFX11-NEXT:    ; implicit-def: $vgpr123
-; GFX11-NEXT:    ; implicit-def: $vgpr106
-; GFX11-NEXT:    ; implicit-def: $vgpr107
-; GFX11-NEXT:    ; implicit-def: $vgpr108
-; GFX11-NEXT:    ; implicit-def: $vgpr109
-; GFX11-NEXT:    ; implicit-def: $vgpr110
-; GFX11-NEXT:    ; implicit-def: $vgpr93
-; GFX11-NEXT:    ; implicit-def: $vgpr94
-; GFX11-NEXT:    ; implicit-def: $vgpr95
-; GFX11-NEXT:    ; implicit-def: $vgpr104
-; GFX11-NEXT:    ; implicit-def: $vgpr105
-; GFX11-NEXT:    ; implicit-def: $vgpr79
-; GFX11-NEXT:    ; implicit-def: $vgpr88
-; GFX11-NEXT:    ; implicit-def: $vgpr89
-; GFX11-NEXT:    ; implicit-def: $vgpr90
-; GFX11-NEXT:    ; implicit-def: $vgpr91
-; GFX11-NEXT:    ; implicit-def: $vgpr61
-; GFX11-NEXT:    ; implicit-def: $vgpr62
-; GFX11-NEXT:    ; implicit-def: $vgpr63
-; GFX11-NEXT:    ; implicit-def: $vgpr72
-; GFX11-NEXT:    ; implicit-def: $vgpr73
-; GFX11-NEXT:    ; implicit-def: $vgpr45
-; GFX11-NEXT:    ; implicit-def: $vgpr46
-; GFX11-NEXT:    ; implicit-def: $vgpr47
-; GFX11-NEXT:    ; implicit-def: $vgpr56
-; GFX11-NEXT:    ; implicit-def: $vgpr57
-; GFX11-NEXT:    ; implicit-def: $vgpr179
-; GFX11-NEXT:    ; implicit-def: $vgpr180
-; GFX11-NEXT:    ; implicit-def: $vgpr181
-; GFX11-NEXT:    ; implicit-def: $vgpr182
-; GFX11-NEXT:    ; implicit-def: $vgpr183
-; GFX11-NEXT:    ; implicit-def: $vgpr162
-; GFX11-NEXT:    ; implicit-def: $vgpr163
-; GFX11-NEXT:    ; implicit-def: $vgpr164
-; GFX11-NEXT:    ; implicit-def: $vgpr165
-; GFX11-NEXT:    ; implicit-def: $vgpr166
-; GFX11-NEXT:    ; implicit-def: $vgpr144
-; GFX11-NEXT:    ; implicit-def: $vgpr145
-; GFX11-NEXT:    ; implicit-def: $vgpr146
-; GFX11-NEXT:    ; implicit-def: $vgpr147
-; GFX11-NEXT:    ; implicit-def: $vgpr148
-; GFX11-NEXT:    ; implicit-def: $vgpr119
-; GFX11-NEXT:    ; implicit-def: $vgpr128
-; GFX11-NEXT:    ; implicit-def: $vgpr129
-; GFX11-NEXT:    ; implicit-def: $vgpr130
-; GFX11-NEXT:    ; implicit-def: $vgpr131
-; GFX11-NEXT:    ; implicit-def: $vgpr114
-; GFX11-NEXT:    ; implicit-def: $vgpr115
-; GFX11-NEXT:    ; implicit-def: $vgpr116
-; GFX11-NEXT:    ; implicit-def: $vgpr117
-; GFX11-NEXT:    ; implicit-def: $vgpr118
-; GFX11-NEXT:    ; implicit-def: $vgpr99
-; GFX11-NEXT:    ; implicit-def: $vgpr100
-; GFX11-NEXT:    ; implicit-def: $vgpr101
-; GFX11-NEXT:    ; implicit-def: $vgpr102
-; GFX11-NEXT:    ; implicit-def: $vgpr103
-; GFX11-NEXT:  .LBB37_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB37_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v55, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v54, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v53, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v52, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v51, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_add_nc_u16 v5, v50, 3
-; GFX11-NEXT:    v_or_b32_e32 v0, v124, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v125, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v126, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v127, v3
-; GFX11-NEXT:    v_add_nc_u16 v6, v49, 3
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v7, v48, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_add_nc_u16 v8, v37, 3
-; GFX11-NEXT:    v_add_nc_u16 v9, v36, 3
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_add_nc_u16 v10, v35, 3
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_add_nc_u16 v2, v39, 3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v5
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v11, v34, 3
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v2, v123, v2
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_or_b32_e32 v3, v111, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v120, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v121, v5
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v6, v122, v6
-; GFX11-NEXT:    v_or_b32_e32 v8, v107, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v108, v9
-; GFX11-NEXT:    v_or_b32_e32 v10, v109, v10
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v38, 3
-; GFX11-NEXT:    v_or_b32_e32 v11, v110, v11
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v10
-; GFX11-NEXT:    v_or_b32_e32 v2, v106, v2
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v11
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_or_b32_e32 v2, v3, v4
-; GFX11-NEXT:    v_or_b32_e32 v3, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v5, v8, v9
-; GFX11-NEXT:    v_or_b32_e32 v4, v7, v12
-; GFX11-NEXT:    v_or_b32_e32 v6, v10, v11
-; GFX11-NEXT:    v_add_nc_u16 v7, v33, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v32, 3
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_nc_u16 v9, v92, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, v78, 3
-; GFX11-NEXT:    v_add_nc_u16 v11, v77, 3
-; GFX11-NEXT:    v_add_nc_u16 v12, v76, 3
-; GFX11-NEXT:    v_add_nc_u16 v13, v75, 3
-; GFX11-NEXT:    v_add_nc_u16 v14, v74, 3
-; GFX11-NEXT:    v_add_nc_u16 v15, v60, 3
-; GFX11-NEXT:    v_add_nc_u16 v16, v59, 3
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_or_b32_e32 v7, v93, v7
-; GFX11-NEXT:    v_or_b32_e32 v8, v94, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v95, v9
-; GFX11-NEXT:    v_or_b32_e32 v10, v104, v10
-; GFX11-NEXT:    v_or_b32_e32 v11, v105, v11
-; GFX11-NEXT:    v_or_b32_e32 v12, v79, v12
-; GFX11-NEXT:    v_or_b32_e32 v13, v88, v13
-; GFX11-NEXT:    v_or_b32_e32 v14, v89, v14
-; GFX11-NEXT:    v_or_b32_e32 v15, v90, v15
-; GFX11-NEXT:    v_or_b32_e32 v16, v91, v16
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v10
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v11
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v12
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v13
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v14
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v15
-; GFX11-NEXT:    v_add_nc_u16 v16, 0x300, v16
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v8, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v9, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v10, v13, v14
-; GFX11-NEXT:    v_or_b32_e32 v11, v15, v16
-; GFX11-NEXT:    v_add_nc_u16 v12, v58, 3
-; GFX11-NEXT:    v_add_nc_u16 v13, v44, 3
-; GFX11-NEXT:    v_add_nc_u16 v14, v43, 3
-; GFX11-NEXT:    v_add_nc_u16 v15, v42, 3
-; GFX11-NEXT:    v_add_nc_u16 v16, v41, 3
-; GFX11-NEXT:    v_add_nc_u16 v17, v40, 3
-; GFX11-NEXT:    v_add_nc_u16 v18, v178, 3
-; GFX11-NEXT:    v_add_nc_u16 v19, v177, 3
-; GFX11-NEXT:    v_add_nc_u16 v20, v176, 3
-; GFX11-NEXT:    v_add_nc_u16 v21, v167, 3
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v17
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v19
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v21
-; GFX11-NEXT:    v_or_b32_e32 v12, v61, v12
-; GFX11-NEXT:    v_or_b32_e32 v13, v62, v13
-; GFX11-NEXT:    v_or_b32_e32 v14, v63, v14
-; GFX11-NEXT:    v_or_b32_e32 v15, v72, v15
-; GFX11-NEXT:    v_or_b32_e32 v16, v73, v16
-; GFX11-NEXT:    v_or_b32_e32 v17, v45, v17
-; GFX11-NEXT:    v_or_b32_e32 v18, v46, v18
-; GFX11-NEXT:    v_or_b32_e32 v19, v47, v19
-; GFX11-NEXT:    v_or_b32_e32 v20, v56, v20
-; GFX11-NEXT:    v_or_b32_e32 v21, v57, v21
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v12
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v13
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v14
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v15
-; GFX11-NEXT:    v_add_nc_u16 v16, 0x300, v16
-; GFX11-NEXT:    v_add_nc_u16 v17, 0x300, v17
-; GFX11-NEXT:    v_add_nc_u16 v18, 0x300, v18
-; GFX11-NEXT:    v_add_nc_u16 v19, 0x300, v19
-; GFX11-NEXT:    v_add_nc_u16 v20, 0x300, v20
-; GFX11-NEXT:    v_add_nc_u16 v21, 0x300, v21
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xffff, v18
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xffff, v20
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v13, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v14, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v15, v18, v19
-; GFX11-NEXT:    v_or_b32_e32 v16, v20, v21
-; GFX11-NEXT:    v_add_nc_u16 v17, v161, 3
-; GFX11-NEXT:    v_add_nc_u16 v18, v160, 3
-; GFX11-NEXT:    v_add_nc_u16 v19, v151, 3
-; GFX11-NEXT:    v_add_nc_u16 v20, v150, 3
-; GFX11-NEXT:    v_add_nc_u16 v21, v149, 3
-; GFX11-NEXT:    v_add_nc_u16 v22, v135, 3
-; GFX11-NEXT:    v_add_nc_u16 v23, v134, 3
-; GFX11-NEXT:    v_add_nc_u16 v24, v133, 3
-; GFX11-NEXT:    v_add_nc_u16 v25, v132, 3
-; GFX11-NEXT:    v_add_nc_u16 v26, v113, 3
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v17
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v19
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v21
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v23
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v24
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v25
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v26
-; GFX11-NEXT:    v_or_b32_e32 v17, v179, v17
-; GFX11-NEXT:    v_or_b32_e32 v18, v180, v18
-; GFX11-NEXT:    v_or_b32_e32 v19, v181, v19
-; GFX11-NEXT:    v_or_b32_e32 v20, v182, v20
-; GFX11-NEXT:    v_or_b32_e32 v21, v183, v21
-; GFX11-NEXT:    v_or_b32_e32 v22, v162, v22
-; GFX11-NEXT:    v_or_b32_e32 v23, v163, v23
-; GFX11-NEXT:    v_or_b32_e32 v24, v164, v24
-; GFX11-NEXT:    v_or_b32_e32 v25, v165, v25
-; GFX11-NEXT:    v_or_b32_e32 v26, v166, v26
-; GFX11-NEXT:    v_add_nc_u16 v17, 0x300, v17
-; GFX11-NEXT:    v_add_nc_u16 v18, 0x300, v18
-; GFX11-NEXT:    v_add_nc_u16 v19, 0x300, v19
-; GFX11-NEXT:    v_add_nc_u16 v20, 0x300, v20
-; GFX11-NEXT:    v_add_nc_u16 v21, 0x300, v21
-; GFX11-NEXT:    v_add_nc_u16 v22, 0x300, v22
-; GFX11-NEXT:    v_add_nc_u16 v23, 0x300, v23
-; GFX11-NEXT:    v_add_nc_u16 v24, 0x300, v24
-; GFX11-NEXT:    v_add_nc_u16 v25, 0x300, v25
-; GFX11-NEXT:    v_add_nc_u16 v26, 0x300, v26
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff, v19
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xffff, v21
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xffff, v23
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xffff, v25
-; GFX11-NEXT:    v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-NEXT:    v_or_b32_e32 v17, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v18, v19, v20
-; GFX11-NEXT:    v_or_b32_e32 v19, v21, v22
-; GFX11-NEXT:    v_or_b32_e32 v20, v23, v24
-; GFX11-NEXT:    v_or_b32_e32 v21, v25, v26
-; GFX11-NEXT:    v_add_nc_u16 v22, v112, 3
-; GFX11-NEXT:    v_add_nc_u16 v23, v98, 3
-; GFX11-NEXT:    v_add_nc_u16 v24, v97, 3
-; GFX11-NEXT:    v_add_nc_u16 v25, v96, 3
-; GFX11-NEXT:    v_add_nc_u16 v26, v87, 3
-; GFX11-NEXT:    v_add_nc_u16 v27, v86, 3
-; GFX11-NEXT:    v_add_nc_u16 v28, v85, 3
-; GFX11-NEXT:    v_add_nc_u16 v29, v84, 3
-; GFX11-NEXT:    v_add_nc_u16 v30, v83, 3
-; GFX11-NEXT:    v_add_nc_u16 v31, v82, 3
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v23
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v24
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v25
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v26
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v27
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v29
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v30
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v31
-; GFX11-NEXT:    v_or_b32_e32 v22, v144, v22
-; GFX11-NEXT:    v_or_b32_e32 v23, v145, v23
-; GFX11-NEXT:    v_or_b32_e32 v24, v146, v24
-; GFX11-NEXT:    v_or_b32_e32 v25, v147, v25
-; GFX11-NEXT:    v_or_b32_e32 v26, v148, v26
-; GFX11-NEXT:    v_or_b32_e32 v27, v119, v27
-; GFX11-NEXT:    v_or_b32_e32 v28, v128, v28
-; GFX11-NEXT:    v_or_b32_e32 v29, v129, v29
-; GFX11-NEXT:    v_or_b32_e32 v30, v130, v30
-; GFX11-NEXT:    v_or_b32_e32 v31, v131, v31
-; GFX11-NEXT:    v_add_nc_u16 v22, 0x300, v22
-; GFX11-NEXT:    v_add_nc_u16 v23, 0x300, v23
-; GFX11-NEXT:    v_add_nc_u16 v24, 0x300, v24
-; GFX11-NEXT:    v_add_nc_u16 v25, 0x300, v25
-; GFX11-NEXT:    v_add_nc_u16 v26, 0x300, v26
-; GFX11-NEXT:    v_add_nc_u16 v27, 0x300, v27
-; GFX11-NEXT:    v_add_nc_u16 v28, 0x300, v28
-; GFX11-NEXT:    v_add_nc_u16 v29, 0x300, v29
-; GFX11-NEXT:    v_add_nc_u16 v30, 0x300, v30
-; GFX11-NEXT:    v_add_nc_u16 v31, 0x300, v31
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xffff, v22
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xffff, v24
-; GFX11-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xffff, v26
-; GFX11-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xffff, v28
-; GFX11-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xffff, v30
-; GFX11-NEXT:    v_lshlrev_b32_e32 v31, 16, v31
-; GFX11-NEXT:    v_or_b32_e32 v22, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v23, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v24, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v25, v28, v29
-; GFX11-NEXT:    v_or_b32_e32 v26, v30, v31
-; GFX11-NEXT:    v_add_nc_u16 v27, v81, 3
-; GFX11-NEXT:    v_add_nc_u16 v28, v80, 3
-; GFX11-NEXT:    v_add_nc_u16 v29, v71, 3
-; GFX11-NEXT:    v_add_nc_u16 v30, v70, 3
-; GFX11-NEXT:    v_add_nc_u16 v31, v69, 3
-; GFX11-NEXT:    v_add_nc_u16 v32, v68, 3
-; GFX11-NEXT:    v_add_nc_u16 v33, v67, 3
-; GFX11-NEXT:    v_add_nc_u16 v34, v66, 3
-; GFX11-NEXT:    v_add_nc_u16 v35, v65, 3
-; GFX11-NEXT:    v_add_nc_u16 v36, v64, 3
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v27
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v29
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v30
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v31
-; GFX11-NEXT:    v_and_b32_e32 v32, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v34, 0xff, v34
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xff, v35
-; GFX11-NEXT:    v_and_b32_e32 v36, 0xff, v36
-; GFX11-NEXT:    v_or_b32_e32 v27, v114, v27
-; GFX11-NEXT:    v_or_b32_e32 v28, v115, v28
-; GFX11-NEXT:    v_or_b32_e32 v29, v116, v29
-; GFX11-NEXT:    v_or_b32_e32 v30, v117, v30
-; GFX11-NEXT:    v_or_b32_e32 v31, v118, v31
-; GFX11-NEXT:    v_or_b32_e32 v32, v99, v32
-; GFX11-NEXT:    v_or_b32_e32 v33, v100, v33
-; GFX11-NEXT:    v_or_b32_e32 v34, v101, v34
-; GFX11-NEXT:    v_or_b32_e32 v35, v102, v35
-; GFX11-NEXT:    v_or_b32_e32 v36, v103, v36
-; GFX11-NEXT:    v_add_nc_u16 v27, 0x300, v27
-; GFX11-NEXT:    v_add_nc_u16 v28, 0x300, v28
-; GFX11-NEXT:    v_add_nc_u16 v29, 0x300, v29
-; GFX11-NEXT:    v_add_nc_u16 v30, 0x300, v30
-; GFX11-NEXT:    v_add_nc_u16 v31, 0x300, v31
-; GFX11-NEXT:    v_add_nc_u16 v32, 0x300, v32
-; GFX11-NEXT:    v_add_nc_u16 v33, 0x300, v33
-; GFX11-NEXT:    v_add_nc_u16 v34, 0x300, v34
-; GFX11-NEXT:    v_add_nc_u16 v35, 0x300, v35
-; GFX11-NEXT:    v_add_nc_u16 v36, 0x300, v36
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xffff, v27
-; GFX11-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xffff, v29
-; GFX11-NEXT:    v_lshlrev_b32_e32 v30, 16, v30
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xffff, v31
-; GFX11-NEXT:    v_lshlrev_b32_e32 v32, 16, v32
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xffff, v33
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v34
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xffff, v35
-; GFX11-NEXT:    v_lshlrev_b32_e32 v36, 16, v36
-; GFX11-NEXT:    v_or_b32_e32 v27, v27, v28
-; GFX11-NEXT:    v_or_b32_e32 v28, v29, v30
-; GFX11-NEXT:    v_or_b32_e32 v29, v31, v32
-; GFX11-NEXT:    v_or_b32_e32 v30, v33, v34
-; GFX11-NEXT:    v_or_b32_e32 v31, v35, v36
-; GFX11-NEXT:  .LBB37_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_b32 v138, off, s32 offset:392
-; GFX11-NEXT:    scratch_load_b32 v137, off, s32 offset:396
-; GFX11-NEXT:    scratch_load_b32 v136, off, s32 offset:400
-; GFX11-NEXT:    scratch_load_b32 v127, off, s32 offset:404
-; GFX11-NEXT:    scratch_load_b32 v126, off, s32 offset:408
-; GFX11-NEXT:    scratch_load_b32 v125, off, s32 offset:412
-; GFX11-NEXT:    scratch_load_b32 v124, off, s32 offset:416
-; GFX11-NEXT:    scratch_load_b32 v123, off, s32 offset:420
-; GFX11-NEXT:    scratch_load_b32 v122, off, s32 offset:424
-; GFX11-NEXT:    scratch_load_b32 v121, off, s32 offset:428
-; GFX11-NEXT:    scratch_load_b32 v120, off, s32 offset:432
-; GFX11-NEXT:    scratch_load_b32 v111, off, s32 offset:436
-; GFX11-NEXT:    scratch_load_b32 v110, off, s32 offset:440
-; GFX11-NEXT:    scratch_load_b32 v109, off, s32 offset:444
-; GFX11-NEXT:    scratch_load_b32 v108, off, s32 offset:448
-; GFX11-NEXT:    scratch_load_b32 v107, off, s32 offset:452
-; GFX11-NEXT:    scratch_load_b32 v106, off, s32 offset:456
-; GFX11-NEXT:    scratch_load_b32 v105, off, s32 offset:460
-; GFX11-NEXT:    scratch_load_b32 v104, off, s32 offset:464
-; GFX11-NEXT:    scratch_load_b32 v95, off, s32 offset:468
-; GFX11-NEXT:    scratch_load_b32 v94, off, s32 offset:472
-; GFX11-NEXT:    scratch_load_b32 v93, off, s32 offset:476
-; GFX11-NEXT:    scratch_load_b32 v92, off, s32 offset:480
-; GFX11-NEXT:    scratch_load_b32 v91, off, s32 offset:484
-; GFX11-NEXT:    scratch_load_b32 v90, off, s32 offset:488
-; GFX11-NEXT:    scratch_load_b32 v89, off, s32 offset:492
-; GFX11-NEXT:    scratch_load_b32 v88, off, s32 offset:496
-; GFX11-NEXT:    scratch_load_b32 v79, off, s32 offset:500
-; GFX11-NEXT:    scratch_load_b32 v78, off, s32 offset:504
-; GFX11-NEXT:    scratch_load_b32 v77, off, s32 offset:508
-; GFX11-NEXT:    scratch_load_b32 v76, off, s32 offset:512
-; GFX11-NEXT:    scratch_load_b32 v75, off, s32 offset:516
-; GFX11-NEXT:    s_clause 0x12
-; GFX11-NEXT:    scratch_load_b32 v74, off, s32 offset:520
-; GFX11-NEXT:    scratch_load_b32 v73, off, s32 offset:524
-; GFX11-NEXT:    scratch_load_b32 v72, off, s32 offset:528
-; GFX11-NEXT:    scratch_load_b32 v63, off, s32 offset:532
-; GFX11-NEXT:    scratch_load_b32 v62, off, s32 offset:536
-; GFX11-NEXT:    scratch_load_b32 v61, off, s32 offset:540
-; GFX11-NEXT:    scratch_load_b32 v60, off, s32 offset:544
-; GFX11-NEXT:    scratch_load_b32 v59, off, s32 offset:548
-; GFX11-NEXT:    scratch_load_b32 v58, off, s32 offset:552
-; GFX11-NEXT:    scratch_load_b32 v57, off, s32 offset:556
-; GFX11-NEXT:    scratch_load_b32 v56, off, s32 offset:560
-; GFX11-NEXT:    scratch_load_b32 v47, off, s32 offset:564
-; GFX11-NEXT:    scratch_load_b32 v46, off, s32 offset:568
-; GFX11-NEXT:    scratch_load_b32 v45, off, s32 offset:572
-; GFX11-NEXT:    scratch_load_b32 v44, off, s32 offset:576
-; GFX11-NEXT:    scratch_load_b32 v43, off, s32 offset:580
-; GFX11-NEXT:    scratch_load_b32 v42, off, s32 offset:584
-; GFX11-NEXT:    scratch_load_b32 v41, off, s32 offset:588
-; GFX11-NEXT:    scratch_load_b32 v40, off, s32 offset:592
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v128i8_to_v16f64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32 offset:384
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v32, off, s32 offset:380
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v31, off, s32 offset:376
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v32, off, s32 offset:372
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v50, off, s32 offset:368
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v33, off, s32 offset:364
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v50, off, s32 offset:360
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v33, off, s32 offset:356
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v49, off, s32 offset:352
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v34, off, s32 offset:348
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v51, off, s32 offset:344
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v34, off, s32 offset:340
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v51, off, s32 offset:336
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v35, off, s32 offset:332
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v54, off, s32 offset:328
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v35, off, s32 offset:324
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v53, off, s32 offset:320
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v36, off, s32 offset:316
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v53, off, s32 offset:312
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v36, off, s32 offset:308
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v54, off, s32 offset:304
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v37, off, s32 offset:300
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v55, off, s32 offset:296
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v37, off, s32 offset:292
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v64, off, s32 offset:288
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v38, off, s32 offset:284
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v64, off, s32 offset:280
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v38, off, s32 offset:276
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v55, off, s32 offset:272
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v39, off, s32 offset:268
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v65, off, s32 offset:264
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v39, off, s32 offset:260
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v65, off, s32 offset:256
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v48, off, s32 offset:252
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v69, off, s32 offset:248
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v48, off, s32 offset:244
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v68, off, s32 offset:240
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v49, off, s32 offset:236
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v68, off, s32 offset:232
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v52, off, s32 offset:228
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v69, off, s32 offset:224
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v52, off, s32 offset:220
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v70, off, s32 offset:216
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v103, off, s32 offset:388
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v81, off, s32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v81, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v82, off, s32 offset:16
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v82, off, s32 offset:24
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v83, off, s32 offset:32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v86, off, s32 offset:40
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v86, off, s32 offset:48
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v87, off, s32 offset:56
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v87, off, s32 offset:64
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v96, off, s32 offset:72
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v99, off, s32 offset:80
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v99, off, s32 offset:88
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v100, off, s32 offset:96
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v100, off, s32 offset:104
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v101, off, s32 offset:112
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v160, off, s32 offset:120
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v160, off, s32 offset:128
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v161, off, s32 offset:136
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v161, off, s32 offset:144
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v162, off, s32 offset:152
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v162, off, s32 offset:160
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v163, off, s32 offset:168
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v163, off, s32 offset:176
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v164, off, s32 offset:184
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v164, off, s32 offset:192
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v165, off, s32 offset:200
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v165, off, s32 offset:208
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v66, off, s32 offset:212
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v66, off, s32 offset:204
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v67, off, s32 offset:196
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v67, off, s32 offset:188
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v70, off, s32 offset:180
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v71, off, s32 offset:172
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v71, off, s32 offset:164
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v80, off, s32 offset:156
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v80, off, s32 offset:148
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v83, off, s32 offset:140
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v84, off, s32 offset:132
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v84, off, s32 offset:124
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v85, off, s32 offset:116
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v85, off, s32 offset:108
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v96, off, s32 offset:100
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v97, off, s32 offset:92
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v97, off, s32 offset:84
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v98, off, s32 offset:76
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v98, off, s32 offset:68
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v101, off, s32 offset:60
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v102, off, s32 offset:52
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v102, off, s32 offset:44
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v113, off, s32 offset:36
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v114, off, s32 offset:28
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v114, off, s32 offset:20
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v115, off, s32 offset:12
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v115, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v118.h, v30.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v119.l, v28.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v119.h, v26.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v130.h, v24.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v131.l, v22.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v131.h, v20.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v132.l, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v135.l, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v135.h, v14.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v144.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v144.h, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v145.l, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v148.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v148.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v149.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v149.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v150.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v150.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v151.l, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v151.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v145.h, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v146.l, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v146.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v147.l, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v147.h, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v132.h, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v133.l, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v133.h, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v134.l, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v134.h, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v128.l, 8, v29.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(62)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v50.h, 8, v50.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v50.l, 8, v50.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v49.h, 8, v49.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v54.l, 8, v54.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v53.h, 8, v53.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v53.l, 8, v53.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v64.h, 8, v64.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v64.l, 8, v64.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v55.h, 8, v55.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v69.l, 8, v69.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(61)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v68.h, 8, v68.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(59)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v68.l, 8, v68.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(54)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v103
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(53)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v128.h, 8, v81.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(52)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v129.l, 8, v81.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(51)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v129.h, 8, v82.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(50)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v130.l, 8, v82.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(49)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v116.l, 8, v83.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(48)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v116.h, 8, v86.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(47)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v117.l, 8, v86.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(46)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v117.h, 8, v87.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(45)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v118.l, 8, v87.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(44)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v103.l, 8, v96.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(43)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v103.h, 8, v99.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(42)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v112.l, 8, v99.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(41)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v112.h, 8, v100.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(40)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v113.l, 8, v100.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(39)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v99.l, 8, v101.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(38)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v99.h, 8, v160.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(37)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v100.l, 8, v160.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(36)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v100.h, 8, v161.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(35)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v101.l, 8, v161.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(34)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v86.l, 8, v162.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v86.h, 8, v162.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(32)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v87.l, 8, v163.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v87.h, 8, v163.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(30)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v96.l, 8, v164.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(29)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v81.l, 8, v164.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(28)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v81.h, 8, v165.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(27)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v82.l, 8, v165.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v82.h, 8, v70.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v83.l, 8, v69.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v69.h, 8, v65.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v70.l, 8, v65.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v65.l, 8, v55.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v65.h, 8, v54.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v54.h, 8, v51.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v55.l, 8, v51.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v51.l, 8, v31.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v51.h, 8, v31.l
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB37_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB37_4
+; GFX11-TRUE16-NEXT:  .LBB37_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB37_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v149.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v149.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v148.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v148.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v0.h, v150.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v150.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v151.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v1.h, v151.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v145.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v144.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v145.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v144.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v5
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v135.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v2.h, v146.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v132.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v135.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v146.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v147.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v5
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v131.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v132.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v3.h, v147.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v131.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v119.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v2.h, v133.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v7, v8
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v119.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v6
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v130.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v133.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v134.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v118.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v128.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v3.h, v134.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v9, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v11, v12
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v115.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v114.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v7.h, v128.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v114.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v115.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v129.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v130.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v10
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v113.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v116.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v6, v14
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v8.h, v129.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v102.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v102.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v101.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v7.h, v116.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v12, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v98.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v11
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v117.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v8.h, v117.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v118.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v98.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v97.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v103.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v14, v15
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v16, v17
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v97.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v96.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v12.h, v103.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v112.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v85.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v10, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v11, v19
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v13.h, v112.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v113.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v15
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v85.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v84.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v99.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v16
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v14
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v84.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v83.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v12.h, v99.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v100.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v17, v18
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v80.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v13.h, v100.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v101.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v19, v20
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.h, 0xff, v80.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v71.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v70.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v17.l, v86.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v21, v22
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.h, 0xff, v71.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v17.h, v86.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v18.l, v87.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v19.l, v96.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff, v17
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v67.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v15, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, v16, v24
+; GFX11-TRUE16-NEXT:    v_or_b16 v21.l, v18.h, v87.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v20
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v19
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.h, 0xff, v67.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v66.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.h, 0xff, v66.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v52.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v17.l, v81.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v21
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v17.h, v81.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v18.l, v82.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v21.l, v18.h, v82.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v19.l, v83.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, v22, v23
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v52.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v48.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v19
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v18, v24, v25
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.h, 0xff, v49.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.h, 0xff, v48.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v39.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v22.l, v68.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v23.l, v69.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v19, v26, v27
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, v21, v29
+; GFX11-TRUE16-NEXT:    v_or_b16 v25.l, v22.h, v68.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v26.l, v23.h, v69.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v24.l, v70.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v27, 0xffff, v22
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v29, 0xffff, v23
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v39.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v38.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, v20, v28
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v25
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v26
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff, v24
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.h, 0xff, v38.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.h, 0xff, v37.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v37.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v22.l, v55.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v23.l, v64.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v25.l, v22.h, v64.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v26.l, v23.h, v65.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v24.l, v65.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, v27, v28
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, v29, v30
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.l, 0xff, v36.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.l, 0xff, v35.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v29.l, 0xff, v34.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v26
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v24
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.h, 0xff, v36.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.h, 0xff, v35.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.l, v27.l, v53.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.l, v28.l, v54.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v29.l, v29.l, v55.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v25
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, v31, v37
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v26, v26, v39
+; GFX11-TRUE16-NEXT:    v_or_b16 v30.l, v27.h, v53.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v31.l, v28.h, v54.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v35, 0xffff, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v37, 0xffff, v28
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v29
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.l, 0xff, v34.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.h, 0xff, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.l, 0xff, v33.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.h, 0xff, v32.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v29.l, 0xff, v32.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v25, v25, v38
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v36, 16, v30
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v31
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.l, v27.l, v49.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v30.l, v27.h, v50.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.l, v28.l, v50.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v31.l, v28.h, v51.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v29.l, v29.l, v51.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v30, 0xffff, v30
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v33, 16, v28
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff, v31
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v29
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v27, v35, v36
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v28, v37, v38
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v29, v39, v32
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v30, v30, v33
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v31, v31, v34
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr149_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr148_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr148_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr145_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr144_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr144_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr135_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr132_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr131_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr131_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr130_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr119_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr118_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr115_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr114_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr114_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr97_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr85_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr71_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr67_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr150_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr150_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr151_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr145_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr146_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr147_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr147_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr132_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr133_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr133_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr134_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr134_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr128_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr128_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr129_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr130_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr116_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr116_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr117_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr118_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr103_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr112_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr113_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr99_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr100_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr101_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr86_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr83_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr68_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr70_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB37_2
+; GFX11-TRUE16-NEXT:  .LBB37_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v149.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v149.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v148.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v145.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v148.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v150.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v150.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v151.h, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v145.h, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v151.l, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v144.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v144.l, 3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, v135.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, v135.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v5
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v146.l, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v146.h, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v147.h, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v147.l, v3.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v2
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v132.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v131.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v131.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, v119.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v132.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v133.l, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v6
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v3.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, v130.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v7, v8
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v119.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, v118.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v133.h, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v134.h, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v6
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v134.l, v3.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v128.l, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v128.h, v7.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v4
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v9, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v11, v12
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, v115.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, v114.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v114.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.h, v115.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.l, 0x300, v7.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, v113.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v129.l, v8.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v130.l, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v116.l, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.h, v129.h, v8.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v8.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v10
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v116.h, v7.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v6, v14
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, v102.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, v101.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.l, 0x300, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v12, v13
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, v98.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, 0x300, v8.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.h, v102.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.h, v98.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v117.l, v8.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v118.l, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v103.l, v12.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v11
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.h, v117.h, v8.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v8.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v9.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, v97.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.h, v103.h, v12.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, 0x300, v12.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, 0x300, v8.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v14, v15
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v16, v17
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.h, v97.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, v96.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, v85.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v112.l, v13.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.l, 0x300, v12.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.h, v85.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.h, v112.h, v13.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v113.l, v14.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, 0x300, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v99.l, v12.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v10, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v11, v19
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, 0x300, v14.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v15
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, v84.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.h, v99.h, v12.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, 0x300, v12.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v16.l, 0x300, v13.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v14
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.h, v84.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, v83.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.l, 0x300, v12.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v17, v18
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.l, v80.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v100.l, v13.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.h, v80.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v16
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.h, v100.h, v13.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v101.l, v14.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, 0x300, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.h, 0xff, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v86.l, v17.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v16.l, 0x300, v13.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, 0x300, v14.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v19, v20
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.l, v71.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v19.l, v70.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.h, v86.h, v17.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.l, 0x300, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v21, v22
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.h, v71.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff, v17
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.l, v67.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.h, 0xff, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v87.l, v18.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v96.l, v19.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v20.l, 0x300, v17.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.h, v67.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v17.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.h, v87.h, v18.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.l, 0x300, v18.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v19.l, 0x300, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.h, 0xff, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v81.l, v17.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v15, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, v16, v24
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v21.l, 0x300, v18.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v20
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v19
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.l, v66.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.h, v66.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v19.l, v52.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.h, v81.h, v17.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.l, 0x300, v17.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.h, 0xff, v18.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v19.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v20.l, 0x300, v17.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, v22, v23
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.l, v52.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.l, v48.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v82.l, v18.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.h, v82.h, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v83.l, v19.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.h, v49.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.h, v48.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v21
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.l, 0x300, v18.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v21.l, 0x300, v18.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v19.l, 0x300, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.h, 0xff, v22.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.h, 0xff, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v68.l, v22.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v69.l, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v19
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v18, v24, v25
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v24.l, v39.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.h, v68.h, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.h, v69.h, v23.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.l, 0x300, v22.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.l, 0x300, v23.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v19, v26, v27
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, v21, v29
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v27, 0xffff, v22
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v29, 0xffff, v23
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.l, v39.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.l, v38.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v70.l, v24.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v25.l, 0x300, v22.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v26.l, 0x300, v23.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.h, v38.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.h, v37.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v23.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff, v20
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v24.l, 0x300, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.h, 0xff, v22.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.h, 0xff, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v55.h, v22.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v64.h, v23.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, v20, v28
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v25
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v26
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff, v24
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v24.l, v37.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.h, v64.l, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.h, v65.l, v23.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.l, 0x300, v22.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.l, 0x300, v23.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v25.l, 0x300, v22.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v26.l, 0x300, v23.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, v27, v28
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, v29, v30
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.l, v36.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.l, v35.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v29.l, v34.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v65.h, v24.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.h, v36.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.h, v35.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.l, 0xff, v27.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v29.l, 0xff, v29.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v24.l, 0x300, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.h, 0xff, v27.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.h, 0xff, v28.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.l, v53.l, v27.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.l, v54.l, v28.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v29.l, v55.l, v29.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v26
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v24
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.h, v53.h, v27.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.h, v54.h, v28.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.l, 0x300, v27.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.l, 0x300, v28.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v29.l, 0x300, v29.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, v31, v37
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v26, v26, v39
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v30.l, 0x300, v27.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v31.l, 0x300, v28.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v35, 0xffff, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v37, 0xffff, v28
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v29
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.l, v34.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.h, v33.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.l, v33.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.h, v32.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v29.l, v32.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.l, 0xff, v27.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.h, 0xff, v27.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.h, 0xff, v28.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v29.l, 0xff, v29.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v25
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.l, v49.h, v27.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.h, v50.l, v27.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.l, v50.h, v28.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.h, v51.l, v28.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v29.l, v51.h, v29.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v25, v25, v38
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v36, 16, v30
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v31
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.l, 0x300, v27.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v30.l, 0x300, v27.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.l, 0x300, v28.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v31.l, 0x300, v28.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v29.l, 0x300, v29.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v30, 0xffff, v30
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v33, 16, v28
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff, v31
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v29
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v27, v35, v36
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v28, v37, v38
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v29, v39, v32
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v30, v30, v33
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v31, v31, v34
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v128i8_to_v16f64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s32 offset:592
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v41, s32 offset:588
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v42, s32 offset:584
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v43, s32 offset:580
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v44, s32 offset:576
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v45, s32 offset:572
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v46, s32 offset:568
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v47, s32 offset:564
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v56, s32 offset:560
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v57, s32 offset:556
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v58, s32 offset:552
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v59, s32 offset:548
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v60, s32 offset:544
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v61, s32 offset:540
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v62, s32 offset:536
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v63, s32 offset:532
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v72, s32 offset:528
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v73, s32 offset:524
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v74, s32 offset:520
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v75, s32 offset:516
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v76, s32 offset:512
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v77, s32 offset:508
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v78, s32 offset:504
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v79, s32 offset:500
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v88, s32 offset:496
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v89, s32 offset:492
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v90, s32 offset:488
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v91, s32 offset:484
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v92, s32 offset:480
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v93, s32 offset:476
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v94, s32 offset:472
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v95, s32 offset:468
+; GFX11-FAKE16-NEXT:    s_clause 0x12
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v104, s32 offset:464
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v105, s32 offset:460
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v106, s32 offset:456
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v107, s32 offset:452
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v108, s32 offset:448
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v109, s32 offset:444
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v110, s32 offset:440
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v111, s32 offset:436
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v120, s32 offset:432
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v121, s32 offset:428
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v122, s32 offset:424
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v123, s32 offset:420
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v124, s32 offset:416
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v125, s32 offset:412
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v126, s32 offset:408
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v127, s32 offset:404
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v136, s32 offset:400
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v137, s32 offset:396
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v138, s32 offset:392
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v36, v22 :: v_dual_mov_b32 v37, v20
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v38, v18 :: v_dual_mov_b32 v39, v16
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v48, v14 :: v_dual_mov_b32 v49, v12
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v50, v10 :: v_dual_mov_b32 v51, v8
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v52, v6 :: v_dual_mov_b32 v53, v4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v54, v2 :: v_dual_mov_b32 v55, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v0, off, s32 offset:384
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v64, off, s32 offset:380
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32 offset:376
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v65, off, s32 offset:372
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v4, off, s32 offset:368
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v66, off, s32 offset:364
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v6, off, s32 offset:360
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v67, off, s32 offset:356
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v8, off, s32 offset:352
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v68, off, s32 offset:348
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v10, off, s32 offset:344
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v69, off, s32 offset:340
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v12, off, s32 offset:336
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v70, off, s32 offset:332
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v14, off, s32 offset:328
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v71, off, s32 offset:324
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v16, off, s32 offset:320
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v80, off, s32 offset:316
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v18, off, s32 offset:312
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v81, off, s32 offset:308
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v20, off, s32 offset:304
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v82, off, s32 offset:300
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v22, off, s32 offset:296
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v83, off, s32 offset:292
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v24, off, s32 offset:288
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v84, off, s32 offset:284
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v26, off, s32 offset:280
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v85, off, s32 offset:276
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v28, off, s32 offset:272
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v86, off, s32 offset:268
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v30, off, s32 offset:264
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v87, off, s32 offset:260
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v31, off, s32 offset:256
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v96, off, s32 offset:252
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v99, off, s32 offset:248
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v97, off, s32 offset:244
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v100, off, s32 offset:240
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v98, off, s32 offset:236
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v101, off, s32 offset:232
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v112, off, s32 offset:228
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v102, off, s32 offset:224
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v113, off, s32 offset:220
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v103, off, s32 offset:216
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v114, off, s32 offset:388
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v115, off, s32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v116, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v117, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v118, off, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v119, off, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v128, off, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v129, off, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v130, off, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v131, off, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v144, off, s32 offset:72
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v145, off, s32 offset:80
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v146, off, s32 offset:88
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v147, off, s32 offset:96
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v148, off, s32 offset:104
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v162, off, s32 offset:112
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v163, off, s32 offset:120
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v164, off, s32 offset:128
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v165, off, s32 offset:136
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v166, off, s32 offset:144
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v179, off, s32 offset:152
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v180, off, s32 offset:160
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v181, off, s32 offset:168
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v182, off, s32 offset:176
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v183, off, s32 offset:184
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v136, off, s32 offset:192
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v137, off, s32 offset:200
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v138, off, s32 offset:208
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v132, off, s32 offset:212
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v133, off, s32 offset:204
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v134, off, s32 offset:196
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v135, off, s32 offset:188
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v149, off, s32 offset:180
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v150, off, s32 offset:172
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v151, off, s32 offset:164
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v160, off, s32 offset:156
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v161, off, s32 offset:148
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v167, off, s32 offset:140
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v176, off, s32 offset:132
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v177, off, s32 offset:124
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v178, off, s32 offset:116
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v40, off, s32 offset:108
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v41, off, s32 offset:100
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v42, off, s32 offset:92
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v43, off, s32 offset:84
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v44, off, s32 offset:76
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v58, off, s32 offset:68
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v59, off, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v60, off, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v74, off, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v75, off, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v76, off, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v77, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v78, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v92, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v124, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v125, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v126, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v127, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v111, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v120, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v121, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v122, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v123, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v106, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v107, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v108, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v109, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v110, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v93, 8, v29
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(54)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v114
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(53)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v94, 8, v115
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(52)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v95, 8, v116
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(51)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v104, 8, v117
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(50)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v105, 8, v118
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(49)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v79, 8, v119
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(48)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v88, 8, v128
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(47)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v89, 8, v129
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(46)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v90, 8, v130
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(45)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v91, 8, v131
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(44)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v61, 8, v144
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(43)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v62, 8, v145
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(42)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v63, 8, v146
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(41)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v72, 8, v147
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(40)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v73, 8, v148
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(39)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v45, 8, v162
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(38)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v46, 8, v163
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(37)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v47, 8, v164
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(36)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v56, 8, v165
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(35)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v57, 8, v166
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(34)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v179, 8, v179
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v180, 8, v180
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(32)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v181, 8, v181
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v182, 8, v182
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(30)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v183, 8, v183
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(29)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v162, 8, v136
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(28)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v163, 8, v137
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(27)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v164, 8, v138
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v165, 8, v103
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v166, 8, v102
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v144, 8, v101
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v145, 8, v100
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v146, 8, v99
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v147, 8, v31
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v148, 8, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v119, 8, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v128, 8, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v129, 8, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v130, 8, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v131, 8, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v114, 8, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v115, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v116, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v117, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v118, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v99, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v100, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v101, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v102, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v103, 8, v0
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB37_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v53
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v52
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v51
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v124
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v125
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v126
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v127
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v50
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v37
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v49
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v48
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v111
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v121
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v120
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v122
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v123
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v107
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v38
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v108
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v109
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v110
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v106
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v6, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v8, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v10, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v32
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v92
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v78
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v77
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v76
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v75
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v74
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v60
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v59
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v93
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v94
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v95
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v104
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v105
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v79
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v88
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v89
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v90
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v91
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v13, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v15, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v58
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v44
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v43
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v42
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v41
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v40
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v178
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v177
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v176
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v167
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v61
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v62
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v63
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v72
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v73
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v17, v45
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v18, v46
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v19, v47
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v56
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v21, v57
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xffff, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xffff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v18, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v20, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v161
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v160
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v151
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v150
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v149
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v135
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v134
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v133
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v132
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v113
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v17, v179
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v18, v180
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v19, v181
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v182
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v21, v183
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v22, v162
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v23, v163
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v24, v164
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v165
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v26, v166
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xffff, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xffff, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v19, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v21, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v23, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v25, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v112
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v98
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v97
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v96
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v87
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v86
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v84
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v83
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v82
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v22, v144
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v23, v145
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v24, v146
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v147
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v26, v148
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v27, v119
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v28, v128
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v29, v129
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v30, v130
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v31, v131
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xffff, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xffff, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xffff, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xffff, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xffff, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v31
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v28, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v30, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v81
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v71
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v70
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v69
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v32, 0xff, v68
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xff, v67
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v34, 0xff, v66
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xff, v65
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v36, 0xff, v64
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v27, v114
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v28, v115
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v29, v116
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v30, v117
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v31, v118
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v32, v32, v99
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v33, v33, v100
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v34, v34, v101
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, v35, v102
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, v36, v103
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xffff, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xffff, v29
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xffff, v31
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xffff, v33
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xffff, v35
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v36, 16, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v27, v28
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v29, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v31, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v33, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v35, v36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr92
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr78
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr77
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr76
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr75
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr74
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr60
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr59
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr58
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr44
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr43
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr42
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr41
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr40
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr178
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr177
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr176
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr167
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr161
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr160
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr151
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr150
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr149
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr135
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr124
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr125
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr126
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr127
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr111
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr120
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr121
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr122
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr123
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr106
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr107
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr108
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr109
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr110
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr93
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr94
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr95
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr104
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr105
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr79
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr88
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr89
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr90
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr91
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr61
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr62
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr63
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr72
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr73
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr45
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr46
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr47
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr56
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr57
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr179
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr180
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr181
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr182
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr183
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr162
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr163
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr164
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr165
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr166
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr144
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr147
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr148
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT:  .LBB37_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB37_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v55, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v54, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v53, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v52, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v51, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v50, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v124, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v125, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v126, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v127, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v49, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v48, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v37, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v36, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v35, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v39, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, v34, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v123, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v111, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v120, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v121, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v122, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v107, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v108, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v109, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v38, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v110, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v106, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v3, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v8, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v10, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v33, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v32, 3
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v92, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v78, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, v77, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v76, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v75, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v74, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, v60, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, v59, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v93, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v94, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v95, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v104, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v105, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v79, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v88, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v89, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v90, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v91, v16
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v13
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, 0x300, v15
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, 0x300, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v13, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v15, v16
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v58, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v44, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v43, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, v42, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, v41, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, v40, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, v178, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, v177, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, v176, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, v167, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v61, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v62, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v63, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v72, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v73, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v45, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v46, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v47, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v56, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v57, v21
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v13
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, 0x300, v15
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, 0x300, v16
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, 0x300, v17
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, 0x300, v18
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, 0x300, v19
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, 0x300, v20
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, 0x300, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xffff, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xffff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v18, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v20, v21
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, v161, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, v160, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, v151, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, v150, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, v149, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, v135, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v23, v134, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v24, v133, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v25, v132, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v26, v113, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v179, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v180, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v181, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v182, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v183, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v162, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v163, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v164, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v165, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v166, v26
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, 0x300, v17
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, 0x300, v18
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, 0x300, v19
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, 0x300, v20
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, 0x300, v21
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, 0x300, v22
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v23, 0x300, v23
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v24, 0x300, v24
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v25, 0x300, v25
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v26, 0x300, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xffff, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xffff, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v19, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v21, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v23, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v25, v26
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, v112, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v23, v98, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v24, v97, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v25, v96, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v26, v87, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v27, v86, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v28, v85, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v29, v84, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v30, v83, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v31, v82, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v144, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v145, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v146, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v147, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v148, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v119, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v128, v28
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v129, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v130, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v131, v31
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, 0x300, v22
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v23, 0x300, v23
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v24, 0x300, v24
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v25, 0x300, v25
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v26, 0x300, v26
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v27, 0x300, v27
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v28, 0x300, v28
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v29, 0x300, v29
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v30, 0x300, v30
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v31, 0x300, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xffff, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xffff, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xffff, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xffff, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xffff, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v31
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v28, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v30, v31
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v27, v81, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v28, v80, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v29, v71, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v30, v70, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v31, v69, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v32, v68, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v33, v67, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v34, v66, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v35, v65, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v36, v64, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v32, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v34, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v36, 0xff, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v114, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v115, v28
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v116, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v117, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v118, v31
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v32, v99, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v33, v100, v33
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v34, v101, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, v102, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, v103, v36
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v27, 0x300, v27
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v28, 0x300, v28
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v29, 0x300, v29
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v30, 0x300, v30
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v31, 0x300, v31
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v32, 0x300, v32
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v33, 0x300, v33
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v34, 0x300, v34
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v35, 0x300, v35
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v36, 0x300, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xffff, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xffff, v29
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xffff, v31
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xffff, v33
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xffff, v35
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v36, 16, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v27, v28
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v29, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v31, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v33, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v35, v36
+; GFX11-FAKE16-NEXT:  .LBB37_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v138, off, s32 offset:392
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v137, off, s32 offset:396
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v136, off, s32 offset:400
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v127, off, s32 offset:404
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v126, off, s32 offset:408
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v125, off, s32 offset:412
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v124, off, s32 offset:416
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v123, off, s32 offset:420
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v122, off, s32 offset:424
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v121, off, s32 offset:428
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v120, off, s32 offset:432
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v111, off, s32 offset:436
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v110, off, s32 offset:440
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v109, off, s32 offset:444
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v108, off, s32 offset:448
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v107, off, s32 offset:452
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v106, off, s32 offset:456
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v105, off, s32 offset:460
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v104, off, s32 offset:464
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v95, off, s32 offset:468
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v94, off, s32 offset:472
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v93, off, s32 offset:476
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v92, off, s32 offset:480
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v91, off, s32 offset:484
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v90, off, s32 offset:488
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v89, off, s32 offset:492
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v88, off, s32 offset:496
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v79, off, s32 offset:500
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v78, off, s32 offset:504
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v77, off, s32 offset:508
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v76, off, s32 offset:512
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v75, off, s32 offset:516
+; GFX11-FAKE16-NEXT:    s_clause 0x12
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v74, off, s32 offset:520
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v73, off, s32 offset:524
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v72, off, s32 offset:528
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v63, off, s32 offset:532
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v62, off, s32 offset:536
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v61, off, s32 offset:540
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v60, off, s32 offset:544
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v59, off, s32 offset:548
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v58, off, s32 offset:552
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v57, off, s32 offset:556
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v56, off, s32 offset:560
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v47, off, s32 offset:564
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v46, off, s32 offset:568
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v45, off, s32 offset:572
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v44, off, s32 offset:576
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v43, off, s32 offset:580
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v42, off, s32 offset:584
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v41, off, s32 offset:588
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s32 offset:592
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -60671,550 +68383,1113 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v64bf16_to_v16f64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_b32 v32, off, s32 offset:4
-; GFX11-NEXT:    scratch_load_b32 v31, off, s32
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v32
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB39_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v33, 16, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v32, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
-; GFX11-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v37, v33, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v34, v32, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v35, 0x400000, v32
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_bfe_u32 v39, v14, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-NEXT:    v_add3_u32 v37, v37, v33, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v34, v34, v32, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v34, v35, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v35, v39, v14, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-NEXT:    v_or_b32_e32 v34, 0x400000, v33
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-NEXT:    v_bfe_u32 v36, v15, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v15
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v36, v36, v15, 0x7fff
-; GFX11-NEXT:    v_dual_cndmask_b32 v15, v36, v38 :: v_dual_lshlrev_b32 v36, 16, v13
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v15, v15, v32, 0x7060302
-; GFX11-NEXT:    v_dual_cndmask_b32 v33, v37, v34 :: v_dual_add_f32 v34, 0x40c00000, v36
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v32, v34, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v14
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_cndmask_b32 v14, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v12
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_perm_b32 v14, v14, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v13, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_cndmask_b32 v32, v32, v36
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-NEXT:    v_add3_u32 v33, v33, v13, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cndmask_b32_e32 v13, v33, v37, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v11
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_perm_b32 v13, v13, v32, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v32, v35, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-NEXT:    v_bfe_u32 v34, v12, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v12
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v34, v34, v12, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v12, v34, v38, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v12, v12, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v11, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_add3_u32 v33, v33, v11, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v35, v10, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v35, v35, v10, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v11, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v10
-; GFX11-NEXT:    v_perm_b32 v11, v11, v32, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    v_dual_cndmask_b32 v10, v35, v38 :: v_dual_lshlrev_b32 v37, 16, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_lshlrev_b32 v35, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-NEXT:    v_perm_b32 v10, v10, v33, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v32, v34, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v8, 0x40c00000, v8
-; GFX11-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v34, v8, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v9, 0x40c00000, v9
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_add3_u32 v34, v34, v8, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v33, v9, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v9
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    v_add3_u32 v33, v33, v9, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v9, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v8
-; GFX11-NEXT:    v_perm_b32 v9, v9, v32, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-NEXT:    v_cndmask_b32_e32 v8, v34, v38, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v8, v8, v33, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_add_f32 v35, 0x40c00000, v37
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v32, v35, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-NEXT:    v_bfe_u32 v35, v6, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v7, 0x40c00000, v7
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_add3_u32 v35, v35, v6, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v33, v7, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v7
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    v_add3_u32 v33, v33, v7, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v7, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v6
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v6, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v5
-; GFX11-NEXT:    v_perm_b32 v7, v7, v32, 0x7060302
-; GFX11-NEXT:    v_perm_b32 v6, v6, v33, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v4, 0x40c00000, v4
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v37
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v32, v34, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT:    v_bfe_u32 v34, v4, 16, 1
-; GFX11-NEXT:    v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v5, 0x40c00000, v5
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add3_u32 v34, v34, v4, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v33, v5, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v5
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v33, v33, v5, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v5, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v3
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v4
-; GFX11-NEXT:    v_perm_b32 v5, v5, v32, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_cndmask_b32 v4, v34, v38
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v2
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT:    v_bfe_u32 v32, v35, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_perm_b32 v4, v4, v33, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v35, v2, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_add3_u32 v35, v35, v2, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-NEXT:    v_bfe_u32 v33, v3, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v3
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v33, v33, v3, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v1
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v37
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v2, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v0
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    v_perm_b32 v3, v3, v32, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v32, v34, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_perm_b32 v2, v2, v33, 0x7060302
-; GFX11-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v34, v0, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_add3_u32 v34, v34, v0, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-NEXT:    v_bfe_u32 v33, v1, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v33, v33, v1, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v31
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v0
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xffff0000, v31
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_add_f32_e32 v31, 0x40c00000, v31
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v34, v38, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v30
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xffff0000, v30
-; GFX11-NEXT:    v_perm_b32 v1, v1, v32, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v32, v35, 16, 1
-; GFX11-NEXT:    v_perm_b32 v0, v0, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v31, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v30, 0x40c00000, v30
-; GFX11-NEXT:    v_add3_u32 v33, v33, v31, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v31
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-NEXT:    v_bfe_u32 v35, v30, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_cndmask_b32_e32 v31, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v29
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add3_u32 v35, v35, v30, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v30
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xffff0000, v29
-; GFX11-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add_f32_e32 v29, 0x40c00000, v29
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_dual_cndmask_b32 v30, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v28
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xffff0000, v28
-; GFX11-NEXT:    v_perm_b32 v31, v31, v32, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v32, v34, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v30, v30, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v29, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v28, 0x40c00000, v28
-; GFX11-NEXT:    v_add3_u32 v33, v33, v29, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v29
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11-NEXT:    v_bfe_u32 v34, v28, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cndmask_b32_e32 v29, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v27
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_add3_u32 v34, v34, v28, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v28
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xffff0000, v27
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v27, 0x40c00000, v27
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cndmask_b32_e32 v28, v34, v38, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v26
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xffff0000, v26
-; GFX11-NEXT:    v_perm_b32 v29, v29, v32, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v32, v35, 16, 1
-; GFX11-NEXT:    v_perm_b32 v28, v28, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v27, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v26, 0x40c00000, v26
-; GFX11-NEXT:    v_add3_u32 v33, v33, v27, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v27
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11-NEXT:    v_bfe_u32 v35, v26, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_cndmask_b32_e32 v27, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v25
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add3_u32 v35, v35, v26, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v26
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xffff0000, v25
-; GFX11-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add_f32_e32 v25, 0x40c00000, v25
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_dual_cndmask_b32 v26, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v24
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xffff0000, v24
-; GFX11-NEXT:    v_perm_b32 v27, v27, v32, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v32, v34, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v26, v26, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v25, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v24, 0x40c00000, v24
-; GFX11-NEXT:    v_add3_u32 v33, v33, v25, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v25
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-NEXT:    v_bfe_u32 v34, v24, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cndmask_b32_e32 v25, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v23
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_add3_u32 v34, v34, v24, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v24
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-NEXT:    v_perm_b32 v25, v25, v32, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v23, 0x40c00000, v23
-; GFX11-NEXT:    v_bfe_u32 v32, v35, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cndmask_b32_e32 v24, v34, v38, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xffff0000, v22
-; GFX11-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_perm_b32 v24, v24, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v33, v23, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-NEXT:    v_add_f32_e32 v22, 0x40c00000, v22
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v23
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v33, v23, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-NEXT:    v_bfe_u32 v35, v22, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_cndmask_b32_e32 v23, v33, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v21
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add3_u32 v35, v35, v22, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xffff0000, v21
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v22
-; GFX11-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v21, 0x40c00000, v21
-; GFX11-NEXT:    v_perm_b32 v23, v23, v32, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v36, v34, 16, 1
-; GFX11-NEXT:    v_dual_cndmask_b32 v22, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v20
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v32, v21, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v21
-; GFX11-NEXT:    v_perm_b32 v22, v22, v33, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v33, 0x40c00000, v35
-; GFX11-NEXT:    v_add3_u32 v35, v36, v34, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v34
-; GFX11-NEXT:    v_add3_u32 v32, v32, v21, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xffff0000, v20
-; GFX11-NEXT:    v_bfe_u32 v38, v33, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v34, v35, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-NEXT:    v_add_f32_e32 v20, 0x40c00000, v20
-; GFX11-NEXT:    v_or_b32_e32 v35, 0x400000, v33
-; GFX11-NEXT:    v_lshlrev_b32_e32 v36, 16, v19
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff0000, v19
-; GFX11-NEXT:    v_cndmask_b32_e32 v21, v32, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v32, v38, v33, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-NEXT:    v_dual_add_f32 v33, 0x40c00000, v36 :: v_dual_lshlrev_b32 v36, 16, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v21, v21, v34, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v34, v20, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v35, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v35, 0x400000, v20
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-NEXT:    v_bfe_u32 v37, v33, 16, 1
-; GFX11-NEXT:    v_add3_u32 v34, v34, v20, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v19, 0x40c00000, v19
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xffff0000, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v20, v34, v35, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v36
-; GFX11-NEXT:    v_add3_u32 v35, v37, v33, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v33
-; GFX11-NEXT:    v_bfe_u32 v37, v19, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-NEXT:    v_or_b32_e32 v39, 0x400000, v34
-; GFX11-NEXT:    v_perm_b32 v20, v20, v32, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v35, v36, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v35, v37, v19, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v19
-; GFX11-NEXT:    v_add3_u32 v37, v38, v34, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v38, 16, v17
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-NEXT:    v_bfe_u32 v48, v18, 16, 1
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff0000, v17
-; GFX11-NEXT:    v_cndmask_b32_e32 v19, v35, v36, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add3_u32 v36, v48, v18, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v17, 0x40c00000, v17
-; GFX11-NEXT:    v_perm_b32 v19, v19, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v38, v35, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v34, v37, v39, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v18
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v16
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff0000, v16
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v18, v36, v37, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v16, 0x40c00000, v16
-; GFX11-NEXT:    v_add_f32_e32 v36, 0x40c00000, v39
-; GFX11-NEXT:    v_add3_u32 v37, v38, v35, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v35
-; GFX11-NEXT:    v_bfe_u32 v39, v17, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_bfe_u32 v48, v36, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v49, 0x400000, v36
-; GFX11-NEXT:    v_or_b32_e32 v50, 0x400000, v16
-; GFX11-NEXT:    v_perm_b32 v18, v18, v34, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v35, v37, v38, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v38, v39, v17, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v39, 0x400000, v17
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-NEXT:    v_bfe_u32 v37, v16, 16, 1
-; GFX11-NEXT:    v_add3_u32 v48, v48, v36, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v17, v38, v39, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-NEXT:    v_add3_u32 v37, v37, v16, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v17, v17, v35, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v36, v48, v49, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-NEXT:    v_cndmask_b32_e32 v16, v37, v50, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v16, v16, v36, 0x7060302
-; GFX11-NEXT:  .LBB39_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v64bf16_to_v16f64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v32
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB39_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v33, 0xffff0000, v14
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_lshlrev_b32 v32, 16, v15
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v32, 0x40c00000, v32
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v39, v33, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v32, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v32
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v32
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v32, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v32, v35, v38 :: v_dual_and_b32 v15, 0xffff0000, v15
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v15, 0x40c00000, v15 :: v_dual_lshlrev_b32 v14, 16, v14
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v39, v33, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v32.l, v32.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v15, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v15
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT:    v_add3_u32 v36, v36, v15, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v15, v36, v37
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v48, v14, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v49, 0x400000, v14
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v33
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v15, 0xffff, v32, v15
+; GFX11-TRUE16-NEXT:    v_add3_u32 v38, v48, v14, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v14, v38, v49, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v13
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v14.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v33, v35, v36 :: v_dual_add_f32 v34, 0x40c00000, v34
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v14, 0xffff, v14, v33
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v34, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v38, v13, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v36, v38, v13, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v13
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v13, v36, v37 :: v_dual_and_b32 v38, 0xffff0000, v12
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v35, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v13, 0xffff, v13, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v36
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v12, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v35, 0x400000, v12
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v12, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v12, v32, v35, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v11, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v10
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v11, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v11
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v36
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v11, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v33, v33, v38 :: v_dual_and_b32 v38, 0xffff0000, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v11, 0xffff, v11, v33
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v10, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v10, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v10, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v12, 0xffff, v12, v32
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v9, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v10, 0xffff, v10, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v9, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_cndmask_b32 v9, v32, v36
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v9.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v9, 0xffff, v9, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v8, 0xffff, v8, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v7, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v6, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v7, 0xffff, v7, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v6, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v32, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v4, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v6, 0xffff, v6, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v5, 0xffff, v5, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v4, 0xffff, v4, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_cndmask_b32 v3, v32, v36
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v3, 0xffff, v3, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v2, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v35, 0x40c00000, v38 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v34
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v31
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v31
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v31, 0x40c00000, v31
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v32, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v31, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v30
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v30
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v31, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v31
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v30, 0x40c00000, v30
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v31, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v30, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v0, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v31.l, v31.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v30, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v30
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v29
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v31, 0xffff, v31, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v30, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v29, 0x40c00000, v29
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.l, v30.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v29, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v30, 0xffff, v30, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v28
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v29, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v29
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v28, 0x40c00000, v28
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v29, v32, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v28, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v27
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v28, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v28
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v27, 0x40c00000, v27
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.l, v29.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v28, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v27, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v29, 0xffff, v29, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.l, v28.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v27, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v27
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v26
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v26
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v28, 0xffff, v28, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v27, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v26, 0x40c00000, v26
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.l, v27.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v26, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v27, 0xffff, v27, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v25
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v26, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v26
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v25, 0x40c00000, v25
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v26, v32, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v25, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v24
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v25, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v25
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v24, 0x40c00000, v24
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v26.l, v26.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v25, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v24, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v26, 0xffff, v26, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v25.l, v25.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v24, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v24
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v23
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v25, 0xffff, v25, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v24, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v23, 0x40c00000, v23
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v24.l, v24.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v23, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v24, 0xffff, v24, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v23, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v23
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff0000, v20
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v23, v32, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v22, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v21
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v22, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v22
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v21, 0x40c00000, v21
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v23.l, v23.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v22, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v21, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v23, 0xffff, v23, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.l, v22.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v35, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v21, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v21
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v36
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v22, 0xffff, v22, v33
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v20, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v21, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v39
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v20
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v20, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.l, v21.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v18
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v21, 0xffff, v21, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v19
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v20, v33, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v19, 0x40c00000, v19
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v32, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v19
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v36, v36, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v39, v35, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.l, v20.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v19, v36, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v39, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v18, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v19.h
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v33, v33, v38 :: v_dual_and_b32 v38, 0xffff0000, v17
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v20, 0xffff, v20, v32
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v37, 0x40c00000, v38 :: v_dual_cndmask_b32 v34, v34, v36
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v17, 0x40c00000, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v18
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v16
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v49, 0x400000, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v48, 0x400000, v37
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v19, 0xffff, v19, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v18, v35, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v38, v17, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v37, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v16, 0x40c00000, v16
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v39, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v38, v38, v17, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v51, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v37, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v50, v16, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v39, v39, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v17, v38, v49, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v49, 0x400000, v16
+; GFX11-TRUE16-NEXT:    v_add3_u32 v38, v50, v16, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v18.l, v18.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v17.l, v17.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v36, v39, v51, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v18, 0xffff, v18, v34
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.l, v36.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v35, v35, v48, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v17, 0xffff, v17, v35
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v16, v38, v49, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v16, 0xffff, v36, v16
+; GFX11-TRUE16-NEXT:  .LBB39_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v64bf16_to_v16f64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v32
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB39_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v33, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v33, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v32, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, 0x400000, v32
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v39, v14, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v32
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v37, v33, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v32, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v34, v35, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v39, v14, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v34, 0x400000, v33
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v36, v15, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v15
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v36, v36, v15, 0x7fff
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v15, v36, v38 :: v_dual_lshlrev_b32 v36, 16, v13
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v15, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v33, v37, v34 :: v_dual_add_f32 v34, 0x40c00000, v36
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v14
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v14, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v12
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v14, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v13, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_cndmask_b32 v32, v32, v36
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v13, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v13, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v13, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v12, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v12
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v12, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v34, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v12, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v11, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v11, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v10, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v10
+; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v11, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v35, v38 :: v_dual_lshlrev_b32 v37, 16, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_lshlrev_b32 v35, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v10, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v8, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v8, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v8
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v9, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v34, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v8, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_add_f32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v6, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v7, 0x40c00000, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v6, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v5
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v6, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v32, v32, v36 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v5
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v5, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_cndmask_b32 v4, v34, v38
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v4, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v3, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v31
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xffff0000, v31
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v31, 0x40c00000, v31
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v34, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xffff0000, v30
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v31, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v30, 0x40c00000, v30
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v31, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v31
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v30, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v31, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v29
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v30, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xffff0000, v29
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v29, 0x40c00000, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v30, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xffff0000, v28
+; GFX11-FAKE16-NEXT:    v_perm_b32 v31, v31, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v30, v30, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v29, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v28, 0x40c00000, v28
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v29, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v29
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v28, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v29, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v27
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v28, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xffff0000, v27
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v27, 0x40c00000, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v28, v34, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xffff0000, v26
+; GFX11-FAKE16-NEXT:    v_perm_b32 v29, v29, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v28, v28, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v27, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v26, 0x40c00000, v26
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v27, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v27
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v26, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v27, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v25
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v26, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xffff0000, v25
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v25, 0x40c00000, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v26, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xffff0000, v24
+; GFX11-FAKE16-NEXT:    v_perm_b32 v27, v27, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v34, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v26, v26, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v25, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v24, 0x40c00000, v24
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v25, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v25
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v24, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v25, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v23
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v24, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xffff0000, v23
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-FAKE16-NEXT:    v_perm_b32 v25, v25, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v23, 0x40c00000, v23
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v24, v34, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_perm_b32 v24, v24, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v23, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v23
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v33, v23, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v22, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v23, v33, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v21
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v22, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xffff0000, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v22
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v37 :: v_dual_cndmask_b32 v33, v33, v36
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v21, 0x40c00000, v21
+; GFX11-FAKE16-NEXT:    v_perm_b32 v23, v23, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v36, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v22, v35, v38 :: v_dual_lshlrev_b32 v35, 16, v20
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v21, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v21
+; GFX11-FAKE16-NEXT:    v_perm_b32 v22, v22, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v33, 0x40c00000, v35
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v36, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v32, v21, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v33, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v34, v35, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, 0x400000, v33
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v36, 16, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff0000, v19
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v21, v32, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v38, v33, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v33, 0x40c00000, v36 :: v_dual_lshlrev_b32 v36, 16, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v21, v21, v34, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v20, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v35, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, 0x400000, v20
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v33, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v20, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v20, v34, v35, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v36
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v37, v33, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v33
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v19, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v39, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_perm_b32 v20, v20, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v35, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v37, v19, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v19
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v17
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v48, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff0000, v17
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v19, v35, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v36, v48, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v17, 0x40c00000, v17
+; GFX11-FAKE16-NEXT:    v_perm_b32 v19, v19, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v34, v37, v39, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v16
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v36, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v16, 0x40c00000, v16
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v39
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v38, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v39, v17, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v48, v36, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v49, 0x400000, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v50, 0x400000, v16
+; GFX11-FAKE16-NEXT:    v_perm_b32 v18, v18, v34, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v35, v37, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v38, v39, v17, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v39, 0x400000, v17
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v16, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v48, v48, v36, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v38, v39, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v37, v16, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v17, v17, v35, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v36, v48, v49, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v37, v50, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v16, v16, v36, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB39_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -69155,923 +77430,1689 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v128i8_to_v64bf16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_store_b32 off, v40, s32 offset:580
-; GFX11-NEXT:    scratch_store_b32 off, v41, s32 offset:576
-; GFX11-NEXT:    scratch_store_b32 off, v42, s32 offset:572
-; GFX11-NEXT:    scratch_store_b32 off, v43, s32 offset:568
-; GFX11-NEXT:    scratch_store_b32 off, v44, s32 offset:564
-; GFX11-NEXT:    scratch_store_b32 off, v45, s32 offset:560
-; GFX11-NEXT:    scratch_store_b32 off, v46, s32 offset:556
-; GFX11-NEXT:    scratch_store_b32 off, v47, s32 offset:552
-; GFX11-NEXT:    scratch_store_b32 off, v56, s32 offset:548
-; GFX11-NEXT:    scratch_store_b32 off, v57, s32 offset:544
-; GFX11-NEXT:    scratch_store_b32 off, v58, s32 offset:540
-; GFX11-NEXT:    scratch_store_b32 off, v59, s32 offset:536
-; GFX11-NEXT:    scratch_store_b32 off, v60, s32 offset:532
-; GFX11-NEXT:    scratch_store_b32 off, v61, s32 offset:528
-; GFX11-NEXT:    scratch_store_b32 off, v62, s32 offset:524
-; GFX11-NEXT:    scratch_store_b32 off, v63, s32 offset:520
-; GFX11-NEXT:    scratch_store_b32 off, v72, s32 offset:516
-; GFX11-NEXT:    scratch_store_b32 off, v73, s32 offset:512
-; GFX11-NEXT:    scratch_store_b32 off, v74, s32 offset:508
-; GFX11-NEXT:    scratch_store_b32 off, v75, s32 offset:504
-; GFX11-NEXT:    scratch_store_b32 off, v76, s32 offset:500
-; GFX11-NEXT:    scratch_store_b32 off, v77, s32 offset:496
-; GFX11-NEXT:    scratch_store_b32 off, v78, s32 offset:492
-; GFX11-NEXT:    scratch_store_b32 off, v79, s32 offset:488
-; GFX11-NEXT:    scratch_store_b32 off, v88, s32 offset:484
-; GFX11-NEXT:    scratch_store_b32 off, v89, s32 offset:480
-; GFX11-NEXT:    scratch_store_b32 off, v90, s32 offset:476
-; GFX11-NEXT:    scratch_store_b32 off, v91, s32 offset:472
-; GFX11-NEXT:    scratch_store_b32 off, v92, s32 offset:468
-; GFX11-NEXT:    scratch_store_b32 off, v93, s32 offset:464
-; GFX11-NEXT:    scratch_store_b32 off, v94, s32 offset:460
-; GFX11-NEXT:    scratch_store_b32 off, v95, s32 offset:456
-; GFX11-NEXT:    s_clause 0xf
-; GFX11-NEXT:    scratch_store_b32 off, v104, s32 offset:452
-; GFX11-NEXT:    scratch_store_b32 off, v105, s32 offset:448
-; GFX11-NEXT:    scratch_store_b32 off, v106, s32 offset:444
-; GFX11-NEXT:    scratch_store_b32 off, v107, s32 offset:440
-; GFX11-NEXT:    scratch_store_b32 off, v108, s32 offset:436
-; GFX11-NEXT:    scratch_store_b32 off, v109, s32 offset:432
-; GFX11-NEXT:    scratch_store_b32 off, v110, s32 offset:428
-; GFX11-NEXT:    scratch_store_b32 off, v111, s32 offset:424
-; GFX11-NEXT:    scratch_store_b32 off, v120, s32 offset:420
-; GFX11-NEXT:    scratch_store_b32 off, v121, s32 offset:416
-; GFX11-NEXT:    scratch_store_b32 off, v122, s32 offset:412
-; GFX11-NEXT:    scratch_store_b32 off, v123, s32 offset:408
-; GFX11-NEXT:    scratch_store_b32 off, v124, s32 offset:404
-; GFX11-NEXT:    scratch_store_b32 off, v125, s32 offset:400
-; GFX11-NEXT:    scratch_store_b32 off, v126, s32 offset:396
-; GFX11-NEXT:    scratch_store_b32 off, v127, s32 offset:392
-; GFX11-NEXT:    v_dual_mov_b32 v37, v30 :: v_dual_mov_b32 v54, v24
-; GFX11-NEXT:    v_dual_mov_b32 v55, v28 :: v_dual_mov_b32 v52, v26
-; GFX11-NEXT:    v_dual_mov_b32 v50, v22 :: v_dual_mov_b32 v53, v20
-; GFX11-NEXT:    v_dual_mov_b32 v34, v18 :: v_dual_mov_b32 v51, v16
-; GFX11-NEXT:    v_dual_mov_b32 v36, v14 :: v_dual_mov_b32 v49, v12
-; GFX11-NEXT:    v_dual_mov_b32 v32, v10 :: v_dual_mov_b32 v39, v4
-; GFX11-NEXT:    v_dual_mov_b32 v48, v8 :: v_dual_mov_b32 v33, v6
-; GFX11-NEXT:    v_dual_mov_b32 v35, v2 :: v_dual_mov_b32 v38, v0
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v0, off, s32 offset:384
-; GFX11-NEXT:    scratch_load_u16 v118, off, s32 offset:380
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32 offset:376
-; GFX11-NEXT:    scratch_load_u16 v134, off, s32 offset:372
-; GFX11-NEXT:    scratch_load_u16 v4, off, s32 offset:368
-; GFX11-NEXT:    scratch_load_u16 v116, off, s32 offset:364
-; GFX11-NEXT:    scratch_load_u16 v6, off, s32 offset:360
-; GFX11-NEXT:    scratch_load_u16 v131, off, s32 offset:356
-; GFX11-NEXT:    scratch_load_u16 v8, off, s32 offset:352
-; GFX11-NEXT:    scratch_load_u16 v98, off, s32 offset:348
-; GFX11-NEXT:    scratch_load_u16 v10, off, s32 offset:344
-; GFX11-NEXT:    scratch_load_u16 v129, off, s32 offset:340
-; GFX11-NEXT:    scratch_load_u16 v12, off, s32 offset:336
-; GFX11-NEXT:    scratch_load_u16 v99, off, s32 offset:332
-; GFX11-NEXT:    scratch_load_u16 v14, off, s32 offset:328
-; GFX11-NEXT:    scratch_load_u16 v112, off, s32 offset:324
-; GFX11-NEXT:    scratch_load_u16 v16, off, s32 offset:320
-; GFX11-NEXT:    scratch_load_u16 v81, off, s32 offset:316
-; GFX11-NEXT:    scratch_load_u16 v18, off, s32 offset:312
-; GFX11-NEXT:    scratch_load_u16 v103, off, s32 offset:308
-; GFX11-NEXT:    scratch_load_u16 v20, off, s32 offset:304
-; GFX11-NEXT:    scratch_load_u16 v86, off, s32 offset:300
-; GFX11-NEXT:    scratch_load_u16 v22, off, s32 offset:296
-; GFX11-NEXT:    scratch_load_u16 v101, off, s32 offset:292
-; GFX11-NEXT:    scratch_load_u16 v24, off, s32 offset:288
-; GFX11-NEXT:    scratch_load_u16 v83, off, s32 offset:284
-; GFX11-NEXT:    scratch_load_u16 v26, off, s32 offset:280
-; GFX11-NEXT:    scratch_load_u16 v97, off, s32 offset:276
-; GFX11-NEXT:    scratch_load_u16 v28, off, s32 offset:272
-; GFX11-NEXT:    scratch_load_u16 v67, off, s32 offset:268
-; GFX11-NEXT:    scratch_load_u16 v30, off, s32 offset:264
-; GFX11-NEXT:    scratch_load_u16 v85, off, s32 offset:260
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v31, off, s32 offset:256
-; GFX11-NEXT:    scratch_load_u16 v68, off, s32 offset:252
-; GFX11-NEXT:    scratch_load_u16 v94, off, s32 offset:248
-; GFX11-NEXT:    scratch_load_u16 v80, off, s32 offset:244
-; GFX11-NEXT:    scratch_load_u16 v88, off, s32 offset:240
-; GFX11-NEXT:    scratch_load_u16 v64, off, s32 offset:236
-; GFX11-NEXT:    scratch_load_u16 v93, off, s32 offset:232
-; GFX11-NEXT:    scratch_load_u16 v69, off, s32 offset:228
-; GFX11-NEXT:    scratch_load_u16 v91, off, s32 offset:224
-; GFX11-NEXT:    scratch_load_u16 v65, off, s32 offset:220
-; GFX11-NEXT:    scratch_load_u16 v92, off, s32 offset:216
-; GFX11-NEXT:    scratch_load_b32 v150, off, s32 offset:388
-; GFX11-NEXT:    scratch_load_u16 v182, off, s32
-; GFX11-NEXT:    scratch_load_u16 v40, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_u16 v43, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_u16 v44, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_u16 v45, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_u16 v46, off, s32 offset:40
-; GFX11-NEXT:    scratch_load_u16 v47, off, s32 offset:48
-; GFX11-NEXT:    scratch_load_u16 v56, off, s32 offset:56
-; GFX11-NEXT:    scratch_load_u16 v58, off, s32 offset:64
-; GFX11-NEXT:    scratch_load_u16 v59, off, s32 offset:72
-; GFX11-NEXT:    scratch_load_u16 v60, off, s32 offset:80
-; GFX11-NEXT:    scratch_load_u16 v61, off, s32 offset:88
-; GFX11-NEXT:    scratch_load_u16 v62, off, s32 offset:96
-; GFX11-NEXT:    scratch_load_u16 v63, off, s32 offset:104
-; GFX11-NEXT:    scratch_load_u16 v72, off, s32 offset:112
-; GFX11-NEXT:    scratch_load_u16 v73, off, s32 offset:120
-; GFX11-NEXT:    scratch_load_u16 v74, off, s32 offset:128
-; GFX11-NEXT:    scratch_load_u16 v75, off, s32 offset:136
-; GFX11-NEXT:    scratch_load_u16 v76, off, s32 offset:144
-; GFX11-NEXT:    scratch_load_u16 v77, off, s32 offset:152
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v78, off, s32 offset:160
-; GFX11-NEXT:    scratch_load_u16 v79, off, s32 offset:168
-; GFX11-NEXT:    scratch_load_u16 v89, off, s32 offset:176
-; GFX11-NEXT:    scratch_load_u16 v90, off, s32 offset:184
-; GFX11-NEXT:    scratch_load_u16 v95, off, s32 offset:192
-; GFX11-NEXT:    scratch_load_u16 v104, off, s32 offset:200
-; GFX11-NEXT:    scratch_load_u16 v105, off, s32 offset:208
-; GFX11-NEXT:    scratch_load_u16 v42, off, s32 offset:212
-; GFX11-NEXT:    scratch_load_u16 v180, off, s32 offset:204
-; GFX11-NEXT:    scratch_load_u16 v183, off, s32 offset:196
-; GFX11-NEXT:    scratch_load_u16 v165, off, s32 offset:188
-; GFX11-NEXT:    scratch_load_u16 v179, off, s32 offset:180
-; GFX11-NEXT:    scratch_load_u16 v163, off, s32 offset:172
-; GFX11-NEXT:    scratch_load_u16 v177, off, s32 offset:164
-; GFX11-NEXT:    scratch_load_u16 v145, off, s32 offset:156
-; GFX11-NEXT:    scratch_load_u16 v166, off, s32 offset:148
-; GFX11-NEXT:    scratch_load_u16 v148, off, s32 offset:140
-; GFX11-NEXT:    scratch_load_u16 v151, off, s32 offset:132
-; GFX11-NEXT:    scratch_load_u16 v164, off, s32 offset:124
-; GFX11-NEXT:    scratch_load_u16 v178, off, s32 offset:116
-; GFX11-NEXT:    scratch_load_u16 v146, off, s32 offset:108
-; GFX11-NEXT:    scratch_load_u16 v162, off, s32 offset:100
-; GFX11-NEXT:    scratch_load_u16 v144, off, s32 offset:92
-; GFX11-NEXT:    scratch_load_u16 v149, off, s32 offset:84
-; GFX11-NEXT:    scratch_load_u16 v119, off, s32 offset:76
-; GFX11-NEXT:    scratch_load_u16 v147, off, s32 offset:68
-; GFX11-NEXT:    scratch_load_u16 v130, off, s32 offset:60
-; GFX11-NEXT:    scratch_load_u16 v135, off, s32 offset:52
-; GFX11-NEXT:    scratch_load_u16 v117, off, s32 offset:44
-; GFX11-NEXT:    scratch_load_u16 v133, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_u16 v96, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_u16 v114, off, s32 offset:20
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_u16 v87, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_u16 v102, off, s32 offset:4
-; GFX11-NEXT:    v_lshlrev_b16 v70, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v71, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v84, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v82, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v115, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v66, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v128, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v113, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v132, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v100, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v161, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v160, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v176, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v167, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v181, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(62)
-; GFX11-NEXT:    v_lshlrev_b16 v127, 8, v0
-; GFX11-NEXT:    v_lshlrev_b16 v126, 8, v2
-; GFX11-NEXT:    v_lshlrev_b16 v124, 8, v4
-; GFX11-NEXT:    v_lshlrev_b16 v125, 8, v6
-; GFX11-NEXT:    v_lshlrev_b16 v120, 8, v8
-; GFX11-NEXT:    v_lshlrev_b16 v123, 8, v10
-; GFX11-NEXT:    v_lshlrev_b16 v121, 8, v12
-; GFX11-NEXT:    v_lshlrev_b16 v122, 8, v14
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
-; GFX11-NEXT:    v_lshlrev_b16 v106, 8, v16
-; GFX11-NEXT:    v_lshlrev_b16 v111, 8, v18
-; GFX11-NEXT:    v_lshlrev_b16 v109, 8, v20
-; GFX11-NEXT:    v_lshlrev_b16 v110, 8, v22
-; GFX11-NEXT:    v_lshlrev_b16 v107, 8, v24
-; GFX11-NEXT:    v_lshlrev_b16 v108, 8, v26
-; GFX11-NEXT:    s_waitcnt vmcnt(61)
-; GFX11-NEXT:    v_lshlrev_b16 v88, 8, v88
-; GFX11-NEXT:    s_waitcnt vmcnt(59)
-; GFX11-NEXT:    v_lshlrev_b16 v93, 8, v93
-; GFX11-NEXT:    s_waitcnt vmcnt(57)
-; GFX11-NEXT:    v_lshlrev_b16 v91, 8, v91
-; GFX11-NEXT:    s_waitcnt vmcnt(55)
-; GFX11-NEXT:    v_lshlrev_b16 v92, 8, v92
-; GFX11-NEXT:    s_waitcnt vmcnt(54)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v150
-; GFX11-NEXT:    s_waitcnt vmcnt(53)
-; GFX11-NEXT:    v_lshlrev_b16 v150, 8, v182
-; GFX11-NEXT:    s_waitcnt vmcnt(52)
-; GFX11-NEXT:    v_lshlrev_b16 v41, 8, v40
-; GFX11-NEXT:    s_waitcnt vmcnt(51)
-; GFX11-NEXT:    v_lshlrev_b16 v40, 8, v43
-; GFX11-NEXT:    s_waitcnt vmcnt(50)
-; GFX11-NEXT:    v_lshlrev_b16 v43, 8, v44
-; GFX11-NEXT:    s_waitcnt vmcnt(49)
-; GFX11-NEXT:    v_lshlrev_b16 v182, 8, v45
-; GFX11-NEXT:    s_waitcnt vmcnt(48)
-; GFX11-NEXT:    v_lshlrev_b16 v46, 8, v46
-; GFX11-NEXT:    s_waitcnt vmcnt(47)
-; GFX11-NEXT:    v_lshlrev_b16 v45, 8, v47
-; GFX11-NEXT:    s_waitcnt vmcnt(46)
-; GFX11-NEXT:    v_lshlrev_b16 v57, 8, v56
-; GFX11-NEXT:    s_waitcnt vmcnt(45)
-; GFX11-NEXT:    v_lshlrev_b16 v56, 8, v58
-; GFX11-NEXT:    s_waitcnt vmcnt(44)
-; GFX11-NEXT:    v_lshlrev_b16 v58, 8, v59
-; GFX11-NEXT:    s_waitcnt vmcnt(43)
-; GFX11-NEXT:    v_lshlrev_b16 v44, 8, v60
-; GFX11-NEXT:    s_waitcnt vmcnt(42)
-; GFX11-NEXT:    v_lshlrev_b16 v60, 8, v61
-; GFX11-NEXT:    s_waitcnt vmcnt(41)
-; GFX11-NEXT:    v_lshlrev_b16 v59, 8, v62
-; GFX11-NEXT:    s_waitcnt vmcnt(40)
-; GFX11-NEXT:    v_lshlrev_b16 v62, 8, v63
-; GFX11-NEXT:    s_waitcnt vmcnt(39)
-; GFX11-NEXT:    v_lshlrev_b16 v47, 8, v72
-; GFX11-NEXT:    s_waitcnt vmcnt(38)
-; GFX11-NEXT:    v_lshlrev_b16 v72, 8, v73
-; GFX11-NEXT:    s_waitcnt vmcnt(37)
-; GFX11-NEXT:    v_lshlrev_b16 v63, 8, v74
-; GFX11-NEXT:    s_waitcnt vmcnt(36)
-; GFX11-NEXT:    v_lshlrev_b16 v74, 8, v75
-; GFX11-NEXT:    s_waitcnt vmcnt(35)
-; GFX11-NEXT:    v_lshlrev_b16 v73, 8, v76
-; GFX11-NEXT:    s_waitcnt vmcnt(34)
-; GFX11-NEXT:    v_lshlrev_b16 v75, 8, v77
-; GFX11-NEXT:    s_waitcnt vmcnt(33)
-; GFX11-NEXT:    v_lshlrev_b16 v61, 8, v78
-; GFX11-NEXT:    s_waitcnt vmcnt(32)
-; GFX11-NEXT:    v_lshlrev_b16 v78, 8, v79
-; GFX11-NEXT:    s_waitcnt vmcnt(31)
-; GFX11-NEXT:    v_lshlrev_b16 v77, 8, v89
-; GFX11-NEXT:    s_waitcnt vmcnt(30)
-; GFX11-NEXT:    v_lshlrev_b16 v79, 8, v90
-; GFX11-NEXT:    s_waitcnt vmcnt(29)
-; GFX11-NEXT:    v_lshlrev_b16 v76, 8, v95
-; GFX11-NEXT:    s_waitcnt vmcnt(28)
-; GFX11-NEXT:    v_lshlrev_b16 v90, 8, v104
-; GFX11-NEXT:    s_waitcnt vmcnt(27)
-; GFX11-NEXT:    v_lshlrev_b16 v89, 8, v105
-; GFX11-NEXT:    v_lshlrev_b16 v104, 8, v94
-; GFX11-NEXT:    v_lshlrev_b16 v95, 8, v31
-; GFX11-NEXT:    v_lshlrev_b16 v105, 8, v30
-; GFX11-NEXT:    v_lshlrev_b16 v94, 8, v28
-; GFX11-NEXT:    ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB44_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v38
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v35
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v39
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v48
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v70
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v71
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v84
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v82
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v36
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v51
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v34
-; GFX11-NEXT:    v_perm_b32 v1, v3, v2, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v49
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v53
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v50
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v54
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v52
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v115
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v66
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v128
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v113
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v132
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v100
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v161
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v160
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v176
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v167
-; GFX11-NEXT:    v_perm_b32 v2, v2, v4, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v3, v5, v3, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v4, v7, v6, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v5, v9, v8, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v6, v11, v10, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v55
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v37
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v102
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v87
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v114
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v96
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v133
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v117
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v135
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v130
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v181
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v150
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v41
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v40
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v43
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v182
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v46
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v45
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v57
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v56
-; GFX11-NEXT:    v_perm_b32 v7, v8, v7, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v8, v10, v9, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v9, v12, v11, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v10, v14, v13, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v11, v16, v15, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v147
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v119
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v149
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v144
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v162
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v146
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v178
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v164
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v151
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v148
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v58
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v44
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v60
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v59
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v62
-; GFX11-NEXT:    v_or_b32_e32 v17, v17, v47
-; GFX11-NEXT:    v_or_b32_e32 v18, v18, v72
-; GFX11-NEXT:    v_or_b32_e32 v19, v19, v63
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v74
-; GFX11-NEXT:    v_or_b32_e32 v21, v21, v73
-; GFX11-NEXT:    v_perm_b32 v12, v13, v12, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v13, v15, v14, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v14, v17, v16, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v15, v19, v18, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v16, v21, v20, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v166
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v145
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v177
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v163
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v179
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v165
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v183
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v180
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v42
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v65
-; GFX11-NEXT:    v_or_b32_e32 v17, v17, v75
-; GFX11-NEXT:    v_or_b32_e32 v18, v18, v61
-; GFX11-NEXT:    v_or_b32_e32 v19, v19, v78
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v77
-; GFX11-NEXT:    v_or_b32_e32 v21, v21, v79
-; GFX11-NEXT:    v_or_b32_e32 v22, v22, v76
-; GFX11-NEXT:    v_or_b32_e32 v23, v23, v90
-; GFX11-NEXT:    v_or_b32_e32 v24, v24, v89
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v92
-; GFX11-NEXT:    v_or_b32_e32 v26, v26, v91
-; GFX11-NEXT:    v_perm_b32 v17, v18, v17, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v18, v20, v19, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v19, v22, v21, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v20, v24, v23, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v21, v26, v25, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v69
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v64
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v80
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v68
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v85
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v67
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v97
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v83
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v101
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v86
-; GFX11-NEXT:    v_or_b32_e32 v22, v22, v93
-; GFX11-NEXT:    v_or_b32_e32 v23, v23, v88
-; GFX11-NEXT:    v_or_b32_e32 v24, v24, v104
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v95
-; GFX11-NEXT:    v_or_b32_e32 v26, v26, v105
-; GFX11-NEXT:    v_or_b32_e32 v27, v27, v94
-; GFX11-NEXT:    v_or_b32_e32 v28, v28, v108
-; GFX11-NEXT:    v_or_b32_e32 v29, v29, v107
-; GFX11-NEXT:    v_or_b32_e32 v30, v30, v110
-; GFX11-NEXT:    v_or_b32_e32 v31, v31, v109
-; GFX11-NEXT:    v_perm_b32 v22, v23, v22, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v23, v25, v24, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v24, v27, v26, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v25, v29, v28, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v26, v31, v30, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v103
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v81
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v112
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v99
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v129
-; GFX11-NEXT:    v_and_b32_e32 v32, 0xff, v98
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xff, v131
-; GFX11-NEXT:    v_and_b32_e32 v34, 0xff, v116
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xff, v134
-; GFX11-NEXT:    v_and_b32_e32 v36, 0xff, v118
-; GFX11-NEXT:    v_or_b32_e32 v27, v27, v111
-; GFX11-NEXT:    v_or_b32_e32 v28, v28, v106
-; GFX11-NEXT:    v_or_b32_e32 v29, v29, v122
-; GFX11-NEXT:    v_or_b32_e32 v30, v30, v121
-; GFX11-NEXT:    v_or_b32_e32 v31, v31, v123
-; GFX11-NEXT:    v_or_b32_e32 v32, v32, v120
-; GFX11-NEXT:    v_or_b32_e32 v33, v33, v125
-; GFX11-NEXT:    v_or_b32_e32 v34, v34, v124
-; GFX11-NEXT:    v_or_b32_e32 v35, v35, v126
-; GFX11-NEXT:    v_or_b32_e32 v36, v36, v127
-; GFX11-NEXT:    v_perm_b32 v27, v28, v27, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v28, v30, v29, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v29, v32, v31, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v30, v34, v33, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v31, v36, v35, 0x5040100
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr102
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr114
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr133
-; GFX11-NEXT:    ; implicit-def: $vgpr117
-; GFX11-NEXT:    ; implicit-def: $vgpr135
-; GFX11-NEXT:    ; implicit-def: $vgpr130
-; GFX11-NEXT:    ; implicit-def: $vgpr147
-; GFX11-NEXT:    ; implicit-def: $vgpr119
-; GFX11-NEXT:    ; implicit-def: $vgpr149
-; GFX11-NEXT:    ; implicit-def: $vgpr144
-; GFX11-NEXT:    ; implicit-def: $vgpr162
-; GFX11-NEXT:    ; implicit-def: $vgpr146
-; GFX11-NEXT:    ; implicit-def: $vgpr178
-; GFX11-NEXT:    ; implicit-def: $vgpr164
-; GFX11-NEXT:    ; implicit-def: $vgpr151
-; GFX11-NEXT:    ; implicit-def: $vgpr148
-; GFX11-NEXT:    ; implicit-def: $vgpr166
-; GFX11-NEXT:    ; implicit-def: $vgpr145
-; GFX11-NEXT:    ; implicit-def: $vgpr177
-; GFX11-NEXT:    ; implicit-def: $vgpr163
-; GFX11-NEXT:    ; implicit-def: $vgpr179
-; GFX11-NEXT:    ; implicit-def: $vgpr165
-; GFX11-NEXT:    ; implicit-def: $vgpr183
-; GFX11-NEXT:    ; implicit-def: $vgpr180
-; GFX11-NEXT:    ; implicit-def: $vgpr42
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr67
-; GFX11-NEXT:    ; implicit-def: $vgpr97
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr101
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr103
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr112
-; GFX11-NEXT:    ; implicit-def: $vgpr99
-; GFX11-NEXT:    ; implicit-def: $vgpr129
-; GFX11-NEXT:    ; implicit-def: $vgpr98
-; GFX11-NEXT:    ; implicit-def: $vgpr131
-; GFX11-NEXT:    ; implicit-def: $vgpr116
-; GFX11-NEXT:    ; implicit-def: $vgpr134
-; GFX11-NEXT:    ; implicit-def: $vgpr118
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr115
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr128
-; GFX11-NEXT:    ; implicit-def: $vgpr113
-; GFX11-NEXT:    ; implicit-def: $vgpr132
-; GFX11-NEXT:    ; implicit-def: $vgpr100
-; GFX11-NEXT:    ; implicit-def: $vgpr161
-; GFX11-NEXT:    ; implicit-def: $vgpr160
-; GFX11-NEXT:    ; implicit-def: $vgpr176
-; GFX11-NEXT:    ; implicit-def: $vgpr167
-; GFX11-NEXT:    ; implicit-def: $vgpr181
-; GFX11-NEXT:    ; implicit-def: $vgpr150
-; GFX11-NEXT:    ; implicit-def: $vgpr41
-; GFX11-NEXT:    ; implicit-def: $vgpr40
-; GFX11-NEXT:    ; implicit-def: $vgpr43
-; GFX11-NEXT:    ; implicit-def: $vgpr182
-; GFX11-NEXT:    ; implicit-def: $vgpr46
-; GFX11-NEXT:    ; implicit-def: $vgpr45
-; GFX11-NEXT:    ; implicit-def: $vgpr57
-; GFX11-NEXT:    ; implicit-def: $vgpr56
-; GFX11-NEXT:    ; implicit-def: $vgpr58
-; GFX11-NEXT:    ; implicit-def: $vgpr44
-; GFX11-NEXT:    ; implicit-def: $vgpr60
-; GFX11-NEXT:    ; implicit-def: $vgpr59
-; GFX11-NEXT:    ; implicit-def: $vgpr62
-; GFX11-NEXT:    ; implicit-def: $vgpr47
-; GFX11-NEXT:    ; implicit-def: $vgpr72
-; GFX11-NEXT:    ; implicit-def: $vgpr63
-; GFX11-NEXT:    ; implicit-def: $vgpr74
-; GFX11-NEXT:    ; implicit-def: $vgpr73
-; GFX11-NEXT:    ; implicit-def: $vgpr75
-; GFX11-NEXT:    ; implicit-def: $vgpr61
-; GFX11-NEXT:    ; implicit-def: $vgpr78
-; GFX11-NEXT:    ; implicit-def: $vgpr77
-; GFX11-NEXT:    ; implicit-def: $vgpr79
-; GFX11-NEXT:    ; implicit-def: $vgpr76
-; GFX11-NEXT:    ; implicit-def: $vgpr90
-; GFX11-NEXT:    ; implicit-def: $vgpr89
-; GFX11-NEXT:    ; implicit-def: $vgpr92
-; GFX11-NEXT:    ; implicit-def: $vgpr91
-; GFX11-NEXT:    ; implicit-def: $vgpr93
-; GFX11-NEXT:    ; implicit-def: $vgpr88
-; GFX11-NEXT:    ; implicit-def: $vgpr104
-; GFX11-NEXT:    ; implicit-def: $vgpr95
-; GFX11-NEXT:    ; implicit-def: $vgpr105
-; GFX11-NEXT:    ; implicit-def: $vgpr94
-; GFX11-NEXT:    ; implicit-def: $vgpr108
-; GFX11-NEXT:    ; implicit-def: $vgpr107
-; GFX11-NEXT:    ; implicit-def: $vgpr110
-; GFX11-NEXT:    ; implicit-def: $vgpr109
-; GFX11-NEXT:    ; implicit-def: $vgpr111
-; GFX11-NEXT:    ; implicit-def: $vgpr106
-; GFX11-NEXT:    ; implicit-def: $vgpr122
-; GFX11-NEXT:    ; implicit-def: $vgpr121
-; GFX11-NEXT:    ; implicit-def: $vgpr123
-; GFX11-NEXT:    ; implicit-def: $vgpr120
-; GFX11-NEXT:    ; implicit-def: $vgpr125
-; GFX11-NEXT:    ; implicit-def: $vgpr124
-; GFX11-NEXT:    ; implicit-def: $vgpr126
-; GFX11-NEXT:    ; implicit-def: $vgpr127
-; GFX11-NEXT:  .LBB44_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB44_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v134, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v118, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v131, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v116, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v129, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_add_nc_u16 v35, v35, 3
-; GFX11-NEXT:    v_or_b32_e32 v0, v126, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v127, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v125, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v124, v3
-; GFX11-NEXT:    v_add_nc_u16 v33, v33, 3
-; GFX11-NEXT:    v_add_nc_u16 v31, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v98, 3
-; GFX11-NEXT:    v_add_nc_u16 v116, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v30, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v98, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v1, v112, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v4
-; GFX11-NEXT:    v_add_nc_u16 v3, v99, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v4, v103, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v123, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v0, v120, v0
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v1, v122, v1
-; GFX11-NEXT:    v_add_nc_u16 v29, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v121, v3
-; GFX11-NEXT:    v_add_nc_u16 v99, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v111, v4
-; GFX11-NEXT:    v_add_nc_u16 v28, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v81, 3
-; GFX11-NEXT:    v_add_nc_u16 v81, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v101, 3
-; GFX11-NEXT:    v_add_nc_u16 v27, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v86, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v3, v97, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v4, v83, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v106, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v110, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v0, v109, v0
-; GFX11-NEXT:    v_add_nc_u16 v83, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v108, v3
-; GFX11-NEXT:    v_add_nc_u16 v26, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v107, v4
-; GFX11-NEXT:    v_add_nc_u16 v86, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v85, 3
-; GFX11-NEXT:    v_add_nc_u16 v25, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v67, 3
-; GFX11-NEXT:    v_add_nc_u16 v67, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v80, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v3, v68, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v4, v69, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_or_b32_e32 v0, v105, v0
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v1, v94, v1
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v2, v104, v2
-; GFX11-NEXT:    v_add_nc_u16 v24, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v95, v3
-; GFX11-NEXT:    v_add_nc_u16 v68, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v93, v4
-; GFX11-NEXT:    v_add_nc_u16 v23, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v64, 3
-; GFX11-NEXT:    v_add_nc_u16 v64, 0x300, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(26)
-; GFX11-NEXT:    v_add_nc_u16 v0, v42, 3
-; GFX11-NEXT:    v_add_nc_u16 v22, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v65, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(24)
-; GFX11-NEXT:    v_add_nc_u16 v3, v183, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v4, v180, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v88, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v0, v92, v0
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v1, v91, v1
-; GFX11-NEXT:    v_add_nc_u16 v65, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v90, v3
-; GFX11-NEXT:    v_add_nc_u16 v21, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v89, v4
-; GFX11-NEXT:    v_add_nc_u16 v69, 0x300, v1
-; GFX11-NEXT:    s_waitcnt vmcnt(22)
-; GFX11-NEXT:    v_add_nc_u16 v1, v179, 3
-; GFX11-NEXT:    v_add_nc_u16 v20, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v165, 3
-; GFX11-NEXT:    v_add_nc_u16 v80, 0x300, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(20)
-; GFX11-NEXT:    v_add_nc_u16 v0, v177, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v3, v163, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(18)
-; GFX11-NEXT:    v_add_nc_u16 v4, v166, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v79, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v76, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v0, v78, v0
-; GFX11-NEXT:    v_add_nc_u16 v19, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v77, v3
-; GFX11-NEXT:    v_add_nc_u16 v85, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v75, v4
-; GFX11-NEXT:    v_add_nc_u16 v18, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v145, 3
-; GFX11-NEXT:    v_add_nc_u16 v97, 0x300, v1
-; GFX11-NEXT:    s_waitcnt vmcnt(16)
-; GFX11-NEXT:    v_add_nc_u16 v1, v151, 3
-; GFX11-NEXT:    v_add_nc_u16 v17, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v148, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(14)
-; GFX11-NEXT:    v_add_nc_u16 v3, v178, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v4, v164, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_or_b32_e32 v0, v61, v0
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v1, v74, v1
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v2, v73, v2
-; GFX11-NEXT:    v_add_nc_u16 v101, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v72, v3
-; GFX11-NEXT:    v_add_nc_u16 v16, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v63, v4
-; GFX11-NEXT:    v_add_nc_u16 v103, 0x300, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(12)
-; GFX11-NEXT:    v_add_nc_u16 v2, v162, 3
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v146, 3
-; GFX11-NEXT:    v_add_nc_u16 v112, 0x300, v1
-; GFX11-NEXT:    s_waitcnt vmcnt(10)
-; GFX11-NEXT:    v_add_nc_u16 v1, v149, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, v144, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(8)
-; GFX11-NEXT:    v_add_nc_u16 v4, v147, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v62, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v0, v47, v0
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v1, v60, v1
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v59, v3
-; GFX11-NEXT:    v_add_nc_u16 v118, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v58, v4
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v119, 3
-; GFX11-NEXT:    v_add_nc_u16 v119, 0x300, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(6)
-; GFX11-NEXT:    v_add_nc_u16 v2, v135, 3
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v130, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    s_waitcnt vmcnt(4)
-; GFX11-NEXT:    v_add_nc_u16 v3, v133, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v4, v117, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v44, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v57, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v0, v56, v0
-; GFX11-NEXT:    v_add_nc_u16 v117, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v46, v3
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v45, v4
-; GFX11-NEXT:    v_add_nc_u16 v129, 0x300, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(2)
-; GFX11-NEXT:    v_add_nc_u16 v0, v114, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v96, 3
-; GFX11-NEXT:    v_add_nc_u16 v96, 0x300, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_nc_u16 v2, v102, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v3, v87, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v4, v55, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_or_b32_e32 v0, v43, v0
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v1, v182, v1
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v2, v41, v2
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v40, v3
-; GFX11-NEXT:    v_add_nc_u16 v55, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v181, v4
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v37, 3
-; GFX11-NEXT:    v_add_nc_u16 v37, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v54, 3
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v52, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, v53, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v4, v50, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v150, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v0, v176, v0
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v1, v167, v1
-; GFX11-NEXT:    v_add_nc_u16 v50, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v161, v3
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v160, v4
-; GFX11-NEXT:    v_add_nc_u16 v52, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v51, 3
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v49, 3
-; GFX11-NEXT:    v_add_nc_u16 v49, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v48, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v3, v34, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v4, v36, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v132, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v128, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v0, v115, v0
-; GFX11-NEXT:    v_add_nc_u16 v34, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v100, v3
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v113, v4
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v39, 3
-; GFX11-NEXT:    v_add_nc_u16 v36, v38, 3
-; GFX11-NEXT:    v_add_nc_u16 v32, v32, 3
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xff, v35
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v36, 0xff, v36
-; GFX11-NEXT:    v_and_b32_e32 v32, 0xff, v32
-; GFX11-NEXT:    v_or_b32_e32 v35, v71, v35
-; GFX11-NEXT:    v_or_b32_e32 v33, v82, v33
-; GFX11-NEXT:    v_or_b32_e32 v0, v84, v0
-; GFX11-NEXT:    v_or_b32_e32 v36, v70, v36
-; GFX11-NEXT:    v_or_b32_e32 v32, v66, v32
-; GFX11-NEXT:    v_add_nc_u16 v35, 0x300, v35
-; GFX11-NEXT:    v_add_nc_u16 v33, 0x300, v33
-; GFX11-NEXT:    v_add_nc_u16 v38, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v36
-; GFX11-NEXT:    v_add_nc_u16 v32, 0x300, v32
-; GFX11-NEXT:    v_add_nc_u16 v36, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v39, 0x300, v1
-; GFX11-NEXT:    v_perm_b32 v1, v33, v38, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v0, v35, v0, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v2, v32, v4, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v3, v36, v3, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v4, v39, v34, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v5, v49, v5, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v6, v52, v6, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v7, v50, v7, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v8, v37, v8, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v9, v55, v9, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v10, v96, v10, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v11, v129, v11, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v12, v117, v12, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v13, v119, v13, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v14, v118, v14, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v15, v112, v15, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v16, v103, v16, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v17, v101, v17, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v18, v97, v18, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v19, v85, v19, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v20, v80, v20, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v21, v69, v21, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v22, v65, v22, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v23, v64, v23, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v24, v68, v24, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v25, v67, v25, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v26, v86, v26, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v27, v83, v27, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v28, v81, v28, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v29, v99, v29, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v30, v98, v30, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v31, v116, v31, 0x5040100
-; GFX11-NEXT:  .LBB44_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_b32 v127, off, s32 offset:392
-; GFX11-NEXT:    scratch_load_b32 v126, off, s32 offset:396
-; GFX11-NEXT:    scratch_load_b32 v125, off, s32 offset:400
-; GFX11-NEXT:    scratch_load_b32 v124, off, s32 offset:404
-; GFX11-NEXT:    scratch_load_b32 v123, off, s32 offset:408
-; GFX11-NEXT:    scratch_load_b32 v122, off, s32 offset:412
-; GFX11-NEXT:    scratch_load_b32 v121, off, s32 offset:416
-; GFX11-NEXT:    scratch_load_b32 v120, off, s32 offset:420
-; GFX11-NEXT:    scratch_load_b32 v111, off, s32 offset:424
-; GFX11-NEXT:    scratch_load_b32 v110, off, s32 offset:428
-; GFX11-NEXT:    scratch_load_b32 v109, off, s32 offset:432
-; GFX11-NEXT:    scratch_load_b32 v108, off, s32 offset:436
-; GFX11-NEXT:    scratch_load_b32 v107, off, s32 offset:440
-; GFX11-NEXT:    scratch_load_b32 v106, off, s32 offset:444
-; GFX11-NEXT:    scratch_load_b32 v105, off, s32 offset:448
-; GFX11-NEXT:    scratch_load_b32 v104, off, s32 offset:452
-; GFX11-NEXT:    scratch_load_b32 v95, off, s32 offset:456
-; GFX11-NEXT:    scratch_load_b32 v94, off, s32 offset:460
-; GFX11-NEXT:    scratch_load_b32 v93, off, s32 offset:464
-; GFX11-NEXT:    scratch_load_b32 v92, off, s32 offset:468
-; GFX11-NEXT:    scratch_load_b32 v91, off, s32 offset:472
-; GFX11-NEXT:    scratch_load_b32 v90, off, s32 offset:476
-; GFX11-NEXT:    scratch_load_b32 v89, off, s32 offset:480
-; GFX11-NEXT:    scratch_load_b32 v88, off, s32 offset:484
-; GFX11-NEXT:    scratch_load_b32 v79, off, s32 offset:488
-; GFX11-NEXT:    scratch_load_b32 v78, off, s32 offset:492
-; GFX11-NEXT:    scratch_load_b32 v77, off, s32 offset:496
-; GFX11-NEXT:    scratch_load_b32 v76, off, s32 offset:500
-; GFX11-NEXT:    scratch_load_b32 v75, off, s32 offset:504
-; GFX11-NEXT:    scratch_load_b32 v74, off, s32 offset:508
-; GFX11-NEXT:    scratch_load_b32 v73, off, s32 offset:512
-; GFX11-NEXT:    scratch_load_b32 v72, off, s32 offset:516
-; GFX11-NEXT:    s_clause 0xf
-; GFX11-NEXT:    scratch_load_b32 v63, off, s32 offset:520
-; GFX11-NEXT:    scratch_load_b32 v62, off, s32 offset:524
-; GFX11-NEXT:    scratch_load_b32 v61, off, s32 offset:528
-; GFX11-NEXT:    scratch_load_b32 v60, off, s32 offset:532
-; GFX11-NEXT:    scratch_load_b32 v59, off, s32 offset:536
-; GFX11-NEXT:    scratch_load_b32 v58, off, s32 offset:540
-; GFX11-NEXT:    scratch_load_b32 v57, off, s32 offset:544
-; GFX11-NEXT:    scratch_load_b32 v56, off, s32 offset:548
-; GFX11-NEXT:    scratch_load_b32 v47, off, s32 offset:552
-; GFX11-NEXT:    scratch_load_b32 v46, off, s32 offset:556
-; GFX11-NEXT:    scratch_load_b32 v45, off, s32 offset:560
-; GFX11-NEXT:    scratch_load_b32 v44, off, s32 offset:564
-; GFX11-NEXT:    scratch_load_b32 v43, off, s32 offset:568
-; GFX11-NEXT:    scratch_load_b32 v42, off, s32 offset:572
-; GFX11-NEXT:    scratch_load_b32 v41, off, s32 offset:576
-; GFX11-NEXT:    scratch_load_b32 v40, off, s32 offset:580
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v128i8_to_v64bf16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32 offset:384
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v39, off, s32 offset:380
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v31, off, s32 offset:376
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v50, off, s32 offset:372
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v150, off, s32 offset:368
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v39, off, s32 offset:364
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v150, off, s32 offset:360
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v50, off, s32 offset:356
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v147, off, s32 offset:352
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v37, off, s32 offset:348
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v149, off, s32 offset:344
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v49, off, s32 offset:340
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v149, off, s32 offset:336
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v38, off, s32 offset:332
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v148, off, s32 offset:328
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v48, off, s32 offset:324
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v145, off, s32 offset:320
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v34, off, s32 offset:316
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v148, off, s32 offset:312
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v48, off, s32 offset:308
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v147, off, s32 offset:304
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v36, off, s32 offset:300
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v146, off, s32 offset:296
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v38, off, s32 offset:292
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v146, off, s32 offset:288
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v36, off, s32 offset:284
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v145, off, s32 offset:280
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v37, off, s32 offset:276
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v134, off, s32 offset:272
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v33, off, s32 offset:268
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v144, off, s32 offset:264
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v35, off, s32 offset:260
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v144, off, s32 offset:256
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v33, off, s32 offset:252
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v135, off, s32 offset:248
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v35, off, s32 offset:244
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v132, off, s32 offset:240
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v32, off, s32 offset:236
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v135, off, s32 offset:232
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v34, off, s32 offset:228
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v134, off, s32 offset:224
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v32, off, s32 offset:220
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v133, off, s32 offset:216
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v160, off, s32 offset:388
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v101, off, s32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v103, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v113, off, s32 offset:16
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v113, off, s32 offset:24
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v114, off, s32 offset:32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v114, off, s32 offset:40
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v115, off, s32 offset:48
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v116, off, s32 offset:56
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v116, off, s32 offset:64
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v117, off, s32 offset:72
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v117, off, s32 offset:80
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v118, off, s32 offset:88
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v118, off, s32 offset:96
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v119, off, s32 offset:104
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v119, off, s32 offset:112
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v128, off, s32 offset:120
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v128, off, s32 offset:128
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v129, off, s32 offset:136
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v129, off, s32 offset:144
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v130, off, s32 offset:152
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v130, off, s32 offset:160
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v131, off, s32 offset:168
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v131, off, s32 offset:176
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v132, off, s32 offset:184
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v133, off, s32 offset:192
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v151, off, s32 offset:200
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v151, off, s32 offset:208
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v100, off, s32 offset:212
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v98, off, s32 offset:204
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v100, off, s32 offset:196
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v85, off, s32 offset:188
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v97, off, s32 offset:180
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v86, off, s32 offset:172
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v96, off, s32 offset:164
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v71, off, s32 offset:156
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v87, off, s32 offset:148
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v80, off, s32 offset:140
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v84, off, s32 offset:132
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v86, off, s32 offset:124
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v96, off, s32 offset:116
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v80, off, s32 offset:108
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v85, off, s32 offset:100
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v82, off, s32 offset:92
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v84, off, s32 offset:84
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v69, off, s32 offset:76
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v83, off, s32 offset:68
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v69, off, s32 offset:60
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v71, off, s32 offset:52
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v68, off, s32 offset:44
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v70, off, s32 offset:36
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v66, off, s32 offset:28
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v68, off, s32 offset:20
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v66, off, s32 offset:12
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v67, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v54.l, v30.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v67.l, v28.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.h, v26.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.h, v24.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v22.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.l, v20.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v52.l, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.h, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.h, v14.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v49.h, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v54.h, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v51.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.l, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v51.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v52.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v81.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v81.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v82.h, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v83.l, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v97.h, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v70.l, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v98.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v99.l, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v99.h, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v87.l, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v101.h, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v102.l, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v102.h, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v103.l, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v112.l, 8, v29.l
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(62)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v150.h, 8, v150.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v150.l, 8, v150.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v147.h, 8, v147.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v149.h, 8, v149.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v149.l, 8, v149.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v148.h, 8, v148.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v145.l, 8, v145.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v148.l, 8, v148.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v147.l, 8, v147.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v146.h, 8, v146.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v146.l, 8, v146.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v145.h, 8, v145.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v134.h, 8, v134.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v144.h, 8, v144.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v144.l, 8, v144.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v135.h, 8, v135.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(61)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v132.l, 8, v132.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(59)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v135.l, 8, v135.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(57)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v134.l, 8, v134.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(55)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v133.h, 8, v133.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(54)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v160
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(53)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v101.l, 8, v101.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(52)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v112.h, 8, v103.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(51)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v113.l, 8, v113.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(50)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v113.h, 8, v113.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(49)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v103.h, 8, v114.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(48)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v115.l, 8, v114.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(47)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v115.h, 8, v115.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(46)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v116.l, 8, v116.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(45)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v116.h, 8, v116.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(44)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v117.l, 8, v117.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(43)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v114.l, 8, v117.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(42)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v118.l, 8, v118.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(41)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v118.h, 8, v118.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(40)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v119.l, 8, v119.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(39)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v114.h, 8, v119.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(38)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v119.h, 8, v128.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(37)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v128.l, 8, v128.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(36)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v128.h, 8, v129.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(35)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v129.l, 8, v129.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(34)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v130.l, 8, v130.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v117.h, 8, v130.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(32)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v130.h, 8, v131.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v131.l, 8, v131.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(30)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v131.h, 8, v132.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(29)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v129.h, 8, v133.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(28)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v132.h, 8, v151.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(27)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v133.l, 8, v151.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v151.l, 8, v31.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v151.h, 8, v31.l
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB44_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB44_4
+; GFX11-TRUE16-NEXT:  .LBB44_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB44_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v52.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v51.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v53.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v51.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v54.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v49.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v55.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v53.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v55.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v52.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v65.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v64.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v65.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v64.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v67.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v54.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v67.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v66.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v68.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.h, 0xff, v66.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v70.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.h, 0xff, v68.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v71.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.h, 0xff, v69.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v83.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v69.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v84.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v82.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v85.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.h, 0xff, v80.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.l, 0xff, v96.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.h, 0xff, v86.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v16.l, 0xff, v84.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v16.h, 0xff, v80.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v87.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.h, 0xff, v71.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v96.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.h, 0xff, v86.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v97.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.h, 0xff, v85.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v20.l, 0xff, v100.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v20.h, 0xff, v98.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v21.l, 0xff, v100.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v21.h, 0xff, v32.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v34.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.h, 0xff, v32.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v35.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.h, 0xff, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v35.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.h, 0xff, v33.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v25.l, 0xff, v37.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v25.h, 0xff, v36.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v26.l, 0xff, v38.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v26.h, 0xff, v36.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.l, 0xff, v48.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.h, 0xff, v34.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.l, 0xff, v48.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.h, 0xff, v38.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v29.l, 0xff, v49.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v29.h, 0xff, v37.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v30.l, 0xff, v50.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v30.h, 0xff, v39.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v31.l, 0xff, v50.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v31.h, 0xff, v39.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v81.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v81.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v82.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v1.h, v83.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v97.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v2.h, v70.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v98.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v3.h, v99.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v99.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.h, v4.h, v87.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v101.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.h, v5.h, v102.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v102.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v6.h, v103.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v112.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v7.h, v101.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v112.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.h, v8.h, v113.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v113.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.h, v9.h, v103.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v115.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.h, v10.h, v115.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v116.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.h, v11.h, v116.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v117.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.h, v12.h, v114.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v118.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.h, v13.h, v118.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v119.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.h, v14.h, v114.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v15.l, v119.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.h, v15.h, v128.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v16.l, v128.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.h, v16.h, v129.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v17.l, v130.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.h, v17.h, v117.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v18.l, v130.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.h, v18.h, v131.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v19.l, v131.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.h, v19.h, v129.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v20.l, v132.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.h, v20.h, v133.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v21.l, v21.l, v133.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v21.h, v21.h, v134.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v22.l, v135.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.h, v22.h, v132.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v23.l, v135.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.h, v23.h, v144.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v24.l, v144.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.h, v24.h, v134.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v25.l, v25.l, v145.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v25.h, v25.h, v146.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v26.l, v26.l, v146.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v26.h, v26.h, v147.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.l, v27.l, v148.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.h, v27.h, v145.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.l, v28.l, v148.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.h, v28.h, v149.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v29.l, v29.l, v149.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v29.h, v29.h, v147.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v30.l, v30.l, v150.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v30.h, v30.h, v150.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v31.l, v31.l, v151.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v31.h, v31.h, v151.h
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr67_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr68_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr71_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr85_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr86_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr97_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr100_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr83_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr70_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr99_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr103_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr101_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr112_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr113_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr115_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr116_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr116_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr117_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr114_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr118_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr118_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr119_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr114_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr128_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr128_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr130_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr130_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr131_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr131_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr129_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr132_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr133_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr133_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr134_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr132_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr135_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr144_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr144_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr134_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr145_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr146_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr147_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr148_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr145_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr148_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr149_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr147_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr150_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr150_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr151_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB44_2
+; GFX11-TRUE16-NEXT:  .LBB44_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v50.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v39.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v50.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v39.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v48.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v151.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v151.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v150.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v150.h, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v148.l, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v31.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v31.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v30.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v30.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v49.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v37.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v48.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v38.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v36.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v149.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v147.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v148.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v149.l, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v29.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v29.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v34.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v38.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v36.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v37.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v146.l, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v25.h, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v145.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v146.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v147.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v145.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v34.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v26.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v26.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v25.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v35.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v33.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v35.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v33.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v135.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v144.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v134.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v135.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v144.l, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v24.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v24.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v32.l, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(26)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v100.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v32.h, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(24)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v100.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v98.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v132.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v133.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v134.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v132.h, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v133.l, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v21.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v21.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v20.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(22)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v97.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v85.h, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(20)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v96.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v86.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v20.h, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(18)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v87.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v131.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v129.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v130.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v131.l, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v19.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v19.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v71.h, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(16)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v84.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v80.h, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(14)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v96.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v130.l, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v117.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v128.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v129.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v119.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v86.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v16.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v16.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(12)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v85.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v80.l, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(10)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v84.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v82.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v128.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v119.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v114.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v118.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v118.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.h, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(8)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v83.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v69.l, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(6)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v71.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v69.h, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v70.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v117.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v114.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v116.l, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v116.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v115.l, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v68.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v68.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v66.l, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v67.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v66.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v115.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v113.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v103.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v112.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v113.l, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.h, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v67.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v54.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v65.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v64.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v65.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v112.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v101.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v102.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v103.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v101.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v64.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v55.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v52.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v55.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v53.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v102.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v99.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v87.l, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v98.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v99.l, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v54.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v49.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v53.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v51.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v52.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v51.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v97.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v70.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v82.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v32.l, v83.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v32.h, v81.l, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v33.l, v81.h, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, 0x300, v32.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v32.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, 0x300, v33.l
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v128i8_to_v64bf16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s32 offset:580
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v41, s32 offset:576
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v42, s32 offset:572
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v43, s32 offset:568
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v44, s32 offset:564
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v45, s32 offset:560
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v46, s32 offset:556
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v47, s32 offset:552
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v56, s32 offset:548
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v57, s32 offset:544
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v58, s32 offset:540
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v59, s32 offset:536
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v60, s32 offset:532
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v61, s32 offset:528
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v62, s32 offset:524
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v63, s32 offset:520
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v72, s32 offset:516
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v73, s32 offset:512
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v74, s32 offset:508
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v75, s32 offset:504
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v76, s32 offset:500
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v77, s32 offset:496
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v78, s32 offset:492
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v79, s32 offset:488
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v88, s32 offset:484
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v89, s32 offset:480
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v90, s32 offset:476
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v91, s32 offset:472
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v92, s32 offset:468
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v93, s32 offset:464
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v94, s32 offset:460
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v95, s32 offset:456
+; GFX11-FAKE16-NEXT:    s_clause 0xf
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v104, s32 offset:452
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v105, s32 offset:448
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v106, s32 offset:444
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v107, s32 offset:440
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v108, s32 offset:436
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v109, s32 offset:432
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v110, s32 offset:428
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v111, s32 offset:424
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v120, s32 offset:420
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v121, s32 offset:416
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v122, s32 offset:412
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v123, s32 offset:408
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v124, s32 offset:404
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v125, s32 offset:400
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v126, s32 offset:396
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v127, s32 offset:392
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v37, v30 :: v_dual_mov_b32 v54, v24
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v55, v28 :: v_dual_mov_b32 v52, v26
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v50, v22 :: v_dual_mov_b32 v53, v20
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v34, v18 :: v_dual_mov_b32 v51, v16
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v36, v14 :: v_dual_mov_b32 v49, v12
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v32, v10 :: v_dual_mov_b32 v39, v4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v48, v8 :: v_dual_mov_b32 v33, v6
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v35, v2 :: v_dual_mov_b32 v38, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v0, off, s32 offset:384
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v118, off, s32 offset:380
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32 offset:376
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v134, off, s32 offset:372
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v4, off, s32 offset:368
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v116, off, s32 offset:364
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v6, off, s32 offset:360
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v131, off, s32 offset:356
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v8, off, s32 offset:352
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v98, off, s32 offset:348
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v10, off, s32 offset:344
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v129, off, s32 offset:340
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v12, off, s32 offset:336
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v99, off, s32 offset:332
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v14, off, s32 offset:328
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v112, off, s32 offset:324
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v16, off, s32 offset:320
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v81, off, s32 offset:316
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v18, off, s32 offset:312
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v103, off, s32 offset:308
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v20, off, s32 offset:304
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v86, off, s32 offset:300
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v22, off, s32 offset:296
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v101, off, s32 offset:292
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v24, off, s32 offset:288
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v83, off, s32 offset:284
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v26, off, s32 offset:280
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v97, off, s32 offset:276
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v28, off, s32 offset:272
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v67, off, s32 offset:268
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v30, off, s32 offset:264
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v85, off, s32 offset:260
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v31, off, s32 offset:256
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v68, off, s32 offset:252
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v94, off, s32 offset:248
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v80, off, s32 offset:244
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v88, off, s32 offset:240
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v64, off, s32 offset:236
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v93, off, s32 offset:232
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v69, off, s32 offset:228
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v91, off, s32 offset:224
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v65, off, s32 offset:220
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v92, off, s32 offset:216
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v150, off, s32 offset:388
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v182, off, s32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v40, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v43, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v44, off, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v45, off, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v46, off, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v47, off, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v56, off, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v58, off, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v59, off, s32 offset:72
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v60, off, s32 offset:80
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v61, off, s32 offset:88
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v62, off, s32 offset:96
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v63, off, s32 offset:104
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v72, off, s32 offset:112
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v73, off, s32 offset:120
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v74, off, s32 offset:128
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v75, off, s32 offset:136
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v76, off, s32 offset:144
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v77, off, s32 offset:152
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v78, off, s32 offset:160
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v79, off, s32 offset:168
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v89, off, s32 offset:176
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v90, off, s32 offset:184
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v95, off, s32 offset:192
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v104, off, s32 offset:200
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v105, off, s32 offset:208
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v42, off, s32 offset:212
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v180, off, s32 offset:204
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v183, off, s32 offset:196
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v165, off, s32 offset:188
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v179, off, s32 offset:180
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v163, off, s32 offset:172
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v177, off, s32 offset:164
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v145, off, s32 offset:156
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v166, off, s32 offset:148
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v148, off, s32 offset:140
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v151, off, s32 offset:132
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v164, off, s32 offset:124
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v178, off, s32 offset:116
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v146, off, s32 offset:108
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v162, off, s32 offset:100
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v144, off, s32 offset:92
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v149, off, s32 offset:84
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v119, off, s32 offset:76
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v147, off, s32 offset:68
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v130, off, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v135, off, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v117, off, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v133, off, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v96, off, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v114, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v87, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v102, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v70, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v71, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v84, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v82, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v115, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v66, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v128, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v113, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v132, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v100, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v161, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v160, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v176, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v167, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v181, 8, v29
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(62)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v127, 8, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v126, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v124, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v125, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v120, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v123, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v121, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v122, 8, v14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v106, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v111, 8, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v109, 8, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v110, 8, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v107, 8, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v108, 8, v26
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(61)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v88, 8, v88
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(59)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v93, 8, v93
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(57)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v91, 8, v91
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(55)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v92, 8, v92
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(54)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v150
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(53)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v150, 8, v182
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(52)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v41, 8, v40
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(51)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v40, 8, v43
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(50)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v43, 8, v44
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(49)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v182, 8, v45
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(48)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v46, 8, v46
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(47)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v45, 8, v47
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(46)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v57, 8, v56
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(45)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v56, 8, v58
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(44)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v58, 8, v59
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(43)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v44, 8, v60
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(42)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v60, 8, v61
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(41)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v59, 8, v62
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(40)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v62, 8, v63
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(39)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v47, 8, v72
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(38)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v72, 8, v73
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(37)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v63, 8, v74
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(36)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v74, 8, v75
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(35)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v73, 8, v76
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(34)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v75, 8, v77
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v61, 8, v78
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(32)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v78, 8, v79
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v77, 8, v89
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(30)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v79, 8, v90
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(29)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v76, 8, v95
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(28)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v90, 8, v104
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(27)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v89, 8, v105
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v104, 8, v94
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v95, 8, v31
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v105, 8, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v94, 8, v28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB44_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v38
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v48
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v70
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v71
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v84
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v82
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v51
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v49
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v53
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v50
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v52
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v115
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v66
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v128
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v113
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v132
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v100
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v161
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v160
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v176
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v167
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v4, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v5, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v7, v6, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v9, v8, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v11, v10, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v37
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v102
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v87
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v114
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v96
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v133
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v117
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v135
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v130
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v181
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v150
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v41
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v40
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v43
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v182
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v46
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v45
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v57
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v56
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v8, v7, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v10, v9, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v12, v11, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v14, v13, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v16, v15, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v147
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v119
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v149
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v144
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v162
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v146
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v178
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v164
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v151
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v148
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v58
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v44
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v60
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v59
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v62
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v17, v47
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v18, v72
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v19, v63
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v74
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v21, v73
+; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v13, v12, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v15, v14, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v17, v16, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v19, v18, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v16, v21, v20, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v166
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v145
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v177
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v163
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v179
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v165
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v183
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v180
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v42
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v17, v75
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v18, v61
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v19, v78
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v77
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v21, v79
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v22, v76
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v23, v90
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v24, v89
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v92
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v26, v91
+; GFX11-FAKE16-NEXT:    v_perm_b32 v17, v18, v17, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v18, v20, v19, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v19, v22, v21, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v20, v24, v23, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v21, v26, v25, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v69
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v64
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v68
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v67
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v97
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v83
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v101
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v86
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v22, v93
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v23, v88
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v24, v104
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v95
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v26, v105
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v27, v94
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v28, v108
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v29, v107
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v30, v110
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v31, v109
+; GFX11-FAKE16-NEXT:    v_perm_b32 v22, v23, v22, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v23, v25, v24, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v24, v27, v26, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v25, v29, v28, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v26, v31, v30, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v103
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v81
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v112
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v99
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v129
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v32, 0xff, v98
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xff, v131
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v34, 0xff, v116
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xff, v134
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v36, 0xff, v118
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v27, v111
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v28, v106
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v29, v122
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v30, v121
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v31, v123
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v32, v32, v120
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v33, v33, v125
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v34, v34, v124
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, v35, v126
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, v36, v127
+; GFX11-FAKE16-NEXT:    v_perm_b32 v27, v28, v27, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v28, v30, v29, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v29, v32, v31, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v30, v34, v33, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v31, v36, v35, 0x5040100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr135
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr147
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr149
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr144
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr162
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr178
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr164
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr151
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr148
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr166
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr177
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr163
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr179
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr165
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr183
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr180
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr42
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr161
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr160
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr176
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr167
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr181
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr150
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr41
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr40
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr43
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr182
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr46
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr45
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr57
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr56
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr58
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr44
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr60
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr59
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr62
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr47
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr72
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr63
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr74
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr73
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr75
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr61
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr78
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr77
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr79
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr76
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr90
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr89
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr92
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr91
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr93
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr88
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr104
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr95
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr105
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr94
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr108
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr107
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr110
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr109
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr111
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr106
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr122
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr121
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr123
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr120
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr125
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr124
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr126
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr127
+; GFX11-FAKE16-NEXT:  .LBB44_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB44_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v134, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v118, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v131, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v116, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v129, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v35, v35, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v126, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v127, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v125, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v124, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v33, v33, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v31, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v98, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v116, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v30, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v98, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v112, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v99, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v103, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v123, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v120, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v122, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v29, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v121, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v99, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v111, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v28, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v81, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v81, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v101, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v27, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v86, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v97, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v83, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v106, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v110, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v109, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v83, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v108, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v26, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v107, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v86, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v85, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v25, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v67, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v67, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v80, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v68, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v69, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v105, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v94, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v104, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v24, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v95, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v68, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v93, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v23, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v64, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v64, 0x300, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(26)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v42, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v65, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(24)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v183, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v180, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v88, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v92, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v91, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v65, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v90, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v89, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v69, 0x300, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(22)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v179, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v165, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v80, 0x300, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(20)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v177, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v163, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(18)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v166, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v79, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v76, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v78, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v77, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v85, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v75, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v145, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v97, 0x300, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(16)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v151, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v148, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(14)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v178, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v164, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v61, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v74, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v73, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v101, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v72, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v63, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v103, 0x300, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(12)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v162, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v146, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v112, 0x300, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(10)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v149, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v144, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(8)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v147, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v62, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v47, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v60, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v59, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v118, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v58, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v119, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v119, 0x300, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(6)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v135, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v130, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(4)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v133, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v117, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v44, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v57, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v56, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v117, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v46, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v45, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v129, 0x300, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v114, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v96, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v96, 0x300, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v102, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v87, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v55, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v43, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v182, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v41, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v40, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v55, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v181, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v37, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v37, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v54, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v52, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v53, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v50, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v150, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v176, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v167, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v50, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v161, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v160, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v52, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v51, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v49, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v49, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v48, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v34, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v36, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v132, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v128, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v115, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v34, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v100, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v113, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v39, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v36, v38, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v32, v32, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v36, 0xff, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v32, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, v71, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v33, v82, v33
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v84, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, v70, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v32, v66, v32
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v35, 0x300, v35
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v33, 0x300, v33
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v38, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v36
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v32, 0x300, v32
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v36, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v39, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v33, v38, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v35, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v32, v4, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v36, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v39, v34, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v49, v5, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v52, v6, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v50, v7, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v37, v8, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v55, v9, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v96, v10, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v129, v11, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v117, v12, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v119, v13, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v118, v14, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v112, v15, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v16, v103, v16, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v17, v101, v17, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v18, v97, v18, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v19, v85, v19, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v20, v80, v20, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v21, v69, v21, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v22, v65, v22, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v23, v64, v23, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v24, v68, v24, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v25, v67, v25, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v26, v86, v26, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v27, v83, v27, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v28, v81, v28, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v29, v99, v29, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v30, v98, v30, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v31, v116, v31, 0x5040100
+; GFX11-FAKE16-NEXT:  .LBB44_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v127, off, s32 offset:392
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v126, off, s32 offset:396
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v125, off, s32 offset:400
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v124, off, s32 offset:404
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v123, off, s32 offset:408
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v122, off, s32 offset:412
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v121, off, s32 offset:416
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v120, off, s32 offset:420
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v111, off, s32 offset:424
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v110, off, s32 offset:428
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v109, off, s32 offset:432
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v108, off, s32 offset:436
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v107, off, s32 offset:440
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v106, off, s32 offset:444
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v105, off, s32 offset:448
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v104, off, s32 offset:452
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v95, off, s32 offset:456
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v94, off, s32 offset:460
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v93, off, s32 offset:464
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v92, off, s32 offset:468
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v91, off, s32 offset:472
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v90, off, s32 offset:476
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v89, off, s32 offset:480
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v88, off, s32 offset:484
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v79, off, s32 offset:488
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v78, off, s32 offset:492
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v77, off, s32 offset:496
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v76, off, s32 offset:500
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v75, off, s32 offset:504
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v74, off, s32 offset:508
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v73, off, s32 offset:512
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v72, off, s32 offset:516
+; GFX11-FAKE16-NEXT:    s_clause 0xf
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v63, off, s32 offset:520
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v62, off, s32 offset:524
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v61, off, s32 offset:528
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v60, off, s32 offset:532
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v59, off, s32 offset:536
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v58, off, s32 offset:540
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v57, off, s32 offset:544
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v56, off, s32 offset:548
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v47, off, s32 offset:552
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v46, off, s32 offset:556
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v45, off, s32 offset:560
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v44, off, s32 offset:564
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v43, off, s32 offset:568
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v42, off, s32 offset:572
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v41, off, s32 offset:576
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s32 offset:580
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -75313,1179 +84354,2445 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v64bf16_to_v128i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x15
-; GFX11-NEXT:    scratch_store_b32 off, v40, s32 offset:96
-; GFX11-NEXT:    scratch_store_b32 off, v41, s32 offset:92
-; GFX11-NEXT:    scratch_store_b32 off, v42, s32 offset:88
-; GFX11-NEXT:    scratch_store_b32 off, v43, s32 offset:84
-; GFX11-NEXT:    scratch_store_b32 off, v44, s32 offset:80
-; GFX11-NEXT:    scratch_store_b32 off, v45, s32 offset:76
-; GFX11-NEXT:    scratch_store_b32 off, v46, s32 offset:72
-; GFX11-NEXT:    scratch_store_b32 off, v47, s32 offset:68
-; GFX11-NEXT:    scratch_store_b32 off, v56, s32 offset:64
-; GFX11-NEXT:    scratch_store_b32 off, v57, s32 offset:60
-; GFX11-NEXT:    scratch_store_b32 off, v58, s32 offset:56
-; GFX11-NEXT:    scratch_store_b32 off, v59, s32 offset:52
-; GFX11-NEXT:    scratch_store_b32 off, v60, s32 offset:48
-; GFX11-NEXT:    scratch_store_b32 off, v61, s32 offset:44
-; GFX11-NEXT:    scratch_store_b32 off, v62, s32 offset:40
-; GFX11-NEXT:    scratch_store_b32 off, v63, s32 offset:36
-; GFX11-NEXT:    scratch_store_b32 off, v72, s32 offset:32
-; GFX11-NEXT:    scratch_store_b32 off, v73, s32 offset:28
-; GFX11-NEXT:    scratch_store_b32 off, v74, s32 offset:24
-; GFX11-NEXT:    scratch_store_b32 off, v75, s32 offset:20
-; GFX11-NEXT:    scratch_store_b32 off, v76, s32 offset:16
-; GFX11-NEXT:    scratch_store_b32 off, v77, s32 offset:12
-; GFX11-NEXT:    s_clause 0x2
-; GFX11-NEXT:    scratch_load_b32 v33, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_b32 v32, off, s32 offset:4
-; GFX11-NEXT:    scratch_load_b32 v31, off, s32
-; GFX11-NEXT:    ; implicit-def: $vgpr76
-; GFX11-NEXT:    ; implicit-def: $vgpr75
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr73
-; GFX11-NEXT:    ; implicit-def: $vgpr166
-; GFX11-NEXT:    ; implicit-def: $vgpr63
-; GFX11-NEXT:    ; implicit-def: $vgpr62
-; GFX11-NEXT:    ; implicit-def: $vgpr60
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr58
-; GFX11-NEXT:    ; implicit-def: $vgpr160
-; GFX11-NEXT:    ; implicit-def: $vgpr56
-; GFX11-NEXT:    ; implicit-def: $vgpr45
-; GFX11-NEXT:    ; implicit-def: $vgpr44
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr42
-; GFX11-NEXT:    ; implicit-def: $vgpr147
-; GFX11-NEXT:    ; implicit-def: $vgpr41
-; GFX11-NEXT:    ; implicit-def: $vgpr183
-; GFX11-NEXT:    ; implicit-def: $vgpr181
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr180
-; GFX11-NEXT:    ; implicit-def: $vgpr132
-; GFX11-NEXT:    ; implicit-def: $vgpr179
-; GFX11-NEXT:    ; implicit-def: $vgpr177
-; GFX11-NEXT:    ; implicit-def: $vgpr167
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr165
-; GFX11-NEXT:    ; implicit-def: $vgpr119
-; GFX11-NEXT:    ; implicit-def: $vgpr164
-; GFX11-NEXT:    ; implicit-def: $vgpr162
-; GFX11-NEXT:    ; implicit-def: $vgpr161
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr150
-; GFX11-NEXT:    ; implicit-def: $vgpr118
-; GFX11-NEXT:    ; implicit-def: $vgpr149
-; GFX11-NEXT:    ; implicit-def: $vgpr148
-; GFX11-NEXT:    ; implicit-def: $vgpr145
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr144
-; GFX11-NEXT:    ; implicit-def: $vgpr116
-; GFX11-NEXT:    ; implicit-def: $vgpr135
-; GFX11-NEXT:    ; implicit-def: $vgpr134
-; GFX11-NEXT:    ; implicit-def: $vgpr131
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr130
-; GFX11-NEXT:    ; implicit-def: $vgpr114
-; GFX11-NEXT:    ; implicit-def: $vgpr129
-; GFX11-NEXT:    ; implicit-def: $vgpr74
-; GFX11-NEXT:    ; implicit-def: $vgpr72
-; GFX11-NEXT:    ; implicit-def: $vgpr67
-; GFX11-NEXT:    ; implicit-def: $vgpr61
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr59
-; GFX11-NEXT:    ; implicit-def: $vgpr57
-; GFX11-NEXT:    ; implicit-def: $vgpr47
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr46
-; GFX11-NEXT:    ; implicit-def: $vgpr146
-; GFX11-NEXT:    ; implicit-def: $vgpr43
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr40
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr133
-; GFX11-NEXT:    ; implicit-def: $vgpr182
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr178
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr128
-; GFX11-NEXT:    ; implicit-def: $vgpr176
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr163
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr117
-; GFX11-NEXT:    ; implicit-def: $vgpr151
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr103
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr115
-; GFX11-NEXT:    ; implicit-def: $vgpr102
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr101
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr113
-; GFX11-NEXT:    ; implicit-def: $vgpr100
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr99
-; GFX11-NEXT:    ; implicit-def: $vgpr97
-; GFX11-NEXT:    ; implicit-def: $vgpr112
-; GFX11-NEXT:    ; implicit-def: $vgpr98
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    s_waitcnt vmcnt(2)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v33
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB45_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b64 v[48:49], 24, v[15:16]
-; GFX11-NEXT:    v_lshrrev_b64 v[49:50], 24, v[13:14]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
-; GFX11-NEXT:    v_lshrrev_b64 v[50:51], 24, v[11:12]
-; GFX11-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
-; GFX11-NEXT:    v_lshrrev_b64 v[51:52], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
-; GFX11-NEXT:    v_lshrrev_b64 v[52:53], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
-; GFX11-NEXT:    v_lshrrev_b64 v[53:54], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[66:67], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v129, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v114, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v130, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v131, 16, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v134, 8, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v135, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v116, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v144, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v145, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v148, 8, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v149, 24, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v118, 16, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v150, 8, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v161, 16, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v162, 8, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v164, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v119, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v165, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v167, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v177, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v179, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v132, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v180, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v181, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v183, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v41, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v147, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v42, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v44, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v45, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v56, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v160, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v58, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v60, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v62, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v63, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v166, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v73, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v75, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v76, 8, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v98, 24, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v112, 16, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v97, 8, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v99, 16, v31
-; GFX11-NEXT:    v_lshrrev_b32_e32 v96, 8, v31
-; GFX11-NEXT:    v_lshrrev_b32_e32 v100, 24, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v113, 16, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v87, 8, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v101, 16, v29
-; GFX11-NEXT:    v_lshrrev_b32_e32 v86, 8, v29
-; GFX11-NEXT:    v_lshrrev_b32_e32 v102, 24, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v115, 16, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v85, 8, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v103, 16, v27
-; GFX11-NEXT:    v_lshrrev_b32_e32 v84, 8, v27
-; GFX11-NEXT:    v_lshrrev_b32_e32 v151, 24, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v117, 16, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v83, 8, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v163, 16, v25
-; GFX11-NEXT:    v_lshrrev_b32_e32 v82, 8, v25
-; GFX11-NEXT:    v_lshrrev_b32_e32 v176, 24, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v128, 16, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v81, 8, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v178, 16, v23
-; GFX11-NEXT:    v_lshrrev_b32_e32 v80, 8, v23
-; GFX11-NEXT:    v_lshrrev_b32_e32 v182, 24, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v133, 16, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v71, 8, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v40, 16, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v70, 8, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v43, 24, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v146, 16, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v46, 8, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v47, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v57, 8, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v59, 24, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v69, 16, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v61, 8, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v72, 16, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v74, 8, v17
-; GFX11-NEXT:    v_lshrrev_b64 v[54:55], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
-; GFX11-NEXT:    v_lshrrev_b64 v[64:65], 24, v[19:20]
-; GFX11-NEXT:    v_lshrrev_b64 v[67:68], 24, v[17:18]
-; GFX11-NEXT:  .LBB45_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB45_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v33, 16, v18
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v17
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff0000, v17
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add_f32_e32 v33, 0x40c00000, v33
-; GFX11-NEXT:    v_add_f32_e32 v35, 0x40c00000, v17
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v17, v33, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v33
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-NEXT:    v_add3_u32 v17, v17, v33, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_cndmask_b32 v17, v17, v36 :: v_dual_and_b32 v18, 0xffff0000, v18
-; GFX11-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v37, v18, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v39, 0x400000, v18
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_add3_u32 v37, v37, v18, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_cndmask_b32 v77, v37, v39 :: v_dual_add_f32 v34, 0x40c00000, v34
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v20
-; GFX11-NEXT:    v_perm_b32 v69, v77, v17, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v38, v34, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v18, 0x400000, v34
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v59, 24, v69
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v38, v38, v34, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xffff0000, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v61, 8, v69
-; GFX11-NEXT:    v_dual_cndmask_b32 v33, v38, v18 :: v_dual_add_f32 v20, 0x40c00000, v20
-; GFX11-NEXT:    v_bfe_u32 v48, v35, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v39, 0x400000, v35
-; GFX11-NEXT:    v_add_f32_e32 v18, 0x40c00000, v37
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add3_u32 v36, v48, v35, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v35, v18, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v34, v36, v39, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v36, 16, v19
-; GFX11-NEXT:    v_add3_u32 v35, v35, v18, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff0000, v19
-; GFX11-NEXT:    v_perm_b32 v68, v34, v33, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v34, v20, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v18, v35, v37, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_add_f32 v38, 0x40c00000, v19 :: v_dual_lshlrev_b32 v37, 16, v22
-; GFX11-NEXT:    v_add3_u32 v34, v34, v20, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v19, 0x400000, v20
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-NEXT:    v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-NEXT:    v_bfe_u32 v35, v38, 16, 1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v72, 16, v68
-; GFX11-NEXT:    v_lshrrev_b32_e32 v74, 8, v68
-; GFX11-NEXT:    v_cndmask_b32_e32 v19, v34, v19, vcc_lo
-; GFX11-NEXT:    v_bfe_u32 v39, v36, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v34, 0x400000, v36
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-NEXT:    v_add3_u32 v35, v35, v38, 0x7fff
-; GFX11-NEXT:    v_perm_b32 v65, v19, v18, 0x7060302
-; GFX11-NEXT:    v_add3_u32 v20, v39, v36, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v39, 0x400000, v38
-; GFX11-NEXT:    v_lshrrev_b32_e32 v146, 16, v19
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v43, 24, v65
-; GFX11-NEXT:    v_cndmask_b32_e32 v34, v20, v34, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v20, 0x40c00000, v37
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v38, v38
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xffff0000, v22
-; GFX11-NEXT:    v_lshlrev_b32_e32 v37, 16, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v19, 16, v34
-; GFX11-NEXT:    v_bfe_u32 v36, v20, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v35, v35, v39, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v20
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-NEXT:    v_add_f32_e32 v37, 0x40c00000, v37
-; GFX11-NEXT:    v_add3_u32 v36, v36, v20, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xffff0000, v21
-; GFX11-NEXT:    v_perm_b32 v64, v35, v34, 0x7060302
-; GFX11-NEXT:    v_lshrrev_b32_e32 v46, 8, v65
-; GFX11-NEXT:    v_bfe_u32 v48, v37, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v20, v36, v38, vcc_lo
-; GFX11-NEXT:    v_dual_add_f32 v22, 0x40c00000, v22 :: v_dual_add_f32 v39, 0x40c00000, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v47, 16, v64
-; GFX11-NEXT:    v_lshrrev_b32_e32 v57, 8, v64
-; GFX11-NEXT:    v_lshrrev_b64 v[64:65], 24, v[64:65]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v35, v22, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v22
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-NEXT:    v_lshlrev_b32_e32 v38, 16, v24
-; GFX11-NEXT:    v_bfe_u32 v36, v39, 16, 1
-; GFX11-NEXT:    v_add3_u32 v35, v35, v22, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v22, v48, v37, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v48, 0x400000, v39
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xffff0000, v24
-; GFX11-NEXT:    v_add3_u32 v36, v36, v39, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v21, v35, v21, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v35, 0x400000, v37
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v37, v37
-; GFX11-NEXT:    v_add_f32_e32 v24, 0x40c00000, v24
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v71, v21, v20, 0x7060302
-; GFX11-NEXT:    v_lshrrev_b32_e32 v133, 16, v21
-; GFX11-NEXT:    v_dual_cndmask_b32 v35, v22, v35 :: v_dual_add_f32 v22, 0x40c00000, v38
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v39, v39
-; GFX11-NEXT:    v_lshlrev_b32_e32 v38, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 16, v35
-; GFX11-NEXT:    v_bfe_u32 v37, v22, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v36, v36, v48, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v39, 0x400000, v22
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-NEXT:    v_add_f32_e32 v38, 0x40c00000, v38
-; GFX11-NEXT:    v_add3_u32 v37, v37, v22, 0x7fff
-; GFX11-NEXT:    v_perm_b32 v70, v36, v35, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v48, 0x40c00000, v23
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v49, v38, 16, 1
-; GFX11-NEXT:    v_dual_cndmask_b32 v22, v37, v39 :: v_dual_lshlrev_b32 v39, 16, v26
-; GFX11-NEXT:    v_bfe_u32 v36, v24, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v23, 0x400000, v24
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-NEXT:    v_bfe_u32 v37, v48, 16, 1
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xffff0000, v26
-; GFX11-NEXT:    v_add3_u32 v36, v36, v24, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v24, v49, v38, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v49, 0x400000, v48
-; GFX11-NEXT:    v_add3_u32 v37, v37, v48, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_add_f32 v26, 0x40c00000, v26 :: v_dual_cndmask_b32 v23, v36, v23
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v38
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v38, v38
-; GFX11-NEXT:    v_lshrrev_b32_e32 v40, 16, v70
-; GFX11-NEXT:    v_lshrrev_b32_e32 v128, 16, v23
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v36, v24, v36, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v24, 0x40c00000, v39
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v48, v48
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xffff0000, v25
-; GFX11-NEXT:    v_perm_b32 v81, v23, v22, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v38, v24, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v37, v37, v49, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v39, 0x40c00000, v39
-; GFX11-NEXT:    v_or_b32_e32 v48, 0x400000, v24
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-NEXT:    v_add3_u32 v38, v38, v24, 0x7fff
-; GFX11-NEXT:    v_perm_b32 v80, v37, v36, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v37, v26, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v49, 0x40c00000, v25
-; GFX11-NEXT:    v_or_b32_e32 v25, 0x400000, v26
-; GFX11-NEXT:    v_bfe_u32 v50, v39, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v24, v38, v48, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v37, v37, v26, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-NEXT:    v_bfe_u32 v38, v49, 16, 1
-; GFX11-NEXT:    v_add3_u32 v26, v50, v39, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v48, 16, v28
-; GFX11-NEXT:    v_or_b32_e32 v50, 0x400000, v49
-; GFX11-NEXT:    v_cndmask_b32_e32 v25, v37, v25, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v39
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v39, v39
-; GFX11-NEXT:    v_add3_u32 v38, v38, v49, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xffff0000, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 16, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v178, 16, v80
-; GFX11-NEXT:    v_dual_cndmask_b32 v37, v26, v37 :: v_dual_add_f32 v26, 0x40c00000, v48
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v49, v49
-; GFX11-NEXT:    v_add_f32_e32 v28, 0x40c00000, v28
-; GFX11-NEXT:    v_lshlrev_b32_e32 v48, 16, v27
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xffff0000, v27
-; GFX11-NEXT:    v_bfe_u32 v39, v26, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v38, v38, v50, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v49, 0x400000, v26
-; GFX11-NEXT:    v_add_f32_e32 v48, 0x40c00000, v48
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-NEXT:    v_add3_u32 v39, v39, v26, 0x7fff
-; GFX11-NEXT:    v_perm_b32 v82, v38, v37, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v38, v28, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v50, 0x40c00000, v27
-; GFX11-NEXT:    v_or_b32_e32 v27, 0x400000, v28
-; GFX11-NEXT:    v_bfe_u32 v51, v48, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v26, v39, v49, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v38, v38, v28, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11-NEXT:    v_bfe_u32 v39, v50, 16, 1
-; GFX11-NEXT:    v_add3_u32 v28, v51, v48, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v49, 16, v30
-; GFX11-NEXT:    v_or_b32_e32 v51, 0x400000, v50
-; GFX11-NEXT:    v_cndmask_b32_e32 v27, v38, v27, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v48
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v48, v48
-; GFX11-NEXT:    v_add3_u32 v39, v39, v50, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xffff0000, v30
-; GFX11-NEXT:    v_perm_b32 v83, v25, v24, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v38, v28, v38, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v28, 0x40c00000, v49
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v50, v50
-; GFX11-NEXT:    v_dual_add_f32 v30, 0x40c00000, v30 :: v_dual_lshlrev_b32 v49, 16, v29
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xffff0000, v29
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v48, v28, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v39, v39, v51, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v50, 0x400000, v28
-; GFX11-NEXT:    v_add_f32_e32 v49, 0x40c00000, v49
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11-NEXT:    v_add3_u32 v48, v48, v28, 0x7fff
-; GFX11-NEXT:    v_perm_b32 v84, v39, v38, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v39, v30, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v51, 0x40c00000, v29
-; GFX11-NEXT:    v_or_b32_e32 v29, 0x400000, v30
-; GFX11-NEXT:    v_bfe_u32 v52, v49, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v28, v48, v50, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v39, v39, v30, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-NEXT:    v_bfe_u32 v48, v51, 16, 1
-; GFX11-NEXT:    v_add3_u32 v30, v52, v49, 0x7fff
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v50, 16, v32
-; GFX11-NEXT:    v_or_b32_e32 v52, 0x400000, v51
-; GFX11-NEXT:    v_cndmask_b32_e32 v29, v39, v29, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v39, 0x400000, v49
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v49, v49
-; GFX11-NEXT:    v_add3_u32 v48, v48, v51, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v32, 0xffff0000, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v151, 24, v83
-; GFX11-NEXT:    v_dual_cndmask_b32 v39, v30, v39 :: v_dual_add_f32 v30, 0x40c00000, v50
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v51, v51
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v32, 0x40c00000, v32
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v50, 16, v31
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xffff0000, v31
-; GFX11-NEXT:    v_bfe_u32 v49, v30, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v48, v48, v52, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v51, 0x400000, v30
-; GFX11-NEXT:    v_add_f32_e32 v50, 0x40c00000, v50
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-NEXT:    v_add3_u32 v49, v49, v30, 0x7fff
-; GFX11-NEXT:    v_perm_b32 v86, v48, v39, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v48, v32, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v52, 0x40c00000, v31
-; GFX11-NEXT:    v_or_b32_e32 v31, 0x400000, v32
-; GFX11-NEXT:    v_bfe_u32 v53, v50, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v30, v49, v51, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v48, v48, v32, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-NEXT:    v_bfe_u32 v49, v52, 16, 1
-; GFX11-NEXT:    v_add3_u32 v32, v53, v50, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v51, 16, v2
-; GFX11-NEXT:    v_or_b32_e32 v53, 0x400000, v52
-; GFX11-NEXT:    v_cndmask_b32_e32 v31, v48, v31, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v48, 0x400000, v50
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v50, v50
-; GFX11-NEXT:    v_add3_u32 v49, v49, v52, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT:    v_perm_b32 v85, v27, v26, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v48, v32, v48, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v32, 0x40c00000, v51
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v51, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v50, v32, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v49, v49, v53, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v52, 0x400000, v32
-; GFX11-NEXT:    v_add_f32_e32 v51, 0x40c00000, v51
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-NEXT:    v_add3_u32 v50, v50, v32, 0x7fff
-; GFX11-NEXT:    v_perm_b32 v96, v49, v48, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v49, v2, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v53, 0x40c00000, v1
-; GFX11-NEXT:    v_or_b32_e32 v54, 0x400000, v2
-; GFX11-NEXT:    v_bfe_u32 v55, v51, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v50, v52, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v49, v49, v2, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_bfe_u32 v32, v53, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v50, 0x400000, v51
-; GFX11-NEXT:    v_perm_b32 v87, v29, v28, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v49, v54, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v49, v55, v51, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v54, 16, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v51, v51
-; GFX11-NEXT:    v_add3_u32 v52, v32, v53, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v55, 0x400000, v53
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v49, v50, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v49, 0x40c00000, v54
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v53, v53
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-NEXT:    v_bfe_u32 v51, v49, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v50, v52, v55, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v52, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT:    v_or_b32_e32 v53, 0x400000, v49
-; GFX11-NEXT:    v_add3_u32 v51, v51, v49, 0x7fff
-; GFX11-NEXT:    v_perm_b32 v98, v50, v32, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v50, v4, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v52, 0x40c00000, v52
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v49, v49
-; GFX11-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-NEXT:    v_or_b32_e32 v54, 0x400000, v4
-; GFX11-NEXT:    v_add3_u32 v50, v50, v4, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v55, v52, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v49, v51, v53, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    v_bfe_u32 v51, v3, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v53, 0x400000, v52
-; GFX11-NEXT:    v_lshrrev_b32_e32 v75, 16, v98
-; GFX11-NEXT:    v_lshrrev_b32_e32 v76, 8, v98
-; GFX11-NEXT:    v_cndmask_b32_e32 v4, v50, v54, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v50, v55, v52, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v54, 16, v6
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11-NEXT:    v_add3_u32 v51, v51, v3, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v55, 0x400000, v3
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT:    v_add_f32_e32 v52, 0x40c00000, v54
-; GFX11-NEXT:    v_cndmask_b32_e32 v50, v50, v53, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v53, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT:    v_or_b32_e32 v54, 0x400000, v52
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v51, v55, vcc_lo
-; GFX11-NEXT:    v_bfe_u32 v51, v52, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v53, 0x40c00000, v53
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-NEXT:    v_perm_b32 v100, v3, v50, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v3, v6, 16, 1
-; GFX11-NEXT:    v_add3_u32 v51, v51, v52, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v55, 0x400000, v6
-; GFX11-NEXT:    v_bfe_u32 v66, v53, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v52, v5, 16, 1
-; GFX11-NEXT:    v_add3_u32 v3, v3, v6, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v51, v51, v54, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    v_add3_u32 v6, v66, v53, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v54, 0x400000, v53
-; GFX11-NEXT:    v_add3_u32 v52, v52, v5, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v66, 0x400000, v5
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v3, v55, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v55, 16, v8
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v53, v53
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-NEXT:    v_perm_b32 v97, v31, v30, 0x7060302
-; GFX11-NEXT:    v_perm_b32 v103, v3, v51, 0x7060302
-; GFX11-NEXT:    v_lshrrev_b32_e32 v147, 16, v3
-; GFX11-NEXT:    v_dual_cndmask_b32 v53, v6, v54 :: v_dual_add_f32 v6, 0x40c00000, v55
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    v_add_f32_e32 v8, 0x40c00000, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v54, 16, v7
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-NEXT:    v_or_b32_e32 v55, 0x400000, v6
-; GFX11-NEXT:    v_cndmask_b32_e32 v5, v52, v66, vcc_lo
-; GFX11-NEXT:    v_bfe_u32 v52, v6, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v54, 0x40c00000, v54
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-NEXT:    v_perm_b32 v102, v5, v53, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v5, v8, 16, 1
-; GFX11-NEXT:    v_add3_u32 v52, v52, v6, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v66, 0x400000, v8
-; GFX11-NEXT:    v_bfe_u32 v67, v54, 16, 1
-; GFX11-NEXT:    v_perm_b32 v99, v2, v1, 0x7060302
-; GFX11-NEXT:    v_add3_u32 v5, v5, v8, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v6, v52, v55, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-NEXT:    v_bfe_u32 v52, v7, 16, 1
-; GFX11-NEXT:    v_add3_u32 v8, v67, v54, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v55, 0x400000, v54
-; GFX11-NEXT:    v_or_b32_e32 v67, 0x400000, v7
-; GFX11-NEXT:    v_cndmask_b32_e32 v5, v5, v66, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v66, 16, v10
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v54, v54
-; GFX11-NEXT:    v_add3_u32 v52, v52, v7, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v166, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-NEXT:    v_cndmask_b32_e32 v54, v8, v55, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v8, 0x40c00000, v66
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v55, 16, v9
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v66, 0x400000, v8
-; GFX11-NEXT:    v_cndmask_b32_e32 v7, v52, v67, vcc_lo
-; GFX11-NEXT:    v_bfe_u32 v52, v8, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v55, 0x40c00000, v55
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-NEXT:    v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-NEXT:    v_perm_b32 v182, v7, v54, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v7, v10, 16, 1
-; GFX11-NEXT:    v_add3_u32 v52, v52, v8, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v67, 0x400000, v10
-; GFX11-NEXT:    v_bfe_u32 v112, v55, 16, 1
-; GFX11-NEXT:    v_perm_b32 v183, v5, v6, 0x7060302
-; GFX11-NEXT:    v_add3_u32 v7, v7, v10, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v8, v52, v66, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    v_bfe_u32 v52, v9, 16, 1
-; GFX11-NEXT:    v_add3_u32 v10, v112, v55, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v66, 0x400000, v55
-; GFX11-NEXT:    v_or_b32_e32 v112, 0x400000, v9
-; GFX11-NEXT:    v_cndmask_b32_e32 v7, v7, v67, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v67, 16, v12
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v55, v55
-; GFX11-NEXT:    v_add3_u32 v52, v52, v9, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-NEXT:    v_perm_b32 v101, v4, v49, 0x7060302
-; GFX11-NEXT:    v_lshrrev_b32_e32 v160, 16, v4
-; GFX11-NEXT:    v_dual_cndmask_b32 v55, v10, v66 :: v_dual_add_f32 v10, 0x40c00000, v67
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v4, 16, v49
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v50
-; GFX11-NEXT:    v_bfe_u32 v66, v10, 16, 1
-; GFX11-NEXT:    v_dual_cndmask_b32 v9, v52, v112 :: v_dual_lshlrev_b32 v52, 16, v11
-; GFX11-NEXT:    v_bfe_u32 v67, v12, 16, 1
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v176, v9, v55, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v9, 0x40c00000, v52
-; GFX11-NEXT:    v_add3_u32 v52, v66, v10, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v66, 0x400000, v10
-; GFX11-NEXT:    v_add3_u32 v67, v67, v12, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v112, 0x400000, v12
-; GFX11-NEXT:    v_bfe_u32 v113, v9, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_add_f32 v11, 0x40c00000, v11 :: v_dual_cndmask_b32 v10, v52, v66
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-NEXT:    v_or_b32_e32 v66, 0x400000, v9
-; GFX11-NEXT:    v_add3_u32 v52, v113, v9, 0x7fff
-; GFX11-NEXT:    v_perm_b32 v177, v7, v8, 0x7060302
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v32
-; GFX11-NEXT:    v_dual_cndmask_b32 v12, v67, v112 :: v_dual_lshlrev_b32 v67, 16, v14
-; GFX11-NEXT:    v_bfe_u32 v112, v11, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 16, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 16, v26
-; GFX11-NEXT:    v_dual_cndmask_b32 v9, v52, v66 :: v_dual_add_f32 v52, 0x40c00000, v67
-; GFX11-NEXT:    v_add3_u32 v66, v112, v11, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v67, 0x400000, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v112, 16, v13
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-NEXT:    v_bfe_u32 v113, v52, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 16, v24
-; GFX11-NEXT:    v_dual_cndmask_b32 v11, v66, v67 :: v_dual_add_f32 v66, 0x40c00000, v112
-; GFX11-NEXT:    v_add3_u32 v67, v113, v52, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v112, 0x400000, v52
-; GFX11-NEXT:    v_bfe_u32 v113, v14, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11-NEXT:    v_bfe_u32 v114, v66, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-NEXT:    v_or_b32_e32 v115, 0x400000, v66
-; GFX11-NEXT:    v_perm_b32 v162, v11, v9, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v52, v67, v112, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v67, v113, v14, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v112, 0x400000, v14
-; GFX11-NEXT:    v_add3_u32 v113, v114, v66, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v114, 16, v16
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-NEXT:    v_bfe_u32 v116, v13, 16, 1
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff0000, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v24, 16, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 16, v20
-; GFX11-NEXT:    v_dual_cndmask_b32 v14, v67, v112 :: v_dual_add_f32 v67, 0x40c00000, v114
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v66, v66
-; GFX11-NEXT:    v_add3_u32 v112, v116, v13, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v16, 0x40c00000, v16
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v149, v14, v52, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v114, v67, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v66, v113, v115, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v113, 0x400000, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v115, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-NEXT:    v_perm_b32 v163, v12, v10, 0x7060302
-; GFX11-NEXT:    v_lshrrev_b32_e32 v20, 16, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v17
-; GFX11-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-NEXT:    v_dual_cndmask_b32 v13, v112, v113 :: v_dual_add_f32 v112, 0x40c00000, v115
-; GFX11-NEXT:    v_add3_u32 v113, v114, v67, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v114, 0x400000, v67
-; GFX11-NEXT:    v_bfe_u32 v115, v16, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v67, v67
-; GFX11-NEXT:    v_bfe_u32 v116, v112, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v117, 0x400000, v112
-; GFX11-NEXT:    v_or_b32_e32 v118, 0x400000, v15
-; GFX11-NEXT:    v_perm_b32 v148, v13, v66, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v67, v113, v114, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v114, v115, v16, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v115, 0x400000, v16
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-NEXT:    v_bfe_u32 v113, v15, 16, 1
-; GFX11-NEXT:    v_add3_u32 v116, v116, v112, 0x7fff
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 16, v33
-; GFX11-NEXT:    v_lshrrev_b64 v[33:34], 24, v[96:97]
-; GFX11-NEXT:    v_cndmask_b32_e32 v16, v114, v115, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v112, v112
-; GFX11-NEXT:    v_add3_u32 v113, v113, v15, 0x7fff
-; GFX11-NEXT:    v_lshrrev_b64 v[34:35], 24, v[86:87]
-; GFX11-NEXT:    v_lshrrev_b64 v[35:36], 24, v[84:85]
-; GFX11-NEXT:    v_perm_b32 v135, v16, v67, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v112, v116, v117, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v116, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v52
-; GFX11-NEXT:    v_lshrrev_b32_e32 v132, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 16, v53
-; GFX11-NEXT:    v_cndmask_b32_e32 v15, v113, v118, vcc_lo
-; GFX11-NEXT:    v_lshrrev_b32_e32 v118, 16, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v12, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v8, 16, v6
-; GFX11-NEXT:    v_perm_b32 v134, v15, v112, 0x7060302
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 16, v112
-; GFX11-NEXT:    v_lshrrev_b32_e32 v112, 16, v31
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 16, v48
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v51
-; GFX11-NEXT:    v_lshrrev_b64 v[48:49], 24, v[134:135]
-; GFX11-NEXT:    v_lshrrev_b64 v[49:50], 24, v[148:149]
-; GFX11-NEXT:    v_lshrrev_b64 v[50:51], 24, v[162:163]
-; GFX11-NEXT:    v_lshrrev_b64 v[51:52], 24, v[176:177]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v117, 16, v25
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 16, v37
-; GFX11-NEXT:    v_lshrrev_b64 v[52:53], 24, v[182:183]
-; GFX11-NEXT:    v_lshrrev_b64 v[36:37], 24, v[82:83]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v114, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v16, 16, v67
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 16, v66
-; GFX11-NEXT:    v_lshrrev_b32_e32 v119, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 16, v54
-; GFX11-NEXT:    v_lshrrev_b32_e32 v115, 16, v27
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 16, v38
-; GFX11-NEXT:    v_lshrrev_b64 v[53:54], 24, v[102:103]
-; GFX11-NEXT:    v_lshrrev_b64 v[66:67], 24, v[98:99]
-; GFX11-NEXT:    v_lshrrev_b64 v[37:38], 24, v[80:81]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v11, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 16, v55
-; GFX11-NEXT:    v_lshrrev_b32_e32 v113, 16, v29
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 16, v39
-; GFX11-NEXT:    v_lshrrev_b64 v[54:55], 24, v[100:101]
-; GFX11-NEXT:    v_lshrrev_b64 v[38:39], 24, v[70:71]
-; GFX11-NEXT:    v_lshrrev_b64 v[67:68], 24, v[68:69]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v129, 24, v135
-; GFX11-NEXT:    v_lshrrev_b32_e32 v130, 8, v135
-; GFX11-NEXT:    v_lshrrev_b32_e32 v131, 16, v134
-; GFX11-NEXT:    v_lshrrev_b32_e32 v134, 8, v134
-; GFX11-NEXT:    v_lshrrev_b32_e32 v135, 24, v149
-; GFX11-NEXT:    v_lshrrev_b32_e32 v144, 8, v149
-; GFX11-NEXT:    v_lshrrev_b32_e32 v145, 16, v148
-; GFX11-NEXT:    v_lshrrev_b32_e32 v148, 8, v148
-; GFX11-NEXT:    v_lshrrev_b32_e32 v149, 24, v163
-; GFX11-NEXT:    v_lshrrev_b32_e32 v150, 8, v163
-; GFX11-NEXT:    v_lshrrev_b32_e32 v161, 16, v162
-; GFX11-NEXT:    v_lshrrev_b32_e32 v162, 8, v162
-; GFX11-NEXT:    v_lshrrev_b32_e32 v164, 24, v177
-; GFX11-NEXT:    v_lshrrev_b32_e32 v165, 8, v177
-; GFX11-NEXT:    v_lshrrev_b32_e32 v167, 16, v176
-; GFX11-NEXT:    v_lshrrev_b32_e32 v177, 8, v176
-; GFX11-NEXT:    v_lshrrev_b32_e32 v179, 24, v183
-; GFX11-NEXT:    v_lshrrev_b32_e32 v180, 8, v183
-; GFX11-NEXT:    v_lshrrev_b32_e32 v181, 16, v182
-; GFX11-NEXT:    v_lshrrev_b32_e32 v183, 8, v182
-; GFX11-NEXT:    v_lshrrev_b32_e32 v41, 24, v103
-; GFX11-NEXT:    v_lshrrev_b32_e32 v42, 8, v103
-; GFX11-NEXT:    v_lshrrev_b32_e32 v44, 16, v102
-; GFX11-NEXT:    v_lshrrev_b32_e32 v45, 8, v102
-; GFX11-NEXT:    v_lshrrev_b32_e32 v56, 24, v101
-; GFX11-NEXT:    v_lshrrev_b32_e32 v58, 8, v101
-; GFX11-NEXT:    v_lshrrev_b32_e32 v60, 16, v100
-; GFX11-NEXT:    v_lshrrev_b32_e32 v62, 8, v100
-; GFX11-NEXT:    v_lshrrev_b32_e32 v63, 24, v99
-; GFX11-NEXT:    v_lshrrev_b32_e32 v73, 8, v99
-; GFX11-NEXT:    v_lshrrev_b32_e32 v98, 24, v97
-; GFX11-NEXT:    v_lshrrev_b32_e32 v97, 8, v97
-; GFX11-NEXT:    v_lshrrev_b32_e32 v99, 16, v96
-; GFX11-NEXT:    v_lshrrev_b32_e32 v96, 8, v96
-; GFX11-NEXT:    v_lshrrev_b32_e32 v100, 24, v87
-; GFX11-NEXT:    v_lshrrev_b32_e32 v87, 8, v87
-; GFX11-NEXT:    v_lshrrev_b32_e32 v101, 16, v86
-; GFX11-NEXT:    v_lshrrev_b32_e32 v86, 8, v86
-; GFX11-NEXT:    v_lshrrev_b32_e32 v102, 24, v85
-; GFX11-NEXT:    v_lshrrev_b32_e32 v85, 8, v85
-; GFX11-NEXT:    v_lshrrev_b32_e32 v103, 16, v84
-; GFX11-NEXT:    v_lshrrev_b32_e32 v84, 8, v84
-; GFX11-NEXT:    v_lshrrev_b32_e32 v83, 8, v83
-; GFX11-NEXT:    v_lshrrev_b32_e32 v163, 16, v82
-; GFX11-NEXT:    v_lshrrev_b32_e32 v82, 8, v82
-; GFX11-NEXT:    v_lshrrev_b32_e32 v176, 24, v81
-; GFX11-NEXT:    v_lshrrev_b32_e32 v81, 8, v81
-; GFX11-NEXT:    v_lshrrev_b32_e32 v80, 8, v80
-; GFX11-NEXT:    v_lshrrev_b32_e32 v182, 24, v71
-; GFX11-NEXT:    v_lshrrev_b32_e32 v71, 8, v71
-; GFX11-NEXT:    v_lshrrev_b32_e32 v70, 8, v70
-; GFX11-NEXT:    v_lshrrev_b32_e32 v69, 16, v77
-; GFX11-NEXT:  .LBB45_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v76
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v66
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v63
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v54
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v55
-; GFX11-NEXT:    v_and_b32_e32 v55, 0xff, v75
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v66, 0xff, v60
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_or_b32_e32 v39, v55, v39
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v73
-; GFX11-NEXT:    v_or_b32_e32 v54, v66, v54
-; GFX11-NEXT:    v_lshlrev_b16 v66, 8, v56
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v39
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v55
-; GFX11-NEXT:    v_and_b32_e32 v55, 0xff, v166
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v53
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v39
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_or_b32_e32 v55, v55, v65
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v62
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_lshlrev_b16 v52, 8, v52
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v65
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v58
-; GFX11-NEXT:    v_and_b32_e32 v65, 0xff, v160
-; GFX11-NEXT:    v_lshlrev_b16 v51, 8, v51
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v39
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v54
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v55
-; GFX11-NEXT:    v_or_b32_e32 v54, v65, v66
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v45
-; GFX11-NEXT:    v_and_b32_e32 v65, 0xff, v44
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v39
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v54
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v55
-; GFX11-NEXT:    v_or_b32_e32 v53, v65, v53
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v42
-; GFX11-NEXT:    v_and_b32_e32 v55, 0xff, v147
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v41
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v39
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v53
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v54
-; GFX11-NEXT:    v_or_b32_e32 v53, v55, v65
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v183
-; GFX11-NEXT:    v_and_b32_e32 v55, 0xff, v181
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v39
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v53
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v54
-; GFX11-NEXT:    v_or_b32_e32 v52, v55, v52
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v180
-; GFX11-NEXT:    v_and_b32_e32 v54, 0xff, v132
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v179
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v39
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v52
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v53
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_or_b32_e32 v52, v54, v55
-; GFX11-NEXT:    v_and_b32_e32 v54, 0xff, v167
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v177
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v165
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v52, 16, v52
-; GFX11-NEXT:    v_or_b32_e32 v51, v54, v51
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v53
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v55
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v39
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v52
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v51
-; GFX11-NEXT:    v_and_b32_e32 v51, 0xff, v119
-; GFX11-NEXT:    v_lshlrev_b16 v52, 8, v164
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v162
-; GFX11-NEXT:    v_and_b32_e32 v54, 0xff, v161
-; GFX11-NEXT:    v_lshlrev_b16 v50, 8, v50
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v150
-; GFX11-NEXT:    v_and_b32_e32 v65, 0xff, v118
-; GFX11-NEXT:    v_lshlrev_b16 v66, 8, v149
-; GFX11-NEXT:    v_or_b32_e32 v51, v51, v52
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v53
-; GFX11-NEXT:    v_or_b32_e32 v50, v54, v50
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v55
-; GFX11-NEXT:    v_or_b32_e32 v52, v65, v66
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v51, 16, v51
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v50, 16, v50
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v52, 16, v52
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off
-; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
-; GFX11-NEXT:    v_or_b32_e32 v1, v9, v39
-; GFX11-NEXT:    v_or_b32_e32 v2, v10, v51
-; GFX11-NEXT:    v_or_b32_e32 v3, v11, v50
-; GFX11-NEXT:    v_or_b32_e32 v4, v12, v52
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v13
-; GFX11-NEXT:    v_lshlrev_b16 v6, 8, v148
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v145
-; GFX11-NEXT:    v_lshlrev_b16 v8, 8, v49
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v14
-; GFX11-NEXT:    v_lshlrev_b16 v10, 8, v144
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v116
-; GFX11-NEXT:    v_lshlrev_b16 v12, 8, v135
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v15
-; GFX11-NEXT:    v_lshlrev_b16 v14, 8, v134
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v8, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v9, v13, v14
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v131
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v48
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v16
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v130
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v114
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v129
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v17
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v74
-; GFX11-NEXT:    v_and_b32_e32 v39, 0xff, v72
-; GFX11-NEXT:    v_lshlrev_b16 v48, 8, v67
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v11, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v12, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v13, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v14, v39, v48
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v8, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v9, v13, v14
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v18
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v61
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v69
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v59
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v19
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v57
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v47
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v64
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v20
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v46
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v11, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v12, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v13, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v14, v18, v19
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v146
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v43
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v21
-; GFX11-NEXT:    v_lshlrev_b16 v18, 8, v70
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v40
-; GFX11-NEXT:    v_lshlrev_b16 v20, 8, v38
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v22
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v71
-; GFX11-NEXT:    v_and_b32_e32 v38, 0xff, v133
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v182
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v16
-; GFX11-NEXT:    v_or_b32_e32 v16, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v17, v19, v20
-; GFX11-NEXT:    v_or_b32_e32 v18, v21, v22
-; GFX11-NEXT:    v_or_b32_e32 v19, v38, v39
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xffff, v18
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v11, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v12, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v13, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v14, v18, v19
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v23
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v80
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v178
-; GFX11-NEXT:    v_lshlrev_b16 v18, 8, v37
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v24
-; GFX11-NEXT:    v_lshlrev_b16 v20, 8, v81
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v128
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v176
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v25
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v82
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v16
-; GFX11-NEXT:    v_or_b32_e32 v16, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v17, v19, v20
-; GFX11-NEXT:    v_or_b32_e32 v18, v21, v22
-; GFX11-NEXT:    v_or_b32_e32 v19, v23, v24
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v163
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v36
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v26
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v83
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v117
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v151
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v27
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v84
-; GFX11-NEXT:    v_and_b32_e32 v36, 0xff, v103
-; GFX11-NEXT:    v_lshlrev_b16 v35, 8, v35
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v21, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v22, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v23, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v24, v36, v35
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff, v19
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xffff, v21
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xffff, v23
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v16
-; GFX11-NEXT:    v_or_b32_e32 v16, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v17, v19, v20
-; GFX11-NEXT:    v_or_b32_e32 v18, v21, v22
-; GFX11-NEXT:    v_or_b32_e32 v19, v23, v24
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v28
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v85
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v115
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v102
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v29
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v86
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v101
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v34
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v30
-; GFX11-NEXT:    v_lshlrev_b16 v29, 8, v87
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v21, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v22, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v23, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v24, v28, v29
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v113
-; GFX11-NEXT:    v_lshlrev_b16 v26, 8, v100
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v31
-; GFX11-NEXT:    v_lshlrev_b16 v28, 8, v96
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v99
-; GFX11-NEXT:    v_lshlrev_b16 v30, 8, v33
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v32
-; GFX11-NEXT:    v_lshlrev_b16 v32, 8, v97
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xff, v112
-; GFX11-NEXT:    v_lshlrev_b16 v34, 8, v98
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v26
-; GFX11-NEXT:    v_or_b32_e32 v26, v27, v28
-; GFX11-NEXT:    v_or_b32_e32 v27, v29, v30
-; GFX11-NEXT:    v_or_b32_e32 v28, v31, v32
-; GFX11-NEXT:    v_or_b32_e32 v29, v33, v34
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xffff, v20
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xffff, v22
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xffff, v24
-; GFX11-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xffff, v26
-; GFX11-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xffff, v28
-; GFX11-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v21, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v22, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v23, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v24, v28, v29
-; GFX11-NEXT:    s_clause 0x5
-; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off offset:32
-; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:48
-; GFX11-NEXT:    scratch_store_b128 v0, v[9:12], off offset:64
-; GFX11-NEXT:    scratch_store_b128 v0, v[13:16], off offset:80
-; GFX11-NEXT:    scratch_store_b128 v0, v[17:20], off offset:96
-; GFX11-NEXT:    scratch_store_b128 v0, v[21:24], off offset:112
-; GFX11-NEXT:    s_clause 0x15
-; GFX11-NEXT:    scratch_load_b32 v77, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_b32 v76, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_b32 v75, off, s32 offset:20
-; GFX11-NEXT:    scratch_load_b32 v74, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_b32 v73, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_b32 v72, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_b32 v63, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_b32 v62, off, s32 offset:40
-; GFX11-NEXT:    scratch_load_b32 v61, off, s32 offset:44
-; GFX11-NEXT:    scratch_load_b32 v60, off, s32 offset:48
-; GFX11-NEXT:    scratch_load_b32 v59, off, s32 offset:52
-; GFX11-NEXT:    scratch_load_b32 v58, off, s32 offset:56
-; GFX11-NEXT:    scratch_load_b32 v57, off, s32 offset:60
-; GFX11-NEXT:    scratch_load_b32 v56, off, s32 offset:64
-; GFX11-NEXT:    scratch_load_b32 v47, off, s32 offset:68
-; GFX11-NEXT:    scratch_load_b32 v46, off, s32 offset:72
-; GFX11-NEXT:    scratch_load_b32 v45, off, s32 offset:76
-; GFX11-NEXT:    scratch_load_b32 v44, off, s32 offset:80
-; GFX11-NEXT:    scratch_load_b32 v43, off, s32 offset:84
-; GFX11-NEXT:    scratch_load_b32 v42, off, s32 offset:88
-; GFX11-NEXT:    scratch_load_b32 v41, off, s32 offset:92
-; GFX11-NEXT:    scratch_load_b32 v40, off, s32 offset:96
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v64bf16_to_v128i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v40, s32 offset:156
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v41, s32 offset:152
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v42, s32 offset:148
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v43, s32 offset:144
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v44, s32 offset:140
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v45, s32 offset:136
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v46, s32 offset:132
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v47, s32 offset:128
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v56, s32 offset:124
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v57, s32 offset:120
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v58, s32 offset:116
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v59, s32 offset:112
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v60, s32 offset:108
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v61, s32 offset:104
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v62, s32 offset:100
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v63, s32 offset:96
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v72, s32 offset:92
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v73, s32 offset:88
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v74, s32 offset:84
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v75, s32 offset:80
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v76, s32 offset:76
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v77, s32 offset:72
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v78, s32 offset:68
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v79, s32 offset:64
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v88, s32 offset:60
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v89, s32 offset:56
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v90, s32 offset:52
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v91, s32 offset:48
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v92, s32 offset:44
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v93, s32 offset:40
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v94, s32 offset:36
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v95, s32 offset:32
+; GFX11-TRUE16-NEXT:    s_clause 0x4
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v104, s32 offset:28
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v105, s32 offset:24
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v106, s32 offset:20
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v107, s32 offset:16
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v108, s32 offset:12
+; GFX11-TRUE16-NEXT:    s_clause 0x2
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v33, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr144_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr108_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr68_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr131_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr107_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr132_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr106_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr162_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr105_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr67_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr147_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr95_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr93_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr180_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr90_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr164_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr88_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr165_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr78_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr46_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr75_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr178_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr63_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr179_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr62_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr74_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr57_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr45_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr56_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr42_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr43_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr89_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr40_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr59_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr182_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr60_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr181_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr94_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr167_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr77_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr163_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr76_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr160_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr104_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr151_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr91_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr92_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr79_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr73_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr72_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr61_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr58_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr47_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr44_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr41_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr183_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr177_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr176_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr166_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr161_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr150_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr148_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr112_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr145_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr134_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr133_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr130_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr128_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr116_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr119_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr114_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr118_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr117_lo16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v33
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB45_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[64:65], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[65:66], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[48:49], 24, v[15:16]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[66:67], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[49:50], 24, v[13:14]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[67:68], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v135, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v146, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v151, 8, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v160, 24, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v163, 8, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v167, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v181, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v182, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v40, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v43, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v56, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v57, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v62, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v63, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v75, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v78, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v88, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v90, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v93, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v95, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v105, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v106, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v107, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v108, 8, v1
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v117, 24, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v118, 8, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v119, 8, v31
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v128, 24, v30
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v129, 8, v30
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v130, 8, v29
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v133, 24, v28
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v134, 8, v28
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v145, 8, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v148, 24, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v150, 8, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v161, 8, v25
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v166, 24, v24
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v176, 8, v24
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v177, 8, v23
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v183, 24, v22
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v41, 8, v22
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v44, 8, v21
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v47, 24, v20
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v58, 8, v20
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v61, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v72, 24, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v73, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v79, 8, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[68:69], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[50:51], 24, v[19:20]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[53:54], 24, v[17:18]
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v144.h, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v131.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v132.h, v2.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v162.h, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v147.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v149.h, v4.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v180.h, v5.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v164.h, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v165.h, v6.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v46.h, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v178.h, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v179.h, v8.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v74.h, v9.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v45.h, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v42.h, v10.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v89.h, v11.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v59.h, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v60.h, v12.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v94.h, v13.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v77.h, v14.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v76.h, v14.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v104.h, v15.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v91.h, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v92.h, v16.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v80.h, v17.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.h, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v70.h, v18.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v83.h, v19.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v81.h, v20.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v71.h, v20.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v85.h, v21.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v82.h, v22.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v84.h, v22.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v96.h, v23.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v86.h, v24.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v87.h, v24.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v101.h, v25.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v97.h, v26.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v98.h, v26.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v112.h, v27.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v99.h, v28.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v100.h, v28.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v113.h, v29.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v103.h, v30.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v102.h, v30.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v116.h, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v114.h, v32.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v115.h, v32.h
+; GFX11-TRUE16-NEXT:  .LBB45_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB45_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v17
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v17, 0x40c00000, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v51, 0x400000, v17
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v33, 0xffff0000, v18
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_lshlrev_b32 v18, 16, v18
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v33, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v18, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v18
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v33
+; GFX11-TRUE16-NEXT:    v_add3_u32 v36, v36, v33, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v37, v37, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v55, v37, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v35, 0xffff0000, v20
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v50, v17, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v33.l, v55.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v70, v36, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v35, 0x40c00000, v35
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v37, v50, v17, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v48, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v49, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v80, v37, v51, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_add3_u32 v18, v48, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v20
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v34.l, v80.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v17, v18, v49, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v18, 0xffff, v33, v70
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v20, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v17, 0xffff, v34, v17
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v20, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v72, 24, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v73, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v79, 8, v17
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v81, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_lshlrev_b32 v19, 16, v19
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v35, 0xffff0000, v22
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_lshlrev_b32 v22, 16, v22
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v71, v34, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v34.l, v81.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v19
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_add3_u32 v20, v20, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v22, 0x40c00000, v22 :: v_dual_cndmask_b32 v83, v33, v37
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v22, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v37.l, v83.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v36, v20, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v20, v33, v22, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v33, 0x400000, v22
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v21
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v82, v20, v33 :: v_dual_add_f32 v35, 0x40c00000, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v20, 0xffff, v34, v71
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.l, v82.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v35, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v47, 24, v20
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v58, 8, v20
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v19, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v33, 0x40c00000, v38 :: v_dual_cndmask_b32 v84, v19, v39
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v19, 0xffff, v37, v36
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v24
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v21, 0x40c00000, v21
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v33, 16, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v33
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v36
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v34, v21, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v21
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v33, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v34, v21, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v22, 0xffff, v22, v84
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v61, 8, v19
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v85, v34, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v24, 0x40c00000, v24
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v183, 24, v22
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v41, 8, v22
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v21, v35, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v34, v24, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v24
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v35.l, v85.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v34, v24, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v37, 0xffff0000, v23
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v21, 0xffff, v35, v21
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v86, v34, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v26
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v23, 0x40c00000, v23
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v37, 0x40c00000, v37 :: v_dual_lshlrev_b32 v26, 16, v26
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v87, v33, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v33.l, v86.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v34, v23, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v24, v37, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v23
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v37
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v34, v23, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v24, v24, v37, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v26, 0x40c00000, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v44, 8, v21
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v96, v34, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.l, v96.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v23, v24, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v24, 0xffff, v33, v87
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v26, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v23, 0xffff, v36, v23
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v25
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v26, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v26
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v36
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v166, 24, v24
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v176, 8, v24
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v97, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v25, 0x40c00000, v25
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v26, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v177, 8, v23
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v98, v35, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v25, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v25
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT:    v_add3_u32 v26, v26, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v25, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v101, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v35, 0xffff0000, v28
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v34.l, v97.h
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v36, v26, v38 :: v_dual_add_f32 v35, 0x40c00000, v35
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v28, 0x40c00000, v28
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v27
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v37.l, v101.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v25, v35, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v28, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_add3_u32 v25, v25, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v26, v33, v28, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v33, 0x400000, v28
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v99, v26, v33, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v26, 0xffff, v34, v98
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v100, v25, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v25, 0xffff, v37, v36
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v30
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v30
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.l, v99.h
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v148, 24, v26
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v27, 0x40c00000, v27
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v30, 0x40c00000, v30
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v28, 0xffff, v28, v100
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v150, 8, v26
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v34, v27, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v27
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v133, 24, v28
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v134, 8, v28
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v34, v27, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v33, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v161, 8, v25
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v112, v34, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v33, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v33
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v33, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v27, v35, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v37, 0xffff0000, v29
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v34, v30, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v30
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v35.l, v112.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v34, v30, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v27, 0xffff, v35, v27
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v103, v34, v38 :: v_dual_and_b32 v38, 0xffff0000, v32
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v29, 0x40c00000, v29
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v145, 8, v27
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v34, v29, 16, 1
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v102, v33, v39 :: v_dual_add_f32 v37, 0x40c00000, v37
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v29
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v34, v29, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v33.l, v103.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v30, v37, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v37
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v32, 0x40c00000, v32
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v113, v34, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11-TRUE16-NEXT:    v_add3_u32 v30, v30, v37, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.l, v113.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v29, v30, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v30, 0xffff, v33, v102
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v29, 0xffff, v36, v29
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v31
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v31
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v32, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v32
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v31, 0x40c00000, v31
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v32, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v128, 24, v30
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v129, 8, v30
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v130, 8, v29
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v114, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v31, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v31
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v32, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v115, v35, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v31, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v35, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v34.l, v114.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v116, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v37.l, v116.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v31, v35, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v36, v32, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v31, v31, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v33, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v33, 0x400000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v131, v32, v33, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v33, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v32, 0xffff, v34, v115
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v34, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v132, v31, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v31, 0xffff, v37, v36
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v33, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v34, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v33
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v33, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v2.l, v131.h
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v117, 24, v32
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v144, v34, v37 :: v_dual_and_b32 v37, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v2, v132
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v37, 0x40c00000, v37
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v34, v4, 16, 1
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v1, v35, v38 :: v_dual_add_f32 v36, 0x40c00000, v36
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v34, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v4, v37, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v147, v34, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v35.l, v144.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v4, v4, v37, 0x7fff
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v106, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v107, 8, v2
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v149, v33, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v37
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v34, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v35, v1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v34, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v118, 8, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v119, 8, v31
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v108, 8, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v162, v34, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v36.l, v162.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v4, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff0000, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v3, 0xffff, v36, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v36, 0xffff0000, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v33.l, v147.h
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v34, 0x40c00000, v38 :: v_dual_add_f32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v105, 8, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v4, 0xffff, v33, v149
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v6, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v93, 24, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v6, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v95, 8, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v164, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v36
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v165, v35, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v35, 0xffff0000, v8
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
+; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v6, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v34.l, v164.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v180, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v5, v35, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v37.l, v180.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v36, v6, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v5, v5, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v33, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v33, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v178, v6, v33, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v33, 0x40c00000, v39
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v6, 0xffff, v34, v165
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff0000, v9
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v179, v5, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v5, 0xffff, v37, v36
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v34, v33, 16, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v36, 16, v10
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v34, v33, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v33
+; GFX11-TRUE16-NEXT:    v_mov_b16_e64 v8.l, v178.h
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v78, 24, v6
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v46, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v36
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v8, 0xffff, v8, v179
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v88, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v90, 8, v5
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v34, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v7, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v62, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v63, 8, v8
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v7, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v45, v7, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v9
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v9, 0x40c00000, v39
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v34.l, v46.h
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v9, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v49, 0x400000, v7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v36, v36, v9, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v10, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v10
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v10, 0x7fff
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v42, v35, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v37, 0x40c00000, v10
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v35.l, v45.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v38, v37, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v10, 0xffff, v35, v42
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v50, 0x400000, v37
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11-TRUE16-NEXT:    v_add3_u32 v38, v38, v37, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v48, v12, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v52, 0x400000, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v43, 24, v10
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v59, v38, v50, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    v_add3_u32 v48, v48, v12, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v59.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v74, v35, v49, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v51, 0xffff0000, v11
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v56, 8, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v60, v48, v52 :: v_dual_add_f32 v37, 0x40c00000, v51
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v49, v14, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v12, 0xffff, v7, v60
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v37, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v9, v36, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v7, 0x40c00000, v11
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.l, v74.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v35, v37, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v35, 0x400000, v37
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v39, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v181, 24, v12
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v9, 0xffff, v36, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v182, 8, v12
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v11, v11, v35, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_add3_u32 v37, v39, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff0000, v13
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v48, v35, 16, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[64:65], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v89, v37, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_add3_u32 v37, v48, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v48, 0x400000, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v57, 8, v9
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v76, v37, v38 :: v_dual_and_b32 v37, 0xffff0000, v16
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v7, 0x40c00000, v39 :: v_dual_lshlrev_b32 v16, 16, v16
+; GFX11-TRUE16-NEXT:    v_add3_u32 v39, v49, v14, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v16, 0x40c00000, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v49, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v35, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v77, v39, v48, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    v_add3_u32 v14, v49, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v49, 0x400000, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v38.l, v77.h
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v7, v14, v35 :: v_dual_add_f32 v14, 0x40c00000, v37
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v15
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v48, v14, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v37, 0x40c00000, v37
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v51, 0x400000, v37
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v50, v15, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v39, v13, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v39, v13, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v13
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v16, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v94, v35, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v39, v37, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v13, v13, v16, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v48, v14, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v48, 0x400000, v14
+; GFX11-TRUE16-NEXT:    v_add3_u32 v39, v39, v37, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, 0x400000, v15
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v91, v13, v49, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11-TRUE16-NEXT:    v_add3_u32 v13, v50, v15, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v37.l, v94.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v104, v39, v51, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v39.l, v89.h
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v14, 0xffff, v38, v76
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v92, v35, v48, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v104.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v35.l, v91.h
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v11, 0xffff, v39, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v160, 24, v14
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v13, v13, v16, vcc_lo
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v163, 8, v14
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v16, 0xffff, v35, v92
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[53:54], 24, v[17:18]
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v15, 0xffff, v15, v13
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v13, 0xffff, v37, v7
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v7, 0xffff, v34, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[48:49], 24, v[15:16]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[65:66], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[66:67], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[49:50], 24, v[13:14]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[67:68], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[68:69], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[50:51], 24, v[19:20]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v135, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v146, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v151, 8, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v167, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v40, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v75, 8, v7
+; GFX11-TRUE16-NEXT:  .LBB45_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v144.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v108.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v68.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v132.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 8, v106.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v149.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v1.h, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v131.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v107.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.l, 8, v78.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v3.l, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.h, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v105.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v8
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v162.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v67.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v4, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v147.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v95.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.l, 8, v93.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v8, v10
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.h, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v5.l, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v180.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v90.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v10
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v3.h, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v5.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v66.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v6, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v12
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v164.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v4.h, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.l, 8, v88.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v165.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v8, v10
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.h, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.h, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v65.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v46.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v75.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v5.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v5.h, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v8, v10
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v178.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v63.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v179.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v62.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v14
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v74.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v10, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v16
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v57.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v64.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v45.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v56.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v18.l, v8.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.h, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v16
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v18
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v18.l, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.l, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v52.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v10, v16
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v89.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v40.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v12, v14
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v18
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v20
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v42.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v43.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v60.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.l, 8, v181.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v11.h
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v94.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v167.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v59.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v182.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v49.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v10, v11
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v77.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v163.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v15.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v48.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v20, v9
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v76.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v160.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v104.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v151.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v6
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v12, v14
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v91.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v146.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v92.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v135.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v10, v11
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v55.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v73.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v80.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v79.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v17.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v53.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v70.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v72.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v16, v18
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v12, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v14, v15
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v83.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v61.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v19.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v50.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v71.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v47.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v18, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v16, v17
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v81.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v58.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v11
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v85.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v44.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v18, v9
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v14.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v21.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v38.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v15, v16
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.l, 0xff, v96.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v177.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v14
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v82.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v41.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v84.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v183.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v17, v18
+; GFX11-TRUE16-NEXT:    v_and_b16 v16.l, 0xff, v23.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v37.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v86.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v176.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v15.l, v15.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v14.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v19, v20
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v87.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v166.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v101.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v161.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v16.l, v16.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v17.l, v17.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.l, 0xff, v25.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v36.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v21, v22
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v18.l, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v19.l, v19.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v16
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff, v17
+; GFX11-TRUE16-NEXT:    v_and_b16 v16.l, 0xff, v97.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v150.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v98.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v148.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v15.l, v15.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v24, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff, v19
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v112.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v145.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v27.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v35.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v16.l, v16.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v17.l, v17.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v15
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v18.l, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v19.l, v19.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v16
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v20, v21
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, v22, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, v24, v25
+; GFX11-TRUE16-NEXT:    v_and_b16 v20.l, 0xff, v99.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v134.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v21.l, 0xff, v100.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.h, 8, v133.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v113.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v22.h, 8, v130.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v29.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.h, 8, v34.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v103.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v24.h, 8, v129.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v28, 0xffff, v18
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v20.l, v20.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v21.l, v21.l, v21.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v22.l, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v23.l, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v24.l, v24.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v18, v26, v27
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v19, v28, v19
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v20
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v21
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v27, 0xffff, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v23
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v29, 0xffff, v24
+; GFX11-TRUE16-NEXT:    v_and_b16 v20.l, 0xff, v102.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v128.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v21.l, 0xff, v116.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.h, 8, v119.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v31.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v22.h, 8, v33.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v114.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.h, 8, v118.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v115.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v24.h, 8, v117.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v20.l, v20.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v21.l, v21.l, v21.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v22.l, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v23.l, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v24.l, v24.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v20
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff, v21
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v22
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v33, 0xffff, v23
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, v25, v26
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, v27, v28
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, v29, v30
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, v31, v32
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, v33, v24
+; GFX11-TRUE16-NEXT:    s_clause 0x5
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off offset:32
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:48
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[9:12], off offset:64
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[13:16], off offset:80
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[17:20], off offset:96
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[21:24], off offset:112
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v108, off, s32 offset:12
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v107, off, s32 offset:16
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v106, off, s32 offset:20
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v105, off, s32 offset:24
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v104, off, s32 offset:28
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v95, off, s32 offset:32
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v94, off, s32 offset:36
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v93, off, s32 offset:40
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v92, off, s32 offset:44
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v91, off, s32 offset:48
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v90, off, s32 offset:52
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v89, off, s32 offset:56
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v88, off, s32 offset:60
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v79, off, s32 offset:64
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v78, off, s32 offset:68
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v77, off, s32 offset:72
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v76, off, s32 offset:76
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v75, off, s32 offset:80
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v74, off, s32 offset:84
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v73, off, s32 offset:88
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v72, off, s32 offset:92
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v63, off, s32 offset:96
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v62, off, s32 offset:100
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v61, off, s32 offset:104
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v60, off, s32 offset:108
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v59, off, s32 offset:112
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v58, off, s32 offset:116
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v57, off, s32 offset:120
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v56, off, s32 offset:124
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v47, off, s32 offset:128
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v46, off, s32 offset:132
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v45, off, s32 offset:136
+; GFX11-TRUE16-NEXT:    s_clause 0x4
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v44, off, s32 offset:140
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v43, off, s32 offset:144
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v42, off, s32 offset:148
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v41, off, s32 offset:152
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v40, off, s32 offset:156
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v64bf16_to_v128i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x15
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s32 offset:96
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v41, s32 offset:92
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v42, s32 offset:88
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v43, s32 offset:84
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v44, s32 offset:80
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v45, s32 offset:76
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v46, s32 offset:72
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v47, s32 offset:68
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v56, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v57, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v58, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v59, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v60, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v61, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v62, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v63, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v72, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v73, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v74, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v75, s32 offset:20
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v76, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v77, s32 offset:12
+; GFX11-FAKE16-NEXT:    s_clause 0x2
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v33, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr76
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr75
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr73
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr166
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr63
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr62
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr60
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr58
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr160
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr56
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr45
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr44
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr42
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr147
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr41
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr183
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr181
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr180
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr179
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr177
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr167
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr165
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr164
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr162
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr161
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr150
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr149
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr148
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr144
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr135
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr74
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr72
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr61
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr59
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr57
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr47
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr46
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr43
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr40
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr182
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr178
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr176
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr163
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr151
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB45_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[48:49], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[49:50], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[50:51], 24, v[11:12]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[51:52], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[52:53], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[53:54], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[66:67], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v129, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v114, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v130, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v131, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v134, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v135, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v116, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v144, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v145, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v148, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v149, 24, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v118, 16, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v150, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v161, 16, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v162, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v164, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v119, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v165, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v167, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v177, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v179, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v132, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v180, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v181, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v183, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v41, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v147, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v42, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v44, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v45, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v56, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v160, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v58, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v60, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v62, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v63, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v166, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v73, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v75, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v76, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v98, 24, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v112, 16, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v97, 8, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v99, 16, v31
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 8, v31
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v100, 24, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v113, 16, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 8, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v101, 16, v29
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v86, 8, v29
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v102, 24, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v115, 16, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v85, 8, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v103, 16, v27
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v151, 24, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v117, 16, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 8, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v163, 16, v25
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v82, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v176, 24, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v128, 16, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v81, 8, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v178, 16, v23
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v182, 24, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v133, 16, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 8, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v40, 16, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v70, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v43, 24, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v146, 16, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v46, 8, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v47, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v57, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v59, 24, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v69, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v61, 8, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v72, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v74, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[54:55], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[64:65], 24, v[19:20]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[67:68], 24, v[17:18]
+; GFX11-FAKE16-NEXT:  .LBB45_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB45_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v33, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff0000, v17
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v33, 0x40c00000, v33
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v17
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v17, v33, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v33
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v17, v33, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v17, v17, v36 :: v_dual_and_b32 v18, 0xffff0000, v18
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v39, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v37, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v77, v37, v39 :: v_dual_add_f32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v20
+; GFX11-FAKE16-NEXT:    v_perm_b32 v69, v77, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v59, 24, v69
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v38, v38, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v61, 8, v69
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v33, v38, v18 :: v_dual_add_f32 v20, 0x40c00000, v20
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v48, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v39, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v36, v48, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v34, v36, v39, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v36, 16, v19
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff0000, v19
+; GFX11-FAKE16-NEXT:    v_perm_b32 v68, v34, v33, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v20, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v35, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v38, 0x40c00000, v19 :: v_dual_lshlrev_b32 v37, 16, v22
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v34, v20, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, 0x400000, v20
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v36
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v38, 16, 1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v72, 16, v68
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v74, 8, v68
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v19, v34, v19, vcc_lo
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v39, v36, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v34, 0x400000, v36
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v38, 0x7fff
+; GFX11-FAKE16-NEXT:    v_perm_b32 v65, v19, v18, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add3_u32 v20, v39, v36, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v39, 0x400000, v38
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v146, 16, v19
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v43, 24, v65
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v34, v20, v34, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v38, v38
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v19, 16, v34
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v36, v20, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v35, v35, v39, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v20
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v37, 0x40c00000, v37
+; GFX11-FAKE16-NEXT:    v_add3_u32 v36, v36, v20, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xffff0000, v21
+; GFX11-FAKE16-NEXT:    v_perm_b32 v64, v35, v34, 0x7060302
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v46, 8, v65
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v48, v37, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v20, v36, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v22, 0x40c00000, v22 :: v_dual_add_f32 v39, 0x40c00000, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v47, 16, v64
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v57, 8, v64
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[64:65], 24, v[64:65]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v22, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v22
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v24
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v36, v39, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v22, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v22, v48, v37, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v48, 0x400000, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xffff0000, v24
+; GFX11-FAKE16-NEXT:    v_add3_u32 v36, v36, v39, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v21, v35, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, 0x400000, v37
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v24, 0x40c00000, v24
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v71, v21, v20, 0x7060302
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v133, 16, v21
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v35, v22, v35 :: v_dual_add_f32 v22, 0x40c00000, v38
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v39, v39
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xffff0000, v23
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 16, v35
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v22, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v36, v36, v48, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v39, 0x400000, v22
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v38, 0x40c00000, v38
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v37, v22, 0x7fff
+; GFX11-FAKE16-NEXT:    v_perm_b32 v70, v36, v35, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v48, 0x40c00000, v23
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v49, v38, 16, 1
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v22, v37, v39 :: v_dual_lshlrev_b32 v39, 16, v26
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v36, v24, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, 0x400000, v24
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v48, 16, 1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xffff0000, v26
+; GFX11-FAKE16-NEXT:    v_add3_u32 v36, v36, v24, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v24, v49, v38, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v49, 0x400000, v48
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v37, v48, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v26, 0x40c00000, v26 :: v_dual_cndmask_b32 v23, v36, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v38
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v38, v38
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v40, 16, v70
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v128, 16, v23
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v36, v24, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v24, 0x40c00000, v39
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v48, v48
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xffff0000, v25
+; GFX11-FAKE16-NEXT:    v_perm_b32 v81, v23, v22, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v24, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v37, v37, v49, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v39, 0x40c00000, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v48, 0x400000, v24
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-FAKE16-NEXT:    v_add3_u32 v38, v38, v24, 0x7fff
+; GFX11-FAKE16-NEXT:    v_perm_b32 v80, v37, v36, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v26, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v49, 0x40c00000, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, 0x400000, v26
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v50, v39, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v24, v38, v48, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v37, v26, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v49, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v26, v50, v39, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v48, 16, v28
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v50, 0x400000, v49
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v25, v37, v25, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v39
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v39, v39
+; GFX11-FAKE16-NEXT:    v_add3_u32 v38, v38, v49, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xffff0000, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 16, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v178, 16, v80
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v37, v26, v37 :: v_dual_add_f32 v26, 0x40c00000, v48
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v49, v49
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v28, 0x40c00000, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v48, 16, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xffff0000, v27
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v39, v26, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v38, v38, v50, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v49, 0x400000, v26
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v48, 0x40c00000, v48
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-FAKE16-NEXT:    v_add3_u32 v39, v39, v26, 0x7fff
+; GFX11-FAKE16-NEXT:    v_perm_b32 v82, v38, v37, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v28, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v50, 0x40c00000, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, 0x400000, v28
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v51, v48, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v26, v39, v49, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v38, v38, v28, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v39, v50, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v28, v51, v48, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v49, 16, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v51, 0x400000, v50
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v27, v38, v27, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v48
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v48, v48
+; GFX11-FAKE16-NEXT:    v_add3_u32 v39, v39, v50, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xffff0000, v30
+; GFX11-FAKE16-NEXT:    v_perm_b32 v83, v25, v24, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v38, v28, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v28, 0x40c00000, v49
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v50, v50
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v30, 0x40c00000, v30 :: v_dual_lshlrev_b32 v49, 16, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xffff0000, v29
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v48, v28, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v39, v39, v51, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v50, 0x400000, v28
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v49, 0x40c00000, v49
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-FAKE16-NEXT:    v_add3_u32 v48, v48, v28, 0x7fff
+; GFX11-FAKE16-NEXT:    v_perm_b32 v84, v39, v38, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v39, v30, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v51, 0x40c00000, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, 0x400000, v30
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v52, v49, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v28, v48, v50, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v39, v39, v30, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v48, v51, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v30, v52, v49, 0x7fff
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v50, 16, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v52, 0x400000, v51
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v29, v39, v29, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v39, 0x400000, v49
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v49, v49
+; GFX11-FAKE16-NEXT:    v_add3_u32 v48, v48, v51, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v32, 0xffff0000, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v151, 24, v83
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v39, v30, v39 :: v_dual_add_f32 v30, 0x40c00000, v50
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v51, v51
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v32, 0x40c00000, v32
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v50, 16, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xffff0000, v31
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v49, v30, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v48, v48, v52, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v51, 0x400000, v30
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v50, 0x40c00000, v50
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-FAKE16-NEXT:    v_add3_u32 v49, v49, v30, 0x7fff
+; GFX11-FAKE16-NEXT:    v_perm_b32 v86, v48, v39, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v48, v32, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v52, 0x40c00000, v31
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, 0x400000, v32
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v53, v50, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v30, v49, v51, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v48, v48, v32, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v32
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v49, v52, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v53, v50, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v51, 16, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v53, 0x400000, v52
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v31, v48, v31, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v48, 0x400000, v50
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v50, v50
+; GFX11-FAKE16-NEXT:    v_add3_u32 v49, v49, v52, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_perm_b32 v85, v27, v26, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v48, v32, v48, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v32, 0x40c00000, v51
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v52, v52
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v51, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v50, v32, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v49, v49, v53, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v52, 0x400000, v32
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v51, 0x40c00000, v51
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v32
+; GFX11-FAKE16-NEXT:    v_add3_u32 v50, v50, v32, 0x7fff
+; GFX11-FAKE16-NEXT:    v_perm_b32 v96, v49, v48, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v49, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v53, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v54, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v55, v51, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v50, v52, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v49, v49, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v53, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v50, 0x400000, v51
+; GFX11-FAKE16-NEXT:    v_perm_b32 v87, v29, v28, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v49, v54, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v49, v55, v51, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v51, v51
+; GFX11-FAKE16-NEXT:    v_add3_u32 v52, v32, v53, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, 0x400000, v53
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v49, v50, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v49, 0x40c00000, v54
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v53, v53
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v51, v49, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v50, v52, v55, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v52, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v53, 0x400000, v49
+; GFX11-FAKE16-NEXT:    v_add3_u32 v51, v51, v49, 0x7fff
+; GFX11-FAKE16-NEXT:    v_perm_b32 v98, v50, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v50, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v52, 0x40c00000, v52
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v49, v49
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v54, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_add3_u32 v50, v50, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v55, v52, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v49, v51, v53, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v51, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v53, 0x400000, v52
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v75, 16, v98
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v76, 8, v98
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v50, v54, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v50, v55, v52, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v6
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v52, v52
+; GFX11-FAKE16-NEXT:    v_add3_u32 v51, v51, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v52, 0x40c00000, v54
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v50, v50, v53, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v53, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v54, 0x400000, v52
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v51, v55, vcc_lo
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v51, v52, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v53, 0x40c00000, v53
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v52, v52
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    v_perm_b32 v100, v3, v50, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v6, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v51, v51, v52, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v66, v53, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v52, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v3, v3, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v51, v51, v54, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v66, v53, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v54, 0x400000, v53
+; GFX11-FAKE16-NEXT:    v_add3_u32 v52, v52, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v66, 0x400000, v5
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v55, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v55, 16, v8
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v53, v53
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT:    v_perm_b32 v97, v31, v30, 0x7060302
+; GFX11-FAKE16-NEXT:    v_perm_b32 v103, v3, v51, 0x7060302
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v147, 16, v3
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v53, v6, v54 :: v_dual_add_f32 v6, 0x40c00000, v55
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v52, v66, vcc_lo
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v52, v6, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v54, 0x40c00000, v54
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-FAKE16-NEXT:    v_perm_b32 v102, v5, v53, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v5, v8, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v52, v52, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v66, 0x400000, v8
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v67, v54, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v99, v2, v1, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add3_u32 v5, v5, v8, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v52, v55, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v52, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v67, v54, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, 0x400000, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v67, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v5, v66, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v66, 16, v10
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v54, v54
+; GFX11-FAKE16-NEXT:    v_add3_u32 v52, v52, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v166, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v54, v8, v55, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v66
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v55, 16, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v66, 0x400000, v8
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v52, v67, vcc_lo
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v52, v8, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v55, 0x40c00000, v55
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT:    v_perm_b32 v182, v7, v54, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v7, v10, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v52, v52, v8, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v67, 0x400000, v10
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v112, v55, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v183, v5, v6, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v7, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v52, v66, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v52, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v10, v112, v55, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v66, 0x400000, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v112, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v7, v67, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v67, 16, v12
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v55, v55
+; GFX11-FAKE16-NEXT:    v_add3_u32 v52, v52, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-FAKE16-NEXT:    v_perm_b32 v101, v4, v49, 0x7060302
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v160, 16, v4
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v55, v10, v66 :: v_dual_add_f32 v10, 0x40c00000, v67
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v49
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v50
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v66, v10, 16, 1
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v9, v52, v112 :: v_dual_lshlrev_b32 v52, 16, v11
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v67, v12, 16, 1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v176, v9, v55, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v9, 0x40c00000, v52
+; GFX11-FAKE16-NEXT:    v_add3_u32 v52, v66, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v66, 0x400000, v10
+; GFX11-FAKE16-NEXT:    v_add3_u32 v67, v67, v12, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v112, 0x400000, v12
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v113, v9, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v11, 0x40c00000, v11 :: v_dual_cndmask_b32 v10, v52, v66
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v66, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_add3_u32 v52, v113, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    v_perm_b32 v177, v7, v8, 0x7060302
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v32
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v12, v67, v112 :: v_dual_lshlrev_b32 v67, 16, v14
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v112, v11, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 16, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 16, v26
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v9, v52, v66 :: v_dual_add_f32 v52, 0x40c00000, v67
+; GFX11-FAKE16-NEXT:    v_add3_u32 v66, v112, v11, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v67, 0x400000, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v112, 16, v13
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v113, v52, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 16, v24
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v11, v66, v67 :: v_dual_add_f32 v66, 0x40c00000, v112
+; GFX11-FAKE16-NEXT:    v_add3_u32 v67, v113, v52, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v112, 0x400000, v52
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v113, v14, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v52, v52
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v114, v66, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v115, 0x400000, v66
+; GFX11-FAKE16-NEXT:    v_perm_b32 v162, v11, v9, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v52, v67, v112, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v67, v113, v14, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v112, 0x400000, v14
+; GFX11-FAKE16-NEXT:    v_add3_u32 v113, v114, v66, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v114, 16, v16
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v116, v13, 16, 1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 16, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 16, v20
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v14, v67, v112 :: v_dual_add_f32 v67, 0x40c00000, v114
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v66, v66
+; GFX11-FAKE16-NEXT:    v_add3_u32 v112, v116, v13, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v16, 0x40c00000, v16
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v149, v14, v52, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v114, v67, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v66, v113, v115, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v113, 0x400000, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v115, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-FAKE16-NEXT:    v_perm_b32 v163, v12, v10, 0x7060302
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v20, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v17
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v13, v112, v113 :: v_dual_add_f32 v112, 0x40c00000, v115
+; GFX11-FAKE16-NEXT:    v_add3_u32 v113, v114, v67, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v114, 0x400000, v67
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v115, v16, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v67, v67
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v116, v112, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v117, 0x400000, v112
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v118, 0x400000, v15
+; GFX11-FAKE16-NEXT:    v_perm_b32 v148, v13, v66, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v67, v113, v114, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v114, v115, v16, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v115, 0x400000, v16
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v113, v15, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v116, v116, v112, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 16, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[33:34], 24, v[96:97]
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v114, v115, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v112, v112
+; GFX11-FAKE16-NEXT:    v_add3_u32 v113, v113, v15, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[86:87]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[84:85]
+; GFX11-FAKE16-NEXT:    v_perm_b32 v135, v16, v67, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v112, v116, v117, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v116, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v52
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v132, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v53
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v15, v113, v118, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v118, 16, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v12, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v6
+; GFX11-FAKE16-NEXT:    v_perm_b32 v134, v15, v112, 0x7060302
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 16, v112
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v112, 16, v31
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 16, v48
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v51
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[48:49], 24, v[134:135]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[49:50], 24, v[148:149]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[50:51], 24, v[162:163]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[51:52], 24, v[176:177]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v117, 16, v25
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[52:53], 24, v[182:183]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[82:83]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v114, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 16, v67
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 16, v66
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v119, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v54
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v115, 16, v27
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 16, v38
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[53:54], 24, v[102:103]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[66:67], 24, v[98:99]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[37:38], 24, v[80:81]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v11, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v55
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v113, 16, v29
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 16, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[54:55], 24, v[100:101]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[38:39], 24, v[70:71]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[67:68], 24, v[68:69]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v129, 24, v135
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v130, 8, v135
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v131, 16, v134
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v134, 8, v134
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v135, 24, v149
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v144, 8, v149
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v145, 16, v148
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v148, 8, v148
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v149, 24, v163
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v150, 8, v163
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v161, 16, v162
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v162, 8, v162
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v164, 24, v177
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v165, 8, v177
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v167, 16, v176
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v177, 8, v176
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v179, 24, v183
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v180, 8, v183
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v181, 16, v182
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v183, 8, v182
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v41, 24, v103
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v42, 8, v103
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v44, 16, v102
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v45, 8, v102
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v56, 24, v101
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v58, 8, v101
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v60, 16, v100
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v62, 8, v100
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v63, 24, v99
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v73, 8, v99
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v98, 24, v97
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v97, 8, v97
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v99, 16, v96
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 8, v96
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v100, 24, v87
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 8, v87
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v101, 16, v86
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v86, 8, v86
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v102, 24, v85
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v85, 8, v85
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v103, 16, v84
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 8, v84
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 8, v83
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v163, 16, v82
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v82, 8, v82
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v176, 24, v81
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v81, 8, v81
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 8, v80
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v182, 24, v71
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 8, v71
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v70, 8, v70
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v69, 16, v77
+; GFX11-FAKE16-NEXT:  .LBB45_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v76
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v66
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v63
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v55, 0xff, v75
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v66, 0xff, v60
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v39, v55, v39
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v73
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v54, v66, v54
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v66, 8, v56
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v55, 0xff, v166
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v53, 8, v53
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, v55, v65
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v62
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v52, 8, v52
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v65
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v58
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v65, 0xff, v160
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v51, 8, v51
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v54, v65, v66
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v45
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v65, 0xff, v44
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v53, v65, v53
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v42
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v55, 0xff, v147
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v41
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v53, v55, v65
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v183
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v55, 0xff, v181
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v52, v55, v52
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v53, 8, v180
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v54, 0xff, v132
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v179
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v39
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v52
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v53
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v52, v54, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v54, 0xff, v167
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v53, 8, v177
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v165
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v52, 16, v52
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v51, v54, v51
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v52
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v51
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v51, 0xff, v119
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v52, 8, v164
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v53, 8, v162
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v54, 0xff, v161
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v50, 8, v50
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v150
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v65, 0xff, v118
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v66, 8, v149
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v51, v51, v52
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v50, v54, v50
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v52, v65, v66
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v51, 16, v51
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v50, 16, v50
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v52, 16, v52
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v9, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v10, v51
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v11, v50
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v12, v52
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v6, 8, v148
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v145
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v49
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v10, 8, v144
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v116
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v12, 8, v135
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v14, 8, v134
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v13, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v131
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v48
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v130
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v114
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v129
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v74
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v39, 0xff, v72
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v48, 8, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v39, v48
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v13, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v61
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v69
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v59
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v57
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v47
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v64
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v46
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v18, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v146
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v43
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v18, 8, v70
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v40
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v38
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v71
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v38, 0xff, v133
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v182
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v19, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v21, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v38, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xffff, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v18, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v178
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v18, 8, v37
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v81
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v128
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v176
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v82
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v19, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v21, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v23, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v163
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v83
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v117
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v151
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v84
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v36, 0xff, v103
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v35, 8, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v36, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xffff, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v19, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v21, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v23, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v115
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v102
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v29
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v86
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v101
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v29, 8, v87
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v28, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v113
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v26, 8, v100
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v28, 8, v96
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v99
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v30, 8, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v32, 8, v97
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xff, v112
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v34, 8, v98
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v27, v28
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v29, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v31, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v33, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xffff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xffff, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xffff, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xffff, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xffff, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v28, v29
+; GFX11-FAKE16-NEXT:    s_clause 0x5
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off offset:32
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:48
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[9:12], off offset:64
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[13:16], off offset:80
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[17:20], off offset:96
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[21:24], off offset:112
+; GFX11-FAKE16-NEXT:    s_clause 0x15
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v77, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v76, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v75, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v74, off, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v73, off, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v72, off, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v63, off, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v62, off, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v61, off, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v60, off, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v59, off, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v58, off, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v57, off, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v56, off, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v47, off, s32 offset:68
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v46, off, s32 offset:72
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v45, off, s32 offset:76
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v44, off, s32 offset:80
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v43, off, s32 offset:84
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v42, off, s32 offset:88
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v41, off, s32 offset:92
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s32 offset:96
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -81276,923 +91583,1689 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v128i8_to_v64f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_store_b32 off, v40, s32 offset:580
-; GFX11-NEXT:    scratch_store_b32 off, v41, s32 offset:576
-; GFX11-NEXT:    scratch_store_b32 off, v42, s32 offset:572
-; GFX11-NEXT:    scratch_store_b32 off, v43, s32 offset:568
-; GFX11-NEXT:    scratch_store_b32 off, v44, s32 offset:564
-; GFX11-NEXT:    scratch_store_b32 off, v45, s32 offset:560
-; GFX11-NEXT:    scratch_store_b32 off, v46, s32 offset:556
-; GFX11-NEXT:    scratch_store_b32 off, v47, s32 offset:552
-; GFX11-NEXT:    scratch_store_b32 off, v56, s32 offset:548
-; GFX11-NEXT:    scratch_store_b32 off, v57, s32 offset:544
-; GFX11-NEXT:    scratch_store_b32 off, v58, s32 offset:540
-; GFX11-NEXT:    scratch_store_b32 off, v59, s32 offset:536
-; GFX11-NEXT:    scratch_store_b32 off, v60, s32 offset:532
-; GFX11-NEXT:    scratch_store_b32 off, v61, s32 offset:528
-; GFX11-NEXT:    scratch_store_b32 off, v62, s32 offset:524
-; GFX11-NEXT:    scratch_store_b32 off, v63, s32 offset:520
-; GFX11-NEXT:    scratch_store_b32 off, v72, s32 offset:516
-; GFX11-NEXT:    scratch_store_b32 off, v73, s32 offset:512
-; GFX11-NEXT:    scratch_store_b32 off, v74, s32 offset:508
-; GFX11-NEXT:    scratch_store_b32 off, v75, s32 offset:504
-; GFX11-NEXT:    scratch_store_b32 off, v76, s32 offset:500
-; GFX11-NEXT:    scratch_store_b32 off, v77, s32 offset:496
-; GFX11-NEXT:    scratch_store_b32 off, v78, s32 offset:492
-; GFX11-NEXT:    scratch_store_b32 off, v79, s32 offset:488
-; GFX11-NEXT:    scratch_store_b32 off, v88, s32 offset:484
-; GFX11-NEXT:    scratch_store_b32 off, v89, s32 offset:480
-; GFX11-NEXT:    scratch_store_b32 off, v90, s32 offset:476
-; GFX11-NEXT:    scratch_store_b32 off, v91, s32 offset:472
-; GFX11-NEXT:    scratch_store_b32 off, v92, s32 offset:468
-; GFX11-NEXT:    scratch_store_b32 off, v93, s32 offset:464
-; GFX11-NEXT:    scratch_store_b32 off, v94, s32 offset:460
-; GFX11-NEXT:    scratch_store_b32 off, v95, s32 offset:456
-; GFX11-NEXT:    s_clause 0xf
-; GFX11-NEXT:    scratch_store_b32 off, v104, s32 offset:452
-; GFX11-NEXT:    scratch_store_b32 off, v105, s32 offset:448
-; GFX11-NEXT:    scratch_store_b32 off, v106, s32 offset:444
-; GFX11-NEXT:    scratch_store_b32 off, v107, s32 offset:440
-; GFX11-NEXT:    scratch_store_b32 off, v108, s32 offset:436
-; GFX11-NEXT:    scratch_store_b32 off, v109, s32 offset:432
-; GFX11-NEXT:    scratch_store_b32 off, v110, s32 offset:428
-; GFX11-NEXT:    scratch_store_b32 off, v111, s32 offset:424
-; GFX11-NEXT:    scratch_store_b32 off, v120, s32 offset:420
-; GFX11-NEXT:    scratch_store_b32 off, v121, s32 offset:416
-; GFX11-NEXT:    scratch_store_b32 off, v122, s32 offset:412
-; GFX11-NEXT:    scratch_store_b32 off, v123, s32 offset:408
-; GFX11-NEXT:    scratch_store_b32 off, v124, s32 offset:404
-; GFX11-NEXT:    scratch_store_b32 off, v125, s32 offset:400
-; GFX11-NEXT:    scratch_store_b32 off, v126, s32 offset:396
-; GFX11-NEXT:    scratch_store_b32 off, v127, s32 offset:392
-; GFX11-NEXT:    v_dual_mov_b32 v37, v30 :: v_dual_mov_b32 v54, v24
-; GFX11-NEXT:    v_dual_mov_b32 v55, v28 :: v_dual_mov_b32 v52, v26
-; GFX11-NEXT:    v_dual_mov_b32 v50, v22 :: v_dual_mov_b32 v53, v20
-; GFX11-NEXT:    v_dual_mov_b32 v34, v18 :: v_dual_mov_b32 v51, v16
-; GFX11-NEXT:    v_dual_mov_b32 v36, v14 :: v_dual_mov_b32 v49, v12
-; GFX11-NEXT:    v_dual_mov_b32 v32, v10 :: v_dual_mov_b32 v39, v4
-; GFX11-NEXT:    v_dual_mov_b32 v48, v8 :: v_dual_mov_b32 v33, v6
-; GFX11-NEXT:    v_dual_mov_b32 v35, v2 :: v_dual_mov_b32 v38, v0
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v0, off, s32 offset:384
-; GFX11-NEXT:    scratch_load_u16 v118, off, s32 offset:380
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32 offset:376
-; GFX11-NEXT:    scratch_load_u16 v134, off, s32 offset:372
-; GFX11-NEXT:    scratch_load_u16 v4, off, s32 offset:368
-; GFX11-NEXT:    scratch_load_u16 v116, off, s32 offset:364
-; GFX11-NEXT:    scratch_load_u16 v6, off, s32 offset:360
-; GFX11-NEXT:    scratch_load_u16 v131, off, s32 offset:356
-; GFX11-NEXT:    scratch_load_u16 v8, off, s32 offset:352
-; GFX11-NEXT:    scratch_load_u16 v98, off, s32 offset:348
-; GFX11-NEXT:    scratch_load_u16 v10, off, s32 offset:344
-; GFX11-NEXT:    scratch_load_u16 v129, off, s32 offset:340
-; GFX11-NEXT:    scratch_load_u16 v12, off, s32 offset:336
-; GFX11-NEXT:    scratch_load_u16 v99, off, s32 offset:332
-; GFX11-NEXT:    scratch_load_u16 v14, off, s32 offset:328
-; GFX11-NEXT:    scratch_load_u16 v112, off, s32 offset:324
-; GFX11-NEXT:    scratch_load_u16 v16, off, s32 offset:320
-; GFX11-NEXT:    scratch_load_u16 v81, off, s32 offset:316
-; GFX11-NEXT:    scratch_load_u16 v18, off, s32 offset:312
-; GFX11-NEXT:    scratch_load_u16 v103, off, s32 offset:308
-; GFX11-NEXT:    scratch_load_u16 v20, off, s32 offset:304
-; GFX11-NEXT:    scratch_load_u16 v86, off, s32 offset:300
-; GFX11-NEXT:    scratch_load_u16 v22, off, s32 offset:296
-; GFX11-NEXT:    scratch_load_u16 v101, off, s32 offset:292
-; GFX11-NEXT:    scratch_load_u16 v24, off, s32 offset:288
-; GFX11-NEXT:    scratch_load_u16 v83, off, s32 offset:284
-; GFX11-NEXT:    scratch_load_u16 v26, off, s32 offset:280
-; GFX11-NEXT:    scratch_load_u16 v97, off, s32 offset:276
-; GFX11-NEXT:    scratch_load_u16 v28, off, s32 offset:272
-; GFX11-NEXT:    scratch_load_u16 v67, off, s32 offset:268
-; GFX11-NEXT:    scratch_load_u16 v30, off, s32 offset:264
-; GFX11-NEXT:    scratch_load_u16 v85, off, s32 offset:260
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v31, off, s32 offset:256
-; GFX11-NEXT:    scratch_load_u16 v68, off, s32 offset:252
-; GFX11-NEXT:    scratch_load_u16 v94, off, s32 offset:248
-; GFX11-NEXT:    scratch_load_u16 v80, off, s32 offset:244
-; GFX11-NEXT:    scratch_load_u16 v88, off, s32 offset:240
-; GFX11-NEXT:    scratch_load_u16 v64, off, s32 offset:236
-; GFX11-NEXT:    scratch_load_u16 v93, off, s32 offset:232
-; GFX11-NEXT:    scratch_load_u16 v69, off, s32 offset:228
-; GFX11-NEXT:    scratch_load_u16 v91, off, s32 offset:224
-; GFX11-NEXT:    scratch_load_u16 v65, off, s32 offset:220
-; GFX11-NEXT:    scratch_load_u16 v92, off, s32 offset:216
-; GFX11-NEXT:    scratch_load_b32 v150, off, s32 offset:388
-; GFX11-NEXT:    scratch_load_u16 v182, off, s32
-; GFX11-NEXT:    scratch_load_u16 v40, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_u16 v43, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_u16 v44, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_u16 v45, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_u16 v46, off, s32 offset:40
-; GFX11-NEXT:    scratch_load_u16 v47, off, s32 offset:48
-; GFX11-NEXT:    scratch_load_u16 v56, off, s32 offset:56
-; GFX11-NEXT:    scratch_load_u16 v58, off, s32 offset:64
-; GFX11-NEXT:    scratch_load_u16 v59, off, s32 offset:72
-; GFX11-NEXT:    scratch_load_u16 v60, off, s32 offset:80
-; GFX11-NEXT:    scratch_load_u16 v61, off, s32 offset:88
-; GFX11-NEXT:    scratch_load_u16 v62, off, s32 offset:96
-; GFX11-NEXT:    scratch_load_u16 v63, off, s32 offset:104
-; GFX11-NEXT:    scratch_load_u16 v72, off, s32 offset:112
-; GFX11-NEXT:    scratch_load_u16 v73, off, s32 offset:120
-; GFX11-NEXT:    scratch_load_u16 v74, off, s32 offset:128
-; GFX11-NEXT:    scratch_load_u16 v75, off, s32 offset:136
-; GFX11-NEXT:    scratch_load_u16 v76, off, s32 offset:144
-; GFX11-NEXT:    scratch_load_u16 v77, off, s32 offset:152
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v78, off, s32 offset:160
-; GFX11-NEXT:    scratch_load_u16 v79, off, s32 offset:168
-; GFX11-NEXT:    scratch_load_u16 v89, off, s32 offset:176
-; GFX11-NEXT:    scratch_load_u16 v90, off, s32 offset:184
-; GFX11-NEXT:    scratch_load_u16 v95, off, s32 offset:192
-; GFX11-NEXT:    scratch_load_u16 v104, off, s32 offset:200
-; GFX11-NEXT:    scratch_load_u16 v105, off, s32 offset:208
-; GFX11-NEXT:    scratch_load_u16 v42, off, s32 offset:212
-; GFX11-NEXT:    scratch_load_u16 v180, off, s32 offset:204
-; GFX11-NEXT:    scratch_load_u16 v183, off, s32 offset:196
-; GFX11-NEXT:    scratch_load_u16 v165, off, s32 offset:188
-; GFX11-NEXT:    scratch_load_u16 v179, off, s32 offset:180
-; GFX11-NEXT:    scratch_load_u16 v163, off, s32 offset:172
-; GFX11-NEXT:    scratch_load_u16 v177, off, s32 offset:164
-; GFX11-NEXT:    scratch_load_u16 v145, off, s32 offset:156
-; GFX11-NEXT:    scratch_load_u16 v166, off, s32 offset:148
-; GFX11-NEXT:    scratch_load_u16 v148, off, s32 offset:140
-; GFX11-NEXT:    scratch_load_u16 v151, off, s32 offset:132
-; GFX11-NEXT:    scratch_load_u16 v164, off, s32 offset:124
-; GFX11-NEXT:    scratch_load_u16 v178, off, s32 offset:116
-; GFX11-NEXT:    scratch_load_u16 v146, off, s32 offset:108
-; GFX11-NEXT:    scratch_load_u16 v162, off, s32 offset:100
-; GFX11-NEXT:    scratch_load_u16 v144, off, s32 offset:92
-; GFX11-NEXT:    scratch_load_u16 v149, off, s32 offset:84
-; GFX11-NEXT:    scratch_load_u16 v119, off, s32 offset:76
-; GFX11-NEXT:    scratch_load_u16 v147, off, s32 offset:68
-; GFX11-NEXT:    scratch_load_u16 v130, off, s32 offset:60
-; GFX11-NEXT:    scratch_load_u16 v135, off, s32 offset:52
-; GFX11-NEXT:    scratch_load_u16 v117, off, s32 offset:44
-; GFX11-NEXT:    scratch_load_u16 v133, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_u16 v96, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_u16 v114, off, s32 offset:20
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_u16 v87, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_u16 v102, off, s32 offset:4
-; GFX11-NEXT:    v_lshlrev_b16 v70, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v71, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v84, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v82, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v115, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v66, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v128, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v113, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v132, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v100, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v161, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v160, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v176, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v167, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v181, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(62)
-; GFX11-NEXT:    v_lshlrev_b16 v127, 8, v0
-; GFX11-NEXT:    v_lshlrev_b16 v126, 8, v2
-; GFX11-NEXT:    v_lshlrev_b16 v124, 8, v4
-; GFX11-NEXT:    v_lshlrev_b16 v125, 8, v6
-; GFX11-NEXT:    v_lshlrev_b16 v120, 8, v8
-; GFX11-NEXT:    v_lshlrev_b16 v123, 8, v10
-; GFX11-NEXT:    v_lshlrev_b16 v121, 8, v12
-; GFX11-NEXT:    v_lshlrev_b16 v122, 8, v14
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
-; GFX11-NEXT:    v_lshlrev_b16 v106, 8, v16
-; GFX11-NEXT:    v_lshlrev_b16 v111, 8, v18
-; GFX11-NEXT:    v_lshlrev_b16 v109, 8, v20
-; GFX11-NEXT:    v_lshlrev_b16 v110, 8, v22
-; GFX11-NEXT:    v_lshlrev_b16 v107, 8, v24
-; GFX11-NEXT:    v_lshlrev_b16 v108, 8, v26
-; GFX11-NEXT:    s_waitcnt vmcnt(61)
-; GFX11-NEXT:    v_lshlrev_b16 v88, 8, v88
-; GFX11-NEXT:    s_waitcnt vmcnt(59)
-; GFX11-NEXT:    v_lshlrev_b16 v93, 8, v93
-; GFX11-NEXT:    s_waitcnt vmcnt(57)
-; GFX11-NEXT:    v_lshlrev_b16 v91, 8, v91
-; GFX11-NEXT:    s_waitcnt vmcnt(55)
-; GFX11-NEXT:    v_lshlrev_b16 v92, 8, v92
-; GFX11-NEXT:    s_waitcnt vmcnt(54)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v150
-; GFX11-NEXT:    s_waitcnt vmcnt(53)
-; GFX11-NEXT:    v_lshlrev_b16 v150, 8, v182
-; GFX11-NEXT:    s_waitcnt vmcnt(52)
-; GFX11-NEXT:    v_lshlrev_b16 v41, 8, v40
-; GFX11-NEXT:    s_waitcnt vmcnt(51)
-; GFX11-NEXT:    v_lshlrev_b16 v40, 8, v43
-; GFX11-NEXT:    s_waitcnt vmcnt(50)
-; GFX11-NEXT:    v_lshlrev_b16 v43, 8, v44
-; GFX11-NEXT:    s_waitcnt vmcnt(49)
-; GFX11-NEXT:    v_lshlrev_b16 v182, 8, v45
-; GFX11-NEXT:    s_waitcnt vmcnt(48)
-; GFX11-NEXT:    v_lshlrev_b16 v46, 8, v46
-; GFX11-NEXT:    s_waitcnt vmcnt(47)
-; GFX11-NEXT:    v_lshlrev_b16 v45, 8, v47
-; GFX11-NEXT:    s_waitcnt vmcnt(46)
-; GFX11-NEXT:    v_lshlrev_b16 v57, 8, v56
-; GFX11-NEXT:    s_waitcnt vmcnt(45)
-; GFX11-NEXT:    v_lshlrev_b16 v56, 8, v58
-; GFX11-NEXT:    s_waitcnt vmcnt(44)
-; GFX11-NEXT:    v_lshlrev_b16 v58, 8, v59
-; GFX11-NEXT:    s_waitcnt vmcnt(43)
-; GFX11-NEXT:    v_lshlrev_b16 v44, 8, v60
-; GFX11-NEXT:    s_waitcnt vmcnt(42)
-; GFX11-NEXT:    v_lshlrev_b16 v60, 8, v61
-; GFX11-NEXT:    s_waitcnt vmcnt(41)
-; GFX11-NEXT:    v_lshlrev_b16 v59, 8, v62
-; GFX11-NEXT:    s_waitcnt vmcnt(40)
-; GFX11-NEXT:    v_lshlrev_b16 v62, 8, v63
-; GFX11-NEXT:    s_waitcnt vmcnt(39)
-; GFX11-NEXT:    v_lshlrev_b16 v47, 8, v72
-; GFX11-NEXT:    s_waitcnt vmcnt(38)
-; GFX11-NEXT:    v_lshlrev_b16 v72, 8, v73
-; GFX11-NEXT:    s_waitcnt vmcnt(37)
-; GFX11-NEXT:    v_lshlrev_b16 v63, 8, v74
-; GFX11-NEXT:    s_waitcnt vmcnt(36)
-; GFX11-NEXT:    v_lshlrev_b16 v74, 8, v75
-; GFX11-NEXT:    s_waitcnt vmcnt(35)
-; GFX11-NEXT:    v_lshlrev_b16 v73, 8, v76
-; GFX11-NEXT:    s_waitcnt vmcnt(34)
-; GFX11-NEXT:    v_lshlrev_b16 v75, 8, v77
-; GFX11-NEXT:    s_waitcnt vmcnt(33)
-; GFX11-NEXT:    v_lshlrev_b16 v61, 8, v78
-; GFX11-NEXT:    s_waitcnt vmcnt(32)
-; GFX11-NEXT:    v_lshlrev_b16 v78, 8, v79
-; GFX11-NEXT:    s_waitcnt vmcnt(31)
-; GFX11-NEXT:    v_lshlrev_b16 v77, 8, v89
-; GFX11-NEXT:    s_waitcnt vmcnt(30)
-; GFX11-NEXT:    v_lshlrev_b16 v79, 8, v90
-; GFX11-NEXT:    s_waitcnt vmcnt(29)
-; GFX11-NEXT:    v_lshlrev_b16 v76, 8, v95
-; GFX11-NEXT:    s_waitcnt vmcnt(28)
-; GFX11-NEXT:    v_lshlrev_b16 v90, 8, v104
-; GFX11-NEXT:    s_waitcnt vmcnt(27)
-; GFX11-NEXT:    v_lshlrev_b16 v89, 8, v105
-; GFX11-NEXT:    v_lshlrev_b16 v104, 8, v94
-; GFX11-NEXT:    v_lshlrev_b16 v95, 8, v31
-; GFX11-NEXT:    v_lshlrev_b16 v105, 8, v30
-; GFX11-NEXT:    v_lshlrev_b16 v94, 8, v28
-; GFX11-NEXT:    ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB46_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v38
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v35
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v39
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v48
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v70
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v71
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v84
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v82
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v36
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v51
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v34
-; GFX11-NEXT:    v_perm_b32 v1, v3, v2, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v49
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v53
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v50
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v54
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v52
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v115
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v66
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v128
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v113
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v132
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v100
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v161
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v160
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v176
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v167
-; GFX11-NEXT:    v_perm_b32 v2, v2, v4, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v3, v5, v3, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v4, v7, v6, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v5, v9, v8, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v6, v11, v10, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v55
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v37
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v102
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v87
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v114
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v96
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v133
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v117
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v135
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v130
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v181
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v150
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v41
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v40
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v43
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v182
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v46
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v45
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v57
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v56
-; GFX11-NEXT:    v_perm_b32 v7, v8, v7, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v8, v10, v9, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v9, v12, v11, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v10, v14, v13, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v11, v16, v15, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v147
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v119
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v149
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v144
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v162
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v146
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v178
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v164
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v151
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v148
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v58
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v44
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v60
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v59
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v62
-; GFX11-NEXT:    v_or_b32_e32 v17, v17, v47
-; GFX11-NEXT:    v_or_b32_e32 v18, v18, v72
-; GFX11-NEXT:    v_or_b32_e32 v19, v19, v63
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v74
-; GFX11-NEXT:    v_or_b32_e32 v21, v21, v73
-; GFX11-NEXT:    v_perm_b32 v12, v13, v12, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v13, v15, v14, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v14, v17, v16, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v15, v19, v18, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v16, v21, v20, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v166
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v145
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v177
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v163
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v179
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v165
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v183
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v180
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v42
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v65
-; GFX11-NEXT:    v_or_b32_e32 v17, v17, v75
-; GFX11-NEXT:    v_or_b32_e32 v18, v18, v61
-; GFX11-NEXT:    v_or_b32_e32 v19, v19, v78
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v77
-; GFX11-NEXT:    v_or_b32_e32 v21, v21, v79
-; GFX11-NEXT:    v_or_b32_e32 v22, v22, v76
-; GFX11-NEXT:    v_or_b32_e32 v23, v23, v90
-; GFX11-NEXT:    v_or_b32_e32 v24, v24, v89
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v92
-; GFX11-NEXT:    v_or_b32_e32 v26, v26, v91
-; GFX11-NEXT:    v_perm_b32 v17, v18, v17, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v18, v20, v19, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v19, v22, v21, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v20, v24, v23, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v21, v26, v25, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v69
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v64
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v80
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v68
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v85
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v67
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v97
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v83
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v101
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v86
-; GFX11-NEXT:    v_or_b32_e32 v22, v22, v93
-; GFX11-NEXT:    v_or_b32_e32 v23, v23, v88
-; GFX11-NEXT:    v_or_b32_e32 v24, v24, v104
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v95
-; GFX11-NEXT:    v_or_b32_e32 v26, v26, v105
-; GFX11-NEXT:    v_or_b32_e32 v27, v27, v94
-; GFX11-NEXT:    v_or_b32_e32 v28, v28, v108
-; GFX11-NEXT:    v_or_b32_e32 v29, v29, v107
-; GFX11-NEXT:    v_or_b32_e32 v30, v30, v110
-; GFX11-NEXT:    v_or_b32_e32 v31, v31, v109
-; GFX11-NEXT:    v_perm_b32 v22, v23, v22, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v23, v25, v24, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v24, v27, v26, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v25, v29, v28, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v26, v31, v30, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v103
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v81
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v112
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v99
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v129
-; GFX11-NEXT:    v_and_b32_e32 v32, 0xff, v98
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xff, v131
-; GFX11-NEXT:    v_and_b32_e32 v34, 0xff, v116
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xff, v134
-; GFX11-NEXT:    v_and_b32_e32 v36, 0xff, v118
-; GFX11-NEXT:    v_or_b32_e32 v27, v27, v111
-; GFX11-NEXT:    v_or_b32_e32 v28, v28, v106
-; GFX11-NEXT:    v_or_b32_e32 v29, v29, v122
-; GFX11-NEXT:    v_or_b32_e32 v30, v30, v121
-; GFX11-NEXT:    v_or_b32_e32 v31, v31, v123
-; GFX11-NEXT:    v_or_b32_e32 v32, v32, v120
-; GFX11-NEXT:    v_or_b32_e32 v33, v33, v125
-; GFX11-NEXT:    v_or_b32_e32 v34, v34, v124
-; GFX11-NEXT:    v_or_b32_e32 v35, v35, v126
-; GFX11-NEXT:    v_or_b32_e32 v36, v36, v127
-; GFX11-NEXT:    v_perm_b32 v27, v28, v27, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v28, v30, v29, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v29, v32, v31, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v30, v34, v33, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v31, v36, v35, 0x5040100
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr102
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr114
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr133
-; GFX11-NEXT:    ; implicit-def: $vgpr117
-; GFX11-NEXT:    ; implicit-def: $vgpr135
-; GFX11-NEXT:    ; implicit-def: $vgpr130
-; GFX11-NEXT:    ; implicit-def: $vgpr147
-; GFX11-NEXT:    ; implicit-def: $vgpr119
-; GFX11-NEXT:    ; implicit-def: $vgpr149
-; GFX11-NEXT:    ; implicit-def: $vgpr144
-; GFX11-NEXT:    ; implicit-def: $vgpr162
-; GFX11-NEXT:    ; implicit-def: $vgpr146
-; GFX11-NEXT:    ; implicit-def: $vgpr178
-; GFX11-NEXT:    ; implicit-def: $vgpr164
-; GFX11-NEXT:    ; implicit-def: $vgpr151
-; GFX11-NEXT:    ; implicit-def: $vgpr148
-; GFX11-NEXT:    ; implicit-def: $vgpr166
-; GFX11-NEXT:    ; implicit-def: $vgpr145
-; GFX11-NEXT:    ; implicit-def: $vgpr177
-; GFX11-NEXT:    ; implicit-def: $vgpr163
-; GFX11-NEXT:    ; implicit-def: $vgpr179
-; GFX11-NEXT:    ; implicit-def: $vgpr165
-; GFX11-NEXT:    ; implicit-def: $vgpr183
-; GFX11-NEXT:    ; implicit-def: $vgpr180
-; GFX11-NEXT:    ; implicit-def: $vgpr42
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr67
-; GFX11-NEXT:    ; implicit-def: $vgpr97
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr101
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr103
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr112
-; GFX11-NEXT:    ; implicit-def: $vgpr99
-; GFX11-NEXT:    ; implicit-def: $vgpr129
-; GFX11-NEXT:    ; implicit-def: $vgpr98
-; GFX11-NEXT:    ; implicit-def: $vgpr131
-; GFX11-NEXT:    ; implicit-def: $vgpr116
-; GFX11-NEXT:    ; implicit-def: $vgpr134
-; GFX11-NEXT:    ; implicit-def: $vgpr118
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr115
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr128
-; GFX11-NEXT:    ; implicit-def: $vgpr113
-; GFX11-NEXT:    ; implicit-def: $vgpr132
-; GFX11-NEXT:    ; implicit-def: $vgpr100
-; GFX11-NEXT:    ; implicit-def: $vgpr161
-; GFX11-NEXT:    ; implicit-def: $vgpr160
-; GFX11-NEXT:    ; implicit-def: $vgpr176
-; GFX11-NEXT:    ; implicit-def: $vgpr167
-; GFX11-NEXT:    ; implicit-def: $vgpr181
-; GFX11-NEXT:    ; implicit-def: $vgpr150
-; GFX11-NEXT:    ; implicit-def: $vgpr41
-; GFX11-NEXT:    ; implicit-def: $vgpr40
-; GFX11-NEXT:    ; implicit-def: $vgpr43
-; GFX11-NEXT:    ; implicit-def: $vgpr182
-; GFX11-NEXT:    ; implicit-def: $vgpr46
-; GFX11-NEXT:    ; implicit-def: $vgpr45
-; GFX11-NEXT:    ; implicit-def: $vgpr57
-; GFX11-NEXT:    ; implicit-def: $vgpr56
-; GFX11-NEXT:    ; implicit-def: $vgpr58
-; GFX11-NEXT:    ; implicit-def: $vgpr44
-; GFX11-NEXT:    ; implicit-def: $vgpr60
-; GFX11-NEXT:    ; implicit-def: $vgpr59
-; GFX11-NEXT:    ; implicit-def: $vgpr62
-; GFX11-NEXT:    ; implicit-def: $vgpr47
-; GFX11-NEXT:    ; implicit-def: $vgpr72
-; GFX11-NEXT:    ; implicit-def: $vgpr63
-; GFX11-NEXT:    ; implicit-def: $vgpr74
-; GFX11-NEXT:    ; implicit-def: $vgpr73
-; GFX11-NEXT:    ; implicit-def: $vgpr75
-; GFX11-NEXT:    ; implicit-def: $vgpr61
-; GFX11-NEXT:    ; implicit-def: $vgpr78
-; GFX11-NEXT:    ; implicit-def: $vgpr77
-; GFX11-NEXT:    ; implicit-def: $vgpr79
-; GFX11-NEXT:    ; implicit-def: $vgpr76
-; GFX11-NEXT:    ; implicit-def: $vgpr90
-; GFX11-NEXT:    ; implicit-def: $vgpr89
-; GFX11-NEXT:    ; implicit-def: $vgpr92
-; GFX11-NEXT:    ; implicit-def: $vgpr91
-; GFX11-NEXT:    ; implicit-def: $vgpr93
-; GFX11-NEXT:    ; implicit-def: $vgpr88
-; GFX11-NEXT:    ; implicit-def: $vgpr104
-; GFX11-NEXT:    ; implicit-def: $vgpr95
-; GFX11-NEXT:    ; implicit-def: $vgpr105
-; GFX11-NEXT:    ; implicit-def: $vgpr94
-; GFX11-NEXT:    ; implicit-def: $vgpr108
-; GFX11-NEXT:    ; implicit-def: $vgpr107
-; GFX11-NEXT:    ; implicit-def: $vgpr110
-; GFX11-NEXT:    ; implicit-def: $vgpr109
-; GFX11-NEXT:    ; implicit-def: $vgpr111
-; GFX11-NEXT:    ; implicit-def: $vgpr106
-; GFX11-NEXT:    ; implicit-def: $vgpr122
-; GFX11-NEXT:    ; implicit-def: $vgpr121
-; GFX11-NEXT:    ; implicit-def: $vgpr123
-; GFX11-NEXT:    ; implicit-def: $vgpr120
-; GFX11-NEXT:    ; implicit-def: $vgpr125
-; GFX11-NEXT:    ; implicit-def: $vgpr124
-; GFX11-NEXT:    ; implicit-def: $vgpr126
-; GFX11-NEXT:    ; implicit-def: $vgpr127
-; GFX11-NEXT:  .LBB46_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB46_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v134, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v118, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v131, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v116, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v129, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_add_nc_u16 v35, v35, 3
-; GFX11-NEXT:    v_or_b32_e32 v0, v126, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v127, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v125, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v124, v3
-; GFX11-NEXT:    v_add_nc_u16 v33, v33, 3
-; GFX11-NEXT:    v_add_nc_u16 v31, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v98, 3
-; GFX11-NEXT:    v_add_nc_u16 v116, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v30, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v98, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v1, v112, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v4
-; GFX11-NEXT:    v_add_nc_u16 v3, v99, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v4, v103, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v123, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v0, v120, v0
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v1, v122, v1
-; GFX11-NEXT:    v_add_nc_u16 v29, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v121, v3
-; GFX11-NEXT:    v_add_nc_u16 v99, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v111, v4
-; GFX11-NEXT:    v_add_nc_u16 v28, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v81, 3
-; GFX11-NEXT:    v_add_nc_u16 v81, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v101, 3
-; GFX11-NEXT:    v_add_nc_u16 v27, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v86, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v3, v97, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v4, v83, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v106, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v110, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v0, v109, v0
-; GFX11-NEXT:    v_add_nc_u16 v83, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v108, v3
-; GFX11-NEXT:    v_add_nc_u16 v26, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v107, v4
-; GFX11-NEXT:    v_add_nc_u16 v86, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v85, 3
-; GFX11-NEXT:    v_add_nc_u16 v25, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v67, 3
-; GFX11-NEXT:    v_add_nc_u16 v67, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v80, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v3, v68, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v4, v69, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_or_b32_e32 v0, v105, v0
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v1, v94, v1
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v2, v104, v2
-; GFX11-NEXT:    v_add_nc_u16 v24, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v95, v3
-; GFX11-NEXT:    v_add_nc_u16 v68, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v93, v4
-; GFX11-NEXT:    v_add_nc_u16 v23, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v64, 3
-; GFX11-NEXT:    v_add_nc_u16 v64, 0x300, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(26)
-; GFX11-NEXT:    v_add_nc_u16 v0, v42, 3
-; GFX11-NEXT:    v_add_nc_u16 v22, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v65, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(24)
-; GFX11-NEXT:    v_add_nc_u16 v3, v183, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v4, v180, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v88, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v0, v92, v0
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v1, v91, v1
-; GFX11-NEXT:    v_add_nc_u16 v65, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v90, v3
-; GFX11-NEXT:    v_add_nc_u16 v21, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v89, v4
-; GFX11-NEXT:    v_add_nc_u16 v69, 0x300, v1
-; GFX11-NEXT:    s_waitcnt vmcnt(22)
-; GFX11-NEXT:    v_add_nc_u16 v1, v179, 3
-; GFX11-NEXT:    v_add_nc_u16 v20, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v165, 3
-; GFX11-NEXT:    v_add_nc_u16 v80, 0x300, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(20)
-; GFX11-NEXT:    v_add_nc_u16 v0, v177, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v3, v163, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(18)
-; GFX11-NEXT:    v_add_nc_u16 v4, v166, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v79, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v76, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v0, v78, v0
-; GFX11-NEXT:    v_add_nc_u16 v19, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v77, v3
-; GFX11-NEXT:    v_add_nc_u16 v85, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v75, v4
-; GFX11-NEXT:    v_add_nc_u16 v18, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v145, 3
-; GFX11-NEXT:    v_add_nc_u16 v97, 0x300, v1
-; GFX11-NEXT:    s_waitcnt vmcnt(16)
-; GFX11-NEXT:    v_add_nc_u16 v1, v151, 3
-; GFX11-NEXT:    v_add_nc_u16 v17, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v148, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(14)
-; GFX11-NEXT:    v_add_nc_u16 v3, v178, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v4, v164, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_or_b32_e32 v0, v61, v0
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v1, v74, v1
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v2, v73, v2
-; GFX11-NEXT:    v_add_nc_u16 v101, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v72, v3
-; GFX11-NEXT:    v_add_nc_u16 v16, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v63, v4
-; GFX11-NEXT:    v_add_nc_u16 v103, 0x300, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(12)
-; GFX11-NEXT:    v_add_nc_u16 v2, v162, 3
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v146, 3
-; GFX11-NEXT:    v_add_nc_u16 v112, 0x300, v1
-; GFX11-NEXT:    s_waitcnt vmcnt(10)
-; GFX11-NEXT:    v_add_nc_u16 v1, v149, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, v144, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(8)
-; GFX11-NEXT:    v_add_nc_u16 v4, v147, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v62, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v0, v47, v0
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v1, v60, v1
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v59, v3
-; GFX11-NEXT:    v_add_nc_u16 v118, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v58, v4
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v119, 3
-; GFX11-NEXT:    v_add_nc_u16 v119, 0x300, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(6)
-; GFX11-NEXT:    v_add_nc_u16 v2, v135, 3
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v130, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    s_waitcnt vmcnt(4)
-; GFX11-NEXT:    v_add_nc_u16 v3, v133, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v4, v117, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v44, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v57, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v0, v56, v0
-; GFX11-NEXT:    v_add_nc_u16 v117, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v46, v3
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v45, v4
-; GFX11-NEXT:    v_add_nc_u16 v129, 0x300, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(2)
-; GFX11-NEXT:    v_add_nc_u16 v0, v114, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v96, 3
-; GFX11-NEXT:    v_add_nc_u16 v96, 0x300, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_nc_u16 v2, v102, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v3, v87, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v4, v55, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_or_b32_e32 v0, v43, v0
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v1, v182, v1
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v2, v41, v2
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v40, v3
-; GFX11-NEXT:    v_add_nc_u16 v55, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v181, v4
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v37, 3
-; GFX11-NEXT:    v_add_nc_u16 v37, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v54, 3
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v52, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, v53, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v4, v50, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v150, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v0, v176, v0
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v1, v167, v1
-; GFX11-NEXT:    v_add_nc_u16 v50, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v161, v3
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v160, v4
-; GFX11-NEXT:    v_add_nc_u16 v52, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v51, 3
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v49, 3
-; GFX11-NEXT:    v_add_nc_u16 v49, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v48, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v3, v34, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v4, v36, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v132, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v128, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v0, v115, v0
-; GFX11-NEXT:    v_add_nc_u16 v34, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v100, v3
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v113, v4
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v39, 3
-; GFX11-NEXT:    v_add_nc_u16 v36, v38, 3
-; GFX11-NEXT:    v_add_nc_u16 v32, v32, 3
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xff, v35
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v36, 0xff, v36
-; GFX11-NEXT:    v_and_b32_e32 v32, 0xff, v32
-; GFX11-NEXT:    v_or_b32_e32 v35, v71, v35
-; GFX11-NEXT:    v_or_b32_e32 v33, v82, v33
-; GFX11-NEXT:    v_or_b32_e32 v0, v84, v0
-; GFX11-NEXT:    v_or_b32_e32 v36, v70, v36
-; GFX11-NEXT:    v_or_b32_e32 v32, v66, v32
-; GFX11-NEXT:    v_add_nc_u16 v35, 0x300, v35
-; GFX11-NEXT:    v_add_nc_u16 v33, 0x300, v33
-; GFX11-NEXT:    v_add_nc_u16 v38, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v36
-; GFX11-NEXT:    v_add_nc_u16 v32, 0x300, v32
-; GFX11-NEXT:    v_add_nc_u16 v36, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v39, 0x300, v1
-; GFX11-NEXT:    v_perm_b32 v1, v33, v38, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v0, v35, v0, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v2, v32, v4, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v3, v36, v3, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v4, v39, v34, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v5, v49, v5, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v6, v52, v6, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v7, v50, v7, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v8, v37, v8, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v9, v55, v9, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v10, v96, v10, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v11, v129, v11, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v12, v117, v12, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v13, v119, v13, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v14, v118, v14, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v15, v112, v15, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v16, v103, v16, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v17, v101, v17, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v18, v97, v18, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v19, v85, v19, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v20, v80, v20, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v21, v69, v21, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v22, v65, v22, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v23, v64, v23, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v24, v68, v24, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v25, v67, v25, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v26, v86, v26, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v27, v83, v27, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v28, v81, v28, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v29, v99, v29, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v30, v98, v30, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v31, v116, v31, 0x5040100
-; GFX11-NEXT:  .LBB46_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_b32 v127, off, s32 offset:392
-; GFX11-NEXT:    scratch_load_b32 v126, off, s32 offset:396
-; GFX11-NEXT:    scratch_load_b32 v125, off, s32 offset:400
-; GFX11-NEXT:    scratch_load_b32 v124, off, s32 offset:404
-; GFX11-NEXT:    scratch_load_b32 v123, off, s32 offset:408
-; GFX11-NEXT:    scratch_load_b32 v122, off, s32 offset:412
-; GFX11-NEXT:    scratch_load_b32 v121, off, s32 offset:416
-; GFX11-NEXT:    scratch_load_b32 v120, off, s32 offset:420
-; GFX11-NEXT:    scratch_load_b32 v111, off, s32 offset:424
-; GFX11-NEXT:    scratch_load_b32 v110, off, s32 offset:428
-; GFX11-NEXT:    scratch_load_b32 v109, off, s32 offset:432
-; GFX11-NEXT:    scratch_load_b32 v108, off, s32 offset:436
-; GFX11-NEXT:    scratch_load_b32 v107, off, s32 offset:440
-; GFX11-NEXT:    scratch_load_b32 v106, off, s32 offset:444
-; GFX11-NEXT:    scratch_load_b32 v105, off, s32 offset:448
-; GFX11-NEXT:    scratch_load_b32 v104, off, s32 offset:452
-; GFX11-NEXT:    scratch_load_b32 v95, off, s32 offset:456
-; GFX11-NEXT:    scratch_load_b32 v94, off, s32 offset:460
-; GFX11-NEXT:    scratch_load_b32 v93, off, s32 offset:464
-; GFX11-NEXT:    scratch_load_b32 v92, off, s32 offset:468
-; GFX11-NEXT:    scratch_load_b32 v91, off, s32 offset:472
-; GFX11-NEXT:    scratch_load_b32 v90, off, s32 offset:476
-; GFX11-NEXT:    scratch_load_b32 v89, off, s32 offset:480
-; GFX11-NEXT:    scratch_load_b32 v88, off, s32 offset:484
-; GFX11-NEXT:    scratch_load_b32 v79, off, s32 offset:488
-; GFX11-NEXT:    scratch_load_b32 v78, off, s32 offset:492
-; GFX11-NEXT:    scratch_load_b32 v77, off, s32 offset:496
-; GFX11-NEXT:    scratch_load_b32 v76, off, s32 offset:500
-; GFX11-NEXT:    scratch_load_b32 v75, off, s32 offset:504
-; GFX11-NEXT:    scratch_load_b32 v74, off, s32 offset:508
-; GFX11-NEXT:    scratch_load_b32 v73, off, s32 offset:512
-; GFX11-NEXT:    scratch_load_b32 v72, off, s32 offset:516
-; GFX11-NEXT:    s_clause 0xf
-; GFX11-NEXT:    scratch_load_b32 v63, off, s32 offset:520
-; GFX11-NEXT:    scratch_load_b32 v62, off, s32 offset:524
-; GFX11-NEXT:    scratch_load_b32 v61, off, s32 offset:528
-; GFX11-NEXT:    scratch_load_b32 v60, off, s32 offset:532
-; GFX11-NEXT:    scratch_load_b32 v59, off, s32 offset:536
-; GFX11-NEXT:    scratch_load_b32 v58, off, s32 offset:540
-; GFX11-NEXT:    scratch_load_b32 v57, off, s32 offset:544
-; GFX11-NEXT:    scratch_load_b32 v56, off, s32 offset:548
-; GFX11-NEXT:    scratch_load_b32 v47, off, s32 offset:552
-; GFX11-NEXT:    scratch_load_b32 v46, off, s32 offset:556
-; GFX11-NEXT:    scratch_load_b32 v45, off, s32 offset:560
-; GFX11-NEXT:    scratch_load_b32 v44, off, s32 offset:564
-; GFX11-NEXT:    scratch_load_b32 v43, off, s32 offset:568
-; GFX11-NEXT:    scratch_load_b32 v42, off, s32 offset:572
-; GFX11-NEXT:    scratch_load_b32 v41, off, s32 offset:576
-; GFX11-NEXT:    scratch_load_b32 v40, off, s32 offset:580
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v128i8_to_v64f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32 offset:384
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v39, off, s32 offset:380
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v31, off, s32 offset:376
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v50, off, s32 offset:372
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v150, off, s32 offset:368
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v39, off, s32 offset:364
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v150, off, s32 offset:360
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v50, off, s32 offset:356
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v147, off, s32 offset:352
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v37, off, s32 offset:348
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v149, off, s32 offset:344
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v49, off, s32 offset:340
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v149, off, s32 offset:336
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v38, off, s32 offset:332
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v148, off, s32 offset:328
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v48, off, s32 offset:324
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v145, off, s32 offset:320
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v34, off, s32 offset:316
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v148, off, s32 offset:312
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v48, off, s32 offset:308
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v147, off, s32 offset:304
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v36, off, s32 offset:300
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v146, off, s32 offset:296
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v38, off, s32 offset:292
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v146, off, s32 offset:288
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v36, off, s32 offset:284
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v145, off, s32 offset:280
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v37, off, s32 offset:276
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v134, off, s32 offset:272
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v33, off, s32 offset:268
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v144, off, s32 offset:264
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v35, off, s32 offset:260
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v144, off, s32 offset:256
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v33, off, s32 offset:252
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v135, off, s32 offset:248
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v35, off, s32 offset:244
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v132, off, s32 offset:240
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v32, off, s32 offset:236
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v135, off, s32 offset:232
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v34, off, s32 offset:228
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v134, off, s32 offset:224
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v32, off, s32 offset:220
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v133, off, s32 offset:216
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v160, off, s32 offset:388
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v101, off, s32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v103, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v113, off, s32 offset:16
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v113, off, s32 offset:24
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v114, off, s32 offset:32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v114, off, s32 offset:40
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v115, off, s32 offset:48
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v116, off, s32 offset:56
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v116, off, s32 offset:64
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v117, off, s32 offset:72
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v117, off, s32 offset:80
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v118, off, s32 offset:88
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v118, off, s32 offset:96
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v119, off, s32 offset:104
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v119, off, s32 offset:112
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v128, off, s32 offset:120
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v128, off, s32 offset:128
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v129, off, s32 offset:136
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v129, off, s32 offset:144
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v130, off, s32 offset:152
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v130, off, s32 offset:160
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v131, off, s32 offset:168
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v131, off, s32 offset:176
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v132, off, s32 offset:184
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v133, off, s32 offset:192
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v151, off, s32 offset:200
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v151, off, s32 offset:208
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v100, off, s32 offset:212
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v98, off, s32 offset:204
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v100, off, s32 offset:196
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v85, off, s32 offset:188
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v97, off, s32 offset:180
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v86, off, s32 offset:172
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v96, off, s32 offset:164
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v71, off, s32 offset:156
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v87, off, s32 offset:148
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v80, off, s32 offset:140
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v84, off, s32 offset:132
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v86, off, s32 offset:124
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v96, off, s32 offset:116
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v80, off, s32 offset:108
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v85, off, s32 offset:100
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v82, off, s32 offset:92
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v84, off, s32 offset:84
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v69, off, s32 offset:76
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v83, off, s32 offset:68
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v69, off, s32 offset:60
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v71, off, s32 offset:52
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v68, off, s32 offset:44
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v70, off, s32 offset:36
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v66, off, s32 offset:28
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v68, off, s32 offset:20
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v66, off, s32 offset:12
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v67, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v54.l, v30.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v67.l, v28.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.h, v26.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.h, v24.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v22.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.l, v20.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v52.l, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.h, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.h, v14.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v49.h, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v54.h, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v51.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.l, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v51.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v52.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v81.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v81.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v82.h, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v83.l, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v97.h, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v70.l, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v98.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v99.l, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v99.h, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v87.l, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v101.h, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v102.l, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v102.h, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v103.l, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v112.l, 8, v29.l
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(62)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v150.h, 8, v150.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v150.l, 8, v150.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v147.h, 8, v147.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v149.h, 8, v149.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v149.l, 8, v149.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v148.h, 8, v148.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v145.l, 8, v145.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v148.l, 8, v148.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v147.l, 8, v147.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v146.h, 8, v146.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v146.l, 8, v146.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v145.h, 8, v145.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v134.h, 8, v134.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v144.h, 8, v144.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v144.l, 8, v144.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v135.h, 8, v135.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(61)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v132.l, 8, v132.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(59)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v135.l, 8, v135.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(57)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v134.l, 8, v134.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(55)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v133.h, 8, v133.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(54)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v160
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(53)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v101.l, 8, v101.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(52)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v112.h, 8, v103.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(51)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v113.l, 8, v113.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(50)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v113.h, 8, v113.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(49)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v103.h, 8, v114.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(48)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v115.l, 8, v114.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(47)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v115.h, 8, v115.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(46)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v116.l, 8, v116.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(45)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v116.h, 8, v116.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(44)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v117.l, 8, v117.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(43)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v114.l, 8, v117.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(42)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v118.l, 8, v118.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(41)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v118.h, 8, v118.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(40)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v119.l, 8, v119.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(39)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v114.h, 8, v119.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(38)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v119.h, 8, v128.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(37)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v128.l, 8, v128.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(36)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v128.h, 8, v129.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(35)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v129.l, 8, v129.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(34)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v130.l, 8, v130.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v117.h, 8, v130.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(32)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v130.h, 8, v131.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v131.l, 8, v131.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(30)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v131.h, 8, v132.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(29)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v129.h, 8, v133.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(28)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v132.h, 8, v151.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(27)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v133.l, 8, v151.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v151.l, 8, v31.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v151.h, 8, v31.l
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB46_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB46_4
+; GFX11-TRUE16-NEXT:  .LBB46_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB46_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v52.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v51.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v53.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v51.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v54.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v49.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v55.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v53.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v55.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v52.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v65.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v64.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v65.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v64.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v67.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v54.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v67.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v66.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v68.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.h, 0xff, v66.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v70.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.h, 0xff, v68.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v71.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.h, 0xff, v69.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v83.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v69.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v84.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v82.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v85.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.h, 0xff, v80.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.l, 0xff, v96.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.h, 0xff, v86.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v16.l, 0xff, v84.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v16.h, 0xff, v80.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v87.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.h, 0xff, v71.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v96.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.h, 0xff, v86.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v97.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.h, 0xff, v85.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v20.l, 0xff, v100.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v20.h, 0xff, v98.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v21.l, 0xff, v100.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v21.h, 0xff, v32.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v34.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.h, 0xff, v32.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v35.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.h, 0xff, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v35.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.h, 0xff, v33.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v25.l, 0xff, v37.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v25.h, 0xff, v36.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v26.l, 0xff, v38.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v26.h, 0xff, v36.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.l, 0xff, v48.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.h, 0xff, v34.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.l, 0xff, v48.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.h, 0xff, v38.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v29.l, 0xff, v49.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v29.h, 0xff, v37.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v30.l, 0xff, v50.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v30.h, 0xff, v39.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v31.l, 0xff, v50.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v31.h, 0xff, v39.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v81.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v81.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v82.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v1.h, v83.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v97.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v2.h, v70.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v98.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v3.h, v99.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v99.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.h, v4.h, v87.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v101.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.h, v5.h, v102.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v102.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v6.h, v103.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v112.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v7.h, v101.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v112.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.h, v8.h, v113.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v113.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.h, v9.h, v103.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v115.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.h, v10.h, v115.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v116.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.h, v11.h, v116.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v117.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.h, v12.h, v114.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v118.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.h, v13.h, v118.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v119.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.h, v14.h, v114.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v15.l, v119.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.h, v15.h, v128.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v16.l, v128.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.h, v16.h, v129.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v17.l, v130.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.h, v17.h, v117.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v18.l, v130.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.h, v18.h, v131.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v19.l, v131.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.h, v19.h, v129.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v20.l, v132.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.h, v20.h, v133.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v21.l, v21.l, v133.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v21.h, v21.h, v134.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v22.l, v135.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.h, v22.h, v132.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v23.l, v135.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.h, v23.h, v144.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v24.l, v144.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.h, v24.h, v134.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v25.l, v25.l, v145.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v25.h, v25.h, v146.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v26.l, v26.l, v146.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v26.h, v26.h, v147.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.l, v27.l, v148.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.h, v27.h, v145.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.l, v28.l, v148.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.h, v28.h, v149.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v29.l, v29.l, v149.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v29.h, v29.h, v147.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v30.l, v30.l, v150.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v30.h, v30.h, v150.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v31.l, v31.l, v151.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v31.h, v31.h, v151.h
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr67_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr68_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr71_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr85_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr86_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr97_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr100_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr83_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr70_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr99_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr103_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr101_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr112_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr113_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr115_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr116_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr116_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr117_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr114_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr118_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr118_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr119_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr114_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr128_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr128_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr130_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr130_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr131_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr131_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr129_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr132_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr133_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr133_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr134_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr132_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr135_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr144_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr144_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr134_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr145_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr146_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr147_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr148_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr145_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr148_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr149_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr147_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr150_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr150_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr151_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB46_2
+; GFX11-TRUE16-NEXT:  .LBB46_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v50.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v39.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v50.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v39.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v48.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v151.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v151.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v150.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v150.h, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v148.l, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v31.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v31.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v30.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v30.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v49.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v37.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v48.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v38.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v36.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v149.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v147.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v148.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v149.l, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v29.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v29.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v34.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v38.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v36.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v37.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v146.l, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v25.h, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v145.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v146.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v147.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v145.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v34.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v26.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v26.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v25.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v35.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v33.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v35.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v33.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v135.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v144.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v134.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v135.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v144.l, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v24.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v24.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v32.l, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(26)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v100.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v32.h, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(24)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v100.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v98.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v132.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v133.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v134.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v132.h, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v133.l, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v21.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v21.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v20.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(22)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v97.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v85.h, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(20)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v96.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v86.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v20.h, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(18)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v87.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v131.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v129.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v130.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v131.l, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v19.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v19.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v71.h, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(16)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v84.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v80.h, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(14)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v96.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v130.l, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v117.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v128.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v129.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v119.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v86.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v16.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v16.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(12)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v85.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v80.l, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(10)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v84.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v82.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v128.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v119.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v114.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v118.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v118.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.h, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(8)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v83.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v69.l, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(6)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v71.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v69.h, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v70.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v117.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v114.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v116.l, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v116.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v115.l, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v68.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v68.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v66.l, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v67.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v66.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v115.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v113.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v103.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v112.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v113.l, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.h, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v67.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v54.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v65.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v64.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v65.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v112.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v101.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v102.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v103.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v101.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v64.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v55.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v52.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v55.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v53.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v102.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v99.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v87.l, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v98.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v99.l, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v54.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v49.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v53.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v51.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v52.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v51.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v97.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v70.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v82.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v32.l, v83.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v32.h, v81.l, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v33.l, v81.h, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, 0x300, v32.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v32.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, 0x300, v33.l
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v128i8_to_v64f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s32 offset:580
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v41, s32 offset:576
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v42, s32 offset:572
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v43, s32 offset:568
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v44, s32 offset:564
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v45, s32 offset:560
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v46, s32 offset:556
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v47, s32 offset:552
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v56, s32 offset:548
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v57, s32 offset:544
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v58, s32 offset:540
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v59, s32 offset:536
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v60, s32 offset:532
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v61, s32 offset:528
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v62, s32 offset:524
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v63, s32 offset:520
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v72, s32 offset:516
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v73, s32 offset:512
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v74, s32 offset:508
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v75, s32 offset:504
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v76, s32 offset:500
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v77, s32 offset:496
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v78, s32 offset:492
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v79, s32 offset:488
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v88, s32 offset:484
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v89, s32 offset:480
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v90, s32 offset:476
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v91, s32 offset:472
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v92, s32 offset:468
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v93, s32 offset:464
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v94, s32 offset:460
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v95, s32 offset:456
+; GFX11-FAKE16-NEXT:    s_clause 0xf
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v104, s32 offset:452
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v105, s32 offset:448
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v106, s32 offset:444
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v107, s32 offset:440
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v108, s32 offset:436
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v109, s32 offset:432
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v110, s32 offset:428
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v111, s32 offset:424
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v120, s32 offset:420
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v121, s32 offset:416
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v122, s32 offset:412
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v123, s32 offset:408
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v124, s32 offset:404
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v125, s32 offset:400
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v126, s32 offset:396
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v127, s32 offset:392
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v37, v30 :: v_dual_mov_b32 v54, v24
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v55, v28 :: v_dual_mov_b32 v52, v26
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v50, v22 :: v_dual_mov_b32 v53, v20
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v34, v18 :: v_dual_mov_b32 v51, v16
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v36, v14 :: v_dual_mov_b32 v49, v12
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v32, v10 :: v_dual_mov_b32 v39, v4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v48, v8 :: v_dual_mov_b32 v33, v6
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v35, v2 :: v_dual_mov_b32 v38, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v0, off, s32 offset:384
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v118, off, s32 offset:380
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32 offset:376
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v134, off, s32 offset:372
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v4, off, s32 offset:368
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v116, off, s32 offset:364
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v6, off, s32 offset:360
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v131, off, s32 offset:356
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v8, off, s32 offset:352
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v98, off, s32 offset:348
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v10, off, s32 offset:344
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v129, off, s32 offset:340
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v12, off, s32 offset:336
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v99, off, s32 offset:332
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v14, off, s32 offset:328
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v112, off, s32 offset:324
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v16, off, s32 offset:320
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v81, off, s32 offset:316
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v18, off, s32 offset:312
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v103, off, s32 offset:308
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v20, off, s32 offset:304
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v86, off, s32 offset:300
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v22, off, s32 offset:296
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v101, off, s32 offset:292
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v24, off, s32 offset:288
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v83, off, s32 offset:284
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v26, off, s32 offset:280
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v97, off, s32 offset:276
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v28, off, s32 offset:272
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v67, off, s32 offset:268
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v30, off, s32 offset:264
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v85, off, s32 offset:260
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v31, off, s32 offset:256
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v68, off, s32 offset:252
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v94, off, s32 offset:248
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v80, off, s32 offset:244
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v88, off, s32 offset:240
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v64, off, s32 offset:236
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v93, off, s32 offset:232
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v69, off, s32 offset:228
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v91, off, s32 offset:224
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v65, off, s32 offset:220
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v92, off, s32 offset:216
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v150, off, s32 offset:388
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v182, off, s32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v40, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v43, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v44, off, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v45, off, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v46, off, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v47, off, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v56, off, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v58, off, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v59, off, s32 offset:72
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v60, off, s32 offset:80
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v61, off, s32 offset:88
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v62, off, s32 offset:96
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v63, off, s32 offset:104
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v72, off, s32 offset:112
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v73, off, s32 offset:120
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v74, off, s32 offset:128
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v75, off, s32 offset:136
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v76, off, s32 offset:144
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v77, off, s32 offset:152
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v78, off, s32 offset:160
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v79, off, s32 offset:168
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v89, off, s32 offset:176
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v90, off, s32 offset:184
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v95, off, s32 offset:192
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v104, off, s32 offset:200
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v105, off, s32 offset:208
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v42, off, s32 offset:212
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v180, off, s32 offset:204
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v183, off, s32 offset:196
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v165, off, s32 offset:188
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v179, off, s32 offset:180
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v163, off, s32 offset:172
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v177, off, s32 offset:164
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v145, off, s32 offset:156
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v166, off, s32 offset:148
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v148, off, s32 offset:140
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v151, off, s32 offset:132
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v164, off, s32 offset:124
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v178, off, s32 offset:116
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v146, off, s32 offset:108
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v162, off, s32 offset:100
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v144, off, s32 offset:92
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v149, off, s32 offset:84
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v119, off, s32 offset:76
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v147, off, s32 offset:68
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v130, off, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v135, off, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v117, off, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v133, off, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v96, off, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v114, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v87, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v102, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v70, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v71, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v84, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v82, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v115, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v66, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v128, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v113, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v132, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v100, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v161, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v160, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v176, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v167, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v181, 8, v29
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(62)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v127, 8, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v126, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v124, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v125, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v120, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v123, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v121, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v122, 8, v14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v106, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v111, 8, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v109, 8, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v110, 8, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v107, 8, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v108, 8, v26
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(61)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v88, 8, v88
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(59)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v93, 8, v93
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(57)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v91, 8, v91
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(55)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v92, 8, v92
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(54)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v150
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(53)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v150, 8, v182
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(52)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v41, 8, v40
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(51)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v40, 8, v43
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(50)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v43, 8, v44
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(49)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v182, 8, v45
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(48)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v46, 8, v46
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(47)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v45, 8, v47
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(46)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v57, 8, v56
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(45)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v56, 8, v58
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(44)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v58, 8, v59
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(43)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v44, 8, v60
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(42)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v60, 8, v61
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(41)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v59, 8, v62
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(40)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v62, 8, v63
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(39)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v47, 8, v72
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(38)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v72, 8, v73
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(37)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v63, 8, v74
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(36)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v74, 8, v75
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(35)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v73, 8, v76
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(34)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v75, 8, v77
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v61, 8, v78
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(32)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v78, 8, v79
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v77, 8, v89
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(30)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v79, 8, v90
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(29)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v76, 8, v95
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(28)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v90, 8, v104
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(27)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v89, 8, v105
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v104, 8, v94
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v95, 8, v31
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v105, 8, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v94, 8, v28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB46_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v38
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v48
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v70
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v71
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v84
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v82
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v51
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v49
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v53
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v50
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v52
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v115
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v66
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v128
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v113
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v132
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v100
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v161
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v160
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v176
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v167
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v4, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v5, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v7, v6, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v9, v8, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v11, v10, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v37
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v102
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v87
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v114
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v96
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v133
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v117
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v135
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v130
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v181
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v150
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v41
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v40
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v43
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v182
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v46
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v45
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v57
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v56
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v8, v7, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v10, v9, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v12, v11, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v14, v13, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v16, v15, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v147
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v119
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v149
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v144
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v162
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v146
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v178
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v164
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v151
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v148
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v58
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v44
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v60
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v59
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v62
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v17, v47
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v18, v72
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v19, v63
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v74
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v21, v73
+; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v13, v12, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v15, v14, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v17, v16, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v19, v18, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v16, v21, v20, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v166
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v145
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v177
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v163
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v179
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v165
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v183
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v180
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v42
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v17, v75
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v18, v61
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v19, v78
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v77
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v21, v79
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v22, v76
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v23, v90
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v24, v89
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v92
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v26, v91
+; GFX11-FAKE16-NEXT:    v_perm_b32 v17, v18, v17, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v18, v20, v19, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v19, v22, v21, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v20, v24, v23, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v21, v26, v25, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v69
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v64
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v68
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v67
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v97
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v83
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v101
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v86
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v22, v93
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v23, v88
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v24, v104
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v95
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v26, v105
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v27, v94
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v28, v108
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v29, v107
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v30, v110
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v31, v109
+; GFX11-FAKE16-NEXT:    v_perm_b32 v22, v23, v22, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v23, v25, v24, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v24, v27, v26, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v25, v29, v28, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v26, v31, v30, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v103
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v81
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v112
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v99
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v129
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v32, 0xff, v98
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xff, v131
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v34, 0xff, v116
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xff, v134
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v36, 0xff, v118
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v27, v111
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v28, v106
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v29, v122
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v30, v121
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v31, v123
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v32, v32, v120
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v33, v33, v125
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v34, v34, v124
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, v35, v126
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, v36, v127
+; GFX11-FAKE16-NEXT:    v_perm_b32 v27, v28, v27, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v28, v30, v29, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v29, v32, v31, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v30, v34, v33, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v31, v36, v35, 0x5040100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr135
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr147
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr149
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr144
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr162
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr178
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr164
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr151
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr148
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr166
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr177
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr163
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr179
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr165
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr183
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr180
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr42
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr161
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr160
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr176
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr167
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr181
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr150
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr41
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr40
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr43
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr182
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr46
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr45
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr57
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr56
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr58
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr44
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr60
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr59
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr62
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr47
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr72
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr63
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr74
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr73
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr75
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr61
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr78
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr77
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr79
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr76
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr90
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr89
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr92
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr91
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr93
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr88
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr104
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr95
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr105
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr94
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr108
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr107
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr110
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr109
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr111
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr106
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr122
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr121
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr123
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr120
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr125
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr124
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr126
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr127
+; GFX11-FAKE16-NEXT:  .LBB46_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB46_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v134, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v118, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v131, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v116, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v129, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v35, v35, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v126, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v127, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v125, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v124, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v33, v33, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v31, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v98, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v116, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v30, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v98, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v112, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v99, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v103, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v123, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v120, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v122, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v29, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v121, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v99, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v111, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v28, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v81, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v81, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v101, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v27, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v86, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v97, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v83, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v106, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v110, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v109, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v83, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v108, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v26, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v107, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v86, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v85, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v25, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v67, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v67, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v80, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v68, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v69, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v105, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v94, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v104, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v24, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v95, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v68, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v93, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v23, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v64, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v64, 0x300, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(26)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v42, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v65, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(24)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v183, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v180, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v88, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v92, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v91, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v65, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v90, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v89, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v69, 0x300, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(22)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v179, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v165, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v80, 0x300, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(20)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v177, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v163, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(18)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v166, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v79, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v76, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v78, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v77, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v85, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v75, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v145, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v97, 0x300, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(16)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v151, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v148, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(14)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v178, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v164, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v61, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v74, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v73, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v101, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v72, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v63, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v103, 0x300, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(12)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v162, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v146, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v112, 0x300, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(10)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v149, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v144, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(8)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v147, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v62, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v47, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v60, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v59, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v118, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v58, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v119, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v119, 0x300, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(6)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v135, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v130, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(4)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v133, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v117, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v44, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v57, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v56, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v117, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v46, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v45, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v129, 0x300, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v114, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v96, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v96, 0x300, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v102, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v87, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v55, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v43, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v182, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v41, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v40, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v55, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v181, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v37, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v37, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v54, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v52, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v53, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v50, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v150, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v176, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v167, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v50, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v161, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v160, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v52, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v51, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v49, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v49, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v48, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v34, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v36, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v132, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v128, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v115, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v34, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v100, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v113, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v39, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v36, v38, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v32, v32, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v36, 0xff, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v32, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, v71, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v33, v82, v33
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v84, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, v70, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v32, v66, v32
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v35, 0x300, v35
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v33, 0x300, v33
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v38, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v36
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v32, 0x300, v32
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v36, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v39, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v33, v38, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v35, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v32, v4, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v36, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v39, v34, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v49, v5, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v52, v6, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v50, v7, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v37, v8, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v55, v9, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v96, v10, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v129, v11, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v117, v12, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v119, v13, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v118, v14, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v112, v15, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v16, v103, v16, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v17, v101, v17, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v18, v97, v18, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v19, v85, v19, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v20, v80, v20, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v21, v69, v21, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v22, v65, v22, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v23, v64, v23, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v24, v68, v24, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v25, v67, v25, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v26, v86, v26, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v27, v83, v27, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v28, v81, v28, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v29, v99, v29, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v30, v98, v30, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v31, v116, v31, 0x5040100
+; GFX11-FAKE16-NEXT:  .LBB46_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v127, off, s32 offset:392
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v126, off, s32 offset:396
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v125, off, s32 offset:400
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v124, off, s32 offset:404
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v123, off, s32 offset:408
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v122, off, s32 offset:412
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v121, off, s32 offset:416
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v120, off, s32 offset:420
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v111, off, s32 offset:424
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v110, off, s32 offset:428
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v109, off, s32 offset:432
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v108, off, s32 offset:436
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v107, off, s32 offset:440
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v106, off, s32 offset:444
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v105, off, s32 offset:448
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v104, off, s32 offset:452
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v95, off, s32 offset:456
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v94, off, s32 offset:460
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v93, off, s32 offset:464
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v92, off, s32 offset:468
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v91, off, s32 offset:472
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v90, off, s32 offset:476
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v89, off, s32 offset:480
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v88, off, s32 offset:484
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v79, off, s32 offset:488
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v78, off, s32 offset:492
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v77, off, s32 offset:496
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v76, off, s32 offset:500
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v75, off, s32 offset:504
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v74, off, s32 offset:508
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v73, off, s32 offset:512
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v72, off, s32 offset:516
+; GFX11-FAKE16-NEXT:    s_clause 0xf
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v63, off, s32 offset:520
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v62, off, s32 offset:524
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v61, off, s32 offset:528
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v60, off, s32 offset:532
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v59, off, s32 offset:536
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v58, off, s32 offset:540
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v57, off, s32 offset:544
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v56, off, s32 offset:548
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v47, off, s32 offset:552
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v46, off, s32 offset:556
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v45, off, s32 offset:560
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v44, off, s32 offset:564
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v43, off, s32 offset:568
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v42, off, s32 offset:572
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v41, off, s32 offset:576
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s32 offset:580
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -86308,692 +97381,1256 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v64f16_to_v128i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x13
-; GFX11-NEXT:    scratch_store_b32 off, v40, s32 offset:88
-; GFX11-NEXT:    scratch_store_b32 off, v41, s32 offset:84
-; GFX11-NEXT:    scratch_store_b32 off, v42, s32 offset:80
-; GFX11-NEXT:    scratch_store_b32 off, v43, s32 offset:76
-; GFX11-NEXT:    scratch_store_b32 off, v44, s32 offset:72
-; GFX11-NEXT:    scratch_store_b32 off, v45, s32 offset:68
-; GFX11-NEXT:    scratch_store_b32 off, v46, s32 offset:64
-; GFX11-NEXT:    scratch_store_b32 off, v47, s32 offset:60
-; GFX11-NEXT:    scratch_store_b32 off, v56, s32 offset:56
-; GFX11-NEXT:    scratch_store_b32 off, v57, s32 offset:52
-; GFX11-NEXT:    scratch_store_b32 off, v58, s32 offset:48
-; GFX11-NEXT:    scratch_store_b32 off, v59, s32 offset:44
-; GFX11-NEXT:    scratch_store_b32 off, v60, s32 offset:40
-; GFX11-NEXT:    scratch_store_b32 off, v61, s32 offset:36
-; GFX11-NEXT:    scratch_store_b32 off, v62, s32 offset:32
-; GFX11-NEXT:    scratch_store_b32 off, v63, s32 offset:28
-; GFX11-NEXT:    scratch_store_b32 off, v72, s32 offset:24
-; GFX11-NEXT:    scratch_store_b32 off, v73, s32 offset:20
-; GFX11-NEXT:    scratch_store_b32 off, v74, s32 offset:16
-; GFX11-NEXT:    scratch_store_b32 off, v75, s32 offset:12
-; GFX11-NEXT:    s_clause 0x2
-; GFX11-NEXT:    scratch_load_b32 v33, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_b32 v32, off, s32 offset:4
-; GFX11-NEXT:    scratch_load_b32 v31, off, s32
-; GFX11-NEXT:    ; implicit-def: $vgpr74
-; GFX11-NEXT:    ; implicit-def: $vgpr72
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr63
-; GFX11-NEXT:    ; implicit-def: $vgpr62
-; GFX11-NEXT:    ; implicit-def: $vgpr60
-; GFX11-NEXT:    ; implicit-def: $vgpr57
-; GFX11-NEXT:    ; implicit-def: $vgpr47
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr45
-; GFX11-NEXT:    ; implicit-def: $vgpr43
-; GFX11-NEXT:    ; implicit-def: $vgpr42
-; GFX11-NEXT:    ; implicit-def: $vgpr183
-; GFX11-NEXT:    ; implicit-def: $vgpr181
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr179
-; GFX11-NEXT:    ; implicit-def: $vgpr177
-; GFX11-NEXT:    ; implicit-def: $vgpr167
-; GFX11-NEXT:    ; implicit-def: $vgpr165
-; GFX11-NEXT:    ; implicit-def: $vgpr164
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr161
-; GFX11-NEXT:    ; implicit-def: $vgpr151
-; GFX11-NEXT:    ; implicit-def: $vgpr150
-; GFX11-NEXT:    ; implicit-def: $vgpr147
-; GFX11-NEXT:    ; implicit-def: $vgpr145
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr144
-; GFX11-NEXT:    ; implicit-def: $vgpr133
-; GFX11-NEXT:    ; implicit-def: $vgpr131
-; GFX11-NEXT:    ; implicit-def: $vgpr129
-; GFX11-NEXT:    ; implicit-def: $vgpr119
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr117
-; GFX11-NEXT:    ; implicit-def: $vgpr116
-; GFX11-NEXT:    ; implicit-def: $vgpr115
-; GFX11-NEXT:    ; implicit-def: $vgpr102
-; GFX11-NEXT:    ; implicit-def: $vgpr100
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr98
-; GFX11-NEXT:    ; implicit-def: $vgpr97
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr75
-; GFX11-NEXT:    ; implicit-def: $vgpr73
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr61
-; GFX11-NEXT:    ; implicit-def: $vgpr59
-; GFX11-NEXT:    ; implicit-def: $vgpr58
-; GFX11-NEXT:    ; implicit-def: $vgpr56
-; GFX11-NEXT:    ; implicit-def: $vgpr46
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr44
-; GFX11-NEXT:    ; implicit-def: $vgpr41
-; GFX11-NEXT:    ; implicit-def: $vgpr40
-; GFX11-NEXT:    ; implicit-def: $vgpr182
-; GFX11-NEXT:    ; implicit-def: $vgpr180
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr178
-; GFX11-NEXT:    ; implicit-def: $vgpr176
-; GFX11-NEXT:    ; implicit-def: $vgpr166
-; GFX11-NEXT:    ; implicit-def: $vgpr163
-; GFX11-NEXT:    ; implicit-def: $vgpr162
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr160
-; GFX11-NEXT:    ; implicit-def: $vgpr149
-; GFX11-NEXT:    ; implicit-def: $vgpr148
-; GFX11-NEXT:    ; implicit-def: $vgpr146
-; GFX11-NEXT:    ; implicit-def: $vgpr135
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr134
-; GFX11-NEXT:    ; implicit-def: $vgpr132
-; GFX11-NEXT:    ; implicit-def: $vgpr130
-; GFX11-NEXT:    ; implicit-def: $vgpr128
-; GFX11-NEXT:    ; implicit-def: $vgpr118
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr114
-; GFX11-NEXT:    ; implicit-def: $vgpr113
-; GFX11-NEXT:    ; implicit-def: $vgpr112
-; GFX11-NEXT:    ; implicit-def: $vgpr103
-; GFX11-NEXT:    ; implicit-def: $vgpr101
-; GFX11-NEXT:    ; implicit-def: $vgpr99
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    s_waitcnt vmcnt(2)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v33
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB47_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b64 v[48:49], 24, v[15:16]
-; GFX11-NEXT:    v_lshrrev_b64 v[49:50], 24, v[13:14]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
-; GFX11-NEXT:    v_lshrrev_b64 v[50:51], 24, v[11:12]
-; GFX11-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
-; GFX11-NEXT:    v_lshrrev_b64 v[51:52], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
-; GFX11-NEXT:    v_lshrrev_b64 v[52:53], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[64:65], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
-; GFX11-NEXT:    v_lshrrev_b64 v[53:54], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
-; GFX11-NEXT:    v_lshrrev_b64 v[65:66], 24, v[19:20]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v68, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v70, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v80, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v82, 16, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v86, 8, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v96, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v97, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v98, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v100, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v102, 8, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v115, 24, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v116, 16, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v117, 8, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v119, 16, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v129, 8, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v131, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v133, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v144, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v145, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v147, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v150, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v151, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v161, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v164, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v165, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v167, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v177, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v179, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v181, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v183, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v42, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v43, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v45, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v47, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v57, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v60, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v62, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v63, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v72, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v74, 8, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v69, 24, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v71, 16, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v81, 8, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v83, 16, v31
-; GFX11-NEXT:    v_lshrrev_b32_e32 v84, 8, v31
-; GFX11-NEXT:    v_lshrrev_b32_e32 v85, 24, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v87, 16, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v99, 8, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v101, 16, v29
-; GFX11-NEXT:    v_lshrrev_b32_e32 v103, 8, v29
-; GFX11-NEXT:    v_lshrrev_b32_e32 v112, 24, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v113, 16, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v114, 8, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v118, 16, v27
-; GFX11-NEXT:    v_lshrrev_b32_e32 v128, 8, v27
-; GFX11-NEXT:    v_lshrrev_b32_e32 v130, 24, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v132, 16, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v134, 8, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v135, 16, v25
-; GFX11-NEXT:    v_lshrrev_b32_e32 v146, 8, v25
-; GFX11-NEXT:    v_lshrrev_b32_e32 v148, 24, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v149, 16, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v160, 8, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v162, 16, v23
-; GFX11-NEXT:    v_lshrrev_b32_e32 v163, 8, v23
-; GFX11-NEXT:    v_lshrrev_b32_e32 v166, 24, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v176, 16, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v178, 8, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v180, 16, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v182, 8, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v40, 24, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v41, 16, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v44, 8, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v46, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v56, 8, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v58, 24, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v59, 16, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v61, 8, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v73, 16, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v75, 8, v17
-; GFX11-NEXT:    v_lshrrev_b64 v[54:55], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
-; GFX11-NEXT:    v_lshrrev_b64 v[66:67], 24, v[17:18]
-; GFX11-NEXT:  .LBB47_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB47_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_pk_add_f16 v32, 0x200, v32 op_sel_hi:[0,1]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_pk_add_f16 v31, 0x200, v31 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v30, 0x200, v30 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_lshrrev_b64 v[48:49], 24, v[15:16]
-; GFX11-NEXT:    v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_lshrrev_b64 v[49:50], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
-; GFX11-NEXT:    v_lshrrev_b64 v[50:51], 24, v[11:12]
-; GFX11-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
-; GFX11-NEXT:    v_lshrrev_b64 v[51:52], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
-; GFX11-NEXT:    v_lshrrev_b64 v[52:53], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[64:65], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
-; GFX11-NEXT:    v_lshrrev_b64 v[53:54], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
-; GFX11-NEXT:    v_lshrrev_b64 v[65:66], 24, v[19:20]
-; GFX11-NEXT:    v_lshrrev_b64 v[54:55], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
-; GFX11-NEXT:    v_lshrrev_b64 v[66:67], 24, v[17:18]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v68, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v70, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v80, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v82, 16, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v86, 8, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v96, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v97, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v98, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v100, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v102, 8, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v115, 24, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v116, 16, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v117, 8, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v119, 16, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v129, 8, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v131, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v133, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v144, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v145, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v147, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v150, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v151, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v161, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v164, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v165, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v167, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v177, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v179, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v181, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v183, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v42, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v43, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v45, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v47, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v57, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v60, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v62, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v63, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v72, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v74, 8, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v69, 24, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v71, 16, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v81, 8, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v83, 16, v31
-; GFX11-NEXT:    v_lshrrev_b32_e32 v84, 8, v31
-; GFX11-NEXT:    v_lshrrev_b32_e32 v85, 24, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v87, 16, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v99, 8, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v101, 16, v29
-; GFX11-NEXT:    v_lshrrev_b32_e32 v103, 8, v29
-; GFX11-NEXT:    v_lshrrev_b32_e32 v112, 24, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v113, 16, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v114, 8, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v118, 16, v27
-; GFX11-NEXT:    v_lshrrev_b32_e32 v128, 8, v27
-; GFX11-NEXT:    v_lshrrev_b32_e32 v130, 24, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v132, 16, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v134, 8, v26
-; GFX11-NEXT:    v_lshrrev_b32_e32 v135, 16, v25
-; GFX11-NEXT:    v_lshrrev_b32_e32 v146, 8, v25
-; GFX11-NEXT:    v_lshrrev_b32_e32 v148, 24, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v149, 16, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v160, 8, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v162, 16, v23
-; GFX11-NEXT:    v_lshrrev_b32_e32 v163, 8, v23
-; GFX11-NEXT:    v_lshrrev_b32_e32 v166, 24, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v176, 16, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v178, 8, v22
-; GFX11-NEXT:    v_lshrrev_b32_e32 v180, 16, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v182, 8, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v40, 24, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v41, 16, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v44, 8, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v46, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v56, 8, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v58, 24, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v59, 16, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v61, 8, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v73, 16, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v75, 8, v17
-; GFX11-NEXT:  .LBB47_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v74
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v64
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_lshlrev_b16 v64, 8, v60
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v54
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v55
-; GFX11-NEXT:    v_and_b32_e32 v55, 0xff, v72
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v67, 0xff, v47
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_or_b32_e32 v39, v55, v39
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v63
-; GFX11-NEXT:    v_or_b32_e32 v54, v67, v54
-; GFX11-NEXT:    v_lshlrev_b16 v67, 8, v42
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v39
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v55
-; GFX11-NEXT:    v_and_b32_e32 v55, 0xff, v62
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v53
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v39
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_or_b32_e32 v55, v55, v64
-; GFX11-NEXT:    v_lshlrev_b16 v64, 8, v57
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_lshlrev_b16 v52, 8, v52
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v64
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v45
-; GFX11-NEXT:    v_and_b32_e32 v64, 0xff, v43
-; GFX11-NEXT:    v_lshlrev_b16 v51, 8, v51
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v39
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v54
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v55
-; GFX11-NEXT:    v_or_b32_e32 v54, v64, v67
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v183
-; GFX11-NEXT:    v_and_b32_e32 v64, 0xff, v181
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v39
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v54
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v55
-; GFX11-NEXT:    v_or_b32_e32 v53, v64, v53
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v179
-; GFX11-NEXT:    v_and_b32_e32 v55, 0xff, v177
-; GFX11-NEXT:    v_lshlrev_b16 v64, 8, v167
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v39
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v53
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v54
-; GFX11-NEXT:    v_or_b32_e32 v53, v55, v64
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v165
-; GFX11-NEXT:    v_and_b32_e32 v55, 0xff, v164
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v39
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v53
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v54
-; GFX11-NEXT:    v_or_b32_e32 v52, v55, v52
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v161
-; GFX11-NEXT:    v_and_b32_e32 v54, 0xff, v151
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v150
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v39
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v52
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v53
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_or_b32_e32 v52, v54, v55
-; GFX11-NEXT:    v_and_b32_e32 v54, 0xff, v145
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v147
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v144
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v52, 16, v52
-; GFX11-NEXT:    v_or_b32_e32 v51, v54, v51
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v53
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v55
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v39
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v52
-; GFX11-NEXT:    v_lshlrev_b32_e32 v39, 16, v51
-; GFX11-NEXT:    v_and_b32_e32 v51, 0xff, v133
-; GFX11-NEXT:    v_lshlrev_b16 v52, 8, v131
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v129
-; GFX11-NEXT:    v_and_b32_e32 v54, 0xff, v119
-; GFX11-NEXT:    v_lshlrev_b16 v50, 8, v50
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v117
-; GFX11-NEXT:    v_and_b32_e32 v64, 0xff, v116
-; GFX11-NEXT:    v_lshlrev_b16 v67, 8, v115
-; GFX11-NEXT:    v_or_b32_e32 v51, v51, v52
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v53
-; GFX11-NEXT:    v_or_b32_e32 v50, v54, v50
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v55
-; GFX11-NEXT:    v_or_b32_e32 v52, v64, v67
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v51, 16, v51
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v50, 16, v50
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v52, 16, v52
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off
-; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
-; GFX11-NEXT:    v_or_b32_e32 v1, v9, v39
-; GFX11-NEXT:    v_or_b32_e32 v2, v10, v51
-; GFX11-NEXT:    v_or_b32_e32 v3, v11, v50
-; GFX11-NEXT:    v_or_b32_e32 v4, v12, v52
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v13
-; GFX11-NEXT:    v_lshlrev_b16 v6, 8, v102
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v100
-; GFX11-NEXT:    v_lshlrev_b16 v8, 8, v49
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v14
-; GFX11-NEXT:    v_lshlrev_b16 v10, 8, v98
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v97
-; GFX11-NEXT:    v_lshlrev_b16 v12, 8, v96
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v15
-; GFX11-NEXT:    v_lshlrev_b16 v14, 8, v86
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v8, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v9, v13, v14
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v82
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v48
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v16
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v80
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v70
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v68
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v17
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v75
-; GFX11-NEXT:    v_and_b32_e32 v39, 0xff, v73
-; GFX11-NEXT:    v_lshlrev_b16 v48, 8, v66
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v11, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v12, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v13, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v14, v39, v48
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v8, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v9, v13, v14
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v18
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v61
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v59
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v58
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v19
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v56
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v46
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v65
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v20
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v44
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v11, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v12, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v13, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v14, v18, v19
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v41
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v40
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v21
-; GFX11-NEXT:    v_lshlrev_b16 v18, 8, v182
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v180
-; GFX11-NEXT:    v_lshlrev_b16 v20, 8, v38
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v22
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v178
-; GFX11-NEXT:    v_and_b32_e32 v38, 0xff, v176
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v166
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v16
-; GFX11-NEXT:    v_or_b32_e32 v16, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v17, v19, v20
-; GFX11-NEXT:    v_or_b32_e32 v18, v21, v22
-; GFX11-NEXT:    v_or_b32_e32 v19, v38, v39
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xffff, v18
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v11, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v12, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v13, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v14, v18, v19
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v23
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v163
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v162
-; GFX11-NEXT:    v_lshlrev_b16 v18, 8, v37
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v24
-; GFX11-NEXT:    v_lshlrev_b16 v20, 8, v160
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v149
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v148
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v25
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v146
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v16
-; GFX11-NEXT:    v_or_b32_e32 v16, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v17, v19, v20
-; GFX11-NEXT:    v_or_b32_e32 v18, v21, v22
-; GFX11-NEXT:    v_or_b32_e32 v19, v23, v24
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v135
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v36
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v26
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v134
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v132
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v130
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v27
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v128
-; GFX11-NEXT:    v_and_b32_e32 v36, 0xff, v118
-; GFX11-NEXT:    v_lshlrev_b16 v35, 8, v35
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v21, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v22, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v23, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v24, v36, v35
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff, v19
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xffff, v21
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xffff, v23
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v16
-; GFX11-NEXT:    v_or_b32_e32 v16, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v17, v19, v20
-; GFX11-NEXT:    v_or_b32_e32 v18, v21, v22
-; GFX11-NEXT:    v_or_b32_e32 v19, v23, v24
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v28
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v114
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v113
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v112
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v29
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v103
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v101
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v34
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v30
-; GFX11-NEXT:    v_lshlrev_b16 v29, 8, v99
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v21, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v22, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v23, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v24, v28, v29
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v87
-; GFX11-NEXT:    v_lshlrev_b16 v26, 8, v85
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v31
-; GFX11-NEXT:    v_lshlrev_b16 v28, 8, v84
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v83
-; GFX11-NEXT:    v_lshlrev_b16 v30, 8, v33
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v32
-; GFX11-NEXT:    v_lshlrev_b16 v32, 8, v81
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xff, v71
-; GFX11-NEXT:    v_lshlrev_b16 v34, 8, v69
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v26
-; GFX11-NEXT:    v_or_b32_e32 v26, v27, v28
-; GFX11-NEXT:    v_or_b32_e32 v27, v29, v30
-; GFX11-NEXT:    v_or_b32_e32 v28, v31, v32
-; GFX11-NEXT:    v_or_b32_e32 v29, v33, v34
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xffff, v20
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xffff, v22
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xffff, v24
-; GFX11-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xffff, v26
-; GFX11-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xffff, v28
-; GFX11-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v21, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v22, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v23, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v24, v28, v29
-; GFX11-NEXT:    s_clause 0x5
-; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off offset:32
-; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:48
-; GFX11-NEXT:    scratch_store_b128 v0, v[9:12], off offset:64
-; GFX11-NEXT:    scratch_store_b128 v0, v[13:16], off offset:80
-; GFX11-NEXT:    scratch_store_b128 v0, v[17:20], off offset:96
-; GFX11-NEXT:    scratch_store_b128 v0, v[21:24], off offset:112
-; GFX11-NEXT:    s_clause 0x13
-; GFX11-NEXT:    scratch_load_b32 v75, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_b32 v74, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_b32 v73, off, s32 offset:20
-; GFX11-NEXT:    scratch_load_b32 v72, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_b32 v63, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_b32 v62, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_b32 v61, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_b32 v60, off, s32 offset:40
-; GFX11-NEXT:    scratch_load_b32 v59, off, s32 offset:44
-; GFX11-NEXT:    scratch_load_b32 v58, off, s32 offset:48
-; GFX11-NEXT:    scratch_load_b32 v57, off, s32 offset:52
-; GFX11-NEXT:    scratch_load_b32 v56, off, s32 offset:56
-; GFX11-NEXT:    scratch_load_b32 v47, off, s32 offset:60
-; GFX11-NEXT:    scratch_load_b32 v46, off, s32 offset:64
-; GFX11-NEXT:    scratch_load_b32 v45, off, s32 offset:68
-; GFX11-NEXT:    scratch_load_b32 v44, off, s32 offset:72
-; GFX11-NEXT:    scratch_load_b32 v43, off, s32 offset:76
-; GFX11-NEXT:    scratch_load_b32 v42, off, s32 offset:80
-; GFX11-NEXT:    scratch_load_b32 v41, off, s32 offset:84
-; GFX11-NEXT:    scratch_load_b32 v40, off, s32 offset:88
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v64f16_to_v128i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x2
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v33, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr163_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr68_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr162_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr161_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr160_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr67_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr151_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr150_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr149_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr148_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr147_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr134_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr131_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr130_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr119_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr117_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr115_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr114_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr103_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr101_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr99_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr85_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr145_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr144_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr133_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr132_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr128_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr118_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr116_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr113_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr100_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr97_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr86_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr83_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr71_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr70_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v33
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB47_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[64:65], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[65:66], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[48:49], 24, v[15:16]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[66:67], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[49:50], 24, v[13:14]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[67:68], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v85, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v87, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v98, 8, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v99, 24, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v101, 8, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v103, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v114, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v115, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v117, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v119, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v130, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v131, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v134, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v135, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v146, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v147, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v148, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v149, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v150, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v151, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v160, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v161, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v162, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v163, 8, v1
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v55, 24, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v70, 8, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v71, 8, v31
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v80, 24, v30
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v81, 8, v30
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v82, 8, v29
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v83, 24, v28
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v84, 8, v28
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v86, 8, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v96, 24, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v97, 8, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v100, 8, v25
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v102, 24, v24
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v112, 8, v24
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v113, 8, v23
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v116, 24, v22
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v118, 8, v22
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v128, 8, v21
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v129, 24, v20
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v132, 8, v20
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v133, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v144, 24, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v145, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[68:69], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[50:51], 24, v[19:20]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[53:54], 24, v[17:18]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v17
+; GFX11-TRUE16-NEXT:  .LBB47_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB47_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v32, 0x200, v32 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v31, 0x200, v31 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v30, 0x200, v30 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[64:65], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[65:66], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[48:49], 24, v[15:16]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[66:67], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[49:50], 24, v[13:14]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[67:68], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[68:69], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[50:51], 24, v[19:20]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[53:54], 24, v[17:18]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v85, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v87, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v98, 8, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v99, 24, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v101, 8, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v103, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v114, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v115, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v117, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v119, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v130, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v131, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v134, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v135, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v146, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v147, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v148, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v149, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v150, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v151, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v160, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v161, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v162, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v163, 8, v1
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v55, 24, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v70, 8, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v71, 8, v31
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v80, 24, v30
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v81, 8, v30
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v82, 8, v29
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v83, 24, v28
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v84, 8, v28
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v86, 8, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v96, 24, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v97, 8, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v100, 8, v25
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v102, 24, v24
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v112, 8, v24
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v113, 8, v23
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v116, 24, v22
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v118, 8, v22
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v128, 8, v21
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v129, 24, v20
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v132, 8, v20
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v133, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v144, 24, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v145, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v17
+; GFX11-TRUE16-NEXT:  .LBB47_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v163.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v34.h, 8, v68.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v33.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v161.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v51.l, v1.h, v34.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v162.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v54.l, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v51, 16, v51
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.h, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v54, 0xffff, v54
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v160.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v150.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v68.l, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v69.l, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v67.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v54, v51
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v54, 0xffff, v68
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v67, 16, v69
+; GFX11-TRUE16-NEXT:    v_or_b16 v51.l, v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 8, v151.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v54, v67
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v51, 0xffff, v51
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v54.l, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.h, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.h, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v149.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v54
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v67.l, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v68.l, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v66.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v3.h, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v51, v54
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v51, 0xffff, v67
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v68
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v4.h, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.l, 8, v148.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v147.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v66.l, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v51, v54
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v54.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.h, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.h, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v65.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v51, 0xffff, v66
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v146.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v54
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v66.l, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v5.h, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v51, v54
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v66
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v66.l, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v135.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v134.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v51, 0xffff, v65
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.l, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v51, v54
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v51, 0xffff, v65
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v64.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v130.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.l, v8.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v131.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v10.l, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v64, 0xffff, v64
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v65, 16, v65
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v66
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.h, v8.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v67.l, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v11.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v64, v65
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v65, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v10.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v117.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v52.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v66.l, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v51, v54
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v119.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v11.h
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v103.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v115.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v34.h, 8, v114.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v49.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v33.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v51.l, v12.h, v34.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v10, v11
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v101.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v15.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v48.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v51, 16, v51
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v65, v9
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v14.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v99.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v98.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v6
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v12, v51
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v16.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v87.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v16.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v85.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v10, v11
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v145.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v39.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v18.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v144.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v12, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v14, v15
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v19.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v133.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v19.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v50.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v20.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v129.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v16, v17
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v20.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v132.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v11
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v21.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v128.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v14.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v21.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v38.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v15, v16
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.l, 0xff, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v113.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v14
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v118.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v17, v18
+; GFX11-TRUE16-NEXT:    v_and_b16 v16.l, 0xff, v23.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v37.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v112.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v15.l, v15.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v19, v20
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v24.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v102.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v25.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v100.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v16.l, v16.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v17.l, v17.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.l, 0xff, v25.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v36.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v38, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v21, v22
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v18.l, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v19.l, v19.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v16
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff, v17
+; GFX11-TRUE16-NEXT:    v_and_b16 v16.l, 0xff, v26.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v97.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v26.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v96.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v15.l, v15.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff, v19
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v16.l, v16.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v17.l, v17.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v15
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v27.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v86.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v27.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v16
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v20, v21
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, v22, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, v24, v25
+; GFX11-TRUE16-NEXT:    v_and_b16 v20.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v84.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v21.l, 0xff, v28.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.h, 8, v83.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v29.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v22.h, 8, v82.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v29.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.h, 8, v34.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v30.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v24.h, 8, v81.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v18.l, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v20.l, v20.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v21.l, v21.l, v21.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v22.l, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v23.l, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v24.l, v24.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v53.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v116.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v35.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v35, 0xffff, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v18, v26, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v20
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v21
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v27, 0xffff, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v23
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v29, 0xffff, v24
+; GFX11-TRUE16-NEXT:    v_and_b16 v20.l, 0xff, v30.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v80.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v21.l, 0xff, v31.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.h, 8, v71.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v31.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v22.h, 8, v33.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v32.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.h, 8, v70.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v32.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v24.h, 8, v55.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v14.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v19.l, v19.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v54, 0xffff, v66
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v64, 16, v67
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v20.l, v20.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v21.l, v21.l, v21.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v22.l, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v23.l, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v24.l, v24.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v54, v64
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v20
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff, v21
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v22
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v33, 0xffff, v23
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v39, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v38, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v19, v35, v19
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, v25, v26
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, v27, v28
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, v29, v30
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, v31, v32
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, v33, v24
+; GFX11-TRUE16-NEXT:    s_clause 0x5
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off offset:32
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:48
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[9:12], off offset:64
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[13:16], off offset:80
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[17:20], off offset:96
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[21:24], off offset:112
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v64f16_to_v128i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x13
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s32 offset:88
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v41, s32 offset:84
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v42, s32 offset:80
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v43, s32 offset:76
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v44, s32 offset:72
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v45, s32 offset:68
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v46, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v47, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v56, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v57, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v58, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v59, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v60, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v61, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v62, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v63, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v72, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v73, s32 offset:20
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v74, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v75, s32 offset:12
+; GFX11-FAKE16-NEXT:    s_clause 0x2
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v33, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr74
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr72
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr63
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr62
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr60
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr57
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr47
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr45
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr43
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr42
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr183
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr181
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr179
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr177
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr167
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr165
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr164
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr161
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr151
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr150
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr147
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr144
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr75
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr73
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr61
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr59
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr58
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr56
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr46
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr44
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr41
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr40
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr182
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr180
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr178
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr176
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr166
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr163
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr162
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr160
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr149
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr148
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr135
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB47_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[48:49], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[49:50], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[50:51], 24, v[11:12]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[51:52], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[52:53], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[64:65], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[53:54], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[65:66], 24, v[19:20]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v68, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v70, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v82, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v86, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v97, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v98, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v100, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v102, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v115, 24, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v116, 16, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v117, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v119, 16, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v129, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v131, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v133, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v144, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v145, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v147, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v150, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v151, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v161, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v164, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v165, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v167, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v177, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v179, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v181, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v183, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v42, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v43, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v45, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v47, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v57, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v60, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v62, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v63, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v72, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v74, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v69, 24, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 16, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v81, 8, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 16, v31
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 8, v31
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v85, 24, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 16, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v99, 8, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v101, 16, v29
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v103, 8, v29
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v112, 24, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v113, 16, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v114, 8, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v118, 16, v27
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v128, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v130, 24, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v132, 16, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v134, 8, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v135, 16, v25
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v146, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v148, 24, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v149, 16, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v160, 8, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v162, 16, v23
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v163, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v166, 24, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v176, 16, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v178, 8, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v180, 16, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v182, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v40, 24, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v41, 16, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v44, 8, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v46, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v56, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v58, 24, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v59, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v61, 8, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v73, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v75, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[54:55], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[66:67], 24, v[17:18]
+; GFX11-FAKE16-NEXT:  .LBB47_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB47_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v32, 0x200, v32 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v31, 0x200, v31 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v30, 0x200, v30 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[48:49], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[49:50], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[33:34], 24, v[31:32]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[50:51], 24, v[11:12]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[29:30]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[51:52], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[27:28]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[52:53], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[64:65], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[53:54], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[65:66], 24, v[19:20]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[54:55], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[66:67], 24, v[17:18]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v68, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v70, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v82, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v86, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v97, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v98, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v100, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v102, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v115, 24, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v116, 16, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v117, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v119, 16, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v129, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v131, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v133, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v144, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v145, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v147, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v150, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v151, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v161, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v164, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v165, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v167, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v177, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v179, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v181, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v183, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v42, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v43, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v45, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v47, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v57, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v60, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v62, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v63, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v72, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v74, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v69, 24, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 16, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v81, 8, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 16, v31
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 8, v31
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v85, 24, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 16, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v99, 8, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v101, 16, v29
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v103, 8, v29
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v112, 24, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v113, 16, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v114, 8, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v118, 16, v27
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v128, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v130, 24, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v132, 16, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v134, 8, v26
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v135, 16, v25
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v146, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v148, 24, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v149, 16, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v160, 8, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v162, 16, v23
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v163, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v166, 24, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v176, 16, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v178, 8, v22
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v180, 16, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v182, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v40, 24, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v41, 16, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v44, 8, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v46, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v56, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v58, 24, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v59, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v61, 8, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v73, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v75, 8, v17
+; GFX11-FAKE16-NEXT:  .LBB47_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v74
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v64
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v64, 8, v60
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v55, 0xff, v72
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v67, 0xff, v47
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v39, v55, v39
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v63
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v54, v67, v54
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v67, 8, v42
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v55, 0xff, v62
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v53, 8, v53
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, v55, v64
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v64, 8, v57
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v52, 8, v52
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v64
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v45
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v64, 0xff, v43
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v51, 8, v51
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v54, v64, v67
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v183
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v64, 0xff, v181
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v53, v64, v53
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v179
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v55, 0xff, v177
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v64, 8, v167
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v53, v55, v64
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v165
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v55, 0xff, v164
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v52, v55, v52
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v53, 8, v161
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v54, 0xff, v151
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v150
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v39
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v52
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v53
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v52, v54, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v54, 0xff, v145
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v53, 8, v147
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v144
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v52, 16, v52
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v51, v54, v51
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v52
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v51
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v51, 0xff, v133
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v52, 8, v131
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v53, 8, v129
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v54, 0xff, v119
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v50, 8, v50
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v117
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v64, 0xff, v116
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v67, 8, v115
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v51, v51, v52
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v50, v54, v50
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v52, v64, v67
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v51, 16, v51
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v50, 16, v50
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v52, 16, v52
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v9, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v10, v51
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v11, v50
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v12, v52
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v6, 8, v102
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v100
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v49
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v10, 8, v98
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v97
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v12, 8, v96
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v14, 8, v86
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v13, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v82
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v48
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v70
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v68
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v75
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v39, 0xff, v73
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v48, 8, v66
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v39, v48
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v13, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v61
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v59
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v58
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v56
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v46
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v65
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v44
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v18, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v41
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v40
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v18, 8, v182
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v180
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v38
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v178
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v38, 0xff, v176
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v166
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v19, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v21, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v38, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xffff, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v18, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v163
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v162
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v18, 8, v37
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v160
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v149
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v148
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v146
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v19, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v21, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v23, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v135
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v134
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v132
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v130
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v128
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v36, 0xff, v118
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v35, 8, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v36, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xffff, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v19, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v21, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v23, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v114
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v113
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v112
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v29
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v103
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v101
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v29, 8, v99
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v28, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v87
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v26, 8, v85
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v28, 8, v84
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v83
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v30, 8, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v32, 8, v81
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xff, v71
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v34, 8, v69
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v27, v28
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v29, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v31, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v33, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xffff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xffff, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xffff, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xffff, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xffff, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v28, v29
+; GFX11-FAKE16-NEXT:    s_clause 0x5
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off offset:32
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:48
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[9:12], off offset:64
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[13:16], off offset:80
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[17:20], off offset:96
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[21:24], off offset:112
+; GFX11-FAKE16-NEXT:    s_clause 0x13
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v75, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v74, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v73, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v72, off, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v63, off, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v62, off, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v61, off, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v60, off, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v59, off, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v58, off, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v57, off, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v56, off, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v47, off, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v46, off, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v45, off, s32 offset:68
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v44, off, s32 offset:72
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v43, off, s32 offset:76
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v42, off, s32 offset:80
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v41, off, s32 offset:84
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s32 offset:88
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -91819,923 +103456,1689 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v128i8_to_v64i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_store_b32 off, v40, s32 offset:580
-; GFX11-NEXT:    scratch_store_b32 off, v41, s32 offset:576
-; GFX11-NEXT:    scratch_store_b32 off, v42, s32 offset:572
-; GFX11-NEXT:    scratch_store_b32 off, v43, s32 offset:568
-; GFX11-NEXT:    scratch_store_b32 off, v44, s32 offset:564
-; GFX11-NEXT:    scratch_store_b32 off, v45, s32 offset:560
-; GFX11-NEXT:    scratch_store_b32 off, v46, s32 offset:556
-; GFX11-NEXT:    scratch_store_b32 off, v47, s32 offset:552
-; GFX11-NEXT:    scratch_store_b32 off, v56, s32 offset:548
-; GFX11-NEXT:    scratch_store_b32 off, v57, s32 offset:544
-; GFX11-NEXT:    scratch_store_b32 off, v58, s32 offset:540
-; GFX11-NEXT:    scratch_store_b32 off, v59, s32 offset:536
-; GFX11-NEXT:    scratch_store_b32 off, v60, s32 offset:532
-; GFX11-NEXT:    scratch_store_b32 off, v61, s32 offset:528
-; GFX11-NEXT:    scratch_store_b32 off, v62, s32 offset:524
-; GFX11-NEXT:    scratch_store_b32 off, v63, s32 offset:520
-; GFX11-NEXT:    scratch_store_b32 off, v72, s32 offset:516
-; GFX11-NEXT:    scratch_store_b32 off, v73, s32 offset:512
-; GFX11-NEXT:    scratch_store_b32 off, v74, s32 offset:508
-; GFX11-NEXT:    scratch_store_b32 off, v75, s32 offset:504
-; GFX11-NEXT:    scratch_store_b32 off, v76, s32 offset:500
-; GFX11-NEXT:    scratch_store_b32 off, v77, s32 offset:496
-; GFX11-NEXT:    scratch_store_b32 off, v78, s32 offset:492
-; GFX11-NEXT:    scratch_store_b32 off, v79, s32 offset:488
-; GFX11-NEXT:    scratch_store_b32 off, v88, s32 offset:484
-; GFX11-NEXT:    scratch_store_b32 off, v89, s32 offset:480
-; GFX11-NEXT:    scratch_store_b32 off, v90, s32 offset:476
-; GFX11-NEXT:    scratch_store_b32 off, v91, s32 offset:472
-; GFX11-NEXT:    scratch_store_b32 off, v92, s32 offset:468
-; GFX11-NEXT:    scratch_store_b32 off, v93, s32 offset:464
-; GFX11-NEXT:    scratch_store_b32 off, v94, s32 offset:460
-; GFX11-NEXT:    scratch_store_b32 off, v95, s32 offset:456
-; GFX11-NEXT:    s_clause 0xf
-; GFX11-NEXT:    scratch_store_b32 off, v104, s32 offset:452
-; GFX11-NEXT:    scratch_store_b32 off, v105, s32 offset:448
-; GFX11-NEXT:    scratch_store_b32 off, v106, s32 offset:444
-; GFX11-NEXT:    scratch_store_b32 off, v107, s32 offset:440
-; GFX11-NEXT:    scratch_store_b32 off, v108, s32 offset:436
-; GFX11-NEXT:    scratch_store_b32 off, v109, s32 offset:432
-; GFX11-NEXT:    scratch_store_b32 off, v110, s32 offset:428
-; GFX11-NEXT:    scratch_store_b32 off, v111, s32 offset:424
-; GFX11-NEXT:    scratch_store_b32 off, v120, s32 offset:420
-; GFX11-NEXT:    scratch_store_b32 off, v121, s32 offset:416
-; GFX11-NEXT:    scratch_store_b32 off, v122, s32 offset:412
-; GFX11-NEXT:    scratch_store_b32 off, v123, s32 offset:408
-; GFX11-NEXT:    scratch_store_b32 off, v124, s32 offset:404
-; GFX11-NEXT:    scratch_store_b32 off, v125, s32 offset:400
-; GFX11-NEXT:    scratch_store_b32 off, v126, s32 offset:396
-; GFX11-NEXT:    scratch_store_b32 off, v127, s32 offset:392
-; GFX11-NEXT:    v_dual_mov_b32 v37, v30 :: v_dual_mov_b32 v54, v24
-; GFX11-NEXT:    v_dual_mov_b32 v55, v28 :: v_dual_mov_b32 v52, v26
-; GFX11-NEXT:    v_dual_mov_b32 v50, v22 :: v_dual_mov_b32 v53, v20
-; GFX11-NEXT:    v_dual_mov_b32 v34, v18 :: v_dual_mov_b32 v51, v16
-; GFX11-NEXT:    v_dual_mov_b32 v36, v14 :: v_dual_mov_b32 v49, v12
-; GFX11-NEXT:    v_dual_mov_b32 v32, v10 :: v_dual_mov_b32 v39, v4
-; GFX11-NEXT:    v_dual_mov_b32 v48, v8 :: v_dual_mov_b32 v33, v6
-; GFX11-NEXT:    v_dual_mov_b32 v35, v2 :: v_dual_mov_b32 v38, v0
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v0, off, s32 offset:384
-; GFX11-NEXT:    scratch_load_u16 v118, off, s32 offset:380
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32 offset:376
-; GFX11-NEXT:    scratch_load_u16 v134, off, s32 offset:372
-; GFX11-NEXT:    scratch_load_u16 v4, off, s32 offset:368
-; GFX11-NEXT:    scratch_load_u16 v116, off, s32 offset:364
-; GFX11-NEXT:    scratch_load_u16 v6, off, s32 offset:360
-; GFX11-NEXT:    scratch_load_u16 v131, off, s32 offset:356
-; GFX11-NEXT:    scratch_load_u16 v8, off, s32 offset:352
-; GFX11-NEXT:    scratch_load_u16 v98, off, s32 offset:348
-; GFX11-NEXT:    scratch_load_u16 v10, off, s32 offset:344
-; GFX11-NEXT:    scratch_load_u16 v129, off, s32 offset:340
-; GFX11-NEXT:    scratch_load_u16 v12, off, s32 offset:336
-; GFX11-NEXT:    scratch_load_u16 v99, off, s32 offset:332
-; GFX11-NEXT:    scratch_load_u16 v14, off, s32 offset:328
-; GFX11-NEXT:    scratch_load_u16 v112, off, s32 offset:324
-; GFX11-NEXT:    scratch_load_u16 v16, off, s32 offset:320
-; GFX11-NEXT:    scratch_load_u16 v81, off, s32 offset:316
-; GFX11-NEXT:    scratch_load_u16 v18, off, s32 offset:312
-; GFX11-NEXT:    scratch_load_u16 v103, off, s32 offset:308
-; GFX11-NEXT:    scratch_load_u16 v20, off, s32 offset:304
-; GFX11-NEXT:    scratch_load_u16 v86, off, s32 offset:300
-; GFX11-NEXT:    scratch_load_u16 v22, off, s32 offset:296
-; GFX11-NEXT:    scratch_load_u16 v101, off, s32 offset:292
-; GFX11-NEXT:    scratch_load_u16 v24, off, s32 offset:288
-; GFX11-NEXT:    scratch_load_u16 v83, off, s32 offset:284
-; GFX11-NEXT:    scratch_load_u16 v26, off, s32 offset:280
-; GFX11-NEXT:    scratch_load_u16 v97, off, s32 offset:276
-; GFX11-NEXT:    scratch_load_u16 v28, off, s32 offset:272
-; GFX11-NEXT:    scratch_load_u16 v67, off, s32 offset:268
-; GFX11-NEXT:    scratch_load_u16 v30, off, s32 offset:264
-; GFX11-NEXT:    scratch_load_u16 v85, off, s32 offset:260
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v31, off, s32 offset:256
-; GFX11-NEXT:    scratch_load_u16 v68, off, s32 offset:252
-; GFX11-NEXT:    scratch_load_u16 v94, off, s32 offset:248
-; GFX11-NEXT:    scratch_load_u16 v80, off, s32 offset:244
-; GFX11-NEXT:    scratch_load_u16 v88, off, s32 offset:240
-; GFX11-NEXT:    scratch_load_u16 v64, off, s32 offset:236
-; GFX11-NEXT:    scratch_load_u16 v93, off, s32 offset:232
-; GFX11-NEXT:    scratch_load_u16 v69, off, s32 offset:228
-; GFX11-NEXT:    scratch_load_u16 v91, off, s32 offset:224
-; GFX11-NEXT:    scratch_load_u16 v65, off, s32 offset:220
-; GFX11-NEXT:    scratch_load_u16 v92, off, s32 offset:216
-; GFX11-NEXT:    scratch_load_b32 v150, off, s32 offset:388
-; GFX11-NEXT:    scratch_load_u16 v182, off, s32
-; GFX11-NEXT:    scratch_load_u16 v40, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_u16 v43, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_u16 v44, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_u16 v45, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_u16 v46, off, s32 offset:40
-; GFX11-NEXT:    scratch_load_u16 v47, off, s32 offset:48
-; GFX11-NEXT:    scratch_load_u16 v56, off, s32 offset:56
-; GFX11-NEXT:    scratch_load_u16 v58, off, s32 offset:64
-; GFX11-NEXT:    scratch_load_u16 v59, off, s32 offset:72
-; GFX11-NEXT:    scratch_load_u16 v60, off, s32 offset:80
-; GFX11-NEXT:    scratch_load_u16 v61, off, s32 offset:88
-; GFX11-NEXT:    scratch_load_u16 v62, off, s32 offset:96
-; GFX11-NEXT:    scratch_load_u16 v63, off, s32 offset:104
-; GFX11-NEXT:    scratch_load_u16 v72, off, s32 offset:112
-; GFX11-NEXT:    scratch_load_u16 v73, off, s32 offset:120
-; GFX11-NEXT:    scratch_load_u16 v74, off, s32 offset:128
-; GFX11-NEXT:    scratch_load_u16 v75, off, s32 offset:136
-; GFX11-NEXT:    scratch_load_u16 v76, off, s32 offset:144
-; GFX11-NEXT:    scratch_load_u16 v77, off, s32 offset:152
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v78, off, s32 offset:160
-; GFX11-NEXT:    scratch_load_u16 v79, off, s32 offset:168
-; GFX11-NEXT:    scratch_load_u16 v89, off, s32 offset:176
-; GFX11-NEXT:    scratch_load_u16 v90, off, s32 offset:184
-; GFX11-NEXT:    scratch_load_u16 v95, off, s32 offset:192
-; GFX11-NEXT:    scratch_load_u16 v104, off, s32 offset:200
-; GFX11-NEXT:    scratch_load_u16 v105, off, s32 offset:208
-; GFX11-NEXT:    scratch_load_u16 v42, off, s32 offset:212
-; GFX11-NEXT:    scratch_load_u16 v180, off, s32 offset:204
-; GFX11-NEXT:    scratch_load_u16 v183, off, s32 offset:196
-; GFX11-NEXT:    scratch_load_u16 v165, off, s32 offset:188
-; GFX11-NEXT:    scratch_load_u16 v179, off, s32 offset:180
-; GFX11-NEXT:    scratch_load_u16 v163, off, s32 offset:172
-; GFX11-NEXT:    scratch_load_u16 v177, off, s32 offset:164
-; GFX11-NEXT:    scratch_load_u16 v145, off, s32 offset:156
-; GFX11-NEXT:    scratch_load_u16 v166, off, s32 offset:148
-; GFX11-NEXT:    scratch_load_u16 v148, off, s32 offset:140
-; GFX11-NEXT:    scratch_load_u16 v151, off, s32 offset:132
-; GFX11-NEXT:    scratch_load_u16 v164, off, s32 offset:124
-; GFX11-NEXT:    scratch_load_u16 v178, off, s32 offset:116
-; GFX11-NEXT:    scratch_load_u16 v146, off, s32 offset:108
-; GFX11-NEXT:    scratch_load_u16 v162, off, s32 offset:100
-; GFX11-NEXT:    scratch_load_u16 v144, off, s32 offset:92
-; GFX11-NEXT:    scratch_load_u16 v149, off, s32 offset:84
-; GFX11-NEXT:    scratch_load_u16 v119, off, s32 offset:76
-; GFX11-NEXT:    scratch_load_u16 v147, off, s32 offset:68
-; GFX11-NEXT:    scratch_load_u16 v130, off, s32 offset:60
-; GFX11-NEXT:    scratch_load_u16 v135, off, s32 offset:52
-; GFX11-NEXT:    scratch_load_u16 v117, off, s32 offset:44
-; GFX11-NEXT:    scratch_load_u16 v133, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_u16 v96, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_u16 v114, off, s32 offset:20
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_u16 v87, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_u16 v102, off, s32 offset:4
-; GFX11-NEXT:    v_lshlrev_b16 v70, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v71, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v84, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v82, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v115, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v66, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v128, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v113, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v132, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v100, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v161, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v160, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v176, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v167, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v181, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(62)
-; GFX11-NEXT:    v_lshlrev_b16 v127, 8, v0
-; GFX11-NEXT:    v_lshlrev_b16 v126, 8, v2
-; GFX11-NEXT:    v_lshlrev_b16 v124, 8, v4
-; GFX11-NEXT:    v_lshlrev_b16 v125, 8, v6
-; GFX11-NEXT:    v_lshlrev_b16 v120, 8, v8
-; GFX11-NEXT:    v_lshlrev_b16 v123, 8, v10
-; GFX11-NEXT:    v_lshlrev_b16 v121, 8, v12
-; GFX11-NEXT:    v_lshlrev_b16 v122, 8, v14
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
-; GFX11-NEXT:    v_lshlrev_b16 v106, 8, v16
-; GFX11-NEXT:    v_lshlrev_b16 v111, 8, v18
-; GFX11-NEXT:    v_lshlrev_b16 v109, 8, v20
-; GFX11-NEXT:    v_lshlrev_b16 v110, 8, v22
-; GFX11-NEXT:    v_lshlrev_b16 v107, 8, v24
-; GFX11-NEXT:    v_lshlrev_b16 v108, 8, v26
-; GFX11-NEXT:    s_waitcnt vmcnt(61)
-; GFX11-NEXT:    v_lshlrev_b16 v88, 8, v88
-; GFX11-NEXT:    s_waitcnt vmcnt(59)
-; GFX11-NEXT:    v_lshlrev_b16 v93, 8, v93
-; GFX11-NEXT:    s_waitcnt vmcnt(57)
-; GFX11-NEXT:    v_lshlrev_b16 v91, 8, v91
-; GFX11-NEXT:    s_waitcnt vmcnt(55)
-; GFX11-NEXT:    v_lshlrev_b16 v92, 8, v92
-; GFX11-NEXT:    s_waitcnt vmcnt(54)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v150
-; GFX11-NEXT:    s_waitcnt vmcnt(53)
-; GFX11-NEXT:    v_lshlrev_b16 v150, 8, v182
-; GFX11-NEXT:    s_waitcnt vmcnt(52)
-; GFX11-NEXT:    v_lshlrev_b16 v41, 8, v40
-; GFX11-NEXT:    s_waitcnt vmcnt(51)
-; GFX11-NEXT:    v_lshlrev_b16 v40, 8, v43
-; GFX11-NEXT:    s_waitcnt vmcnt(50)
-; GFX11-NEXT:    v_lshlrev_b16 v43, 8, v44
-; GFX11-NEXT:    s_waitcnt vmcnt(49)
-; GFX11-NEXT:    v_lshlrev_b16 v182, 8, v45
-; GFX11-NEXT:    s_waitcnt vmcnt(48)
-; GFX11-NEXT:    v_lshlrev_b16 v46, 8, v46
-; GFX11-NEXT:    s_waitcnt vmcnt(47)
-; GFX11-NEXT:    v_lshlrev_b16 v45, 8, v47
-; GFX11-NEXT:    s_waitcnt vmcnt(46)
-; GFX11-NEXT:    v_lshlrev_b16 v57, 8, v56
-; GFX11-NEXT:    s_waitcnt vmcnt(45)
-; GFX11-NEXT:    v_lshlrev_b16 v56, 8, v58
-; GFX11-NEXT:    s_waitcnt vmcnt(44)
-; GFX11-NEXT:    v_lshlrev_b16 v58, 8, v59
-; GFX11-NEXT:    s_waitcnt vmcnt(43)
-; GFX11-NEXT:    v_lshlrev_b16 v44, 8, v60
-; GFX11-NEXT:    s_waitcnt vmcnt(42)
-; GFX11-NEXT:    v_lshlrev_b16 v60, 8, v61
-; GFX11-NEXT:    s_waitcnt vmcnt(41)
-; GFX11-NEXT:    v_lshlrev_b16 v59, 8, v62
-; GFX11-NEXT:    s_waitcnt vmcnt(40)
-; GFX11-NEXT:    v_lshlrev_b16 v62, 8, v63
-; GFX11-NEXT:    s_waitcnt vmcnt(39)
-; GFX11-NEXT:    v_lshlrev_b16 v47, 8, v72
-; GFX11-NEXT:    s_waitcnt vmcnt(38)
-; GFX11-NEXT:    v_lshlrev_b16 v72, 8, v73
-; GFX11-NEXT:    s_waitcnt vmcnt(37)
-; GFX11-NEXT:    v_lshlrev_b16 v63, 8, v74
-; GFX11-NEXT:    s_waitcnt vmcnt(36)
-; GFX11-NEXT:    v_lshlrev_b16 v74, 8, v75
-; GFX11-NEXT:    s_waitcnt vmcnt(35)
-; GFX11-NEXT:    v_lshlrev_b16 v73, 8, v76
-; GFX11-NEXT:    s_waitcnt vmcnt(34)
-; GFX11-NEXT:    v_lshlrev_b16 v75, 8, v77
-; GFX11-NEXT:    s_waitcnt vmcnt(33)
-; GFX11-NEXT:    v_lshlrev_b16 v61, 8, v78
-; GFX11-NEXT:    s_waitcnt vmcnt(32)
-; GFX11-NEXT:    v_lshlrev_b16 v78, 8, v79
-; GFX11-NEXT:    s_waitcnt vmcnt(31)
-; GFX11-NEXT:    v_lshlrev_b16 v77, 8, v89
-; GFX11-NEXT:    s_waitcnt vmcnt(30)
-; GFX11-NEXT:    v_lshlrev_b16 v79, 8, v90
-; GFX11-NEXT:    s_waitcnt vmcnt(29)
-; GFX11-NEXT:    v_lshlrev_b16 v76, 8, v95
-; GFX11-NEXT:    s_waitcnt vmcnt(28)
-; GFX11-NEXT:    v_lshlrev_b16 v90, 8, v104
-; GFX11-NEXT:    s_waitcnt vmcnt(27)
-; GFX11-NEXT:    v_lshlrev_b16 v89, 8, v105
-; GFX11-NEXT:    v_lshlrev_b16 v104, 8, v94
-; GFX11-NEXT:    v_lshlrev_b16 v95, 8, v31
-; GFX11-NEXT:    v_lshlrev_b16 v105, 8, v30
-; GFX11-NEXT:    v_lshlrev_b16 v94, 8, v28
-; GFX11-NEXT:    ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB48_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v38
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v35
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v39
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v48
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v70
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v71
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v84
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v82
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v36
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v51
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v34
-; GFX11-NEXT:    v_perm_b32 v1, v3, v2, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v49
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v53
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v50
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v54
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v52
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v115
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v66
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v128
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v113
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v132
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v100
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v161
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v160
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v176
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v167
-; GFX11-NEXT:    v_perm_b32 v2, v2, v4, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v3, v5, v3, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v4, v7, v6, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v5, v9, v8, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v6, v11, v10, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v55
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v37
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v102
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v87
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v114
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v96
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v133
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v117
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v135
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v130
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v181
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v150
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v41
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v40
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v43
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v182
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v46
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v45
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v57
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v56
-; GFX11-NEXT:    v_perm_b32 v7, v8, v7, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v8, v10, v9, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v9, v12, v11, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v10, v14, v13, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v11, v16, v15, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v147
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v119
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v149
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v144
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v162
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v146
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v178
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v164
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v151
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v148
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v58
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v44
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v60
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v59
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v62
-; GFX11-NEXT:    v_or_b32_e32 v17, v17, v47
-; GFX11-NEXT:    v_or_b32_e32 v18, v18, v72
-; GFX11-NEXT:    v_or_b32_e32 v19, v19, v63
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v74
-; GFX11-NEXT:    v_or_b32_e32 v21, v21, v73
-; GFX11-NEXT:    v_perm_b32 v12, v13, v12, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v13, v15, v14, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v14, v17, v16, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v15, v19, v18, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v16, v21, v20, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v166
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v145
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v177
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v163
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v179
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v165
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v183
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v180
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v42
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v65
-; GFX11-NEXT:    v_or_b32_e32 v17, v17, v75
-; GFX11-NEXT:    v_or_b32_e32 v18, v18, v61
-; GFX11-NEXT:    v_or_b32_e32 v19, v19, v78
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v77
-; GFX11-NEXT:    v_or_b32_e32 v21, v21, v79
-; GFX11-NEXT:    v_or_b32_e32 v22, v22, v76
-; GFX11-NEXT:    v_or_b32_e32 v23, v23, v90
-; GFX11-NEXT:    v_or_b32_e32 v24, v24, v89
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v92
-; GFX11-NEXT:    v_or_b32_e32 v26, v26, v91
-; GFX11-NEXT:    v_perm_b32 v17, v18, v17, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v18, v20, v19, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v19, v22, v21, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v20, v24, v23, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v21, v26, v25, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v69
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v64
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v80
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v68
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v85
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v67
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v97
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v83
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v101
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v86
-; GFX11-NEXT:    v_or_b32_e32 v22, v22, v93
-; GFX11-NEXT:    v_or_b32_e32 v23, v23, v88
-; GFX11-NEXT:    v_or_b32_e32 v24, v24, v104
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v95
-; GFX11-NEXT:    v_or_b32_e32 v26, v26, v105
-; GFX11-NEXT:    v_or_b32_e32 v27, v27, v94
-; GFX11-NEXT:    v_or_b32_e32 v28, v28, v108
-; GFX11-NEXT:    v_or_b32_e32 v29, v29, v107
-; GFX11-NEXT:    v_or_b32_e32 v30, v30, v110
-; GFX11-NEXT:    v_or_b32_e32 v31, v31, v109
-; GFX11-NEXT:    v_perm_b32 v22, v23, v22, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v23, v25, v24, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v24, v27, v26, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v25, v29, v28, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v26, v31, v30, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xff, v103
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v81
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xff, v112
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v99
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xff, v129
-; GFX11-NEXT:    v_and_b32_e32 v32, 0xff, v98
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xff, v131
-; GFX11-NEXT:    v_and_b32_e32 v34, 0xff, v116
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xff, v134
-; GFX11-NEXT:    v_and_b32_e32 v36, 0xff, v118
-; GFX11-NEXT:    v_or_b32_e32 v27, v27, v111
-; GFX11-NEXT:    v_or_b32_e32 v28, v28, v106
-; GFX11-NEXT:    v_or_b32_e32 v29, v29, v122
-; GFX11-NEXT:    v_or_b32_e32 v30, v30, v121
-; GFX11-NEXT:    v_or_b32_e32 v31, v31, v123
-; GFX11-NEXT:    v_or_b32_e32 v32, v32, v120
-; GFX11-NEXT:    v_or_b32_e32 v33, v33, v125
-; GFX11-NEXT:    v_or_b32_e32 v34, v34, v124
-; GFX11-NEXT:    v_or_b32_e32 v35, v35, v126
-; GFX11-NEXT:    v_or_b32_e32 v36, v36, v127
-; GFX11-NEXT:    v_perm_b32 v27, v28, v27, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v28, v30, v29, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v29, v32, v31, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v30, v34, v33, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v31, v36, v35, 0x5040100
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr102
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr114
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr133
-; GFX11-NEXT:    ; implicit-def: $vgpr117
-; GFX11-NEXT:    ; implicit-def: $vgpr135
-; GFX11-NEXT:    ; implicit-def: $vgpr130
-; GFX11-NEXT:    ; implicit-def: $vgpr147
-; GFX11-NEXT:    ; implicit-def: $vgpr119
-; GFX11-NEXT:    ; implicit-def: $vgpr149
-; GFX11-NEXT:    ; implicit-def: $vgpr144
-; GFX11-NEXT:    ; implicit-def: $vgpr162
-; GFX11-NEXT:    ; implicit-def: $vgpr146
-; GFX11-NEXT:    ; implicit-def: $vgpr178
-; GFX11-NEXT:    ; implicit-def: $vgpr164
-; GFX11-NEXT:    ; implicit-def: $vgpr151
-; GFX11-NEXT:    ; implicit-def: $vgpr148
-; GFX11-NEXT:    ; implicit-def: $vgpr166
-; GFX11-NEXT:    ; implicit-def: $vgpr145
-; GFX11-NEXT:    ; implicit-def: $vgpr177
-; GFX11-NEXT:    ; implicit-def: $vgpr163
-; GFX11-NEXT:    ; implicit-def: $vgpr179
-; GFX11-NEXT:    ; implicit-def: $vgpr165
-; GFX11-NEXT:    ; implicit-def: $vgpr183
-; GFX11-NEXT:    ; implicit-def: $vgpr180
-; GFX11-NEXT:    ; implicit-def: $vgpr42
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr67
-; GFX11-NEXT:    ; implicit-def: $vgpr97
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr101
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr103
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr112
-; GFX11-NEXT:    ; implicit-def: $vgpr99
-; GFX11-NEXT:    ; implicit-def: $vgpr129
-; GFX11-NEXT:    ; implicit-def: $vgpr98
-; GFX11-NEXT:    ; implicit-def: $vgpr131
-; GFX11-NEXT:    ; implicit-def: $vgpr116
-; GFX11-NEXT:    ; implicit-def: $vgpr134
-; GFX11-NEXT:    ; implicit-def: $vgpr118
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr115
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr128
-; GFX11-NEXT:    ; implicit-def: $vgpr113
-; GFX11-NEXT:    ; implicit-def: $vgpr132
-; GFX11-NEXT:    ; implicit-def: $vgpr100
-; GFX11-NEXT:    ; implicit-def: $vgpr161
-; GFX11-NEXT:    ; implicit-def: $vgpr160
-; GFX11-NEXT:    ; implicit-def: $vgpr176
-; GFX11-NEXT:    ; implicit-def: $vgpr167
-; GFX11-NEXT:    ; implicit-def: $vgpr181
-; GFX11-NEXT:    ; implicit-def: $vgpr150
-; GFX11-NEXT:    ; implicit-def: $vgpr41
-; GFX11-NEXT:    ; implicit-def: $vgpr40
-; GFX11-NEXT:    ; implicit-def: $vgpr43
-; GFX11-NEXT:    ; implicit-def: $vgpr182
-; GFX11-NEXT:    ; implicit-def: $vgpr46
-; GFX11-NEXT:    ; implicit-def: $vgpr45
-; GFX11-NEXT:    ; implicit-def: $vgpr57
-; GFX11-NEXT:    ; implicit-def: $vgpr56
-; GFX11-NEXT:    ; implicit-def: $vgpr58
-; GFX11-NEXT:    ; implicit-def: $vgpr44
-; GFX11-NEXT:    ; implicit-def: $vgpr60
-; GFX11-NEXT:    ; implicit-def: $vgpr59
-; GFX11-NEXT:    ; implicit-def: $vgpr62
-; GFX11-NEXT:    ; implicit-def: $vgpr47
-; GFX11-NEXT:    ; implicit-def: $vgpr72
-; GFX11-NEXT:    ; implicit-def: $vgpr63
-; GFX11-NEXT:    ; implicit-def: $vgpr74
-; GFX11-NEXT:    ; implicit-def: $vgpr73
-; GFX11-NEXT:    ; implicit-def: $vgpr75
-; GFX11-NEXT:    ; implicit-def: $vgpr61
-; GFX11-NEXT:    ; implicit-def: $vgpr78
-; GFX11-NEXT:    ; implicit-def: $vgpr77
-; GFX11-NEXT:    ; implicit-def: $vgpr79
-; GFX11-NEXT:    ; implicit-def: $vgpr76
-; GFX11-NEXT:    ; implicit-def: $vgpr90
-; GFX11-NEXT:    ; implicit-def: $vgpr89
-; GFX11-NEXT:    ; implicit-def: $vgpr92
-; GFX11-NEXT:    ; implicit-def: $vgpr91
-; GFX11-NEXT:    ; implicit-def: $vgpr93
-; GFX11-NEXT:    ; implicit-def: $vgpr88
-; GFX11-NEXT:    ; implicit-def: $vgpr104
-; GFX11-NEXT:    ; implicit-def: $vgpr95
-; GFX11-NEXT:    ; implicit-def: $vgpr105
-; GFX11-NEXT:    ; implicit-def: $vgpr94
-; GFX11-NEXT:    ; implicit-def: $vgpr108
-; GFX11-NEXT:    ; implicit-def: $vgpr107
-; GFX11-NEXT:    ; implicit-def: $vgpr110
-; GFX11-NEXT:    ; implicit-def: $vgpr109
-; GFX11-NEXT:    ; implicit-def: $vgpr111
-; GFX11-NEXT:    ; implicit-def: $vgpr106
-; GFX11-NEXT:    ; implicit-def: $vgpr122
-; GFX11-NEXT:    ; implicit-def: $vgpr121
-; GFX11-NEXT:    ; implicit-def: $vgpr123
-; GFX11-NEXT:    ; implicit-def: $vgpr120
-; GFX11-NEXT:    ; implicit-def: $vgpr125
-; GFX11-NEXT:    ; implicit-def: $vgpr124
-; GFX11-NEXT:    ; implicit-def: $vgpr126
-; GFX11-NEXT:    ; implicit-def: $vgpr127
-; GFX11-NEXT:  .LBB48_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB48_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v134, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v118, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v131, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v116, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v129, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_add_nc_u16 v35, v35, 3
-; GFX11-NEXT:    v_or_b32_e32 v0, v126, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v127, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v125, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v124, v3
-; GFX11-NEXT:    v_add_nc_u16 v33, v33, 3
-; GFX11-NEXT:    v_add_nc_u16 v31, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v98, 3
-; GFX11-NEXT:    v_add_nc_u16 v116, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v30, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v98, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v1, v112, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v4
-; GFX11-NEXT:    v_add_nc_u16 v3, v99, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v4, v103, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v123, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v0, v120, v0
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v1, v122, v1
-; GFX11-NEXT:    v_add_nc_u16 v29, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v121, v3
-; GFX11-NEXT:    v_add_nc_u16 v99, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v111, v4
-; GFX11-NEXT:    v_add_nc_u16 v28, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v81, 3
-; GFX11-NEXT:    v_add_nc_u16 v81, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v101, 3
-; GFX11-NEXT:    v_add_nc_u16 v27, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v86, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v3, v97, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v4, v83, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v106, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v110, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v0, v109, v0
-; GFX11-NEXT:    v_add_nc_u16 v83, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v108, v3
-; GFX11-NEXT:    v_add_nc_u16 v26, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v107, v4
-; GFX11-NEXT:    v_add_nc_u16 v86, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v85, 3
-; GFX11-NEXT:    v_add_nc_u16 v25, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v67, 3
-; GFX11-NEXT:    v_add_nc_u16 v67, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v80, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v3, v68, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v4, v69, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_or_b32_e32 v0, v105, v0
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v1, v94, v1
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v2, v104, v2
-; GFX11-NEXT:    v_add_nc_u16 v24, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v95, v3
-; GFX11-NEXT:    v_add_nc_u16 v68, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v93, v4
-; GFX11-NEXT:    v_add_nc_u16 v23, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v64, 3
-; GFX11-NEXT:    v_add_nc_u16 v64, 0x300, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(26)
-; GFX11-NEXT:    v_add_nc_u16 v0, v42, 3
-; GFX11-NEXT:    v_add_nc_u16 v22, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v65, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(24)
-; GFX11-NEXT:    v_add_nc_u16 v3, v183, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v4, v180, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v88, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v0, v92, v0
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v1, v91, v1
-; GFX11-NEXT:    v_add_nc_u16 v65, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v90, v3
-; GFX11-NEXT:    v_add_nc_u16 v21, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v89, v4
-; GFX11-NEXT:    v_add_nc_u16 v69, 0x300, v1
-; GFX11-NEXT:    s_waitcnt vmcnt(22)
-; GFX11-NEXT:    v_add_nc_u16 v1, v179, 3
-; GFX11-NEXT:    v_add_nc_u16 v20, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v165, 3
-; GFX11-NEXT:    v_add_nc_u16 v80, 0x300, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(20)
-; GFX11-NEXT:    v_add_nc_u16 v0, v177, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v3, v163, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(18)
-; GFX11-NEXT:    v_add_nc_u16 v4, v166, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v79, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v76, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v0, v78, v0
-; GFX11-NEXT:    v_add_nc_u16 v19, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v77, v3
-; GFX11-NEXT:    v_add_nc_u16 v85, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v75, v4
-; GFX11-NEXT:    v_add_nc_u16 v18, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v145, 3
-; GFX11-NEXT:    v_add_nc_u16 v97, 0x300, v1
-; GFX11-NEXT:    s_waitcnt vmcnt(16)
-; GFX11-NEXT:    v_add_nc_u16 v1, v151, 3
-; GFX11-NEXT:    v_add_nc_u16 v17, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v148, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(14)
-; GFX11-NEXT:    v_add_nc_u16 v3, v178, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v4, v164, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_or_b32_e32 v0, v61, v0
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v1, v74, v1
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v2, v73, v2
-; GFX11-NEXT:    v_add_nc_u16 v101, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v72, v3
-; GFX11-NEXT:    v_add_nc_u16 v16, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v63, v4
-; GFX11-NEXT:    v_add_nc_u16 v103, 0x300, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(12)
-; GFX11-NEXT:    v_add_nc_u16 v2, v162, 3
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v146, 3
-; GFX11-NEXT:    v_add_nc_u16 v112, 0x300, v1
-; GFX11-NEXT:    s_waitcnt vmcnt(10)
-; GFX11-NEXT:    v_add_nc_u16 v1, v149, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, v144, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(8)
-; GFX11-NEXT:    v_add_nc_u16 v4, v147, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v62, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v0, v47, v0
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v1, v60, v1
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v59, v3
-; GFX11-NEXT:    v_add_nc_u16 v118, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v58, v4
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v119, 3
-; GFX11-NEXT:    v_add_nc_u16 v119, 0x300, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(6)
-; GFX11-NEXT:    v_add_nc_u16 v2, v135, 3
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v130, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    s_waitcnt vmcnt(4)
-; GFX11-NEXT:    v_add_nc_u16 v3, v133, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v4, v117, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v44, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v57, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v0, v56, v0
-; GFX11-NEXT:    v_add_nc_u16 v117, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v46, v3
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v45, v4
-; GFX11-NEXT:    v_add_nc_u16 v129, 0x300, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(2)
-; GFX11-NEXT:    v_add_nc_u16 v0, v114, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v96, 3
-; GFX11-NEXT:    v_add_nc_u16 v96, 0x300, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_nc_u16 v2, v102, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v3, v87, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v4, v55, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_or_b32_e32 v0, v43, v0
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v1, v182, v1
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v2, v41, v2
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v40, v3
-; GFX11-NEXT:    v_add_nc_u16 v55, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v181, v4
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v37, 3
-; GFX11-NEXT:    v_add_nc_u16 v37, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v54, 3
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v52, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, v53, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v4, v50, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v150, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v0, v176, v0
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v1, v167, v1
-; GFX11-NEXT:    v_add_nc_u16 v50, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v161, v3
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v160, v4
-; GFX11-NEXT:    v_add_nc_u16 v52, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v51, 3
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v49, 3
-; GFX11-NEXT:    v_add_nc_u16 v49, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v48, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v3, v34, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v4, v36, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v132, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v128, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v0, v115, v0
-; GFX11-NEXT:    v_add_nc_u16 v34, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v100, v3
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v113, v4
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v39, 3
-; GFX11-NEXT:    v_add_nc_u16 v36, v38, 3
-; GFX11-NEXT:    v_add_nc_u16 v32, v32, 3
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xff, v35
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v36, 0xff, v36
-; GFX11-NEXT:    v_and_b32_e32 v32, 0xff, v32
-; GFX11-NEXT:    v_or_b32_e32 v35, v71, v35
-; GFX11-NEXT:    v_or_b32_e32 v33, v82, v33
-; GFX11-NEXT:    v_or_b32_e32 v0, v84, v0
-; GFX11-NEXT:    v_or_b32_e32 v36, v70, v36
-; GFX11-NEXT:    v_or_b32_e32 v32, v66, v32
-; GFX11-NEXT:    v_add_nc_u16 v35, 0x300, v35
-; GFX11-NEXT:    v_add_nc_u16 v33, 0x300, v33
-; GFX11-NEXT:    v_add_nc_u16 v38, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v36
-; GFX11-NEXT:    v_add_nc_u16 v32, 0x300, v32
-; GFX11-NEXT:    v_add_nc_u16 v36, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v39, 0x300, v1
-; GFX11-NEXT:    v_perm_b32 v1, v33, v38, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v0, v35, v0, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v2, v32, v4, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v3, v36, v3, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v4, v39, v34, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v5, v49, v5, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v6, v52, v6, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v7, v50, v7, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v8, v37, v8, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v9, v55, v9, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v10, v96, v10, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v11, v129, v11, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v12, v117, v12, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v13, v119, v13, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v14, v118, v14, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v15, v112, v15, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v16, v103, v16, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v17, v101, v17, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v18, v97, v18, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v19, v85, v19, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v20, v80, v20, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v21, v69, v21, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v22, v65, v22, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v23, v64, v23, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v24, v68, v24, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v25, v67, v25, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v26, v86, v26, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v27, v83, v27, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v28, v81, v28, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v29, v99, v29, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v30, v98, v30, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v31, v116, v31, 0x5040100
-; GFX11-NEXT:  .LBB48_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_b32 v127, off, s32 offset:392
-; GFX11-NEXT:    scratch_load_b32 v126, off, s32 offset:396
-; GFX11-NEXT:    scratch_load_b32 v125, off, s32 offset:400
-; GFX11-NEXT:    scratch_load_b32 v124, off, s32 offset:404
-; GFX11-NEXT:    scratch_load_b32 v123, off, s32 offset:408
-; GFX11-NEXT:    scratch_load_b32 v122, off, s32 offset:412
-; GFX11-NEXT:    scratch_load_b32 v121, off, s32 offset:416
-; GFX11-NEXT:    scratch_load_b32 v120, off, s32 offset:420
-; GFX11-NEXT:    scratch_load_b32 v111, off, s32 offset:424
-; GFX11-NEXT:    scratch_load_b32 v110, off, s32 offset:428
-; GFX11-NEXT:    scratch_load_b32 v109, off, s32 offset:432
-; GFX11-NEXT:    scratch_load_b32 v108, off, s32 offset:436
-; GFX11-NEXT:    scratch_load_b32 v107, off, s32 offset:440
-; GFX11-NEXT:    scratch_load_b32 v106, off, s32 offset:444
-; GFX11-NEXT:    scratch_load_b32 v105, off, s32 offset:448
-; GFX11-NEXT:    scratch_load_b32 v104, off, s32 offset:452
-; GFX11-NEXT:    scratch_load_b32 v95, off, s32 offset:456
-; GFX11-NEXT:    scratch_load_b32 v94, off, s32 offset:460
-; GFX11-NEXT:    scratch_load_b32 v93, off, s32 offset:464
-; GFX11-NEXT:    scratch_load_b32 v92, off, s32 offset:468
-; GFX11-NEXT:    scratch_load_b32 v91, off, s32 offset:472
-; GFX11-NEXT:    scratch_load_b32 v90, off, s32 offset:476
-; GFX11-NEXT:    scratch_load_b32 v89, off, s32 offset:480
-; GFX11-NEXT:    scratch_load_b32 v88, off, s32 offset:484
-; GFX11-NEXT:    scratch_load_b32 v79, off, s32 offset:488
-; GFX11-NEXT:    scratch_load_b32 v78, off, s32 offset:492
-; GFX11-NEXT:    scratch_load_b32 v77, off, s32 offset:496
-; GFX11-NEXT:    scratch_load_b32 v76, off, s32 offset:500
-; GFX11-NEXT:    scratch_load_b32 v75, off, s32 offset:504
-; GFX11-NEXT:    scratch_load_b32 v74, off, s32 offset:508
-; GFX11-NEXT:    scratch_load_b32 v73, off, s32 offset:512
-; GFX11-NEXT:    scratch_load_b32 v72, off, s32 offset:516
-; GFX11-NEXT:    s_clause 0xf
-; GFX11-NEXT:    scratch_load_b32 v63, off, s32 offset:520
-; GFX11-NEXT:    scratch_load_b32 v62, off, s32 offset:524
-; GFX11-NEXT:    scratch_load_b32 v61, off, s32 offset:528
-; GFX11-NEXT:    scratch_load_b32 v60, off, s32 offset:532
-; GFX11-NEXT:    scratch_load_b32 v59, off, s32 offset:536
-; GFX11-NEXT:    scratch_load_b32 v58, off, s32 offset:540
-; GFX11-NEXT:    scratch_load_b32 v57, off, s32 offset:544
-; GFX11-NEXT:    scratch_load_b32 v56, off, s32 offset:548
-; GFX11-NEXT:    scratch_load_b32 v47, off, s32 offset:552
-; GFX11-NEXT:    scratch_load_b32 v46, off, s32 offset:556
-; GFX11-NEXT:    scratch_load_b32 v45, off, s32 offset:560
-; GFX11-NEXT:    scratch_load_b32 v44, off, s32 offset:564
-; GFX11-NEXT:    scratch_load_b32 v43, off, s32 offset:568
-; GFX11-NEXT:    scratch_load_b32 v42, off, s32 offset:572
-; GFX11-NEXT:    scratch_load_b32 v41, off, s32 offset:576
-; GFX11-NEXT:    scratch_load_b32 v40, off, s32 offset:580
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v128i8_to_v64i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32 offset:384
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v39, off, s32 offset:380
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v31, off, s32 offset:376
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v50, off, s32 offset:372
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v150, off, s32 offset:368
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v39, off, s32 offset:364
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v150, off, s32 offset:360
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v50, off, s32 offset:356
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v147, off, s32 offset:352
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v37, off, s32 offset:348
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v149, off, s32 offset:344
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v49, off, s32 offset:340
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v149, off, s32 offset:336
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v38, off, s32 offset:332
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v148, off, s32 offset:328
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v48, off, s32 offset:324
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v145, off, s32 offset:320
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v34, off, s32 offset:316
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v148, off, s32 offset:312
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v48, off, s32 offset:308
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v147, off, s32 offset:304
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v36, off, s32 offset:300
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v146, off, s32 offset:296
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v38, off, s32 offset:292
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v146, off, s32 offset:288
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v36, off, s32 offset:284
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v145, off, s32 offset:280
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v37, off, s32 offset:276
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v134, off, s32 offset:272
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v33, off, s32 offset:268
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v144, off, s32 offset:264
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v35, off, s32 offset:260
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v144, off, s32 offset:256
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v33, off, s32 offset:252
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v135, off, s32 offset:248
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v35, off, s32 offset:244
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v132, off, s32 offset:240
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v32, off, s32 offset:236
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v135, off, s32 offset:232
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v34, off, s32 offset:228
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v134, off, s32 offset:224
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v32, off, s32 offset:220
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v133, off, s32 offset:216
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v160, off, s32 offset:388
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v101, off, s32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v103, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v113, off, s32 offset:16
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v113, off, s32 offset:24
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v114, off, s32 offset:32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v114, off, s32 offset:40
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v115, off, s32 offset:48
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v116, off, s32 offset:56
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v116, off, s32 offset:64
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v117, off, s32 offset:72
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v117, off, s32 offset:80
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v118, off, s32 offset:88
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v118, off, s32 offset:96
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v119, off, s32 offset:104
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v119, off, s32 offset:112
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v128, off, s32 offset:120
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v128, off, s32 offset:128
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v129, off, s32 offset:136
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v129, off, s32 offset:144
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v130, off, s32 offset:152
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v130, off, s32 offset:160
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v131, off, s32 offset:168
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v131, off, s32 offset:176
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v132, off, s32 offset:184
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v133, off, s32 offset:192
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v151, off, s32 offset:200
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v151, off, s32 offset:208
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v100, off, s32 offset:212
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v98, off, s32 offset:204
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v100, off, s32 offset:196
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v85, off, s32 offset:188
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v97, off, s32 offset:180
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v86, off, s32 offset:172
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v96, off, s32 offset:164
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v71, off, s32 offset:156
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v87, off, s32 offset:148
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v80, off, s32 offset:140
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v84, off, s32 offset:132
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v86, off, s32 offset:124
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v96, off, s32 offset:116
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v80, off, s32 offset:108
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v85, off, s32 offset:100
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v82, off, s32 offset:92
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v84, off, s32 offset:84
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v69, off, s32 offset:76
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v83, off, s32 offset:68
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v69, off, s32 offset:60
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v71, off, s32 offset:52
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v68, off, s32 offset:44
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v70, off, s32 offset:36
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v66, off, s32 offset:28
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v68, off, s32 offset:20
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v66, off, s32 offset:12
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v67, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v54.l, v30.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v67.l, v28.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.h, v26.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.h, v24.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v22.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.l, v20.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v52.l, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.h, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.h, v14.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v49.h, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v54.h, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v51.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.l, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v51.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v52.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v81.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v81.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v82.h, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v83.l, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v97.h, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v70.l, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v98.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v99.l, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v99.h, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v87.l, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v101.h, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v102.l, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v102.h, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v103.l, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v112.l, 8, v29.l
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(62)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v150.h, 8, v150.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v150.l, 8, v150.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v147.h, 8, v147.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v149.h, 8, v149.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v149.l, 8, v149.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v148.h, 8, v148.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v145.l, 8, v145.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v148.l, 8, v148.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v147.l, 8, v147.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v146.h, 8, v146.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v146.l, 8, v146.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v145.h, 8, v145.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v134.h, 8, v134.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v144.h, 8, v144.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v144.l, 8, v144.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v135.h, 8, v135.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(61)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v132.l, 8, v132.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(59)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v135.l, 8, v135.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(57)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v134.l, 8, v134.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(55)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v133.h, 8, v133.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(54)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v160
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(53)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v101.l, 8, v101.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(52)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v112.h, 8, v103.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(51)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v113.l, 8, v113.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(50)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v113.h, 8, v113.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(49)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v103.h, 8, v114.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(48)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v115.l, 8, v114.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(47)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v115.h, 8, v115.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(46)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v116.l, 8, v116.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(45)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v116.h, 8, v116.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(44)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v117.l, 8, v117.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(43)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v114.l, 8, v117.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(42)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v118.l, 8, v118.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(41)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v118.h, 8, v118.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(40)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v119.l, 8, v119.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(39)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v114.h, 8, v119.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(38)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v119.h, 8, v128.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(37)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v128.l, 8, v128.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(36)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v128.h, 8, v129.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(35)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v129.l, 8, v129.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(34)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v130.l, 8, v130.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v117.h, 8, v130.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(32)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v130.h, 8, v131.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v131.l, 8, v131.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(30)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v131.h, 8, v132.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(29)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v129.h, 8, v133.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(28)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v132.h, 8, v151.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(27)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v133.l, 8, v151.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v151.l, 8, v31.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v151.h, 8, v31.l
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB48_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB48_4
+; GFX11-TRUE16-NEXT:  .LBB48_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB48_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v52.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v51.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v53.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v51.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v54.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v49.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v55.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v53.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v55.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v52.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v65.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v64.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v65.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v64.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v67.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v54.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v67.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v66.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v68.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.h, 0xff, v66.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v70.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.h, 0xff, v68.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v71.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.h, 0xff, v69.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v83.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v69.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v84.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v82.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v85.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.h, 0xff, v80.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.l, 0xff, v96.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.h, 0xff, v86.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v16.l, 0xff, v84.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v16.h, 0xff, v80.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.l, 0xff, v87.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v17.h, 0xff, v71.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.l, 0xff, v96.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v18.h, 0xff, v86.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.l, 0xff, v97.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v19.h, 0xff, v85.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v20.l, 0xff, v100.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v20.h, 0xff, v98.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v21.l, 0xff, v100.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v21.h, 0xff, v32.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.l, 0xff, v34.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v22.h, 0xff, v32.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.l, 0xff, v35.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v23.h, 0xff, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.l, 0xff, v35.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v24.h, 0xff, v33.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v25.l, 0xff, v37.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v25.h, 0xff, v36.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v26.l, 0xff, v38.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v26.h, 0xff, v36.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.l, 0xff, v48.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v27.h, 0xff, v34.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.l, 0xff, v48.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v28.h, 0xff, v38.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v29.l, 0xff, v49.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v29.h, 0xff, v37.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v30.l, 0xff, v50.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v30.h, 0xff, v39.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v31.l, 0xff, v50.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v31.h, 0xff, v39.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v81.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v81.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v82.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v1.h, v83.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v97.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v2.h, v70.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v98.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v3.h, v99.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v99.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.h, v4.h, v87.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v101.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.h, v5.h, v102.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v102.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v6.h, v103.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v112.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v7.h, v101.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v112.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.h, v8.h, v113.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v113.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.h, v9.h, v103.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v115.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.h, v10.h, v115.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v116.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.h, v11.h, v116.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v117.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.h, v12.h, v114.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v118.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.h, v13.h, v118.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v119.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.h, v14.h, v114.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v15.l, v119.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.h, v15.h, v128.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v16.l, v128.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.h, v16.h, v129.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v17.l, v130.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.h, v17.h, v117.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v18.l, v130.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.h, v18.h, v131.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v19.l, v131.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.h, v19.h, v129.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v20.l, v132.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.h, v20.h, v133.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v21.l, v21.l, v133.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v21.h, v21.h, v134.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v22.l, v135.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.h, v22.h, v132.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v23.l, v135.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.h, v23.h, v144.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v24.l, v144.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.h, v24.h, v134.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v25.l, v25.l, v145.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v25.h, v25.h, v146.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v26.l, v26.l, v146.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v26.h, v26.h, v147.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.l, v27.l, v148.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v27.h, v27.h, v145.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.l, v28.l, v148.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.h, v28.h, v149.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v29.l, v29.l, v149.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v29.h, v29.h, v147.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v30.l, v30.l, v150.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v30.h, v30.h, v150.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v31.l, v31.l, v151.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v31.h, v31.h, v151.h
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr67_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr68_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr71_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr69_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr83_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr85_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr96_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr86_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr80_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr87_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr71_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr86_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr97_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr100_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr100_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr83_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr97_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr70_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr99_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr99_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr101_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr102_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr103_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr101_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr112_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr113_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr113_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr103_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr115_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr115_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr116_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr116_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr117_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr114_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr118_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr118_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr119_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr114_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr128_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr128_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr130_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr130_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr131_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr131_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr129_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr132_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr133_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr133_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr134_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr132_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr135_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr144_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr144_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr134_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr145_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr146_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr147_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr148_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr145_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr148_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr149_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr149_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr147_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr150_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr150_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr151_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB48_2
+; GFX11-TRUE16-NEXT:  .LBB48_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v50.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v39.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v50.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v39.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v48.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v151.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v151.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v150.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v150.h, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v148.l, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v31.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v31.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v30.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v30.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v49.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v37.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v48.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v38.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v36.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v149.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v147.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v148.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v149.l, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v29.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v29.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v28.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v34.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v38.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v36.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v37.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v146.l, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v25.h, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v145.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v146.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v147.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v145.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v34.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v27.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v26.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v26.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v25.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v35.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v33.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v35.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v33.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v135.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v144.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v134.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v135.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v144.l, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v24.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v24.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v23.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v32.l, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(26)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v100.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v32.h, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(24)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v100.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v98.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v132.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v133.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v134.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v132.h, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v133.l, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v22.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v21.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v21.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v20.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(22)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v97.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v85.h, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(20)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v96.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v86.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v20.h, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(18)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v87.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v131.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v129.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v130.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v131.l, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v19.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v19.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v18.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v71.h, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(16)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v84.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v80.h, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(14)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v96.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v130.l, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v117.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v128.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v129.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v119.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v86.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v17.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v16.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v16.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(12)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v85.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v80.l, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(10)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v84.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v82.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v128.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v119.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v114.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v118.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v118.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.h, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(8)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v83.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v69.l, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(6)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v71.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v69.h, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v70.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v117.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v114.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v116.l, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v116.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v115.l, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v68.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v68.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v66.l, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v67.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v66.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v115.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v113.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v103.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v112.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v113.l, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.h, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v67.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v54.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v65.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v64.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v65.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v112.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v101.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v102.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v103.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v101.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v64.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v55.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v52.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v55.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v53.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v102.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v99.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v87.l, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v98.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v99.l, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v54.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v49.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v53.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v51.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v52.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v51.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v97.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v70.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v82.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v32.l, v83.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v32.h, v81.l, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v33.l, v81.h, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, 0x300, v32.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v32.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, 0x300, v33.l
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v128i8_to_v64i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s32 offset:580
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v41, s32 offset:576
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v42, s32 offset:572
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v43, s32 offset:568
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v44, s32 offset:564
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v45, s32 offset:560
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v46, s32 offset:556
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v47, s32 offset:552
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v56, s32 offset:548
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v57, s32 offset:544
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v58, s32 offset:540
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v59, s32 offset:536
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v60, s32 offset:532
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v61, s32 offset:528
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v62, s32 offset:524
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v63, s32 offset:520
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v72, s32 offset:516
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v73, s32 offset:512
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v74, s32 offset:508
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v75, s32 offset:504
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v76, s32 offset:500
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v77, s32 offset:496
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v78, s32 offset:492
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v79, s32 offset:488
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v88, s32 offset:484
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v89, s32 offset:480
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v90, s32 offset:476
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v91, s32 offset:472
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v92, s32 offset:468
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v93, s32 offset:464
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v94, s32 offset:460
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v95, s32 offset:456
+; GFX11-FAKE16-NEXT:    s_clause 0xf
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v104, s32 offset:452
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v105, s32 offset:448
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v106, s32 offset:444
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v107, s32 offset:440
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v108, s32 offset:436
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v109, s32 offset:432
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v110, s32 offset:428
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v111, s32 offset:424
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v120, s32 offset:420
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v121, s32 offset:416
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v122, s32 offset:412
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v123, s32 offset:408
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v124, s32 offset:404
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v125, s32 offset:400
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v126, s32 offset:396
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v127, s32 offset:392
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v37, v30 :: v_dual_mov_b32 v54, v24
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v55, v28 :: v_dual_mov_b32 v52, v26
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v50, v22 :: v_dual_mov_b32 v53, v20
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v34, v18 :: v_dual_mov_b32 v51, v16
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v36, v14 :: v_dual_mov_b32 v49, v12
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v32, v10 :: v_dual_mov_b32 v39, v4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v48, v8 :: v_dual_mov_b32 v33, v6
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v35, v2 :: v_dual_mov_b32 v38, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v0, off, s32 offset:384
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v118, off, s32 offset:380
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32 offset:376
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v134, off, s32 offset:372
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v4, off, s32 offset:368
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v116, off, s32 offset:364
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v6, off, s32 offset:360
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v131, off, s32 offset:356
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v8, off, s32 offset:352
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v98, off, s32 offset:348
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v10, off, s32 offset:344
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v129, off, s32 offset:340
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v12, off, s32 offset:336
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v99, off, s32 offset:332
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v14, off, s32 offset:328
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v112, off, s32 offset:324
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v16, off, s32 offset:320
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v81, off, s32 offset:316
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v18, off, s32 offset:312
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v103, off, s32 offset:308
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v20, off, s32 offset:304
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v86, off, s32 offset:300
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v22, off, s32 offset:296
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v101, off, s32 offset:292
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v24, off, s32 offset:288
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v83, off, s32 offset:284
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v26, off, s32 offset:280
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v97, off, s32 offset:276
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v28, off, s32 offset:272
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v67, off, s32 offset:268
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v30, off, s32 offset:264
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v85, off, s32 offset:260
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v31, off, s32 offset:256
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v68, off, s32 offset:252
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v94, off, s32 offset:248
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v80, off, s32 offset:244
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v88, off, s32 offset:240
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v64, off, s32 offset:236
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v93, off, s32 offset:232
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v69, off, s32 offset:228
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v91, off, s32 offset:224
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v65, off, s32 offset:220
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v92, off, s32 offset:216
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v150, off, s32 offset:388
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v182, off, s32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v40, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v43, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v44, off, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v45, off, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v46, off, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v47, off, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v56, off, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v58, off, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v59, off, s32 offset:72
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v60, off, s32 offset:80
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v61, off, s32 offset:88
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v62, off, s32 offset:96
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v63, off, s32 offset:104
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v72, off, s32 offset:112
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v73, off, s32 offset:120
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v74, off, s32 offset:128
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v75, off, s32 offset:136
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v76, off, s32 offset:144
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v77, off, s32 offset:152
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v78, off, s32 offset:160
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v79, off, s32 offset:168
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v89, off, s32 offset:176
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v90, off, s32 offset:184
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v95, off, s32 offset:192
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v104, off, s32 offset:200
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v105, off, s32 offset:208
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v42, off, s32 offset:212
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v180, off, s32 offset:204
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v183, off, s32 offset:196
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v165, off, s32 offset:188
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v179, off, s32 offset:180
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v163, off, s32 offset:172
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v177, off, s32 offset:164
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v145, off, s32 offset:156
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v166, off, s32 offset:148
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v148, off, s32 offset:140
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v151, off, s32 offset:132
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v164, off, s32 offset:124
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v178, off, s32 offset:116
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v146, off, s32 offset:108
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v162, off, s32 offset:100
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v144, off, s32 offset:92
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v149, off, s32 offset:84
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v119, off, s32 offset:76
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v147, off, s32 offset:68
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v130, off, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v135, off, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v117, off, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v133, off, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v96, off, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v114, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v87, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v102, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v70, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v71, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v84, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v82, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v115, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v66, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v128, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v113, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v132, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v100, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v161, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v160, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v176, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v167, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v181, 8, v29
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(62)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v127, 8, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v126, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v124, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v125, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v120, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v123, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v121, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v122, 8, v14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v106, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v111, 8, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v109, 8, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v110, 8, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v107, 8, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v108, 8, v26
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(61)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v88, 8, v88
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(59)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v93, 8, v93
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(57)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v91, 8, v91
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(55)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v92, 8, v92
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(54)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v150
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(53)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v150, 8, v182
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(52)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v41, 8, v40
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(51)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v40, 8, v43
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(50)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v43, 8, v44
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(49)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v182, 8, v45
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(48)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v46, 8, v46
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(47)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v45, 8, v47
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(46)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v57, 8, v56
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(45)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v56, 8, v58
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(44)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v58, 8, v59
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(43)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v44, 8, v60
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(42)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v60, 8, v61
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(41)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v59, 8, v62
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(40)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v62, 8, v63
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(39)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v47, 8, v72
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(38)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v72, 8, v73
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(37)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v63, 8, v74
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(36)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v74, 8, v75
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(35)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v73, 8, v76
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(34)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v75, 8, v77
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v61, 8, v78
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(32)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v78, 8, v79
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v77, 8, v89
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(30)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v79, 8, v90
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(29)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v76, 8, v95
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(28)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v90, 8, v104
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(27)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v89, 8, v105
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v104, 8, v94
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v95, 8, v31
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v105, 8, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v94, 8, v28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB48_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v38
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v48
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v70
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v71
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v84
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v82
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v51
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v49
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v53
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v50
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v52
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v115
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v66
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v128
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v113
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v132
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v100
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v161
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v160
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v176
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v167
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v4, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v5, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v7, v6, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v9, v8, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v11, v10, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v37
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v102
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v87
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v114
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v96
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v133
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v117
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v135
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v130
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v181
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v150
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v41
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v40
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v43
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v182
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v46
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v45
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v57
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v56
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v8, v7, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v10, v9, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v12, v11, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v14, v13, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v16, v15, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v147
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v119
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v149
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v144
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v162
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v146
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v178
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v164
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v151
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v148
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v58
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v44
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v60
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v59
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v62
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v17, v47
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v18, v72
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v19, v63
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v74
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v21, v73
+; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v13, v12, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v15, v14, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v17, v16, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v19, v18, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v16, v21, v20, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v166
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v145
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v177
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v163
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v179
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v165
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v183
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v180
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v42
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v17, v75
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v18, v61
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v19, v78
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v77
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v21, v79
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v22, v76
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v23, v90
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v24, v89
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v92
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v26, v91
+; GFX11-FAKE16-NEXT:    v_perm_b32 v17, v18, v17, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v18, v20, v19, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v19, v22, v21, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v20, v24, v23, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v21, v26, v25, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v69
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v64
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v68
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v67
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v97
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v83
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v101
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v86
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v22, v93
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v23, v88
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v24, v104
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v95
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v26, v105
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v27, v94
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v28, v108
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v29, v107
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v30, v110
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v31, v109
+; GFX11-FAKE16-NEXT:    v_perm_b32 v22, v23, v22, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v23, v25, v24, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v24, v27, v26, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v25, v29, v28, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v26, v31, v30, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xff, v103
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v81
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xff, v112
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v99
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xff, v129
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v32, 0xff, v98
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xff, v131
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v34, 0xff, v116
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xff, v134
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v36, 0xff, v118
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, v27, v111
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, v28, v106
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v29, v29, v122
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, v30, v121
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, v31, v123
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v32, v32, v120
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v33, v33, v125
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v34, v34, v124
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, v35, v126
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, v36, v127
+; GFX11-FAKE16-NEXT:    v_perm_b32 v27, v28, v27, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v28, v30, v29, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v29, v32, v31, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v30, v34, v33, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v31, v36, v35, 0x5040100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr133
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr135
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr130
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr147
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr149
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr144
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr162
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr146
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr178
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr164
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr151
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr148
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr166
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr177
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr163
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr179
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr165
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr183
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr180
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr42
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr131
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr134
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr161
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr160
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr176
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr167
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr181
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr150
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr41
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr40
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr43
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr182
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr46
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr45
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr57
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr56
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr58
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr44
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr60
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr59
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr62
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr47
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr72
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr63
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr74
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr73
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr75
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr61
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr78
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr77
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr79
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr76
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr90
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr89
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr92
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr91
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr93
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr88
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr104
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr95
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr105
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr94
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr108
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr107
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr110
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr109
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr111
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr106
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr122
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr121
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr123
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr120
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr125
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr124
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr126
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr127
+; GFX11-FAKE16-NEXT:  .LBB48_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB48_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v134, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v118, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v131, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v116, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v129, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v35, v35, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v126, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v127, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v125, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v124, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v33, v33, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v31, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v98, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v116, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v30, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v98, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v112, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v99, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v103, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v123, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v120, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v122, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v29, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v121, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v99, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v111, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v28, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v81, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v81, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v101, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v27, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v86, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v97, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v83, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v106, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v110, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v109, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v83, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v108, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v26, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v107, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v86, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v85, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v25, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v67, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v67, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v80, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v68, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v69, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v105, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v94, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v104, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v24, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v95, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v68, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v93, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v23, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v64, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v64, 0x300, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(26)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v42, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v65, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(24)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v183, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v180, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v88, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v92, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v91, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v65, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v90, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v89, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v69, 0x300, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(22)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v179, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v165, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v80, 0x300, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(20)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v177, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v163, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(18)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v166, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v79, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v76, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v78, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v77, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v85, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v75, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v145, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v97, 0x300, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(16)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v151, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v148, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(14)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v178, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v164, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v61, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v74, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v73, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v101, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v72, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v63, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v103, 0x300, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(12)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v162, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v146, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v112, 0x300, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(10)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v149, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v144, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(8)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v147, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v62, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v47, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v60, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v59, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v118, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v58, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v119, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v119, 0x300, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(6)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v135, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v130, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(4)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v133, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v117, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v44, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v57, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v56, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v117, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v46, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v45, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v129, 0x300, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v114, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v96, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v96, 0x300, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v102, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v87, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v55, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v43, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v182, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v41, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v40, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v55, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v181, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v37, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v37, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v54, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v52, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v53, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v50, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v150, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v176, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v167, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v50, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v161, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v160, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v52, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v51, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v49, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v49, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v48, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v34, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v36, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v132, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v128, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v115, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v34, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v100, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v113, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v39, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v36, v38, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v32, v32, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v36, 0xff, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v32, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, v71, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v33, v82, v33
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v84, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, v70, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v32, v66, v32
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v35, 0x300, v35
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v33, 0x300, v33
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v38, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v36
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v32, 0x300, v32
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v36, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v39, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v33, v38, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v35, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v32, v4, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v36, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v39, v34, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v49, v5, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v52, v6, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v50, v7, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v37, v8, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v55, v9, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v96, v10, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v129, v11, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v117, v12, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v119, v13, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v118, v14, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v112, v15, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v16, v103, v16, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v17, v101, v17, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v18, v97, v18, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v19, v85, v19, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v20, v80, v20, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v21, v69, v21, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v22, v65, v22, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v23, v64, v23, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v24, v68, v24, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v25, v67, v25, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v26, v86, v26, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v27, v83, v27, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v28, v81, v28, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v29, v99, v29, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v30, v98, v30, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v31, v116, v31, 0x5040100
+; GFX11-FAKE16-NEXT:  .LBB48_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v127, off, s32 offset:392
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v126, off, s32 offset:396
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v125, off, s32 offset:400
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v124, off, s32 offset:404
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v123, off, s32 offset:408
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v122, off, s32 offset:412
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v121, off, s32 offset:416
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v120, off, s32 offset:420
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v111, off, s32 offset:424
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v110, off, s32 offset:428
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v109, off, s32 offset:432
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v108, off, s32 offset:436
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v107, off, s32 offset:440
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v106, off, s32 offset:444
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v105, off, s32 offset:448
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v104, off, s32 offset:452
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v95, off, s32 offset:456
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v94, off, s32 offset:460
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v93, off, s32 offset:464
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v92, off, s32 offset:468
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v91, off, s32 offset:472
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v90, off, s32 offset:476
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v89, off, s32 offset:480
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v88, off, s32 offset:484
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v79, off, s32 offset:488
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v78, off, s32 offset:492
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v77, off, s32 offset:496
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v76, off, s32 offset:500
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v75, off, s32 offset:504
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v74, off, s32 offset:508
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v73, off, s32 offset:512
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v72, off, s32 offset:516
+; GFX11-FAKE16-NEXT:    s_clause 0xf
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v63, off, s32 offset:520
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v62, off, s32 offset:524
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v61, off, s32 offset:528
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v60, off, s32 offset:532
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v59, off, s32 offset:536
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v58, off, s32 offset:540
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v57, off, s32 offset:544
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v56, off, s32 offset:548
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v47, off, s32 offset:552
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v46, off, s32 offset:556
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v45, off, s32 offset:560
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v44, off, s32 offset:564
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v43, off, s32 offset:568
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v42, off, s32 offset:572
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v41, off, s32 offset:576
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s32 offset:580
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -95300,532 +107703,1071 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v64bf16_to_v64f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_b32 v32, off, s32 offset:4
-; GFX11-NEXT:    scratch_load_b32 v31, off, s32
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v32
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB49_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v33, 16, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v32, 16, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v69, 16, v2
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v71, 16, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
-; GFX11-NEXT:    v_dual_add_f32 v69, 0x40c00000, v69 :: v_dual_lshlrev_b32 v70, 16, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v81, 16, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v37, v33, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v32
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-NEXT:    v_lshlrev_b32_e32 v83, 16, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v85, 16, v10
-; GFX11-NEXT:    v_add3_u32 v37, v37, v33, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff0000, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v87, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v35, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xffff0000, v18
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v16
-; GFX11-NEXT:    v_bfe_u32 v16, v32, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v87, 0x40c00000, v87
-; GFX11-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v39, 0x400000, v34
-; GFX11-NEXT:    v_add3_u32 v16, v16, v32, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff0000, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v80, 16, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v82, 16, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v84, 16, v9
-; GFX11-NEXT:    v_cndmask_b32_e32 v16, v16, v38, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v36, 0x40c00000, v17
-; GFX11-NEXT:    v_bfe_u32 v17, v34, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add_f32_e32 v38, 0x40c00000, v18
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v19
-; GFX11-NEXT:    v_lshlrev_b32_e32 v86, 16, v11
-; GFX11-NEXT:    v_add3_u32 v17, v17, v34, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v34, v36, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v17, v39, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v17, 0x400000, v33
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-NEXT:    v_add3_u32 v33, v34, v36, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v34, 0x400000, v36
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v17, v37, v17, vcc_lo
-; GFX11-NEXT:    v_bfe_u32 v37, v35, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v34, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v39, 0x40c00000, v18
-; GFX11-NEXT:    v_add3_u32 v34, v37, v35, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v37, v38, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff0000, v19
-; GFX11-NEXT:    v_perm_b32 v17, v33, v17, 0x7060302
-; GFX11-NEXT:    v_perm_b32 v16, v32, v16, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v18, v34, v36, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v34, v37, v38, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v36, v39, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v37, 0x40c00000, v19
-; GFX11-NEXT:    v_or_b32_e32 v35, 0x400000, v38
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v38, v38
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xffff0000, v20
-; GFX11-NEXT:    v_bfe_u32 v38, v37, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v34, v34, v35, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v35, v36, v39, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v39
-; GFX11-NEXT:    v_add_f32_e32 v48, 0x40c00000, v19
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v39, v39
-; GFX11-NEXT:    v_add_f32_e32 v39, 0x40c00000, v20
-; GFX11-NEXT:    v_perm_b32 v18, v34, v18, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v19, v35, v36, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v35, v38, v37, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v37
-; GFX11-NEXT:    v_bfe_u32 v38, v48, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v37, v37
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v21
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v48
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xffff0000, v21
-; GFX11-NEXT:    v_cndmask_b32_e32 v35, v35, v36, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v36, v38, v48, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v38, v39, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v48, v48
-; GFX11-NEXT:    v_dual_add_f32 v49, 0x40c00000, v20 :: v_dual_add_f32 v48, 0x40c00000, v21
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xffff0000, v22
-; GFX11-NEXT:    v_cndmask_b32_e32 v20, v36, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v36, v38, v39, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v39
-; GFX11-NEXT:    v_bfe_u32 v38, v49, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v39, v39
-; GFX11-NEXT:    v_bfe_u32 v39, v48, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v50, 0x40c00000, v21
-; GFX11-NEXT:    v_perm_b32 v19, v35, v19, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v36, v36, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v37, v38, v49, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v49
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v49, v49
-; GFX11-NEXT:    v_dual_add_f32 v49, 0x40c00000, v22 :: v_dual_lshlrev_b32 v22, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11-NEXT:    v_perm_b32 v20, v36, v20, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v21, v37, v38, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v37, v39, v48, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v48
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v48, v48
-; GFX11-NEXT:    v_bfe_u32 v48, v49, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v51, 0x40c00000, v22
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v37, v37, v38, vcc_lo
-; GFX11-NEXT:    v_bfe_u32 v39, v50, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v50, v50
-; GFX11-NEXT:    v_perm_b32 v21, v37, v21, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v38, v39, v50, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v39, 0x400000, v50
-; GFX11-NEXT:    v_add_f32_e32 v50, 0x40c00000, v23
-; GFX11-NEXT:    v_cndmask_b32_e32 v22, v38, v39, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v38, v48, v49, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v39, 0x400000, v49
-; GFX11-NEXT:    v_bfe_u32 v48, v51, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v49, v49
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v24
-; GFX11-NEXT:    v_bfe_u32 v49, v50, 16, 1
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xffff0000, v24
-; GFX11-NEXT:    v_cndmask_b32_e32 v38, v38, v39, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v39, v48, v51, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v48, 0x400000, v51
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v51, v51
-; GFX11-NEXT:    v_dual_add_f32 v52, 0x40c00000, v23 :: v_dual_add_f32 v51, 0x40c00000, v24
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xffff0000, v25
-; GFX11-NEXT:    v_cndmask_b32_e32 v23, v39, v48, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v39, v49, v50, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v48, 0x400000, v50
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v50, v50
-; GFX11-NEXT:    v_bfe_u32 v50, v51, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v53, 0x40c00000, v24
-; GFX11-NEXT:    v_perm_b32 v22, v38, v22, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v39, v39, v48, vcc_lo
-; GFX11-NEXT:    v_bfe_u32 v49, v52, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v23, v39, v23, 0x7060302
-; GFX11-NEXT:    v_add3_u32 v48, v49, v52, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v49, 0x400000, v52
-; GFX11-NEXT:    v_add_f32_e32 v52, 0x40c00000, v25
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v24, v48, v49, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v48, v50, v51, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v49, 0x400000, v51
-; GFX11-NEXT:    v_bfe_u32 v50, v53, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v51, v51
-; GFX11-NEXT:    v_lshlrev_b32_e32 v25, 16, v26
-; GFX11-NEXT:    v_bfe_u32 v51, v52, 16, 1
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xffff0000, v26
-; GFX11-NEXT:    v_cndmask_b32_e32 v48, v48, v49, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v49, v50, v53, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v50, 0x400000, v53
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v53, v53
-; GFX11-NEXT:    v_dual_add_f32 v54, 0x40c00000, v25 :: v_dual_add_f32 v53, 0x40c00000, v26
-; GFX11-NEXT:    v_lshlrev_b32_e32 v26, 16, v27
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xffff0000, v27
-; GFX11-NEXT:    v_cndmask_b32_e32 v25, v49, v50, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v49, v51, v52, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v50, 0x400000, v52
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11-NEXT:    v_bfe_u32 v52, v53, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v55, 0x40c00000, v26
-; GFX11-NEXT:    v_perm_b32 v24, v48, v24, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v49, v49, v50, vcc_lo
-; GFX11-NEXT:    v_bfe_u32 v51, v54, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v54, v54
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v25, v49, v25, 0x7060302
-; GFX11-NEXT:    v_add3_u32 v50, v51, v54, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v51, 0x400000, v54
-; GFX11-NEXT:    v_add_f32_e32 v54, 0x40c00000, v27
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v26, v50, v51, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v50, v52, v53, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v51, 0x400000, v53
-; GFX11-NEXT:    v_bfe_u32 v52, v55, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v53, v53
-; GFX11-NEXT:    v_lshlrev_b32_e32 v27, 16, v28
-; GFX11-NEXT:    v_bfe_u32 v53, v54, 16, 1
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xffff0000, v28
-; GFX11-NEXT:    v_cndmask_b32_e32 v50, v50, v51, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v51, v52, v55, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v52, 0x400000, v55
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v55, v55
-; GFX11-NEXT:    v_dual_add_f32 v64, 0x40c00000, v27 :: v_dual_add_f32 v55, 0x40c00000, v28
-; GFX11-NEXT:    v_lshlrev_b32_e32 v28, 16, v29
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xffff0000, v29
-; GFX11-NEXT:    v_cndmask_b32_e32 v27, v51, v52, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v51, v53, v54, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v52, 0x400000, v54
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v54, v54
-; GFX11-NEXT:    v_bfe_u32 v54, v55, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v65, 0x40c00000, v28
-; GFX11-NEXT:    v_perm_b32 v26, v50, v26, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v51, v51, v52, vcc_lo
-; GFX11-NEXT:    v_bfe_u32 v53, v64, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v64, v64
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v27, v51, v27, 0x7060302
-; GFX11-NEXT:    v_add3_u32 v52, v53, v64, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v53, 0x400000, v64
-; GFX11-NEXT:    v_add_f32_e32 v64, 0x40c00000, v29
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v28, v52, v53, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v52, v54, v55, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v53, 0x400000, v55
-; GFX11-NEXT:    v_bfe_u32 v54, v65, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v55, v55
-; GFX11-NEXT:    v_lshlrev_b32_e32 v29, 16, v30
-; GFX11-NEXT:    v_bfe_u32 v55, v64, 16, 1
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xffff0000, v30
-; GFX11-NEXT:    v_cndmask_b32_e32 v52, v52, v53, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v53, v54, v65, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v54, 0x400000, v65
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v65, v65
-; GFX11-NEXT:    v_dual_add_f32 v66, 0x40c00000, v29 :: v_dual_add_f32 v65, 0x40c00000, v30
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v30, 16, v31
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xffff0000, v31
-; GFX11-NEXT:    v_cndmask_b32_e32 v29, v53, v54, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v53, v55, v64, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v54, 0x400000, v64
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v64, v64
-; GFX11-NEXT:    v_bfe_u32 v64, v65, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v67, 0x40c00000, v30
-; GFX11-NEXT:    v_perm_b32 v28, v52, v28, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v53, v53, v54, vcc_lo
-; GFX11-NEXT:    v_bfe_u32 v55, v66, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v66, v66
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v29, v53, v29, 0x7060302
-; GFX11-NEXT:    v_add3_u32 v54, v55, v66, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v55, 0x400000, v66
-; GFX11-NEXT:    v_add_f32_e32 v66, 0x40c00000, v31
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v30, v54, v55, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v54, v64, v65, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v55, 0x400000, v65
-; GFX11-NEXT:    v_bfe_u32 v64, v67, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v65, v65
-; GFX11-NEXT:    v_lshlrev_b32_e32 v31, 16, v0
-; GFX11-NEXT:    v_bfe_u32 v65, v66, 16, 1
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v54, v54, v55, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v55, v64, v67, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v64, 0x400000, v67
-; GFX11-NEXT:    v_add_f32_e32 v68, 0x40c00000, v31
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v67, v67
-; GFX11-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v67, 16, v1
-; GFX11-NEXT:    v_perm_b32 v30, v54, v30, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v31, v55, v64, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_add_f32_e32 v67, 0x40c00000, v67
-; GFX11-NEXT:    v_add3_u32 v55, v65, v66, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v64, 0x400000, v66
-; GFX11-NEXT:    v_bfe_u32 v65, v68, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v66, v66
-; GFX11-NEXT:    v_bfe_u32 v66, v0, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v55, v55, v64, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v64, v65, v68, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v65, 0x400000, v68
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v68, v68
-; GFX11-NEXT:    v_bfe_u32 v68, v67, 16, 1
-; GFX11-NEXT:    v_perm_b32 v31, v55, v31, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v64, v64, v65, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v65, v66, v0, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v66, 0x400000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_dual_cndmask_b32 v0, v65, v66 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-NEXT:    v_add3_u32 v65, v68, v67, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v66, 0x400000, v67
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v67, v67
-; GFX11-NEXT:    v_perm_b32 v0, v0, v64, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v68, v1, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v67, 0x400000, v1
-; GFX11-NEXT:    v_cndmask_b32_e32 v65, v65, v66, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v66, v68, v1, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v68, v69, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v66, v67, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v66, v68, v69, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v67, 0x400000, v69
-; GFX11-NEXT:    v_bfe_u32 v68, v2, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v69, v69
-; GFX11-NEXT:    v_perm_b32 v1, v1, v65, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v66, v66, v67, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v67, v68, v2, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v68, 0x400000, v2
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_dual_cndmask_b32 v2, v67, v68 :: v_dual_and_b32 v3, 0xffff0000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v70, 0x40c00000, v70 :: v_dual_add_f32 v3, 0x40c00000, v3
-; GFX11-NEXT:    v_perm_b32 v2, v2, v66, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v69, v70, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v68, 0x400000, v70
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v70, v70
-; GFX11-NEXT:    v_add3_u32 v67, v69, v70, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v69, v3, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v67, v67, v68, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v68, v69, v3, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v69, 0x400000, v3
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_cndmask_b32 v3, v68, v69 :: v_dual_and_b32 v4, 0xffff0000, v4
-; GFX11-NEXT:    v_dual_add_f32 v71, 0x40c00000, v71 :: v_dual_add_f32 v4, 0x40c00000, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_perm_b32 v3, v3, v67, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v70, v71, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v69, 0x400000, v71
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v71, v71
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v68, v70, v71, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v70, v4, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v68, v68, v69, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v69, v70, v4, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v70, 0x400000, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    v_dual_cndmask_b32 v4, v69, v70 :: v_dual_and_b32 v5, 0xffff0000, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v80, 0x40c00000, v80 :: v_dual_add_f32 v5, 0x40c00000, v5
-; GFX11-NEXT:    v_perm_b32 v4, v4, v68, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v71, v80, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v70, 0x400000, v80
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v80, v80
-; GFX11-NEXT:    v_add3_u32 v69, v71, v80, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v71, v5, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v69, v69, v70, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v70, v71, v5, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v71, 0x400000, v5
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_cndmask_b32 v5, v70, v71 :: v_dual_and_b32 v6, 0xffff0000, v6
-; GFX11-NEXT:    v_dual_add_f32 v81, 0x40c00000, v81 :: v_dual_add_f32 v6, 0x40c00000, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_perm_b32 v5, v5, v69, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v80, v81, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v71, 0x400000, v81
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v81, v81
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v70, v80, v81, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v80, v6, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v70, v70, v71, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v71, v80, v6, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v80, 0x400000, v6
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    v_dual_cndmask_b32 v6, v71, v80 :: v_dual_and_b32 v7, 0xffff0000, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v82, 0x40c00000, v82 :: v_dual_add_f32 v7, 0x40c00000, v7
-; GFX11-NEXT:    v_perm_b32 v6, v6, v70, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v81, v82, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v80, 0x400000, v82
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v82, v82
-; GFX11-NEXT:    v_add3_u32 v71, v81, v82, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v81, v7, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v71, v71, v80, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v80, v81, v7, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v81, 0x400000, v7
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_cndmask_b32 v7, v80, v81 :: v_dual_and_b32 v8, 0xffff0000, v8
-; GFX11-NEXT:    v_dual_add_f32 v83, 0x40c00000, v83 :: v_dual_add_f32 v8, 0x40c00000, v8
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_perm_b32 v7, v7, v71, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v82, v83, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v81, 0x400000, v83
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v83, v83
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v80, v82, v83, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v82, v8, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v80, v80, v81, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v81, v82, v8, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v82, 0x400000, v8
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-NEXT:    v_dual_cndmask_b32 v8, v81, v82 :: v_dual_and_b32 v9, 0xffff0000, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v84, 0x40c00000, v84 :: v_dual_add_f32 v9, 0x40c00000, v9
-; GFX11-NEXT:    v_perm_b32 v8, v8, v80, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v83, v84, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v82, 0x400000, v84
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v84, v84
-; GFX11-NEXT:    v_add3_u32 v81, v83, v84, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v83, v9, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v81, v81, v82, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v82, v83, v9, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v83, 0x400000, v9
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_cndmask_b32 v9, v82, v83 :: v_dual_and_b32 v10, 0xffff0000, v10
-; GFX11-NEXT:    v_dual_add_f32 v85, 0x40c00000, v85 :: v_dual_add_f32 v10, 0x40c00000, v10
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_perm_b32 v9, v9, v81, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v84, v85, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v83, 0x400000, v85
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v85, v85
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v82, v84, v85, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v84, v10, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v82, v82, v83, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v83, v84, v10, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v84, 0x400000, v10
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    v_dual_cndmask_b32 v10, v83, v84 :: v_dual_and_b32 v11, 0xffff0000, v11
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v86, 0x40c00000, v86 :: v_dual_add_f32 v11, 0x40c00000, v11
-; GFX11-NEXT:    v_perm_b32 v10, v10, v82, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v85, v86, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v84, 0x400000, v86
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v86, v86
-; GFX11-NEXT:    v_or_b32_e32 v96, 0x400000, v11
-; GFX11-NEXT:    v_add3_u32 v83, v85, v86, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v85, v11, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_cndmask_b32 v83, v83, v84 :: v_dual_lshlrev_b32 v84, 16, v13
-; GFX11-NEXT:    v_bfe_u32 v86, v87, 16, 1
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-NEXT:    v_or_b32_e32 v97, 0x400000, v87
-; GFX11-NEXT:    v_add_f32_e32 v84, 0x40c00000, v84
-; GFX11-NEXT:    v_add3_u32 v86, v86, v87, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v87, v87
-; GFX11-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-NEXT:    v_bfe_u32 v98, v12, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v99, v84, 16, 1
-; GFX11-NEXT:    v_add3_u32 v85, v85, v11, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v86, v86, v97, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v97, 0x400000, v12
-; GFX11-NEXT:    v_add3_u32 v87, v98, v12, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v98, v99, v84, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v99, 16, v14
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-NEXT:    v_or_b32_e32 v100, 0x400000, v84
-; GFX11-NEXT:    v_bfe_u32 v101, v13, 16, 1
-; GFX11-NEXT:    v_dual_cndmask_b32 v12, v87, v97 :: v_dual_add_f32 v87, 0x40c00000, v99
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v84, v84
-; GFX11-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v97, v101, v13, 0x7fff
-; GFX11-NEXT:    v_perm_b32 v12, v12, v86, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v99, v87, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v84, v98, v100, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v98, 16, v15
-; GFX11-NEXT:    v_or_b32_e32 v101, 0x400000, v87
-; GFX11-NEXT:    v_bfe_u32 v102, v14, 16, 1
-; GFX11-NEXT:    v_add3_u32 v99, v99, v87, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v87, v87
-; GFX11-NEXT:    v_or_b32_e32 v100, 0x400000, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_add_f32 v98, 0x40c00000, v98 :: v_dual_cndmask_b32 v87, v99, v101
-; GFX11-NEXT:    v_add3_u32 v101, v102, v14, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v102, 0x400000, v14
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-NEXT:    v_bfe_u32 v103, v98, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v112, 0x400000, v98
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v14, v101, v102 :: v_dual_add_f32 v15, 0x40c00000, v15
-; GFX11-NEXT:    v_add3_u32 v103, v103, v98, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v98, v98
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v14, v14, v87, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v99, v15, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v113, 0x400000, v15
-; GFX11-NEXT:    v_cndmask_b32_e32 v98, v103, v112, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v99, v99, v15, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v15, v99, v113, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_perm_b32 v15, v15, v98, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v13, v97, v100, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-NEXT:    v_perm_b32 v13, v13, v84, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v11, v85, v96, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v11, v11, v83, 0x7060302
-; GFX11-NEXT:  .LBB49_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v64bf16_to_v64f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v32
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB49_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v32, 0xffff0000, v16
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v48, 0xffff0000, v20
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v51, 0xffff0000, v23
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v71, 0xffff0000, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v80, 0xffff0000, v5
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v32, 0x40c00000, v32
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v81, 0xffff0000, v6
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v71, 0x40c00000, v71
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v82, 0xffff0000, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v32
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v32
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v33, 0xffff0000, v17
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v83, 0xffff0000, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v84, 0xffff0000, v9
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v33, 0x40c00000, v33
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v85, 0xffff0000, v10
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v17
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v86, 0xffff0000, v11
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v87, 0xffff0000, v12
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v33, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v96, 0xffff0000, v13
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v97, 0xffff0000, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v49, 0xffff0000, v21
+; GFX11-TRUE16-NEXT:    v_add3_u32 v37, v37, v33, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v35, 0xffff0000, v18
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v16
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v32, 16, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v16, v16, v32, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v32, 0x400000, v33
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v52, 0xffff0000, v24
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v16, v16, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v34, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v54, 0xffff0000, v26
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v17, v17, v39 :: v_dual_lshlrev_b32 v26, 16, v26
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v34, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v34, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v65, 0xffff0000, v29
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v32, v37, v32 :: v_dual_lshlrev_b32 v29, 16, v29
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff0000, v19
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v35, 16, 1
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v67, 0xffff0000, v31
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v31, 16, v31
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v38, 0x40c00000, v18
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v18, v33, v34, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v37, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v34, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v37, 0x40c00000, v39
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v38, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v35, 0x400000, v38
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v80, 0x40c00000, v80
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v81, 0x40c00000, v81 :: v_dual_lshlrev_b32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v34, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v36, v38, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v37, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v38, v38
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v38, 0x40c00000, v48 :: v_dual_add_f32 v39, 0x40c00000, v19
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v48, 0x40c00000, v20
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v19, v34, v35
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v36, v37, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v35, 0x400000, v37
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v39, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v38, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v82, 0x40c00000, v82
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v83, 0x40c00000, v83 :: v_dual_lshlrev_b32 v8, 16, v8
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v34, v35, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v36, v39, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v39
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v39, v39
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v39, 0x40c00000, v49
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v49, 0x40c00000, v21
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff0000, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v20, v35, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v37, v38, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v38
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v48, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v38, v38
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v38, v39, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v50, 0x40c00000, v21
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v84, 0x40c00000, v84
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v35, v35, v36, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v36, v37, v48, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v48
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v48, v48
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v48, v49, 16, 1
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v85, 0x40c00000, v85 :: v_dual_lshlrev_b32 v10, 16, v10
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v86, 0x40c00000, v86
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v36, v36, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v37, v38, v39, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v39
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v39, v39
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.l, v36.h
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v87, 0x40c00000, v87 :: v_dual_lshlrev_b32 v12, 16, v12
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v96, 0x40c00000, v96 :: v_dual_cndmask_b32 v21, v37, v38
+; GFX11-TRUE16-NEXT:    v_add3_u32 v37, v48, v49, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v49
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v49, v49
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v48, 0x40c00000, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v98, 16, v15
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v22, v37, v38 :: v_dual_add_f32 v49, 0x40c00000, v51
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v39, v50, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v50
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v50, v50
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v51, 0x40c00000, v23 :: v_dual_add_f32 v14, 0x40c00000, v14
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v37, v39, v50, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v39, v48, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v50, v49, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v98, 0x40c00000, v98
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v101, v14, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v37, v37, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v38, v39, v48, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v48
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v48, v48
+; GFX11-TRUE16-NEXT:    v_add3_u32 v101, v101, v14, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v112, 0x400000, v14
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v102, v98, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v114, 0x400000, v98
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v23, v38, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v38, v50, v49, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v49
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v50, 0x40c00000, v52
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v48, v51, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v49, v49
+; GFX11-TRUE16-NEXT:    v_add3_u32 v102, v102, v98, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v49, v50, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v38, v38, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v39, v48, v51, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v48, 0x400000, v51
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v51, v51
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v53, 0xffff0000, v25
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v52, 0x40c00000, v24 :: v_dual_lshlrev_b32 v25, 16, v25
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v24, v39, v48, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v39, v49, v50, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v48, 0x400000, v50
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v50, v50
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v51, 0x40c00000, v53
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v49, v52, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v39, v39, v48, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v50, v51, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v48, v49, v52, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v49, 0x400000, v52
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v52, v52
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v52, 0x40c00000, v54 :: v_dual_add_f32 v53, 0x40c00000, v25
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v54, 0x40c00000, v26
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v25, v48, v49 :: v_dual_and_b32 v26, 0xffff0000, v27
+; GFX11-TRUE16-NEXT:    v_add3_u32 v48, v50, v51, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v49, 0x400000, v51
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v50, v53, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v51, v51
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v51, v52, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v48, v48, v49, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v49, v50, v53, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v50, 0x400000, v53
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v53, v53
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v53, v54, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v49, v49, v50, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v50, v51, v52, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v51, 0x400000, v52
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v52, v52
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v55, 0x40c00000, v26
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v49.l, v49.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v26, v50, v51, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v50, v53, v54, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v51, 0x400000, v54
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v54, v54
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v64, 0xffff0000, v28
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v52, v55, 16, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v54, 0x40c00000, v64 :: v_dual_add_f32 v53, 0x40c00000, v27
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v27, v50, v51, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v50, v52, v55, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v51, 0x400000, v55
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v55, v55
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v52, v53, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v55, v54, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v64, 0x40c00000, v28
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v50, v50, v51, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v51, v52, v53, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v52, 0x400000, v53
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v53, v53
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v28, v51, v52, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v51, v55, v54, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v52, 0x400000, v54
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v55, 0x40c00000, v65
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v53, v64, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v54, v54
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v54, v55, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v51, v51, v52, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v52, v53, v64, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v53, 0x400000, v64
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v64, v64
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v66, 0xffff0000, v30
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v65, 0x40c00000, v29 :: v_dual_lshlrev_b32 v30, 16, v30
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v29, v52, v53, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v52, v54, v55, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v53, 0x400000, v55
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v55, v55
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v64, 0x40c00000, v66
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v54, v65, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v52, v52, v53, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v55, v64, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v53, v54, v65, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v54, 0x400000, v65
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v65, v65
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v65, 0x40c00000, v67 :: v_dual_add_f32 v66, 0x40c00000, v30
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v67, 0x40c00000, v31
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v30, v53, v54 :: v_dual_and_b32 v31, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_add3_u32 v53, v55, v64, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v54, 0x400000, v64
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v55, v66, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v64, v64
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v64, v65, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v53, v53, v54, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v54, v55, v66, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v55, 0x400000, v66
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v66, v66
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v66, v67, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v54, v54, v55, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v55, v64, v65, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v64, 0x400000, v65
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v65, v65
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v68, 0x40c00000, v31
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v54.l, v54.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v31, v55, v64, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v55, v66, v67, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v64, 0x400000, v67
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v67, v67
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v69, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v65, v68, 16, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v67, 0x40c00000, v69 :: v_dual_add_f32 v66, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v55, v64, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v55, v65, v68, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v64, 0x400000, v68
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v68, v68
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v65, v66, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v68, v67, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v69, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v55, v55, v64, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v64, v65, v66, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v65, 0x400000, v66
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v66, v66
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v70, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v66, 0x400000, v67
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v64, v64, v65, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v65, v68, v67, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v68, v69, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v67, v67
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v67, v70, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v64.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v65, v66, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v65, v68, v69, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v68, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v66, 0x400000, v69
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v69, v69
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v69, v2, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v68, 0x40c00000, v68 :: v_dual_cndmask_b32 v65, v65, v66
+; GFX11-TRUE16-NEXT:    v_add3_u32 v66, v67, v70, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v67, 0x400000, v70
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v70, v70
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v70, v68, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.l, v65.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v66, v66, v67, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v67, v69, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v69, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v65, v1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.l, v28.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v67, v69, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v67, v70, v68, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v69, 0x400000, v68
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v70, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v68, v68
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v68, v70, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v67, v67, v69, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v69, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v70, v71, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v2, v66
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v66.l, v27.h
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v27, 0xffff, v65, v50
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v50.l, v25.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v68, v69, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v68, v70, v71, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v69, 0x400000, v71
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v70, v4, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v71, v71
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v71, v80, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v25, 0xffff, v49, v48
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v48.l, v17.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v68, v68, v69, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v69, v70, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v70, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v3, 0xffff, v3, v67
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v26, 0xffff, v66, v26
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v16, 0xffff, v48, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v4, v69, v70 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT:    v_add3_u32 v69, v71, v80, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v70, 0x400000, v80
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v80, v80
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v80, v81, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v71, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v69, v69, v70, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v70, v71, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v71, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v4, 0xffff, v4, v68
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v68.l, v0.h
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v64, v55
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v30.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v70, v71, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v70, v80, v81, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v71, 0x400000, v81
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v80, v6, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v81, v81
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v81, v82, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v29.h
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v29, 0xffff, v55, v52
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v52.l, v23.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v70, v70, v71, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v71, v80, v6, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v80, 0x400000, v6
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v28, 0xffff, v64, v51
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v51.l, v24.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v5.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v6, v71, v80 :: v_dual_add_f32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT:    v_add3_u32 v71, v81, v82, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v80, 0x400000, v82
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v82, v82
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v82, v83, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v81, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v30, 0xffff, v54, v53
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v71, v71, v80, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    v_add3_u32 v80, v81, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v81, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.l, v22.h
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v24, 0xffff, v50, v39
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v23, 0xffff, v51, v38
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v22, 0xffff, v52, v37
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v7, v80, v81, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v80, v82, v83, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v81, 0x400000, v83
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v82, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v83, v83
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v83, v84, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v37.l, v20.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v38.l, v19.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v80, v80, v81, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v81, v82, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v82, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v39.l, v18.h
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v7, 0xffff, v7, v71
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v6, 0xffff, v6, v70
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v8, v81, v82 :: v_dual_add_f32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT:    v_add3_u32 v81, v83, v84, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v82, 0x400000, v84
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v84, v84
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v84, v85, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v83, v9, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v5, 0xffff, v5, v69
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v81, v81, v82, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT:    v_add3_u32 v82, v83, v9, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v83, 0x400000, v9
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v8, 0xffff, v8, v80
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v31, 0xffff, v68, v31
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v21, 0xffff, v53, v21
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v20, 0xffff, v36, v35
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v9, v82, v83, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v82, v84, v85, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v83, 0x400000, v85
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v84, v10, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v85, v85
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v85, v86, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v19, 0xffff, v37, v34
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v18, 0xffff, v38, v33
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v82, v82, v83, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v83, v84, v10, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v84, 0x400000, v10
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v9, 0xffff, v9, v81
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v17, 0xffff, v39, v32
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v10, v83, v84 :: v_dual_add_f32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT:    v_add3_u32 v83, v85, v86, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v84, 0x400000, v86
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v86, v86
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v86, v87, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v85, v11, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v83, v83, v84, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v84, v85, v11, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v85, 0x400000, v11
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v10, 0xffff, v10, v82
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v11, v84, v85, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v84, v86, v87, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v85, 0x400000, v87
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v86, v12, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v87, v87
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v87, v96, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v84, v84, v85, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v85, v86, v12, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v86, 0x400000, v12
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v11, 0xffff, v11, v83
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v12, v85, v86 :: v_dual_add_f32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT:    v_add3_u32 v85, v87, v96, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v12.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v86, v13, 16, 1
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v14, v101, v112 :: v_dual_add_f32 v87, 0x40c00000, v97
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v98, v98
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-TRUE16-NEXT:    v_add3_u32 v86, v86, v13, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v100, 0x400000, v13
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v99, v87, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v98, v102, v114 :: v_dual_add_f32 v15, 0x40c00000, v15
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v103, 0x400000, v87
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v87, v87
+; GFX11-TRUE16-NEXT:    v_add3_u32 v99, v99, v87, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v97, 0x400000, v96
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v113, v15, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v112, 0x400000, v15
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v98.l, v98.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v87, v99, v103, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT:    v_add3_u32 v101, v113, v15, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v14.h
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v12, 0xffff, v12, v84
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v15, v101, v112, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v14, 0xffff, v14, v87
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v15, 0xffff, v98, v15
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v13, v86, v100, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v96, v96
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v85, v85, v97, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v13, 0xffff, v13, v85
+; GFX11-TRUE16-NEXT:  .LBB49_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v64bf16_to_v64f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v32
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB49_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v33, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v69, 16, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v71, 16, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v69, 0x40c00000, v69 :: v_dual_lshlrev_b32 v70, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v33, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v32
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v32
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v83, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v85, 16, v10
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v37, v33, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v87, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v35, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v16
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v32, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v87, 0x40c00000, v87
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v39, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v32, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff0000, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v80, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v82, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v84, 16, v9
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v16, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v17
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v17, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v38, 0x40c00000, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v86, 16, v11
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v17, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v36, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v17, v39, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, 0x400000, v33
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v34, v36, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v34, 0x400000, v36
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v37, v17, vcc_lo
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v34, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v39, 0x40c00000, v18
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v37, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v38, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff0000, v19
+; GFX11-FAKE16-NEXT:    v_perm_b32 v17, v33, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    v_perm_b32 v16, v32, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v34, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v37, v38, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v36, v39, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v37, 0x40c00000, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, 0x400000, v38
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v38, v38
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v37, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v34, v34, v35, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v36, v39, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v39
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v48, 0x40c00000, v19
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v39, v39
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v39, 0x40c00000, v20
+; GFX11-FAKE16-NEXT:    v_perm_b32 v18, v34, v18, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v19, v35, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v38, v37, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v37
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v48, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v48
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xffff0000, v21
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v35, v35, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v36, v38, v48, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v39, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v48, v48
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v49, 0x40c00000, v20 :: v_dual_add_f32 v48, 0x40c00000, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v20, v36, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v36, v38, v39, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v39
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v49, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v39, v39
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v39, v48, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v50, 0x40c00000, v21
+; GFX11-FAKE16-NEXT:    v_perm_b32 v19, v35, v19, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v36, v36, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v38, v49, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v49
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v49, v49
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v49, 0x40c00000, v22 :: v_dual_lshlrev_b32 v22, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xffff0000, v23
+; GFX11-FAKE16-NEXT:    v_perm_b32 v20, v36, v20, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v21, v37, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v39, v48, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v48
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v48, v48
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v48, v49, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v51, 0x40c00000, v22
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v37, v37, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v39, v50, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v50, v50
+; GFX11-FAKE16-NEXT:    v_perm_b32 v21, v37, v21, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v38, v39, v50, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v39, 0x400000, v50
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v50, 0x40c00000, v23
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v22, v38, v39, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v38, v48, v49, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v39, 0x400000, v49
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v48, v51, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v49, v49
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v24
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v49, v50, 16, 1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xffff0000, v24
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v38, v38, v39, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v39, v48, v51, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v48, 0x400000, v51
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v51, v51
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v52, 0x40c00000, v23 :: v_dual_add_f32 v51, 0x40c00000, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xffff0000, v25
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v23, v39, v48, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v39, v49, v50, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v48, 0x400000, v50
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v50, v50
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v50, v51, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v53, 0x40c00000, v24
+; GFX11-FAKE16-NEXT:    v_perm_b32 v22, v38, v22, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v39, v39, v48, vcc_lo
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v49, v52, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v52, v52
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v23, v39, v23, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add3_u32 v48, v49, v52, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v49, 0x400000, v52
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v52, 0x40c00000, v25
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v24, v48, v49, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v48, v50, v51, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v49, 0x400000, v51
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v50, v53, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v51, v51
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v26
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v51, v52, 16, 1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xffff0000, v26
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v48, v48, v49, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v49, v50, v53, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v50, 0x400000, v53
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v53, v53
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v54, 0x40c00000, v25 :: v_dual_add_f32 v53, 0x40c00000, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xffff0000, v27
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v25, v49, v50, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v49, v51, v52, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v50, 0x400000, v52
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v52, v52
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v52, v53, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v55, 0x40c00000, v26
+; GFX11-FAKE16-NEXT:    v_perm_b32 v24, v48, v24, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v49, v49, v50, vcc_lo
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v51, v54, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v54, v54
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v25, v49, v25, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add3_u32 v50, v51, v54, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v51, 0x400000, v54
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v54, 0x40c00000, v27
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v26, v50, v51, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v50, v52, v53, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v51, 0x400000, v53
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v52, v55, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v53, v53
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v28
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v53, v54, 16, 1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xffff0000, v28
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v50, v50, v51, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v51, v52, v55, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v52, 0x400000, v55
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v55, v55
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v64, 0x40c00000, v27 :: v_dual_add_f32 v55, 0x40c00000, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xffff0000, v29
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v27, v51, v52, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v51, v53, v54, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v52, 0x400000, v54
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v54, v54
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v54, v55, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v65, 0x40c00000, v28
+; GFX11-FAKE16-NEXT:    v_perm_b32 v26, v50, v26, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v51, v51, v52, vcc_lo
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v53, v64, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v64, v64
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v27, v51, v27, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add3_u32 v52, v53, v64, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v53, 0x400000, v64
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v64, 0x40c00000, v29
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v28, v52, v53, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v52, v54, v55, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v53, 0x400000, v55
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v54, v65, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v55, v55
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v30
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v55, v64, 16, 1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xffff0000, v30
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v52, v52, v53, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v53, v54, v65, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v54, 0x400000, v65
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v65, v65
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v66, 0x40c00000, v29 :: v_dual_add_f32 v65, 0x40c00000, v30
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xffff0000, v31
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v29, v53, v54, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v53, v55, v64, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v54, 0x400000, v64
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v64, v64
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v64, v65, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v67, 0x40c00000, v30
+; GFX11-FAKE16-NEXT:    v_perm_b32 v28, v52, v28, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v53, v53, v54, vcc_lo
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v55, v66, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v66, v66
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v29, v53, v29, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add3_u32 v54, v55, v66, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, 0x400000, v66
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v66, 0x40c00000, v31
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v30, v54, v55, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v54, v64, v65, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, 0x400000, v65
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v64, v67, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v65, v65
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v0
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v65, v66, 16, 1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v54, v54, v55, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v55, v64, v67, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v64, 0x400000, v67
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v68, 0x40c00000, v31
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v67, v67
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v67, 16, v1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v30, v54, v30, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v31, v55, v64, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v67, 0x40c00000, v67
+; GFX11-FAKE16-NEXT:    v_add3_u32 v55, v65, v66, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v64, 0x400000, v66
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v65, v68, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v66, v66
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v66, v0, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v55, v55, v64, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v64, v65, v68, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v65, 0x400000, v68
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v68, v68
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v68, v67, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v31, v55, v31, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v64, v64, v65, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v65, v66, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v66, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v65, v66 :: v_dual_and_b32 v1, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v65, v68, v67, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v66, 0x400000, v67
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v67, v67
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v64, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v68, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v67, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v65, v65, v66, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v66, v68, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v68, v69, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v66, v67, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v66, v68, v69, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v67, 0x400000, v69
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v68, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v69, v69
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v65, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v66, v66, v67, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v67, v68, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v68, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v67, v68 :: v_dual_and_b32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v70, 0x40c00000, v70 :: v_dual_add_f32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v66, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v69, v70, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v68, 0x400000, v70
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v70, v70
+; GFX11-FAKE16-NEXT:    v_add3_u32 v67, v69, v70, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v69, v3, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v67, v67, v68, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v68, v69, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v69, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v3, v68, v69 :: v_dual_and_b32 v4, 0xffff0000, v4
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v71, 0x40c00000, v71 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v3, v67, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v70, v71, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v69, 0x400000, v71
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v71, v71
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v68, v70, v71, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v70, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v68, v68, v69, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v69, v70, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v70, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v69, v70 :: v_dual_and_b32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v80, 0x40c00000, v80 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v4, v68, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v71, v80, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v70, 0x400000, v80
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v80, v80
+; GFX11-FAKE16-NEXT:    v_add3_u32 v69, v71, v80, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v71, v5, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v69, v69, v70, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v70, v71, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v71, 0x400000, v5
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v5, v70, v71 :: v_dual_and_b32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v81, 0x40c00000, v81 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v5, v69, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v80, v81, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v71, 0x400000, v81
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v81, v81
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v70, v80, v81, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v80, v6, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v70, v70, v71, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v71, v80, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v80, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v6, v71, v80 :: v_dual_and_b32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v82, 0x40c00000, v82 :: v_dual_add_f32 v7, 0x40c00000, v7
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v6, v70, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v81, v82, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v80, 0x400000, v82
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v82, v82
+; GFX11-FAKE16-NEXT:    v_add3_u32 v71, v81, v82, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v81, v7, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v71, v71, v80, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v80, v81, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v81, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v7, v80, v81 :: v_dual_and_b32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v83, 0x40c00000, v83 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v71, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v82, v83, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v81, 0x400000, v83
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v83, v83
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v80, v82, v83, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v82, v8, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v80, v80, v81, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v81, v82, v8, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v82, 0x400000, v8
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v8, v81, v82 :: v_dual_and_b32 v9, 0xffff0000, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v84, 0x40c00000, v84 :: v_dual_add_f32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v8, v80, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v83, v84, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v82, 0x400000, v84
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v84, v84
+; GFX11-FAKE16-NEXT:    v_add3_u32 v81, v83, v84, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v83, v9, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v81, v81, v82, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v82, v83, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v83, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v9, v82, v83 :: v_dual_and_b32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v85, 0x40c00000, v85 :: v_dual_add_f32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v9, v81, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v84, v85, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v83, 0x400000, v85
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v85, v85
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v82, v84, v85, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v84, v10, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v82, v82, v83, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v83, v84, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v84, 0x400000, v10
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v83, v84 :: v_dual_and_b32 v11, 0xffff0000, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v86, 0x40c00000, v86 :: v_dual_add_f32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v10, v82, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v85, v86, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v84, 0x400000, v86
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v86, v86
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v96, 0x400000, v11
+; GFX11-FAKE16-NEXT:    v_add3_u32 v83, v85, v86, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v85, v11, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v83, v83, v84 :: v_dual_lshlrev_b32 v84, 16, v13
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v86, v87, 16, 1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v97, 0x400000, v87
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v84, 0x40c00000, v84
+; GFX11-FAKE16-NEXT:    v_add3_u32 v86, v86, v87, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v87, v87
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v98, v12, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v99, v84, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v85, v85, v11, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v86, v86, v97, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v97, 0x400000, v12
+; GFX11-FAKE16-NEXT:    v_add3_u32 v87, v98, v12, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v98, v99, v84, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v99, 16, v14
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v100, 0x400000, v84
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v101, v13, 16, 1
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v12, v87, v97 :: v_dual_add_f32 v87, 0x40c00000, v99
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v84, v84
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v97, v101, v13, 0x7fff
+; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v12, v86, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v99, v87, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v84, v98, v100, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v98, 16, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v101, 0x400000, v87
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v102, v14, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v99, v99, v87, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v87, v87
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v100, 0x400000, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v98, 0x40c00000, v98 :: v_dual_cndmask_b32 v87, v99, v101
+; GFX11-FAKE16-NEXT:    v_add3_u32 v101, v102, v14, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v102, 0x400000, v14
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v103, v98, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v112, 0x400000, v98
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v14, v101, v102 :: v_dual_add_f32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT:    v_add3_u32 v103, v103, v98, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v98, v98
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v14, v87, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v99, v15, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v113, 0x400000, v15
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v98, v103, v112, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v99, v99, v15, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v15, v99, v113, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v15, v98, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v13, v97, v100, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v13, v84, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v85, v96, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v11, v83, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB49_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -99702,532 +112644,1120 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v64bf16_to_v64i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_b32 v32, off, s32 offset:4
-; GFX11-NEXT:    scratch_load_b32 v31, off, s32
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v32
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB51_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v33, 16, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v32, 16, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v69, 16, v2
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v71, 16, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
-; GFX11-NEXT:    v_dual_add_f32 v69, 0x40c00000, v69 :: v_dual_lshlrev_b32 v70, 16, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v81, 16, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v37, v33, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v32
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-NEXT:    v_lshlrev_b32_e32 v83, 16, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v85, 16, v10
-; GFX11-NEXT:    v_add3_u32 v37, v37, v33, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff0000, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v87, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v35, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xffff0000, v18
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v16
-; GFX11-NEXT:    v_bfe_u32 v16, v32, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v87, 0x40c00000, v87
-; GFX11-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v39, 0x400000, v34
-; GFX11-NEXT:    v_add3_u32 v16, v16, v32, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff0000, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v80, 16, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v82, 16, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v84, 16, v9
-; GFX11-NEXT:    v_cndmask_b32_e32 v16, v16, v38, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v36, 0x40c00000, v17
-; GFX11-NEXT:    v_bfe_u32 v17, v34, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add_f32_e32 v38, 0x40c00000, v18
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v19
-; GFX11-NEXT:    v_lshlrev_b32_e32 v86, 16, v11
-; GFX11-NEXT:    v_add3_u32 v17, v17, v34, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v34, v36, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v17, v39, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v17, 0x400000, v33
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-NEXT:    v_add3_u32 v33, v34, v36, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v34, 0x400000, v36
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v17, v37, v17, vcc_lo
-; GFX11-NEXT:    v_bfe_u32 v37, v35, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v35
-; GFX11-NEXT:    v_cndmask_b32_e32 v33, v33, v34, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v39, 0x40c00000, v18
-; GFX11-NEXT:    v_add3_u32 v34, v37, v35, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v37, v38, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff0000, v19
-; GFX11-NEXT:    v_perm_b32 v17, v33, v17, 0x7060302
-; GFX11-NEXT:    v_perm_b32 v16, v32, v16, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v18, v34, v36, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v34, v37, v38, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v36, v39, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v37, 0x40c00000, v19
-; GFX11-NEXT:    v_or_b32_e32 v35, 0x400000, v38
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v38, v38
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xffff0000, v20
-; GFX11-NEXT:    v_bfe_u32 v38, v37, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v34, v34, v35, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v35, v36, v39, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v39
-; GFX11-NEXT:    v_add_f32_e32 v48, 0x40c00000, v19
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v39, v39
-; GFX11-NEXT:    v_add_f32_e32 v39, 0x40c00000, v20
-; GFX11-NEXT:    v_perm_b32 v18, v34, v18, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v19, v35, v36, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v35, v38, v37, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v37
-; GFX11-NEXT:    v_bfe_u32 v38, v48, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v37, v37
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v21
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v48
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xffff0000, v21
-; GFX11-NEXT:    v_cndmask_b32_e32 v35, v35, v36, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v36, v38, v48, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v38, v39, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v48, v48
-; GFX11-NEXT:    v_dual_add_f32 v49, 0x40c00000, v20 :: v_dual_add_f32 v48, 0x40c00000, v21
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xffff0000, v22
-; GFX11-NEXT:    v_cndmask_b32_e32 v20, v36, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v36, v38, v39, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v39
-; GFX11-NEXT:    v_bfe_u32 v38, v49, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v39, v39
-; GFX11-NEXT:    v_bfe_u32 v39, v48, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v50, 0x40c00000, v21
-; GFX11-NEXT:    v_perm_b32 v19, v35, v19, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v36, v36, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v37, v38, v49, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v49
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v49, v49
-; GFX11-NEXT:    v_dual_add_f32 v49, 0x40c00000, v22 :: v_dual_lshlrev_b32 v22, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11-NEXT:    v_perm_b32 v20, v36, v20, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v21, v37, v38, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v37, v39, v48, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v48
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v48, v48
-; GFX11-NEXT:    v_bfe_u32 v48, v49, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v51, 0x40c00000, v22
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v37, v37, v38, vcc_lo
-; GFX11-NEXT:    v_bfe_u32 v39, v50, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v50, v50
-; GFX11-NEXT:    v_perm_b32 v21, v37, v21, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v38, v39, v50, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v39, 0x400000, v50
-; GFX11-NEXT:    v_add_f32_e32 v50, 0x40c00000, v23
-; GFX11-NEXT:    v_cndmask_b32_e32 v22, v38, v39, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v38, v48, v49, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v39, 0x400000, v49
-; GFX11-NEXT:    v_bfe_u32 v48, v51, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v49, v49
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v24
-; GFX11-NEXT:    v_bfe_u32 v49, v50, 16, 1
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xffff0000, v24
-; GFX11-NEXT:    v_cndmask_b32_e32 v38, v38, v39, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v39, v48, v51, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v48, 0x400000, v51
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v51, v51
-; GFX11-NEXT:    v_dual_add_f32 v52, 0x40c00000, v23 :: v_dual_add_f32 v51, 0x40c00000, v24
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xffff0000, v25
-; GFX11-NEXT:    v_cndmask_b32_e32 v23, v39, v48, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v39, v49, v50, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v48, 0x400000, v50
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v50, v50
-; GFX11-NEXT:    v_bfe_u32 v50, v51, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v53, 0x40c00000, v24
-; GFX11-NEXT:    v_perm_b32 v22, v38, v22, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v39, v39, v48, vcc_lo
-; GFX11-NEXT:    v_bfe_u32 v49, v52, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v23, v39, v23, 0x7060302
-; GFX11-NEXT:    v_add3_u32 v48, v49, v52, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v49, 0x400000, v52
-; GFX11-NEXT:    v_add_f32_e32 v52, 0x40c00000, v25
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v24, v48, v49, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v48, v50, v51, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v49, 0x400000, v51
-; GFX11-NEXT:    v_bfe_u32 v50, v53, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v51, v51
-; GFX11-NEXT:    v_lshlrev_b32_e32 v25, 16, v26
-; GFX11-NEXT:    v_bfe_u32 v51, v52, 16, 1
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xffff0000, v26
-; GFX11-NEXT:    v_cndmask_b32_e32 v48, v48, v49, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v49, v50, v53, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v50, 0x400000, v53
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v53, v53
-; GFX11-NEXT:    v_dual_add_f32 v54, 0x40c00000, v25 :: v_dual_add_f32 v53, 0x40c00000, v26
-; GFX11-NEXT:    v_lshlrev_b32_e32 v26, 16, v27
-; GFX11-NEXT:    v_and_b32_e32 v27, 0xffff0000, v27
-; GFX11-NEXT:    v_cndmask_b32_e32 v25, v49, v50, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v49, v51, v52, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v50, 0x400000, v52
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11-NEXT:    v_bfe_u32 v52, v53, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v55, 0x40c00000, v26
-; GFX11-NEXT:    v_perm_b32 v24, v48, v24, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v49, v49, v50, vcc_lo
-; GFX11-NEXT:    v_bfe_u32 v51, v54, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v54, v54
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v25, v49, v25, 0x7060302
-; GFX11-NEXT:    v_add3_u32 v50, v51, v54, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v51, 0x400000, v54
-; GFX11-NEXT:    v_add_f32_e32 v54, 0x40c00000, v27
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v26, v50, v51, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v50, v52, v53, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v51, 0x400000, v53
-; GFX11-NEXT:    v_bfe_u32 v52, v55, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v53, v53
-; GFX11-NEXT:    v_lshlrev_b32_e32 v27, 16, v28
-; GFX11-NEXT:    v_bfe_u32 v53, v54, 16, 1
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xffff0000, v28
-; GFX11-NEXT:    v_cndmask_b32_e32 v50, v50, v51, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v51, v52, v55, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v52, 0x400000, v55
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v55, v55
-; GFX11-NEXT:    v_dual_add_f32 v64, 0x40c00000, v27 :: v_dual_add_f32 v55, 0x40c00000, v28
-; GFX11-NEXT:    v_lshlrev_b32_e32 v28, 16, v29
-; GFX11-NEXT:    v_and_b32_e32 v29, 0xffff0000, v29
-; GFX11-NEXT:    v_cndmask_b32_e32 v27, v51, v52, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v51, v53, v54, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v52, 0x400000, v54
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v54, v54
-; GFX11-NEXT:    v_bfe_u32 v54, v55, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v65, 0x40c00000, v28
-; GFX11-NEXT:    v_perm_b32 v26, v50, v26, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v51, v51, v52, vcc_lo
-; GFX11-NEXT:    v_bfe_u32 v53, v64, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v64, v64
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v27, v51, v27, 0x7060302
-; GFX11-NEXT:    v_add3_u32 v52, v53, v64, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v53, 0x400000, v64
-; GFX11-NEXT:    v_add_f32_e32 v64, 0x40c00000, v29
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v28, v52, v53, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v52, v54, v55, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v53, 0x400000, v55
-; GFX11-NEXT:    v_bfe_u32 v54, v65, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v55, v55
-; GFX11-NEXT:    v_lshlrev_b32_e32 v29, 16, v30
-; GFX11-NEXT:    v_bfe_u32 v55, v64, 16, 1
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xffff0000, v30
-; GFX11-NEXT:    v_cndmask_b32_e32 v52, v52, v53, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v53, v54, v65, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v54, 0x400000, v65
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v65, v65
-; GFX11-NEXT:    v_dual_add_f32 v66, 0x40c00000, v29 :: v_dual_add_f32 v65, 0x40c00000, v30
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v30, 16, v31
-; GFX11-NEXT:    v_and_b32_e32 v31, 0xffff0000, v31
-; GFX11-NEXT:    v_cndmask_b32_e32 v29, v53, v54, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v53, v55, v64, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v54, 0x400000, v64
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v64, v64
-; GFX11-NEXT:    v_bfe_u32 v64, v65, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v67, 0x40c00000, v30
-; GFX11-NEXT:    v_perm_b32 v28, v52, v28, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v53, v53, v54, vcc_lo
-; GFX11-NEXT:    v_bfe_u32 v55, v66, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v66, v66
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v29, v53, v29, 0x7060302
-; GFX11-NEXT:    v_add3_u32 v54, v55, v66, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v55, 0x400000, v66
-; GFX11-NEXT:    v_add_f32_e32 v66, 0x40c00000, v31
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v30, v54, v55, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v54, v64, v65, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v55, 0x400000, v65
-; GFX11-NEXT:    v_bfe_u32 v64, v67, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v65, v65
-; GFX11-NEXT:    v_lshlrev_b32_e32 v31, 16, v0
-; GFX11-NEXT:    v_bfe_u32 v65, v66, 16, 1
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v54, v54, v55, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v55, v64, v67, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v64, 0x400000, v67
-; GFX11-NEXT:    v_add_f32_e32 v68, 0x40c00000, v31
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v67, v67
-; GFX11-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v67, 16, v1
-; GFX11-NEXT:    v_perm_b32 v30, v54, v30, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v31, v55, v64, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_add_f32_e32 v67, 0x40c00000, v67
-; GFX11-NEXT:    v_add3_u32 v55, v65, v66, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v64, 0x400000, v66
-; GFX11-NEXT:    v_bfe_u32 v65, v68, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v66, v66
-; GFX11-NEXT:    v_bfe_u32 v66, v0, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v55, v55, v64, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v64, v65, v68, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v65, 0x400000, v68
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v68, v68
-; GFX11-NEXT:    v_bfe_u32 v68, v67, 16, 1
-; GFX11-NEXT:    v_perm_b32 v31, v55, v31, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v64, v64, v65, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v65, v66, v0, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v66, 0x400000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_dual_cndmask_b32 v0, v65, v66 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-NEXT:    v_add3_u32 v65, v68, v67, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v66, 0x400000, v67
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v67, v67
-; GFX11-NEXT:    v_perm_b32 v0, v0, v64, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v68, v1, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v67, 0x400000, v1
-; GFX11-NEXT:    v_cndmask_b32_e32 v65, v65, v66, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v66, v68, v1, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v68, v69, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v66, v67, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v66, v68, v69, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v67, 0x400000, v69
-; GFX11-NEXT:    v_bfe_u32 v68, v2, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v69, v69
-; GFX11-NEXT:    v_perm_b32 v1, v1, v65, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v66, v66, v67, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v67, v68, v2, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v68, 0x400000, v2
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_dual_cndmask_b32 v2, v67, v68 :: v_dual_and_b32 v3, 0xffff0000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v70, 0x40c00000, v70 :: v_dual_add_f32 v3, 0x40c00000, v3
-; GFX11-NEXT:    v_perm_b32 v2, v2, v66, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v69, v70, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v68, 0x400000, v70
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v70, v70
-; GFX11-NEXT:    v_add3_u32 v67, v69, v70, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v69, v3, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v67, v67, v68, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v68, v69, v3, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v69, 0x400000, v3
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_cndmask_b32 v3, v68, v69 :: v_dual_and_b32 v4, 0xffff0000, v4
-; GFX11-NEXT:    v_dual_add_f32 v71, 0x40c00000, v71 :: v_dual_add_f32 v4, 0x40c00000, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_perm_b32 v3, v3, v67, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v70, v71, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v69, 0x400000, v71
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v71, v71
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v68, v70, v71, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v70, v4, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v68, v68, v69, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v69, v70, v4, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v70, 0x400000, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    v_dual_cndmask_b32 v4, v69, v70 :: v_dual_and_b32 v5, 0xffff0000, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v80, 0x40c00000, v80 :: v_dual_add_f32 v5, 0x40c00000, v5
-; GFX11-NEXT:    v_perm_b32 v4, v4, v68, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v71, v80, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v70, 0x400000, v80
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v80, v80
-; GFX11-NEXT:    v_add3_u32 v69, v71, v80, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v71, v5, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v69, v69, v70, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v70, v71, v5, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v71, 0x400000, v5
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_cndmask_b32 v5, v70, v71 :: v_dual_and_b32 v6, 0xffff0000, v6
-; GFX11-NEXT:    v_dual_add_f32 v81, 0x40c00000, v81 :: v_dual_add_f32 v6, 0x40c00000, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_perm_b32 v5, v5, v69, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v80, v81, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v71, 0x400000, v81
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v81, v81
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v70, v80, v81, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v80, v6, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v70, v70, v71, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v71, v80, v6, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v80, 0x400000, v6
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    v_dual_cndmask_b32 v6, v71, v80 :: v_dual_and_b32 v7, 0xffff0000, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v82, 0x40c00000, v82 :: v_dual_add_f32 v7, 0x40c00000, v7
-; GFX11-NEXT:    v_perm_b32 v6, v6, v70, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v81, v82, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v80, 0x400000, v82
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v82, v82
-; GFX11-NEXT:    v_add3_u32 v71, v81, v82, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v81, v7, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v71, v71, v80, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v80, v81, v7, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v81, 0x400000, v7
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_cndmask_b32 v7, v80, v81 :: v_dual_and_b32 v8, 0xffff0000, v8
-; GFX11-NEXT:    v_dual_add_f32 v83, 0x40c00000, v83 :: v_dual_add_f32 v8, 0x40c00000, v8
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_perm_b32 v7, v7, v71, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v82, v83, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v81, 0x400000, v83
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v83, v83
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v80, v82, v83, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v82, v8, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v80, v80, v81, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v81, v82, v8, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v82, 0x400000, v8
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-NEXT:    v_dual_cndmask_b32 v8, v81, v82 :: v_dual_and_b32 v9, 0xffff0000, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v84, 0x40c00000, v84 :: v_dual_add_f32 v9, 0x40c00000, v9
-; GFX11-NEXT:    v_perm_b32 v8, v8, v80, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v83, v84, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v82, 0x400000, v84
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v84, v84
-; GFX11-NEXT:    v_add3_u32 v81, v83, v84, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v83, v9, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v81, v81, v82, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v82, v83, v9, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v83, 0x400000, v9
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_cndmask_b32 v9, v82, v83 :: v_dual_and_b32 v10, 0xffff0000, v10
-; GFX11-NEXT:    v_dual_add_f32 v85, 0x40c00000, v85 :: v_dual_add_f32 v10, 0x40c00000, v10
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_perm_b32 v9, v9, v81, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v84, v85, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v83, 0x400000, v85
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v85, v85
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v82, v84, v85, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v84, v10, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v82, v82, v83, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v83, v84, v10, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v84, 0x400000, v10
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    v_dual_cndmask_b32 v10, v83, v84 :: v_dual_and_b32 v11, 0xffff0000, v11
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v86, 0x40c00000, v86 :: v_dual_add_f32 v11, 0x40c00000, v11
-; GFX11-NEXT:    v_perm_b32 v10, v10, v82, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v85, v86, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v84, 0x400000, v86
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v86, v86
-; GFX11-NEXT:    v_or_b32_e32 v96, 0x400000, v11
-; GFX11-NEXT:    v_add3_u32 v83, v85, v86, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v85, v11, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_cndmask_b32 v83, v83, v84 :: v_dual_lshlrev_b32 v84, 16, v13
-; GFX11-NEXT:    v_bfe_u32 v86, v87, 16, 1
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-NEXT:    v_or_b32_e32 v97, 0x400000, v87
-; GFX11-NEXT:    v_add_f32_e32 v84, 0x40c00000, v84
-; GFX11-NEXT:    v_add3_u32 v86, v86, v87, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v87, v87
-; GFX11-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-NEXT:    v_bfe_u32 v98, v12, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v99, v84, 16, 1
-; GFX11-NEXT:    v_add3_u32 v85, v85, v11, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v86, v86, v97, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v97, 0x400000, v12
-; GFX11-NEXT:    v_add3_u32 v87, v98, v12, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v98, v99, v84, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v99, 16, v14
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-NEXT:    v_or_b32_e32 v100, 0x400000, v84
-; GFX11-NEXT:    v_bfe_u32 v101, v13, 16, 1
-; GFX11-NEXT:    v_dual_cndmask_b32 v12, v87, v97 :: v_dual_add_f32 v87, 0x40c00000, v99
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v84, v84
-; GFX11-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v97, v101, v13, 0x7fff
-; GFX11-NEXT:    v_perm_b32 v12, v12, v86, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v99, v87, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v84, v98, v100, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v98, 16, v15
-; GFX11-NEXT:    v_or_b32_e32 v101, 0x400000, v87
-; GFX11-NEXT:    v_bfe_u32 v102, v14, 16, 1
-; GFX11-NEXT:    v_add3_u32 v99, v99, v87, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v87, v87
-; GFX11-NEXT:    v_or_b32_e32 v100, 0x400000, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_add_f32 v98, 0x40c00000, v98 :: v_dual_cndmask_b32 v87, v99, v101
-; GFX11-NEXT:    v_add3_u32 v101, v102, v14, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v102, 0x400000, v14
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-NEXT:    v_bfe_u32 v103, v98, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v112, 0x400000, v98
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v14, v101, v102 :: v_dual_add_f32 v15, 0x40c00000, v15
-; GFX11-NEXT:    v_add3_u32 v103, v103, v98, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v98, v98
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v14, v14, v87, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v99, v15, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v113, 0x400000, v15
-; GFX11-NEXT:    v_cndmask_b32_e32 v98, v103, v112, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v99, v99, v15, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v15, v99, v113, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_perm_b32 v15, v15, v98, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v13, v97, v100, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-NEXT:    v_perm_b32 v13, v13, v84, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v11, v85, v96, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v11, v11, v83, 0x7060302
-; GFX11-NEXT:  .LBB51_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v64bf16_to_v64i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v32
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB51_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v32, 0xffff0000, v16
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v33, 16, v17
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff0000, v17
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v18
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v98, 16, v14
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v32, 0x40c00000, v32
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_lshlrev_b32 v16, 16, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v35, 0x40c00000, v17 :: v_dual_add_f32 v34, 0x40c00000, v34
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v32, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v32
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v39, v33, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v48, v35, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v32
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v32, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v49, 0x400000, v35
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v17, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v38, v39, v33, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v39, v48, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v16, 0x40c00000, v16
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v16, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v16
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v102, v14, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v36, v36, v16, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v32.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v32, 0x400000, v33
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v17, v36, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v35, v39, v49, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v37, v37, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v18
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v18, v38, v32, vcc_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v32.l, v35.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v35, 16, v19
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff0000, v19
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v36, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v36
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v35, 0x40c00000, v35
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v36, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v48, 0x40c00000, v19
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v35, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v33, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v34, v48, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v48
+; GFX11-TRUE16-NEXT:    v_add3_u32 v36, v36, v35, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v33.l, v33.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v19, v37, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v20
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11-TRUE16-NEXT:    v_add3_u32 v34, v34, v48, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v48, v48
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v35
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v49, 0x40c00000, v20 :: v_dual_cndmask_b32 v34, v34, v38
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v37, 0x40c00000, v37
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v34.l, v34.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v20, v36, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v36, 16, v21
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v49, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v38, v37, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v49
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v49, v49
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v48, 0x40c00000, v36
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v49, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v38, v38, v37, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v36, 0x400000, v37
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v35, v35, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff0000, v21
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v35.l, v35.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v36, v38, v36 :: v_dual_add_f32 v21, 0x40c00000, v21
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v39, v48, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v50, 0x400000, v48
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v36, 16, v36
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v21, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v49, 0x400000, v21
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT:    v_add3_u32 v39, v39, v48, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v37, v37, v21, 0x7fff
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v38, 16, v22
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v21, v37, v49 :: v_dual_and_b32 v22, 0xffff0000, v22
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v48, v48
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v51, 0x40c00000, v22 :: v_dual_lshlrev_b32 v48, 16, v23
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v38, 0x40c00000, v38
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v22, v39, v50 :: v_dual_and_b32 v23, 0xffff0000, v23
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v39, v51, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v49, 0x400000, v51
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v38, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v51, v51
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v50, 0x400000, v38
+; GFX11-TRUE16-NEXT:    v_add3_u32 v39, v39, v51, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v52, 0x40c00000, v23
+; GFX11-TRUE16-NEXT:    v_add3_u32 v37, v37, v38, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.l, v21.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v39, v39, v49, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v38, v38
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v48, 0x40c00000, v48 :: v_dual_cndmask_b32 v23, v37, v50
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v37.l, v39.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v39, 16, v24
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff0000, v24
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v49, v48, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v51, 0x400000, v48
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v53, 0x40c00000, v24
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v38, v52, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v50, 0x400000, v52
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v52, v52
+; GFX11-TRUE16-NEXT:    v_add3_u32 v49, v49, v48, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v38, v38, v52, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v39, 0x40c00000, v39 :: v_dual_cndmask_b32 v38, v38, v50
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v48, v48
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v48, v53, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v50, v39, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v52, 0x400000, v39
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v38.l, v38.h
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v24, v49, v51 :: v_dual_lshlrev_b32 v49, 16, v25
+; GFX11-TRUE16-NEXT:    v_add3_u32 v48, v48, v53, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v51, 0x400000, v53
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v53, v53
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff0000, v25
+; GFX11-TRUE16-NEXT:    v_add3_u32 v50, v50, v39, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v49, 0x40c00000, v49 :: v_dual_cndmask_b32 v48, v48, v51
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v39, v39
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v54, 0x40c00000, v25
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v39.l, v48.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v25, v50, v52, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v50, v54, 16, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v48, 16, v26
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v51, v49, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v52, 0x400000, v54
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v54, v54
+; GFX11-TRUE16-NEXT:    v_add3_u32 v50, v50, v54, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v53, 0x40c00000, v48
+; GFX11-TRUE16-NEXT:    v_add3_u32 v51, v51, v49, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v48, 0x400000, v49
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v50, v50, v52, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v49, v49
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v49, v51, v48 :: v_dual_and_b32 v26, 0xffff0000, v26
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v26, 0x40c00000, v26
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v52, v53, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v48.l, v50.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v55, 0x400000, v53
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v49, 16, v49
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v51, v26, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v54, 0x400000, v26
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-TRUE16-NEXT:    v_add3_u32 v52, v52, v53, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v51, v51, v26, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v26, v51, v54, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v53, v53
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v53, 16, v28
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v50, 16, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v27, 0xffff0000, v27
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v28, 0xffff0000, v28
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v26.l, v26.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v53, 0x40c00000, v53 :: v_dual_add_f32 v50, 0x40c00000, v50
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v64, 0x40c00000, v27
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v27, v52, v55, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v65, 0x40c00000, v28
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v51, v50, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v52, v64, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v54, 0x400000, v64
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v64, v64
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v55, 0x400000, v50
+; GFX11-TRUE16-NEXT:    v_add3_u32 v51, v51, v50, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v52, v52, v64, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v64, 0x400000, v53
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v52, v52, v54, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v54, v53, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v50, v50
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v50.l, v52.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v52, 16, v29
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v54, v54, v53, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v28, v51, v55, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v51, v65, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v29, 0xffff0000, v29
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v55, 0x400000, v65
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v65, v65
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v51, v51, v65, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v66, 0x40c00000, v29 :: v_dual_cndmask_b32 v51, v51, v55
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v53, v53
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v53, v66, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v51.l, v51.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v29, v54, v64, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v53, v53, v66, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v64, 0x400000, v66
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v66, v66
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v30
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v53, v53, v64 :: v_dual_and_b32 v30, 0xffff0000, v30
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v52, 0x40c00000, v52 :: v_dual_add_f32 v67, 0x40c00000, v30
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v55, v52, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v65, 0x400000, v52
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v52, v52
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v55, v55, v52, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v52.l, v53.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v53, 16, v31
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v30, v55, v65 :: v_dual_and_b32 v31, 0xffff0000, v31
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v55, v67, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v65, 0x400000, v67
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v67, v67
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v66, 0x40c00000, v53 :: v_dual_add_f32 v31, 0x40c00000, v31
+; GFX11-TRUE16-NEXT:    v_add3_u32 v55, v55, v67, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v67, 0x400000, v31
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v55, v55, v65 :: v_dual_add_f32 v54, 0x40c00000, v54
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v64, v54, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v53, 0x400000, v54
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v54, v54
+; GFX11-TRUE16-NEXT:    v_add3_u32 v64, v64, v54, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v54, v64, v53, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v64, v31, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.l, v55.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v55, 16, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-TRUE16-NEXT:    v_add3_u32 v64, v64, v31, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v55, 0x40c00000, v55
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v65, v66, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v68, 0x400000, v66
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v69, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v31, v64, v67, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v66, v66
+; GFX11-TRUE16-NEXT:    v_add3_u32 v65, v65, v66, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v64, v55, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v67, 0x400000, v69
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v54, 16, v54
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v31.l, v31.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v65, v68, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v65, v69, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v69, v69
+; GFX11-TRUE16-NEXT:    v_add3_u32 v64, v64, v55, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v68, 0x400000, v55
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v65, v65, v69, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v65, v65, v67, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v55, v55
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v66, 16, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v65.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v65, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v70, 0x40c00000, v1 :: v_dual_cndmask_b32 v1, v64, v68
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v66, 0x40c00000, v66 :: v_dual_add_f32 v65, 0x40c00000, v65
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v64, v70, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v68, 0x400000, v70
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v67, v66, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v70, v70
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v69, 0x400000, v66
+; GFX11-TRUE16-NEXT:    v_add3_u32 v64, v64, v70, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v71, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v67, v67, v66, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v70, 0x400000, v65
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v64, v64, v68, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v66, v66
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v66, v71, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v68, v65, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v64.h
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v2, v67, v69 :: v_dual_lshlrev_b32 v67, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v66, v66, v71, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v69, 0x400000, v71
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v71, v71
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    v_add3_u32 v68, v68, v65, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v66, v66, v69 :: v_dual_add_f32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v65, v65
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v67, 0x40c00000, v67
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.l, v66.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v66, 16, v4
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v68, v68, v70, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v70, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v69, v67, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v71, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    v_add3_u32 v70, v70, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v69, v69, v67, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v80, 0x400000, v67
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_cndmask_b32 v3, v70, v71
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v71, 16, v5
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v67, v67
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v66, 0x40c00000, v66
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v67, v69, v80, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v69, v4, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v70, v66, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v80, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v81, 0x400000, v66
+; GFX11-TRUE16-NEXT:    v_add3_u32 v69, v69, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-TRUE16-NEXT:    v_add3_u32 v70, v70, v66, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v4, v69, v80 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v80, 16, v6
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v66, v66
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v71, 0x40c00000, v71
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v66, v70, v81, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v70, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v69, v71, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v81, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_add3_u32 v70, v70, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v69, v69, v71, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v82, 0x400000, v71
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v66, 16, v66
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v70, v81, vcc_lo
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v7
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v71, v71
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v71, v6, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v80, 0x40c00000, v80
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v4, v4, 16, v66
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v69, v69, v82, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v71, v71, v6, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v82, 0x400000, v6
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v70, v80, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v83, 0x400000, v80
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v69, 16, v69
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v6, v71, v82 :: v_dual_add_f32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v82, 16, v8
+; GFX11-TRUE16-NEXT:    v_add3_u32 v70, v70, v80, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v80, v80
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v81, 0x40c00000, v81
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v80, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v70, v70, v83, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v71, v81, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v80, v80, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v83, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    v_add3_u32 v71, v71, v81, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v84, 0x400000, v81
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v70, 16, v70
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v5, v5, 16, v69
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v7, v80, v83, vcc_lo
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v83, 16, v9
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v81, v81
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v81, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v82, 0x40c00000, v82
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v66, 16, v67
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v67, 16, v68
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v71, v71, v84, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v81, v81, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v84, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v80, v82, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v85, 0x400000, v82
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v68, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v8, v81, v84 :: v_dual_add_f32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v84, 16, v10
+; GFX11-TRUE16-NEXT:    v_add3_u32 v80, v80, v82, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v82, v82
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v83, 0x40c00000, v83
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v82, v9, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v69, 16, v1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v80, v80, v85, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v81, v83, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v82, v82, v9, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v85, 0x400000, v9
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT:    v_add3_u32 v81, v81, v83, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v86, 0x400000, v83
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v6, v6, 16, v70
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v70, 16, v0
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v9, v82, v85, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v83, v83
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v84, 0x40c00000, v84
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v85, 0xffff0000, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v83, v10, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v81, v81, v86, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v82, v84, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v86, 0x400000, v10
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT:    v_add3_u32 v83, v83, v10, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v87, 0x400000, v84
+; GFX11-TRUE16-NEXT:    v_add3_u32 v82, v82, v84, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v2, v65, 16, v67
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v10, v83, v86, vcc_lo
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v86, 16, v12
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v84, v84
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v85, 0x40c00000, v85
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v84, v11, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v96, 0x400000, v11
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v82, v82, v87, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v83, v85, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v87, 0x400000, v85
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v85, v85
+; GFX11-TRUE16-NEXT:    v_add3_u32 v84, v84, v11, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT:    v_add3_u32 v83, v83, v85, 0x7fff
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v85, 16, v13
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v1, v64, 16, v68
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v0, v55, 16, v69
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v55, 16, v30
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v83, v83, v87, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v86, 0x40c00000, v86 :: v_dual_add_f32 v85, 0x40c00000, v85
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v64, 16, v29
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v65, 16, v28
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v11, v84, v96, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v84, v86, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v87, 0x400000, v86
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v96, v12, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v86, v86
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v3, v3, 16, v66
+; GFX11-TRUE16-NEXT:    v_add3_u32 v84, v84, v86, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11-TRUE16-NEXT:    v_add3_u32 v86, v96, v12, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v96, v85, 16, 1
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v66, 16, v27
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v84, v84, v87, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v87, 0x400000, v12
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v29, v52, 16, v55
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v28, v51, 16, v64
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v27, v50, 16, v65
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v12, v86, v87, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v97, v13, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v86, v96, v85, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v96, 0x40c00000, v98
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v100, 0x400000, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v87, 0x400000, v85
+; GFX11-TRUE16-NEXT:    v_add3_u32 v97, v97, v13, 0x7fff
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v98, 16, v15
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v50, 16, v25
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v51, 16, v24
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v52, 16, v23
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v98, 0x40c00000, v98 :: v_dual_add_f32 v15, 0x40c00000, v15
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v99, v96, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v101, 0x400000, v96
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v96, v96
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v103, v98, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v112, v15, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v99, v99, v96, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v113, 0x400000, v98
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v96, v99, v101, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v99, v102, v14, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v101, 0x400000, v14
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT:    v_add3_u32 v102, v103, v98, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v103, v112, v15, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v112, 0x400000, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v96, 16, v96
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v14, v99, v101, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v83.l, v83.h
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v84, 16, v84
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v14.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v15, v103, v112, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v98, v98
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v82, 16, v82
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v81, 16, v81
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v80, 16, v80
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v98, v102, v113, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v71, 16, v71
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v30, v53, 16, v54
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v53, 16, v22
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v98
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v13, v97, v100, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v85, v85
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v15.h
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v25, v48, 16, v49
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v24, v39, 16, v50
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v23, v38, 16, v51
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v85, v86, v87, vcc_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v86.l, v12.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v87.l, v13.h
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v15, v13, 16, v14
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v14, v12, 16, v96
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v12, 16, v85
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v22, v37, 16, v52
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v37, 16, v20
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v38, 16, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v39, 16, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v17
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v13, v87, 16, v12
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v12, v86, 16, v84
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v11, v83, 16, v11
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v10, v10, 16, v82
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v9, v9, 16, v81
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v8, v8, 16, v80
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v7, v7, 16, v71
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v31, v31, 16, v70
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v26, v26, 16, v66
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v21, v21, 16, v53
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v20, v35, 16, v36
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v19, v34, 16, v37
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v18, v33, 16, v38
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v17, v32, 16, v39
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v16, v16, 16, v48
+; GFX11-TRUE16-NEXT:  .LBB51_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v64bf16_to_v64i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v32
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB51_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v33, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v69, 16, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v71, 16, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v69, 0x40c00000, v69 :: v_dual_lshlrev_b32 v70, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v33, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v32
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v32
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v83, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v85, 16, v10
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v37, v33, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v87, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v35, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v16
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v32, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v87, 0x40c00000, v87
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v39, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v32, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff0000, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v80, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v82, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v84, 16, v9
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v16, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v36, 0x40c00000, v17
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v17, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v38, 0x40c00000, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v86, 16, v11
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v17, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v36, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v17, v39, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, 0x400000, v33
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v34, v36, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v34, 0x400000, v36
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v37, v17, vcc_lo
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v35, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v35
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v34, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v39, 0x40c00000, v18
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v37, v35, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v38, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff0000, v19
+; GFX11-FAKE16-NEXT:    v_perm_b32 v17, v33, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    v_perm_b32 v16, v32, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v34, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v37, v38, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v36, v39, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v37, 0x40c00000, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v35, 0x400000, v38
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v38, v38
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v37, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v34, v34, v35, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v36, v39, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v39
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v48, 0x40c00000, v19
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v39, v39
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v39, 0x40c00000, v20
+; GFX11-FAKE16-NEXT:    v_perm_b32 v18, v34, v18, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v19, v35, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v38, v37, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v37
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v48, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v48
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xffff0000, v21
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v35, v35, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v36, v38, v48, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v39, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v48, v48
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v49, 0x40c00000, v20 :: v_dual_add_f32 v48, 0x40c00000, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v20, v36, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v36, v38, v39, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v39
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v49, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v39, v39
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v39, v48, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v50, 0x40c00000, v21
+; GFX11-FAKE16-NEXT:    v_perm_b32 v19, v35, v19, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v36, v36, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v38, v49, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v49
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v49, v49
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v49, 0x40c00000, v22 :: v_dual_lshlrev_b32 v22, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xffff0000, v23
+; GFX11-FAKE16-NEXT:    v_perm_b32 v20, v36, v20, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v21, v37, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v39, v48, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v48
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v48, v48
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v48, v49, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v51, 0x40c00000, v22
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v37, v37, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v39, v50, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v50, v50
+; GFX11-FAKE16-NEXT:    v_perm_b32 v21, v37, v21, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v38, v39, v50, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v39, 0x400000, v50
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v50, 0x40c00000, v23
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v22, v38, v39, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v38, v48, v49, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v39, 0x400000, v49
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v48, v51, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v49, v49
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v24
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v49, v50, 16, 1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xffff0000, v24
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v38, v38, v39, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v39, v48, v51, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v48, 0x400000, v51
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v51, v51
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v52, 0x40c00000, v23 :: v_dual_add_f32 v51, 0x40c00000, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xffff0000, v25
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v23, v39, v48, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v39, v49, v50, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v48, 0x400000, v50
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v50, v50
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v50, v51, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v53, 0x40c00000, v24
+; GFX11-FAKE16-NEXT:    v_perm_b32 v22, v38, v22, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v39, v39, v48, vcc_lo
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v49, v52, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v52, v52
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v23, v39, v23, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add3_u32 v48, v49, v52, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v49, 0x400000, v52
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v52, 0x40c00000, v25
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v24, v48, v49, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v48, v50, v51, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v49, 0x400000, v51
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v50, v53, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v51, v51
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v26
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v51, v52, 16, 1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xffff0000, v26
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v48, v48, v49, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v49, v50, v53, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v50, 0x400000, v53
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v53, v53
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v54, 0x40c00000, v25 :: v_dual_add_f32 v53, 0x40c00000, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v27, 0xffff0000, v27
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v25, v49, v50, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v49, v51, v52, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v50, 0x400000, v52
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v52, v52
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v52, v53, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v55, 0x40c00000, v26
+; GFX11-FAKE16-NEXT:    v_perm_b32 v24, v48, v24, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v49, v49, v50, vcc_lo
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v51, v54, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v54, v54
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v25, v49, v25, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add3_u32 v50, v51, v54, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v51, 0x400000, v54
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v54, 0x40c00000, v27
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v26, v50, v51, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v50, v52, v53, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v51, 0x400000, v53
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v52, v55, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v53, v53
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v28
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v53, v54, 16, 1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xffff0000, v28
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v50, v50, v51, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v51, v52, v55, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v52, 0x400000, v55
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v55, v55
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v64, 0x40c00000, v27 :: v_dual_add_f32 v55, 0x40c00000, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v29, 0xffff0000, v29
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v27, v51, v52, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v51, v53, v54, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v52, 0x400000, v54
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v54, v54
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v54, v55, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v65, 0x40c00000, v28
+; GFX11-FAKE16-NEXT:    v_perm_b32 v26, v50, v26, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v51, v51, v52, vcc_lo
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v53, v64, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v64, v64
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v27, v51, v27, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add3_u32 v52, v53, v64, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v53, 0x400000, v64
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v64, 0x40c00000, v29
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v28, v52, v53, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v52, v54, v55, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v53, 0x400000, v55
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v54, v65, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v55, v55
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v30
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v55, v64, 16, 1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xffff0000, v30
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v52, v52, v53, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v53, v54, v65, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v54, 0x400000, v65
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v65, v65
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v66, 0x40c00000, v29 :: v_dual_add_f32 v65, 0x40c00000, v30
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v31, 0xffff0000, v31
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v29, v53, v54, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v53, v55, v64, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v54, 0x400000, v64
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v64, v64
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v64, v65, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v67, 0x40c00000, v30
+; GFX11-FAKE16-NEXT:    v_perm_b32 v28, v52, v28, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v53, v53, v54, vcc_lo
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v55, v66, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v66, v66
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v29, v53, v29, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add3_u32 v54, v55, v66, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, 0x400000, v66
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v66, 0x40c00000, v31
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v30, v54, v55, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v54, v64, v65, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v55, 0x400000, v65
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v64, v67, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v65, v65
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v0
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v65, v66, 16, 1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v54, v54, v55, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v55, v64, v67, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v64, 0x400000, v67
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v68, 0x40c00000, v31
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v67, v67
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v67, 16, v1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v30, v54, v30, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v31, v55, v64, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v67, 0x40c00000, v67
+; GFX11-FAKE16-NEXT:    v_add3_u32 v55, v65, v66, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v64, 0x400000, v66
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v65, v68, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v66, v66
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v66, v0, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v55, v55, v64, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v64, v65, v68, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v65, 0x400000, v68
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v68, v68
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v68, v67, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v31, v55, v31, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v64, v64, v65, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v65, v66, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v66, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v65, v66 :: v_dual_and_b32 v1, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v65, v68, v67, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v66, 0x400000, v67
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v67, v67
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v64, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v68, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v67, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v65, v65, v66, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v66, v68, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v68, v69, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v66, v67, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v66, v68, v69, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v67, 0x400000, v69
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v68, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v69, v69
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v65, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v66, v66, v67, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v67, v68, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v68, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v67, v68 :: v_dual_and_b32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v70, 0x40c00000, v70 :: v_dual_add_f32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v66, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v69, v70, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v68, 0x400000, v70
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v70, v70
+; GFX11-FAKE16-NEXT:    v_add3_u32 v67, v69, v70, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v69, v3, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v67, v67, v68, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v68, v69, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v69, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v3, v68, v69 :: v_dual_and_b32 v4, 0xffff0000, v4
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v71, 0x40c00000, v71 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v3, v67, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v70, v71, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v69, 0x400000, v71
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v71, v71
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v68, v70, v71, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v70, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v68, v68, v69, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v69, v70, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v70, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v69, v70 :: v_dual_and_b32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v80, 0x40c00000, v80 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v4, v68, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v71, v80, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v70, 0x400000, v80
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v80, v80
+; GFX11-FAKE16-NEXT:    v_add3_u32 v69, v71, v80, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v71, v5, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v69, v69, v70, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v70, v71, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v71, 0x400000, v5
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v5, v70, v71 :: v_dual_and_b32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v81, 0x40c00000, v81 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v5, v69, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v80, v81, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v71, 0x400000, v81
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v81, v81
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v70, v80, v81, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v80, v6, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v70, v70, v71, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v71, v80, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v80, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v6, v71, v80 :: v_dual_and_b32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v82, 0x40c00000, v82 :: v_dual_add_f32 v7, 0x40c00000, v7
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v6, v70, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v81, v82, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v80, 0x400000, v82
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v82, v82
+; GFX11-FAKE16-NEXT:    v_add3_u32 v71, v81, v82, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v81, v7, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v71, v71, v80, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v80, v81, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v81, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v7, v80, v81 :: v_dual_and_b32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v83, 0x40c00000, v83 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v71, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v82, v83, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v81, 0x400000, v83
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v83, v83
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v80, v82, v83, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v82, v8, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v80, v80, v81, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v81, v82, v8, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v82, 0x400000, v8
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v8, v81, v82 :: v_dual_and_b32 v9, 0xffff0000, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v84, 0x40c00000, v84 :: v_dual_add_f32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v8, v80, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v83, v84, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v82, 0x400000, v84
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v84, v84
+; GFX11-FAKE16-NEXT:    v_add3_u32 v81, v83, v84, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v83, v9, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v81, v81, v82, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v82, v83, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v83, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v9, v82, v83 :: v_dual_and_b32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v85, 0x40c00000, v85 :: v_dual_add_f32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v9, v81, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v84, v85, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v83, 0x400000, v85
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v85, v85
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v82, v84, v85, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v84, v10, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v82, v82, v83, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v83, v84, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v84, 0x400000, v10
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v83, v84 :: v_dual_and_b32 v11, 0xffff0000, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v86, 0x40c00000, v86 :: v_dual_add_f32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v10, v82, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v85, v86, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v84, 0x400000, v86
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v86, v86
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v96, 0x400000, v11
+; GFX11-FAKE16-NEXT:    v_add3_u32 v83, v85, v86, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v85, v11, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v83, v83, v84 :: v_dual_lshlrev_b32 v84, 16, v13
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v86, v87, 16, 1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v97, 0x400000, v87
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v84, 0x40c00000, v84
+; GFX11-FAKE16-NEXT:    v_add3_u32 v86, v86, v87, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v87, v87
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v98, v12, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v99, v84, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v85, v85, v11, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v86, v86, v97, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v97, 0x400000, v12
+; GFX11-FAKE16-NEXT:    v_add3_u32 v87, v98, v12, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v98, v99, v84, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v99, 16, v14
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v100, 0x400000, v84
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v101, v13, 16, 1
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v12, v87, v97 :: v_dual_add_f32 v87, 0x40c00000, v99
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v84, v84
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v97, v101, v13, 0x7fff
+; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v12, v86, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v99, v87, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v84, v98, v100, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v98, 16, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v101, 0x400000, v87
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v102, v14, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v99, v99, v87, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v87, v87
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v100, 0x400000, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v98, 0x40c00000, v98 :: v_dual_cndmask_b32 v87, v99, v101
+; GFX11-FAKE16-NEXT:    v_add3_u32 v101, v102, v14, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v102, 0x400000, v14
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v103, v98, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v112, 0x400000, v98
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v14, v101, v102 :: v_dual_add_f32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT:    v_add3_u32 v103, v103, v98, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v98, v98
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v14, v87, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v99, v15, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v113, 0x400000, v15
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v98, v103, v112, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v99, v99, v15, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v15, v99, v113, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v15, v98, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v13, v97, v100, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v13, v84, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v85, v96, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v11, v83, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB51_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
index c2cac55e13b09..b040e77125770 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
@@ -3,7 +3,8 @@
 ; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define <4 x float> @bitcast_v4i32_to_v4f32(<4 x i32> %a, i32 %b) {
 ; GCN-LABEL: bitcast_v4i32_to_v4f32:
@@ -1371,83 +1372,170 @@ define <4 x i32> @bitcast_v8bf16_to_v4i32(<8 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v8bf16_to_v4i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v4
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB11_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v3, 16, v3
-; GFX11-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v7, v4, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    v_bfe_u32 v9, v3, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v3
-; GFX11-NEXT:    v_add3_u32 v7, v7, v4, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT:    v_add3_u32 v9, v9, v3, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v4, v7, v8 :: v_dual_add_f32 v5, 0x40c00000, v5
-; GFX11-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v11, v5, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v5
-; GFX11-NEXT:    v_bfe_u32 v13, v2, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v9, v10, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v11, v11, v5, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff0000, v1
-; GFX11-NEXT:    v_add3_u32 v7, v13, v2, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff0000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v5, v11, v12 :: v_dual_add_f32 v6, 0x40c00000, v6
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-NEXT:    v_perm_b32 v3, v4, v3, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v9, v6, 16, 1
-; GFX11-NEXT:    v_dual_cndmask_b32 v2, v7, v8 :: v_dual_add_f32 v7, 0x40c00000, v10
-; GFX11-NEXT:    v_bfe_u32 v10, v1, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add3_u32 v8, v9, v6, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v9, 0x400000, v6
-; GFX11-NEXT:    v_bfe_u32 v11, v7, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v7
-; GFX11-NEXT:    v_perm_b32 v2, v5, v2, 0x7060302
-; GFX11-NEXT:    v_add3_u32 v11, v11, v7, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v6, v8, v9, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v9, v10, v1, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_cndmask_b32 v1, v9, v10
-; GFX11-NEXT:    v_bfe_u32 v8, v0, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    v_or_b32_e32 v13, 0x400000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v8, v8, v0, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v7, v11, v12, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_perm_b32 v1, v6, v1, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v8, v13, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v0, v7, v0, 0x7060302
-; GFX11-NEXT:  .LBB11_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v8bf16_to_v4i32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB11_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v8, v8, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v3, v8, v10 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v7, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v4, v7, v9 :: v_dual_and_b32 v5, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v3, 0xffff, v3, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v11, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v11, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, 0x400000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v13, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v11, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, 0x400000, v6
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v7, v8, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v7, v6, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v9
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v7, v6, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v2, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v9, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v10, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v13, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v10, v14, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v7, v11, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v8.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v6
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v9, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v7, v0
+; GFX11-TRUE16-NEXT:  .LBB11_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v8bf16_to_v4i32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB11_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v7, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v7, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v7, v8 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v11, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v5
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v9, v10, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v11, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v13, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v5, v11, v12 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v6, 16, 1
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v7, v8 :: v_dual_add_f32 v7, 0x40c00000, v10
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v10, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v9, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v11, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v5, v2, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v11, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v8, v9, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v10, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_cndmask_b32 v1, v9, v10
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, 0x400000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v8, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v11, v12, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v6, v1, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v8, v13, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v7, v0, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB11_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -1654,69 +1742,126 @@ define <16 x i8> @bitcast_v4i32_to_v16i8(<4 x i32> %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v12, v17
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v4i32_to_v16i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v16, v2
-; GFX11-NEXT:    v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v4
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB12_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[16:17]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[18:19]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v18
-; GFX11-NEXT:  .LBB12_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB12_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u32_e32 v19, 3, v19
-; GFX11-NEXT:    v_add_nc_u32_e32 v17, 3, v17
-; GFX11-NEXT:    v_add_nc_u32_e32 v16, 3, v16
-; GFX11-NEXT:    v_add_nc_u32_e32 v18, 3, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[16:17]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[18:19]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v18
-; GFX11-NEXT:  .LBB12_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_mov_b32_e32 v0, v18
-; GFX11-NEXT:    v_mov_b32_e32 v4, v19
-; GFX11-NEXT:    v_mov_b32_e32 v8, v16
-; GFX11-NEXT:    v_mov_b32_e32 v12, v17
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v4i32_to_v16i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v16, v2
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB12_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[16:17]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v10
+; GFX11-TRUE16-NEXT:  .LBB12_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB12_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v11, 3, v11
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v17, 3, v17
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v16, 3, v16
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v10, 3, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[16:17]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v10
+; GFX11-TRUE16-NEXT:  .LBB12_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v11.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v11.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v16.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v17.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v17.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v4i32_to_v16i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v16, v2
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB12_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[16:17]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[18:19]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v18
+; GFX11-FAKE16-NEXT:  .LBB12_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB12_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v19, 3, v19
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v17, 3, v17
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v16, 3, v16
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v18, 3, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[16:17]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[18:19]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v18
+; GFX11-FAKE16-NEXT:  .LBB12_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v18
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v19
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v16
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v12, v17
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -2032,126 +2177,260 @@ define <4 x i32> @bitcast_v16i8_to_v4i32(<16 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v16i8_to_v4i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v18, v2 :: v_dual_mov_b32 v17, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v16
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v20, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v5, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v7, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v9, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v15
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB13_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB13_4
-; GFX11-NEXT:  .LBB13_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB13_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v17
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v18
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v10
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v14
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v16
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v19
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v20
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v5
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v7
-; GFX11-NEXT:    v_or_b32_e32 v5, v6, v9
-; GFX11-NEXT:    v_or_b32_e32 v6, v8, v11
-; GFX11-NEXT:    v_or_b32_e32 v7, v10, v13
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr4
-; GFX11-NEXT:    ; implicit-def: $vgpr8
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v7
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB13_2
-; GFX11-NEXT:  .LBB13_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v17, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v18, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v4, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v6, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v8, 3
-; GFX11-NEXT:    v_add_nc_u16 v6, v10, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v12, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, v14, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v0, v16, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v19, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v20, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v5, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v7, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v9, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v11, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v13, v10
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v7
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v16i8_to_v4i32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.h, v9.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 8, v12.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.l, 8, v15.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v16
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB13_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB13_4
+; GFX11-TRUE16-NEXT:  .LBB13_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB13_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v10.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v0.h, v7.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v8.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v0.h, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v1.h, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v8, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v7, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v6, v10
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB13_2
+; GFX11-TRUE16-NEXT:  .LBB13_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v10.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v9.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v9.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v6.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v8.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v10.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v12.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v7.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v7.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v8.h, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v14.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v4.l, v1.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v4.h, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v5.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v5.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v6.l, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v8, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v9, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v5, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v10, v4
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v16i8_to_v4i32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v18, v2 :: v_dual_mov_b32 v17, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB13_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB13_4
+; GFX11-FAKE16-NEXT:  .LBB13_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB13_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v8, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v10, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB13_2
+; GFX11-FAKE16-NEXT:  .LBB13_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v17, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v18, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v4, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v6, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v8, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v10, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v12, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v14, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v16, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v19, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v20, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v5, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v9, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v11, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v13, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -3361,83 +3640,170 @@ define <4 x float> @bitcast_v8bf16_to_v4f32(<8 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v8bf16_to_v4f32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v4
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB23_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v3, 16, v3
-; GFX11-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v7, v4, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    v_bfe_u32 v9, v3, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v3
-; GFX11-NEXT:    v_add3_u32 v7, v7, v4, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT:    v_add3_u32 v9, v9, v3, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v4, v7, v8 :: v_dual_add_f32 v5, 0x40c00000, v5
-; GFX11-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v11, v5, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v5
-; GFX11-NEXT:    v_bfe_u32 v13, v2, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v9, v10, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v11, v11, v5, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff0000, v1
-; GFX11-NEXT:    v_add3_u32 v7, v13, v2, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff0000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v5, v11, v12 :: v_dual_add_f32 v6, 0x40c00000, v6
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-NEXT:    v_perm_b32 v3, v4, v3, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v9, v6, 16, 1
-; GFX11-NEXT:    v_dual_cndmask_b32 v2, v7, v8 :: v_dual_add_f32 v7, 0x40c00000, v10
-; GFX11-NEXT:    v_bfe_u32 v10, v1, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add3_u32 v8, v9, v6, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v9, 0x400000, v6
-; GFX11-NEXT:    v_bfe_u32 v11, v7, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v7
-; GFX11-NEXT:    v_perm_b32 v2, v5, v2, 0x7060302
-; GFX11-NEXT:    v_add3_u32 v11, v11, v7, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v6, v8, v9, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v9, v10, v1, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_cndmask_b32 v1, v9, v10
-; GFX11-NEXT:    v_bfe_u32 v8, v0, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    v_or_b32_e32 v13, 0x400000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v8, v8, v0, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v7, v11, v12, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_perm_b32 v1, v6, v1, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v8, v13, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v0, v7, v0, 0x7060302
-; GFX11-NEXT:  .LBB23_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v8bf16_to_v4f32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB23_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v8, v8, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v3, v8, v10 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v7, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v4, v7, v9 :: v_dual_and_b32 v5, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v3, 0xffff, v3, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v11, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v11, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, 0x400000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v13, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v11, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, 0x400000, v6
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v7, v8, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v7, v6, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v9
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v7, v6, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v2, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v9, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v10, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v13, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v10, v14, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v7, v11, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v8.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v6
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v9, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v7, v0
+; GFX11-TRUE16-NEXT:  .LBB23_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v8bf16_to_v4f32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB23_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v7, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v7, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v7, v8 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v11, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v5
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v9, v10, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v11, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v13, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v5, v11, v12 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v6, 16, 1
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v7, v8 :: v_dual_add_f32 v7, 0x40c00000, v10
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v10, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v9, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v11, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v5, v2, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v11, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v8, v9, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v10, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_cndmask_b32 v1, v9, v10
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, 0x400000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v8, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v11, v12, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v6, v1, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v8, v13, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v7, v0, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB23_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -3644,67 +4010,122 @@ define <16 x i8> @bitcast_v4f32_to_v16i8(<4 x float> %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v12, v17
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v4f32_to_v16i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v16, v2
-; GFX11-NEXT:    v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v4
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB24_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[16:17]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[18:19]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v18
-; GFX11-NEXT:  .LBB24_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB24_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_dual_add_f32 v19, 1.0, v19 :: v_dual_add_f32 v16, 1.0, v16
-; GFX11-NEXT:    v_dual_add_f32 v17, 1.0, v17 :: v_dual_add_f32 v18, 1.0, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v16
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[16:17]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[18:19]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v18
-; GFX11-NEXT:  .LBB24_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_mov_b32_e32 v0, v18
-; GFX11-NEXT:    v_mov_b32_e32 v4, v19
-; GFX11-NEXT:    v_mov_b32_e32 v8, v16
-; GFX11-NEXT:    v_mov_b32_e32 v12, v17
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v4f32_to_v16i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v16, v2
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB24_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[16:17]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v10
+; GFX11-TRUE16-NEXT:  .LBB24_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB24_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v16, 1.0, v16
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v17, 1.0, v17 :: v_dual_add_f32 v10, 1.0, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[16:17]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v10
+; GFX11-TRUE16-NEXT:  .LBB24_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v11.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v11.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v16.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v17.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v17.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v4f32_to_v16i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v16, v2
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB24_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[16:17]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[18:19]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v18
+; GFX11-FAKE16-NEXT:  .LBB24_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB24_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v19, 1.0, v19 :: v_dual_add_f32 v16, 1.0, v16
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v17, 1.0, v17 :: v_dual_add_f32 v18, 1.0, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v16
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[16:17]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[18:19]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v18
+; GFX11-FAKE16-NEXT:  .LBB24_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v18
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v19
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v16
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v12, v17
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -4020,126 +4441,260 @@ define <4 x float> @bitcast_v16i8_to_v4f32(<16 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v16i8_to_v4f32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v18, v2 :: v_dual_mov_b32 v17, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v16
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v20, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v5, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v7, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v9, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v15
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB25_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB25_4
-; GFX11-NEXT:  .LBB25_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB25_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v17
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v18
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v10
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v14
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v16
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v19
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v20
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v5
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v7
-; GFX11-NEXT:    v_or_b32_e32 v5, v6, v9
-; GFX11-NEXT:    v_or_b32_e32 v6, v8, v11
-; GFX11-NEXT:    v_or_b32_e32 v7, v10, v13
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr4
-; GFX11-NEXT:    ; implicit-def: $vgpr8
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v7
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB25_2
-; GFX11-NEXT:  .LBB25_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v17, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v18, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v4, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v6, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v8, 3
-; GFX11-NEXT:    v_add_nc_u16 v6, v10, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v12, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, v14, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v0, v16, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v19, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v20, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v5, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v7, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v9, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v11, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v13, v10
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v7
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v16i8_to_v4f32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.h, v9.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 8, v12.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.l, 8, v15.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v16
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB25_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB25_4
+; GFX11-TRUE16-NEXT:  .LBB25_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB25_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v10.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v0.h, v7.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v8.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v0.h, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v1.h, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v8, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v7, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v6, v10
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB25_2
+; GFX11-TRUE16-NEXT:  .LBB25_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v10.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v9.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v9.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v6.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v8.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v10.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v12.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v7.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v7.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v8.h, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v14.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v4.l, v1.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v4.h, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v5.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v5.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v6.l, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v8, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v9, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v5, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v10, v4
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v16i8_to_v4f32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v18, v2 :: v_dual_mov_b32 v17, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB25_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB25_4
+; GFX11-FAKE16-NEXT:  .LBB25_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB25_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v8, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v10, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB25_2
+; GFX11-FAKE16-NEXT:  .LBB25_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v17, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v18, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v4, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v6, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v8, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v10, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v12, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v14, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v16, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v19, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v20, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v5, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v9, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v11, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v13, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -5196,83 +5751,170 @@ define <2 x i64> @bitcast_v8bf16_to_v2i64(<8 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v8bf16_to_v2i64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v4
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB33_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v3, 16, v3
-; GFX11-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v7, v4, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    v_bfe_u32 v9, v3, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v3
-; GFX11-NEXT:    v_add3_u32 v7, v7, v4, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT:    v_add3_u32 v9, v9, v3, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v4, v7, v8 :: v_dual_add_f32 v5, 0x40c00000, v5
-; GFX11-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v11, v5, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v5
-; GFX11-NEXT:    v_bfe_u32 v13, v2, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v9, v10, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v11, v11, v5, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff0000, v1
-; GFX11-NEXT:    v_add3_u32 v7, v13, v2, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff0000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v5, v11, v12 :: v_dual_add_f32 v6, 0x40c00000, v6
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-NEXT:    v_perm_b32 v3, v4, v3, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v9, v6, 16, 1
-; GFX11-NEXT:    v_dual_cndmask_b32 v2, v7, v8 :: v_dual_add_f32 v7, 0x40c00000, v10
-; GFX11-NEXT:    v_bfe_u32 v10, v1, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add3_u32 v8, v9, v6, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v9, 0x400000, v6
-; GFX11-NEXT:    v_bfe_u32 v11, v7, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v7
-; GFX11-NEXT:    v_perm_b32 v2, v5, v2, 0x7060302
-; GFX11-NEXT:    v_add3_u32 v11, v11, v7, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v6, v8, v9, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v9, v10, v1, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_cndmask_b32 v1, v9, v10
-; GFX11-NEXT:    v_bfe_u32 v8, v0, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    v_or_b32_e32 v13, 0x400000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v8, v8, v0, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v7, v11, v12, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_perm_b32 v1, v6, v1, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v8, v13, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v0, v7, v0, 0x7060302
-; GFX11-NEXT:  .LBB33_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v8bf16_to_v2i64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB33_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v8, v8, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v3, v8, v10 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v7, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v4, v7, v9 :: v_dual_and_b32 v5, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v3, 0xffff, v3, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v11, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v11, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, 0x400000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v13, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v11, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, 0x400000, v6
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v7, v8, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v7, v6, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v9
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v7, v6, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v2, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v9, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v10, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v13, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v10, v14, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v7, v11, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v8.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v6
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v9, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v7, v0
+; GFX11-TRUE16-NEXT:  .LBB33_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v8bf16_to_v2i64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB33_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v7, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v7, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v7, v8 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v11, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v5
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v9, v10, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v11, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v13, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v5, v11, v12 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v6, 16, 1
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v7, v8 :: v_dual_add_f32 v7, 0x40c00000, v10
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v10, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v9, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v11, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v5, v2, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v11, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v8, v9, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v10, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_cndmask_b32 v1, v9, v10
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, 0x400000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v8, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v11, v12, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v6, v1, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v8, v13, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v7, v0, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB33_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -5479,69 +6121,126 @@ define <16 x i8> @bitcast_v2i64_to_v16i8(<2 x i64> %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v12, v17
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v2i64_to_v16i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v16, v2
-; GFX11-NEXT:    v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v4
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB34_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[16:17]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[18:19]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v18
-; GFX11-NEXT:  .LBB34_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB34_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_co_u32 v16, vcc_lo, v16, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v17, null, 0, v17, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v18, vcc_lo, v18, 3
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v19, null, 0, v19, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[16:17]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v17
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[18:19]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v18
-; GFX11-NEXT:  .LBB34_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_mov_b32_e32 v0, v18
-; GFX11-NEXT:    v_mov_b32_e32 v4, v19
-; GFX11-NEXT:    v_mov_b32_e32 v8, v16
-; GFX11-NEXT:    v_mov_b32_e32 v12, v17
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v2i64_to_v16i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v16, v2
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB34_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[16:17]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v10
+; GFX11-TRUE16-NEXT:  .LBB34_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB34_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v16, vcc_lo, v16, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v17, null, 0, v17, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v10, vcc_lo, v10, 3
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[16:17]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v10
+; GFX11-TRUE16-NEXT:  .LBB34_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v11.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v11.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v16.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v17.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v17.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v2i64_to_v16i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v16, v2
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB34_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[16:17]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[18:19]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v18
+; GFX11-FAKE16-NEXT:  .LBB34_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB34_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v16, vcc_lo, v16, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v17, null, 0, v17, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v18, vcc_lo, v18, 3
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v19, null, 0, v19, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[16:17]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[18:19]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v18
+; GFX11-FAKE16-NEXT:  .LBB34_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v18
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v19
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v16
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v12, v17
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -5857,126 +6556,260 @@ define <2 x i64> @bitcast_v16i8_to_v2i64(<16 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v16i8_to_v2i64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v18, v2 :: v_dual_mov_b32 v17, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v16
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v20, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v5, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v7, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v9, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v15
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB35_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB35_4
-; GFX11-NEXT:  .LBB35_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB35_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v17
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v18
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v10
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v14
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v16
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v19
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v20
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v5
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v7
-; GFX11-NEXT:    v_or_b32_e32 v5, v6, v9
-; GFX11-NEXT:    v_or_b32_e32 v6, v8, v11
-; GFX11-NEXT:    v_or_b32_e32 v7, v10, v13
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr4
-; GFX11-NEXT:    ; implicit-def: $vgpr8
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v7
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB35_2
-; GFX11-NEXT:  .LBB35_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v17, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v18, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v4, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v6, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v8, 3
-; GFX11-NEXT:    v_add_nc_u16 v6, v10, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v12, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, v14, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v0, v16, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v19, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v20, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v5, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v7, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v9, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v11, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v13, v10
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v7
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v16i8_to_v2i64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.h, v9.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 8, v12.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.l, 8, v15.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v16
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB35_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB35_4
+; GFX11-TRUE16-NEXT:  .LBB35_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB35_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v10.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v0.h, v7.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v8.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v0.h, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v1.h, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v8, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v7, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v6, v10
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB35_2
+; GFX11-TRUE16-NEXT:  .LBB35_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v10.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v9.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v9.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v6.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v8.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v10.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v12.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v7.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v7.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v8.h, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v14.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v4.l, v1.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v4.h, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v5.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v5.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v6.l, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v8, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v9, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v5, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v10, v4
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v16i8_to_v2i64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v18, v2 :: v_dual_mov_b32 v17, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB35_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB35_4
+; GFX11-FAKE16-NEXT:  .LBB35_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB35_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v8, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v10, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB35_2
+; GFX11-FAKE16-NEXT:  .LBB35_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v17, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v18, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v4, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v6, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v8, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v10, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v12, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v14, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v16, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v19, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v20, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v5, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v9, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v11, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v13, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -6845,83 +7678,170 @@ define <2 x double> @bitcast_v8bf16_to_v2f64(<8 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v8bf16_to_v2f64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v4
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB41_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v3, 16, v3
-; GFX11-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v7, v4, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    v_bfe_u32 v9, v3, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v3
-; GFX11-NEXT:    v_add3_u32 v7, v7, v4, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT:    v_add3_u32 v9, v9, v3, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v4, v7, v8 :: v_dual_add_f32 v5, 0x40c00000, v5
-; GFX11-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v11, v5, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v5
-; GFX11-NEXT:    v_bfe_u32 v13, v2, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v9, v10, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v11, v11, v5, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff0000, v1
-; GFX11-NEXT:    v_add3_u32 v7, v13, v2, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff0000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v5, v11, v12 :: v_dual_add_f32 v6, 0x40c00000, v6
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-NEXT:    v_perm_b32 v3, v4, v3, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v9, v6, 16, 1
-; GFX11-NEXT:    v_dual_cndmask_b32 v2, v7, v8 :: v_dual_add_f32 v7, 0x40c00000, v10
-; GFX11-NEXT:    v_bfe_u32 v10, v1, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add3_u32 v8, v9, v6, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v9, 0x400000, v6
-; GFX11-NEXT:    v_bfe_u32 v11, v7, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v7
-; GFX11-NEXT:    v_perm_b32 v2, v5, v2, 0x7060302
-; GFX11-NEXT:    v_add3_u32 v11, v11, v7, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v6, v8, v9, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v9, v10, v1, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_cndmask_b32 v1, v9, v10
-; GFX11-NEXT:    v_bfe_u32 v8, v0, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    v_or_b32_e32 v13, 0x400000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v8, v8, v0, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v7, v11, v12, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_perm_b32 v1, v6, v1, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v8, v13, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v0, v7, v0, 0x7060302
-; GFX11-NEXT:  .LBB41_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v8bf16_to_v2f64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB41_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v8, v8, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v3, v8, v10 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v7, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v4, v7, v9 :: v_dual_and_b32 v5, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v3, 0xffff, v3, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v11, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v11, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, 0x400000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v13, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v11, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, 0x400000, v6
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v7, v8, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v7, v6, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v9
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v7, v6, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v2, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v9, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v10, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v13, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v10, v14, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v7, v11, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v8.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v6
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v9, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v7, v0
+; GFX11-TRUE16-NEXT:  .LBB41_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v8bf16_to_v2f64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB41_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v7, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v7, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v7, v8 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v11, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v5
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v9, v10, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v11, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v13, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v5, v11, v12 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v6, 16, 1
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v7, v8 :: v_dual_add_f32 v7, 0x40c00000, v10
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v10, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v9, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v11, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v5, v2, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v11, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v8, v9, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v10, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_cndmask_b32 v1, v9, v10
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, 0x400000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v8, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v11, v12, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v6, v1, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v8, v13, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v7, v0, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB41_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -7126,66 +8046,120 @@ define <16 x i8> @bitcast_v2f64_to_v16i8(<2 x double> %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v12, v17
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v2f64_to_v16i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v16, v2
-; GFX11-NEXT:    v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v4
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB42_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[16:17]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[18:19]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v18
-; GFX11-NEXT:  .LBB42_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB42_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_f64 v[16:17], v[16:17], 1.0
-; GFX11-NEXT:    v_add_f64 v[18:19], v[18:19], 1.0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[16:17]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[18:19]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v18
-; GFX11-NEXT:  .LBB42_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_mov_b32_e32 v0, v18
-; GFX11-NEXT:    v_mov_b32_e32 v4, v19
-; GFX11-NEXT:    v_mov_b32_e32 v8, v16
-; GFX11-NEXT:    v_mov_b32_e32 v12, v17
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v2f64_to_v16i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v16, v2
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB42_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[16:17]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v10
+; GFX11-TRUE16-NEXT:  .LBB42_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB42_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_f64 v[16:17], v[16:17], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[10:11], v[10:11], 1.0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[16:17]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v10
+; GFX11-TRUE16-NEXT:  .LBB42_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v11.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v11.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v16.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v17.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v17.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v2f64_to_v16i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v16, v2
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB42_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[16:17]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[18:19]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v18
+; GFX11-FAKE16-NEXT:  .LBB42_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB42_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_f64 v[16:17], v[16:17], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[18:19], v[18:19], 1.0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[16:17]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[18:19]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v18
+; GFX11-FAKE16-NEXT:  .LBB42_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v18
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v19
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v16
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v12, v17
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -7501,126 +8475,260 @@ define <2 x double> @bitcast_v16i8_to_v2f64(<16 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v16i8_to_v2f64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v18, v2 :: v_dual_mov_b32 v17, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v16
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v20, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v5, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v7, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v9, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v15
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB43_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB43_4
-; GFX11-NEXT:  .LBB43_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB43_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v17
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v18
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v10
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v14
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v16
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v19
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v20
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v5
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v7
-; GFX11-NEXT:    v_or_b32_e32 v5, v6, v9
-; GFX11-NEXT:    v_or_b32_e32 v6, v8, v11
-; GFX11-NEXT:    v_or_b32_e32 v7, v10, v13
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr4
-; GFX11-NEXT:    ; implicit-def: $vgpr8
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v7
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB43_2
-; GFX11-NEXT:  .LBB43_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v17, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v18, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v4, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v6, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v8, 3
-; GFX11-NEXT:    v_add_nc_u16 v6, v10, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v12, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, v14, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v0, v16, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v19, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v20, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v5, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v7, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v9, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v11, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v13, v10
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v7
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v16i8_to_v2f64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.h, v9.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 8, v12.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.l, 8, v15.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v16
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB43_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB43_4
+; GFX11-TRUE16-NEXT:  .LBB43_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB43_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v10.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v0.h, v7.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v8.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v0.h, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v1.h, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v8, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v7, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v6, v10
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB43_2
+; GFX11-TRUE16-NEXT:  .LBB43_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v10.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v9.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v9.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v6.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v8.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v10.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v12.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v7.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v7.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v8.h, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v14.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v4.l, v1.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v4.h, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v5.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v5.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v6.l, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v8, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v9, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v5, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v10, v4
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v16i8_to_v2f64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v18, v2 :: v_dual_mov_b32 v17, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB43_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB43_4
+; GFX11-FAKE16-NEXT:  .LBB43_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB43_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v8, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v10, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB43_2
+; GFX11-FAKE16-NEXT:  .LBB43_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v17, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v18, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v4, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v6, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v8, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v10, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v12, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v14, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v16, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v19, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v20, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v5, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v9, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v11, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v13, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -8297,82 +9405,171 @@ define <8 x i16> @bitcast_v8bf16_to_v8i16(<8 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v8bf16_to_v8i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v4
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB47_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-NEXT:    v_bfe_u32 v7, v4, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v7, v7, v4, 0x7fff
-; GFX11-NEXT:    v_dual_cndmask_b32 v4, v7, v8 :: v_dual_and_b32 v5, 0xffff0000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v11, v5, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v5
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    v_bfe_u32 v9, v0, 16, 1
-; GFX11-NEXT:    v_add3_u32 v11, v11, v5, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff0000, v2
-; GFX11-NEXT:    v_bfe_u32 v13, v1, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v1
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v5, v11, v12 :: v_dual_add_f32 v6, 0x40c00000, v6
-; GFX11-NEXT:    v_add3_u32 v7, v13, v1, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff0000, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT:    v_bfe_u32 v11, v6, 16, 1
-; GFX11-NEXT:    v_add3_u32 v9, v9, v0, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v1, v7, v8 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-NEXT:    v_add_f32_e32 v7, 0x40c00000, v12
-; GFX11-NEXT:    v_add3_u32 v8, v11, v6, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v11, 0x400000, v6
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    v_bfe_u32 v12, v2, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v13, v7, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v14, v3, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v15, 0x400000, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v6, v8, v11, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v8, v12, v2, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v11, v13, v7, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v7
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    v_add3_u32 v13, v14, v3, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v14, 0x400000, v3
-; GFX11-NEXT:    v_perm_b32 v1, v5, v1, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v7, v11, v12, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v13, v14, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_perm_b32 v3, v7, v3, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v8, v15, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v2, v6, v2, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v9, v10, vcc_lo
-; GFX11-NEXT:    v_perm_b32 v0, v4, v0, 0x7060302
-; GFX11-NEXT:  .LBB47_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v8bf16_to_v8i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB47_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v11, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v7, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v8, v8, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v11, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v8, v10, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v6, 16, v2
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, 0x400000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v5, v11, v12 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v12, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v13, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v10, v6, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v12, v12, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_cndmask_b32 v1, v7, v9
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v10, v6, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, 0x400000, v6
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v10, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v7, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v1, v1, 16, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v0, v0, 16, v4
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v7, v13, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v7, v10, v14, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v12, v15, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v3, v3, 16, v7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v2, v2, 16, v6
+; GFX11-TRUE16-NEXT:  .LBB47_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v8bf16_to_v8i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB47_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v7, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v7, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v7, v8 :: v_dual_and_b32 v5, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v11, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v5
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v11, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v5, v11, v12 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v13, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v11, v6, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v7, v8 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v7, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v11, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v12, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v14, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v8, v11, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v12, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v13, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    v_add3_u32 v13, v14, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v5, v1, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v11, v12, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v13, v14, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v7, v3, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v8, v15, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v6, v2, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v9, v10, vcc_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v4, v0, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB47_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -8635,69 +9832,126 @@ define <16 x i8> @bitcast_v8i16_to_v16i8(<8 x i16> %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v12, v17
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v8i16_to_v16i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v16, v2
-; GFX11-NEXT:    v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v4
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB48_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[16:17]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[18:19]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v18
-; GFX11-NEXT:  .LBB48_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB48_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[16:17]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[18:19]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v18
-; GFX11-NEXT:  .LBB48_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_mov_b32_e32 v0, v18
-; GFX11-NEXT:    v_mov_b32_e32 v4, v19
-; GFX11-NEXT:    v_mov_b32_e32 v8, v16
-; GFX11-NEXT:    v_mov_b32_e32 v12, v17
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v8i16_to_v16i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v16, v2
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB48_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[16:17]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v10
+; GFX11-TRUE16-NEXT:  .LBB48_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB48_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[16:17]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v10
+; GFX11-TRUE16-NEXT:  .LBB48_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v11.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v11.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v16.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v17.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v17.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v8i16_to_v16i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v16, v2
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB48_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[16:17]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[18:19]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v18
+; GFX11-FAKE16-NEXT:  .LBB48_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB48_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[16:17]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[18:19]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v18
+; GFX11-FAKE16-NEXT:  .LBB48_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v18
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v19
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v16
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v12, v17
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -9026,126 +10280,260 @@ define <8 x i16> @bitcast_v16i8_to_v8i16(<16 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v16i8_to_v8i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v18, v2 :: v_dual_mov_b32 v17, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v16
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v20, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v5, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v7, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v9, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v15
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB49_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB49_4
-; GFX11-NEXT:  .LBB49_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB49_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v17
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v18
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v10
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v14
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v16
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v19
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v20
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v5
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v7
-; GFX11-NEXT:    v_or_b32_e32 v5, v6, v9
-; GFX11-NEXT:    v_or_b32_e32 v6, v8, v11
-; GFX11-NEXT:    v_or_b32_e32 v7, v10, v13
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr4
-; GFX11-NEXT:    ; implicit-def: $vgpr8
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v7
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB49_2
-; GFX11-NEXT:  .LBB49_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v17, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v18, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v4, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v6, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v8, 3
-; GFX11-NEXT:    v_add_nc_u16 v6, v10, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v12, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, v14, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v0, v16, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v19, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v20, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v5, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v7, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v9, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v11, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v13, v10
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v7
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v16i8_to_v8i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.h, v9.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 8, v12.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.l, 8, v15.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v16
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB49_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB49_4
+; GFX11-TRUE16-NEXT:  .LBB49_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB49_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v10.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v0.h, v7.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v8.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v0.h, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v1.h, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v8, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v7, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v6, v10
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB49_2
+; GFX11-TRUE16-NEXT:  .LBB49_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v10.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v9.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v9.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v6.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v8.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v10.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v12.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v7.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v7.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v8.h, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v14.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v4.l, v1.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v4.h, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v5.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v5.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v6.l, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v8, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v9, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v5, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v10, v4
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v16i8_to_v8i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v18, v2 :: v_dual_mov_b32 v17, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB49_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB49_4
+; GFX11-FAKE16-NEXT:  .LBB49_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB49_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v8, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v10, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB49_2
+; GFX11-FAKE16-NEXT:  .LBB49_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v17, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v18, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v4, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v6, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v8, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v10, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v12, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v14, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v16, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v19, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v20, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v5, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v9, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v11, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v13, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -9578,82 +10966,169 @@ define <8 x half> @bitcast_v8bf16_to_v8f16(<8 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v8bf16_to_v8f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v4
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB51_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-NEXT:    v_bfe_u32 v7, v4, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v7, v7, v4, 0x7fff
-; GFX11-NEXT:    v_dual_cndmask_b32 v4, v7, v8 :: v_dual_and_b32 v5, 0xffff0000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v11, v5, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v5
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    v_bfe_u32 v9, v0, 16, 1
-; GFX11-NEXT:    v_add3_u32 v11, v11, v5, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff0000, v2
-; GFX11-NEXT:    v_bfe_u32 v13, v1, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v1
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v5, v11, v12 :: v_dual_add_f32 v6, 0x40c00000, v6
-; GFX11-NEXT:    v_add3_u32 v7, v13, v1, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff0000, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT:    v_bfe_u32 v11, v6, 16, 1
-; GFX11-NEXT:    v_add3_u32 v9, v9, v0, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v1, v7, v8 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-NEXT:    v_add_f32_e32 v7, 0x40c00000, v12
-; GFX11-NEXT:    v_add3_u32 v8, v11, v6, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v11, 0x400000, v6
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    v_bfe_u32 v12, v2, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v13, v7, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v14, v3, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v15, 0x400000, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v6, v8, v11, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v8, v12, v2, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v11, v13, v7, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v7
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    v_add3_u32 v13, v14, v3, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v14, 0x400000, v3
-; GFX11-NEXT:    v_perm_b32 v1, v5, v1, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v7, v11, v12, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v13, v14, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_perm_b32 v3, v7, v3, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v8, v15, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v2, v6, v2, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v9, v10, vcc_lo
-; GFX11-NEXT:    v_perm_b32 v0, v4, v0, 0x7060302
-; GFX11-NEXT:  .LBB51_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v8bf16_to_v8f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB51_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v7, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v4, v7, v8 :: v_dual_and_b32 v5, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v3
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v10, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_add3_u32 v10, v10, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v7, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, 0x400000, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v7, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v10, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_cndmask_b32 v1, v7, v9
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v7, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v5
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v7, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_add_f32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v10, v6, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, 0x400000, v6
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v10, v6, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v10, v8, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v13, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v10, v14, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v2, v6
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v7, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v8.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v3, 0xffff, v7, v3
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v0, v4
+; GFX11-TRUE16-NEXT:  .LBB51_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v8bf16_to_v8f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB51_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v7, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v7, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v7, v8 :: v_dual_and_b32 v5, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v11, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v5
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v11, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v5, v11, v12 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v13, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v11, v6, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v7, v8 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v7, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v11, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v12, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v14, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v8, v11, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v12, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v13, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    v_add3_u32 v13, v14, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v5, v1, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v11, v12, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v13, v14, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v7, v3, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v8, v15, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v6, v2, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v9, v10, vcc_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v4, v0, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB51_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -9915,69 +11390,126 @@ define <16 x i8> @bitcast_v8f16_to_v16i8(<8 x half> %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v12, v17
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v8f16_to_v16i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v16, v2
-; GFX11-NEXT:    v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v4
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB52_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[16:17]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[18:19]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v18
-; GFX11-NEXT:  .LBB52_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB52_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[16:17]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[18:19]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v18
-; GFX11-NEXT:  .LBB52_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_mov_b32_e32 v0, v18
-; GFX11-NEXT:    v_mov_b32_e32 v4, v19
-; GFX11-NEXT:    v_mov_b32_e32 v8, v16
-; GFX11-NEXT:    v_mov_b32_e32 v12, v17
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v8f16_to_v16i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v16, v2
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB52_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[16:17]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v10
+; GFX11-TRUE16-NEXT:  .LBB52_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB52_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[16:17]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v10
+; GFX11-TRUE16-NEXT:  .LBB52_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v11.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v11.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v16.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v17.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v17.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v8f16_to_v16i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v16, v2
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB52_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[16:17]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[18:19]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v18
+; GFX11-FAKE16-NEXT:  .LBB52_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB52_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[16:17]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[18:19]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v18
+; GFX11-FAKE16-NEXT:  .LBB52_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v18
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v19
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v16
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v12, v17
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -10289,126 +11821,260 @@ define <8 x half> @bitcast_v16i8_to_v8f16(<16 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v16i8_to_v8f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v18, v2 :: v_dual_mov_b32 v17, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v16
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v20, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v5, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v7, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v9, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v15
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB53_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB53_4
-; GFX11-NEXT:  .LBB53_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB53_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v17
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v18
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v10
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v14
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v16
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v19
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v20
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v5
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v7
-; GFX11-NEXT:    v_or_b32_e32 v5, v6, v9
-; GFX11-NEXT:    v_or_b32_e32 v6, v8, v11
-; GFX11-NEXT:    v_or_b32_e32 v7, v10, v13
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr4
-; GFX11-NEXT:    ; implicit-def: $vgpr8
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v7
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB53_2
-; GFX11-NEXT:  .LBB53_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v17, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v18, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v4, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v6, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v8, 3
-; GFX11-NEXT:    v_add_nc_u16 v6, v10, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v12, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, v14, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v0, v16, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v19, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v20, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v5, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v7, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v9, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v11, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v13, v10
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v7
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v16i8_to_v8f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.h, v9.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 8, v12.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.l, 8, v15.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v16
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB53_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB53_4
+; GFX11-TRUE16-NEXT:  .LBB53_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB53_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v10.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v0.h, v7.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v8.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v0.h, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v1.h, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v8, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v7, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v6, v10
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB53_2
+; GFX11-TRUE16-NEXT:  .LBB53_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v10.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v9.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v9.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v6.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v8.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v10.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v12.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v7.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v7.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v8.h, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v14.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v4.l, v1.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v4.h, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v5.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v5.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v6.l, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v8, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v9, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v5, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v10, v4
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v16i8_to_v8f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v18, v2 :: v_dual_mov_b32 v17, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB53_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB53_4
+; GFX11-FAKE16-NEXT:  .LBB53_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB53_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v8, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v10, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB53_2
+; GFX11-FAKE16-NEXT:  .LBB53_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v17, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v18, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v4, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v6, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v8, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v10, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v12, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v14, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v16, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v19, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v20, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v5, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v9, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v11, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v13, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -10790,138 +12456,272 @@ define <16 x i8> @bitcast_v8bf16_to_v16i8(<8 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v12, v17
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v8bf16_to_v16i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v16, v2
-; GFX11-NEXT:    v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v4
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB54_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[16:17]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[18:19]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v18
-; GFX11-NEXT:  .LBB54_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB54_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v19
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v19
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v17
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_add_f32 v1, 0x40c00000, v1
-; GFX11-NEXT:    v_bfe_u32 v5, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v6, 0x400000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v7, v1, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v1
-; GFX11-NEXT:    v_add3_u32 v5, v5, v0, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v0, 0x40c00000, v4
-; GFX11-NEXT:    v_add3_u32 v7, v7, v1, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v18
-; GFX11-NEXT:    v_bfe_u32 v6, v0, 16, 1
-; GFX11-NEXT:    v_dual_cndmask_b32 v12, v7, v8 :: v_dual_add_f32 v3, 0x40c00000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add3_u32 v6, v6, v0, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v19, 16, v12
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v11, v3, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v4, 0x400000, v3
-; GFX11-NEXT:    v_add3_u32 v1, v11, v3, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-NEXT:    v_bfe_u32 v9, v2, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v2
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v9, v9, v2, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v9, v10, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v1, v4, vcc_lo
-; GFX11-NEXT:    v_dual_add_f32 v4, 0x40c00000, v7 :: v_dual_lshlrev_b32 v1, 16, v16
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v3
-; GFX11-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v9, v4, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v13, 0x400000, v1
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff0000, v16
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v7, 0x40c00000, v8
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v8, v9, v4, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v9, 0x400000, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    v_bfe_u32 v0, v1, 16, 1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v4, v8, v9, vcc_lo
-; GFX11-NEXT:    v_bfe_u32 v10, v7, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v11, 0x400000, v7
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    v_add3_u32 v0, v0, v1, 0x7fff
-; GFX11-NEXT:    v_perm_b32 v8, v6, v4, 0x7060302
-; GFX11-NEXT:    v_add3_u32 v10, v10, v7, 0x7fff
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v8
-; GFX11-NEXT:    v_cndmask_b32_e32 v7, v10, v11, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_perm_b32 v1, v5, v12, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v9, v0, v13, vcc_lo
-; GFX11-NEXT:    v_perm_b32 v0, v2, v3, 0x7060302
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v8
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
-; GFX11-NEXT:    v_perm_b32 v7, v7, v9, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[0:1]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v16, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
-; GFX11-NEXT:  .LBB54_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_mov_b32_e32 v0, v18
-; GFX11-NEXT:    v_mov_b32_e32 v4, v19
-; GFX11-NEXT:    v_mov_b32_e32 v8, v16
-; GFX11-NEXT:    v_mov_b32_e32 v12, v17
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v8bf16_to_v16i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v11, v3 :: v_dual_mov_b32 v10, v2
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v4
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB54_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[16:17], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[2:3]
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v3.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.h, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v11.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.h, v11.h
+; GFX11-TRUE16-NEXT:  .LBB54_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB54_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v3
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_add3_u32 v14, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v4, v6, v8 :: v_dual_and_b32 v3, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v10
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v14, v7, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v11
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v4.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v9, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v13, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v11
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v2, v12, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v9, 0x40c00000, v10
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v10, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v2, v2, v12, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v11, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v14, v9, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v3, 0xffff, v3, v6
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v12, v2, v13, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v11, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_add3_u32 v2, v14, v9, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v9
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v10, v15, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v12.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v14, v7, v11, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v8.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v11, 0xffff, v5, v14
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v2, v13, vcc_lo
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v10, 0xffff, v7, v2
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v9, v1
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[16:17], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[2:3]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-TRUE16-NEXT:  .LBB54_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v17.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v14.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v8bf16_to_v16i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v16, v2
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB54_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[16:17]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[18:19]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v18
+; GFX11-FAKE16-NEXT:  .LBB54_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB54_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v17
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_add_f32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v5, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, 0x400000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v7, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v5, v5, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v4
+; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v7, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v18
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v12, v7, v8 :: v_dual_add_f32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v19, 16, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v11, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_add3_u32 v1, v11, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v9, v10, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v1, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v4, 0x40c00000, v7 :: v_dual_lshlrev_b32 v1, 16, v16
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v3
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v16
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v7, 0x40c00000, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v9, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v0, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v8, v9, vcc_lo
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v10, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    v_add3_u32 v0, v0, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v6, v4, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add3_u32 v10, v10, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v8
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v10, v11, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v5, v12, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v0, v13, vcc_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v2, v3, 0x7060302
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v9, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[0:1]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-FAKE16-NEXT:  .LBB54_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v18
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v19
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v16
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v12, v17
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -11249,126 +13049,260 @@ define <8 x bfloat> @bitcast_v16i8_to_v8bf16(<16 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v16i8_to_v8bf16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v18, v2 :: v_dual_mov_b32 v17, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v16
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v20, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v5, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v7, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v9, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v15
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB55_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB55_4
-; GFX11-NEXT:  .LBB55_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB55_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v17
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v18
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v10
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v14
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v16
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v19
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v20
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v5
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v7
-; GFX11-NEXT:    v_or_b32_e32 v5, v6, v9
-; GFX11-NEXT:    v_or_b32_e32 v6, v8, v11
-; GFX11-NEXT:    v_or_b32_e32 v7, v10, v13
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr4
-; GFX11-NEXT:    ; implicit-def: $vgpr8
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v7
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB55_2
-; GFX11-NEXT:  .LBB55_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v17, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v18, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v4, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v6, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v8, 3
-; GFX11-NEXT:    v_add_nc_u16 v6, v10, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v12, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, v14, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v0, v16, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v19, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v20, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v5, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v7, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v9, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v11, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v13, v10
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v7
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v16i8_to_v8bf16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.h, v9.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 8, v12.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.l, 8, v15.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v16
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB55_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB55_4
+; GFX11-TRUE16-NEXT:  .LBB55_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB55_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v10.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v0.h, v7.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v8.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v0.h, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v1.h, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v8, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v7, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v6, v10
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB55_2
+; GFX11-TRUE16-NEXT:  .LBB55_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v10.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v9.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v9.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v6.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v8.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v10.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v12.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v7.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v7.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v8.h, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v14.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v4.l, v1.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v4.h, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v5.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v5.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v6.l, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v8, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v9, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v5, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v10, v4
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v16i8_to_v8bf16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v18, v2 :: v_dual_mov_b32 v17, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB55_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB55_4
+; GFX11-FAKE16-NEXT:  .LBB55_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB55_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v8, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v10, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB55_2
+; GFX11-FAKE16-NEXT:  .LBB55_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v17, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v18, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v4, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v6, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v8, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v10, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v12, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v14, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v16, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v19, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v20, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v5, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v9, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v11, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v13, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
index b0627c3d4e77d..1db0cccfe6b72 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
@@ -3,7 +3,8 @@
 ; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define half @bitcast_i16_to_f16(i16 %a, i32 %b) {
 ; GCN-LABEL: bitcast_i16_to_f16:
@@ -58,19 +59,41 @@ define half @bitcast_i16_to_f16(i16 %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_i16_to_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v1
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v0, 3
-; GFX11-NEXT:  ; %bb.2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_i16_to_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.l
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB0_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v0.l, 3
+; GFX11-TRUE16-NEXT:  .LBB0_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v1.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_i16_to_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v1
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v0, 3
+; GFX11-FAKE16-NEXT:  ; %bb.2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -132,19 +155,41 @@ define i16 @bitcast_f16_to_i16(half %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_f16_to_i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v1
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_add_f16_e32 v0, 0x200, v0
-; GFX11-NEXT:  ; %bb.2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_f16_to_i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.l
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB1_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_f16_e32 v1.l, 0x200, v0.l
+; GFX11-TRUE16-NEXT:  .LBB1_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v1.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_f16_to_i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v1
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_f16_e32 v0, 0x200, v0
+; GFX11-FAKE16-NEXT:  ; %bb.2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -205,19 +250,41 @@ define bfloat @bitcast_i16_to_bf16(i16 %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_i16_to_bf16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v1
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v0, 3
-; GFX11-NEXT:  ; %bb.2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_i16_to_bf16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.l
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB2_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v0.l, 3
+; GFX11-TRUE16-NEXT:  .LBB2_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v1.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_i16_to_bf16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v1
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v0, 3
+; GFX11-FAKE16-NEXT:  ; %bb.2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -305,30 +372,61 @@ define i16 @bitcast_bf16_to_i16(bfloat %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_bf16_to_i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v1
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB3_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT:  .LBB3_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_bf16_to_i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v1
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v2.l
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB3_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-TRUE16-NEXT:  .LBB3_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_bf16_to_i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v1
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB3_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT:  .LBB3_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -401,19 +499,41 @@ define bfloat @bitcast_f16_to_bf16(half %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_f16_to_bf16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v1
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_add_f16_e32 v0, 0x200, v0
-; GFX11-NEXT:  ; %bb.2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_f16_to_bf16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.l
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB4_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_f16_e32 v1.l, 0x200, v0.l
+; GFX11-TRUE16-NEXT:  .LBB4_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v1.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_f16_to_bf16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v1
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_f16_e32 v0, 0x200, v0
+; GFX11-FAKE16-NEXT:  ; %bb.2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -503,30 +623,61 @@ define half @bitcast_bf16_to_f16(bfloat %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_bf16_to_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v1
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB5_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT:  .LBB5_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_bf16_to_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v1
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v2.l
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB5_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-TRUE16-NEXT:  .LBB5_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_bf16_to_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v1
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB5_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT:  .LBB5_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -543,3 +694,5 @@ end:
   %phi = phi half [ %a2, %cmp.true ], [ %a3, %cmp.false ]
   ret half %phi
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
index b52d8a89035bc..edeb780d481c4 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
@@ -3,7 +3,8 @@
 ; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define <8 x float> @bitcast_v8i32_to_v8f32(<8 x i32> %a, i32 %b) {
 ; GCN-LABEL: bitcast_v8i32_to_v8f32:
@@ -1918,148 +1919,304 @@ define <8 x i32> @bitcast_v16bf16_to_v8i32(<16 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v16bf16_to_v8i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v8
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB11_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v7
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v8, 0x40c00000, v8
-; GFX11-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v13, v9, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v10, v8, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v11, 0x400000, v8
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_bfe_u32 v15, v6, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-NEXT:    v_add3_u32 v13, v13, v9, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v10, v10, v8, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v8, v10, v11, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v11, v15, v6, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-NEXT:    v_bfe_u32 v12, v7, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v14, 0x400000, v7
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v12, v12, v7, 0x7fff
-; GFX11-NEXT:    v_dual_cndmask_b32 v7, v12, v14 :: v_dual_lshlrev_b32 v12, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v7, v7, v8, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-NEXT:    v_or_b32_e32 v14, 0x400000, v6
-; GFX11-NEXT:    v_dual_cndmask_b32 v9, v13, v10 :: v_dual_add_f32 v10, 0x40c00000, v12
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v8, v5, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v13, 0x400000, v5
-; GFX11-NEXT:    v_bfe_u32 v12, v10, 16, 1
-; GFX11-NEXT:    v_dual_cndmask_b32 v6, v11, v14 :: v_dual_lshlrev_b32 v11, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    v_add3_u32 v8, v8, v5, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v6, v6, v9, 0x7060302
-; GFX11-NEXT:    v_dual_add_f32 v9, 0x40c00000, v11 :: v_dual_add_f32 v4, 0x40c00000, v4
-; GFX11-NEXT:    v_add3_u32 v11, v12, v10, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v10
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v14, v9, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v10, v11, v12, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    v_or_b32_e32 v11, 0x400000, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v5, v8, v13, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v8, v14, v9, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    v_dual_add_f32 v9, 0x40c00000, v12 :: v_dual_lshlrev_b32 v12, 16, v2
-; GFX11-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-NEXT:    v_perm_b32 v5, v5, v10, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v10, v4, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v11, 0x400000, v4
-; GFX11-NEXT:    v_bfe_u32 v13, v9, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    v_add3_u32 v10, v10, v4, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_cndmask_b32_e32 v4, v10, v11, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v10, 0x40c00000, v12
-; GFX11-NEXT:    v_add3_u32 v11, v13, v9, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v9
-; GFX11-NEXT:    v_bfe_u32 v13, v3, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    v_bfe_u32 v14, v10, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v9, v11, v12, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v11, v13, v3, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v3
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT:    v_add3_u32 v13, v14, v10, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v3, v11, v12 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-NEXT:    v_perm_b32 v4, v4, v8, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v11, 0x40c00000, v14
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-NEXT:    v_or_b32_e32 v15, 0x400000, v10
-; GFX11-NEXT:    v_bfe_u32 v16, v2, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    v_bfe_u32 v14, v11, 16, 1
-; GFX11-NEXT:    v_perm_b32 v3, v3, v9, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v12, v16, v2, 0x7fff
-; GFX11-NEXT:    v_dual_cndmask_b32 v10, v13, v15 :: v_dual_lshlrev_b32 v15, 16, v0
-; GFX11-NEXT:    v_or_b32_e32 v13, 0x400000, v2
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v12, v13, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v12, 0x40c00000, v15
-; GFX11-NEXT:    v_add3_u32 v13, v14, v11, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v14, 0x400000, v11
-; GFX11-NEXT:    v_bfe_u32 v15, v1, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-NEXT:    v_bfe_u32 v16, v12, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v17, 0x400000, v12
-; GFX11-NEXT:    v_perm_b32 v2, v2, v10, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v11, v13, v14, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v14, v15, v1, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v15, 0x400000, v1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    v_add3_u32 v16, v16, v12, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_cndmask_b32 v1, v14, v15 :: v_dual_add_f32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-NEXT:    v_perm_b32 v1, v1, v11, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v13, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v18, 0x400000, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v12, v16, v17, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_add3_u32 v13, v13, v0, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v13, v18, vcc_lo
-; GFX11-NEXT:    v_perm_b32 v0, v0, v12, 0x7060302
-; GFX11-NEXT:  .LBB11_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v16bf16_to_v8i32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v8
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB11_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_lshlrev_b32 v8, 16, v7
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v15, v9, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v11, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v11, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v8, v11, v14 :: v_dual_and_b32 v7, 0xffff0000, v7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v7, 0x40c00000, v7 :: v_dual_lshlrev_b32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v15, v9, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v8.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v12, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    v_add3_u32 v12, v12, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v7, v12, v13
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v6, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, 0x400000, v6
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v9
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v7, 0xffff, v8, v7
+; GFX11-TRUE16-NEXT:    v_add3_u32 v14, v16, v6, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v14, v17, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v6.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v9, v11, v12 :: v_dual_add_f32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v6, 0xffff, v6, v9
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v10, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v14, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v13, v10, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v12, v14, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, 0x400000, v10
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v12, v13, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v10, v11, v14 :: v_dual_add_f32 v11, 0x40c00000, v15
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v11, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v4, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v5, 0xffff, v5, v10
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    v_add3_u32 v8, v8, v11, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v11
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v9, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v12, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v11, 0x40c00000, v14
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v8, v13, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v12, v12, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v15, v11, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v4, 0xffff, v4, v8
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v3, v12, v13 :: v_dual_add_f32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v10, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, 0x400000, v10
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v10, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v10, v15, v11, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v9, v9, v14 :: v_dual_and_b32 v14, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v3, 0xffff, v3, v9
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v10, v10, v12 :: v_dual_add_f32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v13, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v13, 0x40c00000, v14 :: v_dual_lshlrev_b32 v14, 16, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v11, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v14
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v14, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v11, v13, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, 0x400000, v13
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v15, v12, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v14, v14, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v19, 0x400000, v12
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v11, v13, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v18, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v15, v15, v12, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v14, v17, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_add3_u32 v14, v18, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v12, v15, v19, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v2, v10
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v11, v11, v16, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v11
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v14, v17, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v12, v0
+; GFX11-TRUE16-NEXT:  .LBB11_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v16bf16_to_v8i32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v8
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB11_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v10, v8, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, 0x400000, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v15, v6, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-FAKE16-NEXT:    v_add3_u32 v13, v13, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v10, v11, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v15, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v12, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v12, v12, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v7, v12, v14 :: v_dual_lshlrev_b32 v12, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v8, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v9, v13, v10 :: v_dual_add_f32 v10, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, 0x400000, v5
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v12, v10, 16, 1
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v6, v11, v14 :: v_dual_lshlrev_b32 v11, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v6, v9, 0x7060302
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v11 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v12, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v10
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v14, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v11, v12, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v8, v13, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v14, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v12 :: v_dual_lshlrev_b32 v12, 16, v2
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v5, v10, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v10, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    v_add3_u32 v10, v10, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v10, v11, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v10, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v13, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v14, v10, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v11, v12, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v13, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_add3_u32 v13, v14, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v3, v11, v12 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v4, v8, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v11, 0x40c00000, v14
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, 0x400000, v10
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v14, v11, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v3, v9, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v12, v16, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v13, v15 :: v_dual_lshlrev_b32 v15, 16, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v12, v13, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v15
+; GFX11-FAKE16-NEXT:    v_add3_u32 v13, v14, v11, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, 0x400000, v11
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v15, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v12, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, 0x400000, v12
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v10, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v13, v14, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v14, v15, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v12, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v14, v15 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v11, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v16, v17, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v13, v13, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v13, v18, vcc_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v12, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB11_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -2402,114 +2559,209 @@ define <32 x i8> @bitcast_v8i32_to_v32i8(<8 x i32> %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v7, v36
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v8i32_to_v32i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
-; GFX11-NEXT:    v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v34, v4
-; GFX11-NEXT:    v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v36, v2
-; GFX11-NEXT:    v_dual_mov_b32 v39, v1 :: v_dual_mov_b32 v38, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB12_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 16, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 24, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 16, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 8, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v38
-; GFX11-NEXT:    v_lshrrev_b64 v[27:28], 24, v[32:33]
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[34:35]
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[36:37]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[38:39]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v38
-; GFX11-NEXT:  .LBB12_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB12_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u32_e32 v39, 3, v39
-; GFX11-NEXT:    v_add_nc_u32_e32 v37, 3, v37
-; GFX11-NEXT:    v_add_nc_u32_e32 v35, 3, v35
-; GFX11-NEXT:    v_add_nc_u32_e32 v33, 3, v33
-; GFX11-NEXT:    v_add_nc_u32_e32 v32, 3, v32
-; GFX11-NEXT:    v_add_nc_u32_e32 v34, 3, v34
-; GFX11-NEXT:    v_add_nc_u32_e32 v36, 3, v36
-; GFX11-NEXT:    v_add_nc_u32_e32 v38, 3, v38
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
-; GFX11-NEXT:    v_lshrrev_b64 v[27:28], 24, v[32:33]
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[34:35]
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[36:37]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[38:39]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 16, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 24, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 16, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 8, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v38
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v38
-; GFX11-NEXT:  .LBB12_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_mov_b32_e32 v0, v38
-; GFX11-NEXT:    v_mov_b32_e32 v4, v39
-; GFX11-NEXT:    v_mov_b32_e32 v8, v36
-; GFX11-NEXT:    v_mov_b32_e32 v12, v37
-; GFX11-NEXT:    v_mov_b32_e32 v16, v34
-; GFX11-NEXT:    v_mov_b32_e32 v20, v35
-; GFX11-NEXT:    v_mov_b32_e32 v24, v32
-; GFX11-NEXT:    v_mov_b32_e32 v28, v33
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v8i32_to_v32i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v27, v5 :: v_dual_mov_b32 v26, v4
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v19, v3 :: v_dual_mov_b32 v18, v2
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v8
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB12_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[32:33]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[26:27]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[18:19]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v10
+; GFX11-TRUE16-NEXT:  .LBB12_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB12_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v33, 3, v33
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v32, 3, v32
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v27, 3, v27
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v26, 3, v26
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v11, 3, v11
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v19, 3, v19
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v18, 3, v18
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v10, 3, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[32:33]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[26:27]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[18:19]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v10
+; GFX11-TRUE16-NEXT:  .LBB12_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v11.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v11.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v18.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v36.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v19.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v19.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v26.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v18.l, v26.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v35.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.l, v27.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.l, v27.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v24.l, v32.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v26.l, v32.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.l, v34.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.l, v33.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.l, v33.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v8i32_to_v32i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v34, v4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v36, v2
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v39, v1 :: v_dual_mov_b32 v38, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB12_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 16, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 16, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v38
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[27:28], 24, v[32:33]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[34:35]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[36:37]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[38:39]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v38
+; GFX11-FAKE16-NEXT:  .LBB12_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB12_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v39, 3, v39
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v37, 3, v37
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v35, 3, v35
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v33, 3, v33
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v32, 3, v32
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v34, 3, v34
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v36, 3, v36
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v38, 3, v38
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[27:28], 24, v[32:33]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[34:35]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[36:37]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[38:39]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 16, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 16, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v38
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v38
+; GFX11-FAKE16-NEXT:  .LBB12_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v38
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v39
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v36
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v12, v37
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v16, v34
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v20, v35
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v24, v32
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v28, v33
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -3066,226 +3318,459 @@ define <8 x i32> @bitcast_v32i8_to_v8i32(<32 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v32i8_to_v8i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v32, v2 :: v_dual_mov_b32 v31, v0
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_b32 v0, off, s32 offset:4
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32
-; GFX11-NEXT:    v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v4
-; GFX11-NEXT:    v_lshlrev_b16 v51, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v49, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v50, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v48, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v38, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v35, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v36, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v37, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v9, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v2
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB13_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB13_4
-; GFX11-NEXT:  .LBB13_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB13_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v31
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v34
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v51
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v49
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v50
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v48
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v38
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v39
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v18
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v12
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v24
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v26
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v30
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v35
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v36
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v37
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v19
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v21
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v9
-; GFX11-NEXT:    v_or_b32_e32 v9, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v10, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v11, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v12, v16, v17
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v4
-; GFX11-NEXT:    v_or_b32_e32 v4, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v5, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v6, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v7, v11, v12
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr8
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB13_2
-; GFX11-NEXT:  .LBB13_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v31, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v32, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v33, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v34, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v8, 3
-; GFX11-NEXT:    v_add_nc_u16 v5, v10, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_or_b32_e32 v0, v51, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v49, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v50, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v48, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v38, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v39, v5
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_add_nc_u16 v6, v18, 3
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_add_nc_u16 v3, v12, 3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    v_add_nc_u16 v4, v14, 3
-; GFX11-NEXT:    v_add_nc_u16 v5, v16, 3
-; GFX11-NEXT:    v_add_nc_u16 v7, v20, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v22, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, v24, 3
-; GFX11-NEXT:    v_add_nc_u16 v12, v26, 3
-; GFX11-NEXT:    v_add_nc_u16 v14, v28, 3
-; GFX11-NEXT:    v_add_nc_u16 v16, v30, 3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_or_b32_e32 v3, v35, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v36, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v37, v5
-; GFX11-NEXT:    v_or_b32_e32 v6, v19, v6
-; GFX11-NEXT:    v_or_b32_e32 v7, v21, v7
-; GFX11-NEXT:    v_or_b32_e32 v8, v9, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v11, v10
-; GFX11-NEXT:    v_or_b32_e32 v10, v13, v12
-; GFX11-NEXT:    v_or_b32_e32 v11, v15, v14
-; GFX11-NEXT:    v_or_b32_e32 v12, v17, v16
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v10
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v11
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v12
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v4
-; GFX11-NEXT:    v_or_b32_e32 v4, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v5, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v6, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v7, v11, v12
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v32i8_to_v8i32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.h, v21.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.h, v19.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v23.h, v17.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v24.h, v15.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v25.h, v13.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.h, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.h, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.l, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.l, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.l, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v25.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.l, 8, v24.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v23.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.l, 8, v22.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v21.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.l, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.l, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v29.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.l, 8, v31.l
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v32
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB13_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB13_4
+; GFX11-TRUE16-NEXT:  .LBB13_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB13_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v20.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v19.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v14.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v0.h, v17.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v1.h, v16.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.l, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.h, v15.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v5, v3
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v16.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v20.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v10.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v11.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v6, v2
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v3.h, v11.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v4.h, v12.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v26.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v30.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v8.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v3.h, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v9.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v4.h, v9.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v10.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v11, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v13, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v15, v8
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v6, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v7, v10
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB13_2
+; GFX11-TRUE16-NEXT:  .LBB13_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v21.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v20.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v14.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v13.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v19.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v18.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v17.l, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v15.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v15.h, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v17.h, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v19.l, 3
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v2, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v5, v3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v13.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, v16.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, v20.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v16.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, v14.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, v18.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v10.h, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v11.h, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v12.h, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v11.l, v3.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.h, v12.l, v4.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v4.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v6, v1
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v3.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v22.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, v24.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, v26.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, v28.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, v30.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v8.l, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v8.h, v3.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v9.l, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.h, v9.h, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v10.l, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v7
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v3.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v4.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v4.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v11, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v13, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v15, v8
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v6, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v7, v10
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v32i8_to_v8i32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v32, v2 :: v_dual_mov_b32 v31, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v0, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v51, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v49, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v50, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v48, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v38, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v35, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v36, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v37, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v29
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB13_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB13_4
+; GFX11-FAKE16-NEXT:  .LBB13_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB13_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v51
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v49
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v50
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v48
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v38
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v37
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v16, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v11, v12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB13_2
+; GFX11-FAKE16-NEXT:  .LBB13_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v31, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v32, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v33, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v34, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v8, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v10, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v51, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v49, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v50, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v48, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v38, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v39, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v18, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v12, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v14, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v16, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v20, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v22, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v24, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v26, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v28, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, v30, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v35, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v36, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v37, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v19, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v21, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v9, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v11, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v13, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v15, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v17, v16
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v11, v12
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -4996,148 +5481,304 @@ define <8 x float> @bitcast_v16bf16_to_v8f32(<16 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v16bf16_to_v8f32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v8
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB23_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v7
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v8, 0x40c00000, v8
-; GFX11-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v13, v9, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v10, v8, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v11, 0x400000, v8
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_bfe_u32 v15, v6, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-NEXT:    v_add3_u32 v13, v13, v9, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v10, v10, v8, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v8, v10, v11, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v11, v15, v6, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-NEXT:    v_bfe_u32 v12, v7, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v14, 0x400000, v7
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v12, v12, v7, 0x7fff
-; GFX11-NEXT:    v_dual_cndmask_b32 v7, v12, v14 :: v_dual_lshlrev_b32 v12, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v7, v7, v8, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-NEXT:    v_or_b32_e32 v14, 0x400000, v6
-; GFX11-NEXT:    v_dual_cndmask_b32 v9, v13, v10 :: v_dual_add_f32 v10, 0x40c00000, v12
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v8, v5, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v13, 0x400000, v5
-; GFX11-NEXT:    v_bfe_u32 v12, v10, 16, 1
-; GFX11-NEXT:    v_dual_cndmask_b32 v6, v11, v14 :: v_dual_lshlrev_b32 v11, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    v_add3_u32 v8, v8, v5, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v6, v6, v9, 0x7060302
-; GFX11-NEXT:    v_dual_add_f32 v9, 0x40c00000, v11 :: v_dual_add_f32 v4, 0x40c00000, v4
-; GFX11-NEXT:    v_add3_u32 v11, v12, v10, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v10
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v14, v9, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v10, v11, v12, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    v_or_b32_e32 v11, 0x400000, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v5, v8, v13, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v8, v14, v9, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    v_dual_add_f32 v9, 0x40c00000, v12 :: v_dual_lshlrev_b32 v12, 16, v2
-; GFX11-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-NEXT:    v_perm_b32 v5, v5, v10, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v10, v4, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v11, 0x400000, v4
-; GFX11-NEXT:    v_bfe_u32 v13, v9, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    v_add3_u32 v10, v10, v4, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_cndmask_b32_e32 v4, v10, v11, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v10, 0x40c00000, v12
-; GFX11-NEXT:    v_add3_u32 v11, v13, v9, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v9
-; GFX11-NEXT:    v_bfe_u32 v13, v3, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    v_bfe_u32 v14, v10, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v9, v11, v12, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v11, v13, v3, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v3
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT:    v_add3_u32 v13, v14, v10, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v3, v11, v12 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-NEXT:    v_perm_b32 v4, v4, v8, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v11, 0x40c00000, v14
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-NEXT:    v_or_b32_e32 v15, 0x400000, v10
-; GFX11-NEXT:    v_bfe_u32 v16, v2, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    v_bfe_u32 v14, v11, 16, 1
-; GFX11-NEXT:    v_perm_b32 v3, v3, v9, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v12, v16, v2, 0x7fff
-; GFX11-NEXT:    v_dual_cndmask_b32 v10, v13, v15 :: v_dual_lshlrev_b32 v15, 16, v0
-; GFX11-NEXT:    v_or_b32_e32 v13, 0x400000, v2
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v12, v13, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v12, 0x40c00000, v15
-; GFX11-NEXT:    v_add3_u32 v13, v14, v11, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v14, 0x400000, v11
-; GFX11-NEXT:    v_bfe_u32 v15, v1, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-NEXT:    v_bfe_u32 v16, v12, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v17, 0x400000, v12
-; GFX11-NEXT:    v_perm_b32 v2, v2, v10, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v11, v13, v14, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v14, v15, v1, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v15, 0x400000, v1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    v_add3_u32 v16, v16, v12, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_cndmask_b32 v1, v14, v15 :: v_dual_add_f32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-NEXT:    v_perm_b32 v1, v1, v11, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v13, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v18, 0x400000, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v12, v16, v17, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_add3_u32 v13, v13, v0, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v13, v18, vcc_lo
-; GFX11-NEXT:    v_perm_b32 v0, v0, v12, 0x7060302
-; GFX11-NEXT:  .LBB23_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v16bf16_to_v8f32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v8
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB23_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_lshlrev_b32 v8, 16, v7
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v15, v9, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v11, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v11, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v8, v11, v14 :: v_dual_and_b32 v7, 0xffff0000, v7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v7, 0x40c00000, v7 :: v_dual_lshlrev_b32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v15, v9, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v8.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v12, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    v_add3_u32 v12, v12, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v7, v12, v13
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v6, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, 0x400000, v6
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v9
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v7, 0xffff, v8, v7
+; GFX11-TRUE16-NEXT:    v_add3_u32 v14, v16, v6, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v14, v17, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v6.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v9, v11, v12 :: v_dual_add_f32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v6, 0xffff, v6, v9
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v10, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v14, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v13, v10, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v12, v14, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, 0x400000, v10
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v12, v13, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v10, v11, v14 :: v_dual_add_f32 v11, 0x40c00000, v15
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v11, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v4, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v5, 0xffff, v5, v10
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    v_add3_u32 v8, v8, v11, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v11
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v9, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v12, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v11, 0x40c00000, v14
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v8, v13, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v12, v12, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v15, v11, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v4, 0xffff, v4, v8
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v3, v12, v13 :: v_dual_add_f32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v10, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, 0x400000, v10
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v10, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v10, v15, v11, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v9, v9, v14 :: v_dual_and_b32 v14, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v3, 0xffff, v3, v9
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v10, v10, v12 :: v_dual_add_f32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v13, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v13, 0x40c00000, v14 :: v_dual_lshlrev_b32 v14, 16, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v11, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v14
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v14, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v11, v13, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, 0x400000, v13
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v15, v12, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v14, v14, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v19, 0x400000, v12
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v11, v13, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v18, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v15, v15, v12, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v14, v17, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_add3_u32 v14, v18, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v12, v15, v19, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v2, v10
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v11, v11, v16, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v11
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v14, v17, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v12, v0
+; GFX11-TRUE16-NEXT:  .LBB23_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v16bf16_to_v8f32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v8
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB23_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v10, v8, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, 0x400000, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v15, v6, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-FAKE16-NEXT:    v_add3_u32 v13, v13, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v10, v11, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v15, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v12, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v12, v12, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v7, v12, v14 :: v_dual_lshlrev_b32 v12, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v8, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v9, v13, v10 :: v_dual_add_f32 v10, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, 0x400000, v5
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v12, v10, 16, 1
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v6, v11, v14 :: v_dual_lshlrev_b32 v11, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v6, v9, 0x7060302
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v11 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v12, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v10
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v14, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v11, v12, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v8, v13, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v14, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v12 :: v_dual_lshlrev_b32 v12, 16, v2
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v5, v10, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v10, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    v_add3_u32 v10, v10, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v10, v11, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v10, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v13, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v14, v10, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v11, v12, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v13, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_add3_u32 v13, v14, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v3, v11, v12 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v4, v8, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v11, 0x40c00000, v14
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, 0x400000, v10
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v14, v11, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v3, v9, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v12, v16, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v13, v15 :: v_dual_lshlrev_b32 v15, 16, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v12, v13, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v15
+; GFX11-FAKE16-NEXT:    v_add3_u32 v13, v14, v11, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, 0x400000, v11
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v15, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v12, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, 0x400000, v12
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v10, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v13, v14, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v14, v15, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v12, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v14, v15 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v11, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v16, v17, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v13, v13, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v13, v18, vcc_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v12, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB23_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -5480,112 +6121,205 @@ define <32 x i8> @bitcast_v8f32_to_v32i8(<8 x float> %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v7, v36
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v8f32_to_v32i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
-; GFX11-NEXT:    v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v34, v4
-; GFX11-NEXT:    v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v36, v2
-; GFX11-NEXT:    v_dual_mov_b32 v39, v1 :: v_dual_mov_b32 v38, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB24_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 16, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 24, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 16, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 8, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v38
-; GFX11-NEXT:    v_lshrrev_b64 v[27:28], 24, v[32:33]
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[34:35]
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[36:37]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[38:39]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v38
-; GFX11-NEXT:  .LBB24_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB24_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_dual_add_f32 v39, 1.0, v39 :: v_dual_add_f32 v32, 1.0, v32
-; GFX11-NEXT:    v_dual_add_f32 v37, 1.0, v37 :: v_dual_add_f32 v34, 1.0, v34
-; GFX11-NEXT:    v_dual_add_f32 v35, 1.0, v35 :: v_dual_add_f32 v36, 1.0, v36
-; GFX11-NEXT:    v_dual_add_f32 v33, 1.0, v33 :: v_dual_add_f32 v38, 1.0, v38
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 16, v32
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[34:35]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[36:37]
-; GFX11-NEXT:    v_lshrrev_b64 v[27:28], 24, v[32:33]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[38:39]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 24, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 16, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 8, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v38
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v38
-; GFX11-NEXT:  .LBB24_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_mov_b32_e32 v0, v38
-; GFX11-NEXT:    v_mov_b32_e32 v4, v39
-; GFX11-NEXT:    v_mov_b32_e32 v8, v36
-; GFX11-NEXT:    v_mov_b32_e32 v12, v37
-; GFX11-NEXT:    v_mov_b32_e32 v16, v34
-; GFX11-NEXT:    v_mov_b32_e32 v20, v35
-; GFX11-NEXT:    v_mov_b32_e32 v24, v32
-; GFX11-NEXT:    v_mov_b32_e32 v28, v33
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v8f32_to_v32i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v27, v5 :: v_dual_mov_b32 v26, v4
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v19, v3 :: v_dual_mov_b32 v18, v2
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v8
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB24_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[32:33]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[26:27]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[18:19]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v10
+; GFX11-TRUE16-NEXT:  .LBB24_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB24_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v32, 1.0, v32
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v33, 1.0, v33 :: v_dual_add_f32 v10, 1.0, v10
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v19, 1.0, v19 :: v_dual_add_f32 v26, 1.0, v26
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v27, 1.0, v27 :: v_dual_add_f32 v18, 1.0, v18
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[32:33]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[26:27]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[18:19]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v10
+; GFX11-TRUE16-NEXT:  .LBB24_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v11.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v11.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v18.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v36.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v19.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v19.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v26.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v18.l, v26.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v35.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.l, v27.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.l, v27.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v24.l, v32.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v26.l, v32.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.l, v34.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.l, v33.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.l, v33.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v8f32_to_v32i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v34, v4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v36, v2
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v39, v1 :: v_dual_mov_b32 v38, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB24_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 16, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 16, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v38
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[27:28], 24, v[32:33]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[34:35]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[36:37]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[38:39]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v38
+; GFX11-FAKE16-NEXT:  .LBB24_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB24_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v39, 1.0, v39 :: v_dual_add_f32 v32, 1.0, v32
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v37, 1.0, v37 :: v_dual_add_f32 v34, 1.0, v34
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v35, 1.0, v35 :: v_dual_add_f32 v36, 1.0, v36
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v33, 1.0, v33 :: v_dual_add_f32 v38, 1.0, v38
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 16, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[34:35]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[36:37]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[27:28], 24, v[32:33]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[38:39]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 16, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v38
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v38
+; GFX11-FAKE16-NEXT:  .LBB24_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v38
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v39
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v36
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v12, v37
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v16, v34
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v20, v35
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v24, v32
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v28, v33
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -6142,226 +6876,459 @@ define <8 x float> @bitcast_v32i8_to_v8f32(<32 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v32i8_to_v8f32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v32, v2 :: v_dual_mov_b32 v31, v0
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_b32 v0, off, s32 offset:4
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32
-; GFX11-NEXT:    v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v4
-; GFX11-NEXT:    v_lshlrev_b16 v51, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v49, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v50, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v48, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v38, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v35, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v36, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v37, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v9, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v2
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB25_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB25_4
-; GFX11-NEXT:  .LBB25_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB25_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v31
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v34
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v51
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v49
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v50
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v48
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v38
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v39
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v18
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v12
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v24
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v26
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v30
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v35
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v36
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v37
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v19
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v21
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v9
-; GFX11-NEXT:    v_or_b32_e32 v9, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v10, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v11, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v12, v16, v17
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v4
-; GFX11-NEXT:    v_or_b32_e32 v4, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v5, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v6, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v7, v11, v12
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr8
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB25_2
-; GFX11-NEXT:  .LBB25_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v31, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v32, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v33, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v34, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v8, 3
-; GFX11-NEXT:    v_add_nc_u16 v5, v10, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_or_b32_e32 v0, v51, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v49, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v50, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v48, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v38, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v39, v5
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_add_nc_u16 v6, v18, 3
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_add_nc_u16 v3, v12, 3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    v_add_nc_u16 v4, v14, 3
-; GFX11-NEXT:    v_add_nc_u16 v5, v16, 3
-; GFX11-NEXT:    v_add_nc_u16 v7, v20, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v22, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, v24, 3
-; GFX11-NEXT:    v_add_nc_u16 v12, v26, 3
-; GFX11-NEXT:    v_add_nc_u16 v14, v28, 3
-; GFX11-NEXT:    v_add_nc_u16 v16, v30, 3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_or_b32_e32 v3, v35, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v36, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v37, v5
-; GFX11-NEXT:    v_or_b32_e32 v6, v19, v6
-; GFX11-NEXT:    v_or_b32_e32 v7, v21, v7
-; GFX11-NEXT:    v_or_b32_e32 v8, v9, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v11, v10
-; GFX11-NEXT:    v_or_b32_e32 v10, v13, v12
-; GFX11-NEXT:    v_or_b32_e32 v11, v15, v14
-; GFX11-NEXT:    v_or_b32_e32 v12, v17, v16
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v10
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v11
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v12
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v4
-; GFX11-NEXT:    v_or_b32_e32 v4, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v5, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v6, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v7, v11, v12
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v32i8_to_v8f32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.h, v21.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.h, v19.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v23.h, v17.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v24.h, v15.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v25.h, v13.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.h, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.h, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.l, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.l, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.l, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v25.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.l, 8, v24.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v23.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.l, 8, v22.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v21.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.l, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.l, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v29.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.l, 8, v31.l
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v32
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB25_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB25_4
+; GFX11-TRUE16-NEXT:  .LBB25_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB25_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v20.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v19.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v14.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v0.h, v17.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v1.h, v16.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.l, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.h, v15.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v5, v3
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v16.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v20.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v10.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v11.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v6, v2
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v3.h, v11.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v4.h, v12.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v26.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v30.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v8.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v3.h, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v9.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v4.h, v9.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v10.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v11, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v13, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v15, v8
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v6, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v7, v10
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB25_2
+; GFX11-TRUE16-NEXT:  .LBB25_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v21.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v20.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v14.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v13.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v19.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v18.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v17.l, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v15.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v15.h, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v17.h, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v19.l, 3
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v2, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v5, v3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v13.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, v16.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, v20.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v16.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, v14.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, v18.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v10.h, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v11.h, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v12.h, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v11.l, v3.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.h, v12.l, v4.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v4.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v6, v1
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v3.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v22.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, v24.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, v26.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, v28.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, v30.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v8.l, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v8.h, v3.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v9.l, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.h, v9.h, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v10.l, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v7
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v3.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v4.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v4.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v11, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v13, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v15, v8
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v6, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v7, v10
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v32i8_to_v8f32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v32, v2 :: v_dual_mov_b32 v31, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v0, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v51, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v49, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v50, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v48, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v38, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v35, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v36, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v37, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v29
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB25_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB25_4
+; GFX11-FAKE16-NEXT:  .LBB25_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB25_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v51
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v49
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v50
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v48
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v38
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v37
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v16, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v11, v12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB25_2
+; GFX11-FAKE16-NEXT:  .LBB25_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v31, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v32, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v33, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v34, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v8, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v10, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v51, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v49, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v50, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v48, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v38, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v39, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v18, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v12, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v14, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v16, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v20, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v22, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v24, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v26, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v28, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, v30, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v35, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v36, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v37, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v19, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v21, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v9, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v11, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v13, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v15, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v17, v16
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v11, v12
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -7903,148 +8870,304 @@ define <4 x i64> @bitcast_v16bf16_to_v4i64(<16 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v16bf16_to_v4i64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v8
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB33_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v7
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v8, 0x40c00000, v8
-; GFX11-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v13, v9, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v10, v8, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v11, 0x400000, v8
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_bfe_u32 v15, v6, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-NEXT:    v_add3_u32 v13, v13, v9, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v10, v10, v8, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v8, v10, v11, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v11, v15, v6, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-NEXT:    v_bfe_u32 v12, v7, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v14, 0x400000, v7
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v12, v12, v7, 0x7fff
-; GFX11-NEXT:    v_dual_cndmask_b32 v7, v12, v14 :: v_dual_lshlrev_b32 v12, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v7, v7, v8, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-NEXT:    v_or_b32_e32 v14, 0x400000, v6
-; GFX11-NEXT:    v_dual_cndmask_b32 v9, v13, v10 :: v_dual_add_f32 v10, 0x40c00000, v12
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v8, v5, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v13, 0x400000, v5
-; GFX11-NEXT:    v_bfe_u32 v12, v10, 16, 1
-; GFX11-NEXT:    v_dual_cndmask_b32 v6, v11, v14 :: v_dual_lshlrev_b32 v11, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    v_add3_u32 v8, v8, v5, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v6, v6, v9, 0x7060302
-; GFX11-NEXT:    v_dual_add_f32 v9, 0x40c00000, v11 :: v_dual_add_f32 v4, 0x40c00000, v4
-; GFX11-NEXT:    v_add3_u32 v11, v12, v10, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v10
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v14, v9, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v10, v11, v12, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    v_or_b32_e32 v11, 0x400000, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v5, v8, v13, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v8, v14, v9, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    v_dual_add_f32 v9, 0x40c00000, v12 :: v_dual_lshlrev_b32 v12, 16, v2
-; GFX11-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-NEXT:    v_perm_b32 v5, v5, v10, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v10, v4, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v11, 0x400000, v4
-; GFX11-NEXT:    v_bfe_u32 v13, v9, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    v_add3_u32 v10, v10, v4, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_cndmask_b32_e32 v4, v10, v11, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v10, 0x40c00000, v12
-; GFX11-NEXT:    v_add3_u32 v11, v13, v9, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v9
-; GFX11-NEXT:    v_bfe_u32 v13, v3, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    v_bfe_u32 v14, v10, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v9, v11, v12, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v11, v13, v3, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v3
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT:    v_add3_u32 v13, v14, v10, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v3, v11, v12 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-NEXT:    v_perm_b32 v4, v4, v8, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v11, 0x40c00000, v14
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-NEXT:    v_or_b32_e32 v15, 0x400000, v10
-; GFX11-NEXT:    v_bfe_u32 v16, v2, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    v_bfe_u32 v14, v11, 16, 1
-; GFX11-NEXT:    v_perm_b32 v3, v3, v9, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v12, v16, v2, 0x7fff
-; GFX11-NEXT:    v_dual_cndmask_b32 v10, v13, v15 :: v_dual_lshlrev_b32 v15, 16, v0
-; GFX11-NEXT:    v_or_b32_e32 v13, 0x400000, v2
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v12, v13, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v12, 0x40c00000, v15
-; GFX11-NEXT:    v_add3_u32 v13, v14, v11, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v14, 0x400000, v11
-; GFX11-NEXT:    v_bfe_u32 v15, v1, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-NEXT:    v_bfe_u32 v16, v12, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v17, 0x400000, v12
-; GFX11-NEXT:    v_perm_b32 v2, v2, v10, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v11, v13, v14, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v14, v15, v1, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v15, 0x400000, v1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    v_add3_u32 v16, v16, v12, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_cndmask_b32 v1, v14, v15 :: v_dual_add_f32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-NEXT:    v_perm_b32 v1, v1, v11, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v13, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v18, 0x400000, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v12, v16, v17, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_add3_u32 v13, v13, v0, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v13, v18, vcc_lo
-; GFX11-NEXT:    v_perm_b32 v0, v0, v12, 0x7060302
-; GFX11-NEXT:  .LBB33_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v16bf16_to_v4i64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v8
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB33_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_lshlrev_b32 v8, 16, v7
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v15, v9, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v11, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v11, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v8, v11, v14 :: v_dual_and_b32 v7, 0xffff0000, v7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v7, 0x40c00000, v7 :: v_dual_lshlrev_b32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v15, v9, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v8.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v12, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    v_add3_u32 v12, v12, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v7, v12, v13
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v6, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, 0x400000, v6
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v9
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v7, 0xffff, v8, v7
+; GFX11-TRUE16-NEXT:    v_add3_u32 v14, v16, v6, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v14, v17, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v6.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v9, v11, v12 :: v_dual_add_f32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v6, 0xffff, v6, v9
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v10, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v14, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v13, v10, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v12, v14, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, 0x400000, v10
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v12, v13, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v10, v11, v14 :: v_dual_add_f32 v11, 0x40c00000, v15
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v11, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v4, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v5, 0xffff, v5, v10
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    v_add3_u32 v8, v8, v11, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v11
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v9, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v12, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v11, 0x40c00000, v14
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v8, v13, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v12, v12, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v15, v11, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v4, 0xffff, v4, v8
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v3, v12, v13 :: v_dual_add_f32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v10, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, 0x400000, v10
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v10, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v10, v15, v11, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v9, v9, v14 :: v_dual_and_b32 v14, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v3, 0xffff, v3, v9
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v10, v10, v12 :: v_dual_add_f32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v13, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v13, 0x40c00000, v14 :: v_dual_lshlrev_b32 v14, 16, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v11, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v14
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v14, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v11, v13, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, 0x400000, v13
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v15, v12, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v14, v14, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v19, 0x400000, v12
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v11, v13, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v18, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v15, v15, v12, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v14, v17, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_add3_u32 v14, v18, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v12, v15, v19, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v2, v10
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v11, v11, v16, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v11
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v14, v17, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v12, v0
+; GFX11-TRUE16-NEXT:  .LBB33_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v16bf16_to_v4i64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v8
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB33_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v10, v8, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, 0x400000, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v15, v6, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-FAKE16-NEXT:    v_add3_u32 v13, v13, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v10, v11, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v15, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v12, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v12, v12, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v7, v12, v14 :: v_dual_lshlrev_b32 v12, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v8, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v9, v13, v10 :: v_dual_add_f32 v10, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, 0x400000, v5
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v12, v10, 16, 1
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v6, v11, v14 :: v_dual_lshlrev_b32 v11, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v6, v9, 0x7060302
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v11 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v12, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v10
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v14, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v11, v12, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v8, v13, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v14, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v12 :: v_dual_lshlrev_b32 v12, 16, v2
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v5, v10, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v10, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    v_add3_u32 v10, v10, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v10, v11, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v10, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v13, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v14, v10, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v11, v12, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v13, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_add3_u32 v13, v14, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v3, v11, v12 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v4, v8, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v11, 0x40c00000, v14
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, 0x400000, v10
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v14, v11, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v3, v9, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v12, v16, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v13, v15 :: v_dual_lshlrev_b32 v15, 16, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v12, v13, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v15
+; GFX11-FAKE16-NEXT:    v_add3_u32 v13, v14, v11, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, 0x400000, v11
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v15, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v12, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, 0x400000, v12
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v10, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v13, v14, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v14, v15, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v12, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v14, v15 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v11, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v16, v17, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v13, v13, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v13, v18, vcc_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v12, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB33_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -8387,117 +9510,215 @@ define <32 x i8> @bitcast_v4i64_to_v32i8(<4 x i64> %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v7, v36
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v4i64_to_v32i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
-; GFX11-NEXT:    v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v34, v4
-; GFX11-NEXT:    v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v36, v2
-; GFX11-NEXT:    v_dual_mov_b32 v39, v1 :: v_dual_mov_b32 v38, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB34_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 16, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 24, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 16, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 8, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v38
-; GFX11-NEXT:    v_lshrrev_b64 v[27:28], 24, v[32:33]
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[34:35]
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[36:37]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[38:39]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v38
-; GFX11-NEXT:  .LBB34_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB34_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_co_u32 v36, vcc_lo, v36, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v37, null, 0, v37, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v34, vcc_lo, v34, 3
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v35, null, 0, v35, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v32, vcc_lo, v32, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v33, null, 0, v33, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v38, vcc_lo, v38, 3
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v39, null, 0, v39, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshrrev_b64 v[27:28], 24, v[32:33]
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[34:35]
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[36:37]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[38:39]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 16, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 24, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 16, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 8, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v38
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v38
-; GFX11-NEXT:  .LBB34_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_mov_b32_e32 v0, v38
-; GFX11-NEXT:    v_mov_b32_e32 v4, v39
-; GFX11-NEXT:    v_mov_b32_e32 v8, v36
-; GFX11-NEXT:    v_mov_b32_e32 v12, v37
-; GFX11-NEXT:    v_mov_b32_e32 v16, v34
-; GFX11-NEXT:    v_mov_b32_e32 v20, v35
-; GFX11-NEXT:    v_mov_b32_e32 v24, v32
-; GFX11-NEXT:    v_mov_b32_e32 v28, v33
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v4i64_to_v32i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v27, v5 :: v_dual_mov_b32 v26, v4
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v19, v3 :: v_dual_mov_b32 v18, v2
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v8
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB34_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[32:33]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[26:27]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[18:19]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v10
+; GFX11-TRUE16-NEXT:  .LBB34_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB34_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v18, vcc_lo, v18, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v19, null, 0, v19, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v26, vcc_lo, v26, 3
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v27, null, 0, v27, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v32, vcc_lo, v32, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v33, null, 0, v33, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v10, vcc_lo, v10, 3
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[32:33]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[26:27]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[18:19]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v10
+; GFX11-TRUE16-NEXT:  .LBB34_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v11.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v11.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v18.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v36.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v19.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v19.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v26.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v18.l, v26.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v35.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.l, v27.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.l, v27.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v24.l, v32.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v26.l, v32.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.l, v34.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.l, v33.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.l, v33.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v4i64_to_v32i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v34, v4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v36, v2
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v39, v1 :: v_dual_mov_b32 v38, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB34_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 16, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 16, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v38
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[27:28], 24, v[32:33]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[34:35]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[36:37]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[38:39]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v38
+; GFX11-FAKE16-NEXT:  .LBB34_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB34_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v36, vcc_lo, v36, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v37, null, 0, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v34, vcc_lo, v34, 3
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v35, null, 0, v35, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v32, vcc_lo, v32, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v33, null, 0, v33, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v38, vcc_lo, v38, 3
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v39, null, 0, v39, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[27:28], 24, v[32:33]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[34:35]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[36:37]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[38:39]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 16, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 16, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v38
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v38
+; GFX11-FAKE16-NEXT:  .LBB34_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v38
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v39
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v36
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v12, v37
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v16, v34
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v20, v35
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v24, v32
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v28, v33
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -9054,226 +10275,459 @@ define <4 x i64> @bitcast_v32i8_to_v4i64(<32 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v32i8_to_v4i64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v32, v2 :: v_dual_mov_b32 v31, v0
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_b32 v0, off, s32 offset:4
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32
-; GFX11-NEXT:    v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v4
-; GFX11-NEXT:    v_lshlrev_b16 v51, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v49, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v50, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v48, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v38, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v35, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v36, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v37, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v9, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v2
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB35_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB35_4
-; GFX11-NEXT:  .LBB35_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB35_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v31
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v34
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v51
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v49
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v50
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v48
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v38
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v39
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v18
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v12
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v24
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v26
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v30
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v35
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v36
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v37
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v19
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v21
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v9
-; GFX11-NEXT:    v_or_b32_e32 v9, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v10, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v11, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v12, v16, v17
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v4
-; GFX11-NEXT:    v_or_b32_e32 v4, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v5, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v6, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v7, v11, v12
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr8
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB35_2
-; GFX11-NEXT:  .LBB35_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v31, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v32, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v33, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v34, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v8, 3
-; GFX11-NEXT:    v_add_nc_u16 v5, v10, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_or_b32_e32 v0, v51, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v49, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v50, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v48, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v38, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v39, v5
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_add_nc_u16 v6, v18, 3
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_add_nc_u16 v3, v12, 3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    v_add_nc_u16 v4, v14, 3
-; GFX11-NEXT:    v_add_nc_u16 v5, v16, 3
-; GFX11-NEXT:    v_add_nc_u16 v7, v20, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v22, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, v24, 3
-; GFX11-NEXT:    v_add_nc_u16 v12, v26, 3
-; GFX11-NEXT:    v_add_nc_u16 v14, v28, 3
-; GFX11-NEXT:    v_add_nc_u16 v16, v30, 3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_or_b32_e32 v3, v35, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v36, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v37, v5
-; GFX11-NEXT:    v_or_b32_e32 v6, v19, v6
-; GFX11-NEXT:    v_or_b32_e32 v7, v21, v7
-; GFX11-NEXT:    v_or_b32_e32 v8, v9, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v11, v10
-; GFX11-NEXT:    v_or_b32_e32 v10, v13, v12
-; GFX11-NEXT:    v_or_b32_e32 v11, v15, v14
-; GFX11-NEXT:    v_or_b32_e32 v12, v17, v16
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v10
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v11
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v12
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v4
-; GFX11-NEXT:    v_or_b32_e32 v4, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v5, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v6, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v7, v11, v12
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v32i8_to_v4i64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.h, v21.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.h, v19.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v23.h, v17.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v24.h, v15.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v25.h, v13.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.h, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.h, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.l, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.l, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.l, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v25.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.l, 8, v24.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v23.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.l, 8, v22.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v21.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.l, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.l, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v29.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.l, 8, v31.l
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v32
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB35_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB35_4
+; GFX11-TRUE16-NEXT:  .LBB35_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB35_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v20.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v19.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v14.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v0.h, v17.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v1.h, v16.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.l, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.h, v15.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v5, v3
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v16.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v20.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v10.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v11.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v6, v2
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v3.h, v11.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v4.h, v12.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v26.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v30.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v8.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v3.h, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v9.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v4.h, v9.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v10.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v11, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v13, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v15, v8
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v6, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v7, v10
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB35_2
+; GFX11-TRUE16-NEXT:  .LBB35_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v21.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v20.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v14.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v13.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v19.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v18.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v17.l, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v15.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v15.h, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v17.h, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v19.l, 3
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v2, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v5, v3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v13.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, v16.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, v20.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v16.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, v14.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, v18.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v10.h, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v11.h, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v12.h, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v11.l, v3.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.h, v12.l, v4.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v4.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v6, v1
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v3.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v22.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, v24.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, v26.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, v28.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, v30.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v8.l, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v8.h, v3.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v9.l, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.h, v9.h, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v10.l, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v7
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v3.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v4.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v4.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v11, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v13, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v15, v8
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v6, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v7, v10
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v32i8_to_v4i64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v32, v2 :: v_dual_mov_b32 v31, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v0, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v51, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v49, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v50, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v48, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v38, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v35, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v36, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v37, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v29
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB35_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB35_4
+; GFX11-FAKE16-NEXT:  .LBB35_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB35_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v51
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v49
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v50
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v48
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v38
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v37
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v16, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v11, v12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB35_2
+; GFX11-FAKE16-NEXT:  .LBB35_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v31, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v32, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v33, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v34, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v8, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v10, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v51, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v49, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v50, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v48, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v38, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v39, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v18, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v12, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v14, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v16, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v20, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v22, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v24, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v26, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v28, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, v30, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v35, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v36, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v37, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v19, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v21, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v9, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v11, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v13, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v15, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v17, v16
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v11, v12
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -10571,148 +12025,304 @@ define <4 x double> @bitcast_v16bf16_to_v4f64(<16 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v16bf16_to_v4f64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v8
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB41_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v7
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v8, 0x40c00000, v8
-; GFX11-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v13, v9, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v10, v8, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v11, 0x400000, v8
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_bfe_u32 v15, v6, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-NEXT:    v_add3_u32 v13, v13, v9, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v10, v10, v8, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v8, v10, v11, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v11, v15, v6, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-NEXT:    v_bfe_u32 v12, v7, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v14, 0x400000, v7
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v12, v12, v7, 0x7fff
-; GFX11-NEXT:    v_dual_cndmask_b32 v7, v12, v14 :: v_dual_lshlrev_b32 v12, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v7, v7, v8, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-NEXT:    v_or_b32_e32 v14, 0x400000, v6
-; GFX11-NEXT:    v_dual_cndmask_b32 v9, v13, v10 :: v_dual_add_f32 v10, 0x40c00000, v12
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v8, v5, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v13, 0x400000, v5
-; GFX11-NEXT:    v_bfe_u32 v12, v10, 16, 1
-; GFX11-NEXT:    v_dual_cndmask_b32 v6, v11, v14 :: v_dual_lshlrev_b32 v11, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    v_add3_u32 v8, v8, v5, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v6, v6, v9, 0x7060302
-; GFX11-NEXT:    v_dual_add_f32 v9, 0x40c00000, v11 :: v_dual_add_f32 v4, 0x40c00000, v4
-; GFX11-NEXT:    v_add3_u32 v11, v12, v10, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v10
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v14, v9, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v10, v11, v12, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    v_or_b32_e32 v11, 0x400000, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v5, v8, v13, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v8, v14, v9, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    v_dual_add_f32 v9, 0x40c00000, v12 :: v_dual_lshlrev_b32 v12, 16, v2
-; GFX11-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-NEXT:    v_perm_b32 v5, v5, v10, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v10, v4, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v11, 0x400000, v4
-; GFX11-NEXT:    v_bfe_u32 v13, v9, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    v_add3_u32 v10, v10, v4, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_cndmask_b32_e32 v4, v10, v11, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v10, 0x40c00000, v12
-; GFX11-NEXT:    v_add3_u32 v11, v13, v9, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v9
-; GFX11-NEXT:    v_bfe_u32 v13, v3, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    v_bfe_u32 v14, v10, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v9, v11, v12, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v11, v13, v3, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v3
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT:    v_add3_u32 v13, v14, v10, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v3, v11, v12 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-NEXT:    v_perm_b32 v4, v4, v8, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v11, 0x40c00000, v14
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-NEXT:    v_or_b32_e32 v15, 0x400000, v10
-; GFX11-NEXT:    v_bfe_u32 v16, v2, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    v_bfe_u32 v14, v11, 16, 1
-; GFX11-NEXT:    v_perm_b32 v3, v3, v9, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v12, v16, v2, 0x7fff
-; GFX11-NEXT:    v_dual_cndmask_b32 v10, v13, v15 :: v_dual_lshlrev_b32 v15, 16, v0
-; GFX11-NEXT:    v_or_b32_e32 v13, 0x400000, v2
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v12, v13, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v12, 0x40c00000, v15
-; GFX11-NEXT:    v_add3_u32 v13, v14, v11, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v14, 0x400000, v11
-; GFX11-NEXT:    v_bfe_u32 v15, v1, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-NEXT:    v_bfe_u32 v16, v12, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v17, 0x400000, v12
-; GFX11-NEXT:    v_perm_b32 v2, v2, v10, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v11, v13, v14, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v14, v15, v1, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v15, 0x400000, v1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    v_add3_u32 v16, v16, v12, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_cndmask_b32 v1, v14, v15 :: v_dual_add_f32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-NEXT:    v_perm_b32 v1, v1, v11, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v13, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v18, 0x400000, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v12, v16, v17, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_add3_u32 v13, v13, v0, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v13, v18, vcc_lo
-; GFX11-NEXT:    v_perm_b32 v0, v0, v12, 0x7060302
-; GFX11-NEXT:  .LBB41_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v16bf16_to_v4f64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v8
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB41_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_lshlrev_b32 v8, 16, v7
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v15, v9, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v11, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v11, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v8, v11, v14 :: v_dual_and_b32 v7, 0xffff0000, v7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v7, 0x40c00000, v7 :: v_dual_lshlrev_b32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v15, v9, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v8.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v12, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    v_add3_u32 v12, v12, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v7, v12, v13
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v6, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, 0x400000, v6
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v9
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v7, 0xffff, v8, v7
+; GFX11-TRUE16-NEXT:    v_add3_u32 v14, v16, v6, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v14, v17, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v6.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v9, v11, v12 :: v_dual_add_f32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v6, 0xffff, v6, v9
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v10, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v14, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v13, v10, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v12, v14, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, 0x400000, v10
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v12, v13, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v10, v11, v14 :: v_dual_add_f32 v11, 0x40c00000, v15
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v11, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v4, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v5, 0xffff, v5, v10
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    v_add3_u32 v8, v8, v11, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v11
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v9, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v12, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v11, 0x40c00000, v14
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v8, v13, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v12, v12, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v15, v11, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v4, 0xffff, v4, v8
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v3, v12, v13 :: v_dual_add_f32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v10, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, 0x400000, v10
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v10, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v10, v15, v11, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v9, v9, v14 :: v_dual_and_b32 v14, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v3, 0xffff, v3, v9
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v10, v10, v12 :: v_dual_add_f32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v13, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v13, 0x40c00000, v14 :: v_dual_lshlrev_b32 v14, 16, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v11, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v14
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v14, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v11, v13, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, 0x400000, v13
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v15, v12, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v14, v14, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v19, 0x400000, v12
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v11, v13, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v18, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v15, v15, v12, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v14, v17, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_add3_u32 v14, v18, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v12, v15, v19, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v2, v10
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v11, v11, v16, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v11
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v14, v17, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v12, v0
+; GFX11-TRUE16-NEXT:  .LBB41_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v16bf16_to_v4f64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v8
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB41_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v10, v8, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, 0x400000, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v15, v6, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-FAKE16-NEXT:    v_add3_u32 v13, v13, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v10, v11, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v15, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v12, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v12, v12, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v7, v12, v14 :: v_dual_lshlrev_b32 v12, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v8, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v9, v13, v10 :: v_dual_add_f32 v10, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, 0x400000, v5
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v12, v10, 16, 1
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v6, v11, v14 :: v_dual_lshlrev_b32 v11, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v6, v9, 0x7060302
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v11 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v12, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v10
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v14, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v11, v12, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v8, v13, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v14, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v12 :: v_dual_lshlrev_b32 v12, 16, v2
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v5, v10, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v10, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    v_add3_u32 v10, v10, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v10, v11, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v10, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v13, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v14, v10, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v11, v12, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v13, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_add3_u32 v13, v14, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v3, v11, v12 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v4, v8, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v11, 0x40c00000, v14
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, 0x400000, v10
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v14, v11, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v3, v9, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v12, v16, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v13, v15 :: v_dual_lshlrev_b32 v15, 16, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v12, v13, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v15
+; GFX11-FAKE16-NEXT:    v_add3_u32 v13, v14, v11, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, 0x400000, v11
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v15, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v12, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, 0x400000, v12
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v10, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v13, v14, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v14, v15, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v12, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v14, v15 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v11, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v16, v17, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v13, v13, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v13, v18, vcc_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v12, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB41_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -11049,112 +12659,205 @@ define <32 x i8> @bitcast_v4f64_to_v32i8(<4 x double> %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v7, v36
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v4f64_to_v32i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
-; GFX11-NEXT:    v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v34, v4
-; GFX11-NEXT:    v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v36, v2
-; GFX11-NEXT:    v_dual_mov_b32 v39, v1 :: v_dual_mov_b32 v38, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB42_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 16, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 24, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 16, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 8, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v38
-; GFX11-NEXT:    v_lshrrev_b64 v[27:28], 24, v[32:33]
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[34:35]
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[36:37]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[38:39]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v38
-; GFX11-NEXT:  .LBB42_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB42_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_f64 v[32:33], v[32:33], 1.0
-; GFX11-NEXT:    v_add_f64 v[34:35], v[34:35], 1.0
-; GFX11-NEXT:    v_add_f64 v[36:37], v[36:37], 1.0
-; GFX11-NEXT:    v_add_f64 v[38:39], v[38:39], 1.0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshrrev_b64 v[27:28], 24, v[32:33]
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[34:35]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[36:37]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[38:39]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 16, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 24, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 16, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 8, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v38
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v38
-; GFX11-NEXT:  .LBB42_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_mov_b32_e32 v0, v38
-; GFX11-NEXT:    v_mov_b32_e32 v4, v39
-; GFX11-NEXT:    v_mov_b32_e32 v8, v36
-; GFX11-NEXT:    v_mov_b32_e32 v12, v37
-; GFX11-NEXT:    v_mov_b32_e32 v16, v34
-; GFX11-NEXT:    v_mov_b32_e32 v20, v35
-; GFX11-NEXT:    v_mov_b32_e32 v24, v32
-; GFX11-NEXT:    v_mov_b32_e32 v28, v33
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v4f64_to_v32i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v27, v5 :: v_dual_mov_b32 v26, v4
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v19, v3 :: v_dual_mov_b32 v18, v2
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v8
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB42_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[32:33]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[26:27]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[18:19]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v10
+; GFX11-TRUE16-NEXT:  .LBB42_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB42_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_f64 v[32:33], v[32:33], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[26:27], v[26:27], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[18:19], v[18:19], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[10:11], v[10:11], 1.0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[32:33]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[26:27]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[18:19]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v10
+; GFX11-TRUE16-NEXT:  .LBB42_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v11.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v11.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v18.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v36.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v19.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v19.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v26.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v18.l, v26.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v35.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.l, v27.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.l, v27.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v24.l, v32.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v26.l, v32.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.l, v34.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.l, v33.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.l, v33.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v4f64_to_v32i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v34, v4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v36, v2
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v39, v1 :: v_dual_mov_b32 v38, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB42_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 16, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 16, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v38
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[27:28], 24, v[32:33]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[34:35]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[36:37]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[38:39]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v38
+; GFX11-FAKE16-NEXT:  .LBB42_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB42_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_f64 v[32:33], v[32:33], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[34:35], v[34:35], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[36:37], v[36:37], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[38:39], v[38:39], 1.0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[27:28], 24, v[32:33]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[34:35]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[36:37]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[38:39]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 16, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 16, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v38
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v38
+; GFX11-FAKE16-NEXT:  .LBB42_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v38
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v39
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v36
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v12, v37
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v16, v34
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v20, v35
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v24, v32
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v28, v33
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -11711,226 +13414,459 @@ define <4 x double> @bitcast_v32i8_to_v4f64(<32 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v32i8_to_v4f64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v32, v2 :: v_dual_mov_b32 v31, v0
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_b32 v0, off, s32 offset:4
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32
-; GFX11-NEXT:    v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v4
-; GFX11-NEXT:    v_lshlrev_b16 v51, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v49, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v50, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v48, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v38, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v35, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v36, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v37, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v9, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v2
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB43_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB43_4
-; GFX11-NEXT:  .LBB43_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB43_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v31
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v34
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v51
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v49
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v50
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v48
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v38
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v39
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v18
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v12
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v24
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v26
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v30
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v35
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v36
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v37
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v19
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v21
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v9
-; GFX11-NEXT:    v_or_b32_e32 v9, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v10, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v11, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v12, v16, v17
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v4
-; GFX11-NEXT:    v_or_b32_e32 v4, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v5, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v6, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v7, v11, v12
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr8
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB43_2
-; GFX11-NEXT:  .LBB43_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v31, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v32, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v33, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v34, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v8, 3
-; GFX11-NEXT:    v_add_nc_u16 v5, v10, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_or_b32_e32 v0, v51, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v49, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v50, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v48, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v38, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v39, v5
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_add_nc_u16 v6, v18, 3
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_add_nc_u16 v3, v12, 3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    v_add_nc_u16 v4, v14, 3
-; GFX11-NEXT:    v_add_nc_u16 v5, v16, 3
-; GFX11-NEXT:    v_add_nc_u16 v7, v20, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v22, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, v24, 3
-; GFX11-NEXT:    v_add_nc_u16 v12, v26, 3
-; GFX11-NEXT:    v_add_nc_u16 v14, v28, 3
-; GFX11-NEXT:    v_add_nc_u16 v16, v30, 3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_or_b32_e32 v3, v35, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v36, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v37, v5
-; GFX11-NEXT:    v_or_b32_e32 v6, v19, v6
-; GFX11-NEXT:    v_or_b32_e32 v7, v21, v7
-; GFX11-NEXT:    v_or_b32_e32 v8, v9, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v11, v10
-; GFX11-NEXT:    v_or_b32_e32 v10, v13, v12
-; GFX11-NEXT:    v_or_b32_e32 v11, v15, v14
-; GFX11-NEXT:    v_or_b32_e32 v12, v17, v16
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v10
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v11
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v12
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v4
-; GFX11-NEXT:    v_or_b32_e32 v4, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v5, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v6, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v7, v11, v12
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v32i8_to_v4f64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.h, v21.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.h, v19.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v23.h, v17.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v24.h, v15.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v25.h, v13.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.h, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.h, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.l, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.l, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.l, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v25.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.l, 8, v24.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v23.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.l, 8, v22.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v21.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.l, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.l, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v29.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.l, 8, v31.l
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v32
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB43_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB43_4
+; GFX11-TRUE16-NEXT:  .LBB43_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB43_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v20.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v19.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v14.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v0.h, v17.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v1.h, v16.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.l, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.h, v15.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v5, v3
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v16.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v20.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v10.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v11.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v6, v2
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v3.h, v11.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v4.h, v12.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v26.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v30.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v8.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v3.h, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v9.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v4.h, v9.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v10.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v11, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v13, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v15, v8
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v6, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v7, v10
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB43_2
+; GFX11-TRUE16-NEXT:  .LBB43_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v21.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v20.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v14.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v13.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v19.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v18.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v17.l, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v15.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v15.h, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v17.h, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v19.l, 3
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v2, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v5, v3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v13.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, v16.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, v20.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v16.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, v14.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, v18.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v10.h, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v11.h, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v12.h, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v11.l, v3.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.h, v12.l, v4.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v4.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v6, v1
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v3.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v22.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, v24.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, v26.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, v28.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, v30.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v8.l, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v8.h, v3.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v9.l, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.h, v9.h, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v10.l, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v7
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v3.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v4.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v4.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v11, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v13, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v15, v8
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v6, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v7, v10
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v32i8_to_v4f64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v32, v2 :: v_dual_mov_b32 v31, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v0, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v51, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v49, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v50, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v48, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v38, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v35, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v36, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v37, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v29
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB43_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB43_4
+; GFX11-FAKE16-NEXT:  .LBB43_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB43_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v51
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v49
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v50
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v48
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v38
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v37
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v16, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v11, v12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB43_2
+; GFX11-FAKE16-NEXT:  .LBB43_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v31, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v32, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v33, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v34, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v8, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v10, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v51, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v49, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v50, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v48, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v38, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v39, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v18, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v12, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v14, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v16, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v20, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v22, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v24, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v26, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v28, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, v30, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v35, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v36, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v37, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v19, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v21, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v9, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v11, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v13, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v15, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v17, v16
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v11, v12
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -12996,152 +14932,310 @@ define <16 x i16> @bitcast_v16bf16_to_v16i16(<16 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v16bf16_to_v16i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v8
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB47_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_lshlrev_b32 v8, 16, v0
-; GFX11-NEXT:    v_add_f32_e32 v8, 0x40c00000, v8
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v13, v9, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v11, v8, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v14, 0x400000, v8
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v13, v13, v9, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v11, v11, v8, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v8, v11, v14 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11-NEXT:    v_or_b32_e32 v11, 0x400000, v9
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v14, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_add_f32 v3, 0x40c00000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v12, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v15, 0x400000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_or_b32_e32 v16, 0x400000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v12, v12, v0, 0x7fff
-; GFX11-NEXT:    v_dual_cndmask_b32 v0, v12, v15 :: v_dual_lshlrev_b32 v15, 16, v4
-; GFX11-NEXT:    v_bfe_u32 v12, v1, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v0, v0, v8, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-NEXT:    v_cndmask_b32_e32 v9, v13, v11, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v11, v12, v1, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v2
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-NEXT:    v_or_b32_e32 v17, 0x400000, v15
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v1, v11, v12 :: v_dual_add_f32 v10, 0x40c00000, v10
-; GFX11-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v18, v4, 16, 1
-; GFX11-NEXT:    v_perm_b32 v1, v1, v9, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v13, v10, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v10
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    v_add3_u32 v11, v13, v10, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v13, v2, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v10, v11, v12, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v11, v13, v2, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v2
-; GFX11-NEXT:    v_bfe_u32 v13, v14, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v11, v12, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v11, v13, v14, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v14
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-NEXT:    v_bfe_u32 v14, v15, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v13, v3, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v11, v11, v12 :: v_dual_lshlrev_b32 v12, 16, v5
-; GFX11-NEXT:    v_add3_u32 v14, v14, v15, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT:    v_add3_u32 v15, v18, v4, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-NEXT:    v_add3_u32 v13, v13, v3, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v14, v14, v17, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-NEXT:    v_perm_b32 v2, v2, v10, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v19, v12, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v12
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v21, v5, 16, 1
-; GFX11-NEXT:    v_add3_u32 v18, v19, v12, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v6
-; GFX11-NEXT:    v_or_b32_e32 v17, 0x400000, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v4, v15, v17 :: v_dual_add_f32 v15, 0x40c00000, v19
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-NEXT:    v_add3_u32 v17, v21, v5, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v19, v15, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v12, v18, v20, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v7
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v15
-; GFX11-NEXT:    v_add3_u32 v19, v19, v15, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v22, v6, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-NEXT:    v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v23, v18, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v15, v19, v21, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v21, v22, v6, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v6
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    v_bfe_u32 v19, v7, 16, 1
-; GFX11-NEXT:    v_add3_u32 v23, v23, v18, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v24, 0x400000, v18
-; GFX11-NEXT:    v_or_b32_e32 v25, 0x400000, v7
-; GFX11-NEXT:    v_cndmask_b32_e32 v6, v21, v22, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_add3_u32 v19, v19, v7, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v6, v6, v15, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v18, v23, v24, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    v_cndmask_b32_e32 v7, v19, v25, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v7, v7, v18, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v5, v17, v20, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_perm_b32 v4, v4, v14, 0x7060302
-; GFX11-NEXT:    v_perm_b32 v5, v5, v12, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v13, v16, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v3, v3, v11, 0x7060302
-; GFX11-NEXT:  .LBB47_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v16bf16_to_v16i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v8
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB47_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v1, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, 0x400000, v6
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v11, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v15, v9, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v11, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v12, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v11, v14, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v12, v12, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_add3_u32 v14, v16, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v15, v9, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v0, v12, v13 :: v_dual_and_b32 v13, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v9
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v14, v17, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, 0x400000, v10
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v9, v11, v12 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v11, v10, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v12, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v11, v10, 0x7fff
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v1, v1, 16, v9
+; GFX11-TRUE16-NEXT:    v_add3_u32 v12, v12, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v0, v8, 16, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v12, v14, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v12, v13, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v14, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v10, v11, v15, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v12, v13, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v13
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v5
+; GFX11-TRUE16-NEXT:    v_add3_u32 v14, v14, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v11, v11, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v13, 0x40c00000, v13 :: v_dual_add_f32 v12, 0x40c00000, v15
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v14, v16, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v13, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v19, 0x400000, v13
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v14, v12, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, 0x400000, v12
+; GFX11-TRUE16-NEXT:    v_add3_u32 v16, v16, v13, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-TRUE16-NEXT:    v_add3_u32 v14, v14, v12, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v2, v2, 16, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v15, v4, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v18, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    v_add3_u32 v15, v15, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v15, v18, vcc_lo
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v7
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v15, 0x40c00000, v21
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_cndmask_b32 v13, v16, v19
+; GFX11-TRUE16-NEXT:    v_add3_u32 v16, v20, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v19, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v15, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, 0x400000, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v15
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v16, v19, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v6, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v20, v15, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v18, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v22, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v16, v16, v6, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v25, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_add3_u32 v20, v20, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v5.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v22, v22, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v16, v23, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v3, v11, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v6.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v16, v20, v24, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v7, v22, v25, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v7.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v15, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 16, v15
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v12, v14, v17, vcc_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v4.h
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v7, v6, 16, v7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v6, v5, 16, v15
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v5, v4, 16, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v12
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v4, v14, 16, v4
+; GFX11-TRUE16-NEXT:  .LBB47_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v16bf16_to_v16i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v8
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB47_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_lshlrev_b32 v8, 16, v0
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v11, v8, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, 0x400000, v8
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v13, v13, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v11, v8, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v8, v11, v14 :: v_dual_and_b32 v1, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v14, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_add_f32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v12, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, 0x400000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v12, v12, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v12, v15 :: v_dual_lshlrev_b32 v15, 16, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v12, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v8, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v13, v11, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v12, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, 0x400000, v15
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v11, v12 :: v_dual_add_f32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v18, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v9, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v10, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v10
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v13, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v2, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v11, v12, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v13, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v14, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v11, v12, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v13, v14, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v14
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v14, v15, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v3, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v11, v11, v12 :: v_dual_lshlrev_b32 v12, 16, v5
+; GFX11-FAKE16-NEXT:    v_add3_u32 v14, v14, v15, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT:    v_add3_u32 v15, v18, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_add3_u32 v13, v13, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v14, v14, v17, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v10, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v19, v12, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v18, v19, v12, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v15, v17 :: v_dual_add_f32 v15, 0x40c00000, v19
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v21, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v19, v15, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v18, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v15
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v19, v15, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v6, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v23, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v15, v19, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v22, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v19, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v23, v23, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v21, v22, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v19, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v6, v15, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v23, v24, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v19, v25, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v18, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v17, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v4, v14, 0x7060302
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v5, v12, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v13, v16, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v3, v11, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB47_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -13600,114 +15694,209 @@ define <32 x i8> @bitcast_v16i16_to_v32i8(<16 x i16> %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v7, v36
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v16i16_to_v32i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
-; GFX11-NEXT:    v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v34, v4
-; GFX11-NEXT:    v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v36, v2
-; GFX11-NEXT:    v_dual_mov_b32 v39, v1 :: v_dual_mov_b32 v38, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB48_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 16, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 24, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 16, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 8, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v38
-; GFX11-NEXT:    v_lshrrev_b64 v[27:28], 24, v[32:33]
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[34:35]
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[36:37]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[38:39]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v38
-; GFX11-NEXT:  .LBB48_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB48_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_pk_add_u16 v39, v39, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v37, v37, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v35, v35, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v33, v33, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v32, v32, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v34, v34, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v36, v36, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v38, v38, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
-; GFX11-NEXT:    v_lshrrev_b64 v[27:28], 24, v[32:33]
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[34:35]
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[36:37]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[38:39]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 16, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 24, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 16, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 8, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v38
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v38
-; GFX11-NEXT:  .LBB48_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_mov_b32_e32 v0, v38
-; GFX11-NEXT:    v_mov_b32_e32 v4, v39
-; GFX11-NEXT:    v_mov_b32_e32 v8, v36
-; GFX11-NEXT:    v_mov_b32_e32 v12, v37
-; GFX11-NEXT:    v_mov_b32_e32 v16, v34
-; GFX11-NEXT:    v_mov_b32_e32 v20, v35
-; GFX11-NEXT:    v_mov_b32_e32 v24, v32
-; GFX11-NEXT:    v_mov_b32_e32 v28, v33
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v16i16_to_v32i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v27, v5 :: v_dual_mov_b32 v26, v4
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v19, v3 :: v_dual_mov_b32 v18, v2
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v8
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB48_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[32:33]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[26:27]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[18:19]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v10
+; GFX11-TRUE16-NEXT:  .LBB48_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB48_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v33, v33, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v32, v32, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[32:33]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[26:27]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[18:19]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v10
+; GFX11-TRUE16-NEXT:  .LBB48_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v11.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v11.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v18.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v36.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v19.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v19.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v26.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v18.l, v26.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v35.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.l, v27.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.l, v27.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v24.l, v32.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v26.l, v32.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.l, v34.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.l, v33.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.l, v33.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v16i16_to_v32i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v34, v4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v36, v2
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v39, v1 :: v_dual_mov_b32 v38, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB48_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 16, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 16, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v38
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[27:28], 24, v[32:33]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[34:35]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[36:37]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[38:39]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v38
+; GFX11-FAKE16-NEXT:  .LBB48_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB48_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v39, v39, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v37, v37, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v35, v35, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v33, v33, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v32, v32, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v34, v34, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v36, v36, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v38, v38, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[27:28], 24, v[32:33]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[34:35]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[36:37]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[38:39]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 16, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 16, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v38
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v38
+; GFX11-FAKE16-NEXT:  .LBB48_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v38
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v39
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v36
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v12, v37
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v16, v34
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v20, v35
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v24, v32
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v28, v33
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -14296,194 +16485,374 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v32i8_to_v16i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v34, v2 :: v_dual_mov_b32 v33, v0
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_b32 v0, off, s32 offset:4
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32
-; GFX11-NEXT:    v_dual_mov_b32 v31, v6 :: v_dual_mov_b32 v32, v4
-; GFX11-NEXT:    v_lshlrev_b16 v37, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v35, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v38, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v36, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v48, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v9, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v49, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v2
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB49_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB49_4
-; GFX11-NEXT:  .LBB49_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB49_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v34
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v31
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v37
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v35
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v38
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v36
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v48
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v9
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v18
-; GFX11-NEXT:    v_perm_b32 v1, v3, v2, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v12
-; GFX11-NEXT:    v_perm_b32 v2, v5, v4, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v24
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v11
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v26
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v30
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v39
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v15
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v13
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v49
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v17
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v21
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v19
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v23
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v25
-; GFX11-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v4, v6, v5, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v5, v8, v7, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v6, v10, v9, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v7, v12, v11, 0x5040100
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr8
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB49_2
-; GFX11-NEXT:  .LBB49_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v28, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v30, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v24, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v26, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v20, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v5, v22, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v0, v23, v0
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v1, v25, v1
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_or_b32_e32 v2, v21, v2
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v19, v3
-; GFX11-NEXT:    v_add_nc_u16 v19, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v49, v4
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v17, v5
-; GFX11-NEXT:    v_add_nc_u16 v17, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v16, 3
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v12, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v18, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v14, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v2
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v0, v15, v0
-; GFX11-NEXT:    v_add_nc_u16 v2, v8, 3
-; GFX11-NEXT:    v_or_b32_e32 v1, v39, v1
-; GFX11-NEXT:    v_add_nc_u16 v14, v31, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, v10, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v13, v3
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v11, v4
-; GFX11-NEXT:    v_add_nc_u16 v4, v32, 3
-; GFX11-NEXT:    v_add_nc_u16 v11, v33, 3
-; GFX11-NEXT:    v_add_nc_u16 v13, v34, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v2, v48, v2
-; GFX11-NEXT:    v_or_b32_e32 v4, v38, v4
-; GFX11-NEXT:    v_or_b32_e32 v11, v37, v11
-; GFX11-NEXT:    v_or_b32_e32 v13, v35, v13
-; GFX11-NEXT:    v_or_b32_e32 v14, v36, v14
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v10
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v11
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v13
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v14
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v0
-; GFX11-NEXT:    v_perm_b32 v0, v11, v10, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v1, v13, v4, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v2, v9, v2, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v3, v14, v3, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v4, v15, v8, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v5, v12, v5, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v6, v17, v6, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v7, v19, v7, 0x5040100
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v32i8_to_v16i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v17.h, v17.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.h, v13.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.h, v11.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.h, v9.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.h, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.l, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.l, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.l, 8, v15.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v14.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.l, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v17.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.l, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.l, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v29.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v31.l
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v32
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB49_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB49_4
+; GFX11-TRUE16-NEXT:  .LBB49_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB49_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v16.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v20.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v26.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v30.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v8.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v10.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v1.h, v11.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v17.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v2.h, v11.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v14.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v3.h, v15.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v15.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.h, v4.h, v16.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v21.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.h, v5.h, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v19.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v6.h, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v20.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v7.h, v19.h
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB49_2
+; GFX11-TRUE16-NEXT:  .LBB49_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v28.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v30.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v24.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v26.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v20.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v20.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v19.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v19.l, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v22.l, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v18.h, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v21.l, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v18.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v16.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v13.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v14.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v17.h, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v16.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v15.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v14.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v15.l, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v13.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v10.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v12.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v9.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v12.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v9.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v17.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v11.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v10.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v11.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.h, v8.h, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, 0x300, v9.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v8.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, 0x300, v8.l
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v32i8_to_v16i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v34, v2 :: v_dual_mov_b32 v33, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v0, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v31, v6 :: v_dual_mov_b32 v32, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v37, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v35, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v38, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v36, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v48, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v49, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v29
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB49_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB49_4
+; GFX11-FAKE16-NEXT:  .LBB49_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB49_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v37
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v38
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v48
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v9
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v5, v4, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v49
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v25
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v6, v5, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v8, v7, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v10, v9, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v12, v11, 0x5040100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB49_2
+; GFX11-FAKE16-NEXT:  .LBB49_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v28, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v30, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v24, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v26, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v20, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v22, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v23, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v25, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v21, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v19, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v49, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v17, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v16, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v12, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v18, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v14, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v15, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v8, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v39, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v31, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v10, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v13, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v11, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v32, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, v33, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v34, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v48, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v38, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v37, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v35, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v36, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v13
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v14
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v11, v10, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v13, v4, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v9, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v14, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v15, v8, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v12, v5, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v17, v6, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v19, v7, 0x5040100
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -15205,152 +17574,308 @@ define <16 x half> @bitcast_v16bf16_to_v16f16(<16 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v16bf16_to_v16f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v8
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB51_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_lshlrev_b32 v8, 16, v0
-; GFX11-NEXT:    v_add_f32_e32 v8, 0x40c00000, v8
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v13, v9, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v11, v8, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v14, 0x400000, v8
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v13, v13, v9, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v11, v11, v8, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v8, v11, v14 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11-NEXT:    v_or_b32_e32 v11, 0x400000, v9
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v14, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_add_f32 v3, 0x40c00000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v12, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v15, 0x400000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_or_b32_e32 v16, 0x400000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v12, v12, v0, 0x7fff
-; GFX11-NEXT:    v_dual_cndmask_b32 v0, v12, v15 :: v_dual_lshlrev_b32 v15, 16, v4
-; GFX11-NEXT:    v_bfe_u32 v12, v1, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v0, v0, v8, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-NEXT:    v_cndmask_b32_e32 v9, v13, v11, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v11, v12, v1, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v2
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-NEXT:    v_or_b32_e32 v17, 0x400000, v15
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v1, v11, v12 :: v_dual_add_f32 v10, 0x40c00000, v10
-; GFX11-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v18, v4, 16, 1
-; GFX11-NEXT:    v_perm_b32 v1, v1, v9, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v13, v10, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v10
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    v_add3_u32 v11, v13, v10, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v13, v2, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v10, v11, v12, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v11, v13, v2, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v2
-; GFX11-NEXT:    v_bfe_u32 v13, v14, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v11, v12, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v11, v13, v14, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v14
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-NEXT:    v_bfe_u32 v14, v15, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v13, v3, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v11, v11, v12 :: v_dual_lshlrev_b32 v12, 16, v5
-; GFX11-NEXT:    v_add3_u32 v14, v14, v15, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT:    v_add3_u32 v15, v18, v4, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-NEXT:    v_add3_u32 v13, v13, v3, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v14, v14, v17, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-NEXT:    v_perm_b32 v2, v2, v10, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v19, v12, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v12
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v21, v5, 16, 1
-; GFX11-NEXT:    v_add3_u32 v18, v19, v12, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v6
-; GFX11-NEXT:    v_or_b32_e32 v17, 0x400000, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v4, v15, v17 :: v_dual_add_f32 v15, 0x40c00000, v19
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-NEXT:    v_add3_u32 v17, v21, v5, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v19, v15, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v12, v18, v20, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v7
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v15
-; GFX11-NEXT:    v_add3_u32 v19, v19, v15, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v22, v6, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-NEXT:    v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v23, v18, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v15, v19, v21, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v21, v22, v6, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v6
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    v_bfe_u32 v19, v7, 16, 1
-; GFX11-NEXT:    v_add3_u32 v23, v23, v18, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v24, 0x400000, v18
-; GFX11-NEXT:    v_or_b32_e32 v25, 0x400000, v7
-; GFX11-NEXT:    v_cndmask_b32_e32 v6, v21, v22, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_add3_u32 v19, v19, v7, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v6, v6, v15, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v18, v23, v24, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    v_cndmask_b32_e32 v7, v19, v25, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v7, v7, v18, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v5, v17, v20, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_perm_b32 v4, v4, v14, 0x7060302
-; GFX11-NEXT:    v_perm_b32 v5, v5, v12, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v13, v16, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v3, v3, v11, 0x7060302
-; GFX11-NEXT:  .LBB51_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v16bf16_to_v16f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v8
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB51_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff0000, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v11, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v11, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v8, v11, v12 :: v_dual_and_b32 v9, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v14, v9, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, 0x400000, v9
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_add3_u32 v14, v14, v9, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v11, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v13, v13, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v11, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v13, v15, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v9, v14, v16 :: v_dual_add_f32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v14, v10, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v11, v13, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v10
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v14, v10, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v14, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v10, v11, v13, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v14, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v9
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v11, v13, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff0000, v4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v13, v13, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_add_f32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v0, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v15, v12, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v11, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, 0x400000, v11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v14, v15, v12, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, 0x400000, v12
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v12, v14, v15, vcc_lo
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff0000, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v13, v15, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v15, v16, v11, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v4, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v18, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v14, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v13, v13, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v19, 0x400000, v14
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v3, 0xffff, v3, v12
+; GFX11-TRUE16-NEXT:    v_add3_u32 v16, v16, v14, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v13, v18, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v7
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v13, v13, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v14, v16, v19, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v16, 0x40c00000, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v19, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_add_f32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v16, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v16
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v13, v19, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v6, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v20, v16, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v18, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, 0x400000, v18
+; GFX11-TRUE16-NEXT:    v_add3_u32 v13, v13, v6, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v23, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v20, v20, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v13, v22, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    v_add3_u32 v13, v23, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v5, 0xffff, v5, v14
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v18, v20, v24, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v2, v10
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v16, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v6, 0xffff, v6, v16
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v7, v13, v22, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v18.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v11, v15, v17, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v7, 0xffff, v13, v7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v4, 0xffff, v4, v11
+; GFX11-TRUE16-NEXT:  .LBB51_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v16bf16_to_v16f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v8
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB51_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_lshlrev_b32 v8, 16, v0
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v11, v8, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, 0x400000, v8
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v13, v13, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v11, v8, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v8, v11, v14 :: v_dual_and_b32 v1, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v14, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_add_f32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v12, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, 0x400000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v12, v12, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v12, v15 :: v_dual_lshlrev_b32 v15, 16, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v12, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v8, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v13, v11, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v12, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, 0x400000, v15
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v11, v12 :: v_dual_add_f32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v18, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v9, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v10, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v10
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v13, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v2, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v11, v12, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v13, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v14, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v11, v12, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v13, v14, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v14
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v14, v15, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v3, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v11, v11, v12 :: v_dual_lshlrev_b32 v12, 16, v5
+; GFX11-FAKE16-NEXT:    v_add3_u32 v14, v14, v15, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT:    v_add3_u32 v15, v18, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_add3_u32 v13, v13, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v14, v14, v17, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v10, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v19, v12, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v18, v19, v12, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v15, v17 :: v_dual_add_f32 v15, 0x40c00000, v19
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v21, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v19, v15, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v18, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v15
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v19, v15, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v6, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v23, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v15, v19, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v22, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v19, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v23, v23, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v21, v22, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v19, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v6, v15, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v23, v24, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v19, v25, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v18, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v17, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v4, v14, 0x7060302
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v5, v12, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v13, v16, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v3, v11, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB51_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -15797,114 +18322,209 @@ define <32 x i8> @bitcast_v16f16_to_v32i8(<16 x half> %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v7, v36
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v16f16_to_v32i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
-; GFX11-NEXT:    v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v34, v4
-; GFX11-NEXT:    v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v36, v2
-; GFX11-NEXT:    v_dual_mov_b32 v39, v1 :: v_dual_mov_b32 v38, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB52_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 16, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 24, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 16, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 8, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v38
-; GFX11-NEXT:    v_lshrrev_b64 v[27:28], 24, v[32:33]
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[34:35]
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[36:37]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[38:39]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v38
-; GFX11-NEXT:  .LBB52_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB52_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_pk_add_f16 v39, 0x200, v39 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v37, 0x200, v37 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v35, 0x200, v35 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v33, 0x200, v33 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v32, 0x200, v32 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v34, 0x200, v34 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v36, 0x200, v36 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v38, 0x200, v38 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
-; GFX11-NEXT:    v_lshrrev_b64 v[27:28], 24, v[32:33]
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[34:35]
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[36:37]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[38:39]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 16, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 24, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 16, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 8, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v38
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v38
-; GFX11-NEXT:  .LBB52_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_mov_b32_e32 v0, v38
-; GFX11-NEXT:    v_mov_b32_e32 v4, v39
-; GFX11-NEXT:    v_mov_b32_e32 v8, v36
-; GFX11-NEXT:    v_mov_b32_e32 v12, v37
-; GFX11-NEXT:    v_mov_b32_e32 v16, v34
-; GFX11-NEXT:    v_mov_b32_e32 v20, v35
-; GFX11-NEXT:    v_mov_b32_e32 v24, v32
-; GFX11-NEXT:    v_mov_b32_e32 v28, v33
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v16f16_to_v32i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v27, v5 :: v_dual_mov_b32 v26, v4
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v19, v3 :: v_dual_mov_b32 v18, v2
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v8
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB52_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[32:33]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[26:27]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[18:19]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v10
+; GFX11-TRUE16-NEXT:  .LBB52_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB52_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v33, 0x200, v33 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v32, 0x200, v32 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[32:33]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[26:27]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[36:37], 24, v[18:19]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v10
+; GFX11-TRUE16-NEXT:  .LBB52_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v11.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v11.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v18.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v36.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v19.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v19.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v26.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v18.l, v26.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v35.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.l, v27.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.l, v27.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v24.l, v32.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v26.l, v32.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.l, v34.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.l, v33.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.l, v33.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v16f16_to_v32i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v34, v4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v36, v2
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v39, v1 :: v_dual_mov_b32 v38, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB52_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 16, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 16, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v38
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[27:28], 24, v[32:33]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[34:35]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[36:37]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[38:39]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v38
+; GFX11-FAKE16-NEXT:  .LBB52_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB52_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v39, 0x200, v39 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v37, 0x200, v37 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v35, 0x200, v35 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v33, 0x200, v33 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v32, 0x200, v32 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v34, 0x200, v34 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v36, 0x200, v36 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v38, 0x200, v38 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[27:28], 24, v[32:33]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[34:35]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[36:37]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[38:39]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 16, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 16, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v38
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v38
+; GFX11-FAKE16-NEXT:  .LBB52_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v38
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v39
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v36
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v12, v37
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v16, v34
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v20, v35
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v24, v32
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v28, v33
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -16460,194 +19080,374 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v32i8_to_v16f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v34, v2 :: v_dual_mov_b32 v33, v0
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_b32 v0, off, s32 offset:4
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32
-; GFX11-NEXT:    v_dual_mov_b32 v31, v6 :: v_dual_mov_b32 v32, v4
-; GFX11-NEXT:    v_lshlrev_b16 v37, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v35, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v38, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v36, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v48, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v9, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v49, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v2
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB53_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB53_4
-; GFX11-NEXT:  .LBB53_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB53_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v34
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v31
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v37
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v35
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v38
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v36
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v48
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v9
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v18
-; GFX11-NEXT:    v_perm_b32 v1, v3, v2, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v12
-; GFX11-NEXT:    v_perm_b32 v2, v5, v4, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v24
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v11
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v26
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v30
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v39
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v15
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v13
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v49
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v17
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v21
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v19
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v23
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v25
-; GFX11-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v4, v6, v5, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v5, v8, v7, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v6, v10, v9, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v7, v12, v11, 0x5040100
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr8
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB53_2
-; GFX11-NEXT:  .LBB53_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v28, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v30, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v24, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v26, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v20, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v5, v22, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v0, v23, v0
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v1, v25, v1
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_or_b32_e32 v2, v21, v2
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v19, v3
-; GFX11-NEXT:    v_add_nc_u16 v19, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v49, v4
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v17, v5
-; GFX11-NEXT:    v_add_nc_u16 v17, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v16, 3
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v12, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v18, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v14, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v2
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v0, v15, v0
-; GFX11-NEXT:    v_add_nc_u16 v2, v8, 3
-; GFX11-NEXT:    v_or_b32_e32 v1, v39, v1
-; GFX11-NEXT:    v_add_nc_u16 v14, v31, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, v10, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v13, v3
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v11, v4
-; GFX11-NEXT:    v_add_nc_u16 v4, v32, 3
-; GFX11-NEXT:    v_add_nc_u16 v11, v33, 3
-; GFX11-NEXT:    v_add_nc_u16 v13, v34, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v2, v48, v2
-; GFX11-NEXT:    v_or_b32_e32 v4, v38, v4
-; GFX11-NEXT:    v_or_b32_e32 v11, v37, v11
-; GFX11-NEXT:    v_or_b32_e32 v13, v35, v13
-; GFX11-NEXT:    v_or_b32_e32 v14, v36, v14
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v10
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v11
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v13
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v14
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v0
-; GFX11-NEXT:    v_perm_b32 v0, v11, v10, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v1, v13, v4, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v2, v9, v2, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v3, v14, v3, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v4, v15, v8, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v5, v12, v5, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v6, v17, v6, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v7, v19, v7, 0x5040100
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v32i8_to_v16f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v17.h, v17.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.h, v13.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.h, v11.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.h, v9.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.h, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.l, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.l, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.l, 8, v15.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v14.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.l, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v17.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.l, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.l, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v29.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v31.l
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v32
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB53_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB53_4
+; GFX11-TRUE16-NEXT:  .LBB53_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB53_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v16.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v20.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v26.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v30.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v8.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v10.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v1.h, v11.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v17.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v2.h, v11.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v14.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v3.h, v15.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v15.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.h, v4.h, v16.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v21.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.h, v5.h, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v19.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v6.h, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v20.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v7.h, v19.h
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB53_2
+; GFX11-TRUE16-NEXT:  .LBB53_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v28.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v30.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v24.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v26.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v20.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v20.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v19.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v19.l, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v22.l, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v18.h, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v21.l, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v18.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v16.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v13.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v14.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v17.h, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v16.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v15.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v14.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v15.l, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v13.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v10.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v12.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v9.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v12.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v9.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v17.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v11.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v10.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v11.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.h, v8.h, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, 0x300, v9.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v8.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, 0x300, v8.l
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v32i8_to_v16f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v34, v2 :: v_dual_mov_b32 v33, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v0, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v31, v6 :: v_dual_mov_b32 v32, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v37, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v35, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v38, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v36, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v48, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v49, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v29
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB53_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB53_4
+; GFX11-FAKE16-NEXT:  .LBB53_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB53_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v37
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v38
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v48
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v9
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v5, v4, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v49
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v25
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v6, v5, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v8, v7, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v10, v9, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v12, v11, 0x5040100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB53_2
+; GFX11-FAKE16-NEXT:  .LBB53_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v28, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v30, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v24, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v26, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v20, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v22, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v23, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v25, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v21, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v19, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v49, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v17, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v16, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v12, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v18, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v14, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v15, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v8, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v39, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v31, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v10, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v13, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v11, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v32, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, v33, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v34, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v48, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v38, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v37, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v35, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v36, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v13
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v14
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v11, v10, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v13, v4, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v9, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v14, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v15, v8, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v12, v5, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v17, v6, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v19, v7, 0x5040100
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -17333,241 +20133,493 @@ define <32 x i8> @bitcast_v16bf16_to_v32i8(<16 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v7, v36
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v16bf16_to_v32i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
-; GFX11-NEXT:    v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v34, v4
-; GFX11-NEXT:    v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v36, v2
-; GFX11-NEXT:    v_dual_mov_b32 v39, v1 :: v_dual_mov_b32 v38, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB54_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 16, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 24, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 16, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v35
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 8, v34
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v39
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v38
-; GFX11-NEXT:    v_lshrrev_b64 v[27:28], 24, v[32:33]
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[34:35]
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[36:37]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[38:39]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v38
-; GFX11-NEXT:  .LBB54_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB54_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff0000, v39
-; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 16, v39
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v38
-; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v38
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff0000, v34
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff0000, v36
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v34
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v6, v1, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v4, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v5, 0x400000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v1
-; GFX11-NEXT:    v_add3_u32 v6, v6, v1, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v4, v4, v0, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v9, v3, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-NEXT:    v_add3_u32 v1, v9, v3, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v9, 0x400000, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 16, v4
-; GFX11-NEXT:    v_cndmask_b32_e32 v5, v6, v8, vcc_lo
-; GFX11-NEXT:    v_bfe_u32 v7, v2, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v0, 0x400000, v2
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff0000, v37
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v37
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v7, v0, vcc_lo
-; GFX11-NEXT:    v_dual_add_f32 v7, 0x40c00000, v8 :: v_dual_add_f32 v6, 0x40c00000, v6
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v36
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-NEXT:    v_or_b32_e32 v11, 0x400000, v7
-; GFX11-NEXT:    v_bfe_u32 v8, v6, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v1, v9, vcc_lo
-; GFX11-NEXT:    v_bfe_u32 v9, v7, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v6
-; GFX11-NEXT:    v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    v_add3_u32 v9, v9, v7, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v12, v3, 16, 1
-; GFX11-NEXT:    v_perm_b32 v1, v5, v4, 0x7060302
-; GFX11-NEXT:    v_perm_b32 v0, v0, v2, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    v_add_f32_e32 v7, 0x40c00000, v13
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 16, v6
-; GFX11-NEXT:    v_cndmask_b32_e32 v11, v9, v11, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v9, v12, v3, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v13, v7, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v35
-; GFX11-NEXT:    v_perm_b32 v8, v11, v6, 0x7060302
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v9, v10, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v9, 0x40c00000, v12
-; GFX11-NEXT:    v_add3_u32 v12, v13, v7, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v13, 0x400000, v7
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff0000, v35
-; GFX11-NEXT:    v_bfe_u32 v15, v9, 16, 1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 16, v3
-; GFX11-NEXT:    v_dual_cndmask_b32 v7, v12, v13 :: v_dual_add_f32 v12, 0x40c00000, v14
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-NEXT:    v_add3_u32 v13, v15, v9, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v14, 0x400000, v9
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    v_bfe_u32 v17, v12, 16, 1
-; GFX11-NEXT:    v_perm_b32 v7, v7, v3, 0x7060302
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[0:1]
-; GFX11-NEXT:    v_dual_cndmask_b32 v13, v13, v14 :: v_dual_add_f32 v14, 0x40c00000, v16
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v16, v17, v12, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v33
-; GFX11-NEXT:    v_bfe_u32 v15, v10, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    v_bfe_u32 v19, v14, 16, 1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 16, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v9, v15, v10, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v15, 0x400000, v10
-; GFX11-NEXT:    v_add3_u32 v10, v19, v14, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v20, v9, v15 :: v_dual_add_f32 v9, 0x40c00000, v17
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff0000, v33
-; GFX11-NEXT:    v_or_b32_e32 v18, 0x400000, v12
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-NEXT:    v_or_b32_e32 v15, 0x400000, v14
-; GFX11-NEXT:    v_cndmask_b32_e32 v12, v16, v18, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-NEXT:    v_bfe_u32 v16, v9, 16, 1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v32
-; GFX11-NEXT:    v_dual_cndmask_b32 v14, v10, v15 :: v_dual_add_f32 v15, 0x40c00000, v17
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v17, 0x40c00000, v18
-; GFX11-NEXT:    v_add3_u32 v16, v16, v9, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v18, 0x400000, v9
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    v_bfe_u32 v19, v15, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v21, v17, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 16, v12
-; GFX11-NEXT:    v_cndmask_b32_e32 v18, v16, v18, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v16, v19, v15, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v19, 0x400000, v15
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-NEXT:    v_add3_u32 v21, v21, v17, 0x7fff
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 16, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v19, v16, v19, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff0000, v32
-; GFX11-NEXT:    v_perm_b32 v16, v19, v18, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v17, v21, v22, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 16, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 16, v17
-; GFX11-NEXT:    v_bfe_u32 v9, v10, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v23, 0x400000, v10
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v16
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add3_u32 v9, v9, v10, 0x7fff
-; GFX11-NEXT:    v_perm_b32 v10, v20, v13, 0x7060302
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v8
-; GFX11-NEXT:    v_cndmask_b32_e32 v15, v9, v23, vcc_lo
-; GFX11-NEXT:    v_perm_b32 v9, v14, v12, 0x7060302
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v11
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 24, v10
-; GFX11-NEXT:    v_perm_b32 v15, v15, v17, 0x7060302
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 8, v9
-; GFX11-NEXT:    v_lshrrev_b64 v[27:28], 24, v[15:16]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 16, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
-; GFX11-NEXT:  .LBB54_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_mov_b32_e32 v0, v38
-; GFX11-NEXT:    v_mov_b32_e32 v4, v39
-; GFX11-NEXT:    v_mov_b32_e32 v8, v36
-; GFX11-NEXT:    v_mov_b32_e32 v12, v37
-; GFX11-NEXT:    v_mov_b32_e32 v16, v34
-; GFX11-NEXT:    v_mov_b32_e32 v20, v35
-; GFX11-NEXT:    v_mov_b32_e32 v24, v32
-; GFX11-NEXT:    v_mov_b32_e32 v28, v33
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v16bf16_to_v32i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v27, v7 :: v_dual_mov_b32 v26, v6
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v19, v5 :: v_dual_mov_b32 v18, v4
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v11, v3 :: v_dual_mov_b32 v10, v2
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB54_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[32:33], 24, v[26:27]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[33:34], 24, v[18:19]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[2:3]
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v3.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.h, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v11.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.h, v11.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.h, v19.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.h, v19.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v24.h, v26.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.h, v27.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.h, v27.h
+; GFX11-TRUE16-NEXT:  .LBB54_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB54_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v11
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v10
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v8, 0x40c00000, v4 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_add3_u32 v12, v4, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v7, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v11, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v0, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v11, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v3, v6, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v0, v0, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v4.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v12, v9, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v12, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v3, 0xffff, v1, v6
+; GFX11-TRUE16-NEXT:    v_add3_u32 v12, v12, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, 0x400000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v12, v12, v14, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v0, v0, v1 :: v_dual_add_f32 v5, 0x40c00000, v15
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v12.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v2, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v10
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v19
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v2, v2, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v14, v9, v16, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v0.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v7, v11, v13, vcc_lo
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v19
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v11, 0xffff, v1, v14
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v8
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v15, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v2, v8, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v8, v15, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v18
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v10, 0x40c00000, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v8, v8, v13 :: v_dual_add_f32 v1, 0x40c00000, v15
+; GFX11-TRUE16-NEXT:    v_add3_u32 v13, v16, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v18
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v10, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v22, v13, v15, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v16, v17, v10, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, 0x400000, v10
+; GFX11-TRUE16-NEXT:    v_add3_u32 v10, v19, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v27
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v18, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v20, v16, v17, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v17.l, v20.h
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v1, v10, v13 :: v_dual_add_f32 v10, 0x40c00000, v15
+; GFX11-TRUE16-NEXT:    v_add3_u32 v15, v16, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v26
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v27
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v23, 0x40c00000, v16 :: v_dual_cndmask_b32 v16, v15, v18
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v10, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v5, v13, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v15, v19, v10, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v23, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, 0x400000, v13
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT:    v_add3_u32 v5, v5, v13, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff0000, v26
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v19, v23, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v26, 0x400000, v23
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v28, v5, v24, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v21
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v25, v18, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v24, v19, v26, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v18
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v28.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v5, v25, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v19, 0xffff, v17, v22
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v30, v15, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v16.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.l, v8.h
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v19
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v27, 0xffff, v10, v30
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v5, v13, vcc_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v24.h
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v18, 0xffff, v15, v1
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v10, 0xffff, v21, v2
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v9, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v27
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v26, 0xffff, v13, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[32:33], 24, v[26:27]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[33:34], 24, v[18:19]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[34:35], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[35:36], 24, v[2:3]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v26
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-TRUE16-NEXT:  .LBB54_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v35.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v34.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v14.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v16.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v18.l, v18.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v33.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.l, v20.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.l, v22.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v24.l, v24.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v26.l, v26.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.l, v32.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.l, v28.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.l, v30.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v16bf16_to_v32i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v34, v4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v36, v2
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v39, v1 :: v_dual_mov_b32 v38, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB54_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 16, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 16, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v35
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v34
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v39
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v38
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[27:28], 24, v[32:33]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[34:35]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[36:37]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[38:39]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v38
+; GFX11-FAKE16-NEXT:  .LBB54_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB54_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v39
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v38
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v38
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff0000, v34
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff0000, v36
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v34
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v4, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v4, v4, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v3, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    v_add3_u32 v1, v9, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 16, v4
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v6, v8, vcc_lo
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v7, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v37
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v37
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v7, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v7, v0, vcc_lo
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v7, 0x40c00000, v8 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v36
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v6, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v9, vcc_lo
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v12, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v5, v4, 0x7060302
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v2, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v7, 0x40c00000, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 16, v6
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v9, v11, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v12, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v35
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v11, v6, 0x7060302
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v9, v10, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v9, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_add3_u32 v12, v13, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v35
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v15, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 16, v3
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v7, v12, v13 :: v_dual_add_f32 v12, 0x40c00000, v14
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT:    v_add3_u32 v13, v15, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v17, v12, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v3, 0x7060302
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[0:1]
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v13, v13, v14 :: v_dual_add_f32 v14, 0x40c00000, v16
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v17, v12, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v33
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v15, v10, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v19, v14, 16, 1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v15, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, 0x400000, v10
+; GFX11-FAKE16-NEXT:    v_add3_u32 v10, v19, v14, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v20, v9, v15 :: v_dual_add_f32 v9, 0x40c00000, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff0000, v33
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, 0x400000, v12
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, 0x400000, v14
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v16, v18, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v32
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v14, v10, v15 :: v_dual_add_f32 v15, 0x40c00000, v17
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v17, 0x40c00000, v18
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v19, v15, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v17, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 16, v12
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v16, v18, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v19, v15, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, 0x400000, v15
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v19, v16, v19, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v32
+; GFX11-FAKE16-NEXT:    v_perm_b32 v16, v19, v18, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v21, v22, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 16, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 16, v17
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v10, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, 0x400000, v10
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v16
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v20, v13, 0x7060302
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v8
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v15, v9, v23, vcc_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v14, v12, 0x7060302
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v10
+; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v15, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[27:28], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-FAKE16-NEXT:  .LBB54_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v38
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v39
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v36
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v12, v37
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v16, v34
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v20, v35
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v24, v32
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v28, v33
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -18154,194 +21206,374 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v32i8_to_v16bf16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v34, v2 :: v_dual_mov_b32 v33, v0
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_b32 v0, off, s32 offset:4
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32
-; GFX11-NEXT:    v_dual_mov_b32 v31, v6 :: v_dual_mov_b32 v32, v4
-; GFX11-NEXT:    v_lshlrev_b16 v37, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v35, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v38, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v36, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v48, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v9, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v49, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v2
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB55_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB55_4
-; GFX11-NEXT:  .LBB55_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB55_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v34
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v31
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v37
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v35
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v38
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v36
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v48
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v9
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v18
-; GFX11-NEXT:    v_perm_b32 v1, v3, v2, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v12
-; GFX11-NEXT:    v_perm_b32 v2, v5, v4, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v24
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v11
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v26
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v30
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v39
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v15
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v13
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v49
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v17
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v21
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v19
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v23
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v25
-; GFX11-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v4, v6, v5, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v5, v8, v7, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v6, v10, v9, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v7, v12, v11, 0x5040100
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr8
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB55_2
-; GFX11-NEXT:  .LBB55_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v28, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v30, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v24, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v26, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v20, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v5, v22, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v0, v23, v0
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v1, v25, v1
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_or_b32_e32 v2, v21, v2
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v19, v3
-; GFX11-NEXT:    v_add_nc_u16 v19, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v49, v4
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v17, v5
-; GFX11-NEXT:    v_add_nc_u16 v17, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v16, 3
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v12, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v18, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v14, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v2
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v0, v15, v0
-; GFX11-NEXT:    v_add_nc_u16 v2, v8, 3
-; GFX11-NEXT:    v_or_b32_e32 v1, v39, v1
-; GFX11-NEXT:    v_add_nc_u16 v14, v31, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, v10, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v13, v3
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v11, v4
-; GFX11-NEXT:    v_add_nc_u16 v4, v32, 3
-; GFX11-NEXT:    v_add_nc_u16 v11, v33, 3
-; GFX11-NEXT:    v_add_nc_u16 v13, v34, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v2, v48, v2
-; GFX11-NEXT:    v_or_b32_e32 v4, v38, v4
-; GFX11-NEXT:    v_or_b32_e32 v11, v37, v11
-; GFX11-NEXT:    v_or_b32_e32 v13, v35, v13
-; GFX11-NEXT:    v_or_b32_e32 v14, v36, v14
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v10
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v11
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v13
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v14
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v0
-; GFX11-NEXT:    v_perm_b32 v0, v11, v10, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v1, v13, v4, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v2, v9, v2, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v3, v14, v3, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v4, v15, v8, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v5, v12, v5, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v6, v17, v6, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v7, v19, v7, 0x5040100
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v32i8_to_v16bf16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v32, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v17.h, v17.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.h, v13.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.h, v11.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.h, v9.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.h, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.l, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.l, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.l, 8, v15.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v14.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.l, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v17.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.l, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.l, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v29.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v31.l
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v32
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB55_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB55_4
+; GFX11-TRUE16-NEXT:  .LBB55_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB55_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v16.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v20.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v26.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v30.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v8.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v10.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v1.h, v11.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v17.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v2.h, v11.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v14.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v3.h, v15.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v15.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.h, v4.h, v16.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v21.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.h, v5.h, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v19.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v6.h, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v20.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v7.h, v19.h
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB55_2
+; GFX11-TRUE16-NEXT:  .LBB55_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v28.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v30.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v24.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v26.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v20.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v20.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v19.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v19.l, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v22.l, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v18.h, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v21.l, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v18.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v16.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v13.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v14.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v17.h, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v16.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v15.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v14.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v15.l, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v13.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v10.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v12.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v9.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v12.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v9.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v17.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v11.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v10.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v11.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.h, v8.h, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, 0x300, v9.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v8.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, 0x300, v8.l
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v32i8_to_v16bf16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v34, v2 :: v_dual_mov_b32 v33, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v0, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v31, v6 :: v_dual_mov_b32 v32, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v37, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v35, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v38, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v36, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v48, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v49, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v29
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB55_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB55_4
+; GFX11-FAKE16-NEXT:  .LBB55_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB55_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v37
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v38
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v48
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v9
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v5, v4, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v49
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v25
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v6, v5, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v8, v7, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v10, v9, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v12, v11, 0x5040100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB55_2
+; GFX11-FAKE16-NEXT:  .LBB55_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v28, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v30, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v24, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v26, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v20, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v22, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v23, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v25, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v21, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v19, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v49, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v17, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v16, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v12, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v18, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v14, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v15, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v8, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v39, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v31, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v10, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v13, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v11, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v32, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, v33, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v34, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v48, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v38, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v37, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v35, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v36, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v13
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v14
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v11, v10, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v13, v4, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v9, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v14, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v15, v8, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v12, v5, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v17, v6, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v19, v7, 0x5040100
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
index 467e7740d24cf..6e6e62c4b05ad 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
@@ -3,7 +3,8 @@
 ; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define <10 x float> @bitcast_v10i32_to_v10f32(<10 x i32> %a, i32 %b) {
 ; GCN-LABEL: bitcast_v10i32_to_v10f32:
@@ -219,384 +220,6 @@ end:
   ret <10 x i32> %phi
 }
 
-define <20 x i16> @bitcast_v10i32_to_v20i16(<10 x i32> %a, i32 %b) {
-; GCN-LABEL: bitcast_v10i32_to_v20i16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v18, v9
-; GCN-NEXT:    v_mov_b32_e32 v16, v8
-; GCN-NEXT:    v_mov_b32_e32 v14, v7
-; GCN-NEXT:    v_mov_b32_e32 v12, v6
-; GCN-NEXT:    v_mov_b32_e32 v20, v5
-; GCN-NEXT:    v_mov_b32_e32 v8, v4
-; GCN-NEXT:    v_mov_b32_e32 v6, v3
-; GCN-NEXT:    v_mov_b32_e32 v4, v2
-; GCN-NEXT:    v_mov_b32_e32 v2, v1
-; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; GCN-NEXT:    ; implicit-def: $vgpr1
-; GCN-NEXT:    ; implicit-def: $vgpr3
-; GCN-NEXT:    ; implicit-def: $vgpr5
-; GCN-NEXT:    ; implicit-def: $vgpr7
-; GCN-NEXT:    ; implicit-def: $vgpr9
-; GCN-NEXT:    ; implicit-def: $vgpr11
-; GCN-NEXT:    ; implicit-def: $vgpr13
-; GCN-NEXT:    ; implicit-def: $vgpr15
-; GCN-NEXT:    ; implicit-def: $vgpr17
-; GCN-NEXT:    ; implicit-def: $vgpr19
-; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB2_2
-; GCN-NEXT:  ; %bb.1: ; %cmp.false
-; GCN-NEXT:    v_alignbit_b32 v17, v18, v16, 16
-; GCN-NEXT:    v_alignbit_b32 v13, v14, v12, 16
-; GCN-NEXT:    v_alignbit_b32 v9, v20, v8, 16
-; GCN-NEXT:    v_alignbit_b32 v5, v6, v4, 16
-; GCN-NEXT:    v_alignbit_b32 v1, v2, v0, 16
-; GCN-NEXT:    v_lshrrev_b32_e32 v19, 16, v18
-; GCN-NEXT:    v_lshrrev_b32_e32 v15, 16, v14
-; GCN-NEXT:    v_lshrrev_b32_e32 v11, 16, v20
-; GCN-NEXT:    v_lshrrev_b32_e32 v7, 16, v6
-; GCN-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
-; GCN-NEXT:  .LBB2_2: ; %Flow
-; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB2_4
-; GCN-NEXT:  ; %bb.3: ; %cmp.true
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, 3, v2
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, 3, v0
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, 3, v6
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, 3, v4
-; GCN-NEXT:    v_add_i32_e32 v20, vcc, 3, v20
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, 3, v8
-; GCN-NEXT:    v_add_i32_e32 v14, vcc, 3, v14
-; GCN-NEXT:    v_add_i32_e32 v12, vcc, 3, v12
-; GCN-NEXT:    v_add_i32_e32 v18, vcc, 3, v18
-; GCN-NEXT:    v_add_i32_e32 v16, vcc, 3, v16
-; GCN-NEXT:    v_alignbit_b32 v17, v18, v16, 16
-; GCN-NEXT:    v_alignbit_b32 v13, v14, v12, 16
-; GCN-NEXT:    v_alignbit_b32 v9, v20, v8, 16
-; GCN-NEXT:    v_alignbit_b32 v5, v6, v4, 16
-; GCN-NEXT:    v_alignbit_b32 v1, v2, v0, 16
-; GCN-NEXT:    v_lshrrev_b32_e32 v19, 16, v18
-; GCN-NEXT:    v_lshrrev_b32_e32 v15, 16, v14
-; GCN-NEXT:    v_lshrrev_b32_e32 v11, 16, v20
-; GCN-NEXT:    v_lshrrev_b32_e32 v7, 16, v6
-; GCN-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
-; GCN-NEXT:  .LBB2_4: ; %end
-; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GCN-NEXT:    v_mov_b32_e32 v10, v20
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; VI-LABEL: bitcast_v10i32_to_v20i16:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB2_2
-; VI-NEXT:  ; %bb.1: ; %cmp.true
-; VI-NEXT:    v_add_u32_e32 v9, vcc, 3, v9
-; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v8
-; VI-NEXT:    v_add_u32_e32 v7, vcc, 3, v7
-; VI-NEXT:    v_add_u32_e32 v6, vcc, 3, v6
-; VI-NEXT:    v_add_u32_e32 v5, vcc, 3, v5
-; VI-NEXT:    v_add_u32_e32 v4, vcc, 3, v4
-; VI-NEXT:    v_add_u32_e32 v3, vcc, 3, v3
-; VI-NEXT:    v_add_u32_e32 v2, vcc, 3, v2
-; VI-NEXT:    v_add_u32_e32 v1, vcc, 3, v1
-; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0
-; VI-NEXT:  .LBB2_2: ; %end
-; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
-; VI-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: bitcast_v10i32_to_v20i16:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB2_2
-; GFX9-NEXT:  ; %bb.1: ; %cmp.true
-; GFX9-NEXT:    v_add_u32_e32 v9, 3, v9
-; GFX9-NEXT:    v_add_u32_e32 v8, 3, v8
-; GFX9-NEXT:    v_add_u32_e32 v7, 3, v7
-; GFX9-NEXT:    v_add_u32_e32 v6, 3, v6
-; GFX9-NEXT:    v_add_u32_e32 v5, 3, v5
-; GFX9-NEXT:    v_add_u32_e32 v4, 3, v4
-; GFX9-NEXT:    v_add_u32_e32 v3, 3, v3
-; GFX9-NEXT:    v_add_u32_e32 v2, 3, v2
-; GFX9-NEXT:    v_add_u32_e32 v1, 3, v1
-; GFX9-NEXT:    v_add_u32_e32 v0, 3, v0
-; GFX9-NEXT:  .LBB2_2: ; %end
-; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: bitcast_v10i32_to_v20i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB2_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u32_e32 v9, 3, v9
-; GFX11-NEXT:    v_add_nc_u32_e32 v8, 3, v8
-; GFX11-NEXT:    v_add_nc_u32_e32 v7, 3, v7
-; GFX11-NEXT:    v_add_nc_u32_e32 v6, 3, v6
-; GFX11-NEXT:    v_add_nc_u32_e32 v5, 3, v5
-; GFX11-NEXT:    v_add_nc_u32_e32 v4, 3, v4
-; GFX11-NEXT:    v_add_nc_u32_e32 v3, 3, v3
-; GFX11-NEXT:    v_add_nc_u32_e32 v2, 3, v2
-; GFX11-NEXT:    v_add_nc_u32_e32 v1, 3, v1
-; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT:  .LBB2_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %cmp = icmp eq i32 %b, 0
-  br i1 %cmp, label %cmp.true, label %cmp.false
-
-cmp.true:
-  %a1 = add <10 x i32> %a, splat (i32 3)
-  %a2 = bitcast <10 x i32> %a1 to <20 x i16>
-  br label %end
-
-cmp.false:
-  %a3 = bitcast <10 x i32> %a to <20 x i16>
-  br label %end
-
-end:
-  %phi = phi <20 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
-  ret <20 x i16> %phi
-}
-
-define <10 x i32> @bitcast_v20i16_to_v10i32(<20 x i16> %a, i32 %b) {
-; GCN-LABEL: bitcast_v20i16_to_v10i32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v25, v8
-; GCN-NEXT:    v_mov_b32_e32 v24, v6
-; GCN-NEXT:    v_mov_b32_e32 v23, v4
-; GCN-NEXT:    v_mov_b32_e32 v22, v2
-; GCN-NEXT:    v_mov_b32_e32 v21, v0
-; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v20
-; GCN-NEXT:    v_lshlrev_b32_e32 v20, 16, v1
-; GCN-NEXT:    v_lshlrev_b32_e32 v26, 16, v3
-; GCN-NEXT:    v_lshlrev_b32_e32 v27, 16, v5
-; GCN-NEXT:    v_lshlrev_b32_e32 v28, 16, v7
-; GCN-NEXT:    v_lshlrev_b32_e32 v29, 16, v9
-; GCN-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GCN-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GCN-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GCN-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GCN-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GCN-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
-; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execnz .LBB3_3
-; GCN-NEXT:  ; %bb.1: ; %Flow
-; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execnz .LBB3_4
-; GCN-NEXT:  .LBB3_2: ; %end
-; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-; GCN-NEXT:  .LBB3_3: ; %cmp.false
-; GCN-NEXT:    v_and_b32_e32 v0, 0xffff, v21
-; GCN-NEXT:    v_and_b32_e32 v1, 0xffff, v22
-; GCN-NEXT:    v_and_b32_e32 v2, 0xffff, v23
-; GCN-NEXT:    v_and_b32_e32 v3, 0xffff, v24
-; GCN-NEXT:    v_and_b32_e32 v4, 0xffff, v25
-; GCN-NEXT:    v_and_b32_e32 v5, 0xffff, v10
-; GCN-NEXT:    v_and_b32_e32 v6, 0xffff, v12
-; GCN-NEXT:    v_and_b32_e32 v7, 0xffff, v14
-; GCN-NEXT:    v_and_b32_e32 v8, 0xffff, v16
-; GCN-NEXT:    v_and_b32_e32 v9, 0xffff, v18
-; GCN-NEXT:    v_or_b32_e32 v0, v0, v20
-; GCN-NEXT:    v_or_b32_e32 v1, v1, v26
-; GCN-NEXT:    v_or_b32_e32 v2, v2, v27
-; GCN-NEXT:    v_or_b32_e32 v3, v3, v28
-; GCN-NEXT:    v_or_b32_e32 v4, v4, v29
-; GCN-NEXT:    v_or_b32_e32 v5, v5, v11
-; GCN-NEXT:    v_or_b32_e32 v6, v6, v13
-; GCN-NEXT:    v_or_b32_e32 v7, v7, v15
-; GCN-NEXT:    v_or_b32_e32 v8, v8, v17
-; GCN-NEXT:    v_or_b32_e32 v9, v9, v19
-; GCN-NEXT:    ; implicit-def: $vgpr21
-; GCN-NEXT:    ; implicit-def: $vgpr22
-; GCN-NEXT:    ; implicit-def: $vgpr23
-; GCN-NEXT:    ; implicit-def: $vgpr24
-; GCN-NEXT:    ; implicit-def: $vgpr25
-; GCN-NEXT:    ; implicit-def: $vgpr10
-; GCN-NEXT:    ; implicit-def: $vgpr12
-; GCN-NEXT:    ; implicit-def: $vgpr14
-; GCN-NEXT:    ; implicit-def: $vgpr16
-; GCN-NEXT:    ; implicit-def: $vgpr18
-; GCN-NEXT:    ; implicit-def: $vgpr20
-; GCN-NEXT:    ; implicit-def: $vgpr26
-; GCN-NEXT:    ; implicit-def: $vgpr27
-; GCN-NEXT:    ; implicit-def: $vgpr28
-; GCN-NEXT:    ; implicit-def: $vgpr29
-; GCN-NEXT:    ; implicit-def: $vgpr11
-; GCN-NEXT:    ; implicit-def: $vgpr13
-; GCN-NEXT:    ; implicit-def: $vgpr15
-; GCN-NEXT:    ; implicit-def: $vgpr17
-; GCN-NEXT:    ; implicit-def: $vgpr19
-; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB3_2
-; GCN-NEXT:  .LBB3_4: ; %cmp.true
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, 3, v21
-; GCN-NEXT:    s_mov_b32 s6, 0x30000
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, 3, v22
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, 3, v23
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, 3, v24
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, 3, v25
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, 3, v10
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, 3, v12
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, 3, v14
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, 3, v16
-; GCN-NEXT:    v_add_i32_e32 v9, vcc, 3, v18
-; GCN-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GCN-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GCN-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GCN-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GCN-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GCN-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GCN-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GCN-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GCN-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GCN-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GCN-NEXT:    v_or_b32_e32 v0, v20, v0
-; GCN-NEXT:    v_or_b32_e32 v1, v26, v1
-; GCN-NEXT:    v_or_b32_e32 v2, v27, v2
-; GCN-NEXT:    v_or_b32_e32 v3, v28, v3
-; GCN-NEXT:    v_or_b32_e32 v4, v29, v4
-; GCN-NEXT:    v_or_b32_e32 v5, v11, v5
-; GCN-NEXT:    v_or_b32_e32 v6, v13, v6
-; GCN-NEXT:    v_or_b32_e32 v7, v15, v7
-; GCN-NEXT:    v_or_b32_e32 v8, v17, v8
-; GCN-NEXT:    v_or_b32_e32 v9, v19, v9
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, 0x30000, v0
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, s6, v1
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, s6, v2
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, s6, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, s6, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, s6, v5
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, s6, v6
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, 0x30000, v7
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, 0x30000, v8
-; GCN-NEXT:    v_add_i32_e32 v9, vcc, 0x30000, v9
-; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; VI-LABEL: bitcast_v20i16_to_v10i32:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB3_2
-; VI-NEXT:  ; %bb.1: ; %cmp.true
-; VI-NEXT:    v_mov_b32_e32 v11, 3
-; VI-NEXT:    v_add_u16_e32 v10, 3, v9
-; VI-NEXT:    v_add_u16_sdwa v9, v9, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v9, v10, v9
-; VI-NEXT:    v_add_u16_e32 v10, 3, v8
-; VI-NEXT:    v_add_u16_sdwa v8, v8, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v8, v10, v8
-; VI-NEXT:    v_add_u16_e32 v10, 3, v7
-; VI-NEXT:    v_add_u16_sdwa v7, v7, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v7, v10, v7
-; VI-NEXT:    v_add_u16_e32 v10, 3, v6
-; VI-NEXT:    v_add_u16_sdwa v6, v6, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v6, v10, v6
-; VI-NEXT:    v_add_u16_e32 v10, 3, v5
-; VI-NEXT:    v_add_u16_sdwa v5, v5, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v5, v10, v5
-; VI-NEXT:    v_add_u16_e32 v10, 3, v4
-; VI-NEXT:    v_add_u16_sdwa v4, v4, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v4, v10, v4
-; VI-NEXT:    v_add_u16_e32 v10, 3, v3
-; VI-NEXT:    v_add_u16_sdwa v3, v3, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v3, v10, v3
-; VI-NEXT:    v_add_u16_e32 v10, 3, v2
-; VI-NEXT:    v_add_u16_sdwa v2, v2, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v2, v10, v2
-; VI-NEXT:    v_add_u16_e32 v10, 3, v1
-; VI-NEXT:    v_add_u16_sdwa v1, v1, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v1, v10, v1
-; VI-NEXT:    v_add_u16_e32 v10, 3, v0
-; VI-NEXT:    v_add_u16_sdwa v0, v0, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v0, v10, v0
-; VI-NEXT:  .LBB3_2: ; %end
-; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
-; VI-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: bitcast_v20i16_to_v10i32:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB3_2
-; GFX9-NEXT:  ; %bb.1: ; %cmp.true
-; GFX9-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:  .LBB3_2: ; %end
-; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: bitcast_v20i16_to_v10i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB3_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:  .LBB3_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %cmp = icmp eq i32 %b, 0
-  br i1 %cmp, label %cmp.true, label %cmp.false
-
-cmp.true:
-  %a1 = add <20 x i16> %a, splat (i16 3)
-  %a2 = bitcast <20 x i16> %a1 to <10 x i32>
-  br label %end
-
-cmp.false:
-  %a3 = bitcast <20 x i16> %a to <10 x i32>
-  br label %end
-
-end:
-  %phi = phi <10 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
-  ret <10 x i32> %phi
-}
-
 define <20 x half> @bitcast_v10i32_to_v20f16(<10 x i32> %a, i32 %b) {
 ; GCN-LABEL: bitcast_v10i32_to_v20f16:
 ; GCN:       ; %bb.0:
@@ -634,14 +257,14 @@ define <20 x half> @bitcast_v10i32_to_v20f16(<10 x i32> %a, i32 %b) {
 ; GCN-NEXT:    ; implicit-def: $vgpr19
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execnz .LBB4_3
+; GCN-NEXT:    s_cbranch_execnz .LBB2_3
 ; GCN-NEXT:  ; %bb.1: ; %Flow
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execnz .LBB4_4
-; GCN-NEXT:  .LBB4_2: ; %end
+; GCN-NEXT:    s_cbranch_execnz .LBB2_4
+; GCN-NEXT:  .LBB2_2: ; %end
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
-; GCN-NEXT:  .LBB4_3: ; %cmp.false
+; GCN-NEXT:  .LBB2_3: ; %cmp.false
 ; GCN-NEXT:    v_lshrrev_b32_e32 v0, 16, v29
 ; GCN-NEXT:    v_lshrrev_b32_e32 v1, 16, v28
 ; GCN-NEXT:    v_lshrrev_b32_e32 v3, 16, v27
@@ -683,8 +306,8 @@ define <20 x half> @bitcast_v10i32_to_v20f16(<10 x i32> %a, i32 %b) {
 ; GCN-NEXT:    ; implicit-def: $vgpr28
 ; GCN-NEXT:    ; implicit-def: $vgpr29
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB4_2
-; GCN-NEXT:  .LBB4_4: ; %cmp.true
+; GCN-NEXT:    s_cbranch_execz .LBB2_2
+; GCN-NEXT:  .LBB2_4: ; %cmp.true
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, 3, v20
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, 3, v21
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, 3, v22
@@ -735,7 +358,7 @@ define <20 x half> @bitcast_v10i32_to_v20f16(<10 x i32> %a, i32 %b) {
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB4_2
+; VI-NEXT:    s_cbranch_execz .LBB2_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.true
 ; VI-NEXT:    v_add_u32_e32 v9, vcc, 3, v9
 ; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v8
@@ -747,7 +370,7 @@ define <20 x half> @bitcast_v10i32_to_v20f16(<10 x i32> %a, i32 %b) {
 ; VI-NEXT:    v_add_u32_e32 v2, vcc, 3, v2
 ; VI-NEXT:    v_add_u32_e32 v1, vcc, 3, v1
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0
-; VI-NEXT:  .LBB4_2: ; %end
+; VI-NEXT:  .LBB2_2: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -758,7 +381,7 @@ define <20 x half> @bitcast_v10i32_to_v20f16(<10 x i32> %a, i32 %b) {
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB4_2
+; GFX9-NEXT:    s_cbranch_execz .LBB2_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX9-NEXT:    v_add_u32_e32 v9, 3, v9
 ; GFX9-NEXT:    v_add_u32_e32 v8, 3, v8
@@ -770,7 +393,7 @@ define <20 x half> @bitcast_v10i32_to_v20f16(<10 x i32> %a, i32 %b) {
 ; GFX9-NEXT:    v_add_u32_e32 v2, 3, v2
 ; GFX9-NEXT:    v_add_u32_e32 v1, 3, v1
 ; GFX9-NEXT:    v_add_u32_e32 v0, 3, v0
-; GFX9-NEXT:  .LBB4_2: ; %end
+; GFX9-NEXT:  .LBB2_2: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -782,7 +405,7 @@ define <20 x half> @bitcast_v10i32_to_v20f16(<10 x i32> %a, i32 %b) {
 ; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB4_2
+; GFX11-NEXT:    s_cbranch_execz .LBB2_2
 ; GFX11-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX11-NEXT:    v_add_nc_u32_e32 v9, 3, v9
 ; GFX11-NEXT:    v_add_nc_u32_e32 v8, 3, v8
@@ -794,7 +417,7 @@ define <20 x half> @bitcast_v10i32_to_v20f16(<10 x i32> %a, i32 %b) {
 ; GFX11-NEXT:    v_add_nc_u32_e32 v2, 3, v2
 ; GFX11-NEXT:    v_add_nc_u32_e32 v1, 3, v1
 ; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT:  .LBB4_2: ; %end
+; GFX11-NEXT:  .LBB2_2: ; %end
 ; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
@@ -842,14 +465,14 @@ define <10 x i32> @bitcast_v20f16_to_v10i32(<20 x half> %a, i32 %b) {
 ; GCN-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execnz .LBB5_3
+; GCN-NEXT:    s_cbranch_execnz .LBB3_3
 ; GCN-NEXT:  ; %bb.1: ; %Flow
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execnz .LBB5_4
-; GCN-NEXT:  .LBB5_2: ; %end
+; GCN-NEXT:    s_cbranch_execnz .LBB3_4
+; GCN-NEXT:  .LBB3_2: ; %end
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
-; GCN-NEXT:  .LBB5_3: ; %cmp.false
+; GCN-NEXT:  .LBB3_3: ; %cmp.false
 ; GCN-NEXT:    v_lshlrev_b32_e32 v0, 16, v33
 ; GCN-NEXT:    v_lshlrev_b32_e32 v1, 16, v32
 ; GCN-NEXT:    v_lshlrev_b32_e32 v2, 16, v31
@@ -891,8 +514,8 @@ define <10 x i32> @bitcast_v20f16_to_v10i32(<20 x half> %a, i32 %b) {
 ; GCN-NEXT:    ; implicit-def: $vgpr13
 ; GCN-NEXT:    ; implicit-def: $vgpr10
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB5_2
-; GCN-NEXT:  .LBB5_4: ; %cmp.true
+; GCN-NEXT:    s_cbranch_execz .LBB3_2
+; GCN-NEXT:  .LBB3_4: ; %cmp.true
 ; GCN-NEXT:    v_cvt_f32_f16_e32 v0, v33
 ; GCN-NEXT:    v_cvt_f32_f16_e32 v1, v29
 ; GCN-NEXT:    v_cvt_f32_f16_e32 v2, v32
@@ -983,7 +606,7 @@ define <10 x i32> @bitcast_v20f16_to_v10i32(<20 x half> %a, i32 %b) {
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB5_2
+; VI-NEXT:    s_cbranch_execz .LBB3_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.true
 ; VI-NEXT:    v_mov_b32_e32 v10, 0x200
 ; VI-NEXT:    v_add_f16_sdwa v11, v9, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
@@ -1016,7 +639,7 @@ define <10 x i32> @bitcast_v20f16_to_v10i32(<20 x half> %a, i32 %b) {
 ; VI-NEXT:    v_add_f16_e32 v0, 0x200, v0
 ; VI-NEXT:    v_or_b32_e32 v1, v1, v11
 ; VI-NEXT:    v_or_b32_e32 v0, v0, v10
-; VI-NEXT:  .LBB5_2: ; %end
+; VI-NEXT:  .LBB3_2: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -1027,7 +650,7 @@ define <10 x i32> @bitcast_v20f16_to_v10i32(<20 x half> %a, i32 %b) {
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB5_2
+; GFX9-NEXT:    s_cbranch_execz .LBB3_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX9-NEXT:    s_movk_i32 s6, 0x200
 ; GFX9-NEXT:    v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]
@@ -1040,7 +663,7 @@ define <10 x i32> @bitcast_v20f16_to_v10i32(<20 x half> %a, i32 %b) {
 ; GFX9-NEXT:    v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
 ; GFX9-NEXT:    v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
 ; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
-; GFX9-NEXT:  .LBB5_2: ; %end
+; GFX9-NEXT:  .LBB3_2: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -1052,7 +675,7 @@ define <10 x i32> @bitcast_v20f16_to_v10i32(<20 x half> %a, i32 %b) {
 ; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB5_2
+; GFX11-NEXT:    s_cbranch_execz .LBB3_2
 ; GFX11-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX11-NEXT:    v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
 ; GFX11-NEXT:    v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
@@ -1064,7 +687,7 @@ define <10 x i32> @bitcast_v20f16_to_v10i32(<20 x half> %a, i32 %b) {
 ; GFX11-NEXT:    v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
 ; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
 ; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
-; GFX11-NEXT:  .LBB5_2: ; %end
+; GFX11-NEXT:  .LBB3_2: ; %end
 ; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
@@ -1121,7 +744,7 @@ define <40 x i8> @bitcast_v10i32_to_v40i8(<10 x i32> %a, i32 %b) {
 ; GCN-NEXT:    ; implicit-def: $vgpr16
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB6_2
+; GCN-NEXT:    s_cbranch_execz .LBB4_2
 ; GCN-NEXT:  ; %bb.1: ; %cmp.false
 ; GCN-NEXT:    v_alignbit_b32 v11, v10, v9, 24
 ; GCN-NEXT:    v_alignbit_b32 v12, v10, v9, 16
@@ -1153,9 +776,9 @@ define <40 x i8> @bitcast_v10i32_to_v40i8(<10 x i32> %a, i32 %b) {
 ; GCN-NEXT:    v_lshrrev_b32_e32 v38, 24, v2
 ; GCN-NEXT:    v_lshrrev_b32_e32 v39, 16, v2
 ; GCN-NEXT:    v_lshrrev_b32_e32 v48, 8, v2
-; GCN-NEXT:  .LBB6_2: ; %Flow
+; GCN-NEXT:  .LBB4_2: ; %Flow
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB6_4
+; GCN-NEXT:    s_cbranch_execz .LBB4_4
 ; GCN-NEXT:  ; %bb.3: ; %cmp.true
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, 3, v2
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, 3, v1
@@ -1197,7 +820,7 @@ define <40 x i8> @bitcast_v10i32_to_v40i8(<10 x i32> %a, i32 %b) {
 ; GCN-NEXT:    v_lshrrev_b32_e32 v38, 24, v2
 ; GCN-NEXT:    v_lshrrev_b32_e32 v39, 16, v2
 ; GCN-NEXT:    v_lshrrev_b32_e32 v48, 8, v2
-; GCN-NEXT:  .LBB6_4: ; %end
+; GCN-NEXT:  .LBB4_4: ; %end
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GCN-NEXT:    v_and_b32_e32 v49, 0xff, v1
 ; GCN-NEXT:    v_lshlrev_b32_e32 v35, 8, v35
@@ -1347,7 +970,7 @@ define <40 x i8> @bitcast_v10i32_to_v40i8(<10 x i32> %a, i32 %b) {
 ; VI-NEXT:    ; implicit-def: $vgpr11
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB6_2
+; VI-NEXT:    s_cbranch_execz .LBB4_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.false
 ; VI-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
 ; VI-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
@@ -1379,9 +1002,9 @@ define <40 x i8> @bitcast_v10i32_to_v40i8(<10 x i32> %a, i32 %b) {
 ; VI-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
 ; VI-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
 ; VI-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; VI-NEXT:  .LBB6_2: ; %Flow
+; VI-NEXT:  .LBB4_2: ; %Flow
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB6_4
+; VI-NEXT:    s_cbranch_execz .LBB4_4
 ; VI-NEXT:  ; %bb.3: ; %cmp.true
 ; VI-NEXT:    v_add_u32_e32 v10, vcc, 3, v10
 ; VI-NEXT:    v_add_u32_e32 v9, vcc, 3, v9
@@ -1423,7 +1046,7 @@ define <40 x i8> @bitcast_v10i32_to_v40i8(<10 x i32> %a, i32 %b) {
 ; VI-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
 ; VI-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
 ; VI-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; VI-NEXT:  .LBB6_4: ; %end
+; VI-NEXT:  .LBB4_4: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; VI-NEXT:    v_lshlrev_b16_e32 v15, 8, v15
 ; VI-NEXT:    v_lshlrev_b16_e32 v16, 8, v16
@@ -1533,7 +1156,7 @@ define <40 x i8> @bitcast_v10i32_to_v40i8(<10 x i32> %a, i32 %b) {
 ; GFX9-NEXT:    ; implicit-def: $vgpr11
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB6_2
+; GFX9-NEXT:    s_cbranch_execz .LBB4_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.false
 ; GFX9-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
 ; GFX9-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
@@ -1565,9 +1188,9 @@ define <40 x i8> @bitcast_v10i32_to_v40i8(<10 x i32> %a, i32 %b) {
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; GFX9-NEXT:  .LBB6_2: ; %Flow
+; GFX9-NEXT:  .LBB4_2: ; %Flow
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB6_4
+; GFX9-NEXT:    s_cbranch_execz .LBB4_4
 ; GFX9-NEXT:  ; %bb.3: ; %cmp.true
 ; GFX9-NEXT:    v_add_u32_e32 v10, 3, v10
 ; GFX9-NEXT:    v_add_u32_e32 v9, 3, v9
@@ -1609,7 +1232,7 @@ define <40 x i8> @bitcast_v10i32_to_v40i8(<10 x i32> %a, i32 %b) {
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; GFX9-NEXT:  .LBB6_4: ; %end
+; GFX9-NEXT:  .LBB4_4: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v15, 8, v15
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v16, 8, v16
@@ -1674,217 +1297,401 @@ define <40 x i8> @bitcast_v10i32_to_v40i8(<10 x i32> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v10i32_to_v40i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB6_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; GFX11-NEXT:  .LBB6_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB6_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u32_e32 v10, 3, v10
-; GFX11-NEXT:    v_add_nc_u32_e32 v9, 3, v9
-; GFX11-NEXT:    v_add_nc_u32_e32 v8, 3, v8
-; GFX11-NEXT:    v_add_nc_u32_e32 v7, 3, v7
-; GFX11-NEXT:    v_add_nc_u32_e32 v6, 3, v6
-; GFX11-NEXT:    v_add_nc_u32_e32 v5, 3, v5
-; GFX11-NEXT:    v_add_nc_u32_e32 v4, 3, v4
-; GFX11-NEXT:    v_add_nc_u32_e32 v3, 3, v3
-; GFX11-NEXT:    v_add_nc_u32_e32 v2, 3, v2
-; GFX11-NEXT:    v_add_nc_u32_e32 v1, 3, v1
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; GFX11-NEXT:  .LBB6_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v16
-; GFX11-NEXT:    v_and_b32_e32 v48, 0xff, v48
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v15
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_lshlrev_b16 v36, 8, v36
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xff, v35
-; GFX11-NEXT:    v_lshlrev_b16 v14, 8, v14
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_lshlrev_b16 v31, 8, v31
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v30
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v13
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v39
-; GFX11-NEXT:    v_and_b32_e32 v38, 0xff, v38
-; GFX11-NEXT:    v_lshlrev_b16 v37, 8, v37
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v16
-; GFX11-NEXT:    v_or_b32_e32 v15, v48, v15
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v36
-; GFX11-NEXT:    v_or_b32_e32 v14, v35, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v31
-; GFX11-NEXT:    v_or_b32_e32 v13, v30, v13
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v39
-; GFX11-NEXT:    v_or_b32_e32 v16, v38, v37
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v15
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v13
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v29
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v28
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v27
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v16
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v26
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_lshlrev_b16 v34, 8, v34
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xff, v33
-; GFX11-NEXT:    v_lshlrev_b16 v32, 8, v32
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v25
-; GFX11-NEXT:    v_lshlrev_b16 v12, 8, v12
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v24
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v13
-; GFX11-NEXT:    v_or_b32_e32 v13, v14, v15
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v23
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v22
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v16
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v21
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v20
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v11
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v19
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v18
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v17
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v34
-; GFX11-NEXT:    v_or_b32_e32 v32, v33, v32
-; GFX11-NEXT:    v_or_b32_e32 v12, v25, v12
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v24
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v16
-; GFX11-NEXT:    v_or_b32_e32 v11, v20, v11
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v19
-; GFX11-NEXT:    v_or_b32_e32 v15, v18, v17
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v30, 16, v32
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v30
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v13
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v12
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v14
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v11
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v15
-; GFX11-NEXT:    s_clause 0x2
-; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off
-; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
-; GFX11-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v10i32_to_v40i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB4_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v18, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v20, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v22, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB4_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB4_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v10, 3, v10
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v9, 3, v9
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, 3, v8
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v7, 3, v7
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, 3, v6
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v5, 3, v5
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v4, 3, v4
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 3, v3
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 3, v2
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v1, 3, v1
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v18, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v20, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v22, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB4_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v16.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.l, 8, v28.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v11.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v30.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v29.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v1.h, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v15.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v29, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v13.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v26.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.l, v2.h, v14.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v30, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v5.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v24.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v15, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.l, 8, v22.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.l, 8, v12.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v13.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v13.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v14, v25
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v6.h, v12.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v20.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v29, v16
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v7.h, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v18.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v10.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v30, v28
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v26, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v15, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v16, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v13, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v17, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v19, v10
+; GFX11-TRUE16-NEXT:    s_clause 0x2
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-TRUE16-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v10i32_to_v40i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB4_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB4_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB4_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v10, 3, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v9, 3, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, 3, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v7, 3, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, 3, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v5, 3, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 3, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, 3, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, 3, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v1, 3, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB4_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v48, 0xff, v48
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v36, 8, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v14, 8, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v31, 8, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v38, 0xff, v38
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v37, 8, v37
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v48, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v35, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v31
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v30, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v38, v37
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v34, 8, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v32, 8, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v12, 8, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v14, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v32, v33, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v25, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v20, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v18, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v15
+; GFX11-FAKE16-NEXT:    s_clause 0x2
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-FAKE16-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -1950,7 +1757,7 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) {
 ; GCN-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB7_2
+; GCN-NEXT:    s_cbranch_execz .LBB5_2
 ; GCN-NEXT:  ; %bb.1: ; %cmp.false
 ; GCN-NEXT:    v_and_b32_e32 v0, 0xff, v31
 ; GCN-NEXT:    v_and_b32_e32 v1, 0xff, v32
@@ -2062,9 +1869,9 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) {
 ; GCN-NEXT:    ; implicit-def: $vgpr23
 ; GCN-NEXT:    ; implicit-def: $vgpr53
 ; GCN-NEXT:    ; implicit-def: $vgpr25
-; GCN-NEXT:  .LBB7_2: ; %Flow
+; GCN-NEXT:  .LBB5_2: ; %Flow
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB7_4
+; GCN-NEXT:    s_cbranch_execz .LBB5_4
 ; GCN-NEXT:  ; %bb.3: ; %cmp.true
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, 3, v31
 ; GCN-NEXT:    s_movk_i32 s6, 0x300
@@ -2178,7 +1985,7 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) {
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, s7, v7
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, 0x3000000, v8
 ; GCN-NEXT:    v_add_i32_e32 v9, vcc, 0x3000000, v9
-; GCN-NEXT:  .LBB7_4: ; %end
+; GCN-NEXT:  .LBB5_4: ; %end
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GCN-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
@@ -2238,7 +2045,7 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) {
 ; VI-NEXT:    v_lshlrev_b16_e32 v13, 8, v44
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB7_2
+; VI-NEXT:    s_cbranch_execz .LBB5_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.false
 ; VI-NEXT:    v_or_b32_sdwa v0, v31, v43 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_sdwa v1, v32, v42 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
@@ -2311,9 +2118,9 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) {
 ; VI-NEXT:    ; implicit-def: $vgpr15
 ; VI-NEXT:    ; implicit-def: $vgpr13
 ; VI-NEXT:    ; implicit-def: $vgpr11
-; VI-NEXT:  .LBB7_2: ; %Flow
+; VI-NEXT:  .LBB5_2: ; %Flow
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB7_4
+; VI-NEXT:    s_cbranch_execz .LBB5_4
 ; VI-NEXT:  ; %bb.3: ; %cmp.true
 ; VI-NEXT:    v_add_u16_e32 v0, 3, v31
 ; VI-NEXT:    v_add_u16_e32 v1, 3, v32
@@ -2387,7 +2194,7 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) {
 ; VI-NEXT:    v_add_u16_e32 v10, 0x300, v10
 ; VI-NEXT:    v_add_u16_sdwa v9, v11, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_e32 v9, v10, v9
-; VI-NEXT:  .LBB7_4: ; %end
+; VI-NEXT:  .LBB5_4: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; VI-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
 ; VI-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
@@ -2450,7 +2257,7 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v13, 8, v44
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB7_2
+; GFX9-NEXT:    s_cbranch_execz .LBB5_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.false
 ; GFX9-NEXT:    v_or_b32_sdwa v0, v31, v43 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; GFX9-NEXT:    v_or_b32_sdwa v1, v32, v42 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
@@ -2523,9 +2330,9 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    ; implicit-def: $vgpr15
 ; GFX9-NEXT:    ; implicit-def: $vgpr13
 ; GFX9-NEXT:    ; implicit-def: $vgpr11
-; GFX9-NEXT:  .LBB7_2: ; %Flow
+; GFX9-NEXT:  .LBB5_2: ; %Flow
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB7_4
+; GFX9-NEXT:    s_cbranch_execz .LBB5_4
 ; GFX9-NEXT:  ; %bb.3: ; %cmp.true
 ; GFX9-NEXT:    v_add_u16_e32 v0, 3, v31
 ; GFX9-NEXT:    v_add_u16_e32 v1, 3, v32
@@ -2599,7 +2406,7 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    v_add_u16_e32 v9, 0x300, v9
 ; GFX9-NEXT:    v_add_u16_sdwa v10, v10, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 ; GFX9-NEXT:    v_or_b32_e32 v9, v9, v10
-; GFX9-NEXT:  .LBB7_4: ; %end
+; GFX9-NEXT:  .LBB5_4: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
 ; GFX9-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
@@ -2609,290 +2416,584 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v40i8_to_v10i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v35, v8 :: v_dual_mov_b32 v34, v6
-; GFX11-NEXT:    v_dual_mov_b32 v33, v4 :: v_dual_mov_b32 v32, v2
-; GFX11-NEXT:    v_mov_b32_e32 v31, v0
-; GFX11-NEXT:    s_clause 0x9
-; GFX11-NEXT:    scratch_load_b32 v0, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32
-; GFX11-NEXT:    scratch_load_u16 v4, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_u16 v6, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_u16 v8, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_u16 v66, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_u16 v36, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_u16 v37, off, s32 offset:20
-; GFX11-NEXT:    scratch_load_u16 v38, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_u16 v39, off, s32 offset:4
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v64, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v48, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v49, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v50, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v51, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v52, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v29, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(9)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(8)
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(7)
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v4
-; GFX11-NEXT:    s_waitcnt vmcnt(6)
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v6
-; GFX11-NEXT:    s_waitcnt vmcnt(5)
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v8
-; GFX11-NEXT:    s_waitcnt vmcnt(4)
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v66
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB7_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB7_4
-; GFX11-NEXT:  .LBB7_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB7_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v31
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v34
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v35
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v10
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v18
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v53
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v54
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v55
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v64
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v65
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v48
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v49
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v50
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v51
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v52
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v7
-; GFX11-NEXT:    v_or_b32_e32 v4, v8, v9
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v24
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v26
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v30
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v39
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v38
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v37
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v36
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v21
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v23
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v25
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v27
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v29
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v11, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v12, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v13, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v14, v18, v19
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v8, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v9, v13, v14
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB7_2
-; GFX11-NEXT:  .LBB7_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v31, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v32, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v33, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v34, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v35, 3
-; GFX11-NEXT:    v_add_nc_u16 v5, v10, 3
-; GFX11-NEXT:    v_add_nc_u16 v6, v12, 3
-; GFX11-NEXT:    v_add_nc_u16 v7, v14, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v16, 3
-; GFX11-NEXT:    v_add_nc_u16 v9, v18, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_or_b32_e32 v0, v53, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v54, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v55, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v64, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v65, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v48, v5
-; GFX11-NEXT:    v_or_b32_e32 v6, v49, v6
-; GFX11-NEXT:    v_or_b32_e32 v7, v50, v7
-; GFX11-NEXT:    v_or_b32_e32 v8, v51, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v52, v9
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v7
-; GFX11-NEXT:    v_or_b32_e32 v4, v8, v9
-; GFX11-NEXT:    v_add_nc_u16 v5, v20, 3
-; GFX11-NEXT:    v_add_nc_u16 v6, v22, 3
-; GFX11-NEXT:    v_add_nc_u16 v7, v24, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v26, 3
-; GFX11-NEXT:    v_add_nc_u16 v9, v28, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, v30, 3
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_nc_u16 v12, v39, 3
-; GFX11-NEXT:    v_add_nc_u16 v14, v38, 3
-; GFX11-NEXT:    v_add_nc_u16 v16, v37, 3
-; GFX11-NEXT:    v_add_nc_u16 v18, v36, 3
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v18
-; GFX11-NEXT:    v_or_b32_e32 v5, v21, v5
-; GFX11-NEXT:    v_or_b32_e32 v6, v23, v6
-; GFX11-NEXT:    v_or_b32_e32 v7, v25, v7
-; GFX11-NEXT:    v_or_b32_e32 v8, v27, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v29, v9
-; GFX11-NEXT:    v_or_b32_e32 v10, v11, v10
-; GFX11-NEXT:    v_or_b32_e32 v11, v13, v12
-; GFX11-NEXT:    v_or_b32_e32 v12, v15, v14
-; GFX11-NEXT:    v_or_b32_e32 v13, v17, v16
-; GFX11-NEXT:    v_or_b32_e32 v14, v19, v18
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v10
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v11
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v12
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v13
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v14
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v8, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v9, v13, v14
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v40i8_to_v10i32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x9
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v36, off, s32 offset:36
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v33, off, s32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v33, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v34, off, s32 offset:16
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v34, off, s32 offset:24
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v35, off, s32 offset:32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32 offset:28
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v31, off, s32 offset:20
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v32, off, s32 offset:12
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v32, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.h, v25.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.h, v23.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.h, v21.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.h, v19.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v17.h, v17.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v17.l, v15.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v14.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.h, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.h, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v25.l, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v25.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v26.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.h, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v22.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.l, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v24.h, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.l, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v17.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v30.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v29.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.l, 8, v28.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v27.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.l, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v29.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(8)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.l, 8, v33.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v33.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(6)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.l, 8, v34.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(5)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v34.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(4)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.l, 8, v35.l
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v36
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB5_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB5_4
+; GFX11-TRUE16-NEXT:  .LBB5_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB5_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v26.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v25.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v25.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v20.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v21.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v23.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v0.h, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v1.h, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v24.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v19.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v16.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v15.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v17.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v0.h, v16.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v1.h, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v18.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v5, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v7, v8
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v20.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v26.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v13.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v14.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v9, v15
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v4, v17
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v5.h, v13.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v6.h, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v30.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v32.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v32.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v31.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v31.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v3, v16
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v10.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v5.h, v10.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v11.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v6.h, v11.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v12.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v13, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v15, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v17, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v8, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v9, v12
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB5_2
+; GFX11-TRUE16-NEXT:  .LBB5_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v26.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v25.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v25.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v21.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v20.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v21.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v23.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v22.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v23.h, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v24.h, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v19.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v15.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v19.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v16.l, 3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v15.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v17.l, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v18.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v16.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v17.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v5, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v7, v8
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, v20.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, v24.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v28.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v18.h, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, v22.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, v26.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v5.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v12.h, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v13.h, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v14.h, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v2
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.h, v13.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v14.l, v6.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v5.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v6.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v9, v15
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v4, v17
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v5.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, v30.l, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, v32.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, v32.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, v31.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v31.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v5.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v10.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.h, v10.h, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v11.l, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v11.h, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v12.l, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v3, v16
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v9
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v5.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v5.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v6.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v6.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v13, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v15, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v17, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v8, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v9, v12
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v10i32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v35, v8 :: v_dual_mov_b32 v34, v6
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v33, v4 :: v_dual_mov_b32 v32, v2
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v31, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x9
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v0, off, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v4, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v6, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v8, off, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v66, off, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v36, off, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v37, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v38, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v39, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v53, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v64, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v48, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v49, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v50, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v51, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v52, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v29, 8, v29
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(9)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(8)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(7)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(6)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v6
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(5)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v8
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(4)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB5_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB5_4
+; GFX11-FAKE16-NEXT:  .LBB5_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB5_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v64
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v48
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v49
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v50
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v51
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v52
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v8, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v30
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v38
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v37
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v18, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v13, v14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB5_2
+; GFX11-FAKE16-NEXT:  .LBB5_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v31, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v32, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v33, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v34, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v35, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v10, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v12, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v14, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v16, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v18, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v53, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v54, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v55, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v64, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v65, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v48, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v49, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v50, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v51, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v52, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v8, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v20, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v22, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v24, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v26, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v28, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v30, 3
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v39, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v38, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, v37, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, v36, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v21, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v23, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v25, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v27, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v29, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v11, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v13, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v15, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v17, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v19, v18
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v13
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v13, v14
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -2918,7 +3019,7 @@ define <5 x double> @bitcast_v10i32_to_v5f64(<10 x i32> %a, i32 %b) {
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB8_2
+; GCN-NEXT:    s_cbranch_execz .LBB6_2
 ; GCN-NEXT:  ; %bb.1: ; %cmp.true
 ; GCN-NEXT:    v_add_i32_e32 v9, vcc, 3, v9
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, 3, v8
@@ -2930,7 +3031,7 @@ define <5 x double> @bitcast_v10i32_to_v5f64(<10 x i32> %a, i32 %b) {
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, 3, v2
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, 3, v1
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, 3, v0
-; GCN-NEXT:  .LBB8_2: ; %end
+; GCN-NEXT:  .LBB6_2: ; %end
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -2941,7 +3042,7 @@ define <5 x double> @bitcast_v10i32_to_v5f64(<10 x i32> %a, i32 %b) {
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB8_2
+; VI-NEXT:    s_cbranch_execz .LBB6_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.true
 ; VI-NEXT:    v_add_u32_e32 v9, vcc, 3, v9
 ; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v8
@@ -2953,7 +3054,7 @@ define <5 x double> @bitcast_v10i32_to_v5f64(<10 x i32> %a, i32 %b) {
 ; VI-NEXT:    v_add_u32_e32 v2, vcc, 3, v2
 ; VI-NEXT:    v_add_u32_e32 v1, vcc, 3, v1
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0
-; VI-NEXT:  .LBB8_2: ; %end
+; VI-NEXT:  .LBB6_2: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -2964,7 +3065,7 @@ define <5 x double> @bitcast_v10i32_to_v5f64(<10 x i32> %a, i32 %b) {
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB8_2
+; GFX9-NEXT:    s_cbranch_execz .LBB6_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX9-NEXT:    v_add_u32_e32 v9, 3, v9
 ; GFX9-NEXT:    v_add_u32_e32 v8, 3, v8
@@ -2976,7 +3077,7 @@ define <5 x double> @bitcast_v10i32_to_v5f64(<10 x i32> %a, i32 %b) {
 ; GFX9-NEXT:    v_add_u32_e32 v2, 3, v2
 ; GFX9-NEXT:    v_add_u32_e32 v1, 3, v1
 ; GFX9-NEXT:    v_add_u32_e32 v0, 3, v0
-; GFX9-NEXT:  .LBB8_2: ; %end
+; GFX9-NEXT:  .LBB6_2: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -2988,7 +3089,7 @@ define <5 x double> @bitcast_v10i32_to_v5f64(<10 x i32> %a, i32 %b) {
 ; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB8_2
+; GFX11-NEXT:    s_cbranch_execz .LBB6_2
 ; GFX11-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX11-NEXT:    v_add_nc_u32_e32 v9, 3, v9
 ; GFX11-NEXT:    v_add_nc_u32_e32 v8, 3, v8
@@ -3000,7 +3101,7 @@ define <5 x double> @bitcast_v10i32_to_v5f64(<10 x i32> %a, i32 %b) {
 ; GFX11-NEXT:    v_add_nc_u32_e32 v2, 3, v2
 ; GFX11-NEXT:    v_add_nc_u32_e32 v1, 3, v1
 ; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT:  .LBB8_2: ; %end
+; GFX11-NEXT:  .LBB6_2: ; %end
 ; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
@@ -3028,14 +3129,14 @@ define <10 x i32> @bitcast_v5f64_to_v10i32(<5 x double> %a, i32 %b) {
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB9_2
+; GCN-NEXT:    s_cbranch_execz .LBB7_2
 ; GCN-NEXT:  ; %bb.1: ; %cmp.true
 ; GCN-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
 ; GCN-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
 ; GCN-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
 ; GCN-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
 ; GCN-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
-; GCN-NEXT:  .LBB9_2: ; %end
+; GCN-NEXT:  .LBB7_2: ; %end
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -3046,14 +3147,14 @@ define <10 x i32> @bitcast_v5f64_to_v10i32(<5 x double> %a, i32 %b) {
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB9_2
+; VI-NEXT:    s_cbranch_execz .LBB7_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.true
 ; VI-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
 ; VI-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
 ; VI-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
 ; VI-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
 ; VI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
-; VI-NEXT:  .LBB9_2: ; %end
+; VI-NEXT:  .LBB7_2: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -3064,14 +3165,14 @@ define <10 x i32> @bitcast_v5f64_to_v10i32(<5 x double> %a, i32 %b) {
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB9_2
+; GFX9-NEXT:    s_cbranch_execz .LBB7_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX9-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
 ; GFX9-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
 ; GFX9-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
 ; GFX9-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
 ; GFX9-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
-; GFX9-NEXT:  .LBB9_2: ; %end
+; GFX9-NEXT:  .LBB7_2: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -3083,14 +3184,14 @@ define <10 x i32> @bitcast_v5f64_to_v10i32(<5 x double> %a, i32 %b) {
 ; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB9_2
+; GFX11-NEXT:    s_cbranch_execz .LBB7_2
 ; GFX11-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX11-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
 ; GFX11-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
 ; GFX11-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
 ; GFX11-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
 ; GFX11-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
-; GFX11-NEXT:  .LBB9_2: ; %end
+; GFX11-NEXT:  .LBB7_2: ; %end
 ; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
@@ -3118,7 +3219,7 @@ define <5 x i64> @bitcast_v10i32_to_v5i64(<10 x i32> %a, i32 %b) {
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB10_2
+; GCN-NEXT:    s_cbranch_execz .LBB8_2
 ; GCN-NEXT:  ; %bb.1: ; %cmp.true
 ; GCN-NEXT:    v_add_i32_e32 v9, vcc, 3, v9
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, 3, v8
@@ -3130,7 +3231,7 @@ define <5 x i64> @bitcast_v10i32_to_v5i64(<10 x i32> %a, i32 %b) {
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, 3, v2
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, 3, v1
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, 3, v0
-; GCN-NEXT:  .LBB10_2: ; %end
+; GCN-NEXT:  .LBB8_2: ; %end
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -3141,7 +3242,7 @@ define <5 x i64> @bitcast_v10i32_to_v5i64(<10 x i32> %a, i32 %b) {
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB10_2
+; VI-NEXT:    s_cbranch_execz .LBB8_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.true
 ; VI-NEXT:    v_add_u32_e32 v9, vcc, 3, v9
 ; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v8
@@ -3153,7 +3254,7 @@ define <5 x i64> @bitcast_v10i32_to_v5i64(<10 x i32> %a, i32 %b) {
 ; VI-NEXT:    v_add_u32_e32 v2, vcc, 3, v2
 ; VI-NEXT:    v_add_u32_e32 v1, vcc, 3, v1
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0
-; VI-NEXT:  .LBB10_2: ; %end
+; VI-NEXT:  .LBB8_2: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -3164,7 +3265,7 @@ define <5 x i64> @bitcast_v10i32_to_v5i64(<10 x i32> %a, i32 %b) {
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB10_2
+; GFX9-NEXT:    s_cbranch_execz .LBB8_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX9-NEXT:    v_add_u32_e32 v9, 3, v9
 ; GFX9-NEXT:    v_add_u32_e32 v8, 3, v8
@@ -3176,7 +3277,7 @@ define <5 x i64> @bitcast_v10i32_to_v5i64(<10 x i32> %a, i32 %b) {
 ; GFX9-NEXT:    v_add_u32_e32 v2, 3, v2
 ; GFX9-NEXT:    v_add_u32_e32 v1, 3, v1
 ; GFX9-NEXT:    v_add_u32_e32 v0, 3, v0
-; GFX9-NEXT:  .LBB10_2: ; %end
+; GFX9-NEXT:  .LBB8_2: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -3188,7 +3289,7 @@ define <5 x i64> @bitcast_v10i32_to_v5i64(<10 x i32> %a, i32 %b) {
 ; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB10_2
+; GFX11-NEXT:    s_cbranch_execz .LBB8_2
 ; GFX11-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX11-NEXT:    v_add_nc_u32_e32 v9, 3, v9
 ; GFX11-NEXT:    v_add_nc_u32_e32 v8, 3, v8
@@ -3200,7 +3301,7 @@ define <5 x i64> @bitcast_v10i32_to_v5i64(<10 x i32> %a, i32 %b) {
 ; GFX11-NEXT:    v_add_nc_u32_e32 v2, 3, v2
 ; GFX11-NEXT:    v_add_nc_u32_e32 v1, 3, v1
 ; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT:  .LBB10_2: ; %end
+; GFX11-NEXT:  .LBB8_2: ; %end
 ; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
@@ -3228,7 +3329,7 @@ define <10 x i32> @bitcast_v5i64_to_v10i32(<5 x i64> %a, i32 %b) {
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB11_2
+; GCN-NEXT:    s_cbranch_execz .LBB9_2
 ; GCN-NEXT:  ; %bb.1: ; %cmp.true
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, 3, v8
 ; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
@@ -3240,7 +3341,7 @@ define <10 x i32> @bitcast_v5i64_to_v10i32(<5 x i64> %a, i32 %b) {
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, 3, v0
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT:  .LBB11_2: ; %end
+; GCN-NEXT:  .LBB9_2: ; %end
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -3251,7 +3352,7 @@ define <10 x i32> @bitcast_v5i64_to_v10i32(<5 x i64> %a, i32 %b) {
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB11_2
+; VI-NEXT:    s_cbranch_execz .LBB9_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.true
 ; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v8
 ; VI-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
@@ -3263,7 +3364,7 @@ define <10 x i32> @bitcast_v5i64_to_v10i32(<5 x i64> %a, i32 %b) {
 ; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0
 ; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT:  .LBB11_2: ; %end
+; VI-NEXT:  .LBB9_2: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -3274,7 +3375,7 @@ define <10 x i32> @bitcast_v5i64_to_v10i32(<5 x i64> %a, i32 %b) {
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB11_2
+; GFX9-NEXT:    s_cbranch_execz .LBB9_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, 3, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
@@ -3286,7 +3387,7 @@ define <10 x i32> @bitcast_v5i64_to_v10i32(<5 x i64> %a, i32 %b) {
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 3, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GFX9-NEXT:  .LBB11_2: ; %end
+; GFX9-NEXT:  .LBB9_2: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -3298,7 +3399,7 @@ define <10 x i32> @bitcast_v5i64_to_v10i32(<5 x i64> %a, i32 %b) {
 ; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB11_2
+; GFX11-NEXT:    s_cbranch_execz .LBB9_2
 ; GFX11-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX11-NEXT:    v_add_co_u32 v8, vcc_lo, v8, 3
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
@@ -3313,7 +3414,7 @@ define <10 x i32> @bitcast_v5i64_to_v10i32(<5 x i64> %a, i32 %b) {
 ; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, v0, 3
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-NEXT:  .LBB11_2: ; %end
+; GFX11-NEXT:  .LBB9_2: ; %end
 ; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
@@ -3333,81 +3434,145 @@ end:
   ret <10 x i32> %phi
 }
 
-define <20 x i16> @bitcast_v10f32_to_v20i16(<10 x float> %a, i32 %b) {
-; GCN-LABEL: bitcast_v10f32_to_v20i16:
+define <20 x half> @bitcast_v10f32_to_v20f16(<10 x float> %a, i32 %b) {
+; GCN-LABEL: bitcast_v10f32_to_v20f16:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v18, v9
-; GCN-NEXT:    v_mov_b32_e32 v16, v8
-; GCN-NEXT:    v_mov_b32_e32 v14, v7
-; GCN-NEXT:    v_mov_b32_e32 v12, v6
-; GCN-NEXT:    v_mov_b32_e32 v20, v5
-; GCN-NEXT:    v_mov_b32_e32 v8, v4
-; GCN-NEXT:    v_mov_b32_e32 v6, v3
-; GCN-NEXT:    v_mov_b32_e32 v4, v2
-; GCN-NEXT:    v_mov_b32_e32 v2, v1
+; GCN-NEXT:    v_mov_b32_e32 v29, v9
+; GCN-NEXT:    v_mov_b32_e32 v28, v8
+; GCN-NEXT:    v_mov_b32_e32 v27, v7
+; GCN-NEXT:    v_mov_b32_e32 v26, v6
+; GCN-NEXT:    v_mov_b32_e32 v25, v5
+; GCN-NEXT:    v_mov_b32_e32 v24, v4
+; GCN-NEXT:    v_mov_b32_e32 v23, v3
+; GCN-NEXT:    v_mov_b32_e32 v22, v2
+; GCN-NEXT:    v_mov_b32_e32 v21, v1
+; GCN-NEXT:    v_mov_b32_e32 v20, v0
 ; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
+; GCN-NEXT:    ; implicit-def: $vgpr0
 ; GCN-NEXT:    ; implicit-def: $vgpr1
+; GCN-NEXT:    ; implicit-def: $vgpr2
 ; GCN-NEXT:    ; implicit-def: $vgpr3
+; GCN-NEXT:    ; implicit-def: $vgpr4
 ; GCN-NEXT:    ; implicit-def: $vgpr5
+; GCN-NEXT:    ; implicit-def: $vgpr6
 ; GCN-NEXT:    ; implicit-def: $vgpr7
+; GCN-NEXT:    ; implicit-def: $vgpr8
 ; GCN-NEXT:    ; implicit-def: $vgpr9
+; GCN-NEXT:    ; implicit-def: $vgpr10
 ; GCN-NEXT:    ; implicit-def: $vgpr11
+; GCN-NEXT:    ; implicit-def: $vgpr12
 ; GCN-NEXT:    ; implicit-def: $vgpr13
+; GCN-NEXT:    ; implicit-def: $vgpr14
 ; GCN-NEXT:    ; implicit-def: $vgpr15
+; GCN-NEXT:    ; implicit-def: $vgpr16
 ; GCN-NEXT:    ; implicit-def: $vgpr17
+; GCN-NEXT:    ; implicit-def: $vgpr18
 ; GCN-NEXT:    ; implicit-def: $vgpr19
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB12_2
-; GCN-NEXT:  ; %bb.1: ; %cmp.false
-; GCN-NEXT:    v_alignbit_b32 v17, v18, v16, 16
-; GCN-NEXT:    v_alignbit_b32 v13, v14, v12, 16
-; GCN-NEXT:    v_alignbit_b32 v9, v20, v8, 16
-; GCN-NEXT:    v_alignbit_b32 v5, v6, v4, 16
-; GCN-NEXT:    v_alignbit_b32 v1, v2, v0, 16
-; GCN-NEXT:    v_lshrrev_b32_e32 v19, 16, v18
-; GCN-NEXT:    v_lshrrev_b32_e32 v15, 16, v14
-; GCN-NEXT:    v_lshrrev_b32_e32 v11, 16, v20
-; GCN-NEXT:    v_lshrrev_b32_e32 v7, 16, v6
-; GCN-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
-; GCN-NEXT:  .LBB12_2: ; %Flow
+; GCN-NEXT:    s_cbranch_execnz .LBB10_3
+; GCN-NEXT:  ; %bb.1: ; %Flow
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB12_4
-; GCN-NEXT:  ; %bb.3: ; %cmp.true
-; GCN-NEXT:    v_add_f32_e32 v2, 1.0, v2
-; GCN-NEXT:    v_add_f32_e32 v0, 1.0, v0
-; GCN-NEXT:    v_add_f32_e32 v6, 1.0, v6
-; GCN-NEXT:    v_add_f32_e32 v4, 1.0, v4
-; GCN-NEXT:    v_add_f32_e32 v20, 1.0, v20
-; GCN-NEXT:    v_add_f32_e32 v8, 1.0, v8
-; GCN-NEXT:    v_add_f32_e32 v14, 1.0, v14
-; GCN-NEXT:    v_add_f32_e32 v12, 1.0, v12
-; GCN-NEXT:    v_add_f32_e32 v18, 1.0, v18
-; GCN-NEXT:    v_add_f32_e32 v16, 1.0, v16
-; GCN-NEXT:    v_alignbit_b32 v17, v18, v16, 16
-; GCN-NEXT:    v_alignbit_b32 v13, v14, v12, 16
-; GCN-NEXT:    v_alignbit_b32 v9, v20, v8, 16
-; GCN-NEXT:    v_alignbit_b32 v5, v6, v4, 16
-; GCN-NEXT:    v_alignbit_b32 v1, v2, v0, 16
-; GCN-NEXT:    v_lshrrev_b32_e32 v19, 16, v18
-; GCN-NEXT:    v_lshrrev_b32_e32 v15, 16, v14
-; GCN-NEXT:    v_lshrrev_b32_e32 v11, 16, v20
-; GCN-NEXT:    v_lshrrev_b32_e32 v7, 16, v6
-; GCN-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
-; GCN-NEXT:  .LBB12_4: ; %end
+; GCN-NEXT:    s_cbranch_execnz .LBB10_4
+; GCN-NEXT:  .LBB10_2: ; %end
+; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
+; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GCN-NEXT:  .LBB10_3: ; %cmp.false
+; GCN-NEXT:    v_lshrrev_b32_e32 v0, 16, v29
+; GCN-NEXT:    v_lshrrev_b32_e32 v1, 16, v28
+; GCN-NEXT:    v_lshrrev_b32_e32 v3, 16, v27
+; GCN-NEXT:    v_lshrrev_b32_e32 v5, 16, v26
+; GCN-NEXT:    v_lshrrev_b32_e32 v7, 16, v25
+; GCN-NEXT:    v_lshrrev_b32_e32 v9, 16, v24
+; GCN-NEXT:    v_lshrrev_b32_e32 v30, 16, v23
+; GCN-NEXT:    v_lshrrev_b32_e32 v31, 16, v22
+; GCN-NEXT:    v_lshrrev_b32_e32 v32, 16, v21
+; GCN-NEXT:    v_lshrrev_b32_e32 v33, 16, v20
+; GCN-NEXT:    v_cvt_f32_f16_e32 v18, v29
+; GCN-NEXT:    v_cvt_f32_f16_e32 v16, v28
+; GCN-NEXT:    v_cvt_f32_f16_e32 v14, v27
+; GCN-NEXT:    v_cvt_f32_f16_e32 v12, v26
+; GCN-NEXT:    v_cvt_f32_f16_e32 v10, v25
+; GCN-NEXT:    v_cvt_f32_f16_e32 v8, v24
+; GCN-NEXT:    v_cvt_f32_f16_e32 v6, v23
+; GCN-NEXT:    v_cvt_f32_f16_e32 v4, v22
+; GCN-NEXT:    v_cvt_f32_f16_e32 v2, v21
+; GCN-NEXT:    v_cvt_f32_f16_e32 v19, v0
+; GCN-NEXT:    v_cvt_f32_f16_e32 v17, v1
+; GCN-NEXT:    v_cvt_f32_f16_e32 v15, v3
+; GCN-NEXT:    v_cvt_f32_f16_e32 v13, v5
+; GCN-NEXT:    v_cvt_f32_f16_e32 v11, v7
+; GCN-NEXT:    v_cvt_f32_f16_e32 v9, v9
+; GCN-NEXT:    v_cvt_f32_f16_e32 v7, v30
+; GCN-NEXT:    v_cvt_f32_f16_e32 v5, v31
+; GCN-NEXT:    v_cvt_f32_f16_e32 v3, v32
+; GCN-NEXT:    v_cvt_f32_f16_e32 v1, v33
+; GCN-NEXT:    v_cvt_f32_f16_e32 v0, v20
+; GCN-NEXT:    ; implicit-def: $vgpr20
+; GCN-NEXT:    ; implicit-def: $vgpr21
+; GCN-NEXT:    ; implicit-def: $vgpr22
+; GCN-NEXT:    ; implicit-def: $vgpr23
+; GCN-NEXT:    ; implicit-def: $vgpr24
+; GCN-NEXT:    ; implicit-def: $vgpr25
+; GCN-NEXT:    ; implicit-def: $vgpr26
+; GCN-NEXT:    ; implicit-def: $vgpr27
+; GCN-NEXT:    ; implicit-def: $vgpr28
+; GCN-NEXT:    ; implicit-def: $vgpr29
+; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GCN-NEXT:    s_cbranch_execz .LBB10_2
+; GCN-NEXT:  .LBB10_4: ; %cmp.true
+; GCN-NEXT:    v_add_f32_e32 v1, 1.0, v20
+; GCN-NEXT:    v_add_f32_e32 v3, 1.0, v21
+; GCN-NEXT:    v_add_f32_e32 v5, 1.0, v22
+; GCN-NEXT:    v_add_f32_e32 v7, 1.0, v23
+; GCN-NEXT:    v_add_f32_e32 v9, 1.0, v24
+; GCN-NEXT:    v_add_f32_e32 v11, 1.0, v25
+; GCN-NEXT:    v_add_f32_e32 v13, 1.0, v26
+; GCN-NEXT:    v_add_f32_e32 v15, 1.0, v27
+; GCN-NEXT:    v_add_f32_e32 v17, 1.0, v28
+; GCN-NEXT:    v_add_f32_e32 v19, 1.0, v29
+; GCN-NEXT:    v_cvt_f32_f16_e32 v18, v19
+; GCN-NEXT:    v_cvt_f32_f16_e32 v16, v17
+; GCN-NEXT:    v_cvt_f32_f16_e32 v14, v15
+; GCN-NEXT:    v_cvt_f32_f16_e32 v12, v13
+; GCN-NEXT:    v_cvt_f32_f16_e32 v10, v11
+; GCN-NEXT:    v_cvt_f32_f16_e32 v8, v9
+; GCN-NEXT:    v_cvt_f32_f16_e32 v6, v7
+; GCN-NEXT:    v_cvt_f32_f16_e32 v4, v5
+; GCN-NEXT:    v_cvt_f32_f16_e32 v2, v3
+; GCN-NEXT:    v_cvt_f32_f16_e32 v0, v1
+; GCN-NEXT:    v_lshrrev_b32_e32 v19, 16, v19
+; GCN-NEXT:    v_lshrrev_b32_e32 v17, 16, v17
+; GCN-NEXT:    v_lshrrev_b32_e32 v15, 16, v15
+; GCN-NEXT:    v_lshrrev_b32_e32 v13, 16, v13
+; GCN-NEXT:    v_lshrrev_b32_e32 v11, 16, v11
+; GCN-NEXT:    v_lshrrev_b32_e32 v9, 16, v9
+; GCN-NEXT:    v_lshrrev_b32_e32 v7, 16, v7
+; GCN-NEXT:    v_lshrrev_b32_e32 v5, 16, v5
+; GCN-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
+; GCN-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GCN-NEXT:    v_cvt_f32_f16_e32 v19, v19
+; GCN-NEXT:    v_cvt_f32_f16_e32 v17, v17
+; GCN-NEXT:    v_cvt_f32_f16_e32 v15, v15
+; GCN-NEXT:    v_cvt_f32_f16_e32 v13, v13
+; GCN-NEXT:    v_cvt_f32_f16_e32 v11, v11
+; GCN-NEXT:    v_cvt_f32_f16_e32 v9, v9
+; GCN-NEXT:    v_cvt_f32_f16_e32 v7, v7
+; GCN-NEXT:    v_cvt_f32_f16_e32 v5, v5
+; GCN-NEXT:    v_cvt_f32_f16_e32 v3, v3
+; GCN-NEXT:    v_cvt_f32_f16_e32 v1, v1
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GCN-NEXT:    v_mov_b32_e32 v10, v20
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
-; VI-LABEL: bitcast_v10f32_to_v20i16:
+; VI-LABEL: bitcast_v10f32_to_v20f16:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB12_2
+; VI-NEXT:    s_cbranch_execz .LBB10_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.true
 ; VI-NEXT:    v_add_f32_e32 v9, 1.0, v9
 ; VI-NEXT:    v_add_f32_e32 v8, 1.0, v8
@@ -3419,18 +3584,18 @@ define <20 x i16> @bitcast_v10f32_to_v20i16(<10 x float> %a, i32 %b) {
 ; VI-NEXT:    v_add_f32_e32 v2, 1.0, v2
 ; VI-NEXT:    v_add_f32_e32 v1, 1.0, v1
 ; VI-NEXT:    v_add_f32_e32 v0, 1.0, v0
-; VI-NEXT:  .LBB12_2: ; %end
+; VI-NEXT:  .LBB10_2: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX9-LABEL: bitcast_v10f32_to_v20i16:
+; GFX9-LABEL: bitcast_v10f32_to_v20f16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB12_2
+; GFX9-NEXT:    s_cbranch_execz .LBB10_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX9-NEXT:    v_add_f32_e32 v9, 1.0, v9
 ; GFX9-NEXT:    v_add_f32_e32 v8, 1.0, v8
@@ -3442,11 +3607,11 @@ define <20 x i16> @bitcast_v10f32_to_v20i16(<10 x float> %a, i32 %b) {
 ; GFX9-NEXT:    v_add_f32_e32 v2, 1.0, v2
 ; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v1
 ; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v0
-; GFX9-NEXT:  .LBB12_2: ; %end
+; GFX9-NEXT:  .LBB10_2: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v10f32_to_v20i16:
+; GFX11-LABEL: bitcast_v10f32_to_v20f16:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX11-NEXT:    s_mov_b32 s0, exec_lo
@@ -3468,204 +3633,249 @@ define <20 x i16> @bitcast_v10f32_to_v20i16(<10 x float> %a, i32 %b) {
 
 cmp.true:
   %a1 = fadd <10 x float> %a, splat (float 1.000000e+00)
-  %a2 = bitcast <10 x float> %a1 to <20 x i16>
+  %a2 = bitcast <10 x float> %a1 to <20 x half>
   br label %end
 
 cmp.false:
-  %a3 = bitcast <10 x float> %a to <20 x i16>
+  %a3 = bitcast <10 x float> %a to <20 x half>
   br label %end
 
 end:
-  %phi = phi <20 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
-  ret <20 x i16> %phi
+  %phi = phi <20 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
+  ret <20 x half> %phi
 }
 
-define <10 x float> @bitcast_v20i16_to_v10f32(<20 x i16> %a, i32 %b) {
-; GCN-LABEL: bitcast_v20i16_to_v10f32:
+define <10 x float> @bitcast_v20f16_to_v10f32(<20 x half> %a, i32 %b) {
+; GCN-LABEL: bitcast_v20f16_to_v10f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v25, v8
-; GCN-NEXT:    v_mov_b32_e32 v24, v6
-; GCN-NEXT:    v_mov_b32_e32 v23, v4
-; GCN-NEXT:    v_mov_b32_e32 v22, v2
-; GCN-NEXT:    v_mov_b32_e32 v21, v0
 ; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v20
-; GCN-NEXT:    v_lshlrev_b32_e32 v20, 16, v1
-; GCN-NEXT:    v_lshlrev_b32_e32 v26, 16, v3
-; GCN-NEXT:    v_lshlrev_b32_e32 v27, 16, v5
-; GCN-NEXT:    v_lshlrev_b32_e32 v28, 16, v7
-; GCN-NEXT:    v_lshlrev_b32_e32 v29, 16, v9
-; GCN-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GCN-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GCN-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GCN-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GCN-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GCN-NEXT:    v_cvt_f16_f32_e32 v33, v1
+; GCN-NEXT:    v_cvt_f16_f32_e32 v29, v0
+; GCN-NEXT:    v_cvt_f16_f32_e32 v32, v3
+; GCN-NEXT:    v_cvt_f16_f32_e32 v27, v2
+; GCN-NEXT:    v_cvt_f16_f32_e32 v31, v5
+; GCN-NEXT:    v_cvt_f16_f32_e32 v25, v4
+; GCN-NEXT:    v_cvt_f16_f32_e32 v30, v7
+; GCN-NEXT:    v_cvt_f16_f32_e32 v23, v6
+; GCN-NEXT:    v_cvt_f16_f32_e32 v28, v9
+; GCN-NEXT:    v_cvt_f16_f32_e32 v22, v8
+; GCN-NEXT:    v_cvt_f16_f32_e32 v26, v11
+; GCN-NEXT:    v_cvt_f16_f32_e32 v21, v10
+; GCN-NEXT:    v_cvt_f16_f32_e32 v24, v13
+; GCN-NEXT:    v_cvt_f16_f32_e32 v20, v12
+; GCN-NEXT:    v_cvt_f16_f32_e32 v15, v15
+; GCN-NEXT:    v_cvt_f16_f32_e32 v12, v14
+; GCN-NEXT:    v_cvt_f16_f32_e32 v14, v17
+; GCN-NEXT:    v_cvt_f16_f32_e32 v11, v16
+; GCN-NEXT:    v_cvt_f16_f32_e32 v13, v19
+; GCN-NEXT:    v_cvt_f16_f32_e32 v10, v18
 ; GCN-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execnz .LBB13_3
+; GCN-NEXT:    s_cbranch_execnz .LBB11_3
 ; GCN-NEXT:  ; %bb.1: ; %Flow
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execnz .LBB13_4
-; GCN-NEXT:  .LBB13_2: ; %end
+; GCN-NEXT:    s_cbranch_execnz .LBB11_4
+; GCN-NEXT:  .LBB11_2: ; %end
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
-; GCN-NEXT:  .LBB13_3: ; %cmp.false
-; GCN-NEXT:    v_and_b32_e32 v0, 0xffff, v21
-; GCN-NEXT:    v_and_b32_e32 v1, 0xffff, v22
-; GCN-NEXT:    v_and_b32_e32 v2, 0xffff, v23
-; GCN-NEXT:    v_and_b32_e32 v3, 0xffff, v24
-; GCN-NEXT:    v_and_b32_e32 v4, 0xffff, v25
-; GCN-NEXT:    v_and_b32_e32 v5, 0xffff, v10
-; GCN-NEXT:    v_and_b32_e32 v6, 0xffff, v12
-; GCN-NEXT:    v_and_b32_e32 v7, 0xffff, v14
-; GCN-NEXT:    v_and_b32_e32 v8, 0xffff, v16
-; GCN-NEXT:    v_and_b32_e32 v9, 0xffff, v18
-; GCN-NEXT:    v_or_b32_e32 v0, v0, v20
-; GCN-NEXT:    v_or_b32_e32 v1, v1, v26
-; GCN-NEXT:    v_or_b32_e32 v2, v2, v27
-; GCN-NEXT:    v_or_b32_e32 v3, v3, v28
-; GCN-NEXT:    v_or_b32_e32 v4, v4, v29
-; GCN-NEXT:    v_or_b32_e32 v5, v5, v11
-; GCN-NEXT:    v_or_b32_e32 v6, v6, v13
-; GCN-NEXT:    v_or_b32_e32 v7, v7, v15
-; GCN-NEXT:    v_or_b32_e32 v8, v8, v17
-; GCN-NEXT:    v_or_b32_e32 v9, v9, v19
-; GCN-NEXT:    ; implicit-def: $vgpr21
-; GCN-NEXT:    ; implicit-def: $vgpr22
-; GCN-NEXT:    ; implicit-def: $vgpr23
-; GCN-NEXT:    ; implicit-def: $vgpr24
+; GCN-NEXT:  .LBB11_3: ; %cmp.false
+; GCN-NEXT:    v_lshlrev_b32_e32 v0, 16, v33
+; GCN-NEXT:    v_lshlrev_b32_e32 v1, 16, v32
+; GCN-NEXT:    v_lshlrev_b32_e32 v2, 16, v31
+; GCN-NEXT:    v_lshlrev_b32_e32 v3, 16, v30
+; GCN-NEXT:    v_lshlrev_b32_e32 v4, 16, v28
+; GCN-NEXT:    v_lshlrev_b32_e32 v5, 16, v26
+; GCN-NEXT:    v_lshlrev_b32_e32 v6, 16, v24
+; GCN-NEXT:    v_lshlrev_b32_e32 v7, 16, v15
+; GCN-NEXT:    v_lshlrev_b32_e32 v8, 16, v14
+; GCN-NEXT:    v_lshlrev_b32_e32 v9, 16, v13
+; GCN-NEXT:    v_or_b32_e32 v0, v29, v0
+; GCN-NEXT:    v_or_b32_e32 v1, v27, v1
+; GCN-NEXT:    v_or_b32_e32 v2, v25, v2
+; GCN-NEXT:    v_or_b32_e32 v3, v23, v3
+; GCN-NEXT:    v_or_b32_e32 v4, v22, v4
+; GCN-NEXT:    v_or_b32_e32 v5, v21, v5
+; GCN-NEXT:    v_or_b32_e32 v6, v20, v6
+; GCN-NEXT:    v_or_b32_e32 v7, v12, v7
+; GCN-NEXT:    v_or_b32_e32 v8, v11, v8
+; GCN-NEXT:    v_or_b32_e32 v9, v10, v9
+; GCN-NEXT:    ; implicit-def: $vgpr33
+; GCN-NEXT:    ; implicit-def: $vgpr29
+; GCN-NEXT:    ; implicit-def: $vgpr32
+; GCN-NEXT:    ; implicit-def: $vgpr27
+; GCN-NEXT:    ; implicit-def: $vgpr31
 ; GCN-NEXT:    ; implicit-def: $vgpr25
-; GCN-NEXT:    ; implicit-def: $vgpr10
+; GCN-NEXT:    ; implicit-def: $vgpr30
+; GCN-NEXT:    ; implicit-def: $vgpr23
+; GCN-NEXT:    ; implicit-def: $vgpr28
+; GCN-NEXT:    ; implicit-def: $vgpr22
+; GCN-NEXT:    ; implicit-def: $vgpr26
+; GCN-NEXT:    ; implicit-def: $vgpr21
+; GCN-NEXT:    ; implicit-def: $vgpr24
+; GCN-NEXT:    ; implicit-def: $vgpr20
+; GCN-NEXT:    ; implicit-def: $vgpr15
 ; GCN-NEXT:    ; implicit-def: $vgpr12
 ; GCN-NEXT:    ; implicit-def: $vgpr14
-; GCN-NEXT:    ; implicit-def: $vgpr16
-; GCN-NEXT:    ; implicit-def: $vgpr18
-; GCN-NEXT:    ; implicit-def: $vgpr20
-; GCN-NEXT:    ; implicit-def: $vgpr26
-; GCN-NEXT:    ; implicit-def: $vgpr27
-; GCN-NEXT:    ; implicit-def: $vgpr28
-; GCN-NEXT:    ; implicit-def: $vgpr29
 ; GCN-NEXT:    ; implicit-def: $vgpr11
 ; GCN-NEXT:    ; implicit-def: $vgpr13
-; GCN-NEXT:    ; implicit-def: $vgpr15
-; GCN-NEXT:    ; implicit-def: $vgpr17
-; GCN-NEXT:    ; implicit-def: $vgpr19
+; GCN-NEXT:    ; implicit-def: $vgpr10
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB13_2
-; GCN-NEXT:  .LBB13_4: ; %cmp.true
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, 3, v21
-; GCN-NEXT:    s_mov_b32 s6, 0x30000
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, 3, v22
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, 3, v23
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, 3, v24
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, 3, v25
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, 3, v10
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, 3, v12
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, 3, v14
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, 3, v16
-; GCN-NEXT:    v_add_i32_e32 v9, vcc, 3, v18
-; GCN-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GCN-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GCN-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GCN-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GCN-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GCN-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GCN-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GCN-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GCN-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GCN-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GCN-NEXT:    v_or_b32_e32 v0, v20, v0
-; GCN-NEXT:    v_or_b32_e32 v1, v26, v1
-; GCN-NEXT:    v_or_b32_e32 v2, v27, v2
-; GCN-NEXT:    v_or_b32_e32 v3, v28, v3
-; GCN-NEXT:    v_or_b32_e32 v4, v29, v4
-; GCN-NEXT:    v_or_b32_e32 v5, v11, v5
-; GCN-NEXT:    v_or_b32_e32 v6, v13, v6
-; GCN-NEXT:    v_or_b32_e32 v7, v15, v7
-; GCN-NEXT:    v_or_b32_e32 v8, v17, v8
-; GCN-NEXT:    v_or_b32_e32 v9, v19, v9
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, 0x30000, v0
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, s6, v1
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, s6, v2
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, s6, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, s6, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, s6, v5
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, s6, v6
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, 0x30000, v7
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, 0x30000, v8
-; GCN-NEXT:    v_add_i32_e32 v9, vcc, 0x30000, v9
+; GCN-NEXT:    s_cbranch_execz .LBB11_2
+; GCN-NEXT:  .LBB11_4: ; %cmp.true
+; GCN-NEXT:    v_cvt_f32_f16_e32 v0, v33
+; GCN-NEXT:    v_cvt_f32_f16_e32 v1, v29
+; GCN-NEXT:    v_cvt_f32_f16_e32 v2, v32
+; GCN-NEXT:    v_cvt_f32_f16_e32 v3, v27
+; GCN-NEXT:    v_cvt_f32_f16_e32 v4, v31
+; GCN-NEXT:    v_cvt_f32_f16_e32 v5, v25
+; GCN-NEXT:    v_cvt_f32_f16_e32 v6, v30
+; GCN-NEXT:    v_cvt_f32_f16_e32 v7, v23
+; GCN-NEXT:    v_cvt_f32_f16_e32 v8, v28
+; GCN-NEXT:    v_cvt_f32_f16_e32 v9, v22
+; GCN-NEXT:    v_cvt_f32_f16_e32 v16, v26
+; GCN-NEXT:    v_cvt_f32_f16_e32 v17, v21
+; GCN-NEXT:    v_cvt_f32_f16_e32 v18, v24
+; GCN-NEXT:    v_cvt_f32_f16_e32 v19, v20
+; GCN-NEXT:    v_cvt_f32_f16_e32 v15, v15
+; GCN-NEXT:    v_cvt_f32_f16_e32 v12, v12
+; GCN-NEXT:    v_cvt_f32_f16_e32 v14, v14
+; GCN-NEXT:    v_cvt_f32_f16_e32 v11, v11
+; GCN-NEXT:    v_cvt_f32_f16_e32 v13, v13
+; GCN-NEXT:    v_cvt_f32_f16_e32 v10, v10
+; GCN-NEXT:    v_add_f32_e32 v0, 0x38000000, v0
+; GCN-NEXT:    v_add_f32_e32 v1, 0x38000000, v1
+; GCN-NEXT:    v_add_f32_e32 v2, 0x38000000, v2
+; GCN-NEXT:    v_add_f32_e32 v3, 0x38000000, v3
+; GCN-NEXT:    v_add_f32_e32 v4, 0x38000000, v4
+; GCN-NEXT:    v_add_f32_e32 v5, 0x38000000, v5
+; GCN-NEXT:    v_add_f32_e32 v6, 0x38000000, v6
+; GCN-NEXT:    v_add_f32_e32 v7, 0x38000000, v7
+; GCN-NEXT:    v_add_f32_e32 v8, 0x38000000, v8
+; GCN-NEXT:    v_add_f32_e32 v9, 0x38000000, v9
+; GCN-NEXT:    v_add_f32_e32 v16, 0x38000000, v16
+; GCN-NEXT:    v_add_f32_e32 v17, 0x38000000, v17
+; GCN-NEXT:    v_add_f32_e32 v18, 0x38000000, v18
+; GCN-NEXT:    v_add_f32_e32 v19, 0x38000000, v19
+; GCN-NEXT:    v_add_f32_e32 v15, 0x38000000, v15
+; GCN-NEXT:    v_add_f32_e32 v12, 0x38000000, v12
+; GCN-NEXT:    v_add_f32_e32 v14, 0x38000000, v14
+; GCN-NEXT:    v_add_f32_e32 v11, 0x38000000, v11
+; GCN-NEXT:    v_add_f32_e32 v13, 0x38000000, v13
+; GCN-NEXT:    v_add_f32_e32 v10, 0x38000000, v10
+; GCN-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GCN-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GCN-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GCN-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; GCN-NEXT:    v_cvt_f16_f32_e32 v4, v4
+; GCN-NEXT:    v_cvt_f16_f32_e32 v5, v5
+; GCN-NEXT:    v_cvt_f16_f32_e32 v6, v6
+; GCN-NEXT:    v_cvt_f16_f32_e32 v7, v7
+; GCN-NEXT:    v_cvt_f16_f32_e32 v8, v8
+; GCN-NEXT:    v_cvt_f16_f32_e32 v9, v9
+; GCN-NEXT:    v_cvt_f16_f32_e32 v16, v16
+; GCN-NEXT:    v_cvt_f16_f32_e32 v17, v17
+; GCN-NEXT:    v_cvt_f16_f32_e32 v18, v18
+; GCN-NEXT:    v_cvt_f16_f32_e32 v19, v19
+; GCN-NEXT:    v_cvt_f16_f32_e32 v15, v15
+; GCN-NEXT:    v_cvt_f16_f32_e32 v12, v12
+; GCN-NEXT:    v_cvt_f16_f32_e32 v14, v14
+; GCN-NEXT:    v_cvt_f16_f32_e32 v11, v11
+; GCN-NEXT:    v_cvt_f16_f32_e32 v13, v13
+; GCN-NEXT:    v_cvt_f16_f32_e32 v10, v10
+; GCN-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GCN-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GCN-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GCN-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GCN-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GCN-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GCN-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GCN-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GCN-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GCN-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GCN-NEXT:    v_or_b32_e32 v0, v1, v0
+; GCN-NEXT:    v_or_b32_e32 v1, v3, v2
+; GCN-NEXT:    v_or_b32_e32 v2, v5, v4
+; GCN-NEXT:    v_or_b32_e32 v3, v7, v6
+; GCN-NEXT:    v_or_b32_e32 v4, v9, v8
+; GCN-NEXT:    v_or_b32_e32 v5, v17, v16
+; GCN-NEXT:    v_or_b32_e32 v6, v19, v18
+; GCN-NEXT:    v_or_b32_e32 v7, v12, v15
+; GCN-NEXT:    v_or_b32_e32 v8, v11, v14
+; GCN-NEXT:    v_or_b32_e32 v9, v10, v13
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
-; VI-LABEL: bitcast_v20i16_to_v10f32:
+; VI-LABEL: bitcast_v20f16_to_v10f32:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB13_2
+; VI-NEXT:    s_cbranch_execz .LBB11_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.true
-; VI-NEXT:    v_mov_b32_e32 v11, 3
-; VI-NEXT:    v_add_u16_e32 v10, 3, v9
-; VI-NEXT:    v_add_u16_sdwa v9, v9, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v9, v10, v9
-; VI-NEXT:    v_add_u16_e32 v10, 3, v8
-; VI-NEXT:    v_add_u16_sdwa v8, v8, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v8, v10, v8
-; VI-NEXT:    v_add_u16_e32 v10, 3, v7
-; VI-NEXT:    v_add_u16_sdwa v7, v7, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v7, v10, v7
-; VI-NEXT:    v_add_u16_e32 v10, 3, v6
-; VI-NEXT:    v_add_u16_sdwa v6, v6, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v6, v10, v6
-; VI-NEXT:    v_add_u16_e32 v10, 3, v5
-; VI-NEXT:    v_add_u16_sdwa v5, v5, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v5, v10, v5
-; VI-NEXT:    v_add_u16_e32 v10, 3, v4
-; VI-NEXT:    v_add_u16_sdwa v4, v4, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v4, v10, v4
-; VI-NEXT:    v_add_u16_e32 v10, 3, v3
-; VI-NEXT:    v_add_u16_sdwa v3, v3, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v3, v10, v3
-; VI-NEXT:    v_add_u16_e32 v10, 3, v2
-; VI-NEXT:    v_add_u16_sdwa v2, v2, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v2, v10, v2
-; VI-NEXT:    v_add_u16_e32 v10, 3, v1
-; VI-NEXT:    v_add_u16_sdwa v1, v1, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v1, v10, v1
-; VI-NEXT:    v_add_u16_e32 v10, 3, v0
-; VI-NEXT:    v_add_u16_sdwa v0, v0, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v0, v10, v0
-; VI-NEXT:  .LBB13_2: ; %end
+; VI-NEXT:    v_mov_b32_e32 v10, 0x200
+; VI-NEXT:    v_add_f16_sdwa v11, v9, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT:    v_add_f16_e32 v9, 0x200, v9
+; VI-NEXT:    v_or_b32_e32 v9, v9, v11
+; VI-NEXT:    v_add_f16_sdwa v11, v8, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT:    v_add_f16_e32 v8, 0x200, v8
+; VI-NEXT:    v_or_b32_e32 v8, v8, v11
+; VI-NEXT:    v_add_f16_sdwa v11, v7, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT:    v_add_f16_e32 v7, 0x200, v7
+; VI-NEXT:    v_or_b32_e32 v7, v7, v11
+; VI-NEXT:    v_add_f16_sdwa v11, v6, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT:    v_add_f16_e32 v6, 0x200, v6
+; VI-NEXT:    v_or_b32_e32 v6, v6, v11
+; VI-NEXT:    v_add_f16_sdwa v11, v5, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT:    v_add_f16_e32 v5, 0x200, v5
+; VI-NEXT:    v_or_b32_e32 v5, v5, v11
+; VI-NEXT:    v_add_f16_sdwa v11, v4, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT:    v_add_f16_e32 v4, 0x200, v4
+; VI-NEXT:    v_or_b32_e32 v4, v4, v11
+; VI-NEXT:    v_add_f16_sdwa v11, v3, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT:    v_add_f16_e32 v3, 0x200, v3
+; VI-NEXT:    v_or_b32_e32 v3, v3, v11
+; VI-NEXT:    v_add_f16_sdwa v11, v2, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT:    v_add_f16_e32 v2, 0x200, v2
+; VI-NEXT:    v_or_b32_e32 v2, v2, v11
+; VI-NEXT:    v_add_f16_sdwa v11, v1, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT:    v_add_f16_e32 v1, 0x200, v1
+; VI-NEXT:    v_add_f16_sdwa v10, v0, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT:    v_add_f16_e32 v0, 0x200, v0
+; VI-NEXT:    v_or_b32_e32 v1, v1, v11
+; VI-NEXT:    v_or_b32_e32 v0, v0, v10
+; VI-NEXT:  .LBB11_2: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX9-LABEL: bitcast_v20i16_to_v10f32:
+; GFX9-LABEL: bitcast_v20f16_to_v10f32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB13_2
+; GFX9-NEXT:    s_cbranch_execz .LBB11_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.true
-; GFX9-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:  .LBB13_2: ; %end
+; GFX9-NEXT:    s_movk_i32 s6, 0x200
+; GFX9-NEXT:    v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]
+; GFX9-NEXT:    v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]
+; GFX9-NEXT:    v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]
+; GFX9-NEXT:    v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]
+; GFX9-NEXT:    v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]
+; GFX9-NEXT:    v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]
+; GFX9-NEXT:    v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]
+; GFX9-NEXT:    v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
+; GFX9-NEXT:    v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
+; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
+; GFX9-NEXT:  .LBB11_2: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v20i16_to_v10f32:
+; GFX11-LABEL: bitcast_v20f16_to_v10f32:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX11-NEXT:    s_mov_b32 s0, exec_lo
@@ -3673,31 +3883,31 @@ define <10 x float> @bitcast_v20i16_to_v10f32(<20 x i16> %a, i32 %b) {
 ; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB13_2
+; GFX11-NEXT:    s_cbranch_execz .LBB11_2
 ; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:  .LBB13_2: ; %end
+; GFX11-NEXT:    v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
+; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
+; GFX11-NEXT:  .LBB11_2: ; %end
 ; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
 cmp.true:
-  %a1 = add <20 x i16> %a, splat (i16 3)
-  %a2 = bitcast <20 x i16> %a1 to <10 x float>
+  %a1 = fadd <20 x half> %a, splat (half 0xH0200)
+  %a2 = bitcast <20 x half> %a1 to <10 x float>
   br label %end
 
 cmp.false:
-  %a3 = bitcast <20 x i16> %a to <10 x float>
+  %a3 = bitcast <20 x half> %a to <10 x float>
   br label %end
 
 end:
@@ -3705,3797 +3915,420 @@ end:
   ret <10 x float> %phi
 }
 
-define <20 x half> @bitcast_v10f32_to_v20f16(<10 x float> %a, i32 %b) {
-; GCN-LABEL: bitcast_v10f32_to_v20f16:
+define <40 x i8> @bitcast_v10f32_to_v40i8(<10 x float> %a, i32 %b) {
+; GCN-LABEL: bitcast_v10f32_to_v40i8:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v29, v9
-; GCN-NEXT:    v_mov_b32_e32 v28, v8
-; GCN-NEXT:    v_mov_b32_e32 v27, v7
-; GCN-NEXT:    v_mov_b32_e32 v26, v6
-; GCN-NEXT:    v_mov_b32_e32 v25, v5
-; GCN-NEXT:    v_mov_b32_e32 v24, v4
-; GCN-NEXT:    v_mov_b32_e32 v23, v3
-; GCN-NEXT:    v_mov_b32_e32 v22, v2
-; GCN-NEXT:    v_mov_b32_e32 v21, v1
-; GCN-NEXT:    v_mov_b32_e32 v20, v0
-; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; GCN-NEXT:    ; implicit-def: $vgpr0
-; GCN-NEXT:    ; implicit-def: $vgpr1
-; GCN-NEXT:    ; implicit-def: $vgpr2
-; GCN-NEXT:    ; implicit-def: $vgpr3
-; GCN-NEXT:    ; implicit-def: $vgpr4
-; GCN-NEXT:    ; implicit-def: $vgpr5
-; GCN-NEXT:    ; implicit-def: $vgpr6
-; GCN-NEXT:    ; implicit-def: $vgpr7
-; GCN-NEXT:    ; implicit-def: $vgpr8
-; GCN-NEXT:    ; implicit-def: $vgpr9
-; GCN-NEXT:    ; implicit-def: $vgpr10
-; GCN-NEXT:    ; implicit-def: $vgpr11
-; GCN-NEXT:    ; implicit-def: $vgpr12
-; GCN-NEXT:    ; implicit-def: $vgpr13
-; GCN-NEXT:    ; implicit-def: $vgpr14
-; GCN-NEXT:    ; implicit-def: $vgpr15
-; GCN-NEXT:    ; implicit-def: $vgpr16
-; GCN-NEXT:    ; implicit-def: $vgpr17
-; GCN-NEXT:    ; implicit-def: $vgpr18
-; GCN-NEXT:    ; implicit-def: $vgpr19
-; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execnz .LBB14_3
-; GCN-NEXT:  ; %bb.1: ; %Flow
-; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execnz .LBB14_4
-; GCN-NEXT:  .LBB14_2: ; %end
-; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-; GCN-NEXT:  .LBB14_3: ; %cmp.false
-; GCN-NEXT:    v_lshrrev_b32_e32 v0, 16, v29
-; GCN-NEXT:    v_lshrrev_b32_e32 v1, 16, v28
-; GCN-NEXT:    v_lshrrev_b32_e32 v3, 16, v27
-; GCN-NEXT:    v_lshrrev_b32_e32 v5, 16, v26
-; GCN-NEXT:    v_lshrrev_b32_e32 v7, 16, v25
-; GCN-NEXT:    v_lshrrev_b32_e32 v9, 16, v24
-; GCN-NEXT:    v_lshrrev_b32_e32 v30, 16, v23
-; GCN-NEXT:    v_lshrrev_b32_e32 v31, 16, v22
-; GCN-NEXT:    v_lshrrev_b32_e32 v32, 16, v21
-; GCN-NEXT:    v_lshrrev_b32_e32 v33, 16, v20
-; GCN-NEXT:    v_cvt_f32_f16_e32 v18, v29
-; GCN-NEXT:    v_cvt_f32_f16_e32 v16, v28
-; GCN-NEXT:    v_cvt_f32_f16_e32 v14, v27
-; GCN-NEXT:    v_cvt_f32_f16_e32 v12, v26
-; GCN-NEXT:    v_cvt_f32_f16_e32 v10, v25
-; GCN-NEXT:    v_cvt_f32_f16_e32 v8, v24
-; GCN-NEXT:    v_cvt_f32_f16_e32 v6, v23
-; GCN-NEXT:    v_cvt_f32_f16_e32 v4, v22
-; GCN-NEXT:    v_cvt_f32_f16_e32 v2, v21
-; GCN-NEXT:    v_cvt_f32_f16_e32 v19, v0
-; GCN-NEXT:    v_cvt_f32_f16_e32 v17, v1
-; GCN-NEXT:    v_cvt_f32_f16_e32 v15, v3
-; GCN-NEXT:    v_cvt_f32_f16_e32 v13, v5
-; GCN-NEXT:    v_cvt_f32_f16_e32 v11, v7
-; GCN-NEXT:    v_cvt_f32_f16_e32 v9, v9
-; GCN-NEXT:    v_cvt_f32_f16_e32 v7, v30
-; GCN-NEXT:    v_cvt_f32_f16_e32 v5, v31
-; GCN-NEXT:    v_cvt_f32_f16_e32 v3, v32
-; GCN-NEXT:    v_cvt_f32_f16_e32 v1, v33
-; GCN-NEXT:    v_cvt_f32_f16_e32 v0, v20
-; GCN-NEXT:    ; implicit-def: $vgpr20
-; GCN-NEXT:    ; implicit-def: $vgpr21
-; GCN-NEXT:    ; implicit-def: $vgpr22
-; GCN-NEXT:    ; implicit-def: $vgpr23
-; GCN-NEXT:    ; implicit-def: $vgpr24
-; GCN-NEXT:    ; implicit-def: $vgpr25
-; GCN-NEXT:    ; implicit-def: $vgpr26
-; GCN-NEXT:    ; implicit-def: $vgpr27
-; GCN-NEXT:    ; implicit-def: $vgpr28
-; GCN-NEXT:    ; implicit-def: $vgpr29
-; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB14_2
-; GCN-NEXT:  .LBB14_4: ; %cmp.true
-; GCN-NEXT:    v_add_f32_e32 v1, 1.0, v20
-; GCN-NEXT:    v_add_f32_e32 v3, 1.0, v21
-; GCN-NEXT:    v_add_f32_e32 v5, 1.0, v22
-; GCN-NEXT:    v_add_f32_e32 v7, 1.0, v23
-; GCN-NEXT:    v_add_f32_e32 v9, 1.0, v24
-; GCN-NEXT:    v_add_f32_e32 v11, 1.0, v25
-; GCN-NEXT:    v_add_f32_e32 v13, 1.0, v26
-; GCN-NEXT:    v_add_f32_e32 v15, 1.0, v27
-; GCN-NEXT:    v_add_f32_e32 v17, 1.0, v28
-; GCN-NEXT:    v_add_f32_e32 v19, 1.0, v29
-; GCN-NEXT:    v_cvt_f32_f16_e32 v18, v19
-; GCN-NEXT:    v_cvt_f32_f16_e32 v16, v17
-; GCN-NEXT:    v_cvt_f32_f16_e32 v14, v15
-; GCN-NEXT:    v_cvt_f32_f16_e32 v12, v13
-; GCN-NEXT:    v_cvt_f32_f16_e32 v10, v11
-; GCN-NEXT:    v_cvt_f32_f16_e32 v8, v9
-; GCN-NEXT:    v_cvt_f32_f16_e32 v6, v7
-; GCN-NEXT:    v_cvt_f32_f16_e32 v4, v5
-; GCN-NEXT:    v_cvt_f32_f16_e32 v2, v3
-; GCN-NEXT:    v_cvt_f32_f16_e32 v0, v1
-; GCN-NEXT:    v_lshrrev_b32_e32 v19, 16, v19
-; GCN-NEXT:    v_lshrrev_b32_e32 v17, 16, v17
-; GCN-NEXT:    v_lshrrev_b32_e32 v15, 16, v15
-; GCN-NEXT:    v_lshrrev_b32_e32 v13, 16, v13
-; GCN-NEXT:    v_lshrrev_b32_e32 v11, 16, v11
-; GCN-NEXT:    v_lshrrev_b32_e32 v9, 16, v9
-; GCN-NEXT:    v_lshrrev_b32_e32 v7, 16, v7
-; GCN-NEXT:    v_lshrrev_b32_e32 v5, 16, v5
-; GCN-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
-; GCN-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GCN-NEXT:    v_cvt_f32_f16_e32 v19, v19
-; GCN-NEXT:    v_cvt_f32_f16_e32 v17, v17
-; GCN-NEXT:    v_cvt_f32_f16_e32 v15, v15
-; GCN-NEXT:    v_cvt_f32_f16_e32 v13, v13
-; GCN-NEXT:    v_cvt_f32_f16_e32 v11, v11
-; GCN-NEXT:    v_cvt_f32_f16_e32 v9, v9
-; GCN-NEXT:    v_cvt_f32_f16_e32 v7, v7
-; GCN-NEXT:    v_cvt_f32_f16_e32 v5, v5
-; GCN-NEXT:    v_cvt_f32_f16_e32 v3, v3
-; GCN-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; VI-LABEL: bitcast_v10f32_to_v20f16:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB14_2
-; VI-NEXT:  ; %bb.1: ; %cmp.true
-; VI-NEXT:    v_add_f32_e32 v9, 1.0, v9
-; VI-NEXT:    v_add_f32_e32 v8, 1.0, v8
-; VI-NEXT:    v_add_f32_e32 v7, 1.0, v7
-; VI-NEXT:    v_add_f32_e32 v6, 1.0, v6
-; VI-NEXT:    v_add_f32_e32 v5, 1.0, v5
-; VI-NEXT:    v_add_f32_e32 v4, 1.0, v4
-; VI-NEXT:    v_add_f32_e32 v3, 1.0, v3
-; VI-NEXT:    v_add_f32_e32 v2, 1.0, v2
-; VI-NEXT:    v_add_f32_e32 v1, 1.0, v1
-; VI-NEXT:    v_add_f32_e32 v0, 1.0, v0
-; VI-NEXT:  .LBB14_2: ; %end
-; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
-; VI-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: bitcast_v10f32_to_v20f16:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB14_2
-; GFX9-NEXT:  ; %bb.1: ; %cmp.true
-; GFX9-NEXT:    v_add_f32_e32 v9, 1.0, v9
-; GFX9-NEXT:    v_add_f32_e32 v8, 1.0, v8
-; GFX9-NEXT:    v_add_f32_e32 v7, 1.0, v7
-; GFX9-NEXT:    v_add_f32_e32 v6, 1.0, v6
-; GFX9-NEXT:    v_add_f32_e32 v5, 1.0, v5
-; GFX9-NEXT:    v_add_f32_e32 v4, 1.0, v4
-; GFX9-NEXT:    v_add_f32_e32 v3, 1.0, v3
-; GFX9-NEXT:    v_add_f32_e32 v2, 1.0, v2
-; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v1
-; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v0
-; GFX9-NEXT:  .LBB14_2: ; %end
-; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: bitcast_v10f32_to_v20f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
-; GFX11-NEXT:    v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
-; GFX11-NEXT:    v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
-; GFX11-NEXT:    v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
-; GFX11-NEXT:    v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-NEXT:  ; %bb.2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %cmp = icmp eq i32 %b, 0
-  br i1 %cmp, label %cmp.true, label %cmp.false
-
-cmp.true:
-  %a1 = fadd <10 x float> %a, splat (float 1.000000e+00)
-  %a2 = bitcast <10 x float> %a1 to <20 x half>
-  br label %end
-
-cmp.false:
-  %a3 = bitcast <10 x float> %a to <20 x half>
-  br label %end
-
-end:
-  %phi = phi <20 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
-  ret <20 x half> %phi
-}
-
-define <10 x float> @bitcast_v20f16_to_v10f32(<20 x half> %a, i32 %b) {
-; GCN-LABEL: bitcast_v20f16_to_v10f32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v20
-; GCN-NEXT:    v_cvt_f16_f32_e32 v33, v1
-; GCN-NEXT:    v_cvt_f16_f32_e32 v29, v0
-; GCN-NEXT:    v_cvt_f16_f32_e32 v32, v3
-; GCN-NEXT:    v_cvt_f16_f32_e32 v27, v2
-; GCN-NEXT:    v_cvt_f16_f32_e32 v31, v5
-; GCN-NEXT:    v_cvt_f16_f32_e32 v25, v4
-; GCN-NEXT:    v_cvt_f16_f32_e32 v30, v7
-; GCN-NEXT:    v_cvt_f16_f32_e32 v23, v6
-; GCN-NEXT:    v_cvt_f16_f32_e32 v28, v9
-; GCN-NEXT:    v_cvt_f16_f32_e32 v22, v8
-; GCN-NEXT:    v_cvt_f16_f32_e32 v26, v11
-; GCN-NEXT:    v_cvt_f16_f32_e32 v21, v10
-; GCN-NEXT:    v_cvt_f16_f32_e32 v24, v13
-; GCN-NEXT:    v_cvt_f16_f32_e32 v20, v12
-; GCN-NEXT:    v_cvt_f16_f32_e32 v15, v15
-; GCN-NEXT:    v_cvt_f16_f32_e32 v12, v14
-; GCN-NEXT:    v_cvt_f16_f32_e32 v14, v17
-; GCN-NEXT:    v_cvt_f16_f32_e32 v11, v16
-; GCN-NEXT:    v_cvt_f16_f32_e32 v13, v19
-; GCN-NEXT:    v_cvt_f16_f32_e32 v10, v18
-; GCN-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
-; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execnz .LBB15_3
-; GCN-NEXT:  ; %bb.1: ; %Flow
-; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execnz .LBB15_4
-; GCN-NEXT:  .LBB15_2: ; %end
-; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-; GCN-NEXT:  .LBB15_3: ; %cmp.false
-; GCN-NEXT:    v_lshlrev_b32_e32 v0, 16, v33
-; GCN-NEXT:    v_lshlrev_b32_e32 v1, 16, v32
-; GCN-NEXT:    v_lshlrev_b32_e32 v2, 16, v31
-; GCN-NEXT:    v_lshlrev_b32_e32 v3, 16, v30
-; GCN-NEXT:    v_lshlrev_b32_e32 v4, 16, v28
-; GCN-NEXT:    v_lshlrev_b32_e32 v5, 16, v26
-; GCN-NEXT:    v_lshlrev_b32_e32 v6, 16, v24
-; GCN-NEXT:    v_lshlrev_b32_e32 v7, 16, v15
-; GCN-NEXT:    v_lshlrev_b32_e32 v8, 16, v14
-; GCN-NEXT:    v_lshlrev_b32_e32 v9, 16, v13
-; GCN-NEXT:    v_or_b32_e32 v0, v29, v0
-; GCN-NEXT:    v_or_b32_e32 v1, v27, v1
-; GCN-NEXT:    v_or_b32_e32 v2, v25, v2
-; GCN-NEXT:    v_or_b32_e32 v3, v23, v3
-; GCN-NEXT:    v_or_b32_e32 v4, v22, v4
-; GCN-NEXT:    v_or_b32_e32 v5, v21, v5
-; GCN-NEXT:    v_or_b32_e32 v6, v20, v6
-; GCN-NEXT:    v_or_b32_e32 v7, v12, v7
-; GCN-NEXT:    v_or_b32_e32 v8, v11, v8
-; GCN-NEXT:    v_or_b32_e32 v9, v10, v9
-; GCN-NEXT:    ; implicit-def: $vgpr33
-; GCN-NEXT:    ; implicit-def: $vgpr29
-; GCN-NEXT:    ; implicit-def: $vgpr32
-; GCN-NEXT:    ; implicit-def: $vgpr27
-; GCN-NEXT:    ; implicit-def: $vgpr31
-; GCN-NEXT:    ; implicit-def: $vgpr25
-; GCN-NEXT:    ; implicit-def: $vgpr30
-; GCN-NEXT:    ; implicit-def: $vgpr23
-; GCN-NEXT:    ; implicit-def: $vgpr28
-; GCN-NEXT:    ; implicit-def: $vgpr22
-; GCN-NEXT:    ; implicit-def: $vgpr26
-; GCN-NEXT:    ; implicit-def: $vgpr21
-; GCN-NEXT:    ; implicit-def: $vgpr24
-; GCN-NEXT:    ; implicit-def: $vgpr20
-; GCN-NEXT:    ; implicit-def: $vgpr15
-; GCN-NEXT:    ; implicit-def: $vgpr12
-; GCN-NEXT:    ; implicit-def: $vgpr14
-; GCN-NEXT:    ; implicit-def: $vgpr11
-; GCN-NEXT:    ; implicit-def: $vgpr13
-; GCN-NEXT:    ; implicit-def: $vgpr10
-; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB15_2
-; GCN-NEXT:  .LBB15_4: ; %cmp.true
-; GCN-NEXT:    v_cvt_f32_f16_e32 v0, v33
-; GCN-NEXT:    v_cvt_f32_f16_e32 v1, v29
-; GCN-NEXT:    v_cvt_f32_f16_e32 v2, v32
-; GCN-NEXT:    v_cvt_f32_f16_e32 v3, v27
-; GCN-NEXT:    v_cvt_f32_f16_e32 v4, v31
-; GCN-NEXT:    v_cvt_f32_f16_e32 v5, v25
-; GCN-NEXT:    v_cvt_f32_f16_e32 v6, v30
-; GCN-NEXT:    v_cvt_f32_f16_e32 v7, v23
-; GCN-NEXT:    v_cvt_f32_f16_e32 v8, v28
-; GCN-NEXT:    v_cvt_f32_f16_e32 v9, v22
-; GCN-NEXT:    v_cvt_f32_f16_e32 v16, v26
-; GCN-NEXT:    v_cvt_f32_f16_e32 v17, v21
-; GCN-NEXT:    v_cvt_f32_f16_e32 v18, v24
-; GCN-NEXT:    v_cvt_f32_f16_e32 v19, v20
-; GCN-NEXT:    v_cvt_f32_f16_e32 v15, v15
-; GCN-NEXT:    v_cvt_f32_f16_e32 v12, v12
-; GCN-NEXT:    v_cvt_f32_f16_e32 v14, v14
-; GCN-NEXT:    v_cvt_f32_f16_e32 v11, v11
-; GCN-NEXT:    v_cvt_f32_f16_e32 v13, v13
-; GCN-NEXT:    v_cvt_f32_f16_e32 v10, v10
-; GCN-NEXT:    v_add_f32_e32 v0, 0x38000000, v0
-; GCN-NEXT:    v_add_f32_e32 v1, 0x38000000, v1
-; GCN-NEXT:    v_add_f32_e32 v2, 0x38000000, v2
-; GCN-NEXT:    v_add_f32_e32 v3, 0x38000000, v3
-; GCN-NEXT:    v_add_f32_e32 v4, 0x38000000, v4
-; GCN-NEXT:    v_add_f32_e32 v5, 0x38000000, v5
-; GCN-NEXT:    v_add_f32_e32 v6, 0x38000000, v6
-; GCN-NEXT:    v_add_f32_e32 v7, 0x38000000, v7
-; GCN-NEXT:    v_add_f32_e32 v8, 0x38000000, v8
-; GCN-NEXT:    v_add_f32_e32 v9, 0x38000000, v9
-; GCN-NEXT:    v_add_f32_e32 v16, 0x38000000, v16
-; GCN-NEXT:    v_add_f32_e32 v17, 0x38000000, v17
-; GCN-NEXT:    v_add_f32_e32 v18, 0x38000000, v18
-; GCN-NEXT:    v_add_f32_e32 v19, 0x38000000, v19
-; GCN-NEXT:    v_add_f32_e32 v15, 0x38000000, v15
-; GCN-NEXT:    v_add_f32_e32 v12, 0x38000000, v12
-; GCN-NEXT:    v_add_f32_e32 v14, 0x38000000, v14
-; GCN-NEXT:    v_add_f32_e32 v11, 0x38000000, v11
-; GCN-NEXT:    v_add_f32_e32 v13, 0x38000000, v13
-; GCN-NEXT:    v_add_f32_e32 v10, 0x38000000, v10
-; GCN-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GCN-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GCN-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; GCN-NEXT:    v_cvt_f16_f32_e32 v3, v3
-; GCN-NEXT:    v_cvt_f16_f32_e32 v4, v4
-; GCN-NEXT:    v_cvt_f16_f32_e32 v5, v5
-; GCN-NEXT:    v_cvt_f16_f32_e32 v6, v6
-; GCN-NEXT:    v_cvt_f16_f32_e32 v7, v7
-; GCN-NEXT:    v_cvt_f16_f32_e32 v8, v8
-; GCN-NEXT:    v_cvt_f16_f32_e32 v9, v9
-; GCN-NEXT:    v_cvt_f16_f32_e32 v16, v16
-; GCN-NEXT:    v_cvt_f16_f32_e32 v17, v17
-; GCN-NEXT:    v_cvt_f16_f32_e32 v18, v18
-; GCN-NEXT:    v_cvt_f16_f32_e32 v19, v19
-; GCN-NEXT:    v_cvt_f16_f32_e32 v15, v15
-; GCN-NEXT:    v_cvt_f16_f32_e32 v12, v12
-; GCN-NEXT:    v_cvt_f16_f32_e32 v14, v14
-; GCN-NEXT:    v_cvt_f16_f32_e32 v11, v11
-; GCN-NEXT:    v_cvt_f16_f32_e32 v13, v13
-; GCN-NEXT:    v_cvt_f16_f32_e32 v10, v10
-; GCN-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
-; GCN-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GCN-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
-; GCN-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GCN-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GCN-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GCN-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GCN-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GCN-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GCN-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GCN-NEXT:    v_or_b32_e32 v0, v1, v0
-; GCN-NEXT:    v_or_b32_e32 v1, v3, v2
-; GCN-NEXT:    v_or_b32_e32 v2, v5, v4
-; GCN-NEXT:    v_or_b32_e32 v3, v7, v6
-; GCN-NEXT:    v_or_b32_e32 v4, v9, v8
-; GCN-NEXT:    v_or_b32_e32 v5, v17, v16
-; GCN-NEXT:    v_or_b32_e32 v6, v19, v18
-; GCN-NEXT:    v_or_b32_e32 v7, v12, v15
-; GCN-NEXT:    v_or_b32_e32 v8, v11, v14
-; GCN-NEXT:    v_or_b32_e32 v9, v10, v13
-; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; VI-LABEL: bitcast_v20f16_to_v10f32:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB15_2
-; VI-NEXT:  ; %bb.1: ; %cmp.true
-; VI-NEXT:    v_mov_b32_e32 v10, 0x200
-; VI-NEXT:    v_add_f16_sdwa v11, v9, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_f16_e32 v9, 0x200, v9
-; VI-NEXT:    v_or_b32_e32 v9, v9, v11
-; VI-NEXT:    v_add_f16_sdwa v11, v8, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_f16_e32 v8, 0x200, v8
-; VI-NEXT:    v_or_b32_e32 v8, v8, v11
-; VI-NEXT:    v_add_f16_sdwa v11, v7, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_f16_e32 v7, 0x200, v7
-; VI-NEXT:    v_or_b32_e32 v7, v7, v11
-; VI-NEXT:    v_add_f16_sdwa v11, v6, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_f16_e32 v6, 0x200, v6
-; VI-NEXT:    v_or_b32_e32 v6, v6, v11
-; VI-NEXT:    v_add_f16_sdwa v11, v5, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_f16_e32 v5, 0x200, v5
-; VI-NEXT:    v_or_b32_e32 v5, v5, v11
-; VI-NEXT:    v_add_f16_sdwa v11, v4, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_f16_e32 v4, 0x200, v4
-; VI-NEXT:    v_or_b32_e32 v4, v4, v11
-; VI-NEXT:    v_add_f16_sdwa v11, v3, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_f16_e32 v3, 0x200, v3
-; VI-NEXT:    v_or_b32_e32 v3, v3, v11
-; VI-NEXT:    v_add_f16_sdwa v11, v2, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_f16_e32 v2, 0x200, v2
-; VI-NEXT:    v_or_b32_e32 v2, v2, v11
-; VI-NEXT:    v_add_f16_sdwa v11, v1, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_f16_e32 v1, 0x200, v1
-; VI-NEXT:    v_add_f16_sdwa v10, v0, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_f16_e32 v0, 0x200, v0
-; VI-NEXT:    v_or_b32_e32 v1, v1, v11
-; VI-NEXT:    v_or_b32_e32 v0, v0, v10
-; VI-NEXT:  .LBB15_2: ; %end
-; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
-; VI-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: bitcast_v20f16_to_v10f32:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB15_2
-; GFX9-NEXT:  ; %bb.1: ; %cmp.true
-; GFX9-NEXT:    s_movk_i32 s6, 0x200
-; GFX9-NEXT:    v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
-; GFX9-NEXT:  .LBB15_2: ; %end
-; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: bitcast_v20f16_to_v10f32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB15_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
-; GFX11-NEXT:  .LBB15_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %cmp = icmp eq i32 %b, 0
-  br i1 %cmp, label %cmp.true, label %cmp.false
-
-cmp.true:
-  %a1 = fadd <20 x half> %a, splat (half 0xH0200)
-  %a2 = bitcast <20 x half> %a1 to <10 x float>
-  br label %end
-
-cmp.false:
-  %a3 = bitcast <20 x half> %a to <10 x float>
-  br label %end
-
-end:
-  %phi = phi <10 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
-  ret <10 x float> %phi
-}
-
-define <40 x i8> @bitcast_v10f32_to_v40i8(<10 x float> %a, i32 %b) {
-; GCN-LABEL: bitcast_v10f32_to_v40i8:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
-; GCN-NEXT:    ; implicit-def: $vgpr35
-; GCN-NEXT:    ; implicit-def: $vgpr33
-; GCN-NEXT:    ; implicit-def: $vgpr32
-; GCN-NEXT:    ; implicit-def: $vgpr48
-; GCN-NEXT:    ; implicit-def: $vgpr39
-; GCN-NEXT:    ; implicit-def: $vgpr38
-; GCN-NEXT:    ; implicit-def: $vgpr29
-; GCN-NEXT:    ; implicit-def: $vgpr27
-; GCN-NEXT:    ; implicit-def: $vgpr26
-; GCN-NEXT:    ; implicit-def: $vgpr37
-; GCN-NEXT:    ; implicit-def: $vgpr36
-; GCN-NEXT:    ; implicit-def: $vgpr34
-; GCN-NEXT:    ; implicit-def: $vgpr23
-; GCN-NEXT:    ; implicit-def: $vgpr21
-; GCN-NEXT:    ; implicit-def: $vgpr20
-; GCN-NEXT:    ; implicit-def: $vgpr31
-; GCN-NEXT:    ; implicit-def: $vgpr30
-; GCN-NEXT:    ; implicit-def: $vgpr28
-; GCN-NEXT:    ; implicit-def: $vgpr17
-; GCN-NEXT:    ; implicit-def: $vgpr15
-; GCN-NEXT:    ; implicit-def: $vgpr14
-; GCN-NEXT:    ; implicit-def: $vgpr25
-; GCN-NEXT:    ; implicit-def: $vgpr24
-; GCN-NEXT:    ; implicit-def: $vgpr22
-; GCN-NEXT:    ; implicit-def: $vgpr13
-; GCN-NEXT:    ; implicit-def: $vgpr12
-; GCN-NEXT:    ; implicit-def: $vgpr11
-; GCN-NEXT:    ; implicit-def: $vgpr19
-; GCN-NEXT:    ; implicit-def: $vgpr18
-; GCN-NEXT:    ; implicit-def: $vgpr16
-; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB16_2
-; GCN-NEXT:  ; %bb.1: ; %cmp.false
-; GCN-NEXT:    v_alignbit_b32 v11, v10, v9, 24
-; GCN-NEXT:    v_alignbit_b32 v12, v10, v9, 16
-; GCN-NEXT:    v_alignbit_b32 v13, v10, v9, 8
-; GCN-NEXT:    v_alignbit_b32 v14, v8, v7, 24
-; GCN-NEXT:    v_alignbit_b32 v15, v8, v7, 16
-; GCN-NEXT:    v_alignbit_b32 v17, v8, v7, 8
-; GCN-NEXT:    v_alignbit_b32 v20, v6, v5, 24
-; GCN-NEXT:    v_alignbit_b32 v21, v6, v5, 16
-; GCN-NEXT:    v_alignbit_b32 v23, v6, v5, 8
-; GCN-NEXT:    v_alignbit_b32 v26, v4, v3, 24
-; GCN-NEXT:    v_alignbit_b32 v27, v4, v3, 16
-; GCN-NEXT:    v_alignbit_b32 v29, v4, v3, 8
-; GCN-NEXT:    v_alignbit_b32 v32, v2, v1, 24
-; GCN-NEXT:    v_alignbit_b32 v33, v2, v1, 16
-; GCN-NEXT:    v_alignbit_b32 v35, v2, v1, 8
-; GCN-NEXT:    v_lshrrev_b32_e32 v16, 24, v10
-; GCN-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
-; GCN-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
-; GCN-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
-; GCN-NEXT:    v_lshrrev_b32_e32 v24, 16, v8
-; GCN-NEXT:    v_lshrrev_b32_e32 v25, 8, v8
-; GCN-NEXT:    v_lshrrev_b32_e32 v28, 24, v6
-; GCN-NEXT:    v_lshrrev_b32_e32 v30, 16, v6
-; GCN-NEXT:    v_lshrrev_b32_e32 v31, 8, v6
-; GCN-NEXT:    v_lshrrev_b32_e32 v34, 24, v4
-; GCN-NEXT:    v_lshrrev_b32_e32 v36, 16, v4
-; GCN-NEXT:    v_lshrrev_b32_e32 v37, 8, v4
-; GCN-NEXT:    v_lshrrev_b32_e32 v38, 24, v2
-; GCN-NEXT:    v_lshrrev_b32_e32 v39, 16, v2
-; GCN-NEXT:    v_lshrrev_b32_e32 v48, 8, v2
-; GCN-NEXT:  .LBB16_2: ; %Flow
-; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB16_4
-; GCN-NEXT:  ; %bb.3: ; %cmp.true
-; GCN-NEXT:    v_add_f32_e32 v2, 1.0, v2
-; GCN-NEXT:    v_add_f32_e32 v1, 1.0, v1
-; GCN-NEXT:    v_add_f32_e32 v4, 1.0, v4
-; GCN-NEXT:    v_add_f32_e32 v3, 1.0, v3
-; GCN-NEXT:    v_add_f32_e32 v6, 1.0, v6
-; GCN-NEXT:    v_add_f32_e32 v5, 1.0, v5
-; GCN-NEXT:    v_add_f32_e32 v8, 1.0, v8
-; GCN-NEXT:    v_add_f32_e32 v7, 1.0, v7
-; GCN-NEXT:    v_add_f32_e32 v10, 1.0, v10
-; GCN-NEXT:    v_add_f32_e32 v9, 1.0, v9
-; GCN-NEXT:    v_alignbit_b32 v11, v10, v9, 24
-; GCN-NEXT:    v_alignbit_b32 v12, v10, v9, 16
-; GCN-NEXT:    v_alignbit_b32 v13, v10, v9, 8
-; GCN-NEXT:    v_alignbit_b32 v14, v8, v7, 24
-; GCN-NEXT:    v_alignbit_b32 v15, v8, v7, 16
-; GCN-NEXT:    v_alignbit_b32 v17, v8, v7, 8
-; GCN-NEXT:    v_alignbit_b32 v20, v6, v5, 24
-; GCN-NEXT:    v_alignbit_b32 v21, v6, v5, 16
-; GCN-NEXT:    v_alignbit_b32 v23, v6, v5, 8
-; GCN-NEXT:    v_alignbit_b32 v26, v4, v3, 24
-; GCN-NEXT:    v_alignbit_b32 v27, v4, v3, 16
-; GCN-NEXT:    v_alignbit_b32 v29, v4, v3, 8
-; GCN-NEXT:    v_alignbit_b32 v32, v2, v1, 24
-; GCN-NEXT:    v_alignbit_b32 v33, v2, v1, 16
-; GCN-NEXT:    v_alignbit_b32 v35, v2, v1, 8
-; GCN-NEXT:    v_lshrrev_b32_e32 v16, 24, v10
-; GCN-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
-; GCN-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
-; GCN-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
-; GCN-NEXT:    v_lshrrev_b32_e32 v24, 16, v8
-; GCN-NEXT:    v_lshrrev_b32_e32 v25, 8, v8
-; GCN-NEXT:    v_lshrrev_b32_e32 v28, 24, v6
-; GCN-NEXT:    v_lshrrev_b32_e32 v30, 16, v6
-; GCN-NEXT:    v_lshrrev_b32_e32 v31, 8, v6
-; GCN-NEXT:    v_lshrrev_b32_e32 v34, 24, v4
-; GCN-NEXT:    v_lshrrev_b32_e32 v36, 16, v4
-; GCN-NEXT:    v_lshrrev_b32_e32 v37, 8, v4
-; GCN-NEXT:    v_lshrrev_b32_e32 v38, 24, v2
-; GCN-NEXT:    v_lshrrev_b32_e32 v39, 16, v2
-; GCN-NEXT:    v_lshrrev_b32_e32 v48, 8, v2
-; GCN-NEXT:  .LBB16_4: ; %end
-; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GCN-NEXT:    v_and_b32_e32 v49, 0xff, v1
-; GCN-NEXT:    v_lshlrev_b32_e32 v35, 8, v35
-; GCN-NEXT:    v_and_b32_e32 v33, 0xff, v33
-; GCN-NEXT:    v_lshlrev_b32_e32 v32, 24, v32
-; GCN-NEXT:    v_and_b32_e32 v50, 0xff, v2
-; GCN-NEXT:    v_lshlrev_b32_e32 v48, 8, v48
-; GCN-NEXT:    v_and_b32_e32 v39, 0xff, v39
-; GCN-NEXT:    v_lshlrev_b32_e32 v38, 24, v38
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, 4, v0
-; GCN-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GCN-NEXT:    v_lshlrev_b32_e32 v29, 8, v29
-; GCN-NEXT:    v_and_b32_e32 v27, 0xff, v27
-; GCN-NEXT:    v_lshlrev_b32_e32 v26, 24, v26
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, 8, v0
-; GCN-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GCN-NEXT:    v_lshlrev_b32_e32 v37, 8, v37
-; GCN-NEXT:    v_and_b32_e32 v36, 0xff, v36
-; GCN-NEXT:    v_lshlrev_b32_e32 v34, 24, v34
-; GCN-NEXT:    v_add_i32_e32 v51, vcc, 12, v0
-; GCN-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GCN-NEXT:    v_lshlrev_b32_e32 v23, 8, v23
-; GCN-NEXT:    v_and_b32_e32 v21, 0xff, v21
-; GCN-NEXT:    v_lshlrev_b32_e32 v20, 24, v20
-; GCN-NEXT:    v_or_b32_e32 v35, v49, v35
-; GCN-NEXT:    v_add_i32_e32 v49, vcc, 16, v0
-; GCN-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GCN-NEXT:    v_lshlrev_b32_e32 v31, 8, v31
-; GCN-NEXT:    v_and_b32_e32 v30, 0xff, v30
-; GCN-NEXT:    v_lshlrev_b32_e32 v28, 24, v28
-; GCN-NEXT:    v_or_b32_e32 v48, v50, v48
-; GCN-NEXT:    v_add_i32_e32 v50, vcc, 20, v0
-; GCN-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GCN-NEXT:    v_lshlrev_b32_e32 v17, 8, v17
-; GCN-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GCN-NEXT:    v_lshlrev_b32_e32 v14, 24, v14
-; GCN-NEXT:    v_or_b32_e32 v3, v3, v29
-; GCN-NEXT:    v_add_i32_e32 v29, vcc, 24, v0
-; GCN-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GCN-NEXT:    v_lshlrev_b32_e32 v25, 8, v25
-; GCN-NEXT:    v_and_b32_e32 v24, 0xff, v24
-; GCN-NEXT:    v_lshlrev_b32_e32 v22, 24, v22
-; GCN-NEXT:    v_or_b32_e32 v4, v4, v37
-; GCN-NEXT:    v_add_i32_e32 v37, vcc, 28, v0
-; GCN-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GCN-NEXT:    v_lshlrev_b32_e32 v13, 8, v13
-; GCN-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GCN-NEXT:    v_lshlrev_b32_e32 v11, 24, v11
-; GCN-NEXT:    v_or_b32_e32 v5, v5, v23
-; GCN-NEXT:    v_add_i32_e32 v23, vcc, 32, v0
-; GCN-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GCN-NEXT:    v_lshlrev_b32_e32 v19, 8, v19
-; GCN-NEXT:    v_and_b32_e32 v18, 0xff, v18
-; GCN-NEXT:    v_lshlrev_b32_e32 v16, 24, v16
-; GCN-NEXT:    v_or_b32_e32 v6, v6, v31
-; GCN-NEXT:    v_add_i32_e32 v31, vcc, 36, v0
-; GCN-NEXT:    v_lshlrev_b32_e32 v33, 16, v33
-; GCN-NEXT:    v_lshlrev_b32_e32 v39, 16, v39
-; GCN-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
-; GCN-NEXT:    v_lshlrev_b32_e32 v36, 16, v36
-; GCN-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GCN-NEXT:    v_lshlrev_b32_e32 v30, 16, v30
-; GCN-NEXT:    v_or_b32_e32 v7, v7, v17
-; GCN-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GCN-NEXT:    v_or_b32_e32 v8, v8, v25
-; GCN-NEXT:    v_lshlrev_b32_e32 v17, 16, v24
-; GCN-NEXT:    v_or_b32_e32 v9, v9, v13
-; GCN-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GCN-NEXT:    v_or_b32_e32 v10, v10, v19
-; GCN-NEXT:    v_lshlrev_b32_e32 v13, 16, v18
-; GCN-NEXT:    v_and_b32_e32 v18, 0xffff, v35
-; GCN-NEXT:    v_or_b32_e32 v19, v32, v33
-; GCN-NEXT:    v_and_b32_e32 v24, 0xffff, v48
-; GCN-NEXT:    v_or_b32_e32 v25, v38, v39
-; GCN-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GCN-NEXT:    v_or_b32_e32 v26, v26, v27
-; GCN-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GCN-NEXT:    v_or_b32_e32 v27, v34, v36
-; GCN-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GCN-NEXT:    v_or_b32_e32 v20, v20, v21
-; GCN-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GCN-NEXT:    v_or_b32_e32 v21, v28, v30
-; GCN-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GCN-NEXT:    v_or_b32_e32 v14, v14, v15
-; GCN-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GCN-NEXT:    v_or_b32_e32 v15, v22, v17
-; GCN-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GCN-NEXT:    v_or_b32_e32 v11, v11, v12
-; GCN-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GCN-NEXT:    v_or_b32_e32 v12, v16, v13
-; GCN-NEXT:    v_or_b32_e32 v13, v18, v19
-; GCN-NEXT:    v_or_b32_e32 v16, v24, v25
-; GCN-NEXT:    v_or_b32_e32 v3, v3, v26
-; GCN-NEXT:    v_or_b32_e32 v4, v4, v27
-; GCN-NEXT:    v_or_b32_e32 v5, v5, v20
-; GCN-NEXT:    v_or_b32_e32 v6, v6, v21
-; GCN-NEXT:    v_or_b32_e32 v7, v7, v14
-; GCN-NEXT:    v_or_b32_e32 v8, v8, v15
-; GCN-NEXT:    v_or_b32_e32 v9, v9, v11
-; GCN-NEXT:    v_or_b32_e32 v10, v10, v12
-; GCN-NEXT:    buffer_store_dword v13, v0, s[0:3], 0 offen
-; GCN-NEXT:    buffer_store_dword v16, v1, s[0:3], 0 offen
-; GCN-NEXT:    buffer_store_dword v3, v2, s[0:3], 0 offen
-; GCN-NEXT:    buffer_store_dword v4, v51, s[0:3], 0 offen
-; GCN-NEXT:    buffer_store_dword v5, v49, s[0:3], 0 offen
-; GCN-NEXT:    buffer_store_dword v6, v50, s[0:3], 0 offen
-; GCN-NEXT:    buffer_store_dword v7, v29, s[0:3], 0 offen
-; GCN-NEXT:    buffer_store_dword v8, v37, s[0:3], 0 offen
-; GCN-NEXT:    buffer_store_dword v9, v23, s[0:3], 0 offen
-; GCN-NEXT:    buffer_store_dword v10, v31, s[0:3], 0 offen
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; VI-LABEL: bitcast_v10f32_to_v40i8:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
-; VI-NEXT:    ; implicit-def: $vgpr16
-; VI-NEXT:    ; implicit-def: $vgpr48
-; VI-NEXT:    ; implicit-def: $vgpr15
-; VI-NEXT:    ; implicit-def: $vgpr39
-; VI-NEXT:    ; implicit-def: $vgpr38
-; VI-NEXT:    ; implicit-def: $vgpr37
-; VI-NEXT:    ; implicit-def: $vgpr36
-; VI-NEXT:    ; implicit-def: $vgpr35
-; VI-NEXT:    ; implicit-def: $vgpr14
-; VI-NEXT:    ; implicit-def: $vgpr34
-; VI-NEXT:    ; implicit-def: $vgpr33
-; VI-NEXT:    ; implicit-def: $vgpr32
-; VI-NEXT:    ; implicit-def: $vgpr31
-; VI-NEXT:    ; implicit-def: $vgpr30
-; VI-NEXT:    ; implicit-def: $vgpr13
-; VI-NEXT:    ; implicit-def: $vgpr29
-; VI-NEXT:    ; implicit-def: $vgpr28
-; VI-NEXT:    ; implicit-def: $vgpr27
-; VI-NEXT:    ; implicit-def: $vgpr26
-; VI-NEXT:    ; implicit-def: $vgpr25
-; VI-NEXT:    ; implicit-def: $vgpr12
-; VI-NEXT:    ; implicit-def: $vgpr24
-; VI-NEXT:    ; implicit-def: $vgpr23
-; VI-NEXT:    ; implicit-def: $vgpr22
-; VI-NEXT:    ; implicit-def: $vgpr21
-; VI-NEXT:    ; implicit-def: $vgpr20
-; VI-NEXT:    ; implicit-def: $vgpr19
-; VI-NEXT:    ; implicit-def: $vgpr18
-; VI-NEXT:    ; implicit-def: $vgpr17
-; VI-NEXT:    ; implicit-def: $vgpr11
-; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB16_2
-; VI-NEXT:  ; %bb.1: ; %cmp.false
-; VI-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
-; VI-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
-; VI-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
-; VI-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
-; VI-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
-; VI-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
-; VI-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
-; VI-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
-; VI-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
-; VI-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
-; VI-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
-; VI-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
-; VI-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
-; VI-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
-; VI-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
-; VI-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
-; VI-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
-; VI-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
-; VI-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
-; VI-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
-; VI-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
-; VI-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
-; VI-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
-; VI-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
-; VI-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
-; VI-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
-; VI-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
-; VI-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
-; VI-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
-; VI-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; VI-NEXT:  .LBB16_2: ; %Flow
-; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB16_4
-; VI-NEXT:  ; %bb.3: ; %cmp.true
-; VI-NEXT:    v_add_f32_e32 v10, 1.0, v10
-; VI-NEXT:    v_add_f32_e32 v9, 1.0, v9
-; VI-NEXT:    v_add_f32_e32 v8, 1.0, v8
-; VI-NEXT:    v_add_f32_e32 v7, 1.0, v7
-; VI-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
-; VI-NEXT:    v_add_f32_e32 v6, 1.0, v6
-; VI-NEXT:    v_add_f32_e32 v5, 1.0, v5
-; VI-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
-; VI-NEXT:    v_add_f32_e32 v4, 1.0, v4
-; VI-NEXT:    v_add_f32_e32 v3, 1.0, v3
-; VI-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
-; VI-NEXT:    v_add_f32_e32 v2, 1.0, v2
-; VI-NEXT:    v_add_f32_e32 v1, 1.0, v1
-; VI-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
-; VI-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
-; VI-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
-; VI-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
-; VI-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
-; VI-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
-; VI-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
-; VI-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
-; VI-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
-; VI-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
-; VI-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
-; VI-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
-; VI-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
-; VI-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
-; VI-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
-; VI-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
-; VI-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
-; VI-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
-; VI-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
-; VI-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
-; VI-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
-; VI-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
-; VI-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
-; VI-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
-; VI-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
-; VI-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
-; VI-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; VI-NEXT:  .LBB16_4: ; %end
-; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
-; VI-NEXT:    v_lshlrev_b16_e32 v15, 8, v15
-; VI-NEXT:    v_lshlrev_b16_e32 v16, 8, v16
-; VI-NEXT:    v_or_b32_sdwa v15, v48, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v1, v1, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v1, v1, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
-; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v39
-; VI-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v37
-; VI-NEXT:    v_or_b32_sdwa v2, v38, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    v_add_u32_e32 v2, vcc, 4, v0
-; VI-NEXT:    buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v36
-; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v14
-; VI-NEXT:    v_or_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v2, v35, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    v_add_u32_e32 v2, vcc, 8, v0
-; VI-NEXT:    buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v34
-; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v32
-; VI-NEXT:    v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v2, v33, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    v_add_u32_e32 v2, vcc, 12, v0
-; VI-NEXT:    buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v31
-; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v13
-; VI-NEXT:    v_or_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v2, v30, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    v_add_u32_e32 v2, vcc, 16, v0
-; VI-NEXT:    buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v29
-; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v27
-; VI-NEXT:    v_or_b32_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v2, v28, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    v_add_u32_e32 v2, vcc, 20, v0
-; VI-NEXT:    buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v26
-; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v12
-; VI-NEXT:    v_or_b32_sdwa v1, v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v2, v25, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    v_add_u32_e32 v2, vcc, 24, v0
-; VI-NEXT:    buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v24
-; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v22
-; VI-NEXT:    v_or_b32_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v2, v23, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    v_add_u32_e32 v2, vcc, 28, v0
-; VI-NEXT:    buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v21
-; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v11
-; VI-NEXT:    v_or_b32_sdwa v1, v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v2, v20, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    v_add_u32_e32 v2, vcc, 32, v0
-; VI-NEXT:    buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v19
-; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v17
-; VI-NEXT:    v_or_b32_sdwa v1, v10, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v2, v18, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    v_add_u32_e32 v0, vcc, 36, v0
-; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
-; VI-NEXT:    s_waitcnt vmcnt(0)
-; VI-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: bitcast_v10f32_to_v40i8:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
-; GFX9-NEXT:    ; implicit-def: $vgpr16
-; GFX9-NEXT:    ; implicit-def: $vgpr48
-; GFX9-NEXT:    ; implicit-def: $vgpr15
-; GFX9-NEXT:    ; implicit-def: $vgpr39
-; GFX9-NEXT:    ; implicit-def: $vgpr38
-; GFX9-NEXT:    ; implicit-def: $vgpr37
-; GFX9-NEXT:    ; implicit-def: $vgpr36
-; GFX9-NEXT:    ; implicit-def: $vgpr35
-; GFX9-NEXT:    ; implicit-def: $vgpr14
-; GFX9-NEXT:    ; implicit-def: $vgpr34
-; GFX9-NEXT:    ; implicit-def: $vgpr33
-; GFX9-NEXT:    ; implicit-def: $vgpr32
-; GFX9-NEXT:    ; implicit-def: $vgpr31
-; GFX9-NEXT:    ; implicit-def: $vgpr30
-; GFX9-NEXT:    ; implicit-def: $vgpr13
-; GFX9-NEXT:    ; implicit-def: $vgpr29
-; GFX9-NEXT:    ; implicit-def: $vgpr28
-; GFX9-NEXT:    ; implicit-def: $vgpr27
-; GFX9-NEXT:    ; implicit-def: $vgpr26
-; GFX9-NEXT:    ; implicit-def: $vgpr25
-; GFX9-NEXT:    ; implicit-def: $vgpr12
-; GFX9-NEXT:    ; implicit-def: $vgpr24
-; GFX9-NEXT:    ; implicit-def: $vgpr23
-; GFX9-NEXT:    ; implicit-def: $vgpr22
-; GFX9-NEXT:    ; implicit-def: $vgpr21
-; GFX9-NEXT:    ; implicit-def: $vgpr20
-; GFX9-NEXT:    ; implicit-def: $vgpr19
-; GFX9-NEXT:    ; implicit-def: $vgpr18
-; GFX9-NEXT:    ; implicit-def: $vgpr17
-; GFX9-NEXT:    ; implicit-def: $vgpr11
-; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB16_2
-; GFX9-NEXT:  ; %bb.1: ; %cmp.false
-; GFX9-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
-; GFX9-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
-; GFX9-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
-; GFX9-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
-; GFX9-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
-; GFX9-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
-; GFX9-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
-; GFX9-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
-; GFX9-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
-; GFX9-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
-; GFX9-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
-; GFX9-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
-; GFX9-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
-; GFX9-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
-; GFX9-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
-; GFX9-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
-; GFX9-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
-; GFX9-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
-; GFX9-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
-; GFX9-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
-; GFX9-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
-; GFX9-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
-; GFX9-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
-; GFX9-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
-; GFX9-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
-; GFX9-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
-; GFX9-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
-; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
-; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
-; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; GFX9-NEXT:  .LBB16_2: ; %Flow
-; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB16_4
-; GFX9-NEXT:  ; %bb.3: ; %cmp.true
-; GFX9-NEXT:    v_add_f32_e32 v10, 1.0, v10
-; GFX9-NEXT:    v_add_f32_e32 v9, 1.0, v9
-; GFX9-NEXT:    v_add_f32_e32 v8, 1.0, v8
-; GFX9-NEXT:    v_add_f32_e32 v7, 1.0, v7
-; GFX9-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
-; GFX9-NEXT:    v_add_f32_e32 v6, 1.0, v6
-; GFX9-NEXT:    v_add_f32_e32 v5, 1.0, v5
-; GFX9-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
-; GFX9-NEXT:    v_add_f32_e32 v4, 1.0, v4
-; GFX9-NEXT:    v_add_f32_e32 v3, 1.0, v3
-; GFX9-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
-; GFX9-NEXT:    v_add_f32_e32 v2, 1.0, v2
-; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v1
-; GFX9-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
-; GFX9-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
-; GFX9-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
-; GFX9-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
-; GFX9-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
-; GFX9-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
-; GFX9-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
-; GFX9-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
-; GFX9-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
-; GFX9-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
-; GFX9-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
-; GFX9-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
-; GFX9-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
-; GFX9-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
-; GFX9-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
-; GFX9-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
-; GFX9-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
-; GFX9-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
-; GFX9-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
-; GFX9-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
-; GFX9-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
-; GFX9-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
-; GFX9-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
-; GFX9-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
-; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
-; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
-; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; GFX9-NEXT:  .LBB16_4: ; %end
-; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GFX9-NEXT:    v_lshlrev_b16_e32 v15, 8, v15
-; GFX9-NEXT:    v_lshlrev_b16_e32 v16, 8, v16
-; GFX9-NEXT:    v_or_b32_sdwa v15, v48, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
-; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v39
-; GFX9-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_lshlrev_b16_e32 v2, 8, v37
-; GFX9-NEXT:    v_or_b32_sdwa v2, v38, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v36
-; GFX9-NEXT:    v_lshlrev_b16_e32 v2, 8, v14
-; GFX9-NEXT:    v_or_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v2, v35, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
-; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v34
-; GFX9-NEXT:    v_lshlrev_b16_e32 v2, 8, v32
-; GFX9-NEXT:    v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v2, v33, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v31
-; GFX9-NEXT:    v_lshlrev_b16_e32 v2, 8, v13
-; GFX9-NEXT:    v_or_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v2, v30, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
-; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v29
-; GFX9-NEXT:    v_lshlrev_b16_e32 v2, 8, v27
-; GFX9-NEXT:    v_or_b32_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v2, v28, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v26
-; GFX9-NEXT:    v_lshlrev_b16_e32 v2, 8, v12
-; GFX9-NEXT:    v_or_b32_sdwa v1, v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v2, v25, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
-; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v24
-; GFX9-NEXT:    v_lshlrev_b16_e32 v2, 8, v22
-; GFX9-NEXT:    v_or_b32_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v2, v23, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v21
-; GFX9-NEXT:    v_lshlrev_b16_e32 v2, 8, v11
-; GFX9-NEXT:    v_or_b32_sdwa v1, v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v2, v20, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
-; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v19
-; GFX9-NEXT:    v_lshlrev_b16_e32 v2, 8, v17
-; GFX9-NEXT:    v_or_b32_sdwa v1, v10, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v2, v18, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: bitcast_v10f32_to_v40i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB16_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; GFX11-NEXT:  .LBB16_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB16_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v9, 1.0, v9
-; GFX11-NEXT:    v_dual_add_f32 v10, 1.0, v10 :: v_dual_add_f32 v1, 1.0, v1
-; GFX11-NEXT:    v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v7, 1.0, v7
-; GFX11-NEXT:    v_dual_add_f32 v8, 1.0, v8 :: v_dual_add_f32 v3, 1.0, v3
-; GFX11-NEXT:    v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
-; GFX11-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; GFX11-NEXT:  .LBB16_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v16
-; GFX11-NEXT:    v_and_b32_e32 v48, 0xff, v48
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v15
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_lshlrev_b16 v36, 8, v36
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xff, v35
-; GFX11-NEXT:    v_lshlrev_b16 v14, 8, v14
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_lshlrev_b16 v31, 8, v31
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v30
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v13
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v39
-; GFX11-NEXT:    v_and_b32_e32 v38, 0xff, v38
-; GFX11-NEXT:    v_lshlrev_b16 v37, 8, v37
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v16
-; GFX11-NEXT:    v_or_b32_e32 v15, v48, v15
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v36
-; GFX11-NEXT:    v_or_b32_e32 v14, v35, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v31
-; GFX11-NEXT:    v_or_b32_e32 v13, v30, v13
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v39
-; GFX11-NEXT:    v_or_b32_e32 v16, v38, v37
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v15
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v13
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v29
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v28
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v27
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v16
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v26
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_lshlrev_b16 v34, 8, v34
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xff, v33
-; GFX11-NEXT:    v_lshlrev_b16 v32, 8, v32
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v25
-; GFX11-NEXT:    v_lshlrev_b16 v12, 8, v12
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v24
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v13
-; GFX11-NEXT:    v_or_b32_e32 v13, v14, v15
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v23
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v22
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v16
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v21
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v20
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v11
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v19
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v18
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v17
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v34
-; GFX11-NEXT:    v_or_b32_e32 v32, v33, v32
-; GFX11-NEXT:    v_or_b32_e32 v12, v25, v12
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v24
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v16
-; GFX11-NEXT:    v_or_b32_e32 v11, v20, v11
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v19
-; GFX11-NEXT:    v_or_b32_e32 v15, v18, v17
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v30, 16, v32
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v30
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v13
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v12
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v14
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v11
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v15
-; GFX11-NEXT:    s_clause 0x2
-; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off
-; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
-; GFX11-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %cmp = icmp eq i32 %b, 0
-  br i1 %cmp, label %cmp.true, label %cmp.false
-
-cmp.true:
-  %a1 = fadd <10 x float> %a, splat (float 1.000000e+00)
-  %a2 = bitcast <10 x float> %a1 to <40 x i8>
-  br label %end
-
-cmp.false:
-  %a3 = bitcast <10 x float> %a to <40 x i8>
-  br label %end
-
-end:
-  %phi = phi <40 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
-  ret <40 x i8> %phi
-}
-
-define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) {
-; GCN-LABEL: bitcast_v40i8_to_v10f32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GCN-NEXT:    v_mov_b32_e32 v35, v8
-; GCN-NEXT:    v_mov_b32_e32 v34, v6
-; GCN-NEXT:    v_mov_b32_e32 v33, v4
-; GCN-NEXT:    v_mov_b32_e32 v32, v2
-; GCN-NEXT:    v_mov_b32_e32 v31, v0
-; GCN-NEXT:    buffer_load_dword v0, off, s[0:3], s32 offset:32
-; GCN-NEXT:    buffer_load_dword v54, off, s[0:3], s32 offset:28
-; GCN-NEXT:    buffer_load_dword v2, off, s[0:3], s32 offset:24
-; GCN-NEXT:    buffer_load_dword v55, off, s[0:3], s32 offset:20
-; GCN-NEXT:    buffer_load_dword v4, off, s[0:3], s32 offset:16
-; GCN-NEXT:    s_waitcnt expcnt(1)
-; GCN-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:12
-; GCN-NEXT:    buffer_load_dword v6, off, s[0:3], s32 offset:8
-; GCN-NEXT:    s_waitcnt expcnt(0)
-; GCN-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:4
-; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s32
-; GCN-NEXT:    buffer_load_dword v53, off, s[0:3], s32 offset:36
-; GCN-NEXT:    v_lshlrev_b32_e32 v38, 8, v1
-; GCN-NEXT:    v_lshlrev_b32_e32 v36, 24, v3
-; GCN-NEXT:    v_lshlrev_b32_e32 v39, 8, v5
-; GCN-NEXT:    v_lshlrev_b32_e32 v37, 24, v7
-; GCN-NEXT:    v_lshlrev_b32_e32 v48, 8, v9
-; GCN-NEXT:    v_lshlrev_b32_e32 v11, 24, v11
-; GCN-NEXT:    v_lshlrev_b32_e32 v49, 8, v13
-; GCN-NEXT:    v_lshlrev_b32_e32 v13, 24, v15
-; GCN-NEXT:    v_lshlrev_b32_e32 v50, 8, v17
-; GCN-NEXT:    v_lshlrev_b32_e32 v15, 24, v19
-; GCN-NEXT:    v_lshlrev_b32_e32 v51, 8, v21
-; GCN-NEXT:    v_lshlrev_b32_e32 v17, 24, v23
-; GCN-NEXT:    v_lshlrev_b32_e32 v52, 8, v25
-; GCN-NEXT:    v_lshlrev_b32_e32 v19, 24, v27
-; GCN-NEXT:    v_lshlrev_b32_e32 v27, 8, v29
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v53
-; GCN-NEXT:    v_lshlrev_b32_e32 v21, 24, v8
-; GCN-NEXT:    v_lshlrev_b32_e32 v29, 8, v6
-; GCN-NEXT:    v_lshlrev_b32_e32 v23, 24, v4
-; GCN-NEXT:    v_lshlrev_b32_e32 v53, 8, v2
-; GCN-NEXT:    v_lshlrev_b32_e32 v25, 24, v0
-; GCN-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
-; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB17_2
-; GCN-NEXT:  ; %bb.1: ; %cmp.false
-; GCN-NEXT:    v_and_b32_e32 v0, 0xff, v31
-; GCN-NEXT:    v_and_b32_e32 v1, 0xff, v32
-; GCN-NEXT:    v_and_b32_e32 v2, 0xff, v33
-; GCN-NEXT:    v_and_b32_e32 v3, 0xff, v34
-; GCN-NEXT:    v_and_b32_e32 v4, 0xff, v35
-; GCN-NEXT:    v_and_b32_e32 v5, 0xff, v10
-; GCN-NEXT:    v_and_b32_e32 v6, 0xff, v12
-; GCN-NEXT:    v_and_b32_e32 v7, 0xff, v14
-; GCN-NEXT:    v_and_b32_e32 v8, 0xff, v16
-; GCN-NEXT:    v_and_b32_e32 v9, 0xff, v18
-; GCN-NEXT:    v_and_b32_e32 v10, 0xff, v20
-; GCN-NEXT:    v_and_b32_e32 v12, 0xff, v22
-; GCN-NEXT:    v_and_b32_e32 v14, 0xff, v24
-; GCN-NEXT:    v_and_b32_e32 v16, 0xff, v26
-; GCN-NEXT:    v_and_b32_e32 v18, 0xff, v28
-; GCN-NEXT:    v_and_b32_e32 v20, 0xff, v30
-; GCN-NEXT:    v_and_b32_e32 v22, 0xff, v41
-; GCN-NEXT:    v_and_b32_e32 v24, 0xff, v40
-; GCN-NEXT:    v_and_b32_e32 v26, 0xff, v55
-; GCN-NEXT:    v_and_b32_e32 v28, 0xff, v54
-; GCN-NEXT:    v_or_b32_e32 v0, v0, v38
-; GCN-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GCN-NEXT:    v_or_b32_e32 v2, v2, v39
-; GCN-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GCN-NEXT:    v_or_b32_e32 v4, v4, v48
-; GCN-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GCN-NEXT:    v_or_b32_e32 v6, v6, v49
-; GCN-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GCN-NEXT:    v_or_b32_e32 v8, v8, v50
-; GCN-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GCN-NEXT:    v_or_b32_e32 v10, v10, v51
-; GCN-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GCN-NEXT:    v_or_b32_e32 v14, v14, v52
-; GCN-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GCN-NEXT:    v_or_b32_e32 v18, v18, v27
-; GCN-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GCN-NEXT:    v_or_b32_e32 v22, v22, v29
-; GCN-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
-; GCN-NEXT:    v_or_b32_e32 v26, v26, v53
-; GCN-NEXT:    v_lshlrev_b32_e32 v27, 16, v28
-; GCN-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GCN-NEXT:    v_or_b32_e32 v1, v36, v1
-; GCN-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GCN-NEXT:    v_or_b32_e32 v3, v37, v3
-; GCN-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GCN-NEXT:    v_or_b32_e32 v5, v11, v5
-; GCN-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GCN-NEXT:    v_or_b32_e32 v7, v13, v7
-; GCN-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GCN-NEXT:    v_or_b32_e32 v9, v15, v9
-; GCN-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GCN-NEXT:    v_or_b32_e32 v11, v17, v12
-; GCN-NEXT:    v_and_b32_e32 v12, 0xffff, v14
-; GCN-NEXT:    v_or_b32_e32 v13, v19, v16
-; GCN-NEXT:    v_and_b32_e32 v14, 0xffff, v18
-; GCN-NEXT:    v_or_b32_e32 v15, v21, v20
-; GCN-NEXT:    v_and_b32_e32 v16, 0xffff, v22
-; GCN-NEXT:    v_or_b32_e32 v17, v23, v24
-; GCN-NEXT:    v_and_b32_e32 v18, 0xffff, v26
-; GCN-NEXT:    v_or_b32_e32 v19, v25, v27
-; GCN-NEXT:    v_or_b32_e32 v0, v0, v1
-; GCN-NEXT:    v_or_b32_e32 v1, v2, v3
-; GCN-NEXT:    v_or_b32_e32 v2, v4, v5
-; GCN-NEXT:    v_or_b32_e32 v3, v6, v7
-; GCN-NEXT:    v_or_b32_e32 v4, v8, v9
-; GCN-NEXT:    v_or_b32_e32 v5, v10, v11
-; GCN-NEXT:    v_or_b32_e32 v6, v12, v13
-; GCN-NEXT:    v_or_b32_e32 v7, v14, v15
-; GCN-NEXT:    v_or_b32_e32 v8, v16, v17
-; GCN-NEXT:    v_or_b32_e32 v9, v18, v19
-; GCN-NEXT:    ; implicit-def: $vgpr31
-; GCN-NEXT:    ; implicit-def: $vgpr32
-; GCN-NEXT:    ; implicit-def: $vgpr33
-; GCN-NEXT:    ; implicit-def: $vgpr34
-; GCN-NEXT:    ; implicit-def: $vgpr35
-; GCN-NEXT:    ; implicit-def: $vgpr10
-; GCN-NEXT:    ; implicit-def: $vgpr12
-; GCN-NEXT:    ; implicit-def: $vgpr14
-; GCN-NEXT:    ; implicit-def: $vgpr16
-; GCN-NEXT:    ; implicit-def: $vgpr18
-; GCN-NEXT:    ; implicit-def: $vgpr20
-; GCN-NEXT:    ; implicit-def: $vgpr22
-; GCN-NEXT:    ; implicit-def: $vgpr24
-; GCN-NEXT:    ; implicit-def: $vgpr26
-; GCN-NEXT:    ; implicit-def: $vgpr28
-; GCN-NEXT:    ; implicit-def: $vgpr30
-; GCN-NEXT:    ; implicit-def: $vgpr41
-; GCN-NEXT:    ; implicit-def: $vgpr40
-; GCN-NEXT:    ; implicit-def: $vgpr55
-; GCN-NEXT:    ; implicit-def: $vgpr54
-; GCN-NEXT:    ; implicit-def: $vgpr38
-; GCN-NEXT:    ; implicit-def: $vgpr36
-; GCN-NEXT:    ; implicit-def: $vgpr39
-; GCN-NEXT:    ; implicit-def: $vgpr37
-; GCN-NEXT:    ; implicit-def: $vgpr48
-; GCN-NEXT:    ; implicit-def: $vgpr11
-; GCN-NEXT:    ; implicit-def: $vgpr49
-; GCN-NEXT:    ; implicit-def: $vgpr13
-; GCN-NEXT:    ; implicit-def: $vgpr50
-; GCN-NEXT:    ; implicit-def: $vgpr15
-; GCN-NEXT:    ; implicit-def: $vgpr51
-; GCN-NEXT:    ; implicit-def: $vgpr17
-; GCN-NEXT:    ; implicit-def: $vgpr52
-; GCN-NEXT:    ; implicit-def: $vgpr19
-; GCN-NEXT:    ; implicit-def: $vgpr27
-; GCN-NEXT:    ; implicit-def: $vgpr21
-; GCN-NEXT:    ; implicit-def: $vgpr29
-; GCN-NEXT:    ; implicit-def: $vgpr23
-; GCN-NEXT:    ; implicit-def: $vgpr53
-; GCN-NEXT:    ; implicit-def: $vgpr25
-; GCN-NEXT:  .LBB17_2: ; %Flow
-; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB17_4
-; GCN-NEXT:  ; %bb.3: ; %cmp.true
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, 3, v31
-; GCN-NEXT:    s_movk_i32 s6, 0x300
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, 3, v32
-; GCN-NEXT:    s_mov_b32 s7, 0x3000000
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, 3, v33
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, 3, v34
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, 3, v35
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, 3, v10
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, 3, v12
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, 3, v14
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, 3, v16
-; GCN-NEXT:    v_add_i32_e32 v9, vcc, 3, v18
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, 3, v20
-; GCN-NEXT:    v_add_i32_e32 v12, vcc, 3, v22
-; GCN-NEXT:    v_add_i32_e32 v14, vcc, 3, v24
-; GCN-NEXT:    v_add_i32_e32 v16, vcc, 3, v26
-; GCN-NEXT:    v_add_i32_e32 v18, vcc, 3, v28
-; GCN-NEXT:    v_add_i32_e32 v20, vcc, 3, v30
-; GCN-NEXT:    v_add_i32_e32 v22, vcc, 3, v41
-; GCN-NEXT:    v_add_i32_e32 v24, vcc, 3, v40
-; GCN-NEXT:    v_add_i32_e32 v26, vcc, 3, v55
-; GCN-NEXT:    v_add_i32_e32 v28, vcc, 3, v54
-; GCN-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GCN-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GCN-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GCN-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GCN-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GCN-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GCN-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GCN-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GCN-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GCN-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GCN-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GCN-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GCN-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GCN-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GCN-NEXT:    v_and_b32_e32 v18, 0xff, v18
-; GCN-NEXT:    v_and_b32_e32 v20, 0xff, v20
-; GCN-NEXT:    v_and_b32_e32 v22, 0xff, v22
-; GCN-NEXT:    v_and_b32_e32 v24, 0xff, v24
-; GCN-NEXT:    v_and_b32_e32 v26, 0xff, v26
-; GCN-NEXT:    v_and_b32_e32 v28, 0xff, v28
-; GCN-NEXT:    v_or_b32_e32 v0, v38, v0
-; GCN-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GCN-NEXT:    v_or_b32_e32 v2, v39, v2
-; GCN-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GCN-NEXT:    v_or_b32_e32 v4, v48, v4
-; GCN-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GCN-NEXT:    v_or_b32_e32 v6, v49, v6
-; GCN-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GCN-NEXT:    v_or_b32_e32 v8, v50, v8
-; GCN-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GCN-NEXT:    v_or_b32_e32 v10, v51, v10
-; GCN-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GCN-NEXT:    v_or_b32_e32 v14, v52, v14
-; GCN-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GCN-NEXT:    v_or_b32_e32 v18, v27, v18
-; GCN-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GCN-NEXT:    v_or_b32_e32 v22, v29, v22
-; GCN-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
-; GCN-NEXT:    v_or_b32_e32 v26, v53, v26
-; GCN-NEXT:    v_lshlrev_b32_e32 v27, 16, v28
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, 0x300, v0
-; GCN-NEXT:    v_or_b32_e32 v1, v36, v1
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, s6, v2
-; GCN-NEXT:    v_or_b32_e32 v3, v37, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, s6, v4
-; GCN-NEXT:    v_or_b32_e32 v5, v11, v5
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, s6, v6
-; GCN-NEXT:    v_or_b32_e32 v7, v13, v7
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, s6, v8
-; GCN-NEXT:    v_or_b32_e32 v9, v15, v9
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, s6, v10
-; GCN-NEXT:    v_or_b32_e32 v11, v17, v12
-; GCN-NEXT:    v_add_i32_e32 v12, vcc, s6, v14
-; GCN-NEXT:    v_or_b32_e32 v13, v19, v16
-; GCN-NEXT:    v_add_i32_e32 v14, vcc, s6, v18
-; GCN-NEXT:    v_or_b32_e32 v15, v21, v20
-; GCN-NEXT:    v_add_i32_e32 v16, vcc, s6, v22
-; GCN-NEXT:    v_or_b32_e32 v17, v23, v24
-; GCN-NEXT:    v_add_i32_e32 v18, vcc, 0x300, v26
-; GCN-NEXT:    v_or_b32_e32 v19, v25, v27
-; GCN-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GCN-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GCN-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GCN-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GCN-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GCN-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GCN-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GCN-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GCN-NEXT:    v_and_b32_e32 v16, 0xffff, v16
-; GCN-NEXT:    v_and_b32_e32 v18, 0xffff, v18
-; GCN-NEXT:    v_or_b32_e32 v0, v1, v0
-; GCN-NEXT:    v_or_b32_e32 v1, v3, v2
-; GCN-NEXT:    v_or_b32_e32 v2, v5, v4
-; GCN-NEXT:    v_or_b32_e32 v3, v7, v6
-; GCN-NEXT:    v_or_b32_e32 v4, v9, v8
-; GCN-NEXT:    v_or_b32_e32 v5, v11, v10
-; GCN-NEXT:    v_or_b32_e32 v6, v13, v12
-; GCN-NEXT:    v_or_b32_e32 v7, v15, v14
-; GCN-NEXT:    v_or_b32_e32 v8, v17, v16
-; GCN-NEXT:    v_or_b32_e32 v9, v19, v18
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, s7, v0
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, s7, v1
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, s7, v2
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, s7, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, s7, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, s7, v5
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, s7, v6
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, s7, v7
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, 0x3000000, v8
-; GCN-NEXT:    v_add_i32_e32 v9, vcc, 0x3000000, v9
-; GCN-NEXT:  .LBB17_4: ; %end
-; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GCN-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; VI-LABEL: bitcast_v40i8_to_v10f32:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; VI-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; VI-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; VI-NEXT:    buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; VI-NEXT:    buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; VI-NEXT:    v_mov_b32_e32 v35, v8
-; VI-NEXT:    v_mov_b32_e32 v34, v6
-; VI-NEXT:    v_mov_b32_e32 v33, v4
-; VI-NEXT:    v_mov_b32_e32 v32, v2
-; VI-NEXT:    v_mov_b32_e32 v31, v0
-; VI-NEXT:    buffer_load_ushort v0, off, s[0:3], s32 offset:16
-; VI-NEXT:    buffer_load_ushort v2, off, s[0:3], s32 offset:8
-; VI-NEXT:    buffer_load_ushort v4, off, s[0:3], s32
-; VI-NEXT:    buffer_load_dword v6, off, s[0:3], s32 offset:36
-; VI-NEXT:    buffer_load_ushort v8, off, s[0:3], s32 offset:32
-; VI-NEXT:    buffer_load_ushort v36, off, s[0:3], s32 offset:28
-; VI-NEXT:    buffer_load_ushort v44, off, s[0:3], s32 offset:24
-; VI-NEXT:    buffer_load_ushort v37, off, s[0:3], s32 offset:20
-; VI-NEXT:    buffer_load_ushort v38, off, s[0:3], s32 offset:12
-; VI-NEXT:    buffer_load_ushort v39, off, s[0:3], s32 offset:4
-; VI-NEXT:    v_lshlrev_b16_e32 v43, 8, v1
-; VI-NEXT:    v_lshlrev_b16_e32 v42, 8, v3
-; VI-NEXT:    v_lshlrev_b16_e32 v41, 8, v5
-; VI-NEXT:    v_lshlrev_b16_e32 v40, 8, v7
-; VI-NEXT:    v_lshlrev_b16_e32 v55, 8, v9
-; VI-NEXT:    v_lshlrev_b16_e32 v54, 8, v11
-; VI-NEXT:    v_lshlrev_b16_e32 v53, 8, v13
-; VI-NEXT:    v_lshlrev_b16_e32 v52, 8, v15
-; VI-NEXT:    v_lshlrev_b16_e32 v51, 8, v17
-; VI-NEXT:    v_lshlrev_b16_e32 v50, 8, v19
-; VI-NEXT:    v_lshlrev_b16_e32 v49, 8, v21
-; VI-NEXT:    v_lshlrev_b16_e32 v48, 8, v23
-; VI-NEXT:    v_lshlrev_b16_e32 v25, 8, v25
-; VI-NEXT:    v_lshlrev_b16_e32 v23, 8, v27
-; VI-NEXT:    v_lshlrev_b16_e32 v21, 8, v29
-; VI-NEXT:    s_waitcnt vmcnt(9)
-; VI-NEXT:    v_lshlrev_b16_e32 v15, 8, v0
-; VI-NEXT:    s_waitcnt vmcnt(8)
-; VI-NEXT:    v_lshlrev_b16_e32 v17, 8, v2
-; VI-NEXT:    s_waitcnt vmcnt(7)
-; VI-NEXT:    v_lshlrev_b16_e32 v19, 8, v4
-; VI-NEXT:    s_waitcnt vmcnt(6)
-; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
-; VI-NEXT:    s_waitcnt vmcnt(5)
-; VI-NEXT:    v_lshlrev_b16_e32 v11, 8, v8
-; VI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
-; VI-NEXT:    s_waitcnt vmcnt(3)
-; VI-NEXT:    v_lshlrev_b16_e32 v13, 8, v44
-; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB17_2
-; VI-NEXT:  ; %bb.1: ; %cmp.false
-; VI-NEXT:    v_or_b32_sdwa v0, v31, v43 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v1, v32, v42 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v1, v33, v41 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v2, v34, v40 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v2, v35, v55 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v3, v10, v54 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v3, v12, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v4, v14, v52 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v4, v16, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v5, v18, v50 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v5, v20, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v6, v22, v48 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v6, v24, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v7, v26, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v7, v28, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v8, v30, v19 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    s_waitcnt vmcnt(0)
-; VI-NEXT:    v_or_b32_sdwa v8, v39, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v9, v38, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v8, v8, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v9, v37, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v10, v36, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v9, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    ; implicit-def: $vgpr31
-; VI-NEXT:    ; implicit-def: $vgpr32
-; VI-NEXT:    ; implicit-def: $vgpr33
-; VI-NEXT:    ; implicit-def: $vgpr34
-; VI-NEXT:    ; implicit-def: $vgpr35
-; VI-NEXT:    ; implicit-def: $vgpr10
-; VI-NEXT:    ; implicit-def: $vgpr12
-; VI-NEXT:    ; implicit-def: $vgpr14
-; VI-NEXT:    ; implicit-def: $vgpr16
-; VI-NEXT:    ; implicit-def: $vgpr18
-; VI-NEXT:    ; implicit-def: $vgpr20
-; VI-NEXT:    ; implicit-def: $vgpr22
-; VI-NEXT:    ; implicit-def: $vgpr24
-; VI-NEXT:    ; implicit-def: $vgpr26
-; VI-NEXT:    ; implicit-def: $vgpr28
-; VI-NEXT:    ; implicit-def: $vgpr30
-; VI-NEXT:    ; implicit-def: $vgpr39
-; VI-NEXT:    ; implicit-def: $vgpr38
-; VI-NEXT:    ; implicit-def: $vgpr37
-; VI-NEXT:    ; implicit-def: $vgpr36
-; VI-NEXT:    ; implicit-def: $vgpr43
-; VI-NEXT:    ; implicit-def: $vgpr42
-; VI-NEXT:    ; implicit-def: $vgpr41
-; VI-NEXT:    ; implicit-def: $vgpr40
-; VI-NEXT:    ; implicit-def: $vgpr55
-; VI-NEXT:    ; implicit-def: $vgpr54
-; VI-NEXT:    ; implicit-def: $vgpr53
-; VI-NEXT:    ; implicit-def: $vgpr52
-; VI-NEXT:    ; implicit-def: $vgpr51
-; VI-NEXT:    ; implicit-def: $vgpr50
-; VI-NEXT:    ; implicit-def: $vgpr49
-; VI-NEXT:    ; implicit-def: $vgpr48
-; VI-NEXT:    ; implicit-def: $vgpr25
-; VI-NEXT:    ; implicit-def: $vgpr23
-; VI-NEXT:    ; implicit-def: $vgpr21
-; VI-NEXT:    ; implicit-def: $vgpr19
-; VI-NEXT:    ; implicit-def: $vgpr17
-; VI-NEXT:    ; implicit-def: $vgpr15
-; VI-NEXT:    ; implicit-def: $vgpr13
-; VI-NEXT:    ; implicit-def: $vgpr11
-; VI-NEXT:  .LBB17_2: ; %Flow
-; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB17_4
-; VI-NEXT:  ; %bb.3: ; %cmp.true
-; VI-NEXT:    v_add_u16_e32 v0, 3, v31
-; VI-NEXT:    v_add_u16_e32 v1, 3, v32
-; VI-NEXT:    v_or_b32_sdwa v0, v43, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_or_b32_sdwa v1, v42, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_mov_b32_e32 v9, 0x300
-; VI-NEXT:    v_add_u16_e32 v0, 0x300, v0
-; VI-NEXT:    v_add_u16_sdwa v1, v1, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v0, v0, v1
-; VI-NEXT:    v_add_u16_e32 v1, 3, v33
-; VI-NEXT:    v_add_u16_e32 v2, 3, v34
-; VI-NEXT:    v_or_b32_sdwa v1, v41, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_or_b32_sdwa v2, v40, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_add_u16_e32 v1, 0x300, v1
-; VI-NEXT:    v_add_u16_sdwa v2, v2, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v1, v1, v2
-; VI-NEXT:    v_add_u16_e32 v2, 3, v35
-; VI-NEXT:    v_add_u16_e32 v3, 3, v10
-; VI-NEXT:    v_or_b32_sdwa v2, v55, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_or_b32_sdwa v3, v54, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_add_u16_e32 v2, 0x300, v2
-; VI-NEXT:    v_add_u16_sdwa v3, v3, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v2, v2, v3
-; VI-NEXT:    v_add_u16_e32 v3, 3, v12
-; VI-NEXT:    v_add_u16_e32 v4, 3, v14
-; VI-NEXT:    v_or_b32_sdwa v3, v53, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_or_b32_sdwa v4, v52, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_add_u16_e32 v3, 0x300, v3
-; VI-NEXT:    v_add_u16_sdwa v4, v4, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v3, v3, v4
-; VI-NEXT:    v_add_u16_e32 v4, 3, v16
-; VI-NEXT:    v_add_u16_e32 v5, 3, v18
-; VI-NEXT:    v_or_b32_sdwa v4, v51, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_or_b32_sdwa v5, v50, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_add_u16_e32 v4, 0x300, v4
-; VI-NEXT:    v_add_u16_sdwa v5, v5, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v4, v4, v5
-; VI-NEXT:    v_add_u16_e32 v5, 3, v20
-; VI-NEXT:    v_add_u16_e32 v6, 3, v22
-; VI-NEXT:    v_or_b32_sdwa v5, v49, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_or_b32_sdwa v6, v48, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_add_u16_e32 v5, 0x300, v5
-; VI-NEXT:    v_add_u16_sdwa v6, v6, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v5, v5, v6
-; VI-NEXT:    v_add_u16_e32 v6, 3, v24
-; VI-NEXT:    v_add_u16_e32 v7, 3, v26
-; VI-NEXT:    v_or_b32_sdwa v6, v25, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_or_b32_sdwa v7, v23, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_add_u16_e32 v6, 0x300, v6
-; VI-NEXT:    v_add_u16_sdwa v7, v7, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v6, v6, v7
-; VI-NEXT:    v_add_u16_e32 v7, 3, v28
-; VI-NEXT:    v_add_u16_e32 v8, 3, v30
-; VI-NEXT:    v_or_b32_sdwa v7, v21, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_or_b32_sdwa v8, v19, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_add_u16_e32 v7, 0x300, v7
-; VI-NEXT:    v_add_u16_sdwa v8, v8, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v7, v7, v8
-; VI-NEXT:    s_waitcnt vmcnt(0)
-; VI-NEXT:    v_add_u16_e32 v8, 3, v39
-; VI-NEXT:    v_add_u16_e32 v10, 3, v38
-; VI-NEXT:    v_or_b32_sdwa v8, v17, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_or_b32_sdwa v10, v15, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_add_u16_e32 v8, 0x300, v8
-; VI-NEXT:    v_add_u16_sdwa v10, v10, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v8, v8, v10
-; VI-NEXT:    v_add_u16_e32 v10, 3, v37
-; VI-NEXT:    v_add_u16_e32 v12, 3, v36
-; VI-NEXT:    v_or_b32_sdwa v10, v13, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_or_b32_sdwa v11, v11, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_add_u16_e32 v10, 0x300, v10
-; VI-NEXT:    v_add_u16_sdwa v9, v11, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v9, v10, v9
-; VI-NEXT:  .LBB17_4: ; %end
-; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
-; VI-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
-; VI-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
-; VI-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
-; VI-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
-; VI-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
-; VI-NEXT:    s_waitcnt vmcnt(0)
-; VI-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: bitcast_v40i8_to_v10f32:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; GFX9-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; GFX9-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; GFX9-NEXT:    buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT:    buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT:    v_mov_b32_e32 v35, v8
-; GFX9-NEXT:    v_mov_b32_e32 v34, v6
-; GFX9-NEXT:    v_mov_b32_e32 v33, v4
-; GFX9-NEXT:    v_mov_b32_e32 v32, v2
-; GFX9-NEXT:    v_mov_b32_e32 v31, v0
-; GFX9-NEXT:    buffer_load_ushort v0, off, s[0:3], s32 offset:16
-; GFX9-NEXT:    buffer_load_ushort v2, off, s[0:3], s32 offset:8
-; GFX9-NEXT:    buffer_load_ushort v4, off, s[0:3], s32
-; GFX9-NEXT:    buffer_load_dword v6, off, s[0:3], s32 offset:36
-; GFX9-NEXT:    buffer_load_ushort v8, off, s[0:3], s32 offset:32
-; GFX9-NEXT:    buffer_load_ushort v36, off, s[0:3], s32 offset:28
-; GFX9-NEXT:    buffer_load_ushort v44, off, s[0:3], s32 offset:24
-; GFX9-NEXT:    buffer_load_ushort v37, off, s[0:3], s32 offset:20
-; GFX9-NEXT:    buffer_load_ushort v38, off, s[0:3], s32 offset:12
-; GFX9-NEXT:    buffer_load_ushort v39, off, s[0:3], s32 offset:4
-; GFX9-NEXT:    v_lshlrev_b16_e32 v43, 8, v1
-; GFX9-NEXT:    v_lshlrev_b16_e32 v42, 8, v3
-; GFX9-NEXT:    v_lshlrev_b16_e32 v41, 8, v5
-; GFX9-NEXT:    v_lshlrev_b16_e32 v40, 8, v7
-; GFX9-NEXT:    v_lshlrev_b16_e32 v55, 8, v9
-; GFX9-NEXT:    v_lshlrev_b16_e32 v54, 8, v11
-; GFX9-NEXT:    v_lshlrev_b16_e32 v53, 8, v13
-; GFX9-NEXT:    v_lshlrev_b16_e32 v52, 8, v15
-; GFX9-NEXT:    v_lshlrev_b16_e32 v51, 8, v17
-; GFX9-NEXT:    v_lshlrev_b16_e32 v50, 8, v19
-; GFX9-NEXT:    v_lshlrev_b16_e32 v49, 8, v21
-; GFX9-NEXT:    v_lshlrev_b16_e32 v48, 8, v23
-; GFX9-NEXT:    v_lshlrev_b16_e32 v25, 8, v25
-; GFX9-NEXT:    v_lshlrev_b16_e32 v23, 8, v27
-; GFX9-NEXT:    v_lshlrev_b16_e32 v21, 8, v29
-; GFX9-NEXT:    s_waitcnt vmcnt(9)
-; GFX9-NEXT:    v_lshlrev_b16_e32 v15, 8, v0
-; GFX9-NEXT:    s_waitcnt vmcnt(8)
-; GFX9-NEXT:    v_lshlrev_b16_e32 v17, 8, v2
-; GFX9-NEXT:    s_waitcnt vmcnt(7)
-; GFX9-NEXT:    v_lshlrev_b16_e32 v19, 8, v4
-; GFX9-NEXT:    s_waitcnt vmcnt(6)
-; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
-; GFX9-NEXT:    s_waitcnt vmcnt(5)
-; GFX9-NEXT:    v_lshlrev_b16_e32 v11, 8, v8
-; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
-; GFX9-NEXT:    s_waitcnt vmcnt(3)
-; GFX9-NEXT:    v_lshlrev_b16_e32 v13, 8, v44
-; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB17_2
-; GFX9-NEXT:  ; %bb.1: ; %cmp.false
-; GFX9-NEXT:    v_or_b32_sdwa v0, v31, v43 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v1, v32, v42 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v1, v33, v41 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v2, v34, v40 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v2, v35, v55 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v3, v10, v54 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v3, v12, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v4, v14, v52 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v4, v16, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v5, v18, v50 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v5, v20, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v6, v22, v48 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v6, v24, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v7, v26, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v7, v28, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v8, v30, v19 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    v_or_b32_sdwa v8, v39, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v9, v38, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v8, v8, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v9, v37, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v10, v36, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v9, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT:    ; implicit-def: $vgpr31
-; GFX9-NEXT:    ; implicit-def: $vgpr32
-; GFX9-NEXT:    ; implicit-def: $vgpr33
-; GFX9-NEXT:    ; implicit-def: $vgpr34
-; GFX9-NEXT:    ; implicit-def: $vgpr35
-; GFX9-NEXT:    ; implicit-def: $vgpr10
-; GFX9-NEXT:    ; implicit-def: $vgpr12
-; GFX9-NEXT:    ; implicit-def: $vgpr14
-; GFX9-NEXT:    ; implicit-def: $vgpr16
-; GFX9-NEXT:    ; implicit-def: $vgpr18
-; GFX9-NEXT:    ; implicit-def: $vgpr20
-; GFX9-NEXT:    ; implicit-def: $vgpr22
-; GFX9-NEXT:    ; implicit-def: $vgpr24
-; GFX9-NEXT:    ; implicit-def: $vgpr26
-; GFX9-NEXT:    ; implicit-def: $vgpr28
-; GFX9-NEXT:    ; implicit-def: $vgpr30
-; GFX9-NEXT:    ; implicit-def: $vgpr39
-; GFX9-NEXT:    ; implicit-def: $vgpr38
-; GFX9-NEXT:    ; implicit-def: $vgpr37
-; GFX9-NEXT:    ; implicit-def: $vgpr36
-; GFX9-NEXT:    ; implicit-def: $vgpr43
-; GFX9-NEXT:    ; implicit-def: $vgpr42
-; GFX9-NEXT:    ; implicit-def: $vgpr41
-; GFX9-NEXT:    ; implicit-def: $vgpr40
-; GFX9-NEXT:    ; implicit-def: $vgpr55
-; GFX9-NEXT:    ; implicit-def: $vgpr54
-; GFX9-NEXT:    ; implicit-def: $vgpr53
-; GFX9-NEXT:    ; implicit-def: $vgpr52
-; GFX9-NEXT:    ; implicit-def: $vgpr51
-; GFX9-NEXT:    ; implicit-def: $vgpr50
-; GFX9-NEXT:    ; implicit-def: $vgpr49
-; GFX9-NEXT:    ; implicit-def: $vgpr48
-; GFX9-NEXT:    ; implicit-def: $vgpr25
-; GFX9-NEXT:    ; implicit-def: $vgpr23
-; GFX9-NEXT:    ; implicit-def: $vgpr21
-; GFX9-NEXT:    ; implicit-def: $vgpr19
-; GFX9-NEXT:    ; implicit-def: $vgpr17
-; GFX9-NEXT:    ; implicit-def: $vgpr15
-; GFX9-NEXT:    ; implicit-def: $vgpr13
-; GFX9-NEXT:    ; implicit-def: $vgpr11
-; GFX9-NEXT:  .LBB17_2: ; %Flow
-; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB17_4
-; GFX9-NEXT:  ; %bb.3: ; %cmp.true
-; GFX9-NEXT:    v_add_u16_e32 v0, 3, v31
-; GFX9-NEXT:    v_add_u16_e32 v1, 3, v32
-; GFX9-NEXT:    v_or_b32_sdwa v0, v43, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    s_movk_i32 s6, 0x300
-; GFX9-NEXT:    v_or_b32_sdwa v1, v42, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT:    v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX9-NEXT:    v_add_u16_e32 v1, 3, v33
-; GFX9-NEXT:    v_add_u16_e32 v2, 3, v34
-; GFX9-NEXT:    v_or_b32_sdwa v1, v41, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_or_b32_sdwa v2, v40, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT:    v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_e32 v1, v1, v2
-; GFX9-NEXT:    v_add_u16_e32 v2, 3, v35
-; GFX9-NEXT:    v_add_u16_e32 v3, 3, v10
-; GFX9-NEXT:    v_or_b32_sdwa v2, v55, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_or_b32_sdwa v3, v54, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT:    v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_e32 v2, v2, v3
-; GFX9-NEXT:    v_add_u16_e32 v3, 3, v12
-; GFX9-NEXT:    v_add_u16_e32 v4, 3, v14
-; GFX9-NEXT:    v_or_b32_sdwa v3, v53, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_or_b32_sdwa v4, v52, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v3, 0x300, v3
-; GFX9-NEXT:    v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_e32 v3, v3, v4
-; GFX9-NEXT:    v_add_u16_e32 v4, 3, v16
-; GFX9-NEXT:    v_add_u16_e32 v5, 3, v18
-; GFX9-NEXT:    v_or_b32_sdwa v4, v51, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_or_b32_sdwa v5, v50, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v4, 0x300, v4
-; GFX9-NEXT:    v_add_u16_sdwa v5, v5, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_e32 v4, v4, v5
-; GFX9-NEXT:    v_add_u16_e32 v5, 3, v20
-; GFX9-NEXT:    v_add_u16_e32 v6, 3, v22
-; GFX9-NEXT:    v_or_b32_sdwa v5, v49, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_or_b32_sdwa v6, v48, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v5, 0x300, v5
-; GFX9-NEXT:    v_add_u16_sdwa v6, v6, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_e32 v5, v5, v6
-; GFX9-NEXT:    v_add_u16_e32 v6, 3, v24
-; GFX9-NEXT:    v_add_u16_e32 v7, 3, v26
-; GFX9-NEXT:    v_or_b32_sdwa v6, v25, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_or_b32_sdwa v7, v23, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v6, 0x300, v6
-; GFX9-NEXT:    v_add_u16_sdwa v7, v7, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_e32 v6, v6, v7
-; GFX9-NEXT:    v_add_u16_e32 v7, 3, v28
-; GFX9-NEXT:    v_add_u16_e32 v8, 3, v30
-; GFX9-NEXT:    v_or_b32_sdwa v7, v21, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_or_b32_sdwa v8, v19, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v7, 0x300, v7
-; GFX9-NEXT:    v_add_u16_sdwa v8, v8, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_e32 v7, v7, v8
-; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    v_add_u16_e32 v8, 3, v39
-; GFX9-NEXT:    v_add_u16_e32 v9, 3, v38
-; GFX9-NEXT:    v_or_b32_sdwa v8, v17, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_or_b32_sdwa v9, v15, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v8, 0x300, v8
-; GFX9-NEXT:    v_add_u16_sdwa v9, v9, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_e32 v8, v8, v9
-; GFX9-NEXT:    v_add_u16_e32 v9, 3, v37
-; GFX9-NEXT:    v_add_u16_e32 v10, 3, v36
-; GFX9-NEXT:    v_or_b32_sdwa v9, v13, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v9, 0x300, v9
-; GFX9-NEXT:    v_add_u16_sdwa v10, v10, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_e32 v9, v9, v10
-; GFX9-NEXT:  .LBB17_4: ; %end
-; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GFX9-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
-; GFX9-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
-; GFX9-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
-; GFX9-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
-; GFX9-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
-; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: bitcast_v40i8_to_v10f32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v35, v8 :: v_dual_mov_b32 v34, v6
-; GFX11-NEXT:    v_dual_mov_b32 v33, v4 :: v_dual_mov_b32 v32, v2
-; GFX11-NEXT:    v_mov_b32_e32 v31, v0
-; GFX11-NEXT:    s_clause 0x9
-; GFX11-NEXT:    scratch_load_b32 v0, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32
-; GFX11-NEXT:    scratch_load_u16 v4, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_u16 v6, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_u16 v8, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_u16 v66, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_u16 v36, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_u16 v37, off, s32 offset:20
-; GFX11-NEXT:    scratch_load_u16 v38, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_u16 v39, off, s32 offset:4
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v64, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v48, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v49, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v50, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v51, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v52, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v29, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(9)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(8)
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(7)
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v4
-; GFX11-NEXT:    s_waitcnt vmcnt(6)
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v6
-; GFX11-NEXT:    s_waitcnt vmcnt(5)
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v8
-; GFX11-NEXT:    s_waitcnt vmcnt(4)
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v66
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB17_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB17_4
-; GFX11-NEXT:  .LBB17_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB17_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v31
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v34
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v35
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v10
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v18
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v53
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v54
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v55
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v64
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v65
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v48
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v49
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v50
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v51
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v52
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v7
-; GFX11-NEXT:    v_or_b32_e32 v4, v8, v9
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v24
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v26
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v30
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v39
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v38
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v37
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v36
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v21
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v23
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v25
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v27
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v29
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v11, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v12, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v13, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v14, v18, v19
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v8, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v9, v13, v14
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB17_2
-; GFX11-NEXT:  .LBB17_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v31, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v32, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v33, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v34, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v35, 3
-; GFX11-NEXT:    v_add_nc_u16 v5, v10, 3
-; GFX11-NEXT:    v_add_nc_u16 v6, v12, 3
-; GFX11-NEXT:    v_add_nc_u16 v7, v14, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v16, 3
-; GFX11-NEXT:    v_add_nc_u16 v9, v18, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_or_b32_e32 v0, v53, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v54, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v55, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v64, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v65, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v48, v5
-; GFX11-NEXT:    v_or_b32_e32 v6, v49, v6
-; GFX11-NEXT:    v_or_b32_e32 v7, v50, v7
-; GFX11-NEXT:    v_or_b32_e32 v8, v51, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v52, v9
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v7
-; GFX11-NEXT:    v_or_b32_e32 v4, v8, v9
-; GFX11-NEXT:    v_add_nc_u16 v5, v20, 3
-; GFX11-NEXT:    v_add_nc_u16 v6, v22, 3
-; GFX11-NEXT:    v_add_nc_u16 v7, v24, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v26, 3
-; GFX11-NEXT:    v_add_nc_u16 v9, v28, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, v30, 3
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_nc_u16 v12, v39, 3
-; GFX11-NEXT:    v_add_nc_u16 v14, v38, 3
-; GFX11-NEXT:    v_add_nc_u16 v16, v37, 3
-; GFX11-NEXT:    v_add_nc_u16 v18, v36, 3
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v18
-; GFX11-NEXT:    v_or_b32_e32 v5, v21, v5
-; GFX11-NEXT:    v_or_b32_e32 v6, v23, v6
-; GFX11-NEXT:    v_or_b32_e32 v7, v25, v7
-; GFX11-NEXT:    v_or_b32_e32 v8, v27, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v29, v9
-; GFX11-NEXT:    v_or_b32_e32 v10, v11, v10
-; GFX11-NEXT:    v_or_b32_e32 v11, v13, v12
-; GFX11-NEXT:    v_or_b32_e32 v12, v15, v14
-; GFX11-NEXT:    v_or_b32_e32 v13, v17, v16
-; GFX11-NEXT:    v_or_b32_e32 v14, v19, v18
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v10
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v11
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v12
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v13
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v14
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v8, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v9, v13, v14
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %cmp = icmp eq i32 %b, 0
-  br i1 %cmp, label %cmp.true, label %cmp.false
-
-cmp.true:
-  %a1 = add <40 x i8> %a, splat (i8 3)
-  %a2 = bitcast <40 x i8> %a1 to <10 x float>
-  br label %end
-
-cmp.false:
-  %a3 = bitcast <40 x i8> %a to <10 x float>
-  br label %end
-
-end:
-  %phi = phi <10 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
-  ret <10 x float> %phi
-}
-
-define <5 x double> @bitcast_v10f32_to_v5f64(<10 x float> %a, i32 %b) {
-; GCN-LABEL: bitcast_v10f32_to_v5f64:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB18_2
-; GCN-NEXT:  ; %bb.1: ; %cmp.true
-; GCN-NEXT:    v_add_f32_e32 v9, 1.0, v9
-; GCN-NEXT:    v_add_f32_e32 v8, 1.0, v8
-; GCN-NEXT:    v_add_f32_e32 v7, 1.0, v7
-; GCN-NEXT:    v_add_f32_e32 v6, 1.0, v6
-; GCN-NEXT:    v_add_f32_e32 v5, 1.0, v5
-; GCN-NEXT:    v_add_f32_e32 v4, 1.0, v4
-; GCN-NEXT:    v_add_f32_e32 v3, 1.0, v3
-; GCN-NEXT:    v_add_f32_e32 v2, 1.0, v2
-; GCN-NEXT:    v_add_f32_e32 v1, 1.0, v1
-; GCN-NEXT:    v_add_f32_e32 v0, 1.0, v0
-; GCN-NEXT:  .LBB18_2: ; %end
-; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; VI-LABEL: bitcast_v10f32_to_v5f64:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB18_2
-; VI-NEXT:  ; %bb.1: ; %cmp.true
-; VI-NEXT:    v_add_f32_e32 v9, 1.0, v9
-; VI-NEXT:    v_add_f32_e32 v8, 1.0, v8
-; VI-NEXT:    v_add_f32_e32 v7, 1.0, v7
-; VI-NEXT:    v_add_f32_e32 v6, 1.0, v6
-; VI-NEXT:    v_add_f32_e32 v5, 1.0, v5
-; VI-NEXT:    v_add_f32_e32 v4, 1.0, v4
-; VI-NEXT:    v_add_f32_e32 v3, 1.0, v3
-; VI-NEXT:    v_add_f32_e32 v2, 1.0, v2
-; VI-NEXT:    v_add_f32_e32 v1, 1.0, v1
-; VI-NEXT:    v_add_f32_e32 v0, 1.0, v0
-; VI-NEXT:  .LBB18_2: ; %end
-; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
-; VI-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: bitcast_v10f32_to_v5f64:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB18_2
-; GFX9-NEXT:  ; %bb.1: ; %cmp.true
-; GFX9-NEXT:    v_add_f32_e32 v9, 1.0, v9
-; GFX9-NEXT:    v_add_f32_e32 v8, 1.0, v8
-; GFX9-NEXT:    v_add_f32_e32 v7, 1.0, v7
-; GFX9-NEXT:    v_add_f32_e32 v6, 1.0, v6
-; GFX9-NEXT:    v_add_f32_e32 v5, 1.0, v5
-; GFX9-NEXT:    v_add_f32_e32 v4, 1.0, v4
-; GFX9-NEXT:    v_add_f32_e32 v3, 1.0, v3
-; GFX9-NEXT:    v_add_f32_e32 v2, 1.0, v2
-; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v1
-; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v0
-; GFX9-NEXT:  .LBB18_2: ; %end
-; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: bitcast_v10f32_to_v5f64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
-; GFX11-NEXT:    v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
-; GFX11-NEXT:    v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
-; GFX11-NEXT:    v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
-; GFX11-NEXT:    v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-NEXT:  ; %bb.2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %cmp = icmp eq i32 %b, 0
-  br i1 %cmp, label %cmp.true, label %cmp.false
-
-cmp.true:
-  %a1 = fadd <10 x float> %a, splat (float 1.000000e+00)
-  %a2 = bitcast <10 x float> %a1 to <5 x double>
-  br label %end
-
-cmp.false:
-  %a3 = bitcast <10 x float> %a to <5 x double>
-  br label %end
-
-end:
-  %phi = phi <5 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
-  ret <5 x double> %phi
-}
-
-define <10 x float> @bitcast_v5f64_to_v10f32(<5 x double> %a, i32 %b) {
-; GCN-LABEL: bitcast_v5f64_to_v10f32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB19_2
-; GCN-NEXT:  ; %bb.1: ; %cmp.true
-; GCN-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
-; GCN-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
-; GCN-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
-; GCN-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
-; GCN-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
-; GCN-NEXT:  .LBB19_2: ; %end
-; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; VI-LABEL: bitcast_v5f64_to_v10f32:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB19_2
-; VI-NEXT:  ; %bb.1: ; %cmp.true
-; VI-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
-; VI-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
-; VI-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
-; VI-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
-; VI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
-; VI-NEXT:  .LBB19_2: ; %end
-; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
-; VI-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: bitcast_v5f64_to_v10f32:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB19_2
-; GFX9-NEXT:  ; %bb.1: ; %cmp.true
-; GFX9-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
-; GFX9-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
-; GFX9-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
-; GFX9-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
-; GFX9-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
-; GFX9-NEXT:  .LBB19_2: ; %end
-; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: bitcast_v5f64_to_v10f32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB19_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
-; GFX11-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
-; GFX11-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
-; GFX11-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
-; GFX11-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
-; GFX11-NEXT:  .LBB19_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %cmp = icmp eq i32 %b, 0
-  br i1 %cmp, label %cmp.true, label %cmp.false
-
-cmp.true:
-  %a1 = fadd <5 x double> %a, splat (double 1.000000e+00)
-  %a2 = bitcast <5 x double> %a1 to <10 x float>
-  br label %end
-
-cmp.false:
-  %a3 = bitcast <5 x double> %a to <10 x float>
-  br label %end
-
-end:
-  %phi = phi <10 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
-  ret <10 x float> %phi
-}
-
-define <5 x i64> @bitcast_v10f32_to_v5i64(<10 x float> %a, i32 %b) {
-; GCN-LABEL: bitcast_v10f32_to_v5i64:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB20_2
-; GCN-NEXT:  ; %bb.1: ; %cmp.true
-; GCN-NEXT:    v_add_f32_e32 v9, 1.0, v9
-; GCN-NEXT:    v_add_f32_e32 v8, 1.0, v8
-; GCN-NEXT:    v_add_f32_e32 v7, 1.0, v7
-; GCN-NEXT:    v_add_f32_e32 v6, 1.0, v6
-; GCN-NEXT:    v_add_f32_e32 v5, 1.0, v5
-; GCN-NEXT:    v_add_f32_e32 v4, 1.0, v4
-; GCN-NEXT:    v_add_f32_e32 v3, 1.0, v3
-; GCN-NEXT:    v_add_f32_e32 v2, 1.0, v2
-; GCN-NEXT:    v_add_f32_e32 v1, 1.0, v1
-; GCN-NEXT:    v_add_f32_e32 v0, 1.0, v0
-; GCN-NEXT:  .LBB20_2: ; %end
-; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; VI-LABEL: bitcast_v10f32_to_v5i64:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB20_2
-; VI-NEXT:  ; %bb.1: ; %cmp.true
-; VI-NEXT:    v_add_f32_e32 v9, 1.0, v9
-; VI-NEXT:    v_add_f32_e32 v8, 1.0, v8
-; VI-NEXT:    v_add_f32_e32 v7, 1.0, v7
-; VI-NEXT:    v_add_f32_e32 v6, 1.0, v6
-; VI-NEXT:    v_add_f32_e32 v5, 1.0, v5
-; VI-NEXT:    v_add_f32_e32 v4, 1.0, v4
-; VI-NEXT:    v_add_f32_e32 v3, 1.0, v3
-; VI-NEXT:    v_add_f32_e32 v2, 1.0, v2
-; VI-NEXT:    v_add_f32_e32 v1, 1.0, v1
-; VI-NEXT:    v_add_f32_e32 v0, 1.0, v0
-; VI-NEXT:  .LBB20_2: ; %end
-; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
-; VI-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: bitcast_v10f32_to_v5i64:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB20_2
-; GFX9-NEXT:  ; %bb.1: ; %cmp.true
-; GFX9-NEXT:    v_add_f32_e32 v9, 1.0, v9
-; GFX9-NEXT:    v_add_f32_e32 v8, 1.0, v8
-; GFX9-NEXT:    v_add_f32_e32 v7, 1.0, v7
-; GFX9-NEXT:    v_add_f32_e32 v6, 1.0, v6
-; GFX9-NEXT:    v_add_f32_e32 v5, 1.0, v5
-; GFX9-NEXT:    v_add_f32_e32 v4, 1.0, v4
-; GFX9-NEXT:    v_add_f32_e32 v3, 1.0, v3
-; GFX9-NEXT:    v_add_f32_e32 v2, 1.0, v2
-; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v1
-; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v0
-; GFX9-NEXT:  .LBB20_2: ; %end
-; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: bitcast_v10f32_to_v5i64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
-; GFX11-NEXT:    v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
-; GFX11-NEXT:    v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
-; GFX11-NEXT:    v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
-; GFX11-NEXT:    v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-NEXT:  ; %bb.2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %cmp = icmp eq i32 %b, 0
-  br i1 %cmp, label %cmp.true, label %cmp.false
-
-cmp.true:
-  %a1 = fadd <10 x float> %a, splat (float 1.000000e+00)
-  %a2 = bitcast <10 x float> %a1 to <5 x i64>
-  br label %end
-
-cmp.false:
-  %a3 = bitcast <10 x float> %a to <5 x i64>
-  br label %end
-
-end:
-  %phi = phi <5 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
-  ret <5 x i64> %phi
-}
-
-define <10 x float> @bitcast_v5i64_to_v10f32(<5 x i64> %a, i32 %b) {
-; GCN-LABEL: bitcast_v5i64_to_v10f32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB21_2
-; GCN-NEXT:  ; %bb.1: ; %cmp.true
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, 3, v8
-; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, 3, v6
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, 3, v4
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, 3, v2
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, 3, v0
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT:  .LBB21_2: ; %end
-; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; VI-LABEL: bitcast_v5i64_to_v10f32:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB21_2
-; VI-NEXT:  ; %bb.1: ; %cmp.true
-; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v8
-; VI-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
-; VI-NEXT:    v_add_u32_e32 v6, vcc, 3, v6
-; VI-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
-; VI-NEXT:    v_add_u32_e32 v4, vcc, 3, v4
-; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; VI-NEXT:    v_add_u32_e32 v2, vcc, 3, v2
-; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0
-; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT:  .LBB21_2: ; %end
-; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
-; VI-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: bitcast_v5i64_to_v10f32:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB21_2
-; GFX9-NEXT:  ; %bb.1: ; %cmp.true
-; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, 3, v8
-; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, 3, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, 3, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, 3, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 3, v0
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GFX9-NEXT:  .LBB21_2: ; %end
-; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: bitcast_v5i64_to_v10f32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB21_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_add_co_u32 v8, vcc_lo, v8, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v6, vcc_lo, v6, 3
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v4, vcc_lo, v4, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v2, vcc_lo, v2, 3
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, v0, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-NEXT:  .LBB21_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %cmp = icmp eq i32 %b, 0
-  br i1 %cmp, label %cmp.true, label %cmp.false
-
-cmp.true:
-  %a1 = add <5 x i64> %a, splat (i64 3)
-  %a2 = bitcast <5 x i64> %a1 to <10 x float>
-  br label %end
-
-cmp.false:
-  %a3 = bitcast <5 x i64> %a to <10 x float>
-  br label %end
-
-end:
-  %phi = phi <10 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
-  ret <10 x float> %phi
-}
-
-define <20 x half> @bitcast_v20i16_to_v20f16(<20 x i16> %a, i32 %b) {
-; GCN-LABEL: bitcast_v20i16_to_v20f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v39, v19
-; GCN-NEXT:    v_mov_b32_e32 v38, v18
-; GCN-NEXT:    v_mov_b32_e32 v37, v17
-; GCN-NEXT:    v_mov_b32_e32 v36, v16
-; GCN-NEXT:    v_mov_b32_e32 v35, v15
-; GCN-NEXT:    v_mov_b32_e32 v34, v14
-; GCN-NEXT:    v_mov_b32_e32 v33, v13
-; GCN-NEXT:    v_mov_b32_e32 v32, v12
-; GCN-NEXT:    v_mov_b32_e32 v31, v11
-; GCN-NEXT:    v_mov_b32_e32 v30, v10
-; GCN-NEXT:    v_mov_b32_e32 v29, v9
-; GCN-NEXT:    v_mov_b32_e32 v28, v8
-; GCN-NEXT:    v_mov_b32_e32 v27, v7
-; GCN-NEXT:    v_mov_b32_e32 v26, v6
-; GCN-NEXT:    v_mov_b32_e32 v25, v5
-; GCN-NEXT:    v_mov_b32_e32 v24, v4
-; GCN-NEXT:    v_mov_b32_e32 v23, v3
-; GCN-NEXT:    v_mov_b32_e32 v22, v2
-; GCN-NEXT:    v_mov_b32_e32 v21, v1
-; GCN-NEXT:    v_mov_b32_e32 v48, v0
-; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v20
-; GCN-NEXT:    ; implicit-def: $vgpr0
-; GCN-NEXT:    ; implicit-def: $vgpr1
-; GCN-NEXT:    ; implicit-def: $vgpr2
-; GCN-NEXT:    ; implicit-def: $vgpr3
-; GCN-NEXT:    ; implicit-def: $vgpr4
-; GCN-NEXT:    ; implicit-def: $vgpr5
-; GCN-NEXT:    ; implicit-def: $vgpr6
-; GCN-NEXT:    ; implicit-def: $vgpr7
-; GCN-NEXT:    ; implicit-def: $vgpr8
-; GCN-NEXT:    ; implicit-def: $vgpr9
-; GCN-NEXT:    ; implicit-def: $vgpr10
-; GCN-NEXT:    ; implicit-def: $vgpr11
-; GCN-NEXT:    ; implicit-def: $vgpr12
-; GCN-NEXT:    ; implicit-def: $vgpr13
-; GCN-NEXT:    ; implicit-def: $vgpr14
-; GCN-NEXT:    ; implicit-def: $vgpr15
-; GCN-NEXT:    ; implicit-def: $vgpr16
-; GCN-NEXT:    ; implicit-def: $vgpr17
-; GCN-NEXT:    ; implicit-def: $vgpr18
-; GCN-NEXT:    ; implicit-def: $vgpr19
-; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execnz .LBB22_3
-; GCN-NEXT:  ; %bb.1: ; %Flow
-; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execnz .LBB22_4
-; GCN-NEXT:  .LBB22_2: ; %end
-; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-; GCN-NEXT:  .LBB22_3: ; %cmp.false
-; GCN-NEXT:    v_cvt_f32_f16_e32 v0, v48
-; GCN-NEXT:    v_cvt_f32_f16_e32 v1, v21
-; GCN-NEXT:    v_cvt_f32_f16_e32 v2, v22
-; GCN-NEXT:    v_cvt_f32_f16_e32 v3, v23
-; GCN-NEXT:    v_cvt_f32_f16_e32 v4, v24
-; GCN-NEXT:    v_cvt_f32_f16_e32 v5, v25
-; GCN-NEXT:    v_cvt_f32_f16_e32 v6, v26
-; GCN-NEXT:    v_cvt_f32_f16_e32 v7, v27
-; GCN-NEXT:    v_cvt_f32_f16_e32 v8, v28
-; GCN-NEXT:    v_cvt_f32_f16_e32 v9, v29
-; GCN-NEXT:    v_cvt_f32_f16_e32 v10, v30
-; GCN-NEXT:    v_cvt_f32_f16_e32 v11, v31
-; GCN-NEXT:    v_cvt_f32_f16_e32 v12, v32
-; GCN-NEXT:    v_cvt_f32_f16_e32 v13, v33
-; GCN-NEXT:    v_cvt_f32_f16_e32 v14, v34
-; GCN-NEXT:    v_cvt_f32_f16_e32 v15, v35
-; GCN-NEXT:    v_cvt_f32_f16_e32 v16, v36
-; GCN-NEXT:    v_cvt_f32_f16_e32 v17, v37
-; GCN-NEXT:    v_cvt_f32_f16_e32 v18, v38
-; GCN-NEXT:    v_cvt_f32_f16_e32 v19, v39
-; GCN-NEXT:    ; implicit-def: $vgpr48
-; GCN-NEXT:    ; implicit-def: $vgpr21
-; GCN-NEXT:    ; implicit-def: $vgpr22
-; GCN-NEXT:    ; implicit-def: $vgpr23
-; GCN-NEXT:    ; implicit-def: $vgpr24
-; GCN-NEXT:    ; implicit-def: $vgpr25
-; GCN-NEXT:    ; implicit-def: $vgpr26
-; GCN-NEXT:    ; implicit-def: $vgpr27
-; GCN-NEXT:    ; implicit-def: $vgpr28
-; GCN-NEXT:    ; implicit-def: $vgpr29
-; GCN-NEXT:    ; implicit-def: $vgpr30
-; GCN-NEXT:    ; implicit-def: $vgpr31
-; GCN-NEXT:    ; implicit-def: $vgpr32
-; GCN-NEXT:    ; implicit-def: $vgpr33
-; GCN-NEXT:    ; implicit-def: $vgpr34
-; GCN-NEXT:    ; implicit-def: $vgpr35
-; GCN-NEXT:    ; implicit-def: $vgpr36
-; GCN-NEXT:    ; implicit-def: $vgpr37
-; GCN-NEXT:    ; implicit-def: $vgpr38
-; GCN-NEXT:    ; implicit-def: $vgpr39
-; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB22_2
-; GCN-NEXT:  .LBB22_4: ; %cmp.true
-; GCN-NEXT:    v_add_i32_e32 v19, vcc, 3, v39
-; GCN-NEXT:    v_add_i32_e32 v18, vcc, 3, v38
-; GCN-NEXT:    v_add_i32_e32 v17, vcc, 3, v37
-; GCN-NEXT:    v_add_i32_e32 v16, vcc, 3, v36
-; GCN-NEXT:    v_add_i32_e32 v15, vcc, 3, v35
-; GCN-NEXT:    v_add_i32_e32 v14, vcc, 3, v34
-; GCN-NEXT:    v_add_i32_e32 v13, vcc, 3, v33
-; GCN-NEXT:    v_add_i32_e32 v12, vcc, 3, v32
-; GCN-NEXT:    v_add_i32_e32 v11, vcc, 3, v31
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, 3, v30
-; GCN-NEXT:    v_add_i32_e32 v9, vcc, 3, v29
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, 3, v28
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, 3, v27
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, 3, v26
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, 3, v25
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, 3, v24
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, 3, v23
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, 3, v22
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, 3, v21
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, 3, v48
-; GCN-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GCN-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; GCN-NEXT:    v_cvt_f32_f16_e32 v2, v2
-; GCN-NEXT:    v_cvt_f32_f16_e32 v3, v3
-; GCN-NEXT:    v_cvt_f32_f16_e32 v4, v4
-; GCN-NEXT:    v_cvt_f32_f16_e32 v5, v5
-; GCN-NEXT:    v_cvt_f32_f16_e32 v6, v6
-; GCN-NEXT:    v_cvt_f32_f16_e32 v7, v7
-; GCN-NEXT:    v_cvt_f32_f16_e32 v8, v8
-; GCN-NEXT:    v_cvt_f32_f16_e32 v9, v9
-; GCN-NEXT:    v_cvt_f32_f16_e32 v10, v10
-; GCN-NEXT:    v_cvt_f32_f16_e32 v11, v11
-; GCN-NEXT:    v_cvt_f32_f16_e32 v12, v12
-; GCN-NEXT:    v_cvt_f32_f16_e32 v13, v13
-; GCN-NEXT:    v_cvt_f32_f16_e32 v14, v14
-; GCN-NEXT:    v_cvt_f32_f16_e32 v15, v15
-; GCN-NEXT:    v_cvt_f32_f16_e32 v16, v16
-; GCN-NEXT:    v_cvt_f32_f16_e32 v17, v17
-; GCN-NEXT:    v_cvt_f32_f16_e32 v18, v18
-; GCN-NEXT:    v_cvt_f32_f16_e32 v19, v19
-; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; VI-LABEL: bitcast_v20i16_to_v20f16:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB22_2
-; VI-NEXT:  ; %bb.1: ; %cmp.true
-; VI-NEXT:    v_mov_b32_e32 v10, 3
-; VI-NEXT:    v_add_u16_sdwa v11, v0, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_u16_sdwa v12, v1, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_u16_sdwa v13, v2, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_u16_sdwa v14, v3, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_u16_sdwa v15, v4, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_u16_sdwa v16, v5, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_u16_sdwa v17, v6, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_u16_sdwa v18, v7, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_u16_sdwa v19, v8, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_u16_sdwa v10, v9, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_u16_e32 v9, 3, v9
-; VI-NEXT:    v_add_u16_e32 v8, 3, v8
-; VI-NEXT:    v_add_u16_e32 v7, 3, v7
-; VI-NEXT:    v_add_u16_e32 v6, 3, v6
-; VI-NEXT:    v_add_u16_e32 v5, 3, v5
-; VI-NEXT:    v_add_u16_e32 v4, 3, v4
-; VI-NEXT:    v_add_u16_e32 v3, 3, v3
-; VI-NEXT:    v_add_u16_e32 v2, 3, v2
-; VI-NEXT:    v_add_u16_e32 v1, 3, v1
-; VI-NEXT:    v_add_u16_e32 v0, 3, v0
-; VI-NEXT:    v_or_b32_e32 v9, v9, v10
-; VI-NEXT:    v_or_b32_e32 v8, v8, v19
-; VI-NEXT:    v_or_b32_e32 v7, v7, v18
-; VI-NEXT:    v_or_b32_e32 v6, v6, v17
-; VI-NEXT:    v_or_b32_e32 v5, v5, v16
-; VI-NEXT:    v_or_b32_e32 v4, v4, v15
-; VI-NEXT:    v_or_b32_e32 v3, v3, v14
-; VI-NEXT:    v_or_b32_e32 v2, v2, v13
-; VI-NEXT:    v_or_b32_e32 v1, v1, v12
-; VI-NEXT:    v_or_b32_e32 v0, v0, v11
-; VI-NEXT:  .LBB22_2: ; %end
-; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
-; VI-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: bitcast_v20i16_to_v20f16:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB22_2
-; GFX9-NEXT:  ; %bb.1: ; %cmp.true
-; GFX9-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:  .LBB22_2: ; %end
-; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: bitcast_v20i16_to_v20f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB22_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:  .LBB22_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %cmp = icmp eq i32 %b, 0
-  br i1 %cmp, label %cmp.true, label %cmp.false
-
-cmp.true:
-  %a1 = add <20 x i16> %a, splat (i16 3)
-  %a2 = bitcast <20 x i16> %a1 to <20 x half>
-  br label %end
-
-cmp.false:
-  %a3 = bitcast <20 x i16> %a to <20 x half>
-  br label %end
-
-end:
-  %phi = phi <20 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
-  ret <20 x half> %phi
-}
-
-define <20 x i16> @bitcast_v20f16_to_v20i16(<20 x half> %a, i32 %b) {
-; GCN-LABEL: bitcast_v20f16_to_v20i16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v20
-; GCN-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GCN-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GCN-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; GCN-NEXT:    v_cvt_f16_f32_e32 v3, v3
-; GCN-NEXT:    v_cvt_f16_f32_e32 v4, v4
-; GCN-NEXT:    v_cvt_f16_f32_e32 v5, v5
-; GCN-NEXT:    v_cvt_f16_f32_e32 v6, v6
-; GCN-NEXT:    v_cvt_f16_f32_e32 v7, v7
-; GCN-NEXT:    v_cvt_f16_f32_e32 v8, v8
-; GCN-NEXT:    v_cvt_f16_f32_e32 v9, v9
-; GCN-NEXT:    v_cvt_f16_f32_e32 v10, v10
-; GCN-NEXT:    v_cvt_f16_f32_e32 v11, v11
-; GCN-NEXT:    v_cvt_f16_f32_e32 v12, v12
-; GCN-NEXT:    v_cvt_f16_f32_e32 v13, v13
-; GCN-NEXT:    v_cvt_f16_f32_e32 v14, v14
-; GCN-NEXT:    v_cvt_f16_f32_e32 v15, v15
-; GCN-NEXT:    v_cvt_f16_f32_e32 v16, v16
-; GCN-NEXT:    v_cvt_f16_f32_e32 v17, v17
-; GCN-NEXT:    v_cvt_f16_f32_e32 v18, v18
-; GCN-NEXT:    v_cvt_f16_f32_e32 v19, v19
-; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB23_2
-; GCN-NEXT:  ; %bb.1: ; %cmp.true
-; GCN-NEXT:    v_cvt_f32_f16_e32 v19, v19
-; GCN-NEXT:    v_cvt_f32_f16_e32 v18, v18
-; GCN-NEXT:    v_add_f32_e32 v19, 0x38000000, v19
-; GCN-NEXT:    v_add_f32_e32 v18, 0x38000000, v18
-; GCN-NEXT:    v_cvt_f16_f32_e32 v19, v19
-; GCN-NEXT:    v_cvt_f16_f32_e32 v18, v18
-; GCN-NEXT:    v_lshlrev_b32_e32 v20, 16, v19
-; GCN-NEXT:    v_or_b32_e32 v18, v18, v20
-; GCN-NEXT:    v_cvt_f32_f16_e32 v15, v15
-; GCN-NEXT:    v_cvt_f32_f16_e32 v14, v14
-; GCN-NEXT:    v_add_f32_e32 v15, 0x38000000, v15
-; GCN-NEXT:    v_add_f32_e32 v14, 0x38000000, v14
-; GCN-NEXT:    v_cvt_f16_f32_e32 v15, v15
-; GCN-NEXT:    v_cvt_f16_f32_e32 v14, v14
-; GCN-NEXT:    v_lshlrev_b32_e32 v20, 16, v15
-; GCN-NEXT:    v_or_b32_e32 v14, v14, v20
-; GCN-NEXT:    v_cvt_f32_f16_e32 v11, v11
-; GCN-NEXT:    v_cvt_f32_f16_e32 v10, v10
-; GCN-NEXT:    v_add_f32_e32 v11, 0x38000000, v11
-; GCN-NEXT:    v_add_f32_e32 v10, 0x38000000, v10
-; GCN-NEXT:    v_cvt_f16_f32_e32 v11, v11
-; GCN-NEXT:    v_cvt_f16_f32_e32 v10, v10
-; GCN-NEXT:    v_lshlrev_b32_e32 v20, 16, v11
-; GCN-NEXT:    v_or_b32_e32 v10, v10, v20
-; GCN-NEXT:    v_cvt_f32_f16_e32 v7, v7
-; GCN-NEXT:    v_cvt_f32_f16_e32 v6, v6
-; GCN-NEXT:    v_add_f32_e32 v7, 0x38000000, v7
-; GCN-NEXT:    v_add_f32_e32 v6, 0x38000000, v6
-; GCN-NEXT:    v_cvt_f16_f32_e32 v7, v7
-; GCN-NEXT:    v_cvt_f16_f32_e32 v6, v6
-; GCN-NEXT:    v_lshlrev_b32_e32 v20, 16, v7
-; GCN-NEXT:    v_or_b32_e32 v6, v6, v20
-; GCN-NEXT:    v_cvt_f32_f16_e32 v3, v3
-; GCN-NEXT:    v_cvt_f32_f16_e32 v2, v2
-; GCN-NEXT:    v_add_f32_e32 v3, 0x38000000, v3
-; GCN-NEXT:    v_add_f32_e32 v2, 0x38000000, v2
-; GCN-NEXT:    v_cvt_f16_f32_e32 v3, v3
-; GCN-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; GCN-NEXT:    v_lshlrev_b32_e32 v20, 16, v3
-; GCN-NEXT:    v_or_b32_e32 v2, v2, v20
-; GCN-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; GCN-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GCN-NEXT:    v_cvt_f32_f16_e32 v5, v5
-; GCN-NEXT:    v_cvt_f32_f16_e32 v4, v4
-; GCN-NEXT:    v_cvt_f32_f16_e32 v9, v9
-; GCN-NEXT:    v_cvt_f32_f16_e32 v8, v8
-; GCN-NEXT:    v_cvt_f32_f16_e32 v13, v13
-; GCN-NEXT:    v_cvt_f32_f16_e32 v12, v12
-; GCN-NEXT:    v_cvt_f32_f16_e32 v17, v17
-; GCN-NEXT:    v_cvt_f32_f16_e32 v16, v16
-; GCN-NEXT:    v_add_f32_e32 v1, 0x38000000, v1
-; GCN-NEXT:    v_add_f32_e32 v0, 0x38000000, v0
-; GCN-NEXT:    v_add_f32_e32 v5, 0x38000000, v5
-; GCN-NEXT:    v_add_f32_e32 v4, 0x38000000, v4
-; GCN-NEXT:    v_add_f32_e32 v9, 0x38000000, v9
-; GCN-NEXT:    v_add_f32_e32 v8, 0x38000000, v8
-; GCN-NEXT:    v_add_f32_e32 v13, 0x38000000, v13
-; GCN-NEXT:    v_add_f32_e32 v12, 0x38000000, v12
-; GCN-NEXT:    v_add_f32_e32 v17, 0x38000000, v17
-; GCN-NEXT:    v_add_f32_e32 v16, 0x38000000, v16
-; GCN-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GCN-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GCN-NEXT:    v_cvt_f16_f32_e32 v5, v5
-; GCN-NEXT:    v_cvt_f16_f32_e32 v4, v4
-; GCN-NEXT:    v_cvt_f16_f32_e32 v9, v9
-; GCN-NEXT:    v_cvt_f16_f32_e32 v8, v8
-; GCN-NEXT:    v_cvt_f16_f32_e32 v13, v13
-; GCN-NEXT:    v_cvt_f16_f32_e32 v12, v12
-; GCN-NEXT:    v_cvt_f16_f32_e32 v17, v17
-; GCN-NEXT:    v_cvt_f16_f32_e32 v16, v16
-; GCN-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GCN-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GCN-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GCN-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GCN-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GCN-NEXT:    v_or_b32_e32 v0, v0, v1
-; GCN-NEXT:    v_or_b32_e32 v4, v4, v5
-; GCN-NEXT:    v_or_b32_e32 v8, v8, v9
-; GCN-NEXT:    v_or_b32_e32 v12, v12, v13
-; GCN-NEXT:    v_or_b32_e32 v16, v16, v17
-; GCN-NEXT:    v_alignbit_b32 v1, v2, v1, 16
-; GCN-NEXT:    v_alignbit_b32 v5, v6, v5, 16
-; GCN-NEXT:    v_alignbit_b32 v9, v10, v9, 16
-; GCN-NEXT:    v_alignbit_b32 v13, v14, v13, 16
-; GCN-NEXT:    v_alignbit_b32 v17, v18, v17, 16
-; GCN-NEXT:  .LBB23_2: ; %end
-; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-;
-; VI-LABEL: bitcast_v20f16_to_v20i16:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB23_2
-; VI-NEXT:  ; %bb.1: ; %cmp.true
-; VI-NEXT:    v_mov_b32_e32 v11, 0x200
-; VI-NEXT:    v_add_f16_e32 v10, 0x200, v0
-; VI-NEXT:    v_add_f16_sdwa v0, v0, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_f16_e32 v12, 0x200, v1
-; VI-NEXT:    v_add_f16_sdwa v1, v1, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_f16_e32 v13, 0x200, v2
-; VI-NEXT:    v_add_f16_sdwa v2, v2, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_f16_e32 v14, 0x200, v3
-; VI-NEXT:    v_add_f16_sdwa v3, v3, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_f16_e32 v15, 0x200, v4
-; VI-NEXT:    v_add_f16_sdwa v4, v4, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_f16_e32 v16, 0x200, v5
-; VI-NEXT:    v_add_f16_sdwa v5, v5, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_f16_e32 v17, 0x200, v6
-; VI-NEXT:    v_add_f16_sdwa v6, v6, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_f16_e32 v18, 0x200, v7
-; VI-NEXT:    v_add_f16_sdwa v7, v7, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_f16_e32 v19, 0x200, v8
-; VI-NEXT:    v_add_f16_sdwa v8, v8, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_f16_sdwa v11, v9, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_f16_e32 v9, 0x200, v9
-; VI-NEXT:    v_or_b32_e32 v9, v9, v11
-; VI-NEXT:    v_or_b32_e32 v8, v19, v8
-; VI-NEXT:    v_or_b32_e32 v7, v18, v7
-; VI-NEXT:    v_or_b32_e32 v6, v17, v6
-; VI-NEXT:    v_or_b32_e32 v5, v16, v5
-; VI-NEXT:    v_or_b32_e32 v4, v15, v4
-; VI-NEXT:    v_or_b32_e32 v3, v14, v3
-; VI-NEXT:    v_or_b32_e32 v2, v13, v2
-; VI-NEXT:    v_or_b32_e32 v1, v12, v1
-; VI-NEXT:    v_or_b32_e32 v0, v10, v0
-; VI-NEXT:  .LBB23_2: ; %end
-; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
-; VI-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: bitcast_v20f16_to_v20i16:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB23_2
-; GFX9-NEXT:  ; %bb.1: ; %cmp.true
-; GFX9-NEXT:    s_movk_i32 s6, 0x200
-; GFX9-NEXT:    v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
-; GFX9-NEXT:  .LBB23_2: ; %end
-; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: bitcast_v20f16_to_v20i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v10
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB23_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
-; GFX11-NEXT:  .LBB23_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %cmp = icmp eq i32 %b, 0
-  br i1 %cmp, label %cmp.true, label %cmp.false
-
-cmp.true:
-  %a1 = fadd <20 x half> %a, splat (half 0xH0200)
-  %a2 = bitcast <20 x half> %a1 to <20 x i16>
-  br label %end
-
-cmp.false:
-  %a3 = bitcast <20 x half> %a to <20 x i16>
-  br label %end
-
-end:
-  %phi = phi <20 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
-  ret <20 x i16> %phi
-}
-
-define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) {
-; GCN-LABEL: bitcast_v20i16_to_v40i8:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v21
-; GCN-NEXT:    v_lshlrev_b32_e32 v56, 16, v2
-; GCN-NEXT:    s_waitcnt expcnt(6)
-; GCN-NEXT:    v_lshlrev_b32_e32 v57, 16, v4
-; GCN-NEXT:    s_waitcnt expcnt(5)
-; GCN-NEXT:    v_lshlrev_b32_e32 v58, 16, v6
-; GCN-NEXT:    s_waitcnt expcnt(4)
-; GCN-NEXT:    v_lshlrev_b32_e32 v59, 16, v8
-; GCN-NEXT:    s_waitcnt expcnt(3)
-; GCN-NEXT:    v_lshlrev_b32_e32 v60, 16, v10
-; GCN-NEXT:    s_waitcnt expcnt(2)
-; GCN-NEXT:    v_lshlrev_b32_e32 v61, 16, v12
-; GCN-NEXT:    s_waitcnt expcnt(1)
-; GCN-NEXT:    v_lshlrev_b32_e32 v62, 16, v14
-; GCN-NEXT:    s_waitcnt expcnt(0)
-; GCN-NEXT:    v_lshlrev_b32_e32 v63, 16, v16
-; GCN-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GCN-NEXT:    v_lshlrev_b32_e32 v22, 16, v20
-; GCN-NEXT:    ; implicit-def: $vgpr50
-; GCN-NEXT:    ; implicit-def: $vgpr44
-; GCN-NEXT:    ; implicit-def: $vgpr43
-; GCN-NEXT:    ; implicit-def: $vgpr41
-; GCN-NEXT:    ; implicit-def: $vgpr39
-; GCN-NEXT:    ; implicit-def: $vgpr47
-; GCN-NEXT:    ; implicit-def: $vgpr51
-; GCN-NEXT:    ; implicit-def: $vgpr54
+; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
+; GCN-NEXT:    ; implicit-def: $vgpr35
+; GCN-NEXT:    ; implicit-def: $vgpr33
 ; GCN-NEXT:    ; implicit-def: $vgpr32
-; GCN-NEXT:    ; implicit-def: $vgpr42
-; GCN-NEXT:    ; implicit-def: $vgpr55
-; GCN-NEXT:    ; implicit-def: $vgpr53
-; GCN-NEXT:    ; implicit-def: $vgpr28
-; GCN-NEXT:    ; implicit-def: $vgpr46
-; GCN-NEXT:    ; implicit-def: $vgpr34
-; GCN-NEXT:    ; implicit-def: $vgpr36
-; GCN-NEXT:    ; implicit-def: $vgpr23
-; GCN-NEXT:    ; implicit-def: $vgpr52
 ; GCN-NEXT:    ; implicit-def: $vgpr48
+; GCN-NEXT:    ; implicit-def: $vgpr39
+; GCN-NEXT:    ; implicit-def: $vgpr38
+; GCN-NEXT:    ; implicit-def: $vgpr29
+; GCN-NEXT:    ; implicit-def: $vgpr27
+; GCN-NEXT:    ; implicit-def: $vgpr26
 ; GCN-NEXT:    ; implicit-def: $vgpr37
+; GCN-NEXT:    ; implicit-def: $vgpr36
+; GCN-NEXT:    ; implicit-def: $vgpr34
+; GCN-NEXT:    ; implicit-def: $vgpr23
 ; GCN-NEXT:    ; implicit-def: $vgpr21
-; GCN-NEXT:    ; implicit-def: $vgpr45
-; GCN-NEXT:    ; implicit-def: $vgpr26
-; GCN-NEXT:    ; implicit-def: $vgpr29
-; GCN-NEXT:    ; implicit-def: $vgpr14
-; GCN-NEXT:    ; implicit-def: $vgpr35
-; GCN-NEXT:    ; implicit-def: $vgpr33
+; GCN-NEXT:    ; implicit-def: $vgpr20
 ; GCN-NEXT:    ; implicit-def: $vgpr31
-; GCN-NEXT:    ; implicit-def: $vgpr10
-; GCN-NEXT:    ; implicit-def: $vgpr40
-; GCN-NEXT:    ; implicit-def: $vgpr2
-; GCN-NEXT:    ; kill: killed $vgpr2
-; GCN-NEXT:    ; implicit-def: $vgpr24
-; GCN-NEXT:    ; implicit-def: $vgpr6
 ; GCN-NEXT:    ; implicit-def: $vgpr30
-; GCN-NEXT:    ; implicit-def: $vgpr27
+; GCN-NEXT:    ; implicit-def: $vgpr28
+; GCN-NEXT:    ; implicit-def: $vgpr17
+; GCN-NEXT:    ; implicit-def: $vgpr15
+; GCN-NEXT:    ; implicit-def: $vgpr14
 ; GCN-NEXT:    ; implicit-def: $vgpr25
-; GCN-NEXT:    ; implicit-def: $vgpr2
-; GCN-NEXT:    ; implicit-def: $vgpr49
-; GCN-NEXT:    ; implicit-def: $vgpr38
-; GCN-NEXT:    ; kill: killed $vgpr38
-; GCN-NEXT:    ; implicit-def: $vgpr38
-; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB24_2
-; GCN-NEXT:  ; %bb.1: ; %cmp.false
-; GCN-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GCN-NEXT:    v_and_b32_e32 v2, 0xffff, v3
-; GCN-NEXT:    v_and_b32_e32 v3, 0xffff, v5
-; GCN-NEXT:    v_and_b32_e32 v5, 0xffff, v7
-; GCN-NEXT:    v_and_b32_e32 v6, 0xffff, v9
-; GCN-NEXT:    v_and_b32_e32 v7, 0xffff, v11
-; GCN-NEXT:    v_and_b32_e32 v9, 0xffff, v13
-; GCN-NEXT:    v_and_b32_e32 v10, 0xffff, v15
-; GCN-NEXT:    v_and_b32_e32 v11, 0xffff, v17
-; GCN-NEXT:    v_and_b32_e32 v13, 0xffff, v19
-; GCN-NEXT:    v_and_b32_e32 v51, 0xffff, v4
-; GCN-NEXT:    v_and_b32_e32 v34, 0xffff, v8
-; GCN-NEXT:    v_and_b32_e32 v26, 0xffff, v12
-; GCN-NEXT:    v_and_b32_e32 v14, 0xffff, v16
-; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; GCN-NEXT:    s_waitcnt expcnt(0)
-; GCN-NEXT:    v_and_b32_e32 v14, 0xffff, v20
-; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; GCN-NEXT:    v_bfe_u32 v54, v4, 8, 8
-; GCN-NEXT:    v_bfe_u32 v36, v8, 8, 8
-; GCN-NEXT:    v_bfe_u32 v29, v12, 8, 8
-; GCN-NEXT:    v_bfe_u32 v24, v16, 8, 8
-; GCN-NEXT:    v_or_b32_e32 v50, v1, v56
-; GCN-NEXT:    v_or_b32_e32 v39, v2, v57
-; GCN-NEXT:    v_or_b32_e32 v32, v3, v58
-; GCN-NEXT:    v_or_b32_e32 v28, v5, v59
-; GCN-NEXT:    v_or_b32_e32 v23, v6, v60
-; GCN-NEXT:    v_or_b32_e32 v21, v7, v61
-; GCN-NEXT:    s_waitcnt expcnt(0)
-; GCN-NEXT:    v_or_b32_e32 v14, v9, v62
-; GCN-NEXT:    v_or_b32_e32 v10, v10, v63
-; GCN-NEXT:    v_or_b32_e32 v6, v11, v18
-; GCN-NEXT:    v_or_b32_e32 v2, v13, v22
-; GCN-NEXT:    v_alignbit_b32 v41, v39, v50, 24
-; GCN-NEXT:    v_alignbit_b32 v43, v39, v50, 16
-; GCN-NEXT:    v_alignbit_b32 v44, v39, v50, 8
-; GCN-NEXT:    v_alignbit_b32 v53, v28, v32, 24
-; GCN-NEXT:    v_alignbit_b32 v55, v28, v32, 16
-; GCN-NEXT:    v_alignbit_b32 v42, v28, v32, 8
-; GCN-NEXT:    v_alignbit_b32 v37, v21, v23, 24
-; GCN-NEXT:    v_alignbit_b32 v48, v21, v23, 16
-; GCN-NEXT:    v_alignbit_b32 v52, v21, v23, 8
-; GCN-NEXT:    v_alignbit_b32 v31, v10, v14, 24
-; GCN-NEXT:    v_alignbit_b32 v33, v10, v14, 16
-; GCN-NEXT:    v_alignbit_b32 v35, v10, v14, 8
-; GCN-NEXT:    v_alignbit_b32 v25, v2, v6, 24
-; GCN-NEXT:    v_alignbit_b32 v27, v2, v6, 16
-; GCN-NEXT:    v_alignbit_b32 v30, v2, v6, 8
-; GCN-NEXT:    v_lshrrev_b32_e32 v47, 8, v39
-; GCN-NEXT:    v_lshrrev_b32_e32 v46, 8, v28
-; GCN-NEXT:    v_lshrrev_b32_e32 v45, 8, v21
-; GCN-NEXT:    v_lshrrev_b32_e32 v40, 8, v10
-; GCN-NEXT:    v_lshrrev_b32_e32 v49, 8, v2
-; GCN-NEXT:    v_bfe_u32 v38, v20, 8, 8
-; GCN-NEXT:    ; implicit-def: $vgpr1
-; GCN-NEXT:    ; implicit-def: $vgpr3
-; GCN-NEXT:    ; implicit-def: $vgpr5
-; GCN-NEXT:    ; implicit-def: $vgpr7
-; GCN-NEXT:    ; implicit-def: $vgpr9
-; GCN-NEXT:    ; implicit-def: $vgpr11
+; GCN-NEXT:    ; implicit-def: $vgpr24
+; GCN-NEXT:    ; implicit-def: $vgpr22
 ; GCN-NEXT:    ; implicit-def: $vgpr13
-; GCN-NEXT:    ; implicit-def: $vgpr15
-; GCN-NEXT:    ; implicit-def: $vgpr17
+; GCN-NEXT:    ; implicit-def: $vgpr12
+; GCN-NEXT:    ; implicit-def: $vgpr11
 ; GCN-NEXT:    ; implicit-def: $vgpr19
-; GCN-NEXT:    ; implicit-def: $vgpr56
-; GCN-NEXT:    ; implicit-def: $vgpr57
-; GCN-NEXT:    ; implicit-def: $vgpr58
-; GCN-NEXT:    ; implicit-def: $vgpr59
-; GCN-NEXT:    ; implicit-def: $vgpr60
-; GCN-NEXT:    ; implicit-def: $vgpr61
-; GCN-NEXT:    ; implicit-def: $vgpr62
-; GCN-NEXT:    ; implicit-def: $vgpr63
 ; GCN-NEXT:    ; implicit-def: $vgpr18
-; GCN-NEXT:    ; implicit-def: $vgpr22
-; GCN-NEXT:  .LBB24_2: ; %Flow
+; GCN-NEXT:    ; implicit-def: $vgpr16
+; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
+; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
+; GCN-NEXT:    s_cbranch_execz .LBB12_2
+; GCN-NEXT:  ; %bb.1: ; %cmp.false
+; GCN-NEXT:    v_alignbit_b32 v11, v10, v9, 24
+; GCN-NEXT:    v_alignbit_b32 v12, v10, v9, 16
+; GCN-NEXT:    v_alignbit_b32 v13, v10, v9, 8
+; GCN-NEXT:    v_alignbit_b32 v14, v8, v7, 24
+; GCN-NEXT:    v_alignbit_b32 v15, v8, v7, 16
+; GCN-NEXT:    v_alignbit_b32 v17, v8, v7, 8
+; GCN-NEXT:    v_alignbit_b32 v20, v6, v5, 24
+; GCN-NEXT:    v_alignbit_b32 v21, v6, v5, 16
+; GCN-NEXT:    v_alignbit_b32 v23, v6, v5, 8
+; GCN-NEXT:    v_alignbit_b32 v26, v4, v3, 24
+; GCN-NEXT:    v_alignbit_b32 v27, v4, v3, 16
+; GCN-NEXT:    v_alignbit_b32 v29, v4, v3, 8
+; GCN-NEXT:    v_alignbit_b32 v32, v2, v1, 24
+; GCN-NEXT:    v_alignbit_b32 v33, v2, v1, 16
+; GCN-NEXT:    v_alignbit_b32 v35, v2, v1, 8
+; GCN-NEXT:    v_lshrrev_b32_e32 v16, 24, v10
+; GCN-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
+; GCN-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
+; GCN-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
+; GCN-NEXT:    v_lshrrev_b32_e32 v24, 16, v8
+; GCN-NEXT:    v_lshrrev_b32_e32 v25, 8, v8
+; GCN-NEXT:    v_lshrrev_b32_e32 v28, 24, v6
+; GCN-NEXT:    v_lshrrev_b32_e32 v30, 16, v6
+; GCN-NEXT:    v_lshrrev_b32_e32 v31, 8, v6
+; GCN-NEXT:    v_lshrrev_b32_e32 v34, 24, v4
+; GCN-NEXT:    v_lshrrev_b32_e32 v36, 16, v4
+; GCN-NEXT:    v_lshrrev_b32_e32 v37, 8, v4
+; GCN-NEXT:    v_lshrrev_b32_e32 v38, 24, v2
+; GCN-NEXT:    v_lshrrev_b32_e32 v39, 16, v2
+; GCN-NEXT:    v_lshrrev_b32_e32 v48, 8, v2
+; GCN-NEXT:  .LBB12_2: ; %Flow
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB24_4
+; GCN-NEXT:    s_cbranch_execz .LBB12_4
 ; GCN-NEXT:  ; %bb.3: ; %cmp.true
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, 3, v17
-; GCN-NEXT:    s_mov_b32 s6, 0x30000
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, 3, v19
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, 3, v13
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, 3, v15
-; GCN-NEXT:    v_add_i32_e32 v9, vcc, 3, v9
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, 3, v11
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, 3, v5
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, 3, v7
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, 3, v1
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, 3, v3
-; GCN-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GCN-NEXT:    v_add_f32_e32 v2, 1.0, v2
+; GCN-NEXT:    v_add_f32_e32 v1, 1.0, v1
+; GCN-NEXT:    v_add_f32_e32 v4, 1.0, v4
+; GCN-NEXT:    v_add_f32_e32 v3, 1.0, v3
+; GCN-NEXT:    v_add_f32_e32 v6, 1.0, v6
+; GCN-NEXT:    v_add_f32_e32 v5, 1.0, v5
+; GCN-NEXT:    v_add_f32_e32 v8, 1.0, v8
+; GCN-NEXT:    v_add_f32_e32 v7, 1.0, v7
+; GCN-NEXT:    v_add_f32_e32 v10, 1.0, v10
+; GCN-NEXT:    v_add_f32_e32 v9, 1.0, v9
+; GCN-NEXT:    v_alignbit_b32 v11, v10, v9, 24
+; GCN-NEXT:    v_alignbit_b32 v12, v10, v9, 16
+; GCN-NEXT:    v_alignbit_b32 v13, v10, v9, 8
+; GCN-NEXT:    v_alignbit_b32 v14, v8, v7, 24
+; GCN-NEXT:    v_alignbit_b32 v15, v8, v7, 16
+; GCN-NEXT:    v_alignbit_b32 v17, v8, v7, 8
+; GCN-NEXT:    v_alignbit_b32 v20, v6, v5, 24
+; GCN-NEXT:    v_alignbit_b32 v21, v6, v5, 16
+; GCN-NEXT:    v_alignbit_b32 v23, v6, v5, 8
+; GCN-NEXT:    v_alignbit_b32 v26, v4, v3, 24
+; GCN-NEXT:    v_alignbit_b32 v27, v4, v3, 16
+; GCN-NEXT:    v_alignbit_b32 v29, v4, v3, 8
+; GCN-NEXT:    v_alignbit_b32 v32, v2, v1, 24
+; GCN-NEXT:    v_alignbit_b32 v33, v2, v1, 16
+; GCN-NEXT:    v_alignbit_b32 v35, v2, v1, 8
+; GCN-NEXT:    v_lshrrev_b32_e32 v16, 24, v10
+; GCN-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
+; GCN-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
+; GCN-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
+; GCN-NEXT:    v_lshrrev_b32_e32 v24, 16, v8
+; GCN-NEXT:    v_lshrrev_b32_e32 v25, 8, v8
+; GCN-NEXT:    v_lshrrev_b32_e32 v28, 24, v6
+; GCN-NEXT:    v_lshrrev_b32_e32 v30, 16, v6
+; GCN-NEXT:    v_lshrrev_b32_e32 v31, 8, v6
+; GCN-NEXT:    v_lshrrev_b32_e32 v34, 24, v4
+; GCN-NEXT:    v_lshrrev_b32_e32 v36, 16, v4
+; GCN-NEXT:    v_lshrrev_b32_e32 v37, 8, v4
+; GCN-NEXT:    v_lshrrev_b32_e32 v38, 24, v2
+; GCN-NEXT:    v_lshrrev_b32_e32 v39, 16, v2
+; GCN-NEXT:    v_lshrrev_b32_e32 v48, 8, v2
+; GCN-NEXT:  .LBB12_4: ; %end
+; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
+; GCN-NEXT:    v_and_b32_e32 v49, 0xff, v1
+; GCN-NEXT:    v_lshlrev_b32_e32 v35, 8, v35
+; GCN-NEXT:    v_and_b32_e32 v33, 0xff, v33
+; GCN-NEXT:    v_lshlrev_b32_e32 v32, 24, v32
+; GCN-NEXT:    v_and_b32_e32 v50, 0xff, v2
+; GCN-NEXT:    v_lshlrev_b32_e32 v48, 8, v48
+; GCN-NEXT:    v_and_b32_e32 v39, 0xff, v39
+; GCN-NEXT:    v_lshlrev_b32_e32 v38, 24, v38
+; GCN-NEXT:    v_add_i32_e32 v1, vcc, 4, v0
+; GCN-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GCN-NEXT:    v_lshlrev_b32_e32 v29, 8, v29
+; GCN-NEXT:    v_and_b32_e32 v27, 0xff, v27
+; GCN-NEXT:    v_lshlrev_b32_e32 v26, 24, v26
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, 8, v0
+; GCN-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GCN-NEXT:    v_lshlrev_b32_e32 v37, 8, v37
+; GCN-NEXT:    v_and_b32_e32 v36, 0xff, v36
+; GCN-NEXT:    v_lshlrev_b32_e32 v34, 24, v34
+; GCN-NEXT:    v_add_i32_e32 v51, vcc, 12, v0
+; GCN-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GCN-NEXT:    v_lshlrev_b32_e32 v23, 8, v23
+; GCN-NEXT:    v_and_b32_e32 v21, 0xff, v21
+; GCN-NEXT:    v_lshlrev_b32_e32 v20, 24, v20
+; GCN-NEXT:    v_or_b32_e32 v35, v49, v35
+; GCN-NEXT:    v_add_i32_e32 v49, vcc, 16, v0
+; GCN-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GCN-NEXT:    v_lshlrev_b32_e32 v31, 8, v31
+; GCN-NEXT:    v_and_b32_e32 v30, 0xff, v30
+; GCN-NEXT:    v_lshlrev_b32_e32 v28, 24, v28
+; GCN-NEXT:    v_or_b32_e32 v48, v50, v48
+; GCN-NEXT:    v_add_i32_e32 v50, vcc, 20, v0
+; GCN-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GCN-NEXT:    v_lshlrev_b32_e32 v17, 8, v17
+; GCN-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GCN-NEXT:    v_lshlrev_b32_e32 v14, 24, v14
+; GCN-NEXT:    v_or_b32_e32 v3, v3, v29
+; GCN-NEXT:    v_add_i32_e32 v29, vcc, 24, v0
+; GCN-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GCN-NEXT:    v_lshlrev_b32_e32 v25, 8, v25
+; GCN-NEXT:    v_and_b32_e32 v24, 0xff, v24
+; GCN-NEXT:    v_lshlrev_b32_e32 v22, 24, v22
+; GCN-NEXT:    v_or_b32_e32 v4, v4, v37
+; GCN-NEXT:    v_add_i32_e32 v37, vcc, 28, v0
+; GCN-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GCN-NEXT:    v_lshlrev_b32_e32 v13, 8, v13
+; GCN-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GCN-NEXT:    v_lshlrev_b32_e32 v11, 24, v11
+; GCN-NEXT:    v_or_b32_e32 v5, v5, v23
+; GCN-NEXT:    v_add_i32_e32 v23, vcc, 32, v0
+; GCN-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GCN-NEXT:    v_lshlrev_b32_e32 v19, 8, v19
+; GCN-NEXT:    v_and_b32_e32 v18, 0xff, v18
+; GCN-NEXT:    v_lshlrev_b32_e32 v16, 24, v16
+; GCN-NEXT:    v_or_b32_e32 v6, v6, v31
+; GCN-NEXT:    v_add_i32_e32 v31, vcc, 36, v0
+; GCN-NEXT:    v_lshlrev_b32_e32 v33, 16, v33
+; GCN-NEXT:    v_lshlrev_b32_e32 v39, 16, v39
+; GCN-NEXT:    v_lshlrev_b32_e32 v27, 16, v27
+; GCN-NEXT:    v_lshlrev_b32_e32 v36, 16, v36
+; GCN-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GCN-NEXT:    v_lshlrev_b32_e32 v30, 16, v30
+; GCN-NEXT:    v_or_b32_e32 v7, v7, v17
+; GCN-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GCN-NEXT:    v_or_b32_e32 v8, v8, v25
+; GCN-NEXT:    v_lshlrev_b32_e32 v17, 16, v24
+; GCN-NEXT:    v_or_b32_e32 v9, v9, v13
+; GCN-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GCN-NEXT:    v_or_b32_e32 v10, v10, v19
+; GCN-NEXT:    v_lshlrev_b32_e32 v13, 16, v18
+; GCN-NEXT:    v_and_b32_e32 v18, 0xffff, v35
+; GCN-NEXT:    v_or_b32_e32 v19, v32, v33
+; GCN-NEXT:    v_and_b32_e32 v24, 0xffff, v48
+; GCN-NEXT:    v_or_b32_e32 v25, v38, v39
+; GCN-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GCN-NEXT:    v_or_b32_e32 v26, v26, v27
 ; GCN-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GCN-NEXT:    v_or_b32_e32 v27, v34, v36
+; GCN-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GCN-NEXT:    v_or_b32_e32 v20, v20, v21
 ; GCN-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GCN-NEXT:    v_or_b32_e32 v21, v28, v30
+; GCN-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GCN-NEXT:    v_or_b32_e32 v14, v14, v15
 ; GCN-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GCN-NEXT:    v_or_b32_e32 v15, v22, v17
 ; GCN-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GCN-NEXT:    v_or_b32_e32 v11, v11, v12
 ; GCN-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GCN-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GCN-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GCN-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GCN-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GCN-NEXT:    v_or_b32_e32 v2, v18, v2
-; GCN-NEXT:    v_or_b32_e32 v4, v22, v4
-; GCN-NEXT:    v_or_b32_e32 v11, v62, v6
-; GCN-NEXT:    v_or_b32_e32 v8, v63, v8
-; GCN-NEXT:    v_or_b32_e32 v9, v60, v9
-; GCN-NEXT:    v_or_b32_e32 v12, v61, v10
-; GCN-NEXT:    v_or_b32_e32 v5, v58, v5
-; GCN-NEXT:    v_or_b32_e32 v7, v59, v7
-; GCN-NEXT:    v_or_b32_e32 v1, v56, v1
-; GCN-NEXT:    v_or_b32_e32 v3, v57, v3
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, 0x30000, v2
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, s6, v4
-; GCN-NEXT:    v_add_i32_e32 v14, vcc, s6, v11
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, s6, v8
-; GCN-NEXT:    v_add_i32_e32 v23, vcc, s6, v9
-; GCN-NEXT:    v_add_i32_e32 v21, vcc, s6, v12
-; GCN-NEXT:    v_add_i32_e32 v32, vcc, s6, v5
-; GCN-NEXT:    v_add_i32_e32 v28, vcc, s6, v7
-; GCN-NEXT:    v_add_i32_e32 v50, vcc, s6, v1
-; GCN-NEXT:    v_add_i32_e32 v39, vcc, s6, v3
-; GCN-NEXT:    v_alignbit_b32 v41, v39, v50, 24
-; GCN-NEXT:    v_alignbit_b32 v43, v39, v50, 16
-; GCN-NEXT:    v_alignbit_b32 v44, v39, v50, 8
-; GCN-NEXT:    v_alignbit_b32 v53, v28, v32, 24
-; GCN-NEXT:    v_alignbit_b32 v55, v28, v32, 16
-; GCN-NEXT:    v_alignbit_b32 v42, v28, v32, 8
-; GCN-NEXT:    v_alignbit_b32 v37, v21, v23, 24
-; GCN-NEXT:    v_alignbit_b32 v48, v21, v23, 16
-; GCN-NEXT:    v_alignbit_b32 v52, v21, v23, 8
-; GCN-NEXT:    v_alignbit_b32 v31, v10, v14, 24
-; GCN-NEXT:    v_alignbit_b32 v33, v10, v14, 16
-; GCN-NEXT:    v_alignbit_b32 v35, v10, v14, 8
-; GCN-NEXT:    v_alignbit_b32 v25, v2, v6, 24
-; GCN-NEXT:    v_alignbit_b32 v27, v2, v6, 16
-; GCN-NEXT:    v_alignbit_b32 v30, v2, v6, 8
-; GCN-NEXT:    v_lshrrev_b32_e32 v54, 24, v39
-; GCN-NEXT:    v_lshrrev_b32_e32 v51, 16, v39
-; GCN-NEXT:    v_lshrrev_b32_e32 v47, 8, v39
-; GCN-NEXT:    v_lshrrev_b32_e32 v36, 24, v28
-; GCN-NEXT:    v_lshrrev_b32_e32 v34, 16, v28
-; GCN-NEXT:    v_lshrrev_b32_e32 v46, 8, v28
-; GCN-NEXT:    v_lshrrev_b32_e32 v29, 24, v21
-; GCN-NEXT:    v_lshrrev_b32_e32 v26, 16, v21
-; GCN-NEXT:    v_lshrrev_b32_e32 v45, 8, v21
-; GCN-NEXT:    v_lshrrev_b32_e32 v24, 24, v10
-; GCN-NEXT:    v_lshrrev_b32_e32 v1, 16, v10
-; GCN-NEXT:    buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; GCN-NEXT:    v_lshrrev_b32_e32 v40, 8, v10
-; GCN-NEXT:    v_lshrrev_b32_e32 v38, 24, v2
-; GCN-NEXT:    s_waitcnt expcnt(0)
-; GCN-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
-; GCN-NEXT:    buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; GCN-NEXT:    v_lshrrev_b32_e32 v49, 8, v2
-; GCN-NEXT:  .LBB24_4: ; %end
-; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GCN-NEXT:    v_and_b32_e32 v4, 0xff, v50
-; GCN-NEXT:    v_lshlrev_b32_e32 v5, 8, v44
-; GCN-NEXT:    v_and_b32_e32 v7, 0xff, v43
-; GCN-NEXT:    v_lshlrev_b32_e32 v8, 24, v41
-; GCN-NEXT:    v_and_b32_e32 v9, 0xff, v39
-; GCN-NEXT:    v_lshlrev_b32_e32 v11, 8, v47
-; GCN-NEXT:    v_and_b32_e32 v12, 0xff, v51
-; GCN-NEXT:    v_lshlrev_b32_e32 v13, 24, v54
-; GCN-NEXT:    s_waitcnt expcnt(0)
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, 4, v0
-; GCN-NEXT:    v_and_b32_e32 v15, 0xff, v32
-; GCN-NEXT:    v_lshlrev_b32_e32 v16, 8, v42
-; GCN-NEXT:    v_and_b32_e32 v17, 0xff, v55
-; GCN-NEXT:    v_lshlrev_b32_e32 v18, 24, v53
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, 8, v0
-; GCN-NEXT:    v_and_b32_e32 v19, 0xff, v28
-; GCN-NEXT:    v_lshlrev_b32_e32 v20, 8, v46
-; GCN-NEXT:    v_and_b32_e32 v22, 0xff, v34
-; GCN-NEXT:    v_lshlrev_b32_e32 v28, 24, v36
-; GCN-NEXT:    v_add_i32_e32 v32, vcc, 12, v0
-; GCN-NEXT:    v_and_b32_e32 v23, 0xff, v23
-; GCN-NEXT:    v_lshlrev_b32_e32 v34, 8, v52
-; GCN-NEXT:    v_and_b32_e32 v36, 0xff, v48
-; GCN-NEXT:    v_lshlrev_b32_e32 v37, 24, v37
-; GCN-NEXT:    v_add_i32_e32 v39, vcc, 16, v0
-; GCN-NEXT:    v_and_b32_e32 v21, 0xff, v21
-; GCN-NEXT:    v_lshlrev_b32_e32 v48, 8, v45
-; GCN-NEXT:    v_and_b32_e32 v26, 0xff, v26
-; GCN-NEXT:    v_lshlrev_b32_e32 v29, 24, v29
-; GCN-NEXT:    v_add_i32_e32 v50, vcc, 20, v0
-; GCN-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GCN-NEXT:    v_lshlrev_b32_e32 v35, 8, v35
-; GCN-NEXT:    v_and_b32_e32 v33, 0xff, v33
-; GCN-NEXT:    v_lshlrev_b32_e32 v31, 24, v31
-; GCN-NEXT:    v_add_i32_e32 v51, vcc, 24, v0
-; GCN-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GCN-NEXT:    v_lshlrev_b32_e32 v52, 8, v40
-; GCN-NEXT:    buffer_load_dword v53, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_and_b32_e32 v53, 0xff, v53
-; GCN-NEXT:    v_lshlrev_b32_e32 v24, 24, v24
-; GCN-NEXT:    v_add_i32_e32 v54, vcc, 28, v0
-; GCN-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GCN-NEXT:    v_lshlrev_b32_e32 v30, 8, v30
-; GCN-NEXT:    v_and_b32_e32 v27, 0xff, v27
-; GCN-NEXT:    v_lshlrev_b32_e32 v25, 24, v25
-; GCN-NEXT:    v_add_i32_e32 v55, vcc, 32, v0
-; GCN-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GCN-NEXT:    v_lshlrev_b32_e32 v49, 8, v49
-; GCN-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_and_b32_e32 v40, 0xff, v40
-; GCN-NEXT:    v_lshlrev_b32_e32 v38, 24, v38
-; GCN-NEXT:    v_add_i32_e32 v41, vcc, 36, v0
-; GCN-NEXT:    v_or_b32_e32 v4, v4, v5
-; GCN-NEXT:    v_lshlrev_b32_e32 v5, 16, v7
-; GCN-NEXT:    v_or_b32_e32 v7, v9, v11
-; GCN-NEXT:    v_lshlrev_b32_e32 v9, 16, v12
-; GCN-NEXT:    v_or_b32_e32 v11, v15, v16
-; GCN-NEXT:    v_lshlrev_b32_e32 v12, 16, v17
-; GCN-NEXT:    v_or_b32_e32 v15, v19, v20
-; GCN-NEXT:    v_lshlrev_b32_e32 v16, 16, v22
-; GCN-NEXT:    v_or_b32_e32 v17, v23, v34
-; GCN-NEXT:    v_lshlrev_b32_e32 v19, 16, v36
-; GCN-NEXT:    v_or_b32_e32 v20, v21, v48
-; GCN-NEXT:    v_lshlrev_b32_e32 v21, 16, v26
-; GCN-NEXT:    v_or_b32_e32 v14, v14, v35
-; GCN-NEXT:    v_lshlrev_b32_e32 v22, 16, v33
-; GCN-NEXT:    v_or_b32_e32 v10, v10, v52
-; GCN-NEXT:    v_lshlrev_b32_e32 v23, 16, v53
-; GCN-NEXT:    v_or_b32_e32 v6, v6, v30
-; GCN-NEXT:    v_lshlrev_b32_e32 v26, 16, v27
-; GCN-NEXT:    v_or_b32_e32 v2, v2, v49
-; GCN-NEXT:    v_lshlrev_b32_e32 v27, 16, v40
-; GCN-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GCN-NEXT:    v_or_b32_e32 v5, v8, v5
-; GCN-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GCN-NEXT:    v_or_b32_e32 v8, v13, v9
-; GCN-NEXT:    v_and_b32_e32 v9, 0xffff, v11
-; GCN-NEXT:    v_or_b32_e32 v11, v18, v12
-; GCN-NEXT:    v_and_b32_e32 v12, 0xffff, v15
-; GCN-NEXT:    v_or_b32_e32 v13, v28, v16
-; GCN-NEXT:    v_and_b32_e32 v15, 0xffff, v17
-; GCN-NEXT:    v_or_b32_e32 v16, v37, v19
-; GCN-NEXT:    v_and_b32_e32 v17, 0xffff, v20
-; GCN-NEXT:    v_or_b32_e32 v18, v29, v21
-; GCN-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GCN-NEXT:    v_or_b32_e32 v19, v31, v22
-; GCN-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GCN-NEXT:    v_or_b32_e32 v20, v24, v23
-; GCN-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GCN-NEXT:    v_or_b32_e32 v21, v25, v26
-; GCN-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GCN-NEXT:    v_or_b32_e32 v22, v38, v27
-; GCN-NEXT:    v_or_b32_e32 v4, v4, v5
-; GCN-NEXT:    v_or_b32_e32 v5, v7, v8
-; GCN-NEXT:    v_or_b32_e32 v7, v9, v11
-; GCN-NEXT:    v_or_b32_e32 v8, v12, v13
-; GCN-NEXT:    v_or_b32_e32 v9, v15, v16
-; GCN-NEXT:    v_or_b32_e32 v11, v17, v18
-; GCN-NEXT:    v_or_b32_e32 v12, v14, v19
-; GCN-NEXT:    v_or_b32_e32 v10, v10, v20
+; GCN-NEXT:    v_or_b32_e32 v12, v16, v13
+; GCN-NEXT:    v_or_b32_e32 v13, v18, v19
+; GCN-NEXT:    v_or_b32_e32 v16, v24, v25
+; GCN-NEXT:    v_or_b32_e32 v3, v3, v26
+; GCN-NEXT:    v_or_b32_e32 v4, v4, v27
+; GCN-NEXT:    v_or_b32_e32 v5, v5, v20
 ; GCN-NEXT:    v_or_b32_e32 v6, v6, v21
-; GCN-NEXT:    v_or_b32_e32 v2, v2, v22
-; GCN-NEXT:    buffer_store_dword v4, v0, s[0:3], 0 offen
-; GCN-NEXT:    buffer_store_dword v5, v1, s[0:3], 0 offen
-; GCN-NEXT:    buffer_store_dword v7, v3, s[0:3], 0 offen
-; GCN-NEXT:    buffer_store_dword v8, v32, s[0:3], 0 offen
-; GCN-NEXT:    buffer_store_dword v9, v39, s[0:3], 0 offen
-; GCN-NEXT:    buffer_store_dword v11, v50, s[0:3], 0 offen
-; GCN-NEXT:    buffer_store_dword v12, v51, s[0:3], 0 offen
-; GCN-NEXT:    buffer_store_dword v10, v54, s[0:3], 0 offen
-; GCN-NEXT:    buffer_store_dword v6, v55, s[0:3], 0 offen
-; GCN-NEXT:    buffer_store_dword v2, v41, s[0:3], 0 offen
-; GCN-NEXT:    buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
+; GCN-NEXT:    v_or_b32_e32 v7, v7, v14
+; GCN-NEXT:    v_or_b32_e32 v8, v8, v15
+; GCN-NEXT:    v_or_b32_e32 v9, v9, v11
+; GCN-NEXT:    v_or_b32_e32 v10, v10, v12
+; GCN-NEXT:    buffer_store_dword v13, v0, s[0:3], 0 offen
+; GCN-NEXT:    buffer_store_dword v16, v1, s[0:3], 0 offen
+; GCN-NEXT:    buffer_store_dword v3, v2, s[0:3], 0 offen
+; GCN-NEXT:    buffer_store_dword v4, v51, s[0:3], 0 offen
+; GCN-NEXT:    buffer_store_dword v5, v49, s[0:3], 0 offen
+; GCN-NEXT:    buffer_store_dword v6, v50, s[0:3], 0 offen
+; GCN-NEXT:    buffer_store_dword v7, v29, s[0:3], 0 offen
+; GCN-NEXT:    buffer_store_dword v8, v37, s[0:3], 0 offen
+; GCN-NEXT:    buffer_store_dword v9, v23, s[0:3], 0 offen
+; GCN-NEXT:    buffer_store_dword v10, v31, s[0:3], 0 offen
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
-; VI-LABEL: bitcast_v20i16_to_v40i8:
+; VI-LABEL: bitcast_v10f32_to_v40i8:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
-; VI-NEXT:    v_lshrrev_b32_e32 v17, 16, v10
-; VI-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
-; VI-NEXT:    v_lshrrev_b32_e32 v18, 16, v8
-; VI-NEXT:    v_lshrrev_b32_e32 v22, 16, v7
-; VI-NEXT:    v_lshrrev_b32_e32 v19, 16, v6
-; VI-NEXT:    v_lshrrev_b32_e32 v24, 16, v5
-; VI-NEXT:    v_lshrrev_b32_e32 v21, 16, v4
-; VI-NEXT:    v_lshrrev_b32_e32 v25, 16, v3
-; VI-NEXT:    v_lshrrev_b32_e32 v23, 16, v2
-; VI-NEXT:    v_lshrrev_b32_e32 v26, 16, v1
-; VI-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT:    buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
-; VI-NEXT:    ; implicit-def: $vgpr34
-; VI-NEXT:    ; implicit-def: $vgpr40
+; VI-NEXT:    ; implicit-def: $vgpr16
+; VI-NEXT:    ; implicit-def: $vgpr48
 ; VI-NEXT:    ; implicit-def: $vgpr15
-; VI-NEXT:    ; implicit-def: $vgpr32
-; VI-NEXT:    ; implicit-def: $vgpr54
-; VI-NEXT:    ; implicit-def: $vgpr41
+; VI-NEXT:    ; implicit-def: $vgpr39
 ; VI-NEXT:    ; implicit-def: $vgpr38
-; VI-NEXT:    ; implicit-def: $vgpr51
-; VI-NEXT:    ; implicit-def: $vgpr14
 ; VI-NEXT:    ; implicit-def: $vgpr37
-; VI-NEXT:    ; implicit-def: $vgpr48
-; VI-NEXT:    ; implicit-def: $vgpr52
-; VI-NEXT:    ; implicit-def: $vgpr50
 ; VI-NEXT:    ; implicit-def: $vgpr36
-; VI-NEXT:    ; implicit-def: $vgpr13
-; VI-NEXT:    ; implicit-def: $vgpr49
 ; VI-NEXT:    ; implicit-def: $vgpr35
-; VI-NEXT:    ; implicit-def: $vgpr39
-; VI-NEXT:    ; implicit-def: $vgpr55
+; VI-NEXT:    ; implicit-def: $vgpr14
+; VI-NEXT:    ; implicit-def: $vgpr34
+; VI-NEXT:    ; implicit-def: $vgpr33
+; VI-NEXT:    ; implicit-def: $vgpr32
 ; VI-NEXT:    ; implicit-def: $vgpr31
-; VI-NEXT:    ; implicit-def: $vgpr12
-; VI-NEXT:    ; implicit-def: $vgpr53
 ; VI-NEXT:    ; implicit-def: $vgpr30
-; VI-NEXT:    ; implicit-def: $vgpr33
-; VI-NEXT:    ; implicit-def: $vgpr43
+; VI-NEXT:    ; implicit-def: $vgpr13
+; VI-NEXT:    ; implicit-def: $vgpr29
 ; VI-NEXT:    ; implicit-def: $vgpr28
-; VI-NEXT:    ; implicit-def: $vgpr11
-; VI-NEXT:    ; implicit-def: $vgpr42
 ; VI-NEXT:    ; implicit-def: $vgpr27
-; VI-NEXT:    ; implicit-def: $vgpr29
+; VI-NEXT:    ; implicit-def: $vgpr26
+; VI-NEXT:    ; implicit-def: $vgpr25
+; VI-NEXT:    ; implicit-def: $vgpr12
+; VI-NEXT:    ; implicit-def: $vgpr24
+; VI-NEXT:    ; implicit-def: $vgpr23
+; VI-NEXT:    ; implicit-def: $vgpr22
+; VI-NEXT:    ; implicit-def: $vgpr21
+; VI-NEXT:    ; implicit-def: $vgpr20
+; VI-NEXT:    ; implicit-def: $vgpr19
+; VI-NEXT:    ; implicit-def: $vgpr18
+; VI-NEXT:    ; implicit-def: $vgpr17
+; VI-NEXT:    ; implicit-def: $vgpr11
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB24_2
+; VI-NEXT:    s_cbranch_execz .LBB12_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.false
 ; VI-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
 ; VI-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
 ; VI-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
 ; VI-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
-; VI-NEXT:    v_lshrrev_b32_e32 v29, 24, v10
-; VI-NEXT:    v_lshrrev_b32_e32 v27, 8, v10
-; VI-NEXT:    v_lshrrev_b32_e32 v28, 8, v9
-; VI-NEXT:    v_lshrrev_b32_e32 v33, 24, v8
-; VI-NEXT:    v_lshrrev_b32_e32 v30, 8, v8
-; VI-NEXT:    v_lshrrev_b32_e32 v31, 8, v7
-; VI-NEXT:    v_lshrrev_b32_e32 v39, 24, v6
-; VI-NEXT:    v_lshrrev_b32_e32 v35, 8, v6
-; VI-NEXT:    v_lshrrev_b32_e32 v36, 8, v5
-; VI-NEXT:    v_lshrrev_b32_e32 v52, 24, v4
-; VI-NEXT:    v_lshrrev_b32_e32 v48, 8, v4
-; VI-NEXT:    v_lshrrev_b32_e32 v51, 8, v3
-; VI-NEXT:    v_lshrrev_b32_e32 v41, 24, v2
-; VI-NEXT:    v_lshrrev_b32_e32 v54, 8, v2
-; VI-NEXT:    v_lshrrev_b32_e32 v40, 8, v1
 ; VI-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
-; VI-NEXT:    v_mov_b32_e32 v34, v1
-; VI-NEXT:    v_mov_b32_e32 v32, v2
-; VI-NEXT:    v_mov_b32_e32 v38, v3
-; VI-NEXT:    v_mov_b32_e32 v37, v4
-; VI-NEXT:    v_mov_b32_e32 v50, v5
-; VI-NEXT:    v_mov_b32_e32 v49, v6
-; VI-NEXT:    v_mov_b32_e32 v55, v7
-; VI-NEXT:    v_mov_b32_e32 v53, v8
-; VI-NEXT:    v_mov_b32_e32 v43, v9
-; VI-NEXT:    v_mov_b32_e32 v42, v10
-; VI-NEXT:    ; implicit-def: $vgpr1
-; VI-NEXT:    ; implicit-def: $vgpr3
-; VI-NEXT:    ; implicit-def: $vgpr5
-; VI-NEXT:    ; implicit-def: $vgpr7
-; VI-NEXT:    ; implicit-def: $vgpr9
-; VI-NEXT:  .LBB24_2: ; %Flow
+; VI-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
+; VI-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
+; VI-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
+; VI-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
+; VI-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
+; VI-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
+; VI-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
+; VI-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
+; VI-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
+; VI-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
+; VI-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
+; VI-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
+; VI-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
+; VI-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
+; VI-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
+; VI-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
+; VI-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
+; VI-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
+; VI-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
+; VI-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
+; VI-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
+; VI-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
+; VI-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
+; VI-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
+; VI-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
+; VI-NEXT:  .LBB12_2: ; %Flow
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB24_4
+; VI-NEXT:    s_cbranch_execz .LBB12_4
 ; VI-NEXT:  ; %bb.3: ; %cmp.true
-; VI-NEXT:    v_mov_b32_e32 v11, 3
-; VI-NEXT:    v_add_u16_sdwa v17, v10, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_u16_sdwa v20, v9, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_u16_sdwa v18, v8, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_u16_sdwa v22, v7, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_u16_e32 v42, 3, v10
-; VI-NEXT:    v_lshlrev_b32_e32 v10, 16, v17
-; VI-NEXT:    v_add_u16_e32 v43, 3, v9
-; VI-NEXT:    v_lshlrev_b32_e32 v9, 16, v20
-; VI-NEXT:    v_add_u16_sdwa v19, v6, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_u16_sdwa v24, v5, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_u16_e32 v53, 3, v8
-; VI-NEXT:    v_lshlrev_b32_e32 v8, 16, v18
-; VI-NEXT:    v_add_u16_e32 v55, 3, v7
-; VI-NEXT:    v_lshlrev_b32_e32 v7, 16, v22
-; VI-NEXT:    v_or_b32_e32 v10, v42, v10
-; VI-NEXT:    v_or_b32_e32 v9, v43, v9
-; VI-NEXT:    v_add_u16_sdwa v23, v2, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_u16_sdwa v26, v1, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_u16_sdwa v21, v4, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_u16_sdwa v25, v3, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_add_u16_e32 v49, 3, v6
-; VI-NEXT:    v_lshlrev_b32_e32 v6, 16, v19
-; VI-NEXT:    v_add_u16_e32 v50, 3, v5
-; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v24
-; VI-NEXT:    v_or_b32_e32 v8, v53, v8
-; VI-NEXT:    v_or_b32_e32 v7, v55, v7
+; VI-NEXT:    v_add_f32_e32 v10, 1.0, v10
+; VI-NEXT:    v_add_f32_e32 v9, 1.0, v9
+; VI-NEXT:    v_add_f32_e32 v8, 1.0, v8
+; VI-NEXT:    v_add_f32_e32 v7, 1.0, v7
 ; VI-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
-; VI-NEXT:    v_add_u16_e32 v37, 3, v4
-; VI-NEXT:    v_lshlrev_b32_e32 v4, 16, v21
-; VI-NEXT:    v_add_u16_e32 v38, 3, v3
-; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v25
-; VI-NEXT:    v_or_b32_e32 v6, v49, v6
-; VI-NEXT:    v_or_b32_e32 v5, v50, v5
+; VI-NEXT:    v_add_f32_e32 v6, 1.0, v6
+; VI-NEXT:    v_add_f32_e32 v5, 1.0, v5
 ; VI-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
-; VI-NEXT:    v_add_u16_e32 v32, 3, v2
-; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v23
-; VI-NEXT:    v_add_u16_e32 v34, 3, v1
-; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v26
-; VI-NEXT:    v_or_b32_e32 v4, v37, v4
-; VI-NEXT:    v_or_b32_e32 v3, v38, v3
+; VI-NEXT:    v_add_f32_e32 v4, 1.0, v4
+; VI-NEXT:    v_add_f32_e32 v3, 1.0, v3
 ; VI-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
-; VI-NEXT:    v_or_b32_e32 v2, v32, v2
-; VI-NEXT:    v_or_b32_e32 v1, v34, v1
+; VI-NEXT:    v_add_f32_e32 v2, 1.0, v2
+; VI-NEXT:    v_add_f32_e32 v1, 1.0, v1
 ; VI-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
 ; VI-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
-; VI-NEXT:    v_lshrrev_b32_e32 v27, 8, v10
-; VI-NEXT:    v_lshrrev_b32_e32 v28, 8, v9
-; VI-NEXT:    v_lshrrev_b32_e32 v30, 8, v8
-; VI-NEXT:    v_lshrrev_b32_e32 v31, 8, v7
-; VI-NEXT:    v_lshrrev_b32_e32 v35, 8, v6
-; VI-NEXT:    v_lshrrev_b32_e32 v36, 8, v5
-; VI-NEXT:    v_lshrrev_b32_e32 v48, 8, v4
-; VI-NEXT:    v_lshrrev_b32_e32 v51, 8, v3
-; VI-NEXT:    v_lshrrev_b32_e32 v54, 8, v2
-; VI-NEXT:    v_lshrrev_b32_e32 v40, 8, v1
-; VI-NEXT:    v_bfe_u32 v29, v17, 8, 8
-; VI-NEXT:    v_bfe_u32 v33, v18, 8, 8
-; VI-NEXT:    v_bfe_u32 v39, v19, 8, 8
-; VI-NEXT:    v_bfe_u32 v52, v21, 8, 8
-; VI-NEXT:    v_bfe_u32 v41, v23, 8, 8
-; VI-NEXT:  .LBB24_4: ; %end
+; VI-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
+; VI-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
+; VI-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
+; VI-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
+; VI-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
+; VI-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
+; VI-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
+; VI-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
+; VI-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
+; VI-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
+; VI-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
+; VI-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
+; VI-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
+; VI-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
+; VI-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
+; VI-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
+; VI-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
+; VI-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
+; VI-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
+; VI-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
+; VI-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
+; VI-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
+; VI-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
+; VI-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
+; VI-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
+; VI-NEXT:  .LBB12_4: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
-; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v40
-; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v15
-; VI-NEXT:    v_or_b32_sdwa v1, v34, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v2, v26, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT:    v_lshlrev_b16_e32 v15, 8, v15
+; VI-NEXT:    v_lshlrev_b16_e32 v16, 8, v16
+; VI-NEXT:    v_or_b32_sdwa v15, v48, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v1, v1, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v1, v1, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
-; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v54
-; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v41
-; VI-NEXT:    v_or_b32_sdwa v1, v32, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v2, v23, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v39
+; VI-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v37
+; VI-NEXT:    v_or_b32_sdwa v2, v38, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; VI-NEXT:    v_add_u32_e32 v2, vcc, 4, v0
 ; VI-NEXT:    buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v51
+; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v36
 ; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v14
-; VI-NEXT:    v_or_b32_sdwa v1, v38, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v2, v25, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v2, v35, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; VI-NEXT:    v_add_u32_e32 v2, vcc, 8, v0
 ; VI-NEXT:    buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v48
-; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v52
-; VI-NEXT:    v_or_b32_sdwa v1, v37, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v2, v21, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v34
+; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v32
+; VI-NEXT:    v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v2, v33, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; VI-NEXT:    v_add_u32_e32 v2, vcc, 12, v0
 ; VI-NEXT:    buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v36
+; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v31
 ; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v13
-; VI-NEXT:    v_or_b32_sdwa v1, v50, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v2, v24, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v2, v30, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; VI-NEXT:    v_add_u32_e32 v2, vcc, 16, v0
 ; VI-NEXT:    buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v35
-; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v39
-; VI-NEXT:    v_or_b32_sdwa v1, v49, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v2, v19, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v29
+; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v27
+; VI-NEXT:    v_or_b32_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v2, v28, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; VI-NEXT:    v_add_u32_e32 v2, vcc, 20, v0
 ; VI-NEXT:    buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v31
+; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v26
 ; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v12
-; VI-NEXT:    v_or_b32_sdwa v1, v55, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v2, v22, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v1, v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v2, v25, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; VI-NEXT:    v_add_u32_e32 v2, vcc, 24, v0
 ; VI-NEXT:    buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v30
-; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v33
-; VI-NEXT:    v_or_b32_sdwa v1, v53, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v2, v18, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v24
+; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v22
+; VI-NEXT:    v_or_b32_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v2, v23, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; VI-NEXT:    v_add_u32_e32 v2, vcc, 28, v0
 ; VI-NEXT:    buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v28
+; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v21
 ; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v11
-; VI-NEXT:    v_or_b32_sdwa v1, v43, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v1, v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_sdwa v2, v20, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; VI-NEXT:    v_add_u32_e32 v2, vcc, 32, v0
 ; VI-NEXT:    buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v27
-; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v29
-; VI-NEXT:    v_or_b32_sdwa v1, v42, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v2, v17, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v19
+; VI-NEXT:    v_lshlrev_b16_e32 v2, 8, v17
+; VI-NEXT:    v_or_b32_sdwa v1, v10, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v2, v18, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, 36, v0
 ; VI-NEXT:    buffer_store_dword v1, v0, s[0:3], 0 offen
-; VI-NEXT:    buffer_load_dword v43, off, s[0:3], s32 ; 4-byte Folded Reload
-; VI-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
-; VI-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
-; VI-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
 ; VI-NEXT:    s_waitcnt vmcnt(0)
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX9-LABEL: bitcast_v20i16_to_v40i8:
+; GFX9-LABEL: bitcast_v10f32_to_v40i8:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
@@ -7531,7 +4364,7 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) {
 ; GFX9-NEXT:    ; implicit-def: $vgpr11
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB24_2
+; GFX9-NEXT:    s_cbranch_execz .LBB12_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.false
 ; GFX9-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
 ; GFX9-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
@@ -7563,23 +4396,23 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) {
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; GFX9-NEXT:  .LBB24_2: ; %Flow
+; GFX9-NEXT:  .LBB12_2: ; %Flow
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB24_4
+; GFX9-NEXT:    s_cbranch_execz .LBB12_4
 ; GFX9-NEXT:  ; %bb.3: ; %cmp.true
-; GFX9-NEXT:    v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
+; GFX9-NEXT:    v_add_f32_e32 v10, 1.0, v10
+; GFX9-NEXT:    v_add_f32_e32 v9, 1.0, v9
+; GFX9-NEXT:    v_add_f32_e32 v8, 1.0, v8
+; GFX9-NEXT:    v_add_f32_e32 v7, 1.0, v7
 ; GFX9-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
-; GFX9-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
+; GFX9-NEXT:    v_add_f32_e32 v6, 1.0, v6
+; GFX9-NEXT:    v_add_f32_e32 v5, 1.0, v5
 ; GFX9-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
-; GFX9-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
+; GFX9-NEXT:    v_add_f32_e32 v4, 1.0, v4
+; GFX9-NEXT:    v_add_f32_e32 v3, 1.0, v3
 ; GFX9-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
-; GFX9-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
+; GFX9-NEXT:    v_add_f32_e32 v2, 1.0, v2
+; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v1
 ; GFX9-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
 ; GFX9-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
@@ -7607,7 +4440,7 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) {
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; GFX9-NEXT:  .LBB24_4: ; %end
+; GFX9-NEXT:  .LBB12_4: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v15, 8, v15
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v16, 8, v16
@@ -7672,227 +4505,403 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v20i16_to_v40i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB24_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; GFX11-NEXT:  .LBB24_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB24_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; GFX11-NEXT:  .LBB24_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v16
-; GFX11-NEXT:    v_and_b32_e32 v48, 0xff, v48
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v15
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_lshlrev_b16 v36, 8, v36
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xff, v35
-; GFX11-NEXT:    v_lshlrev_b16 v14, 8, v14
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_lshlrev_b16 v31, 8, v31
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v30
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v13
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v39
-; GFX11-NEXT:    v_and_b32_e32 v38, 0xff, v38
-; GFX11-NEXT:    v_lshlrev_b16 v37, 8, v37
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v16
-; GFX11-NEXT:    v_or_b32_e32 v15, v48, v15
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v36
-; GFX11-NEXT:    v_or_b32_e32 v14, v35, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v31
-; GFX11-NEXT:    v_or_b32_e32 v13, v30, v13
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v39
-; GFX11-NEXT:    v_or_b32_e32 v16, v38, v37
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v15
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v13
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v29
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v28
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v27
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v16
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v26
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_lshlrev_b16 v34, 8, v34
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xff, v33
-; GFX11-NEXT:    v_lshlrev_b16 v32, 8, v32
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v25
-; GFX11-NEXT:    v_lshlrev_b16 v12, 8, v12
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v24
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v13
-; GFX11-NEXT:    v_or_b32_e32 v13, v14, v15
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v23
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v22
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v16
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v21
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v20
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v11
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v19
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v18
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v17
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v34
-; GFX11-NEXT:    v_or_b32_e32 v32, v33, v32
-; GFX11-NEXT:    v_or_b32_e32 v12, v25, v12
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v24
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v16
-; GFX11-NEXT:    v_or_b32_e32 v11, v20, v11
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v19
-; GFX11-NEXT:    v_or_b32_e32 v15, v18, v17
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v30, 16, v32
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v30
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v13
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v12
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v14
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v11
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v15
-; GFX11-NEXT:    s_clause 0x2
-; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off
-; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
-; GFX11-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v10f32_to_v40i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB12_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v18, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v20, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v22, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB12_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB12_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v9, 1.0, v9
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v10, 1.0, v10 :: v_dual_add_f32 v1, 1.0, v1
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v7, 1.0, v7
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v8, 1.0, v8 :: v_dual_add_f32 v3, 1.0, v3
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v18, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v20, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v22, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB12_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v16.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.l, 8, v28.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v11.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v30.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v29.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v1.h, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v15.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v29, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v13.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v26.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.l, v2.h, v14.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v30, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v5.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v24.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v15, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.l, 8, v22.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.l, 8, v12.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v13.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v13.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v14, v25
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v6.h, v12.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v20.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v29, v16
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v7.h, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v18.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v10.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v30, v28
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v26, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v15, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v16, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v13, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v17, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v19, v10
+; GFX11-TRUE16-NEXT:    s_clause 0x2
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-TRUE16-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v10f32_to_v40i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB12_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB12_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB12_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v9, 1.0, v9
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v10, 1.0, v10 :: v_dual_add_f32 v1, 1.0, v1
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v7, 1.0, v7
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v8, 1.0, v8 :: v_dual_add_f32 v3, 1.0, v3
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB12_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v48, 0xff, v48
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v36, 8, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v14, 8, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v31, 8, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v38, 0xff, v38
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v37, 8, v37
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v48, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v35, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v31
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v30, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v38, v37
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v34, 8, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v32, 8, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v12, 8, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v14, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v32, v33, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v25, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v20, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v18, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v15
+; GFX11-FAKE16-NEXT:    s_clause 0x2
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-FAKE16-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
 cmp.true:
-  %a1 = add <20 x i16> %a, splat (i16 3)
-  %a2 = bitcast <20 x i16> %a1 to <40 x i8>
+  %a1 = fadd <10 x float> %a, splat (float 1.000000e+00)
+  %a2 = bitcast <10 x float> %a1 to <40 x i8>
   br label %end
 
 cmp.false:
-  %a3 = bitcast <20 x i16> %a to <40 x i8>
+  %a3 = bitcast <10 x float> %a to <40 x i8>
   br label %end
 
 end:
@@ -7900,166 +4909,131 @@ end:
   ret <40 x i8> %phi
 }
 
-define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) {
-; GCN-LABEL: bitcast_v40i8_to_v20i16:
+define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) {
+; GCN-LABEL: bitcast_v40i8_to_v10f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_load_dword v31, off, s[0:3], s32 offset:32
-; GCN-NEXT:    s_waitcnt expcnt(2)
-; GCN-NEXT:    buffer_load_dword v57, off, s[0:3], s32 offset:28
-; GCN-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:24
+; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GCN-NEXT:    v_mov_b32_e32 v35, v8
+; GCN-NEXT:    v_mov_b32_e32 v34, v6
+; GCN-NEXT:    v_mov_b32_e32 v33, v4
+; GCN-NEXT:    v_mov_b32_e32 v32, v2
+; GCN-NEXT:    v_mov_b32_e32 v31, v0
+; GCN-NEXT:    buffer_load_dword v0, off, s[0:3], s32 offset:32
+; GCN-NEXT:    buffer_load_dword v54, off, s[0:3], s32 offset:28
+; GCN-NEXT:    buffer_load_dword v2, off, s[0:3], s32 offset:24
+; GCN-NEXT:    buffer_load_dword v55, off, s[0:3], s32 offset:20
+; GCN-NEXT:    buffer_load_dword v4, off, s[0:3], s32 offset:16
 ; GCN-NEXT:    s_waitcnt expcnt(1)
-; GCN-NEXT:    buffer_load_dword v58, off, s[0:3], s32 offset:20
-; GCN-NEXT:    buffer_load_dword v33, off, s[0:3], s32 offset:16
+; GCN-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:12
+; GCN-NEXT:    buffer_load_dword v6, off, s[0:3], s32 offset:8
 ; GCN-NEXT:    s_waitcnt expcnt(0)
-; GCN-NEXT:    buffer_load_dword v59, off, s[0:3], s32 offset:12
-; GCN-NEXT:    buffer_load_dword v34, off, s[0:3], s32 offset:8
-; GCN-NEXT:    buffer_load_dword v56, off, s[0:3], s32 offset:4
-; GCN-NEXT:    buffer_load_dword v35, off, s[0:3], s32
-; GCN-NEXT:    buffer_load_dword v51, off, s[0:3], s32 offset:36
-; GCN-NEXT:    v_lshlrev_b32_e32 v53, 8, v5
-; GCN-NEXT:    v_lshlrev_b32_e32 v36, 24, v7
-; GCN-NEXT:    v_lshlrev_b32_e32 v37, 24, v3
-; GCN-NEXT:    v_lshlrev_b32_e32 v55, 8, v13
-; GCN-NEXT:    v_lshlrev_b32_e32 v38, 24, v15
-; GCN-NEXT:    v_lshlrev_b32_e32 v39, 24, v11
-; GCN-NEXT:    v_lshlrev_b32_e32 v40, 8, v21
-; GCN-NEXT:    v_lshlrev_b32_e32 v48, 24, v23
-; GCN-NEXT:    v_lshlrev_b32_e32 v49, 24, v19
-; GCN-NEXT:    v_lshlrev_b32_e32 v42, 8, v29
-; GCN-NEXT:    v_lshlrev_b32_e32 v50, 24, v27
-; GCN-NEXT:    v_lshlrev_b32_e32 v41, 8, v1
-; GCN-NEXT:    v_lshlrev_b32_e32 v43, 8, v9
-; GCN-NEXT:    v_lshlrev_b32_e32 v44, 8, v17
-; GCN-NEXT:    v_lshlrev_b32_e32 v45, 8, v25
+; GCN-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:4
+; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s32
+; GCN-NEXT:    buffer_load_dword v53, off, s[0:3], s32 offset:36
+; GCN-NEXT:    v_lshlrev_b32_e32 v38, 8, v1
+; GCN-NEXT:    v_lshlrev_b32_e32 v36, 24, v3
+; GCN-NEXT:    v_lshlrev_b32_e32 v39, 8, v5
+; GCN-NEXT:    v_lshlrev_b32_e32 v37, 24, v7
+; GCN-NEXT:    v_lshlrev_b32_e32 v48, 8, v9
+; GCN-NEXT:    v_lshlrev_b32_e32 v11, 24, v11
+; GCN-NEXT:    v_lshlrev_b32_e32 v49, 8, v13
+; GCN-NEXT:    v_lshlrev_b32_e32 v13, 24, v15
+; GCN-NEXT:    v_lshlrev_b32_e32 v50, 8, v17
+; GCN-NEXT:    v_lshlrev_b32_e32 v15, 24, v19
+; GCN-NEXT:    v_lshlrev_b32_e32 v51, 8, v21
+; GCN-NEXT:    v_lshlrev_b32_e32 v17, 24, v23
+; GCN-NEXT:    v_lshlrev_b32_e32 v52, 8, v25
+; GCN-NEXT:    v_lshlrev_b32_e32 v19, 24, v27
+; GCN-NEXT:    v_lshlrev_b32_e32 v27, 8, v29
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v51
-; GCN-NEXT:    v_lshlrev_b32_e32 v51, 24, v35
-; GCN-NEXT:    v_lshlrev_b32_e32 v46, 8, v32
-; GCN-NEXT:    v_lshlrev_b32_e32 v52, 24, v31
-; GCN-NEXT:    v_lshlrev_b32_e32 v54, 24, v33
-; GCN-NEXT:    v_lshlrev_b32_e32 v47, 8, v34
-; GCN-NEXT:    ; implicit-def: $vgpr21
-; GCN-NEXT:    ; implicit-def: $vgpr1
-; GCN-NEXT:    ; implicit-def: $vgpr23
-; GCN-NEXT:    ; implicit-def: $vgpr3
-; GCN-NEXT:    ; implicit-def: $vgpr25
-; GCN-NEXT:    ; implicit-def: $vgpr5
-; GCN-NEXT:    ; implicit-def: $vgpr27
-; GCN-NEXT:    ; implicit-def: $vgpr7
-; GCN-NEXT:    ; implicit-def: $vgpr29
-; GCN-NEXT:    ; implicit-def: $vgpr9
-; GCN-NEXT:    ; implicit-def: $vgpr31
-; GCN-NEXT:    ; implicit-def: $vgpr11
-; GCN-NEXT:    ; implicit-def: $vgpr32
-; GCN-NEXT:    ; implicit-def: $vgpr13
-; GCN-NEXT:    ; implicit-def: $vgpr33
-; GCN-NEXT:    ; implicit-def: $vgpr15
-; GCN-NEXT:    ; implicit-def: $vgpr34
-; GCN-NEXT:    ; implicit-def: $vgpr17
-; GCN-NEXT:    ; implicit-def: $vgpr35
-; GCN-NEXT:    ; implicit-def: $vgpr19
+; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v53
+; GCN-NEXT:    v_lshlrev_b32_e32 v21, 24, v8
+; GCN-NEXT:    v_lshlrev_b32_e32 v29, 8, v6
+; GCN-NEXT:    v_lshlrev_b32_e32 v23, 24, v4
+; GCN-NEXT:    v_lshlrev_b32_e32 v53, 8, v2
+; GCN-NEXT:    v_lshlrev_b32_e32 v25, 24, v0
+; GCN-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB25_2
+; GCN-NEXT:    s_cbranch_execz .LBB13_2
 ; GCN-NEXT:  ; %bb.1: ; %cmp.false
-; GCN-NEXT:    v_and_b32_e32 v1, 0xff, v4
-; GCN-NEXT:    v_and_b32_e32 v3, 0xff, v6
-; GCN-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GCN-NEXT:    v_and_b32_e32 v4, 0xff, v12
-; GCN-NEXT:    v_and_b32_e32 v5, 0xff, v14
-; GCN-NEXT:    v_and_b32_e32 v6, 0xff, v10
-; GCN-NEXT:    v_and_b32_e32 v7, 0xff, v20
-; GCN-NEXT:    v_and_b32_e32 v9, 0xff, v22
-; GCN-NEXT:    v_and_b32_e32 v10, 0xff, v18
-; GCN-NEXT:    v_and_b32_e32 v11, 0xff, v28
-; GCN-NEXT:    v_and_b32_e32 v12, 0xff, v30
-; GCN-NEXT:    v_and_b32_e32 v13, 0xff, v26
-; GCN-NEXT:    v_and_b32_e32 v14, 0xff, v58
-; GCN-NEXT:    v_and_b32_e32 v15, 0xff, v57
-; GCN-NEXT:    v_and_b32_e32 v17, 0xff, v59
-; GCN-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GCN-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GCN-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GCN-NEXT:    v_and_b32_e32 v18, 0xff, v24
-; GCN-NEXT:    v_and_b32_e32 v19, 0xff, v56
-; GCN-NEXT:    v_or_b32_e32 v1, v1, v53
+; GCN-NEXT:    v_and_b32_e32 v0, 0xff, v31
+; GCN-NEXT:    v_and_b32_e32 v1, 0xff, v32
+; GCN-NEXT:    v_and_b32_e32 v2, 0xff, v33
+; GCN-NEXT:    v_and_b32_e32 v3, 0xff, v34
+; GCN-NEXT:    v_and_b32_e32 v4, 0xff, v35
+; GCN-NEXT:    v_and_b32_e32 v5, 0xff, v10
+; GCN-NEXT:    v_and_b32_e32 v6, 0xff, v12
+; GCN-NEXT:    v_and_b32_e32 v7, 0xff, v14
+; GCN-NEXT:    v_and_b32_e32 v8, 0xff, v16
+; GCN-NEXT:    v_and_b32_e32 v9, 0xff, v18
+; GCN-NEXT:    v_and_b32_e32 v10, 0xff, v20
+; GCN-NEXT:    v_and_b32_e32 v12, 0xff, v22
+; GCN-NEXT:    v_and_b32_e32 v14, 0xff, v24
+; GCN-NEXT:    v_and_b32_e32 v16, 0xff, v26
+; GCN-NEXT:    v_and_b32_e32 v18, 0xff, v28
+; GCN-NEXT:    v_and_b32_e32 v20, 0xff, v30
+; GCN-NEXT:    v_and_b32_e32 v22, 0xff, v41
+; GCN-NEXT:    v_and_b32_e32 v24, 0xff, v40
+; GCN-NEXT:    v_and_b32_e32 v26, 0xff, v55
+; GCN-NEXT:    v_and_b32_e32 v28, 0xff, v54
+; GCN-NEXT:    v_or_b32_e32 v0, v0, v38
+; GCN-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GCN-NEXT:    v_or_b32_e32 v2, v2, v39
 ; GCN-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GCN-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GCN-NEXT:    v_or_b32_e32 v4, v4, v55
+; GCN-NEXT:    v_or_b32_e32 v4, v4, v48
 ; GCN-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GCN-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GCN-NEXT:    v_or_b32_e32 v7, v7, v40
+; GCN-NEXT:    v_or_b32_e32 v6, v6, v49
+; GCN-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GCN-NEXT:    v_or_b32_e32 v8, v8, v50
 ; GCN-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GCN-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GCN-NEXT:    v_or_b32_e32 v11, v11, v42
+; GCN-NEXT:    v_or_b32_e32 v10, v10, v51
 ; GCN-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GCN-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GCN-NEXT:    v_or_b32_e32 v14, v14, v46
-; GCN-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GCN-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GCN-NEXT:    v_or_b32_e32 v0, v0, v41
-; GCN-NEXT:    v_or_b32_e32 v8, v8, v43
-; GCN-NEXT:    v_or_b32_e32 v16, v16, v44
-; GCN-NEXT:    v_or_b32_e32 v18, v18, v45
-; GCN-NEXT:    v_or_b32_e32 v19, v19, v47
-; GCN-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GCN-NEXT:    v_or_b32_e32 v3, v36, v3
-; GCN-NEXT:    v_or_b32_e32 v2, v37, v2
-; GCN-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GCN-NEXT:    v_or_b32_e32 v5, v38, v5
-; GCN-NEXT:    v_or_b32_e32 v6, v39, v6
-; GCN-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GCN-NEXT:    v_or_b32_e32 v9, v48, v9
-; GCN-NEXT:    v_or_b32_e32 v10, v49, v10
-; GCN-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GCN-NEXT:    v_or_b32_e32 v12, v51, v12
-; GCN-NEXT:    v_or_b32_e32 v13, v50, v13
-; GCN-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GCN-NEXT:    v_or_b32_e32 v20, v52, v15
-; GCN-NEXT:    v_or_b32_e32 v17, v54, v17
+; GCN-NEXT:    v_or_b32_e32 v14, v14, v52
+; GCN-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GCN-NEXT:    v_or_b32_e32 v18, v18, v27
+; GCN-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GCN-NEXT:    v_or_b32_e32 v22, v22, v29
+; GCN-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GCN-NEXT:    v_or_b32_e32 v26, v26, v53
+; GCN-NEXT:    v_lshlrev_b32_e32 v27, 16, v28
 ; GCN-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GCN-NEXT:    v_or_b32_e32 v1, v36, v1
+; GCN-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GCN-NEXT:    v_or_b32_e32 v3, v37, v3
+; GCN-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GCN-NEXT:    v_or_b32_e32 v5, v11, v5
+; GCN-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GCN-NEXT:    v_or_b32_e32 v7, v13, v7
 ; GCN-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GCN-NEXT:    v_and_b32_e32 v15, 0xffff, v16
-; GCN-NEXT:    v_and_b32_e32 v16, 0xffff, v18
-; GCN-NEXT:    v_and_b32_e32 v18, 0xffff, v19
-; GCN-NEXT:    v_or_b32_e32 v23, v1, v3
-; GCN-NEXT:    v_or_b32_e32 v27, v4, v5
-; GCN-NEXT:    v_or_b32_e32 v31, v7, v9
-; GCN-NEXT:    v_or_b32_e32 v33, v11, v12
-; GCN-NEXT:    v_or_b32_e32 v35, v14, v20
-; GCN-NEXT:    v_or_b32_e32 v21, v0, v2
-; GCN-NEXT:    v_or_b32_e32 v25, v8, v6
-; GCN-NEXT:    v_or_b32_e32 v29, v15, v10
-; GCN-NEXT:    v_or_b32_e32 v32, v16, v13
-; GCN-NEXT:    v_or_b32_e32 v34, v18, v17
-; GCN-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
-; GCN-NEXT:    v_lshrrev_b32_e32 v7, 16, v5
-; GCN-NEXT:    v_lshrrev_b32_e32 v11, 16, v9
-; GCN-NEXT:    v_lshrrev_b32_e32 v15, 16, v12
-; GCN-NEXT:    v_alignbit_b32 v1, v23, v2, 16
-; GCN-NEXT:    v_alignbit_b32 v5, v27, v6, 16
-; GCN-NEXT:    v_alignbit_b32 v9, v31, v10, 16
-; GCN-NEXT:    v_alignbit_b32 v13, v33, v13, 16
-; GCN-NEXT:    v_alignbit_b32 v17, v35, v17, 16
-; GCN-NEXT:    v_lshrrev_b32_e32 v19, 16, v20
-; GCN-NEXT:    ; implicit-def: $vgpr0
-; GCN-NEXT:    ; implicit-def: $vgpr2
-; GCN-NEXT:    ; implicit-def: $vgpr4
-; GCN-NEXT:    ; implicit-def: $vgpr6
-; GCN-NEXT:    ; implicit-def: $vgpr8
+; GCN-NEXT:    v_or_b32_e32 v9, v15, v9
+; GCN-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GCN-NEXT:    v_or_b32_e32 v11, v17, v12
+; GCN-NEXT:    v_and_b32_e32 v12, 0xffff, v14
+; GCN-NEXT:    v_or_b32_e32 v13, v19, v16
+; GCN-NEXT:    v_and_b32_e32 v14, 0xffff, v18
+; GCN-NEXT:    v_or_b32_e32 v15, v21, v20
+; GCN-NEXT:    v_and_b32_e32 v16, 0xffff, v22
+; GCN-NEXT:    v_or_b32_e32 v17, v23, v24
+; GCN-NEXT:    v_and_b32_e32 v18, 0xffff, v26
+; GCN-NEXT:    v_or_b32_e32 v19, v25, v27
+; GCN-NEXT:    v_or_b32_e32 v0, v0, v1
+; GCN-NEXT:    v_or_b32_e32 v1, v2, v3
+; GCN-NEXT:    v_or_b32_e32 v2, v4, v5
+; GCN-NEXT:    v_or_b32_e32 v3, v6, v7
+; GCN-NEXT:    v_or_b32_e32 v4, v8, v9
+; GCN-NEXT:    v_or_b32_e32 v5, v10, v11
+; GCN-NEXT:    v_or_b32_e32 v6, v12, v13
+; GCN-NEXT:    v_or_b32_e32 v7, v14, v15
+; GCN-NEXT:    v_or_b32_e32 v8, v16, v17
+; GCN-NEXT:    v_or_b32_e32 v9, v18, v19
+; GCN-NEXT:    ; implicit-def: $vgpr31
+; GCN-NEXT:    ; implicit-def: $vgpr32
+; GCN-NEXT:    ; implicit-def: $vgpr33
+; GCN-NEXT:    ; implicit-def: $vgpr34
+; GCN-NEXT:    ; implicit-def: $vgpr35
 ; GCN-NEXT:    ; implicit-def: $vgpr10
 ; GCN-NEXT:    ; implicit-def: $vgpr12
 ; GCN-NEXT:    ; implicit-def: $vgpr14
@@ -8071,283 +5045,247 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) {
 ; GCN-NEXT:    ; implicit-def: $vgpr26
 ; GCN-NEXT:    ; implicit-def: $vgpr28
 ; GCN-NEXT:    ; implicit-def: $vgpr30
-; GCN-NEXT:    ; implicit-def: $vgpr56
-; GCN-NEXT:    ; implicit-def: $vgpr59
-; GCN-NEXT:    ; implicit-def: $vgpr58
-; GCN-NEXT:    ; implicit-def: $vgpr57
-; GCN-NEXT:    ; implicit-def: $vgpr53
-; GCN-NEXT:    ; implicit-def: $vgpr36
-; GCN-NEXT:    ; implicit-def: $vgpr37
+; GCN-NEXT:    ; implicit-def: $vgpr41
+; GCN-NEXT:    ; implicit-def: $vgpr40
 ; GCN-NEXT:    ; implicit-def: $vgpr55
+; GCN-NEXT:    ; implicit-def: $vgpr54
 ; GCN-NEXT:    ; implicit-def: $vgpr38
+; GCN-NEXT:    ; implicit-def: $vgpr36
 ; GCN-NEXT:    ; implicit-def: $vgpr39
-; GCN-NEXT:    ; implicit-def: $vgpr40
+; GCN-NEXT:    ; implicit-def: $vgpr37
 ; GCN-NEXT:    ; implicit-def: $vgpr48
+; GCN-NEXT:    ; implicit-def: $vgpr11
 ; GCN-NEXT:    ; implicit-def: $vgpr49
-; GCN-NEXT:    ; implicit-def: $vgpr42
-; GCN-NEXT:    ; implicit-def: $vgpr51
+; GCN-NEXT:    ; implicit-def: $vgpr13
 ; GCN-NEXT:    ; implicit-def: $vgpr50
-; GCN-NEXT:    ; implicit-def: $vgpr46
+; GCN-NEXT:    ; implicit-def: $vgpr15
+; GCN-NEXT:    ; implicit-def: $vgpr51
+; GCN-NEXT:    ; implicit-def: $vgpr17
 ; GCN-NEXT:    ; implicit-def: $vgpr52
-; GCN-NEXT:    ; implicit-def: $vgpr54
-; GCN-NEXT:    ; implicit-def: $vgpr41
-; GCN-NEXT:    ; implicit-def: $vgpr43
-; GCN-NEXT:    ; implicit-def: $vgpr44
-; GCN-NEXT:    ; implicit-def: $vgpr45
-; GCN-NEXT:    ; implicit-def: $vgpr47
-; GCN-NEXT:  .LBB25_2: ; %Flow
+; GCN-NEXT:    ; implicit-def: $vgpr19
+; GCN-NEXT:    ; implicit-def: $vgpr27
+; GCN-NEXT:    ; implicit-def: $vgpr21
+; GCN-NEXT:    ; implicit-def: $vgpr29
+; GCN-NEXT:    ; implicit-def: $vgpr23
+; GCN-NEXT:    ; implicit-def: $vgpr53
+; GCN-NEXT:    ; implicit-def: $vgpr25
+; GCN-NEXT:  .LBB13_2: ; %Flow
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB25_4
+; GCN-NEXT:    s_cbranch_execz .LBB13_4
 ; GCN-NEXT:  ; %bb.3: ; %cmp.true
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, 3, v56
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, 3, v31
 ; GCN-NEXT:    s_movk_i32 s6, 0x300
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, 3, v59
+; GCN-NEXT:    v_add_i32_e32 v1, vcc, 3, v32
 ; GCN-NEXT:    s_mov_b32 s7, 0x3000000
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, 3, v58
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, 3, v57
-; GCN-NEXT:    v_add_i32_e32 v9, vcc, 3, v24
-; GCN-NEXT:    v_add_i32_e32 v11, vcc, 3, v26
-; GCN-NEXT:    v_add_i32_e32 v13, vcc, 3, v28
-; GCN-NEXT:    v_add_i32_e32 v15, vcc, 3, v30
-; GCN-NEXT:    v_add_i32_e32 v16, vcc, 3, v16
-; GCN-NEXT:    v_add_i32_e32 v17, vcc, 3, v18
-; GCN-NEXT:    v_add_i32_e32 v18, vcc, 3, v20
-; GCN-NEXT:    v_add_i32_e32 v19, vcc, 3, v22
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, 3, v8
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, 3, v10
-; GCN-NEXT:    v_add_i32_e32 v12, vcc, 3, v12
-; GCN-NEXT:    v_add_i32_e32 v14, vcc, 3, v14
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, 3, v0
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, 3, v2
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, 3, v4
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, 3, v6
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, 3, v33
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, 3, v34
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, 3, v35
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, 3, v10
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, 3, v12
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, 3, v14
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, 3, v16
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, 3, v18
+; GCN-NEXT:    v_add_i32_e32 v10, vcc, 3, v20
+; GCN-NEXT:    v_add_i32_e32 v12, vcc, 3, v22
+; GCN-NEXT:    v_add_i32_e32 v14, vcc, 3, v24
+; GCN-NEXT:    v_add_i32_e32 v16, vcc, 3, v26
+; GCN-NEXT:    v_add_i32_e32 v18, vcc, 3, v28
+; GCN-NEXT:    v_add_i32_e32 v20, vcc, 3, v30
+; GCN-NEXT:    v_add_i32_e32 v22, vcc, 3, v41
+; GCN-NEXT:    v_add_i32_e32 v24, vcc, 3, v40
+; GCN-NEXT:    v_add_i32_e32 v26, vcc, 3, v55
+; GCN-NEXT:    v_add_i32_e32 v28, vcc, 3, v54
+; GCN-NEXT:    v_and_b32_e32 v0, 0xff, v0
 ; GCN-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GCN-NEXT:    v_and_b32_e32 v2, 0xff, v2
 ; GCN-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GCN-NEXT:    v_and_b32_e32 v4, 0xff, v4
 ; GCN-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GCN-NEXT:    v_and_b32_e32 v6, 0xff, v6
 ; GCN-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GCN-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GCN-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GCN-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GCN-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GCN-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GCN-NEXT:    v_and_b32_e32 v17, 0xff, v17
-; GCN-NEXT:    v_and_b32_e32 v18, 0xff, v18
-; GCN-NEXT:    v_and_b32_e32 v19, 0xff, v19
 ; GCN-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GCN-NEXT:    v_and_b32_e32 v9, 0xff, v9
 ; GCN-NEXT:    v_and_b32_e32 v10, 0xff, v10
 ; GCN-NEXT:    v_and_b32_e32 v12, 0xff, v12
 ; GCN-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GCN-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GCN-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GCN-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GCN-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GCN-NEXT:    v_or_b32_e32 v1, v47, v1
+; GCN-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GCN-NEXT:    v_and_b32_e32 v18, 0xff, v18
+; GCN-NEXT:    v_and_b32_e32 v20, 0xff, v20
+; GCN-NEXT:    v_and_b32_e32 v22, 0xff, v22
+; GCN-NEXT:    v_and_b32_e32 v24, 0xff, v24
+; GCN-NEXT:    v_and_b32_e32 v26, 0xff, v26
+; GCN-NEXT:    v_and_b32_e32 v28, 0xff, v28
+; GCN-NEXT:    v_or_b32_e32 v0, v38, v0
+; GCN-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GCN-NEXT:    v_or_b32_e32 v2, v39, v2
 ; GCN-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GCN-NEXT:    v_or_b32_e32 v5, v46, v5
+; GCN-NEXT:    v_or_b32_e32 v4, v48, v4
+; GCN-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GCN-NEXT:    v_or_b32_e32 v6, v49, v6
 ; GCN-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GCN-NEXT:    v_or_b32_e32 v9, v45, v9
-; GCN-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GCN-NEXT:    v_or_b32_e32 v13, v42, v13
-; GCN-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GCN-NEXT:    v_or_b32_e32 v16, v44, v16
-; GCN-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GCN-NEXT:    v_or_b32_e32 v18, v40, v18
-; GCN-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GCN-NEXT:    v_or_b32_e32 v8, v43, v8
-; GCN-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GCN-NEXT:    v_or_b32_e32 v12, v55, v12
-; GCN-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GCN-NEXT:    v_or_b32_e32 v0, v41, v0
-; GCN-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GCN-NEXT:    v_or_b32_e32 v4, v53, v4
-; GCN-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, 0x300, v1
-; GCN-NEXT:    v_or_b32_e32 v3, v54, v3
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, s6, v5
-; GCN-NEXT:    v_or_b32_e32 v7, v52, v7
-; GCN-NEXT:    v_add_i32_e32 v9, vcc, s6, v9
-; GCN-NEXT:    v_or_b32_e32 v11, v50, v11
-; GCN-NEXT:    v_add_i32_e32 v13, vcc, s6, v13
-; GCN-NEXT:    v_or_b32_e32 v15, v51, v15
-; GCN-NEXT:    v_add_i32_e32 v16, vcc, s6, v16
-; GCN-NEXT:    v_or_b32_e32 v17, v49, v17
-; GCN-NEXT:    v_add_i32_e32 v18, vcc, s6, v18
-; GCN-NEXT:    v_or_b32_e32 v19, v48, v19
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, s6, v8
-; GCN-NEXT:    v_or_b32_e32 v10, v39, v10
-; GCN-NEXT:    v_add_i32_e32 v12, vcc, s6, v12
-; GCN-NEXT:    v_or_b32_e32 v14, v38, v14
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, s6, v0
-; GCN-NEXT:    v_or_b32_e32 v2, v37, v2
+; GCN-NEXT:    v_or_b32_e32 v8, v50, v8
+; GCN-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GCN-NEXT:    v_or_b32_e32 v10, v51, v10
+; GCN-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GCN-NEXT:    v_or_b32_e32 v14, v52, v14
+; GCN-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GCN-NEXT:    v_or_b32_e32 v18, v27, v18
+; GCN-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GCN-NEXT:    v_or_b32_e32 v22, v29, v22
+; GCN-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GCN-NEXT:    v_or_b32_e32 v26, v53, v26
+; GCN-NEXT:    v_lshlrev_b32_e32 v27, 16, v28
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, 0x300, v0
+; GCN-NEXT:    v_or_b32_e32 v1, v36, v1
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, s6, v2
+; GCN-NEXT:    v_or_b32_e32 v3, v37, v3
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, s6, v4
-; GCN-NEXT:    v_or_b32_e32 v6, v36, v6
-; GCN-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GCN-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GCN-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GCN-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GCN-NEXT:    v_and_b32_e32 v16, 0xffff, v16
-; GCN-NEXT:    v_and_b32_e32 v18, 0xffff, v18
-; GCN-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GCN-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GCN-NEXT:    v_or_b32_e32 v5, v11, v5
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, s6, v6
+; GCN-NEXT:    v_or_b32_e32 v7, v13, v7
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, s6, v8
+; GCN-NEXT:    v_or_b32_e32 v9, v15, v9
+; GCN-NEXT:    v_add_i32_e32 v10, vcc, s6, v10
+; GCN-NEXT:    v_or_b32_e32 v11, v17, v12
+; GCN-NEXT:    v_add_i32_e32 v12, vcc, s6, v14
+; GCN-NEXT:    v_or_b32_e32 v13, v19, v16
+; GCN-NEXT:    v_add_i32_e32 v14, vcc, s6, v18
+; GCN-NEXT:    v_or_b32_e32 v15, v21, v20
+; GCN-NEXT:    v_add_i32_e32 v16, vcc, s6, v22
+; GCN-NEXT:    v_or_b32_e32 v17, v23, v24
+; GCN-NEXT:    v_add_i32_e32 v18, vcc, 0x300, v26
+; GCN-NEXT:    v_or_b32_e32 v19, v25, v27
 ; GCN-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GCN-NEXT:    v_and_b32_e32 v2, 0xffff, v2
 ; GCN-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GCN-NEXT:    v_or_b32_e32 v1, v3, v1
-; GCN-NEXT:    v_or_b32_e32 v3, v7, v5
-; GCN-NEXT:    v_or_b32_e32 v5, v11, v9
-; GCN-NEXT:    v_or_b32_e32 v7, v15, v13
-; GCN-NEXT:    v_or_b32_e32 v9, v17, v16
-; GCN-NEXT:    v_or_b32_e32 v11, v19, v18
-; GCN-NEXT:    v_or_b32_e32 v8, v10, v8
-; GCN-NEXT:    v_or_b32_e32 v10, v14, v12
-; GCN-NEXT:    v_or_b32_e32 v0, v2, v0
-; GCN-NEXT:    v_or_b32_e32 v2, v6, v4
-; GCN-NEXT:    v_add_i32_e32 v34, vcc, s7, v1
-; GCN-NEXT:    v_add_i32_e32 v35, vcc, s7, v3
-; GCN-NEXT:    v_add_i32_e32 v32, vcc, s7, v5
-; GCN-NEXT:    v_add_i32_e32 v33, vcc, s7, v7
-; GCN-NEXT:    v_add_i32_e32 v29, vcc, s7, v9
-; GCN-NEXT:    v_add_i32_e32 v31, vcc, s7, v11
-; GCN-NEXT:    v_add_i32_e32 v25, vcc, s7, v8
-; GCN-NEXT:    v_add_i32_e32 v27, vcc, s7, v10
-; GCN-NEXT:    v_add_i32_e32 v21, vcc, s7, v0
-; GCN-NEXT:    v_add_i32_e32 v23, vcc, s7, v2
-; GCN-NEXT:    v_alignbit_b32 v1, v23, v21, 16
-; GCN-NEXT:    v_alignbit_b32 v5, v27, v25, 16
-; GCN-NEXT:    v_alignbit_b32 v9, v31, v29, 16
-; GCN-NEXT:    v_alignbit_b32 v13, v33, v32, 16
-; GCN-NEXT:    v_alignbit_b32 v17, v35, v34, 16
-; GCN-NEXT:    v_lshrrev_b32_e32 v3, 16, v23
-; GCN-NEXT:    v_lshrrev_b32_e32 v7, 16, v27
-; GCN-NEXT:    v_lshrrev_b32_e32 v11, 16, v31
-; GCN-NEXT:    v_lshrrev_b32_e32 v15, 16, v33
-; GCN-NEXT:    v_lshrrev_b32_e32 v19, 16, v35
-; GCN-NEXT:  .LBB25_4: ; %end
+; GCN-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GCN-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GCN-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GCN-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GCN-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GCN-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GCN-NEXT:    v_and_b32_e32 v18, 0xffff, v18
+; GCN-NEXT:    v_or_b32_e32 v0, v1, v0
+; GCN-NEXT:    v_or_b32_e32 v1, v3, v2
+; GCN-NEXT:    v_or_b32_e32 v2, v5, v4
+; GCN-NEXT:    v_or_b32_e32 v3, v7, v6
+; GCN-NEXT:    v_or_b32_e32 v4, v9, v8
+; GCN-NEXT:    v_or_b32_e32 v5, v11, v10
+; GCN-NEXT:    v_or_b32_e32 v6, v13, v12
+; GCN-NEXT:    v_or_b32_e32 v7, v15, v14
+; GCN-NEXT:    v_or_b32_e32 v8, v17, v16
+; GCN-NEXT:    v_or_b32_e32 v9, v19, v18
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, s7, v0
+; GCN-NEXT:    v_add_i32_e32 v1, vcc, s7, v1
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, s7, v2
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, s7, v3
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, s7, v4
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, s7, v5
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, s7, v6
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, s7, v7
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, 0x3000000, v8
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, 0x3000000, v9
+; GCN-NEXT:  .LBB13_4: ; %end
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GCN-NEXT:    v_mov_b32_e32 v0, v21
-; GCN-NEXT:    v_mov_b32_e32 v2, v23
-; GCN-NEXT:    v_mov_b32_e32 v4, v25
-; GCN-NEXT:    v_mov_b32_e32 v6, v27
-; GCN-NEXT:    v_mov_b32_e32 v8, v29
-; GCN-NEXT:    v_mov_b32_e32 v10, v31
-; GCN-NEXT:    v_mov_b32_e32 v12, v32
-; GCN-NEXT:    v_mov_b32_e32 v14, v33
-; GCN-NEXT:    v_mov_b32_e32 v16, v34
-; GCN-NEXT:    v_mov_b32_e32 v18, v35
-; GCN-NEXT:    buffer_load_dword v59, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v58, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v57, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v56, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v47, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v46, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v45, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
-; VI-LABEL: bitcast_v40i8_to_v20i16:
+; VI-LABEL: bitcast_v40i8_to_v10f32:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; VI-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; VI-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; VI-NEXT:    buffer_store_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; VI-NEXT:    buffer_store_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; VI-NEXT:    buffer_store_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; VI-NEXT:    buffer_store_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; VI-NEXT:    buffer_store_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; VI-NEXT:    v_mov_b32_e32 v34, v10
-; VI-NEXT:    v_mov_b32_e32 v33, v8
-; VI-NEXT:    v_mov_b32_e32 v35, v6
-; VI-NEXT:    v_mov_b32_e32 v38, v4
+; VI-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; VI-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; VI-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; VI-NEXT:    buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; VI-NEXT:    buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; VI-NEXT:    v_mov_b32_e32 v35, v8
+; VI-NEXT:    v_mov_b32_e32 v34, v6
+; VI-NEXT:    v_mov_b32_e32 v33, v4
 ; VI-NEXT:    v_mov_b32_e32 v32, v2
-; VI-NEXT:    v_mov_b32_e32 v36, v0
+; VI-NEXT:    v_mov_b32_e32 v31, v0
 ; VI-NEXT:    buffer_load_ushort v0, off, s[0:3], s32 offset:16
 ; VI-NEXT:    buffer_load_ushort v2, off, s[0:3], s32 offset:8
 ; VI-NEXT:    buffer_load_ushort v4, off, s[0:3], s32
 ; VI-NEXT:    buffer_load_dword v6, off, s[0:3], s32 offset:36
 ; VI-NEXT:    buffer_load_ushort v8, off, s[0:3], s32 offset:32
-; VI-NEXT:    buffer_load_ushort v55, off, s[0:3], s32 offset:28
-; VI-NEXT:    buffer_load_ushort v10, off, s[0:3], s32 offset:24
-; VI-NEXT:    buffer_load_ushort v54, off, s[0:3], s32 offset:20
-; VI-NEXT:    buffer_load_ushort v53, off, s[0:3], s32 offset:12
-; VI-NEXT:    buffer_load_ushort v51, off, s[0:3], s32 offset:4
-; VI-NEXT:    v_mov_b32_e32 v31, v14
-; VI-NEXT:    v_mov_b32_e32 v37, v12
-; VI-NEXT:    v_lshlrev_b16_e32 v39, 8, v1
-; VI-NEXT:    v_lshlrev_b16_e32 v48, 8, v3
-; VI-NEXT:    v_lshlrev_b16_e32 v49, 8, v5
-; VI-NEXT:    v_lshlrev_b16_e32 v50, 8, v7
-; VI-NEXT:    v_lshlrev_b16_e32 v52, 8, v9
-; VI-NEXT:    v_lshlrev_b16_e32 v40, 8, v11
-; VI-NEXT:    v_lshlrev_b16_e32 v41, 8, v13
-; VI-NEXT:    v_lshlrev_b16_e32 v42, 8, v15
-; VI-NEXT:    v_lshlrev_b16_e32 v17, 8, v17
-; VI-NEXT:    v_lshlrev_b16_e32 v19, 8, v19
-; VI-NEXT:    v_lshlrev_b16_e32 v21, 8, v21
-; VI-NEXT:    v_lshlrev_b16_e32 v23, 8, v23
+; VI-NEXT:    buffer_load_ushort v36, off, s[0:3], s32 offset:28
+; VI-NEXT:    buffer_load_ushort v44, off, s[0:3], s32 offset:24
+; VI-NEXT:    buffer_load_ushort v37, off, s[0:3], s32 offset:20
+; VI-NEXT:    buffer_load_ushort v38, off, s[0:3], s32 offset:12
+; VI-NEXT:    buffer_load_ushort v39, off, s[0:3], s32 offset:4
+; VI-NEXT:    v_lshlrev_b16_e32 v43, 8, v1
+; VI-NEXT:    v_lshlrev_b16_e32 v42, 8, v3
+; VI-NEXT:    v_lshlrev_b16_e32 v41, 8, v5
+; VI-NEXT:    v_lshlrev_b16_e32 v40, 8, v7
+; VI-NEXT:    v_lshlrev_b16_e32 v55, 8, v9
+; VI-NEXT:    v_lshlrev_b16_e32 v54, 8, v11
+; VI-NEXT:    v_lshlrev_b16_e32 v53, 8, v13
+; VI-NEXT:    v_lshlrev_b16_e32 v52, 8, v15
+; VI-NEXT:    v_lshlrev_b16_e32 v51, 8, v17
+; VI-NEXT:    v_lshlrev_b16_e32 v50, 8, v19
+; VI-NEXT:    v_lshlrev_b16_e32 v49, 8, v21
+; VI-NEXT:    v_lshlrev_b16_e32 v48, 8, v23
 ; VI-NEXT:    v_lshlrev_b16_e32 v25, 8, v25
-; VI-NEXT:    v_lshlrev_b16_e32 v27, 8, v27
-; VI-NEXT:    v_lshlrev_b16_e32 v29, 8, v29
+; VI-NEXT:    v_lshlrev_b16_e32 v23, 8, v27
+; VI-NEXT:    v_lshlrev_b16_e32 v21, 8, v29
 ; VI-NEXT:    s_waitcnt vmcnt(9)
-; VI-NEXT:    v_lshlrev_b16_e32 v45, 8, v0
+; VI-NEXT:    v_lshlrev_b16_e32 v15, 8, v0
 ; VI-NEXT:    s_waitcnt vmcnt(8)
-; VI-NEXT:    v_lshlrev_b16_e32 v44, 8, v2
+; VI-NEXT:    v_lshlrev_b16_e32 v17, 8, v2
 ; VI-NEXT:    s_waitcnt vmcnt(7)
-; VI-NEXT:    v_lshlrev_b16_e32 v43, 8, v4
+; VI-NEXT:    v_lshlrev_b16_e32 v19, 8, v4
 ; VI-NEXT:    s_waitcnt vmcnt(6)
 ; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
 ; VI-NEXT:    s_waitcnt vmcnt(5)
-; VI-NEXT:    v_lshlrev_b16_e32 v47, 8, v8
+; VI-NEXT:    v_lshlrev_b16_e32 v11, 8, v8
+; VI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
 ; VI-NEXT:    s_waitcnt vmcnt(3)
-; VI-NEXT:    v_lshlrev_b16_e32 v46, 8, v10
-; VI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; VI-NEXT:    v_lshlrev_b16_e32 v13, 8, v44
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB25_2
+; VI-NEXT:    s_cbranch_execz .LBB13_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.false
-; VI-NEXT:    v_or_b32_sdwa v0, v36, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v1, v32, v48 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v0, v31, v43 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v1, v32, v42 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v1, v38, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v2, v35, v50 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v1, v33, v41 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v2, v34, v40 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v2, v33, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v3, v34, v40 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v2, v35, v55 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v3, v10, v54 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v3, v37, v41 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v4, v31, v42 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v3, v12, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v4, v14, v52 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v4, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v5, v18, v19 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v4, v16, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v5, v18, v50 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v5, v20, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v6, v22, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v5, v20, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v6, v22, v48 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_sdwa v6, v24, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v7, v26, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v7, v26, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v7, v28, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v8, v30, v43 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v7, v28, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v8, v30, v19 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; VI-NEXT:    s_waitcnt vmcnt(0)
-; VI-NEXT:    v_or_b32_sdwa v8, v51, v44 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v9, v53, v45 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v8, v39, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v9, v38, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_sdwa v8, v8, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v9, v54, v46 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_sdwa v10, v55, v47 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v9, v37, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v10, v36, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_sdwa v9, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT:    ; implicit-def: $vgpr36
+; VI-NEXT:    ; implicit-def: $vgpr31
 ; VI-NEXT:    ; implicit-def: $vgpr32
-; VI-NEXT:    ; implicit-def: $vgpr38
-; VI-NEXT:    ; implicit-def: $vgpr35
 ; VI-NEXT:    ; implicit-def: $vgpr33
 ; VI-NEXT:    ; implicit-def: $vgpr34
-; VI-NEXT:    ; implicit-def: $vgpr37
-; VI-NEXT:    ; implicit-def: $vgpr31
+; VI-NEXT:    ; implicit-def: $vgpr35
+; VI-NEXT:    ; implicit-def: $vgpr10
+; VI-NEXT:    ; implicit-def: $vgpr12
+; VI-NEXT:    ; implicit-def: $vgpr14
 ; VI-NEXT:    ; implicit-def: $vgpr16
 ; VI-NEXT:    ; implicit-def: $vgpr18
 ; VI-NEXT:    ; implicit-def: $vgpr20
@@ -8356,222 +5294,210 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) {
 ; VI-NEXT:    ; implicit-def: $vgpr26
 ; VI-NEXT:    ; implicit-def: $vgpr28
 ; VI-NEXT:    ; implicit-def: $vgpr30
-; VI-NEXT:    ; implicit-def: $vgpr51
-; VI-NEXT:    ; implicit-def: $vgpr53
-; VI-NEXT:    ; implicit-def: $vgpr54
-; VI-NEXT:    ; implicit-def: $vgpr55
 ; VI-NEXT:    ; implicit-def: $vgpr39
-; VI-NEXT:    ; implicit-def: $vgpr48
-; VI-NEXT:    ; implicit-def: $vgpr49
-; VI-NEXT:    ; implicit-def: $vgpr50
-; VI-NEXT:    ; implicit-def: $vgpr52
-; VI-NEXT:    ; implicit-def: $vgpr40
-; VI-NEXT:    ; implicit-def: $vgpr41
+; VI-NEXT:    ; implicit-def: $vgpr38
+; VI-NEXT:    ; implicit-def: $vgpr37
+; VI-NEXT:    ; implicit-def: $vgpr36
+; VI-NEXT:    ; implicit-def: $vgpr43
 ; VI-NEXT:    ; implicit-def: $vgpr42
-; VI-NEXT:    ; implicit-def: $vgpr17
-; VI-NEXT:    ; implicit-def: $vgpr19
-; VI-NEXT:    ; implicit-def: $vgpr21
-; VI-NEXT:    ; implicit-def: $vgpr23
+; VI-NEXT:    ; implicit-def: $vgpr41
+; VI-NEXT:    ; implicit-def: $vgpr40
+; VI-NEXT:    ; implicit-def: $vgpr55
+; VI-NEXT:    ; implicit-def: $vgpr54
+; VI-NEXT:    ; implicit-def: $vgpr53
+; VI-NEXT:    ; implicit-def: $vgpr52
+; VI-NEXT:    ; implicit-def: $vgpr51
+; VI-NEXT:    ; implicit-def: $vgpr50
+; VI-NEXT:    ; implicit-def: $vgpr49
+; VI-NEXT:    ; implicit-def: $vgpr48
 ; VI-NEXT:    ; implicit-def: $vgpr25
-; VI-NEXT:    ; implicit-def: $vgpr27
-; VI-NEXT:    ; implicit-def: $vgpr29
-; VI-NEXT:    ; implicit-def: $vgpr43
-; VI-NEXT:    ; implicit-def: $vgpr44
-; VI-NEXT:    ; implicit-def: $vgpr45
-; VI-NEXT:    ; implicit-def: $vgpr46
-; VI-NEXT:    ; implicit-def: $vgpr47
-; VI-NEXT:  .LBB25_2: ; %Flow
+; VI-NEXT:    ; implicit-def: $vgpr23
+; VI-NEXT:    ; implicit-def: $vgpr21
+; VI-NEXT:    ; implicit-def: $vgpr19
+; VI-NEXT:    ; implicit-def: $vgpr17
+; VI-NEXT:    ; implicit-def: $vgpr15
+; VI-NEXT:    ; implicit-def: $vgpr13
+; VI-NEXT:    ; implicit-def: $vgpr11
+; VI-NEXT:  .LBB13_2: ; %Flow
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB25_4
+; VI-NEXT:    s_cbranch_execz .LBB13_4
 ; VI-NEXT:  ; %bb.3: ; %cmp.true
-; VI-NEXT:    v_add_u16_e32 v0, 3, v55
-; VI-NEXT:    v_or_b32_sdwa v0, v47, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_mov_b32_e32 v1, 0x300
-; VI-NEXT:    v_add_u16_sdwa v9, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-NEXT:    s_waitcnt vmcnt(2)
-; VI-NEXT:    v_add_u16_e32 v0, 3, v54
-; VI-NEXT:    v_or_b32_sdwa v10, v46, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    s_waitcnt vmcnt(1)
-; VI-NEXT:    v_add_u16_e32 v0, 3, v53
-; VI-NEXT:    v_or_b32_sdwa v0, v45, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_add_u16_sdwa v8, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-NEXT:    s_waitcnt vmcnt(0)
-; VI-NEXT:    v_add_u16_e32 v0, 3, v51
-; VI-NEXT:    v_or_b32_sdwa v11, v44, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_add_u16_e32 v0, 3, v30
-; VI-NEXT:    v_or_b32_sdwa v0, v43, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_add_u16_sdwa v7, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-NEXT:    v_add_u16_e32 v0, 3, v28
-; VI-NEXT:    v_or_b32_sdwa v12, v29, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_add_u16_e32 v0, 3, v26
-; VI-NEXT:    v_or_b32_sdwa v0, v27, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_add_u16_sdwa v6, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-NEXT:    v_add_u16_e32 v0, 3, v24
-; VI-NEXT:    v_or_b32_sdwa v13, v25, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_add_u16_e32 v0, 3, v22
-; VI-NEXT:    v_or_b32_sdwa v0, v23, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_add_u16_sdwa v5, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-NEXT:    v_add_u16_e32 v0, 3, v20
-; VI-NEXT:    v_or_b32_sdwa v14, v21, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_add_u16_e32 v0, 3, v18
-; VI-NEXT:    v_or_b32_sdwa v0, v19, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_add_u16_sdwa v4, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-NEXT:    v_add_u16_e32 v0, 3, v16
-; VI-NEXT:    v_or_b32_sdwa v15, v17, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
 ; VI-NEXT:    v_add_u16_e32 v0, 3, v31
-; VI-NEXT:    v_or_b32_sdwa v0, v42, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_add_u16_sdwa v3, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-NEXT:    v_add_u16_e32 v0, 3, v37
-; VI-NEXT:    v_or_b32_sdwa v16, v41, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_add_u16_e32 v0, 3, v34
-; VI-NEXT:    v_or_b32_sdwa v0, v40, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_add_u16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-NEXT:    v_add_u16_e32 v0, 3, v33
-; VI-NEXT:    v_or_b32_sdwa v17, v52, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_add_u16_e32 v0, 3, v35
-; VI-NEXT:    v_or_b32_sdwa v0, v50, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_add_u16_sdwa v18, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-NEXT:    v_add_u16_e32 v0, 3, v38
-; VI-NEXT:    v_or_b32_sdwa v19, v49, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_add_u16_e32 v0, 3, v32
-; VI-NEXT:    v_or_b32_sdwa v0, v48, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT:    v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-NEXT:    v_add_u16_e32 v1, 3, v36
-; VI-NEXT:    v_or_b32_sdwa v1, v39, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; VI-NEXT:    v_add_u16_e32 v1, 3, v32
+; VI-NEXT:    v_or_b32_sdwa v0, v43, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; VI-NEXT:    v_or_b32_sdwa v1, v42, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; VI-NEXT:    v_mov_b32_e32 v9, 0x300
+; VI-NEXT:    v_add_u16_e32 v0, 0x300, v0
+; VI-NEXT:    v_add_u16_sdwa v1, v1, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; VI-NEXT:    v_or_b32_e32 v0, v0, v1
+; VI-NEXT:    v_add_u16_e32 v1, 3, v33
+; VI-NEXT:    v_add_u16_e32 v2, 3, v34
+; VI-NEXT:    v_or_b32_sdwa v1, v41, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; VI-NEXT:    v_or_b32_sdwa v2, v40, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
 ; VI-NEXT:    v_add_u16_e32 v1, 0x300, v1
-; VI-NEXT:    v_or_b32_e32 v0, v1, v0
-; VI-NEXT:    v_add_u16_e32 v1, 0x300, v19
-; VI-NEXT:    v_add_u16_e32 v17, 0x300, v17
-; VI-NEXT:    v_add_u16_e32 v16, 0x300, v16
-; VI-NEXT:    v_add_u16_e32 v15, 0x300, v15
-; VI-NEXT:    v_add_u16_e32 v14, 0x300, v14
-; VI-NEXT:    v_add_u16_e32 v13, 0x300, v13
-; VI-NEXT:    v_add_u16_e32 v12, 0x300, v12
-; VI-NEXT:    v_add_u16_e32 v11, 0x300, v11
+; VI-NEXT:    v_add_u16_sdwa v2, v2, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; VI-NEXT:    v_or_b32_e32 v1, v1, v2
+; VI-NEXT:    v_add_u16_e32 v2, 3, v35
+; VI-NEXT:    v_add_u16_e32 v3, 3, v10
+; VI-NEXT:    v_or_b32_sdwa v2, v55, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; VI-NEXT:    v_or_b32_sdwa v3, v54, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; VI-NEXT:    v_add_u16_e32 v2, 0x300, v2
+; VI-NEXT:    v_add_u16_sdwa v3, v3, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; VI-NEXT:    v_or_b32_e32 v2, v2, v3
+; VI-NEXT:    v_add_u16_e32 v3, 3, v12
+; VI-NEXT:    v_add_u16_e32 v4, 3, v14
+; VI-NEXT:    v_or_b32_sdwa v3, v53, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; VI-NEXT:    v_or_b32_sdwa v4, v52, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; VI-NEXT:    v_add_u16_e32 v3, 0x300, v3
+; VI-NEXT:    v_add_u16_sdwa v4, v4, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; VI-NEXT:    v_or_b32_e32 v3, v3, v4
+; VI-NEXT:    v_add_u16_e32 v4, 3, v16
+; VI-NEXT:    v_add_u16_e32 v5, 3, v18
+; VI-NEXT:    v_or_b32_sdwa v4, v51, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; VI-NEXT:    v_or_b32_sdwa v5, v50, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; VI-NEXT:    v_add_u16_e32 v4, 0x300, v4
+; VI-NEXT:    v_add_u16_sdwa v5, v5, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; VI-NEXT:    v_or_b32_e32 v4, v4, v5
+; VI-NEXT:    v_add_u16_e32 v5, 3, v20
+; VI-NEXT:    v_add_u16_e32 v6, 3, v22
+; VI-NEXT:    v_or_b32_sdwa v5, v49, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; VI-NEXT:    v_or_b32_sdwa v6, v48, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; VI-NEXT:    v_add_u16_e32 v5, 0x300, v5
+; VI-NEXT:    v_add_u16_sdwa v6, v6, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; VI-NEXT:    v_or_b32_e32 v5, v5, v6
+; VI-NEXT:    v_add_u16_e32 v6, 3, v24
+; VI-NEXT:    v_add_u16_e32 v7, 3, v26
+; VI-NEXT:    v_or_b32_sdwa v6, v25, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; VI-NEXT:    v_or_b32_sdwa v7, v23, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; VI-NEXT:    v_add_u16_e32 v6, 0x300, v6
+; VI-NEXT:    v_add_u16_sdwa v7, v7, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; VI-NEXT:    v_or_b32_e32 v6, v6, v7
+; VI-NEXT:    v_add_u16_e32 v7, 3, v28
+; VI-NEXT:    v_add_u16_e32 v8, 3, v30
+; VI-NEXT:    v_or_b32_sdwa v7, v21, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; VI-NEXT:    v_or_b32_sdwa v8, v19, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; VI-NEXT:    v_add_u16_e32 v7, 0x300, v7
+; VI-NEXT:    v_add_u16_sdwa v8, v8, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; VI-NEXT:    v_or_b32_e32 v7, v7, v8
+; VI-NEXT:    s_waitcnt vmcnt(0)
+; VI-NEXT:    v_add_u16_e32 v8, 3, v39
+; VI-NEXT:    v_add_u16_e32 v10, 3, v38
+; VI-NEXT:    v_or_b32_sdwa v8, v17, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; VI-NEXT:    v_or_b32_sdwa v10, v15, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; VI-NEXT:    v_add_u16_e32 v8, 0x300, v8
+; VI-NEXT:    v_add_u16_sdwa v10, v10, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; VI-NEXT:    v_or_b32_e32 v8, v8, v10
+; VI-NEXT:    v_add_u16_e32 v10, 3, v37
+; VI-NEXT:    v_add_u16_e32 v12, 3, v36
+; VI-NEXT:    v_or_b32_sdwa v10, v13, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; VI-NEXT:    v_or_b32_sdwa v11, v11, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
 ; VI-NEXT:    v_add_u16_e32 v10, 0x300, v10
-; VI-NEXT:    v_or_b32_e32 v1, v1, v18
-; VI-NEXT:    v_or_b32_e32 v2, v17, v2
-; VI-NEXT:    v_or_b32_e32 v3, v16, v3
-; VI-NEXT:    v_or_b32_e32 v4, v15, v4
-; VI-NEXT:    v_or_b32_e32 v5, v14, v5
-; VI-NEXT:    v_or_b32_e32 v6, v13, v6
-; VI-NEXT:    v_or_b32_e32 v7, v12, v7
-; VI-NEXT:    v_or_b32_e32 v8, v11, v8
+; VI-NEXT:    v_add_u16_sdwa v9, v11, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_e32 v9, v10, v9
-; VI-NEXT:  .LBB25_4: ; %end
+; VI-NEXT:  .LBB13_4: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
-; VI-NEXT:    buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
-; VI-NEXT:    buffer_load_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
-; VI-NEXT:    buffer_load_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
-; VI-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
-; VI-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
-; VI-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
-; VI-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; VI-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; VI-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
+; VI-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
+; VI-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
+; VI-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
+; VI-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
 ; VI-NEXT:    s_waitcnt vmcnt(0)
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX9-LABEL: bitcast_v40i8_to_v20i16:
+; GFX9-LABEL: bitcast_v40i8_to_v10f32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; GFX9-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; GFX9-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; GFX9-NEXT:    buffer_store_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; GFX9-NEXT:    buffer_store_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; GFX9-NEXT:    buffer_store_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; GFX9-NEXT:    buffer_store_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT:    buffer_store_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT:    v_mov_b32_e32 v31, v10
-; GFX9-NEXT:    v_mov_b32_e32 v32, v8
-; GFX9-NEXT:    v_mov_b32_e32 v38, v6
-; GFX9-NEXT:    v_mov_b32_e32 v35, v4
-; GFX9-NEXT:    v_mov_b32_e32 v33, v2
-; GFX9-NEXT:    v_mov_b32_e32 v36, v0
+; GFX9-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; GFX9-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; GFX9-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; GFX9-NEXT:    buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT:    buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT:    v_mov_b32_e32 v35, v8
+; GFX9-NEXT:    v_mov_b32_e32 v34, v6
+; GFX9-NEXT:    v_mov_b32_e32 v33, v4
+; GFX9-NEXT:    v_mov_b32_e32 v32, v2
+; GFX9-NEXT:    v_mov_b32_e32 v31, v0
 ; GFX9-NEXT:    buffer_load_ushort v0, off, s[0:3], s32 offset:16
 ; GFX9-NEXT:    buffer_load_ushort v2, off, s[0:3], s32 offset:8
 ; GFX9-NEXT:    buffer_load_ushort v4, off, s[0:3], s32
-; GFX9-NEXT:    buffer_load_dword v6, off, s[0:3], s32 offset:36
-; GFX9-NEXT:    buffer_load_ushort v8, off, s[0:3], s32 offset:32
-; GFX9-NEXT:    buffer_load_ushort v54, off, s[0:3], s32 offset:28
-; GFX9-NEXT:    buffer_load_ushort v10, off, s[0:3], s32 offset:24
-; GFX9-NEXT:    buffer_load_ushort v42, off, s[0:3], s32 offset:20
-; GFX9-NEXT:    buffer_load_ushort v53, off, s[0:3], s32 offset:12
-; GFX9-NEXT:    buffer_load_ushort v55, off, s[0:3], s32 offset:4
-; GFX9-NEXT:    v_mov_b32_e32 v37, v14
-; GFX9-NEXT:    v_mov_b32_e32 v34, v12
-; GFX9-NEXT:    v_lshlrev_b16_e32 v48, 8, v1
-; GFX9-NEXT:    v_lshlrev_b16_e32 v39, 8, v3
-; GFX9-NEXT:    v_lshlrev_b16_e32 v50, 8, v5
-; GFX9-NEXT:    v_lshlrev_b16_e32 v49, 8, v7
-; GFX9-NEXT:    v_lshlrev_b16_e32 v52, 8, v9
-; GFX9-NEXT:    v_lshlrev_b16_e32 v51, 8, v11
-; GFX9-NEXT:    v_lshlrev_b16_e32 v41, 8, v13
-; GFX9-NEXT:    v_lshlrev_b16_e32 v40, 8, v15
-; GFX9-NEXT:    v_lshlrev_b16_e32 v43, 8, v17
-; GFX9-NEXT:    v_lshlrev_b16_e32 v17, 8, v19
-; GFX9-NEXT:    v_lshlrev_b16_e32 v21, 8, v21
-; GFX9-NEXT:    v_lshlrev_b16_e32 v19, 8, v23
+; GFX9-NEXT:    buffer_load_dword v6, off, s[0:3], s32 offset:36
+; GFX9-NEXT:    buffer_load_ushort v8, off, s[0:3], s32 offset:32
+; GFX9-NEXT:    buffer_load_ushort v36, off, s[0:3], s32 offset:28
+; GFX9-NEXT:    buffer_load_ushort v44, off, s[0:3], s32 offset:24
+; GFX9-NEXT:    buffer_load_ushort v37, off, s[0:3], s32 offset:20
+; GFX9-NEXT:    buffer_load_ushort v38, off, s[0:3], s32 offset:12
+; GFX9-NEXT:    buffer_load_ushort v39, off, s[0:3], s32 offset:4
+; GFX9-NEXT:    v_lshlrev_b16_e32 v43, 8, v1
+; GFX9-NEXT:    v_lshlrev_b16_e32 v42, 8, v3
+; GFX9-NEXT:    v_lshlrev_b16_e32 v41, 8, v5
+; GFX9-NEXT:    v_lshlrev_b16_e32 v40, 8, v7
+; GFX9-NEXT:    v_lshlrev_b16_e32 v55, 8, v9
+; GFX9-NEXT:    v_lshlrev_b16_e32 v54, 8, v11
+; GFX9-NEXT:    v_lshlrev_b16_e32 v53, 8, v13
+; GFX9-NEXT:    v_lshlrev_b16_e32 v52, 8, v15
+; GFX9-NEXT:    v_lshlrev_b16_e32 v51, 8, v17
+; GFX9-NEXT:    v_lshlrev_b16_e32 v50, 8, v19
+; GFX9-NEXT:    v_lshlrev_b16_e32 v49, 8, v21
+; GFX9-NEXT:    v_lshlrev_b16_e32 v48, 8, v23
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v25, 8, v25
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v23, 8, v27
-; GFX9-NEXT:    v_lshlrev_b16_e32 v29, 8, v29
+; GFX9-NEXT:    v_lshlrev_b16_e32 v21, 8, v29
 ; GFX9-NEXT:    s_waitcnt vmcnt(9)
-; GFX9-NEXT:    v_lshlrev_b16_e32 v44, 8, v0
+; GFX9-NEXT:    v_lshlrev_b16_e32 v15, 8, v0
 ; GFX9-NEXT:    s_waitcnt vmcnt(8)
-; GFX9-NEXT:    v_lshlrev_b16_e32 v45, 8, v2
+; GFX9-NEXT:    v_lshlrev_b16_e32 v17, 8, v2
 ; GFX9-NEXT:    s_waitcnt vmcnt(7)
-; GFX9-NEXT:    v_lshlrev_b16_e32 v27, 8, v4
+; GFX9-NEXT:    v_lshlrev_b16_e32 v19, 8, v4
 ; GFX9-NEXT:    s_waitcnt vmcnt(6)
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
 ; GFX9-NEXT:    s_waitcnt vmcnt(5)
-; GFX9-NEXT:    v_lshlrev_b16_e32 v46, 8, v8
+; GFX9-NEXT:    v_lshlrev_b16_e32 v11, 8, v8
+; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
 ; GFX9-NEXT:    s_waitcnt vmcnt(3)
-; GFX9-NEXT:    v_lshlrev_b16_e32 v47, 8, v10
-; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX9-NEXT:    v_lshlrev_b16_e32 v13, 8, v44
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB25_2
+; GFX9-NEXT:    s_cbranch_execz .LBB13_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.false
-; GFX9-NEXT:    v_or_b32_sdwa v0, v36, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v1, v33, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    s_mov_b32 s6, 0x5040100
-; GFX9-NEXT:    v_perm_b32 v0, v1, v0, s6
-; GFX9-NEXT:    v_or_b32_sdwa v1, v35, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v2, v38, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_perm_b32 v1, v2, v1, s6
-; GFX9-NEXT:    v_or_b32_sdwa v2, v32, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v3, v31, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_perm_b32 v2, v3, v2, s6
-; GFX9-NEXT:    v_or_b32_sdwa v3, v34, v41 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v4, v37, v40 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_perm_b32 v3, v4, v3, s6
-; GFX9-NEXT:    v_or_b32_sdwa v4, v16, v43 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v5, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_perm_b32 v4, v5, v4, s6
-; GFX9-NEXT:    v_or_b32_sdwa v5, v20, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v6, v22, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_perm_b32 v5, v6, v5, s6
+; GFX9-NEXT:    v_or_b32_sdwa v0, v31, v43 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_sdwa v1, v32, v42 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_sdwa v1, v33, v41 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_sdwa v2, v34, v40 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_sdwa v2, v35, v55 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_sdwa v3, v10, v54 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_sdwa v3, v12, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_sdwa v4, v14, v52 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_sdwa v4, v16, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_sdwa v5, v18, v50 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_sdwa v5, v20, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_sdwa v6, v22, v48 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; GFX9-NEXT:    v_or_b32_sdwa v6, v24, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v7, v26, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_perm_b32 v6, v7, v6, s6
-; GFX9-NEXT:    v_or_b32_sdwa v7, v28, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v8, v30, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_perm_b32 v7, v8, v7, s6
+; GFX9-NEXT:    v_or_b32_sdwa v7, v26, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_sdwa v7, v28, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_sdwa v8, v30, v19 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    v_or_b32_sdwa v8, v55, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v9, v53, v44 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_perm_b32 v8, v9, v8, s6
-; GFX9-NEXT:    v_or_b32_sdwa v9, v42, v47 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_or_b32_sdwa v10, v54, v46 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT:    v_perm_b32 v9, v10, v9, s6
-; GFX9-NEXT:    ; implicit-def: $vgpr36
-; GFX9-NEXT:    ; implicit-def: $vgpr33
-; GFX9-NEXT:    ; implicit-def: $vgpr35
-; GFX9-NEXT:    ; implicit-def: $vgpr38
-; GFX9-NEXT:    ; implicit-def: $vgpr32
+; GFX9-NEXT:    v_or_b32_sdwa v8, v39, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_sdwa v9, v38, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_sdwa v8, v8, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_sdwa v9, v37, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_sdwa v10, v36, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_sdwa v9, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; GFX9-NEXT:    ; implicit-def: $vgpr31
+; GFX9-NEXT:    ; implicit-def: $vgpr32
+; GFX9-NEXT:    ; implicit-def: $vgpr33
 ; GFX9-NEXT:    ; implicit-def: $vgpr34
-; GFX9-NEXT:    ; implicit-def: $vgpr37
+; GFX9-NEXT:    ; implicit-def: $vgpr35
+; GFX9-NEXT:    ; implicit-def: $vgpr10
+; GFX9-NEXT:    ; implicit-def: $vgpr12
+; GFX9-NEXT:    ; implicit-def: $vgpr14
 ; GFX9-NEXT:    ; implicit-def: $vgpr16
 ; GFX9-NEXT:    ; implicit-def: $vgpr18
 ; GFX9-NEXT:    ; implicit-def: $vgpr20
@@ -8580,575 +5506,782 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    ; implicit-def: $vgpr26
 ; GFX9-NEXT:    ; implicit-def: $vgpr28
 ; GFX9-NEXT:    ; implicit-def: $vgpr30
-; GFX9-NEXT:    ; implicit-def: $vgpr55
-; GFX9-NEXT:    ; implicit-def: $vgpr53
+; GFX9-NEXT:    ; implicit-def: $vgpr39
+; GFX9-NEXT:    ; implicit-def: $vgpr38
+; GFX9-NEXT:    ; implicit-def: $vgpr37
+; GFX9-NEXT:    ; implicit-def: $vgpr36
+; GFX9-NEXT:    ; implicit-def: $vgpr43
 ; GFX9-NEXT:    ; implicit-def: $vgpr42
+; GFX9-NEXT:    ; implicit-def: $vgpr41
+; GFX9-NEXT:    ; implicit-def: $vgpr40
+; GFX9-NEXT:    ; implicit-def: $vgpr55
 ; GFX9-NEXT:    ; implicit-def: $vgpr54
-; GFX9-NEXT:    ; implicit-def: $vgpr48
-; GFX9-NEXT:    ; implicit-def: $vgpr39
-; GFX9-NEXT:    ; implicit-def: $vgpr50
-; GFX9-NEXT:    ; implicit-def: $vgpr49
+; GFX9-NEXT:    ; implicit-def: $vgpr53
 ; GFX9-NEXT:    ; implicit-def: $vgpr52
 ; GFX9-NEXT:    ; implicit-def: $vgpr51
-; GFX9-NEXT:    ; implicit-def: $vgpr41
-; GFX9-NEXT:    ; implicit-def: $vgpr40
-; GFX9-NEXT:    ; implicit-def: $vgpr43
-; GFX9-NEXT:    ; implicit-def: $vgpr17
-; GFX9-NEXT:    ; implicit-def: $vgpr21
-; GFX9-NEXT:    ; implicit-def: $vgpr19
+; GFX9-NEXT:    ; implicit-def: $vgpr50
+; GFX9-NEXT:    ; implicit-def: $vgpr49
+; GFX9-NEXT:    ; implicit-def: $vgpr48
 ; GFX9-NEXT:    ; implicit-def: $vgpr25
 ; GFX9-NEXT:    ; implicit-def: $vgpr23
-; GFX9-NEXT:    ; implicit-def: $vgpr29
-; GFX9-NEXT:    ; implicit-def: $vgpr27
-; GFX9-NEXT:    ; implicit-def: $vgpr45
-; GFX9-NEXT:    ; implicit-def: $vgpr44
-; GFX9-NEXT:    ; implicit-def: $vgpr47
-; GFX9-NEXT:    ; implicit-def: $vgpr46
-; GFX9-NEXT:  .LBB25_2: ; %Flow
+; GFX9-NEXT:    ; implicit-def: $vgpr21
+; GFX9-NEXT:    ; implicit-def: $vgpr19
+; GFX9-NEXT:    ; implicit-def: $vgpr17
+; GFX9-NEXT:    ; implicit-def: $vgpr15
+; GFX9-NEXT:    ; implicit-def: $vgpr13
+; GFX9-NEXT:    ; implicit-def: $vgpr11
+; GFX9-NEXT:  .LBB13_2: ; %Flow
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB25_4
+; GFX9-NEXT:    s_cbranch_execz .LBB13_4
 ; GFX9-NEXT:  ; %bb.3: ; %cmp.true
-; GFX9-NEXT:    s_waitcnt vmcnt(2)
-; GFX9-NEXT:    v_add_u16_e32 v0, 3, v42
-; GFX9-NEXT:    v_or_b32_sdwa v0, v47, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v9, 0x300, v0
-; GFX9-NEXT:    v_add_u16_e32 v0, 3, v54
-; GFX9-NEXT:    v_or_b32_sdwa v0, v46, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v10, 0x300, v0
-; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    v_add_u16_e32 v0, 3, v55
-; GFX9-NEXT:    v_or_b32_sdwa v0, v45, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v8, 0x300, v0
-; GFX9-NEXT:    v_add_u16_e32 v0, 3, v53
-; GFX9-NEXT:    v_or_b32_sdwa v0, v44, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v11, 0x300, v0
-; GFX9-NEXT:    v_add_u16_e32 v0, 3, v28
-; GFX9-NEXT:    v_or_b32_sdwa v0, v29, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v7, 0x300, v0
-; GFX9-NEXT:    v_add_u16_e32 v0, 3, v30
-; GFX9-NEXT:    v_or_b32_sdwa v0, v27, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v12, 0x300, v0
-; GFX9-NEXT:    v_add_u16_e32 v0, 3, v24
-; GFX9-NEXT:    v_or_b32_sdwa v0, v25, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v6, 0x300, v0
-; GFX9-NEXT:    v_add_u16_e32 v0, 3, v26
-; GFX9-NEXT:    v_or_b32_sdwa v0, v23, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v13, 0x300, v0
-; GFX9-NEXT:    v_add_u16_e32 v0, 3, v20
-; GFX9-NEXT:    v_or_b32_sdwa v0, v21, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v5, 0x300, v0
-; GFX9-NEXT:    v_add_u16_e32 v0, 3, v22
-; GFX9-NEXT:    v_or_b32_sdwa v0, v19, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v14, 0x300, v0
-; GFX9-NEXT:    v_add_u16_e32 v0, 3, v16
-; GFX9-NEXT:    v_or_b32_sdwa v0, v43, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v4, 0x300, v0
-; GFX9-NEXT:    v_add_u16_e32 v0, 3, v18
-; GFX9-NEXT:    v_or_b32_sdwa v0, v17, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v15, 0x300, v0
-; GFX9-NEXT:    v_add_u16_e32 v0, 3, v34
-; GFX9-NEXT:    v_or_b32_sdwa v0, v41, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v3, 0x300, v0
-; GFX9-NEXT:    v_add_u16_e32 v0, 3, v37
-; GFX9-NEXT:    v_or_b32_sdwa v0, v40, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v16, 0x300, v0
-; GFX9-NEXT:    v_add_u16_e32 v0, 3, v32
-; GFX9-NEXT:    v_or_b32_sdwa v0, v52, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v2, 0x300, v0
 ; GFX9-NEXT:    v_add_u16_e32 v0, 3, v31
-; GFX9-NEXT:    v_or_b32_sdwa v0, v51, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v17, 0x300, v0
-; GFX9-NEXT:    v_add_u16_e32 v0, 3, v35
-; GFX9-NEXT:    v_or_b32_sdwa v0, v50, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v1, 0x300, v0
-; GFX9-NEXT:    v_add_u16_e32 v0, 3, v38
-; GFX9-NEXT:    v_or_b32_sdwa v0, v49, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_add_u16_e32 v18, 0x300, v0
-; GFX9-NEXT:    v_add_u16_e32 v0, 3, v36
-; GFX9-NEXT:    v_add_u16_e32 v19, 3, v33
-; GFX9-NEXT:    v_or_b32_sdwa v0, v48, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT:    v_or_b32_sdwa v19, v39, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT:    v_add_u16_e32 v1, 3, v32
+; GFX9-NEXT:    v_or_b32_sdwa v0, v43, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT:    s_movk_i32 s6, 0x300
+; GFX9-NEXT:    v_or_b32_sdwa v1, v42, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
 ; GFX9-NEXT:    v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT:    v_add_u16_e32 v19, 0x300, v19
-; GFX9-NEXT:    s_mov_b32 s6, 0x5040100
-; GFX9-NEXT:    v_perm_b32 v0, v19, v0, s6
-; GFX9-NEXT:    v_perm_b32 v1, v18, v1, s6
-; GFX9-NEXT:    v_perm_b32 v2, v17, v2, s6
-; GFX9-NEXT:    v_perm_b32 v3, v16, v3, s6
-; GFX9-NEXT:    v_perm_b32 v4, v15, v4, s6
-; GFX9-NEXT:    v_perm_b32 v5, v14, v5, s6
-; GFX9-NEXT:    v_perm_b32 v6, v13, v6, s6
-; GFX9-NEXT:    v_perm_b32 v7, v12, v7, s6
-; GFX9-NEXT:    v_perm_b32 v8, v11, v8, s6
-; GFX9-NEXT:    v_perm_b32 v9, v10, v9, s6
-; GFX9-NEXT:  .LBB25_4: ; %end
+; GFX9-NEXT:    v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT:    v_add_u16_e32 v1, 3, v33
+; GFX9-NEXT:    v_add_u16_e32 v2, 3, v34
+; GFX9-NEXT:    v_or_b32_sdwa v1, v41, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT:    v_or_b32_sdwa v2, v40, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT:    v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT:    v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT:    v_add_u16_e32 v2, 3, v35
+; GFX9-NEXT:    v_add_u16_e32 v3, 3, v10
+; GFX9-NEXT:    v_or_b32_sdwa v2, v55, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT:    v_or_b32_sdwa v3, v54, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT:    v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT:    v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT:    v_add_u16_e32 v3, 3, v12
+; GFX9-NEXT:    v_add_u16_e32 v4, 3, v14
+; GFX9-NEXT:    v_or_b32_sdwa v3, v53, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT:    v_or_b32_sdwa v4, v52, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT:    v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT:    v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT:    v_add_u16_e32 v4, 3, v16
+; GFX9-NEXT:    v_add_u16_e32 v5, 3, v18
+; GFX9-NEXT:    v_or_b32_sdwa v4, v51, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT:    v_or_b32_sdwa v5, v50, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT:    v_add_u16_e32 v4, 0x300, v4
+; GFX9-NEXT:    v_add_u16_sdwa v5, v5, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT:    v_add_u16_e32 v5, 3, v20
+; GFX9-NEXT:    v_add_u16_e32 v6, 3, v22
+; GFX9-NEXT:    v_or_b32_sdwa v5, v49, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT:    v_or_b32_sdwa v6, v48, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT:    v_add_u16_e32 v5, 0x300, v5
+; GFX9-NEXT:    v_add_u16_sdwa v6, v6, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT:    v_add_u16_e32 v6, 3, v24
+; GFX9-NEXT:    v_add_u16_e32 v7, 3, v26
+; GFX9-NEXT:    v_or_b32_sdwa v6, v25, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT:    v_or_b32_sdwa v7, v23, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT:    v_add_u16_e32 v6, 0x300, v6
+; GFX9-NEXT:    v_add_u16_sdwa v7, v7, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT:    v_add_u16_e32 v7, 3, v28
+; GFX9-NEXT:    v_add_u16_e32 v8, 3, v30
+; GFX9-NEXT:    v_or_b32_sdwa v7, v21, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT:    v_or_b32_sdwa v8, v19, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT:    v_add_u16_e32 v7, 0x300, v7
+; GFX9-NEXT:    v_add_u16_sdwa v8, v8, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_add_u16_e32 v8, 3, v39
+; GFX9-NEXT:    v_add_u16_e32 v9, 3, v38
+; GFX9-NEXT:    v_or_b32_sdwa v8, v17, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT:    v_or_b32_sdwa v9, v15, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT:    v_add_u16_e32 v8, 0x300, v8
+; GFX9-NEXT:    v_add_u16_sdwa v9, v9, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT:    v_add_u16_e32 v9, 3, v37
+; GFX9-NEXT:    v_add_u16_e32 v10, 3, v36
+; GFX9-NEXT:    v_or_b32_sdwa v9, v13, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT:    v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT:    v_add_u16_e32 v9, 0x300, v9
+; GFX9-NEXT:    v_add_u16_sdwa v10, v10, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT:    v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT:  .LBB13_4: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GFX9-NEXT:    buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
-; GFX9-NEXT:    buffer_load_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
-; GFX9-NEXT:    buffer_load_dword v45, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
-; GFX9-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
-; GFX9-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
-; GFX9-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
-; GFX9-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; GFX9-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; GFX9-NEXT:    buffer_load_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
+; GFX9-NEXT:    buffer_load_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
+; GFX9-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
+; GFX9-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
+; GFX9-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v40i8_to_v20i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v33, v10 :: v_dual_mov_b32 v34, v8
-; GFX11-NEXT:    v_dual_mov_b32 v38, v6 :: v_dual_mov_b32 v35, v4
-; GFX11-NEXT:    v_dual_mov_b32 v37, v2 :: v_dual_mov_b32 v36, v0
-; GFX11-NEXT:    s_clause 0x9
-; GFX11-NEXT:    scratch_load_b32 v0, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32
-; GFX11-NEXT:    scratch_load_u16 v4, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_u16 v6, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_u16 v8, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_u16 v10, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_u16 v66, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_u16 v68, off, s32 offset:20
-; GFX11-NEXT:    scratch_load_u16 v65, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_u16 v67, off, s32 offset:4
-; GFX11-NEXT:    v_dual_mov_b32 v31, v14 :: v_dual_mov_b32 v32, v12
-; GFX11-NEXT:    v_lshlrev_b16 v48, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v49, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v51, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v50, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v52, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v64, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v69, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(9)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(8)
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(7)
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v4
-; GFX11-NEXT:    s_waitcnt vmcnt(6)
-; GFX11-NEXT:    v_lshlrev_b16 v29, 8, v6
-; GFX11-NEXT:    s_waitcnt vmcnt(5)
-; GFX11-NEXT:    v_lshlrev_b16 v70, 8, v8
-; GFX11-NEXT:    s_waitcnt vmcnt(4)
-; GFX11-NEXT:    v_lshlrev_b16 v71, 8, v10
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB25_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB25_4
-; GFX11-NEXT:  .LBB25_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB25_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v36
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v37
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v35
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v38
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v34
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v31
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v18
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v48
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v49
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v51
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v50
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v55
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v39
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v53
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v52
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v54
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v17
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v1, v3, v2, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v2, v5, v4, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v3, v7, v6, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v4, v9, v8, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v24
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v26
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v30
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v67
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v65
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v68
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v66
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v21
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v19
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v64
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v25
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v69
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v23
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v27
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v29
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v70
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v71
-; GFX11-NEXT:    v_perm_b32 v5, v6, v5, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v6, v8, v7, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v7, v10, v9, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v8, v12, v11, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v9, v14, v13, 0x5040100
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr67
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB25_2
-; GFX11-NEXT:  .LBB25_4: ; %cmp.true
-; GFX11-NEXT:    s_waitcnt vmcnt(2)
-; GFX11-NEXT:    v_add_nc_u16 v0, v68, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v66, 3
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_add_nc_u16 v3, v65, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v28, 3
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_nc_u16 v2, v67, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_or_b32_e32 v0, v70, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v71, v1
-; GFX11-NEXT:    v_or_b32_e32 v3, v29, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v2, v27, v2
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v0, v69, v4
-; GFX11-NEXT:    v_add_nc_u16 v1, v30, 3
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v3, v20, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v26, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, v24, 3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, v22, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v23, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_perm_b32 v8, v11, v8, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v0, v25, v0
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v21, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v64, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, v18, 3
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v16, 3
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v32, 3
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v19, v4
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v4, v31, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v0, v54, v0
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v1, v53, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, v34, 3
-; GFX11-NEXT:    v_add_nc_u16 v16, v36, 3
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v17, v3
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v52, v4
-; GFX11-NEXT:    v_add_nc_u16 v4, v35, 3
-; GFX11-NEXT:    v_add_nc_u16 v17, v37, 3
-; GFX11-NEXT:    v_add_nc_u16 v18, v38, 3
-; GFX11-NEXT:    v_add_nc_u16 v19, v33, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v17
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v19
-; GFX11-NEXT:    v_or_b32_e32 v2, v55, v2
-; GFX11-NEXT:    v_or_b32_e32 v4, v51, v4
-; GFX11-NEXT:    v_or_b32_e32 v16, v48, v16
-; GFX11-NEXT:    v_or_b32_e32 v17, v49, v17
-; GFX11-NEXT:    v_or_b32_e32 v18, v50, v18
-; GFX11-NEXT:    v_or_b32_e32 v19, v39, v19
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v16, 0x300, v16
-; GFX11-NEXT:    v_add_nc_u16 v17, 0x300, v17
-; GFX11-NEXT:    v_add_nc_u16 v18, 0x300, v18
-; GFX11-NEXT:    v_add_nc_u16 v19, 0x300, v19
-; GFX11-NEXT:    v_add_nc_u16 v20, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v21, 0x300, v0
-; GFX11-NEXT:    v_perm_b32 v0, v17, v16, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v1, v18, v4, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v2, v19, v2, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v3, v20, v3, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v4, v21, v15, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v5, v14, v5, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v6, v13, v6, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v7, v12, v7, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v9, v10, v9, 0x5040100
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v40i8_to_v10f32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x9
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v36, off, s32 offset:36
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v33, off, s32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v33, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v34, off, s32 offset:16
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v34, off, s32 offset:24
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v35, off, s32 offset:32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32 offset:28
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v31, off, s32 offset:20
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v32, off, s32 offset:12
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v32, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.h, v25.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.h, v23.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.h, v21.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.h, v19.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v17.h, v17.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v17.l, v15.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v14.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.h, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.h, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v25.l, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v25.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v26.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.h, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v22.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.l, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v24.h, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.l, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v17.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v30.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v29.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.l, 8, v28.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v27.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.l, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v29.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(8)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.l, 8, v33.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v33.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(6)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.l, 8, v34.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(5)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v34.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(4)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.l, 8, v35.l
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v36
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB13_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB13_4
+; GFX11-TRUE16-NEXT:  .LBB13_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB13_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v26.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v25.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v25.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v20.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v21.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v23.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v0.h, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v1.h, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v24.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v19.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v16.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v15.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v17.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v0.h, v16.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v1.h, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v18.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v5, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v7, v8
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v20.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v26.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v13.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v14.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v9, v15
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v4, v17
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v5.h, v13.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v6.h, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v30.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v32.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v32.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v31.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v31.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v3, v16
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v10.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v5.h, v10.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v11.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v6.h, v11.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v12.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v13, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v15, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v17, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v8, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v9, v12
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB13_2
+; GFX11-TRUE16-NEXT:  .LBB13_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v26.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v25.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v25.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v21.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v20.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v21.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v23.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v22.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v23.h, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v24.h, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v19.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v15.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v19.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v16.l, 3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v15.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v17.l, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v18.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v16.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v17.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v5, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v7, v8
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, v20.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, v24.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v28.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v18.h, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, v22.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, v26.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v5.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v12.h, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v13.h, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v14.h, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v2
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.h, v13.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v14.l, v6.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v5.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v6.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v9, v15
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v4, v17
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v5.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, v30.l, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, v32.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, v32.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, v31.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v31.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v5.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v10.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.h, v10.h, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v11.l, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v11.h, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v12.l, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v3, v16
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v9
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v5.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v5.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v6.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v6.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v13, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v15, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v17, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v8, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v9, v12
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v10f32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v35, v8 :: v_dual_mov_b32 v34, v6
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v33, v4 :: v_dual_mov_b32 v32, v2
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v31, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x9
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v0, off, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v4, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v6, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v8, off, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v66, off, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v36, off, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v37, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v38, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v39, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v53, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v64, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v48, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v49, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v50, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v51, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v52, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v29, 8, v29
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(9)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(8)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(7)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(6)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v6
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(5)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v8
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(4)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB13_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB13_4
+; GFX11-FAKE16-NEXT:  .LBB13_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB13_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v64
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v48
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v49
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v50
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v51
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v52
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v8, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v30
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v38
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v37
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v18, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v13, v14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB13_2
+; GFX11-FAKE16-NEXT:  .LBB13_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v31, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v32, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v33, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v34, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v35, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v10, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v12, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v14, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v16, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v18, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v53, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v54, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v55, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v64, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v65, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v48, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v49, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v50, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v51, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v52, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v8, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v20, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v22, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v24, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v26, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v28, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v30, 3
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v39, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v38, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, v37, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, v36, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v21, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v23, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v25, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v27, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v29, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v11, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v13, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v15, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v17, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v19, v18
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v13
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v13, v14
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
 cmp.true:
   %a1 = add <40 x i8> %a, splat (i8 3)
-  %a2 = bitcast <40 x i8> %a1 to <20 x i16>
+  %a2 = bitcast <40 x i8> %a1 to <10 x float>
   br label %end
 
 cmp.false:
-  %a3 = bitcast <40 x i8> %a to <20 x i16>
+  %a3 = bitcast <40 x i8> %a to <10 x float>
   br label %end
 
 end:
-  %phi = phi <20 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
-  ret <20 x i16> %phi
+  %phi = phi <10 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
+  ret <10 x float> %phi
 }
 
-define <5 x double> @bitcast_v20i16_to_v5f64(<20 x i16> %a, i32 %b) {
-; GCN-LABEL: bitcast_v20i16_to_v5f64:
+define <5 x double> @bitcast_v10f32_to_v5f64(<10 x float> %a, i32 %b) {
+; GCN-LABEL: bitcast_v10f32_to_v5f64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v28, v14
-; GCN-NEXT:    v_mov_b32_e32 v27, v12
-; GCN-NEXT:    v_mov_b32_e32 v26, v10
-; GCN-NEXT:    v_mov_b32_e32 v21, v8
-; GCN-NEXT:    v_mov_b32_e32 v22, v6
-; GCN-NEXT:    v_mov_b32_e32 v23, v4
-; GCN-NEXT:    v_mov_b32_e32 v24, v2
-; GCN-NEXT:    v_mov_b32_e32 v25, v0
-; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v20
-; GCN-NEXT:    v_lshlrev_b32_e32 v34, 16, v1
-; GCN-NEXT:    v_lshlrev_b32_e32 v35, 16, v3
-; GCN-NEXT:    v_lshlrev_b32_e32 v20, 16, v5
-; GCN-NEXT:    v_lshlrev_b32_e32 v29, 16, v7
-; GCN-NEXT:    v_lshlrev_b32_e32 v30, 16, v9
-; GCN-NEXT:    v_lshlrev_b32_e32 v31, 16, v11
-; GCN-NEXT:    v_lshlrev_b32_e32 v32, 16, v13
-; GCN-NEXT:    v_lshlrev_b32_e32 v33, 16, v15
-; GCN-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GCN-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GCN-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execnz .LBB26_3
-; GCN-NEXT:  ; %bb.1: ; %Flow
-; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execnz .LBB26_4
-; GCN-NEXT:  .LBB26_2: ; %end
-; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-; GCN-NEXT:  .LBB26_3: ; %cmp.false
-; GCN-NEXT:    v_and_b32_e32 v0, 0xffff, v25
-; GCN-NEXT:    v_and_b32_e32 v1, 0xffff, v24
-; GCN-NEXT:    v_or_b32_e32 v0, v0, v34
-; GCN-NEXT:    v_or_b32_e32 v1, v1, v35
-; GCN-NEXT:    v_and_b32_e32 v2, 0xffff, v23
-; GCN-NEXT:    v_and_b32_e32 v3, 0xffff, v22
-; GCN-NEXT:    v_and_b32_e32 v4, 0xffff, v21
-; GCN-NEXT:    v_and_b32_e32 v5, 0xffff, v26
-; GCN-NEXT:    v_and_b32_e32 v6, 0xffff, v27
-; GCN-NEXT:    v_and_b32_e32 v7, 0xffff, v28
-; GCN-NEXT:    v_and_b32_e32 v8, 0xffff, v16
-; GCN-NEXT:    v_and_b32_e32 v9, 0xffff, v18
-; GCN-NEXT:    v_or_b32_e32 v2, v2, v20
-; GCN-NEXT:    v_or_b32_e32 v3, v3, v29
-; GCN-NEXT:    v_or_b32_e32 v4, v4, v30
-; GCN-NEXT:    v_or_b32_e32 v5, v5, v31
-; GCN-NEXT:    v_or_b32_e32 v6, v6, v32
-; GCN-NEXT:    v_or_b32_e32 v7, v7, v33
-; GCN-NEXT:    v_or_b32_e32 v8, v8, v17
-; GCN-NEXT:    v_or_b32_e32 v9, v9, v19
-; GCN-NEXT:    ; implicit-def: $vgpr25
-; GCN-NEXT:    ; implicit-def: $vgpr24
-; GCN-NEXT:    ; implicit-def: $vgpr23
-; GCN-NEXT:    ; implicit-def: $vgpr22
-; GCN-NEXT:    ; implicit-def: $vgpr21
-; GCN-NEXT:    ; implicit-def: $vgpr26
-; GCN-NEXT:    ; implicit-def: $vgpr27
-; GCN-NEXT:    ; implicit-def: $vgpr28
-; GCN-NEXT:    ; implicit-def: $vgpr16
-; GCN-NEXT:    ; implicit-def: $vgpr18
-; GCN-NEXT:    ; implicit-def: $vgpr34
-; GCN-NEXT:    ; implicit-def: $vgpr35
-; GCN-NEXT:    ; implicit-def: $vgpr20
-; GCN-NEXT:    ; implicit-def: $vgpr29
-; GCN-NEXT:    ; implicit-def: $vgpr30
-; GCN-NEXT:    ; implicit-def: $vgpr31
-; GCN-NEXT:    ; implicit-def: $vgpr32
-; GCN-NEXT:    ; implicit-def: $vgpr33
-; GCN-NEXT:    ; implicit-def: $vgpr17
-; GCN-NEXT:    ; implicit-def: $vgpr19
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB26_2
-; GCN-NEXT:  .LBB26_4: ; %cmp.true
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, 3, v25
-; GCN-NEXT:    s_mov_b32 s6, 0x30000
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, 3, v24
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, 3, v23
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, 3, v22
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, 3, v21
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, 3, v26
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, 3, v27
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, 3, v28
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, 3, v16
-; GCN-NEXT:    v_add_i32_e32 v9, vcc, 3, v18
-; GCN-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GCN-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GCN-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GCN-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GCN-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GCN-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GCN-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GCN-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GCN-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GCN-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GCN-NEXT:    v_or_b32_e32 v0, v34, v0
-; GCN-NEXT:    v_or_b32_e32 v1, v35, v1
-; GCN-NEXT:    v_or_b32_e32 v2, v20, v2
-; GCN-NEXT:    v_or_b32_e32 v3, v29, v3
-; GCN-NEXT:    v_or_b32_e32 v4, v30, v4
-; GCN-NEXT:    v_or_b32_e32 v5, v31, v5
-; GCN-NEXT:    v_or_b32_e32 v6, v32, v6
-; GCN-NEXT:    v_or_b32_e32 v7, v33, v7
-; GCN-NEXT:    v_or_b32_e32 v8, v17, v8
-; GCN-NEXT:    v_or_b32_e32 v9, v19, v9
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, 0x30000, v0
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, s6, v1
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, s6, v2
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, s6, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, s6, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, s6, v5
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, s6, v6
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, s6, v7
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, s6, v8
-; GCN-NEXT:    v_add_i32_e32 v9, vcc, 0x30000, v9
+; GCN-NEXT:    s_cbranch_execz .LBB14_2
+; GCN-NEXT:  ; %bb.1: ; %cmp.true
+; GCN-NEXT:    v_add_f32_e32 v9, 1.0, v9
+; GCN-NEXT:    v_add_f32_e32 v8, 1.0, v8
+; GCN-NEXT:    v_add_f32_e32 v7, 1.0, v7
+; GCN-NEXT:    v_add_f32_e32 v6, 1.0, v6
+; GCN-NEXT:    v_add_f32_e32 v5, 1.0, v5
+; GCN-NEXT:    v_add_f32_e32 v4, 1.0, v4
+; GCN-NEXT:    v_add_f32_e32 v3, 1.0, v3
+; GCN-NEXT:    v_add_f32_e32 v2, 1.0, v2
+; GCN-NEXT:    v_add_f32_e32 v1, 1.0, v1
+; GCN-NEXT:    v_add_f32_e32 v0, 1.0, v0
+; GCN-NEXT:  .LBB14_2: ; %end
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
-; VI-LABEL: bitcast_v20i16_to_v5f64:
+; VI-LABEL: bitcast_v10f32_to_v5f64:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB26_2
+; VI-NEXT:    s_cbranch_execz .LBB14_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.true
-; VI-NEXT:    v_mov_b32_e32 v11, 3
-; VI-NEXT:    v_add_u16_e32 v10, 3, v9
-; VI-NEXT:    v_add_u16_sdwa v9, v9, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v9, v10, v9
-; VI-NEXT:    v_add_u16_e32 v10, 3, v8
-; VI-NEXT:    v_add_u16_sdwa v8, v8, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v8, v10, v8
-; VI-NEXT:    v_add_u16_e32 v10, 3, v7
-; VI-NEXT:    v_add_u16_sdwa v7, v7, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v7, v10, v7
-; VI-NEXT:    v_add_u16_e32 v10, 3, v6
-; VI-NEXT:    v_add_u16_sdwa v6, v6, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v6, v10, v6
-; VI-NEXT:    v_add_u16_e32 v10, 3, v5
-; VI-NEXT:    v_add_u16_sdwa v5, v5, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v5, v10, v5
-; VI-NEXT:    v_add_u16_e32 v10, 3, v4
-; VI-NEXT:    v_add_u16_sdwa v4, v4, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v4, v10, v4
-; VI-NEXT:    v_add_u16_e32 v10, 3, v3
-; VI-NEXT:    v_add_u16_sdwa v3, v3, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v3, v10, v3
-; VI-NEXT:    v_add_u16_e32 v10, 3, v2
-; VI-NEXT:    v_add_u16_sdwa v2, v2, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v2, v10, v2
-; VI-NEXT:    v_add_u16_e32 v10, 3, v1
-; VI-NEXT:    v_add_u16_sdwa v1, v1, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v1, v10, v1
-; VI-NEXT:    v_add_u16_e32 v10, 3, v0
-; VI-NEXT:    v_add_u16_sdwa v0, v0, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v0, v10, v0
-; VI-NEXT:  .LBB26_2: ; %end
+; VI-NEXT:    v_add_f32_e32 v9, 1.0, v9
+; VI-NEXT:    v_add_f32_e32 v8, 1.0, v8
+; VI-NEXT:    v_add_f32_e32 v7, 1.0, v7
+; VI-NEXT:    v_add_f32_e32 v6, 1.0, v6
+; VI-NEXT:    v_add_f32_e32 v5, 1.0, v5
+; VI-NEXT:    v_add_f32_e32 v4, 1.0, v4
+; VI-NEXT:    v_add_f32_e32 v3, 1.0, v3
+; VI-NEXT:    v_add_f32_e32 v2, 1.0, v2
+; VI-NEXT:    v_add_f32_e32 v1, 1.0, v1
+; VI-NEXT:    v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT:  .LBB14_2: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX9-LABEL: bitcast_v20i16_to_v5f64:
+; GFX9-LABEL: bitcast_v10f32_to_v5f64:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB26_2
+; GFX9-NEXT:    s_cbranch_execz .LBB14_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.true
-; GFX9-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:  .LBB26_2: ; %end
+; GFX9-NEXT:    v_add_f32_e32 v9, 1.0, v9
+; GFX9-NEXT:    v_add_f32_e32 v8, 1.0, v8
+; GFX9-NEXT:    v_add_f32_e32 v7, 1.0, v7
+; GFX9-NEXT:    v_add_f32_e32 v6, 1.0, v6
+; GFX9-NEXT:    v_add_f32_e32 v5, 1.0, v5
+; GFX9-NEXT:    v_add_f32_e32 v4, 1.0, v4
+; GFX9-NEXT:    v_add_f32_e32 v3, 1.0, v3
+; GFX9-NEXT:    v_add_f32_e32 v2, 1.0, v2
+; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v1
+; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT:  .LBB14_2: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v20i16_to_v5f64:
+; GFX11-LABEL: bitcast_v10f32_to_v5f64:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX11-NEXT:    s_mov_b32 s0, exec_lo
@@ -9156,31 +6289,25 @@ define <5 x double> @bitcast_v20i16_to_v5f64(<20 x i16> %a, i32 %b) {
 ; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB26_2
 ; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:  .LBB26_2: ; %end
+; GFX11-NEXT:    v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
+; GFX11-NEXT:    v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
+; GFX11-NEXT:    v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
+; GFX11-NEXT:    v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
+; GFX11-NEXT:    v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT:  ; %bb.2: ; %end
 ; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
 cmp.true:
-  %a1 = add <20 x i16> %a, splat (i16 3)
-  %a2 = bitcast <20 x i16> %a1 to <5 x double>
+  %a1 = fadd <10 x float> %a, splat (float 1.000000e+00)
+  %a2 = bitcast <10 x float> %a1 to <5 x double>
   br label %end
 
 cmp.false:
-  %a3 = bitcast <20 x i16> %a to <5 x double>
+  %a3 = bitcast <10 x float> %a to <5 x double>
   br label %end
 
 end:
@@ -9188,113 +6315,62 @@ end:
   ret <5 x double> %phi
 }
 
-define <20 x i16> @bitcast_v5f64_to_v20i16(<5 x double> %a, i32 %b) {
-; GCN-LABEL: bitcast_v5f64_to_v20i16:
+define <10 x float> @bitcast_v5f64_to_v10f32(<5 x double> %a, i32 %b) {
+; GCN-LABEL: bitcast_v5f64_to_v10f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v28, v9
-; GCN-NEXT:    v_mov_b32_e32 v27, v8
-; GCN-NEXT:    v_mov_b32_e32 v26, v7
-; GCN-NEXT:    v_mov_b32_e32 v25, v6
-; GCN-NEXT:    v_mov_b32_e32 v24, v5
-; GCN-NEXT:    v_mov_b32_e32 v23, v4
-; GCN-NEXT:    v_mov_b32_e32 v22, v3
-; GCN-NEXT:    v_mov_b32_e32 v21, v2
 ; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; GCN-NEXT:    ; implicit-def: $vgpr20
-; GCN-NEXT:    ; implicit-def: $vgpr3
-; GCN-NEXT:    ; implicit-def: $vgpr5
-; GCN-NEXT:    ; implicit-def: $vgpr7
-; GCN-NEXT:    ; implicit-def: $vgpr9
-; GCN-NEXT:    ; implicit-def: $vgpr11
-; GCN-NEXT:    ; implicit-def: $vgpr13
-; GCN-NEXT:    ; implicit-def: $vgpr15
-; GCN-NEXT:    ; implicit-def: $vgpr17
-; GCN-NEXT:    ; implicit-def: $vgpr19
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB27_2
-; GCN-NEXT:  ; %bb.1: ; %cmp.false
-; GCN-NEXT:    v_alignbit_b32 v17, v28, v27, 16
-; GCN-NEXT:    v_alignbit_b32 v13, v26, v25, 16
-; GCN-NEXT:    v_alignbit_b32 v9, v24, v23, 16
-; GCN-NEXT:    v_alignbit_b32 v5, v22, v21, 16
-; GCN-NEXT:    v_alignbit_b32 v20, v1, v0, 16
-; GCN-NEXT:    v_lshrrev_b32_e32 v19, 16, v28
-; GCN-NEXT:    v_lshrrev_b32_e32 v15, 16, v26
-; GCN-NEXT:    v_lshrrev_b32_e32 v11, 16, v24
-; GCN-NEXT:    v_lshrrev_b32_e32 v7, 16, v22
-; GCN-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GCN-NEXT:  .LBB27_2: ; %Flow
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB27_4
-; GCN-NEXT:  ; %bb.3: ; %cmp.true
+; GCN-NEXT:    s_cbranch_execz .LBB15_2
+; GCN-NEXT:  ; %bb.1: ; %cmp.true
+; GCN-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
+; GCN-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
+; GCN-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
+; GCN-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
 ; GCN-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
-; GCN-NEXT:    v_add_f64 v[21:22], v[21:22], 1.0
-; GCN-NEXT:    v_add_f64 v[23:24], v[23:24], 1.0
-; GCN-NEXT:    v_add_f64 v[25:26], v[25:26], 1.0
-; GCN-NEXT:    v_add_f64 v[27:28], v[27:28], 1.0
-; GCN-NEXT:    v_alignbit_b32 v17, v28, v27, 16
-; GCN-NEXT:    v_alignbit_b32 v13, v26, v25, 16
-; GCN-NEXT:    v_alignbit_b32 v9, v24, v23, 16
-; GCN-NEXT:    v_alignbit_b32 v5, v22, v21, 16
-; GCN-NEXT:    v_alignbit_b32 v20, v1, v0, 16
-; GCN-NEXT:    v_lshrrev_b32_e32 v19, 16, v28
-; GCN-NEXT:    v_lshrrev_b32_e32 v15, 16, v26
-; GCN-NEXT:    v_lshrrev_b32_e32 v11, 16, v24
-; GCN-NEXT:    v_lshrrev_b32_e32 v7, 16, v22
-; GCN-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GCN-NEXT:  .LBB27_4: ; %end
+; GCN-NEXT:  .LBB15_2: ; %end
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GCN-NEXT:    v_mov_b32_e32 v2, v1
-; GCN-NEXT:    v_mov_b32_e32 v4, v21
-; GCN-NEXT:    v_mov_b32_e32 v6, v22
-; GCN-NEXT:    v_mov_b32_e32 v8, v23
-; GCN-NEXT:    v_mov_b32_e32 v10, v24
-; GCN-NEXT:    v_mov_b32_e32 v12, v25
-; GCN-NEXT:    v_mov_b32_e32 v14, v26
-; GCN-NEXT:    v_mov_b32_e32 v16, v27
-; GCN-NEXT:    v_mov_b32_e32 v18, v28
-; GCN-NEXT:    v_mov_b32_e32 v1, v20
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
-; VI-LABEL: bitcast_v5f64_to_v20i16:
+; VI-LABEL: bitcast_v5f64_to_v10f32:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB27_2
+; VI-NEXT:    s_cbranch_execz .LBB15_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.true
 ; VI-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
 ; VI-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
 ; VI-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
 ; VI-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
 ; VI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
-; VI-NEXT:  .LBB27_2: ; %end
+; VI-NEXT:  .LBB15_2: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX9-LABEL: bitcast_v5f64_to_v20i16:
+; GFX9-LABEL: bitcast_v5f64_to_v10f32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB27_2
+; GFX9-NEXT:    s_cbranch_execz .LBB15_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX9-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
 ; GFX9-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
 ; GFX9-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
 ; GFX9-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
 ; GFX9-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
-; GFX9-NEXT:  .LBB27_2: ; %end
+; GFX9-NEXT:  .LBB15_2: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v5f64_to_v20i16:
+; GFX11-LABEL: bitcast_v5f64_to_v10f32:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX11-NEXT:    s_mov_b32 s0, exec_lo
@@ -9302,14 +6378,14 @@ define <20 x i16> @bitcast_v5f64_to_v20i16(<5 x double> %a, i32 %b) {
 ; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB27_2
+; GFX11-NEXT:    s_cbranch_execz .LBB15_2
 ; GFX11-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX11-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
 ; GFX11-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
 ; GFX11-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
 ; GFX11-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
 ; GFX11-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
-; GFX11-NEXT:  .LBB27_2: ; %end
+; GFX11-NEXT:  .LBB15_2: ; %end
 ; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
@@ -9317,207 +6393,89 @@ define <20 x i16> @bitcast_v5f64_to_v20i16(<5 x double> %a, i32 %b) {
 
 cmp.true:
   %a1 = fadd <5 x double> %a, splat (double 1.000000e+00)
-  %a2 = bitcast <5 x double> %a1 to <20 x i16>
+  %a2 = bitcast <5 x double> %a1 to <10 x float>
   br label %end
 
 cmp.false:
-  %a3 = bitcast <5 x double> %a to <20 x i16>
+  %a3 = bitcast <5 x double> %a to <10 x float>
   br label %end
 
 end:
-  %phi = phi <20 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
-  ret <20 x i16> %phi
+  %phi = phi <10 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
+  ret <10 x float> %phi
 }
 
-define <5 x i64> @bitcast_v20i16_to_v5i64(<20 x i16> %a, i32 %b) {
-; GCN-LABEL: bitcast_v20i16_to_v5i64:
+define <5 x i64> @bitcast_v10f32_to_v5i64(<10 x float> %a, i32 %b) {
+; GCN-LABEL: bitcast_v10f32_to_v5i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v28, v14
-; GCN-NEXT:    v_mov_b32_e32 v27, v12
-; GCN-NEXT:    v_mov_b32_e32 v26, v10
-; GCN-NEXT:    v_mov_b32_e32 v21, v8
-; GCN-NEXT:    v_mov_b32_e32 v22, v6
-; GCN-NEXT:    v_mov_b32_e32 v23, v4
-; GCN-NEXT:    v_mov_b32_e32 v24, v2
-; GCN-NEXT:    v_mov_b32_e32 v25, v0
-; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v20
-; GCN-NEXT:    v_lshlrev_b32_e32 v34, 16, v1
-; GCN-NEXT:    v_lshlrev_b32_e32 v35, 16, v3
-; GCN-NEXT:    v_lshlrev_b32_e32 v20, 16, v5
-; GCN-NEXT:    v_lshlrev_b32_e32 v29, 16, v7
-; GCN-NEXT:    v_lshlrev_b32_e32 v30, 16, v9
-; GCN-NEXT:    v_lshlrev_b32_e32 v31, 16, v11
-; GCN-NEXT:    v_lshlrev_b32_e32 v32, 16, v13
-; GCN-NEXT:    v_lshlrev_b32_e32 v33, 16, v15
-; GCN-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GCN-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GCN-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execnz .LBB28_3
-; GCN-NEXT:  ; %bb.1: ; %Flow
-; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execnz .LBB28_4
-; GCN-NEXT:  .LBB28_2: ; %end
-; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-; GCN-NEXT:  .LBB28_3: ; %cmp.false
-; GCN-NEXT:    v_and_b32_e32 v0, 0xffff, v25
-; GCN-NEXT:    v_and_b32_e32 v1, 0xffff, v24
-; GCN-NEXT:    v_or_b32_e32 v0, v0, v34
-; GCN-NEXT:    v_or_b32_e32 v1, v1, v35
-; GCN-NEXT:    v_and_b32_e32 v2, 0xffff, v23
-; GCN-NEXT:    v_and_b32_e32 v3, 0xffff, v22
-; GCN-NEXT:    v_and_b32_e32 v4, 0xffff, v21
-; GCN-NEXT:    v_and_b32_e32 v5, 0xffff, v26
-; GCN-NEXT:    v_and_b32_e32 v6, 0xffff, v27
-; GCN-NEXT:    v_and_b32_e32 v7, 0xffff, v28
-; GCN-NEXT:    v_and_b32_e32 v8, 0xffff, v16
-; GCN-NEXT:    v_and_b32_e32 v9, 0xffff, v18
-; GCN-NEXT:    v_or_b32_e32 v2, v2, v20
-; GCN-NEXT:    v_or_b32_e32 v3, v3, v29
-; GCN-NEXT:    v_or_b32_e32 v4, v4, v30
-; GCN-NEXT:    v_or_b32_e32 v5, v5, v31
-; GCN-NEXT:    v_or_b32_e32 v6, v6, v32
-; GCN-NEXT:    v_or_b32_e32 v7, v7, v33
-; GCN-NEXT:    v_or_b32_e32 v8, v8, v17
-; GCN-NEXT:    v_or_b32_e32 v9, v9, v19
-; GCN-NEXT:    ; implicit-def: $vgpr25
-; GCN-NEXT:    ; implicit-def: $vgpr24
-; GCN-NEXT:    ; implicit-def: $vgpr23
-; GCN-NEXT:    ; implicit-def: $vgpr22
-; GCN-NEXT:    ; implicit-def: $vgpr21
-; GCN-NEXT:    ; implicit-def: $vgpr26
-; GCN-NEXT:    ; implicit-def: $vgpr27
-; GCN-NEXT:    ; implicit-def: $vgpr28
-; GCN-NEXT:    ; implicit-def: $vgpr16
-; GCN-NEXT:    ; implicit-def: $vgpr18
-; GCN-NEXT:    ; implicit-def: $vgpr34
-; GCN-NEXT:    ; implicit-def: $vgpr35
-; GCN-NEXT:    ; implicit-def: $vgpr20
-; GCN-NEXT:    ; implicit-def: $vgpr29
-; GCN-NEXT:    ; implicit-def: $vgpr30
-; GCN-NEXT:    ; implicit-def: $vgpr31
-; GCN-NEXT:    ; implicit-def: $vgpr32
-; GCN-NEXT:    ; implicit-def: $vgpr33
-; GCN-NEXT:    ; implicit-def: $vgpr17
-; GCN-NEXT:    ; implicit-def: $vgpr19
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB28_2
-; GCN-NEXT:  .LBB28_4: ; %cmp.true
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, 3, v25
-; GCN-NEXT:    s_mov_b32 s6, 0x30000
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, 3, v24
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, 3, v23
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, 3, v22
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, 3, v21
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, 3, v26
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, 3, v27
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, 3, v28
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, 3, v16
-; GCN-NEXT:    v_add_i32_e32 v9, vcc, 3, v18
-; GCN-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GCN-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GCN-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GCN-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GCN-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GCN-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GCN-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GCN-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GCN-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GCN-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GCN-NEXT:    v_or_b32_e32 v0, v34, v0
-; GCN-NEXT:    v_or_b32_e32 v1, v35, v1
-; GCN-NEXT:    v_or_b32_e32 v2, v20, v2
-; GCN-NEXT:    v_or_b32_e32 v3, v29, v3
-; GCN-NEXT:    v_or_b32_e32 v4, v30, v4
-; GCN-NEXT:    v_or_b32_e32 v5, v31, v5
-; GCN-NEXT:    v_or_b32_e32 v6, v32, v6
-; GCN-NEXT:    v_or_b32_e32 v7, v33, v7
-; GCN-NEXT:    v_or_b32_e32 v8, v17, v8
-; GCN-NEXT:    v_or_b32_e32 v9, v19, v9
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, 0x30000, v0
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, s6, v1
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, s6, v2
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, s6, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, s6, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, s6, v5
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, s6, v6
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, s6, v7
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, s6, v8
-; GCN-NEXT:    v_add_i32_e32 v9, vcc, 0x30000, v9
+; GCN-NEXT:    s_cbranch_execz .LBB16_2
+; GCN-NEXT:  ; %bb.1: ; %cmp.true
+; GCN-NEXT:    v_add_f32_e32 v9, 1.0, v9
+; GCN-NEXT:    v_add_f32_e32 v8, 1.0, v8
+; GCN-NEXT:    v_add_f32_e32 v7, 1.0, v7
+; GCN-NEXT:    v_add_f32_e32 v6, 1.0, v6
+; GCN-NEXT:    v_add_f32_e32 v5, 1.0, v5
+; GCN-NEXT:    v_add_f32_e32 v4, 1.0, v4
+; GCN-NEXT:    v_add_f32_e32 v3, 1.0, v3
+; GCN-NEXT:    v_add_f32_e32 v2, 1.0, v2
+; GCN-NEXT:    v_add_f32_e32 v1, 1.0, v1
+; GCN-NEXT:    v_add_f32_e32 v0, 1.0, v0
+; GCN-NEXT:  .LBB16_2: ; %end
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
-; VI-LABEL: bitcast_v20i16_to_v5i64:
+; VI-LABEL: bitcast_v10f32_to_v5i64:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB28_2
+; VI-NEXT:    s_cbranch_execz .LBB16_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.true
-; VI-NEXT:    v_mov_b32_e32 v11, 3
-; VI-NEXT:    v_add_u16_e32 v10, 3, v9
-; VI-NEXT:    v_add_u16_sdwa v9, v9, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v9, v10, v9
-; VI-NEXT:    v_add_u16_e32 v10, 3, v8
-; VI-NEXT:    v_add_u16_sdwa v8, v8, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v8, v10, v8
-; VI-NEXT:    v_add_u16_e32 v10, 3, v7
-; VI-NEXT:    v_add_u16_sdwa v7, v7, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v7, v10, v7
-; VI-NEXT:    v_add_u16_e32 v10, 3, v6
-; VI-NEXT:    v_add_u16_sdwa v6, v6, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v6, v10, v6
-; VI-NEXT:    v_add_u16_e32 v10, 3, v5
-; VI-NEXT:    v_add_u16_sdwa v5, v5, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v5, v10, v5
-; VI-NEXT:    v_add_u16_e32 v10, 3, v4
-; VI-NEXT:    v_add_u16_sdwa v4, v4, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v4, v10, v4
-; VI-NEXT:    v_add_u16_e32 v10, 3, v3
-; VI-NEXT:    v_add_u16_sdwa v3, v3, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v3, v10, v3
-; VI-NEXT:    v_add_u16_e32 v10, 3, v2
-; VI-NEXT:    v_add_u16_sdwa v2, v2, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v2, v10, v2
-; VI-NEXT:    v_add_u16_e32 v10, 3, v1
-; VI-NEXT:    v_add_u16_sdwa v1, v1, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v1, v10, v1
-; VI-NEXT:    v_add_u16_e32 v10, 3, v0
-; VI-NEXT:    v_add_u16_sdwa v0, v0, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT:    v_or_b32_e32 v0, v10, v0
-; VI-NEXT:  .LBB28_2: ; %end
+; VI-NEXT:    v_add_f32_e32 v9, 1.0, v9
+; VI-NEXT:    v_add_f32_e32 v8, 1.0, v8
+; VI-NEXT:    v_add_f32_e32 v7, 1.0, v7
+; VI-NEXT:    v_add_f32_e32 v6, 1.0, v6
+; VI-NEXT:    v_add_f32_e32 v5, 1.0, v5
+; VI-NEXT:    v_add_f32_e32 v4, 1.0, v4
+; VI-NEXT:    v_add_f32_e32 v3, 1.0, v3
+; VI-NEXT:    v_add_f32_e32 v2, 1.0, v2
+; VI-NEXT:    v_add_f32_e32 v1, 1.0, v1
+; VI-NEXT:    v_add_f32_e32 v0, 1.0, v0
+; VI-NEXT:  .LBB16_2: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX9-LABEL: bitcast_v20i16_to_v5i64:
+; GFX9-LABEL: bitcast_v10f32_to_v5i64:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB28_2
+; GFX9-NEXT:    s_cbranch_execz .LBB16_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.true
-; GFX9-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
-; GFX9-NEXT:  .LBB28_2: ; %end
+; GFX9-NEXT:    v_add_f32_e32 v9, 1.0, v9
+; GFX9-NEXT:    v_add_f32_e32 v8, 1.0, v8
+; GFX9-NEXT:    v_add_f32_e32 v7, 1.0, v7
+; GFX9-NEXT:    v_add_f32_e32 v6, 1.0, v6
+; GFX9-NEXT:    v_add_f32_e32 v5, 1.0, v5
+; GFX9-NEXT:    v_add_f32_e32 v4, 1.0, v4
+; GFX9-NEXT:    v_add_f32_e32 v3, 1.0, v3
+; GFX9-NEXT:    v_add_f32_e32 v2, 1.0, v2
+; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v1
+; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v0
+; GFX9-NEXT:  .LBB16_2: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v20i16_to_v5i64:
+; GFX11-LABEL: bitcast_v10f32_to_v5i64:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX11-NEXT:    s_mov_b32 s0, exec_lo
@@ -9525,31 +6483,25 @@ define <5 x i64> @bitcast_v20i16_to_v5i64(<20 x i16> %a, i32 %b) {
 ; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB28_2
 ; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:  .LBB28_2: ; %end
+; GFX11-NEXT:    v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
+; GFX11-NEXT:    v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
+; GFX11-NEXT:    v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
+; GFX11-NEXT:    v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
+; GFX11-NEXT:    v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
+; GFX11-NEXT:  ; %bb.2: ; %end
 ; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
 cmp.true:
-  %a1 = add <20 x i16> %a, splat (i16 3)
-  %a2 = bitcast <20 x i16> %a1 to <5 x i64>
+  %a1 = fadd <10 x float> %a, splat (float 1.000000e+00)
+  %a2 = bitcast <10 x float> %a1 to <5 x i64>
   br label %end
 
 cmp.false:
-  %a3 = bitcast <20 x i16> %a to <5 x i64>
+  %a3 = bitcast <10 x float> %a to <5 x i64>
   br label %end
 
 end:
@@ -9557,81 +6509,38 @@ end:
   ret <5 x i64> %phi
 }
 
-define <20 x i16> @bitcast_v5i64_to_v20i16(<5 x i64> %a, i32 %b) {
-; GCN-LABEL: bitcast_v5i64_to_v20i16:
+define <10 x float> @bitcast_v5i64_to_v10f32(<5 x i64> %a, i32 %b) {
+; GCN-LABEL: bitcast_v5i64_to_v10f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v18, v9
-; GCN-NEXT:    v_mov_b32_e32 v16, v8
-; GCN-NEXT:    v_mov_b32_e32 v14, v7
-; GCN-NEXT:    v_mov_b32_e32 v12, v6
-; GCN-NEXT:    v_mov_b32_e32 v20, v5
-; GCN-NEXT:    v_mov_b32_e32 v8, v4
-; GCN-NEXT:    v_mov_b32_e32 v6, v3
-; GCN-NEXT:    v_mov_b32_e32 v4, v2
-; GCN-NEXT:    v_mov_b32_e32 v2, v1
 ; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; GCN-NEXT:    ; implicit-def: $vgpr1
-; GCN-NEXT:    ; implicit-def: $vgpr3
-; GCN-NEXT:    ; implicit-def: $vgpr5
-; GCN-NEXT:    ; implicit-def: $vgpr7
-; GCN-NEXT:    ; implicit-def: $vgpr9
-; GCN-NEXT:    ; implicit-def: $vgpr11
-; GCN-NEXT:    ; implicit-def: $vgpr13
-; GCN-NEXT:    ; implicit-def: $vgpr15
-; GCN-NEXT:    ; implicit-def: $vgpr17
-; GCN-NEXT:    ; implicit-def: $vgpr19
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB29_2
-; GCN-NEXT:  ; %bb.1: ; %cmp.false
-; GCN-NEXT:    v_alignbit_b32 v17, v18, v16, 16
-; GCN-NEXT:    v_alignbit_b32 v13, v14, v12, 16
-; GCN-NEXT:    v_alignbit_b32 v9, v20, v8, 16
-; GCN-NEXT:    v_alignbit_b32 v5, v6, v4, 16
-; GCN-NEXT:    v_alignbit_b32 v1, v2, v0, 16
-; GCN-NEXT:    v_lshrrev_b32_e32 v19, 16, v18
-; GCN-NEXT:    v_lshrrev_b32_e32 v15, 16, v14
-; GCN-NEXT:    v_lshrrev_b32_e32 v11, 16, v20
-; GCN-NEXT:    v_lshrrev_b32_e32 v7, 16, v6
-; GCN-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
-; GCN-NEXT:  .LBB29_2: ; %Flow
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB29_4
-; GCN-NEXT:  ; %bb.3: ; %cmp.true
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, 3, v0
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, 3, v4
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v6, vcc
+; GCN-NEXT:    s_cbranch_execz .LBB17_2
+; GCN-NEXT:  ; %bb.1: ; %cmp.true
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, 3, v8
-; GCN-NEXT:    v_addc_u32_e32 v20, vcc, 0, v20, vcc
-; GCN-NEXT:    v_add_i32_e32 v12, vcc, 3, v12
-; GCN-NEXT:    v_addc_u32_e32 v14, vcc, 0, v14, vcc
-; GCN-NEXT:    v_add_i32_e32 v16, vcc, 3, v16
-; GCN-NEXT:    v_addc_u32_e32 v18, vcc, 0, v18, vcc
-; GCN-NEXT:    v_alignbit_b32 v17, v18, v16, 16
-; GCN-NEXT:    v_alignbit_b32 v13, v14, v12, 16
-; GCN-NEXT:    v_alignbit_b32 v9, v20, v8, 16
-; GCN-NEXT:    v_alignbit_b32 v5, v6, v4, 16
-; GCN-NEXT:    v_alignbit_b32 v1, v2, v0, 16
-; GCN-NEXT:    v_lshrrev_b32_e32 v19, 16, v18
-; GCN-NEXT:    v_lshrrev_b32_e32 v15, 16, v14
-; GCN-NEXT:    v_lshrrev_b32_e32 v11, 16, v20
-; GCN-NEXT:    v_lshrrev_b32_e32 v7, 16, v6
-; GCN-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
-; GCN-NEXT:  .LBB29_4: ; %end
+; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, 3, v6
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, 3, v4
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, 3, v2
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, 3, v0
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GCN-NEXT:  .LBB17_2: ; %end
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GCN-NEXT:    v_mov_b32_e32 v10, v20
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
-; VI-LABEL: bitcast_v5i64_to_v20i16:
+; VI-LABEL: bitcast_v5i64_to_v10f32:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB29_2
+; VI-NEXT:    s_cbranch_execz .LBB17_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.true
 ; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v8
 ; VI-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
@@ -9643,18 +6552,18 @@ define <20 x i16> @bitcast_v5i64_to_v20i16(<5 x i64> %a, i32 %b) {
 ; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0
 ; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT:  .LBB29_2: ; %end
+; VI-NEXT:  .LBB17_2: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX9-LABEL: bitcast_v5i64_to_v20i16:
+; GFX9-LABEL: bitcast_v5i64_to_v10f32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB29_2
+; GFX9-NEXT:    s_cbranch_execz .LBB17_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, 3, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
@@ -9666,11 +6575,11 @@ define <20 x i16> @bitcast_v5i64_to_v20i16(<5 x i64> %a, i32 %b) {
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 3, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GFX9-NEXT:  .LBB29_2: ; %end
+; GFX9-NEXT:  .LBB17_2: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v5i64_to_v20i16:
+; GFX11-LABEL: bitcast_v5i64_to_v10f32:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX11-NEXT:    s_mov_b32 s0, exec_lo
@@ -9678,7 +6587,7 @@ define <20 x i16> @bitcast_v5i64_to_v20i16(<5 x i64> %a, i32 %b) {
 ; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB29_2
+; GFX11-NEXT:    s_cbranch_execz .LBB17_2
 ; GFX11-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX11-NEXT:    v_add_co_u32 v8, vcc_lo, v8, 3
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
@@ -9693,7 +6602,7 @@ define <20 x i16> @bitcast_v5i64_to_v20i16(<5 x i64> %a, i32 %b) {
 ; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, v0, 3
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-NEXT:  .LBB29_2: ; %end
+; GFX11-NEXT:  .LBB17_2: ; %end
 ; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
@@ -9701,16 +6610,16 @@ define <20 x i16> @bitcast_v5i64_to_v20i16(<5 x i64> %a, i32 %b) {
 
 cmp.true:
   %a1 = add <5 x i64> %a, splat (i64 3)
-  %a2 = bitcast <5 x i64> %a1 to <20 x i16>
+  %a2 = bitcast <5 x i64> %a1 to <10 x float>
   br label %end
 
 cmp.false:
-  %a3 = bitcast <5 x i64> %a to <20 x i16>
+  %a3 = bitcast <5 x i64> %a to <10 x float>
   br label %end
 
 end:
-  %phi = phi <20 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
-  ret <20 x i16> %phi
+  %phi = phi <10 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
+  ret <10 x float> %phi
 }
 
 define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) {
@@ -9787,7 +6696,7 @@ define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) {
 ; GCN-NEXT:    ; implicit-def: $vgpr22
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB30_2
+; GCN-NEXT:    s_cbranch_execz .LBB18_2
 ; GCN-NEXT:  ; %bb.1: ; %cmp.false
 ; GCN-NEXT:    v_lshlrev_b32_e32 v6, 16, v55
 ; GCN-NEXT:    v_lshlrev_b32_e32 v7, 16, v21
@@ -9849,9 +6758,9 @@ define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) {
 ; GCN-NEXT:    ; implicit-def: $vgpr47
 ; GCN-NEXT:    ; implicit-def: $vgpr45
 ; GCN-NEXT:    ; implicit-def: $vgpr44
-; GCN-NEXT:  .LBB30_2: ; %Flow
+; GCN-NEXT:  .LBB18_2: ; %Flow
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB30_4
+; GCN-NEXT:    s_cbranch_execz .LBB18_4
 ; GCN-NEXT:  ; %bb.3: ; %cmp.true
 ; GCN-NEXT:    v_cvt_f32_f16_e32 v5, v47
 ; GCN-NEXT:    v_cvt_f32_f16_e32 v6, v45
@@ -9958,7 +6867,7 @@ define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) {
 ; GCN-NEXT:    v_lshrrev_b32_e32 v30, 8, v9
 ; GCN-NEXT:    v_lshrrev_b32_e32 v23, 8, v6
 ; GCN-NEXT:    v_bfe_u32 v22, v1, 8, 8
-; GCN-NEXT:  .LBB30_4: ; %end
+; GCN-NEXT:  .LBB18_4: ; %end
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GCN-NEXT:    v_and_b32_e32 v29, 0xff, v29
 ; GCN-NEXT:    v_lshlrev_b32_e32 v38, 8, v38
@@ -10116,7 +7025,7 @@ define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) {
 ; VI-NEXT:    ; implicit-def: $vgpr11
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB30_2
+; VI-NEXT:    s_cbranch_execz .LBB18_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.false
 ; VI-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
 ; VI-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
@@ -10138,9 +7047,9 @@ define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) {
 ; VI-NEXT:    v_lshrrev_b32_e32 v48, 24, v2
 ; VI-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
 ; VI-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; VI-NEXT:  .LBB30_2: ; %Flow
+; VI-NEXT:  .LBB18_2: ; %Flow
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB30_4
+; VI-NEXT:    s_cbranch_execz .LBB18_4
 ; VI-NEXT:  ; %bb.3: ; %cmp.true
 ; VI-NEXT:    v_mov_b32_e32 v11, 0x200
 ; VI-NEXT:    v_add_f16_sdwa v23, v2, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
@@ -10203,7 +7112,7 @@ define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) {
 ; VI-NEXT:    v_bfe_u32 v35, v19, 8, 8
 ; VI-NEXT:    v_bfe_u32 v38, v21, 8, 8
 ; VI-NEXT:    v_bfe_u32 v48, v23, 8, 8
-; VI-NEXT:  .LBB30_4: ; %end
+; VI-NEXT:  .LBB18_4: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; VI-NEXT:    v_lshlrev_b16_e32 v15, 8, v15
 ; VI-NEXT:    v_lshlrev_b16_e32 v16, 8, v16
@@ -10313,7 +7222,7 @@ define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) {
 ; GFX9-NEXT:    ; implicit-def: $vgpr11
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB30_2
+; GFX9-NEXT:    s_cbranch_execz .LBB18_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.false
 ; GFX9-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
 ; GFX9-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
@@ -10345,9 +7254,9 @@ define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) {
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; GFX9-NEXT:  .LBB30_2: ; %Flow
+; GFX9-NEXT:  .LBB18_2: ; %Flow
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB30_4
+; GFX9-NEXT:    s_cbranch_execz .LBB18_4
 ; GFX9-NEXT:  ; %bb.3: ; %cmp.true
 ; GFX9-NEXT:    s_movk_i32 s6, 0x200
 ; GFX9-NEXT:    v_pk_add_f16 v10, v10, s6 op_sel_hi:[1,0]
@@ -10390,7 +7299,7 @@ define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) {
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; GFX9-NEXT:  .LBB30_4: ; %end
+; GFX9-NEXT:  .LBB18_4: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v15, 8, v15
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v16, 8, v16
@@ -10455,217 +7364,401 @@ define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v20f16_to_v40i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB30_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; GFX11-NEXT:  .LBB30_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB30_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; GFX11-NEXT:  .LBB30_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v16
-; GFX11-NEXT:    v_and_b32_e32 v48, 0xff, v48
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v15
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_lshlrev_b16 v36, 8, v36
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xff, v35
-; GFX11-NEXT:    v_lshlrev_b16 v14, 8, v14
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_lshlrev_b16 v31, 8, v31
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v30
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v13
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v39
-; GFX11-NEXT:    v_and_b32_e32 v38, 0xff, v38
-; GFX11-NEXT:    v_lshlrev_b16 v37, 8, v37
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v16
-; GFX11-NEXT:    v_or_b32_e32 v15, v48, v15
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v36
-; GFX11-NEXT:    v_or_b32_e32 v14, v35, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v31
-; GFX11-NEXT:    v_or_b32_e32 v13, v30, v13
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v39
-; GFX11-NEXT:    v_or_b32_e32 v16, v38, v37
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v15
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v13
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v29
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v28
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v27
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v16
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v26
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_lshlrev_b16 v34, 8, v34
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xff, v33
-; GFX11-NEXT:    v_lshlrev_b16 v32, 8, v32
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v25
-; GFX11-NEXT:    v_lshlrev_b16 v12, 8, v12
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v24
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v13
-; GFX11-NEXT:    v_or_b32_e32 v13, v14, v15
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v23
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v22
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v16
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v21
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v20
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v11
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v19
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v18
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v17
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v34
-; GFX11-NEXT:    v_or_b32_e32 v32, v33, v32
-; GFX11-NEXT:    v_or_b32_e32 v12, v25, v12
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v24
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v16
-; GFX11-NEXT:    v_or_b32_e32 v11, v20, v11
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v19
-; GFX11-NEXT:    v_or_b32_e32 v15, v18, v17
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v30, 16, v32
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v30
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v13
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v12
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v14
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v11
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v15
-; GFX11-NEXT:    s_clause 0x2
-; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off
-; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
-; GFX11-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v20f16_to_v40i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB18_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v18, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v20, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v22, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB18_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB18_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v18, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v20, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v22, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB18_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v16.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.l, 8, v28.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v11.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v30.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v29.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v1.h, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v15.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v29, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v13.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v26.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.l, v2.h, v14.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v30, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v5.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v24.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v15, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.l, 8, v22.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.l, 8, v12.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v13.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v13.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v14, v25
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v6.h, v12.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v20.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v29, v16
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v7.h, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v18.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v10.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v30, v28
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v26, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v15, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v16, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v13, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v17, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v19, v10
+; GFX11-TRUE16-NEXT:    s_clause 0x2
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-TRUE16-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v20f16_to_v40i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB18_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB18_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB18_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB18_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v48, 0xff, v48
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v36, 8, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v14, 8, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v31, 8, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v38, 0xff, v38
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v37, 8, v37
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v48, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v35, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v31
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v30, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v38, v37
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v34, 8, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v32, 8, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v12, 8, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v14, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v32, v33, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v25, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v20, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v18, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v15
+; GFX11-FAKE16-NEXT:    s_clause 0x2
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-FAKE16-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -10754,7 +7847,7 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) {
 ; GCN-NEXT:    ; implicit-def: $vgpr19
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB31_2
+; GCN-NEXT:    s_cbranch_execz .LBB19_2
 ; GCN-NEXT:  ; %bb.1: ; %cmp.false
 ; GCN-NEXT:    v_and_b32_e32 v0, 0xff, v0
 ; GCN-NEXT:    v_and_b32_e32 v1, 0xff, v2
@@ -10856,9 +7949,9 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) {
 ; GCN-NEXT:    ; implicit-def: $vgpr45
 ; GCN-NEXT:    ; implicit-def: $vgpr46
 ; GCN-NEXT:    ; implicit-def: $vgpr47
-; GCN-NEXT:  .LBB31_2: ; %Flow
+; GCN-NEXT:  .LBB19_2: ; %Flow
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB31_4
+; GCN-NEXT:    s_cbranch_execz .LBB19_4
 ; GCN-NEXT:  ; %bb.3: ; %cmp.true
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, 3, v59
 ; GCN-NEXT:    s_movk_i32 s6, 0x300
@@ -10961,7 +8054,7 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) {
 ; GCN-NEXT:    v_cvt_f32_f16_e32 v17, v24
 ; GCN-NEXT:    v_cvt_f32_f16_e32 v34, v22
 ; GCN-NEXT:    v_cvt_f32_f16_e32 v19, v20
-; GCN-NEXT:  .LBB31_4: ; %end
+; GCN-NEXT:  .LBB19_4: ; %end
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GCN-NEXT:    v_mov_b32_e32 v0, v31
 ; GCN-NEXT:    v_mov_b32_e32 v2, v23
@@ -11047,7 +8140,7 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) {
 ; VI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB31_2
+; VI-NEXT:    s_cbranch_execz .LBB19_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.false
 ; VI-NEXT:    v_or_b32_sdwa v0, v36, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_sdwa v1, v32, v48 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
@@ -11120,9 +8213,9 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) {
 ; VI-NEXT:    ; implicit-def: $vgpr45
 ; VI-NEXT:    ; implicit-def: $vgpr46
 ; VI-NEXT:    ; implicit-def: $vgpr47
-; VI-NEXT:  .LBB31_2: ; %Flow
+; VI-NEXT:  .LBB19_2: ; %Flow
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB31_4
+; VI-NEXT:    s_cbranch_execz .LBB19_4
 ; VI-NEXT:  ; %bb.3: ; %cmp.true
 ; VI-NEXT:    v_add_u16_e32 v0, 3, v55
 ; VI-NEXT:    v_or_b32_sdwa v0, v47, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -11198,7 +8291,7 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) {
 ; VI-NEXT:    v_or_b32_e32 v7, v12, v7
 ; VI-NEXT:    v_or_b32_e32 v8, v11, v8
 ; VI-NEXT:    v_or_b32_e32 v9, v10, v9
-; VI-NEXT:  .LBB31_4: ; %end
+; VI-NEXT:  .LBB19_4: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; VI-NEXT:    buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
 ; VI-NEXT:    buffer_load_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
@@ -11270,7 +8363,7 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB31_2
+; GFX9-NEXT:    s_cbranch_execz .LBB19_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.false
 ; GFX9-NEXT:    v_or_b32_sdwa v0, v36, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; GFX9-NEXT:    v_or_b32_sdwa v1, v33, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
@@ -11344,9 +8437,9 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    ; implicit-def: $vgpr44
 ; GFX9-NEXT:    ; implicit-def: $vgpr47
 ; GFX9-NEXT:    ; implicit-def: $vgpr46
-; GFX9-NEXT:  .LBB31_2: ; %Flow
+; GFX9-NEXT:  .LBB19_2: ; %Flow
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB31_4
+; GFX9-NEXT:    s_cbranch_execz .LBB19_4
 ; GFX9-NEXT:  ; %bb.3: ; %cmp.true
 ; GFX9-NEXT:    s_waitcnt vmcnt(2)
 ; GFX9-NEXT:    v_add_u16_e32 v0, 3, v42
@@ -11421,7 +8514,7 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    v_perm_b32 v7, v12, v7, s6
 ; GFX9-NEXT:    v_perm_b32 v8, v11, v8, s6
 ; GFX9-NEXT:    v_perm_b32 v9, v10, v9, s6
-; GFX9-NEXT:  .LBB31_4: ; %end
+; GFX9-NEXT:  .LBB19_4: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
 ; GFX9-NEXT:    buffer_load_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
@@ -11434,255 +8527,496 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v40i8_to_v20f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v33, v10 :: v_dual_mov_b32 v34, v8
-; GFX11-NEXT:    v_dual_mov_b32 v38, v6 :: v_dual_mov_b32 v35, v4
-; GFX11-NEXT:    v_dual_mov_b32 v37, v2 :: v_dual_mov_b32 v36, v0
-; GFX11-NEXT:    s_clause 0x9
-; GFX11-NEXT:    scratch_load_b32 v0, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32
-; GFX11-NEXT:    scratch_load_u16 v4, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_u16 v6, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_u16 v8, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_u16 v10, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_u16 v66, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_u16 v68, off, s32 offset:20
-; GFX11-NEXT:    scratch_load_u16 v65, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_u16 v67, off, s32 offset:4
-; GFX11-NEXT:    v_dual_mov_b32 v31, v14 :: v_dual_mov_b32 v32, v12
-; GFX11-NEXT:    v_lshlrev_b16 v48, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v49, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v51, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v50, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v52, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v64, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v69, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(9)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(8)
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(7)
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v4
-; GFX11-NEXT:    s_waitcnt vmcnt(6)
-; GFX11-NEXT:    v_lshlrev_b16 v29, 8, v6
-; GFX11-NEXT:    s_waitcnt vmcnt(5)
-; GFX11-NEXT:    v_lshlrev_b16 v70, 8, v8
-; GFX11-NEXT:    s_waitcnt vmcnt(4)
-; GFX11-NEXT:    v_lshlrev_b16 v71, 8, v10
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB31_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB31_4
-; GFX11-NEXT:  .LBB31_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB31_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v36
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v37
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v35
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v38
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v34
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v31
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v18
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v48
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v49
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v51
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v50
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v55
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v39
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v53
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v52
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v54
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v17
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v1, v3, v2, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v2, v5, v4, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v3, v7, v6, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v4, v9, v8, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v24
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v26
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v30
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v67
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v65
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v68
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v66
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v21
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v19
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v64
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v25
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v69
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v23
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v27
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v29
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v70
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v71
-; GFX11-NEXT:    v_perm_b32 v5, v6, v5, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v6, v8, v7, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v7, v10, v9, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v8, v12, v11, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v9, v14, v13, 0x5040100
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr67
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB31_2
-; GFX11-NEXT:  .LBB31_4: ; %cmp.true
-; GFX11-NEXT:    s_waitcnt vmcnt(2)
-; GFX11-NEXT:    v_add_nc_u16 v0, v68, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v66, 3
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_add_nc_u16 v3, v65, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v28, 3
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_nc_u16 v2, v67, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_or_b32_e32 v0, v70, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v71, v1
-; GFX11-NEXT:    v_or_b32_e32 v3, v29, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v2, v27, v2
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v0, v69, v4
-; GFX11-NEXT:    v_add_nc_u16 v1, v30, 3
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v3, v20, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v26, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, v24, 3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, v22, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v23, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_perm_b32 v8, v11, v8, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v0, v25, v0
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v21, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v64, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, v18, 3
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v16, 3
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v32, 3
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v19, v4
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v4, v31, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v0, v54, v0
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v1, v53, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, v34, 3
-; GFX11-NEXT:    v_add_nc_u16 v16, v36, 3
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v17, v3
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v52, v4
-; GFX11-NEXT:    v_add_nc_u16 v4, v35, 3
-; GFX11-NEXT:    v_add_nc_u16 v17, v37, 3
-; GFX11-NEXT:    v_add_nc_u16 v18, v38, 3
-; GFX11-NEXT:    v_add_nc_u16 v19, v33, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v17
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v19
-; GFX11-NEXT:    v_or_b32_e32 v2, v55, v2
-; GFX11-NEXT:    v_or_b32_e32 v4, v51, v4
-; GFX11-NEXT:    v_or_b32_e32 v16, v48, v16
-; GFX11-NEXT:    v_or_b32_e32 v17, v49, v17
-; GFX11-NEXT:    v_or_b32_e32 v18, v50, v18
-; GFX11-NEXT:    v_or_b32_e32 v19, v39, v19
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v16, 0x300, v16
-; GFX11-NEXT:    v_add_nc_u16 v17, 0x300, v17
-; GFX11-NEXT:    v_add_nc_u16 v18, 0x300, v18
-; GFX11-NEXT:    v_add_nc_u16 v19, 0x300, v19
-; GFX11-NEXT:    v_add_nc_u16 v20, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v21, 0x300, v0
-; GFX11-NEXT:    v_perm_b32 v0, v17, v16, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v1, v18, v4, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v2, v19, v2, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v3, v20, v3, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v4, v21, v15, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v5, v14, v5, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v6, v13, v6, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v7, v12, v7, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v9, v10, v9, 0x5040100
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v40i8_to_v20f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x9
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v37, off, s32 offset:36
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v33, off, s32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v34, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v34, off, s32 offset:16
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v35, off, s32 offset:24
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v36, off, s32 offset:32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v31, off, s32 offset:28
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v32, off, s32 offset:20
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32 offset:12
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v32, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v35.h, v29.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.h, v27.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.h, v25.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.h, v23.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.l, v21.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.l, v19.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v26.h, v17.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v24.h, v24.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v23.l, v22.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v24.l, v20.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.l, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.h, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.h, v14.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v23.h, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v17.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v17.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.l, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v27.h, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v25.l, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v25.h, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v26.h, 8, v26.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v27.l, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v29.l, 8, v29.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v29.h, 8, v29.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v30.h, 8, v30.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.l, 8, v28.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v35.h, 8, v35.h
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(8)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v28.h, 8, v33.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v34.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(6)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v34.l, 8, v34.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(5)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v34.h, 8, v35.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(4)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v35.l, 8, v36.l
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v37
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB19_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB19_4
+; GFX11-TRUE16-NEXT:  .LBB19_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB19_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v17.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v21.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v17.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v23.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v16.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v20.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v22.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v23.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v24.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v26.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v30.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v32.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v31.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v32.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.h, 0xff, v31.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v18.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v19.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v1.h, v20.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v27.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v2.h, v16.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v25.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v3.h, v25.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v26.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.h, v4.h, v27.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v29.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.h, v5.h, v29.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v30.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v6.h, v33.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v35.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v7.h, v28.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v33.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.h, v8.h, v34.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v34.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.h, v9.h, v35.l
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB19_2
+; GFX11-TRUE16-NEXT:  .LBB19_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v32.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v31.h, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v32.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v31.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v28.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v34.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v35.l, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v33.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v34.l, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v35.h, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v30.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v24.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v26.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v24.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v23.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v28.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v30.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v33.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v29.l, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v22.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v21.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v22.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v20.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v29.h, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v26.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v27.l, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v25.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v25.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v23.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v16.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v21.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v17.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v19.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v17.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v27.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v16.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v19.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v20.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.h, v18.l, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v18.h, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, 0x300, v10.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v10.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, 0x300, v11.l
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v20f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v33, v10 :: v_dual_mov_b32 v34, v8
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v38, v6 :: v_dual_mov_b32 v35, v4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v37, v2 :: v_dual_mov_b32 v36, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x9
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v0, off, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v4, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v6, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v8, off, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v10, off, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v66, off, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v68, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v65, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v67, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v31, v14 :: v_dual_mov_b32 v32, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v48, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v49, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v51, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v50, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v53, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v52, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v64, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v69, 8, v29
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(9)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(8)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(7)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(6)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v29, 8, v6
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(5)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v70, 8, v8
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(4)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v71, 8, v10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB19_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB19_4
+; GFX11-FAKE16-NEXT:  .LBB19_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB19_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v37
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v38
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v48
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v49
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v51
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v50
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v52
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v17
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v5, v4, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v7, v6, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v9, v8, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v30
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v67
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v65
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v68
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v66
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v64
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v69
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v70
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v71
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v6, v5, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v8, v7, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v10, v9, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v12, v11, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v14, v13, 0x5040100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB19_2
+; GFX11-FAKE16-NEXT:  .LBB19_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v68, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v66, 3
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v65, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v28, 3
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v67, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v70, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v71, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v29, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v27, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v69, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v30, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v20, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v26, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v24, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v22, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v23, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v11, v8, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v25, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v21, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v64, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v18, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v16, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v32, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v19, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v31, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v54, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v53, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v34, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, v36, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v17, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v52, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v35, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, v37, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, v38, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, v33, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v55, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v51, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v48, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v49, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v50, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v39, v19
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, 0x300, v16
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, 0x300, v17
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, 0x300, v18
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, 0x300, v19
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v17, v16, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v18, v4, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v19, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v20, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v21, v15, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v14, v5, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v13, v6, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v12, v7, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v10, v9, 0x5040100
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -11728,14 +9062,14 @@ define <5 x double> @bitcast_v20f16_to_v5f64(<20 x half> %a, i32 %b) {
 ; GCN-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execnz .LBB32_3
+; GCN-NEXT:    s_cbranch_execnz .LBB20_3
 ; GCN-NEXT:  ; %bb.1: ; %Flow
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execnz .LBB32_4
-; GCN-NEXT:  .LBB32_2: ; %end
+; GCN-NEXT:    s_cbranch_execnz .LBB20_4
+; GCN-NEXT:  .LBB20_2: ; %end
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
-; GCN-NEXT:  .LBB32_3: ; %cmp.false
+; GCN-NEXT:  .LBB20_3: ; %cmp.false
 ; GCN-NEXT:    v_lshlrev_b32_e32 v0, 16, v36
 ; GCN-NEXT:    v_lshlrev_b32_e32 v1, 16, v34
 ; GCN-NEXT:    v_or_b32_e32 v0, v35, v0
@@ -11777,8 +9111,8 @@ define <5 x double> @bitcast_v20f16_to_v5f64(<20 x half> %a, i32 %b) {
 ; GCN-NEXT:    ; implicit-def: $vgpr19
 ; GCN-NEXT:    ; implicit-def: $vgpr16
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB32_2
-; GCN-NEXT:  .LBB32_4: ; %cmp.true
+; GCN-NEXT:    s_cbranch_execz .LBB20_2
+; GCN-NEXT:  .LBB20_4: ; %cmp.true
 ; GCN-NEXT:    v_cvt_f32_f16_e32 v0, v36
 ; GCN-NEXT:    v_cvt_f32_f16_e32 v1, v35
 ; GCN-NEXT:    v_cvt_f32_f16_e32 v2, v34
@@ -11869,7 +9203,7 @@ define <5 x double> @bitcast_v20f16_to_v5f64(<20 x half> %a, i32 %b) {
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB32_2
+; VI-NEXT:    s_cbranch_execz .LBB20_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.true
 ; VI-NEXT:    v_mov_b32_e32 v10, 0x200
 ; VI-NEXT:    v_add_f16_sdwa v11, v9, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
@@ -11902,7 +9236,7 @@ define <5 x double> @bitcast_v20f16_to_v5f64(<20 x half> %a, i32 %b) {
 ; VI-NEXT:    v_add_f16_e32 v0, 0x200, v0
 ; VI-NEXT:    v_or_b32_e32 v1, v1, v11
 ; VI-NEXT:    v_or_b32_e32 v0, v0, v10
-; VI-NEXT:  .LBB32_2: ; %end
+; VI-NEXT:  .LBB20_2: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -11913,7 +9247,7 @@ define <5 x double> @bitcast_v20f16_to_v5f64(<20 x half> %a, i32 %b) {
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB32_2
+; GFX9-NEXT:    s_cbranch_execz .LBB20_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX9-NEXT:    s_movk_i32 s6, 0x200
 ; GFX9-NEXT:    v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]
@@ -11926,7 +9260,7 @@ define <5 x double> @bitcast_v20f16_to_v5f64(<20 x half> %a, i32 %b) {
 ; GFX9-NEXT:    v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
 ; GFX9-NEXT:    v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
 ; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
-; GFX9-NEXT:  .LBB32_2: ; %end
+; GFX9-NEXT:  .LBB20_2: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -11938,7 +9272,7 @@ define <5 x double> @bitcast_v20f16_to_v5f64(<20 x half> %a, i32 %b) {
 ; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB32_2
+; GFX11-NEXT:    s_cbranch_execz .LBB20_2
 ; GFX11-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX11-NEXT:    v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
 ; GFX11-NEXT:    v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
@@ -11950,7 +9284,7 @@ define <5 x double> @bitcast_v20f16_to_v5f64(<20 x half> %a, i32 %b) {
 ; GFX11-NEXT:    v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
 ; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
 ; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
-; GFX11-NEXT:  .LBB32_2: ; %end
+; GFX11-NEXT:  .LBB20_2: ; %end
 ; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
@@ -11997,7 +9331,7 @@ define <20 x half> @bitcast_v5f64_to_v20f16(<5 x double> %a, i32 %b) {
 ; GCN-NEXT:    ; implicit-def: $vgpr19
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB33_2
+; GCN-NEXT:    s_cbranch_execz .LBB21_2
 ; GCN-NEXT:  ; %bb.1: ; %cmp.false
 ; GCN-NEXT:    v_lshrrev_b32_e32 v11, 16, v9
 ; GCN-NEXT:    v_lshrrev_b32_e32 v13, 16, v8
@@ -12034,9 +9368,9 @@ define <20 x half> @bitcast_v5f64_to_v20f16(<5 x double> %a, i32 %b) {
 ; GCN-NEXT:    ; implicit-def: $vgpr4
 ; GCN-NEXT:    ; implicit-def: $vgpr6
 ; GCN-NEXT:    ; implicit-def: $vgpr8
-; GCN-NEXT:  .LBB33_2: ; %Flow
+; GCN-NEXT:  .LBB21_2: ; %Flow
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB33_4
+; GCN-NEXT:    s_cbranch_execz .LBB21_4
 ; GCN-NEXT:  ; %bb.3: ; %cmp.true
 ; GCN-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
 ; GCN-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
@@ -12073,7 +9407,7 @@ define <20 x half> @bitcast_v5f64_to_v20f16(<5 x double> %a, i32 %b) {
 ; GCN-NEXT:    v_cvt_f32_f16_e32 v27, v27
 ; GCN-NEXT:    v_cvt_f32_f16_e32 v28, v28
 ; GCN-NEXT:    v_cvt_f32_f16_e32 v29, v29
-; GCN-NEXT:  .LBB33_4: ; %end
+; GCN-NEXT:  .LBB21_4: ; %end
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GCN-NEXT:    v_mov_b32_e32 v0, v24
 ; GCN-NEXT:    v_mov_b32_e32 v1, v29
@@ -12094,14 +9428,14 @@ define <20 x half> @bitcast_v5f64_to_v20f16(<5 x double> %a, i32 %b) {
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB33_2
+; VI-NEXT:    s_cbranch_execz .LBB21_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.true
 ; VI-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
 ; VI-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
 ; VI-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
 ; VI-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
 ; VI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
-; VI-NEXT:  .LBB33_2: ; %end
+; VI-NEXT:  .LBB21_2: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -12112,14 +9446,14 @@ define <20 x half> @bitcast_v5f64_to_v20f16(<5 x double> %a, i32 %b) {
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB33_2
+; GFX9-NEXT:    s_cbranch_execz .LBB21_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX9-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
 ; GFX9-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
 ; GFX9-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
 ; GFX9-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
 ; GFX9-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
-; GFX9-NEXT:  .LBB33_2: ; %end
+; GFX9-NEXT:  .LBB21_2: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -12131,14 +9465,14 @@ define <20 x half> @bitcast_v5f64_to_v20f16(<5 x double> %a, i32 %b) {
 ; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB33_2
+; GFX11-NEXT:    s_cbranch_execz .LBB21_2
 ; GFX11-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX11-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
 ; GFX11-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
 ; GFX11-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
 ; GFX11-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
 ; GFX11-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
-; GFX11-NEXT:  .LBB33_2: ; %end
+; GFX11-NEXT:  .LBB21_2: ; %end
 ; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
@@ -12186,14 +9520,14 @@ define <5 x i64> @bitcast_v20f16_to_v5i64(<20 x half> %a, i32 %b) {
 ; GCN-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execnz .LBB34_3
+; GCN-NEXT:    s_cbranch_execnz .LBB22_3
 ; GCN-NEXT:  ; %bb.1: ; %Flow
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execnz .LBB34_4
-; GCN-NEXT:  .LBB34_2: ; %end
+; GCN-NEXT:    s_cbranch_execnz .LBB22_4
+; GCN-NEXT:  .LBB22_2: ; %end
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
-; GCN-NEXT:  .LBB34_3: ; %cmp.false
+; GCN-NEXT:  .LBB22_3: ; %cmp.false
 ; GCN-NEXT:    v_lshlrev_b32_e32 v0, 16, v36
 ; GCN-NEXT:    v_lshlrev_b32_e32 v1, 16, v34
 ; GCN-NEXT:    v_or_b32_e32 v0, v35, v0
@@ -12235,8 +9569,8 @@ define <5 x i64> @bitcast_v20f16_to_v5i64(<20 x half> %a, i32 %b) {
 ; GCN-NEXT:    ; implicit-def: $vgpr19
 ; GCN-NEXT:    ; implicit-def: $vgpr16
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB34_2
-; GCN-NEXT:  .LBB34_4: ; %cmp.true
+; GCN-NEXT:    s_cbranch_execz .LBB22_2
+; GCN-NEXT:  .LBB22_4: ; %cmp.true
 ; GCN-NEXT:    v_cvt_f32_f16_e32 v0, v36
 ; GCN-NEXT:    v_cvt_f32_f16_e32 v1, v35
 ; GCN-NEXT:    v_cvt_f32_f16_e32 v2, v34
@@ -12327,7 +9661,7 @@ define <5 x i64> @bitcast_v20f16_to_v5i64(<20 x half> %a, i32 %b) {
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB34_2
+; VI-NEXT:    s_cbranch_execz .LBB22_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.true
 ; VI-NEXT:    v_mov_b32_e32 v10, 0x200
 ; VI-NEXT:    v_add_f16_sdwa v11, v9, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
@@ -12360,7 +9694,7 @@ define <5 x i64> @bitcast_v20f16_to_v5i64(<20 x half> %a, i32 %b) {
 ; VI-NEXT:    v_add_f16_e32 v0, 0x200, v0
 ; VI-NEXT:    v_or_b32_e32 v1, v1, v11
 ; VI-NEXT:    v_or_b32_e32 v0, v0, v10
-; VI-NEXT:  .LBB34_2: ; %end
+; VI-NEXT:  .LBB22_2: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -12371,7 +9705,7 @@ define <5 x i64> @bitcast_v20f16_to_v5i64(<20 x half> %a, i32 %b) {
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB34_2
+; GFX9-NEXT:    s_cbranch_execz .LBB22_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX9-NEXT:    s_movk_i32 s6, 0x200
 ; GFX9-NEXT:    v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]
@@ -12384,7 +9718,7 @@ define <5 x i64> @bitcast_v20f16_to_v5i64(<20 x half> %a, i32 %b) {
 ; GFX9-NEXT:    v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
 ; GFX9-NEXT:    v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
 ; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
-; GFX9-NEXT:  .LBB34_2: ; %end
+; GFX9-NEXT:  .LBB22_2: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -12396,7 +9730,7 @@ define <5 x i64> @bitcast_v20f16_to_v5i64(<20 x half> %a, i32 %b) {
 ; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB34_2
+; GFX11-NEXT:    s_cbranch_execz .LBB22_2
 ; GFX11-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX11-NEXT:    v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
 ; GFX11-NEXT:    v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
@@ -12408,7 +9742,7 @@ define <5 x i64> @bitcast_v20f16_to_v5i64(<20 x half> %a, i32 %b) {
 ; GFX11-NEXT:    v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
 ; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
 ; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
-; GFX11-NEXT:  .LBB34_2: ; %end
+; GFX11-NEXT:  .LBB22_2: ; %end
 ; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
@@ -12465,14 +9799,14 @@ define <20 x half> @bitcast_v5i64_to_v20f16(<5 x i64> %a, i32 %b) {
 ; GCN-NEXT:    ; implicit-def: $vgpr19
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execnz .LBB35_3
+; GCN-NEXT:    s_cbranch_execnz .LBB23_3
 ; GCN-NEXT:  ; %bb.1: ; %Flow
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execnz .LBB35_4
-; GCN-NEXT:  .LBB35_2: ; %end
+; GCN-NEXT:    s_cbranch_execnz .LBB23_4
+; GCN-NEXT:  .LBB23_2: ; %end
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
-; GCN-NEXT:  .LBB35_3: ; %cmp.false
+; GCN-NEXT:  .LBB23_3: ; %cmp.false
 ; GCN-NEXT:    v_lshrrev_b32_e32 v0, 16, v22
 ; GCN-NEXT:    v_lshrrev_b32_e32 v1, 16, v21
 ; GCN-NEXT:    v_lshrrev_b32_e32 v3, 16, v24
@@ -12514,8 +9848,8 @@ define <20 x half> @bitcast_v5i64_to_v20f16(<5 x i64> %a, i32 %b) {
 ; GCN-NEXT:    ; implicit-def: $vgpr21
 ; GCN-NEXT:    ; implicit-def: $vgpr22
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB35_2
-; GCN-NEXT:  .LBB35_4: ; %cmp.true
+; GCN-NEXT:    s_cbranch_execz .LBB23_2
+; GCN-NEXT:  .LBB23_4: ; %cmp.true
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, 3, v20
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v29, vcc
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, 3, v27
@@ -12566,7 +9900,7 @@ define <20 x half> @bitcast_v5i64_to_v20f16(<5 x i64> %a, i32 %b) {
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB35_2
+; VI-NEXT:    s_cbranch_execz .LBB23_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.true
 ; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v8
 ; VI-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
@@ -12578,7 +9912,7 @@ define <20 x half> @bitcast_v5i64_to_v20f16(<5 x i64> %a, i32 %b) {
 ; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0
 ; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT:  .LBB35_2: ; %end
+; VI-NEXT:  .LBB23_2: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -12589,7 +9923,7 @@ define <20 x half> @bitcast_v5i64_to_v20f16(<5 x i64> %a, i32 %b) {
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB35_2
+; GFX9-NEXT:    s_cbranch_execz .LBB23_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, 3, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
@@ -12601,7 +9935,7 @@ define <20 x half> @bitcast_v5i64_to_v20f16(<5 x i64> %a, i32 %b) {
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 3, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GFX9-NEXT:  .LBB35_2: ; %end
+; GFX9-NEXT:  .LBB23_2: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -12613,7 +9947,7 @@ define <20 x half> @bitcast_v5i64_to_v20f16(<5 x i64> %a, i32 %b) {
 ; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB35_2
+; GFX11-NEXT:    s_cbranch_execz .LBB23_2
 ; GFX11-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX11-NEXT:    v_add_co_u32 v8, vcc_lo, v8, 3
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
@@ -12628,7 +9962,7 @@ define <20 x half> @bitcast_v5i64_to_v20f16(<5 x i64> %a, i32 %b) {
 ; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, v0, 3
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-NEXT:  .LBB35_2: ; %end
+; GFX11-NEXT:  .LBB23_2: ; %end
 ; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
@@ -12707,7 +10041,7 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) {
 ; GCN-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB36_2
+; GCN-NEXT:    s_cbranch_execz .LBB24_2
 ; GCN-NEXT:  ; %bb.1: ; %cmp.false
 ; GCN-NEXT:    v_and_b32_e32 v0, 0xff, v31
 ; GCN-NEXT:    v_and_b32_e32 v1, 0xff, v32
@@ -12819,9 +10153,9 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) {
 ; GCN-NEXT:    ; implicit-def: $vgpr25
 ; GCN-NEXT:    ; implicit-def: $vgpr43
 ; GCN-NEXT:    ; implicit-def: $vgpr27
-; GCN-NEXT:  .LBB36_2: ; %Flow
+; GCN-NEXT:  .LBB24_2: ; %Flow
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB36_4
+; GCN-NEXT:    s_cbranch_execz .LBB24_4
 ; GCN-NEXT:  ; %bb.3: ; %cmp.true
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, 3, v31
 ; GCN-NEXT:    s_movk_i32 s6, 0x300
@@ -12935,7 +10269,7 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) {
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, s7, v7
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, s7, v8
 ; GCN-NEXT:    v_add_i32_e32 v9, vcc, 0x3000000, v9
-; GCN-NEXT:  .LBB36_4: ; %end
+; GCN-NEXT:  .LBB24_4: ; %end
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GCN-NEXT:    buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
@@ -13008,7 +10342,7 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) {
 ; VI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB36_2
+; VI-NEXT:    s_cbranch_execz .LBB24_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.false
 ; VI-NEXT:    v_or_b32_sdwa v0, v31, v56 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_sdwa v1, v32, v47 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
@@ -13081,9 +10415,9 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) {
 ; VI-NEXT:    ; implicit-def: $vgpr21
 ; VI-NEXT:    ; implicit-def: $vgpr19
 ; VI-NEXT:    ; implicit-def: $vgpr17
-; VI-NEXT:  .LBB36_2: ; %Flow
+; VI-NEXT:  .LBB24_2: ; %Flow
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB36_4
+; VI-NEXT:    s_cbranch_execz .LBB24_4
 ; VI-NEXT:  ; %bb.3: ; %cmp.true
 ; VI-NEXT:    v_add_u16_e32 v0, 3, v31
 ; VI-NEXT:    v_add_u16_e32 v1, 3, v32
@@ -13157,7 +10491,7 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) {
 ; VI-NEXT:    v_add_u16_e32 v10, 0x300, v10
 ; VI-NEXT:    v_add_u16_sdwa v9, v11, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_e32 v9, v10, v9
-; VI-NEXT:  .LBB36_4: ; %end
+; VI-NEXT:  .LBB24_4: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; VI-NEXT:    buffer_load_dword v56, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
 ; VI-NEXT:    buffer_load_dword v47, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
@@ -13231,7 +10565,7 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB36_2
+; GFX9-NEXT:    s_cbranch_execz .LBB24_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.false
 ; GFX9-NEXT:    v_or_b32_sdwa v0, v31, v56 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; GFX9-NEXT:    v_or_b32_sdwa v1, v32, v47 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
@@ -13304,9 +10638,9 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    ; implicit-def: $vgpr21
 ; GFX9-NEXT:    ; implicit-def: $vgpr19
 ; GFX9-NEXT:    ; implicit-def: $vgpr17
-; GFX9-NEXT:  .LBB36_2: ; %Flow
+; GFX9-NEXT:  .LBB24_2: ; %Flow
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB36_4
+; GFX9-NEXT:    s_cbranch_execz .LBB24_4
 ; GFX9-NEXT:  ; %bb.3: ; %cmp.true
 ; GFX9-NEXT:    v_add_u16_e32 v0, 3, v31
 ; GFX9-NEXT:    v_add_u16_e32 v1, 3, v32
@@ -13380,7 +10714,7 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    v_add_u16_e32 v9, 0x300, v9
 ; GFX9-NEXT:    v_add_u16_sdwa v10, v10, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 ; GFX9-NEXT:    v_or_b32_e32 v9, v9, v10
-; GFX9-NEXT:  .LBB36_4: ; %end
+; GFX9-NEXT:  .LBB24_4: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    buffer_load_dword v56, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
 ; GFX9-NEXT:    buffer_load_dword v47, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
@@ -13394,291 +10728,585 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v40i8_to_v5f64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v36, v10 :: v_dual_mov_b32 v35, v8
-; GFX11-NEXT:    v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v4
-; GFX11-NEXT:    v_dual_mov_b32 v32, v2 :: v_dual_mov_b32 v31, v0
-; GFX11-NEXT:    s_clause 0x9
-; GFX11-NEXT:    scratch_load_b32 v0, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32
-; GFX11-NEXT:    scratch_load_u16 v4, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_u16 v6, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_u16 v8, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_u16 v10, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_u16 v39, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_u16 v48, off, s32 offset:20
-; GFX11-NEXT:    scratch_load_u16 v49, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_u16 v50, off, s32 offset:4
-; GFX11-NEXT:    v_dual_mov_b32 v38, v14 :: v_dual_mov_b32 v37, v12
-; GFX11-NEXT:    v_lshlrev_b16 v67, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v68, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v69, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v70, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v71, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v64, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v66, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v51, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v52, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v29, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(9)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(8)
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(7)
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v4
-; GFX11-NEXT:    s_waitcnt vmcnt(6)
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v6
-; GFX11-NEXT:    s_waitcnt vmcnt(5)
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v8
-; GFX11-NEXT:    s_waitcnt vmcnt(4)
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v10
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB36_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB36_4
-; GFX11-NEXT:  .LBB36_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB36_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v31
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v34
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v35
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v36
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v37
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v38
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v18
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v67
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v68
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v69
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v70
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v71
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v54
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v55
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v64
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v65
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v66
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v7
-; GFX11-NEXT:    v_or_b32_e32 v4, v8, v9
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v24
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v26
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v30
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v50
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v49
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v48
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v39
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v51
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v52
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v53
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v27
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v29
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v17
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v19
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v21
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v23
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v25
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v8, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v9, v13, v14
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr67
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB36_2
-; GFX11-NEXT:  .LBB36_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v31, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v32, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v33, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v34, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v35, 3
-; GFX11-NEXT:    v_add_nc_u16 v5, v36, 3
-; GFX11-NEXT:    v_add_nc_u16 v6, v37, 3
-; GFX11-NEXT:    v_add_nc_u16 v7, v38, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v16, 3
-; GFX11-NEXT:    v_add_nc_u16 v9, v18, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_or_b32_e32 v0, v67, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v68, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v69, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v70, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v71, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v54, v5
-; GFX11-NEXT:    v_or_b32_e32 v6, v55, v6
-; GFX11-NEXT:    v_or_b32_e32 v7, v64, v7
-; GFX11-NEXT:    v_or_b32_e32 v8, v65, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v66, v9
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v7
-; GFX11-NEXT:    v_or_b32_e32 v4, v8, v9
-; GFX11-NEXT:    v_add_nc_u16 v5, v20, 3
-; GFX11-NEXT:    v_add_nc_u16 v6, v22, 3
-; GFX11-NEXT:    v_add_nc_u16 v7, v24, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v26, 3
-; GFX11-NEXT:    v_add_nc_u16 v9, v28, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, v30, 3
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_nc_u16 v11, v50, 3
-; GFX11-NEXT:    v_add_nc_u16 v12, v49, 3
-; GFX11-NEXT:    v_add_nc_u16 v13, v48, 3
-; GFX11-NEXT:    v_add_nc_u16 v14, v39, 3
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v51, v5
-; GFX11-NEXT:    v_or_b32_e32 v6, v52, v6
-; GFX11-NEXT:    v_or_b32_e32 v7, v53, v7
-; GFX11-NEXT:    v_or_b32_e32 v8, v27, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v29, v9
-; GFX11-NEXT:    v_or_b32_e32 v10, v17, v10
-; GFX11-NEXT:    v_or_b32_e32 v11, v19, v11
-; GFX11-NEXT:    v_or_b32_e32 v12, v21, v12
-; GFX11-NEXT:    v_or_b32_e32 v13, v23, v13
-; GFX11-NEXT:    v_or_b32_e32 v14, v25, v14
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v10
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v11
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v12
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v13
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v14
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v8, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v9, v13, v14
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v40i8_to_v5f64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x9
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v49, off, s32 offset:36
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v36, off, s32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v36, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v37, off, s32 offset:16
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v37, off, s32 offset:24
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v38, off, s32 offset:32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32 offset:28
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v31, off, s32 offset:20
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v32, off, s32 offset:12
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v32, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v38.h, v29.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v39.l, v27.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v39.h, v25.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v48.l, v23.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.h, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.h, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v23.l, v14.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.h, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.h, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v34.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v35.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v35.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v29.h, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v30.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.l, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v34.l, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.h, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v24.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v25.l, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v25.h, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v26.h, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.l, 8, v48.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v39.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v39.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.l, 8, v38.h
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(8)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.l, 8, v36.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v36.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(6)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.l, 8, v37.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(5)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v37.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(4)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.l, 8, v38.l
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v49
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB24_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB24_4
+; GFX11-TRUE16-NEXT:  .LBB24_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB24_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v35.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v34.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v35.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v29.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v28.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v29.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v33.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v0.h, v30.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v1.h, v33.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v34.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v27.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v27.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v22.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v21.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v25.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v0.h, v24.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v1.h, v25.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v26.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v5, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v7, v8
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v20.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v26.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v19.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v9, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v4, v12
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v5.h, v19.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v6.h, v20.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v30.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v32.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v32.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v31.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v31.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v3, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v16.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v5.h, v16.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v17.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v6.h, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v18.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v10, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v12, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v14, v15
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v8, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v9, v17
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB24_2
+; GFX11-TRUE16-NEXT:  .LBB24_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v35.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v34.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v35.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v29.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v28.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v29.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v33.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v30.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v33.h, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v34.l, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v27.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v23.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v27.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v22.h, 3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v23.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v25.l, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v21.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v24.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v25.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v5, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v7, v8
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, v20.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, v24.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v28.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v26.h, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, v22.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, v26.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v5.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v18.h, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v19.h, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v21.l, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.h, v19.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v20.h, v6.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v5.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v6.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v9, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v4, v12
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v5.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, v30.l, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, v32.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, v32.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, v31.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v31.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v5.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v16.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.h, v16.h, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v17.l, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v17.h, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v18.l, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v3, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v9
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v5.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v5.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v6.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v6.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v10, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v12, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v14, v15
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v8, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v9, v17
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v5f64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v36, v10 :: v_dual_mov_b32 v35, v8
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v32, v2 :: v_dual_mov_b32 v31, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x9
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v0, off, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v4, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v6, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v8, off, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v10, off, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v39, off, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v48, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v49, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v50, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v38, v14 :: v_dual_mov_b32 v37, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v67, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v68, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v69, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v70, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v71, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v64, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v66, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v51, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v52, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v53, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v29, 8, v29
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(9)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(8)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(7)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(6)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v6
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(5)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v8
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(4)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB24_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB24_4
+; GFX11-FAKE16-NEXT:  .LBB24_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB24_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v37
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v38
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v68
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v69
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v70
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v71
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v64
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v66
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v8, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v30
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v50
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v49
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v48
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v51
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v52
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v13, v14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB24_2
+; GFX11-FAKE16-NEXT:  .LBB24_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v31, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v32, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v33, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v34, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v35, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v36, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v37, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v38, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v16, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v18, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v67, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v68, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v69, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v70, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v71, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v54, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v55, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v64, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v65, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v66, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v8, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v20, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v22, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v24, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v26, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v28, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v30, 3
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, v50, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v49, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v48, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v39, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v51, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v52, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v53, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v27, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v29, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v17, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v19, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v21, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v23, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v25, v14
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v13
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v13, v14
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -13733,7 +11361,7 @@ define <40 x i8> @bitcast_v5f64_to_v40i8(<5 x double> %a, i32 %b) {
 ; GCN-NEXT:    ; implicit-def: $vgpr20
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB37_2
+; GCN-NEXT:    s_cbranch_execz .LBB25_2
 ; GCN-NEXT:  ; %bb.1: ; %cmp.false
 ; GCN-NEXT:    v_alignbit_b32 v11, v10, v9, 24
 ; GCN-NEXT:    v_alignbit_b32 v12, v10, v9, 16
@@ -13765,9 +11393,9 @@ define <40 x i8> @bitcast_v5f64_to_v40i8(<5 x double> %a, i32 %b) {
 ; GCN-NEXT:    v_lshrrev_b32_e32 v38, 24, v2
 ; GCN-NEXT:    v_lshrrev_b32_e32 v39, 16, v2
 ; GCN-NEXT:    v_lshrrev_b32_e32 v48, 8, v2
-; GCN-NEXT:  .LBB37_2: ; %Flow
+; GCN-NEXT:  .LBB25_2: ; %Flow
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB37_4
+; GCN-NEXT:    s_cbranch_execz .LBB25_4
 ; GCN-NEXT:  ; %bb.3: ; %cmp.true
 ; GCN-NEXT:    v_add_f64 v[1:2], v[1:2], 1.0
 ; GCN-NEXT:    v_add_f64 v[3:4], v[3:4], 1.0
@@ -13804,7 +11432,7 @@ define <40 x i8> @bitcast_v5f64_to_v40i8(<5 x double> %a, i32 %b) {
 ; GCN-NEXT:    v_lshrrev_b32_e32 v38, 24, v2
 ; GCN-NEXT:    v_lshrrev_b32_e32 v39, 16, v2
 ; GCN-NEXT:    v_lshrrev_b32_e32 v48, 8, v2
-; GCN-NEXT:  .LBB37_4: ; %end
+; GCN-NEXT:  .LBB25_4: ; %end
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GCN-NEXT:    v_and_b32_e32 v49, 0xff, v1
 ; GCN-NEXT:    v_lshlrev_b32_e32 v50, 8, v35
@@ -13954,7 +11582,7 @@ define <40 x i8> @bitcast_v5f64_to_v40i8(<5 x double> %a, i32 %b) {
 ; VI-NEXT:    ; implicit-def: $vgpr11
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB37_2
+; VI-NEXT:    s_cbranch_execz .LBB25_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.false
 ; VI-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
 ; VI-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
@@ -13986,9 +11614,9 @@ define <40 x i8> @bitcast_v5f64_to_v40i8(<5 x double> %a, i32 %b) {
 ; VI-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
 ; VI-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
 ; VI-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; VI-NEXT:  .LBB37_2: ; %Flow
+; VI-NEXT:  .LBB25_2: ; %Flow
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB37_4
+; VI-NEXT:    s_cbranch_execz .LBB25_4
 ; VI-NEXT:  ; %bb.3: ; %cmp.true
 ; VI-NEXT:    v_add_f64 v[9:10], v[9:10], 1.0
 ; VI-NEXT:    v_add_f64 v[7:8], v[7:8], 1.0
@@ -14025,7 +11653,7 @@ define <40 x i8> @bitcast_v5f64_to_v40i8(<5 x double> %a, i32 %b) {
 ; VI-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
 ; VI-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
 ; VI-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; VI-NEXT:  .LBB37_4: ; %end
+; VI-NEXT:  .LBB25_4: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; VI-NEXT:    v_lshlrev_b16_e32 v15, 8, v15
 ; VI-NEXT:    v_lshlrev_b16_e32 v16, 8, v16
@@ -14135,7 +11763,7 @@ define <40 x i8> @bitcast_v5f64_to_v40i8(<5 x double> %a, i32 %b) {
 ; GFX9-NEXT:    ; implicit-def: $vgpr11
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB37_2
+; GFX9-NEXT:    s_cbranch_execz .LBB25_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.false
 ; GFX9-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
 ; GFX9-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
@@ -14167,9 +11795,9 @@ define <40 x i8> @bitcast_v5f64_to_v40i8(<5 x double> %a, i32 %b) {
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; GFX9-NEXT:  .LBB37_2: ; %Flow
+; GFX9-NEXT:  .LBB25_2: ; %Flow
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB37_4
+; GFX9-NEXT:    s_cbranch_execz .LBB25_4
 ; GFX9-NEXT:  ; %bb.3: ; %cmp.true
 ; GFX9-NEXT:    v_add_f64 v[9:10], v[9:10], 1.0
 ; GFX9-NEXT:    v_add_f64 v[7:8], v[7:8], 1.0
@@ -14206,7 +11834,7 @@ define <40 x i8> @bitcast_v5f64_to_v40i8(<5 x double> %a, i32 %b) {
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; GFX9-NEXT:  .LBB37_4: ; %end
+; GFX9-NEXT:  .LBB25_4: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v15, 8, v15
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v16, 8, v16
@@ -14271,212 +11899,391 @@ define <40 x i8> @bitcast_v5f64_to_v40i8(<5 x double> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v5f64_to_v40i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB37_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; GFX11-NEXT:  .LBB37_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB37_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_f64 v[9:10], v[9:10], 1.0
-; GFX11-NEXT:    v_add_f64 v[7:8], v[7:8], 1.0
-; GFX11-NEXT:    v_add_f64 v[5:6], v[5:6], 1.0
-; GFX11-NEXT:    v_add_f64 v[3:4], v[3:4], 1.0
-; GFX11-NEXT:    v_add_f64 v[1:2], v[1:2], 1.0
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; GFX11-NEXT:  .LBB37_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v16
-; GFX11-NEXT:    v_and_b32_e32 v48, 0xff, v48
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v15
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_lshlrev_b16 v36, 8, v36
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xff, v35
-; GFX11-NEXT:    v_lshlrev_b16 v14, 8, v14
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_lshlrev_b16 v31, 8, v31
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v30
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v13
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v39
-; GFX11-NEXT:    v_and_b32_e32 v38, 0xff, v38
-; GFX11-NEXT:    v_lshlrev_b16 v37, 8, v37
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v16
-; GFX11-NEXT:    v_or_b32_e32 v15, v48, v15
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v36
-; GFX11-NEXT:    v_or_b32_e32 v14, v35, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v31
-; GFX11-NEXT:    v_or_b32_e32 v13, v30, v13
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v39
-; GFX11-NEXT:    v_or_b32_e32 v16, v38, v37
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v15
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v13
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v29
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v28
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v27
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v16
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v26
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_lshlrev_b16 v34, 8, v34
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xff, v33
-; GFX11-NEXT:    v_lshlrev_b16 v32, 8, v32
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v25
-; GFX11-NEXT:    v_lshlrev_b16 v12, 8, v12
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v24
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v13
-; GFX11-NEXT:    v_or_b32_e32 v13, v14, v15
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v23
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v22
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v16
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v21
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v20
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v11
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v19
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v18
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v17
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v34
-; GFX11-NEXT:    v_or_b32_e32 v32, v33, v32
-; GFX11-NEXT:    v_or_b32_e32 v12, v25, v12
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v24
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v16
-; GFX11-NEXT:    v_or_b32_e32 v11, v20, v11
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v19
-; GFX11-NEXT:    v_or_b32_e32 v15, v18, v17
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v30, 16, v32
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v30
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v13
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v12
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v14
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v11
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v15
-; GFX11-NEXT:    s_clause 0x2
-; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off
-; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
-; GFX11-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v5f64_to_v40i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB25_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v18, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v20, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v22, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB25_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB25_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_f64 v[9:10], v[9:10], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[7:8], v[7:8], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[5:6], v[5:6], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[3:4], v[3:4], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[1:2], v[1:2], 1.0
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v18, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v20, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v22, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB25_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v16.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.l, 8, v28.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v11.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v30.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v29.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v1.h, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v15.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v29, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v13.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v26.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.l, v2.h, v14.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v30, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v5.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v24.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v15, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.l, 8, v22.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.l, 8, v12.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v13.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v13.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v14, v25
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v6.h, v12.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v20.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v29, v16
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v7.h, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v18.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v10.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v30, v28
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v26, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v15, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v16, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v13, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v17, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v19, v10
+; GFX11-TRUE16-NEXT:    s_clause 0x2
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-TRUE16-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v5f64_to_v40i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB25_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB25_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB25_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_f64 v[9:10], v[9:10], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[7:8], v[7:8], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[5:6], v[5:6], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[3:4], v[3:4], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[1:2], v[1:2], 1.0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB25_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v48, 0xff, v48
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v36, 8, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v14, 8, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v31, 8, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v38, 0xff, v38
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v37, 8, v37
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v48, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v35, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v31
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v30, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v38, v37
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v34, 8, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v32, 8, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v12, 8, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v14, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v32, v33, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v25, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v20, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v18, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v15
+; GFX11-FAKE16-NEXT:    s_clause 0x2
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-FAKE16-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -14553,7 +12360,7 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) {
 ; GCN-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB38_2
+; GCN-NEXT:    s_cbranch_execz .LBB26_2
 ; GCN-NEXT:  ; %bb.1: ; %cmp.false
 ; GCN-NEXT:    v_and_b32_e32 v0, 0xff, v31
 ; GCN-NEXT:    v_and_b32_e32 v1, 0xff, v32
@@ -14665,9 +12472,9 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) {
 ; GCN-NEXT:    ; implicit-def: $vgpr25
 ; GCN-NEXT:    ; implicit-def: $vgpr43
 ; GCN-NEXT:    ; implicit-def: $vgpr27
-; GCN-NEXT:  .LBB38_2: ; %Flow
+; GCN-NEXT:  .LBB26_2: ; %Flow
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB38_4
+; GCN-NEXT:    s_cbranch_execz .LBB26_4
 ; GCN-NEXT:  ; %bb.3: ; %cmp.true
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, 3, v31
 ; GCN-NEXT:    s_movk_i32 s6, 0x300
@@ -14781,7 +12588,7 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) {
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, s7, v7
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, s7, v8
 ; GCN-NEXT:    v_add_i32_e32 v9, vcc, 0x3000000, v9
-; GCN-NEXT:  .LBB38_4: ; %end
+; GCN-NEXT:  .LBB26_4: ; %end
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GCN-NEXT:    buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v46, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
@@ -14854,7 +12661,7 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) {
 ; VI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB38_2
+; VI-NEXT:    s_cbranch_execz .LBB26_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.false
 ; VI-NEXT:    v_or_b32_sdwa v0, v31, v56 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_sdwa v1, v32, v47 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
@@ -14927,9 +12734,9 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) {
 ; VI-NEXT:    ; implicit-def: $vgpr21
 ; VI-NEXT:    ; implicit-def: $vgpr19
 ; VI-NEXT:    ; implicit-def: $vgpr17
-; VI-NEXT:  .LBB38_2: ; %Flow
+; VI-NEXT:  .LBB26_2: ; %Flow
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB38_4
+; VI-NEXT:    s_cbranch_execz .LBB26_4
 ; VI-NEXT:  ; %bb.3: ; %cmp.true
 ; VI-NEXT:    v_add_u16_e32 v0, 3, v31
 ; VI-NEXT:    v_add_u16_e32 v1, 3, v32
@@ -15003,7 +12810,7 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) {
 ; VI-NEXT:    v_add_u16_e32 v10, 0x300, v10
 ; VI-NEXT:    v_add_u16_sdwa v9, v11, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 ; VI-NEXT:    v_or_b32_e32 v9, v10, v9
-; VI-NEXT:  .LBB38_4: ; %end
+; VI-NEXT:  .LBB26_4: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; VI-NEXT:    buffer_load_dword v56, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
 ; VI-NEXT:    buffer_load_dword v47, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
@@ -15077,7 +12884,7 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB38_2
+; GFX9-NEXT:    s_cbranch_execz .LBB26_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.false
 ; GFX9-NEXT:    v_or_b32_sdwa v0, v31, v56 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; GFX9-NEXT:    v_or_b32_sdwa v1, v32, v47 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
@@ -15150,9 +12957,9 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    ; implicit-def: $vgpr21
 ; GFX9-NEXT:    ; implicit-def: $vgpr19
 ; GFX9-NEXT:    ; implicit-def: $vgpr17
-; GFX9-NEXT:  .LBB38_2: ; %Flow
+; GFX9-NEXT:  .LBB26_2: ; %Flow
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB38_4
+; GFX9-NEXT:    s_cbranch_execz .LBB26_4
 ; GFX9-NEXT:  ; %bb.3: ; %cmp.true
 ; GFX9-NEXT:    v_add_u16_e32 v0, 3, v31
 ; GFX9-NEXT:    v_add_u16_e32 v1, 3, v32
@@ -15226,7 +13033,7 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    v_add_u16_e32 v9, 0x300, v9
 ; GFX9-NEXT:    v_add_u16_sdwa v10, v10, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 ; GFX9-NEXT:    v_or_b32_e32 v9, v9, v10
-; GFX9-NEXT:  .LBB38_4: ; %end
+; GFX9-NEXT:  .LBB26_4: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    buffer_load_dword v56, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
 ; GFX9-NEXT:    buffer_load_dword v47, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
@@ -15240,291 +13047,585 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v40i8_to_v5i64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v36, v10 :: v_dual_mov_b32 v35, v8
-; GFX11-NEXT:    v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v4
-; GFX11-NEXT:    v_dual_mov_b32 v32, v2 :: v_dual_mov_b32 v31, v0
-; GFX11-NEXT:    s_clause 0x9
-; GFX11-NEXT:    scratch_load_b32 v0, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32
-; GFX11-NEXT:    scratch_load_u16 v4, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_u16 v6, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_u16 v8, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_u16 v10, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_u16 v39, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_u16 v48, off, s32 offset:20
-; GFX11-NEXT:    scratch_load_u16 v49, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_u16 v50, off, s32 offset:4
-; GFX11-NEXT:    v_dual_mov_b32 v38, v14 :: v_dual_mov_b32 v37, v12
-; GFX11-NEXT:    v_lshlrev_b16 v67, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v68, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v69, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v70, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v71, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v64, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v66, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v51, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v52, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v29, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(9)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(8)
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(7)
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v4
-; GFX11-NEXT:    s_waitcnt vmcnt(6)
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v6
-; GFX11-NEXT:    s_waitcnt vmcnt(5)
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v8
-; GFX11-NEXT:    s_waitcnt vmcnt(4)
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v10
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB38_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB38_4
-; GFX11-NEXT:  .LBB38_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB38_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v31
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v34
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v35
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v36
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v37
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v38
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v18
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v67
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v68
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v69
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v70
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v71
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v54
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v55
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v64
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v65
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v66
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v7
-; GFX11-NEXT:    v_or_b32_e32 v4, v8, v9
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v24
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v26
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v30
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v50
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v49
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v48
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v39
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v51
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v52
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v53
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v27
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v29
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v17
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v19
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v21
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v23
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v25
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v8, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v9, v13, v14
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr67
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB38_2
-; GFX11-NEXT:  .LBB38_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v31, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v32, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v33, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v34, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v35, 3
-; GFX11-NEXT:    v_add_nc_u16 v5, v36, 3
-; GFX11-NEXT:    v_add_nc_u16 v6, v37, 3
-; GFX11-NEXT:    v_add_nc_u16 v7, v38, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v16, 3
-; GFX11-NEXT:    v_add_nc_u16 v9, v18, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_or_b32_e32 v0, v67, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v68, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v69, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v70, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v71, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v54, v5
-; GFX11-NEXT:    v_or_b32_e32 v6, v55, v6
-; GFX11-NEXT:    v_or_b32_e32 v7, v64, v7
-; GFX11-NEXT:    v_or_b32_e32 v8, v65, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v66, v9
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v7
-; GFX11-NEXT:    v_or_b32_e32 v4, v8, v9
-; GFX11-NEXT:    v_add_nc_u16 v5, v20, 3
-; GFX11-NEXT:    v_add_nc_u16 v6, v22, 3
-; GFX11-NEXT:    v_add_nc_u16 v7, v24, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v26, 3
-; GFX11-NEXT:    v_add_nc_u16 v9, v28, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, v30, 3
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_nc_u16 v11, v50, 3
-; GFX11-NEXT:    v_add_nc_u16 v12, v49, 3
-; GFX11-NEXT:    v_add_nc_u16 v13, v48, 3
-; GFX11-NEXT:    v_add_nc_u16 v14, v39, 3
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v51, v5
-; GFX11-NEXT:    v_or_b32_e32 v6, v52, v6
-; GFX11-NEXT:    v_or_b32_e32 v7, v53, v7
-; GFX11-NEXT:    v_or_b32_e32 v8, v27, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v29, v9
-; GFX11-NEXT:    v_or_b32_e32 v10, v17, v10
-; GFX11-NEXT:    v_or_b32_e32 v11, v19, v11
-; GFX11-NEXT:    v_or_b32_e32 v12, v21, v12
-; GFX11-NEXT:    v_or_b32_e32 v13, v23, v13
-; GFX11-NEXT:    v_or_b32_e32 v14, v25, v14
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v10
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v11
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v12
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v13
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v14
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v7, v9, v10
-; GFX11-NEXT:    v_or_b32_e32 v8, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v9, v13, v14
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v40i8_to_v5i64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x9
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v49, off, s32 offset:36
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v36, off, s32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v36, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v37, off, s32 offset:16
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v37, off, s32 offset:24
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v38, off, s32 offset:32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32 offset:28
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v31, off, s32 offset:20
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v32, off, s32 offset:12
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v32, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v38.h, v29.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v39.l, v27.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v39.h, v25.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v48.l, v23.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.h, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.h, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v23.l, v14.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.h, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.h, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v34.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v35.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v35.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v29.h, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v30.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.l, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v33.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v34.l, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.h, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v24.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v25.l, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v25.h, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v26.h, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.l, 8, v48.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v39.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v39.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.l, 8, v38.h
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(8)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.l, 8, v36.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v36.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(6)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.l, 8, v37.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(5)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v37.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(4)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.l, 8, v38.l
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v49
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB26_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB26_4
+; GFX11-TRUE16-NEXT:  .LBB26_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB26_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v35.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v34.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v35.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v29.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v28.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v29.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v33.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v0.h, v30.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v1.h, v33.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v34.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v27.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v27.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v22.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v21.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v25.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v0.h, v24.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v1.h, v25.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v26.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v5, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v7, v8
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v20.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v26.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v19.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v9, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v4, v12
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v5.h, v19.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v6.h, v20.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v30.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v32.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v32.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v31.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v31.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v3, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v16.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v5.h, v16.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v17.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v6.h, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v18.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v10, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v12, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v14, v15
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v8, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v9, v17
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB26_2
+; GFX11-TRUE16-NEXT:  .LBB26_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v35.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v34.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v35.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v29.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v28.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v29.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v33.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v30.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v33.h, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v34.l, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v27.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v23.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v27.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v22.h, 3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v23.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v25.l, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v21.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v24.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v25.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v5, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v7, v8
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, v20.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, v24.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v28.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v26.h, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, v22.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, v26.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v5.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v18.h, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v19.h, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v21.l, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.h, v19.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v20.h, v6.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v5.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v6.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v9, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v4, v12
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v5.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, v30.l, 3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, v32.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, v32.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, v31.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v31.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v5.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v16.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.h, v16.h, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v17.l, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v17.h, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v18.l, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v3, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v9
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v5.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v5.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v6.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v6.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v10, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v12, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v14, v15
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v8, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v9, v17
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v5i64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v36, v10 :: v_dual_mov_b32 v35, v8
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v32, v2 :: v_dual_mov_b32 v31, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x9
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v0, off, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v4, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v6, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v8, off, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v10, off, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v39, off, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v48, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v49, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v50, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v38, v14 :: v_dual_mov_b32 v37, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v67, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v68, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v69, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v70, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v71, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v64, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v66, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v51, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v52, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v53, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v29, 8, v29
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(9)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(8)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(7)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(6)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v6
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(5)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v8
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(4)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB26_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB26_4
+; GFX11-FAKE16-NEXT:  .LBB26_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB26_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v37
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v38
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v68
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v69
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v70
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v71
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v55
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v64
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v66
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v8, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v30
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v50
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v49
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v48
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v51
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v52
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v13, v14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB26_2
+; GFX11-FAKE16-NEXT:  .LBB26_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v31, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v32, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v33, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v34, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v35, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v36, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v37, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v38, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v16, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v18, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v67, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v68, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v69, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v70, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v71, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v54, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v55, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v64, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v65, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v66, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v8, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v20, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v22, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v24, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v26, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v28, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v30, 3
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, v50, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v49, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v48, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v39, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v51, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v52, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v53, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v27, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v29, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v17, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v19, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v21, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v23, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v25, v14
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v13
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v9, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v13, v14
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -15579,7 +13680,7 @@ define <40 x i8> @bitcast_v5i64_to_v40i8(<5 x i64> %a, i32 %b) {
 ; GCN-NEXT:    ; implicit-def: $vgpr17
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB39_2
+; GCN-NEXT:    s_cbranch_execz .LBB27_2
 ; GCN-NEXT:  ; %bb.1: ; %cmp.false
 ; GCN-NEXT:    v_alignbit_b32 v11, v10, v9, 24
 ; GCN-NEXT:    v_alignbit_b32 v12, v10, v9, 16
@@ -15611,9 +13712,9 @@ define <40 x i8> @bitcast_v5i64_to_v40i8(<5 x i64> %a, i32 %b) {
 ; GCN-NEXT:    v_lshrrev_b32_e32 v38, 24, v2
 ; GCN-NEXT:    v_lshrrev_b32_e32 v39, 16, v2
 ; GCN-NEXT:    v_lshrrev_b32_e32 v48, 8, v2
-; GCN-NEXT:  .LBB39_2: ; %Flow
+; GCN-NEXT:  .LBB27_2: ; %Flow
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB39_4
+; GCN-NEXT:    s_cbranch_execz .LBB27_4
 ; GCN-NEXT:  ; %bb.3: ; %cmp.true
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, 3, v1
 ; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
@@ -15655,7 +13756,7 @@ define <40 x i8> @bitcast_v5i64_to_v40i8(<5 x i64> %a, i32 %b) {
 ; GCN-NEXT:    v_lshrrev_b32_e32 v38, 24, v2
 ; GCN-NEXT:    v_lshrrev_b32_e32 v39, 16, v2
 ; GCN-NEXT:    v_lshrrev_b32_e32 v48, 8, v2
-; GCN-NEXT:  .LBB39_4: ; %end
+; GCN-NEXT:  .LBB27_4: ; %end
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GCN-NEXT:    v_and_b32_e32 v49, 0xff, v1
 ; GCN-NEXT:    v_lshlrev_b32_e32 v35, 8, v35
@@ -15805,7 +13906,7 @@ define <40 x i8> @bitcast_v5i64_to_v40i8(<5 x i64> %a, i32 %b) {
 ; VI-NEXT:    ; implicit-def: $vgpr11
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB39_2
+; VI-NEXT:    s_cbranch_execz .LBB27_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.false
 ; VI-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
 ; VI-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
@@ -15837,9 +13938,9 @@ define <40 x i8> @bitcast_v5i64_to_v40i8(<5 x i64> %a, i32 %b) {
 ; VI-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
 ; VI-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
 ; VI-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; VI-NEXT:  .LBB39_2: ; %Flow
+; VI-NEXT:  .LBB27_2: ; %Flow
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB39_4
+; VI-NEXT:    s_cbranch_execz .LBB27_4
 ; VI-NEXT:  ; %bb.3: ; %cmp.true
 ; VI-NEXT:    v_add_u32_e32 v1, vcc, 3, v1
 ; VI-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
@@ -15881,7 +13982,7 @@ define <40 x i8> @bitcast_v5i64_to_v40i8(<5 x i64> %a, i32 %b) {
 ; VI-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
 ; VI-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
 ; VI-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; VI-NEXT:  .LBB39_4: ; %end
+; VI-NEXT:  .LBB27_4: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; VI-NEXT:    v_lshlrev_b16_e32 v15, 8, v15
 ; VI-NEXT:    v_lshlrev_b16_e32 v16, 8, v16
@@ -15991,7 +14092,7 @@ define <40 x i8> @bitcast_v5i64_to_v40i8(<5 x i64> %a, i32 %b) {
 ; GFX9-NEXT:    ; implicit-def: $vgpr11
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB39_2
+; GFX9-NEXT:    s_cbranch_execz .LBB27_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.false
 ; GFX9-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
 ; GFX9-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
@@ -16023,9 +14124,9 @@ define <40 x i8> @bitcast_v5i64_to_v40i8(<5 x i64> %a, i32 %b) {
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; GFX9-NEXT:  .LBB39_2: ; %Flow
+; GFX9-NEXT:  .LBB27_2: ; %Flow
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB39_4
+; GFX9-NEXT:    s_cbranch_execz .LBB27_4
 ; GFX9-NEXT:  ; %bb.3: ; %cmp.true
 ; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, 3, v1
 ; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
@@ -16067,7 +14168,7 @@ define <40 x i8> @bitcast_v5i64_to_v40i8(<5 x i64> %a, i32 %b) {
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
 ; GFX9-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; GFX9-NEXT:  .LBB39_4: ; %end
+; GFX9-NEXT:  .LBB27_4: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v15, 8, v15
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v16, 8, v16
@@ -16132,220 +14233,407 @@ define <40 x i8> @bitcast_v5i64_to_v40i8(<5 x i64> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v5i64_to_v40i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB39_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; GFX11-NEXT:  .LBB39_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB39_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_co_u32 v3, vcc_lo, v3, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v4, null, 0, v4, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v5, vcc_lo, v5, 3
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v6, null, 0, v6, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v7, vcc_lo, v7, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v8, null, 0, v8, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v9, vcc_lo, v9, 3
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v10, null, 0, v10, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v1, vcc_lo, v1, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v2, null, 0, v2, vcc_lo
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
-; GFX11-NEXT:  .LBB39_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v16
-; GFX11-NEXT:    v_and_b32_e32 v48, 0xff, v48
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v15
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_lshlrev_b16 v36, 8, v36
-; GFX11-NEXT:    v_and_b32_e32 v35, 0xff, v35
-; GFX11-NEXT:    v_lshlrev_b16 v14, 8, v14
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_lshlrev_b16 v31, 8, v31
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v30
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v13
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v39
-; GFX11-NEXT:    v_and_b32_e32 v38, 0xff, v38
-; GFX11-NEXT:    v_lshlrev_b16 v37, 8, v37
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v16
-; GFX11-NEXT:    v_or_b32_e32 v15, v48, v15
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v36
-; GFX11-NEXT:    v_or_b32_e32 v14, v35, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v31
-; GFX11-NEXT:    v_or_b32_e32 v13, v30, v13
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v39
-; GFX11-NEXT:    v_or_b32_e32 v16, v38, v37
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v15
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v13
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v29
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v28
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v27
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v16
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v26
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_lshlrev_b16 v34, 8, v34
-; GFX11-NEXT:    v_and_b32_e32 v33, 0xff, v33
-; GFX11-NEXT:    v_lshlrev_b16 v32, 8, v32
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v25
-; GFX11-NEXT:    v_lshlrev_b16 v12, 8, v12
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v24
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v13
-; GFX11-NEXT:    v_or_b32_e32 v13, v14, v15
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v23
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v22
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v16
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v21
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v20
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v11
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v19
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v18
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v17
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v34
-; GFX11-NEXT:    v_or_b32_e32 v32, v33, v32
-; GFX11-NEXT:    v_or_b32_e32 v12, v25, v12
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v24
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v16
-; GFX11-NEXT:    v_or_b32_e32 v11, v20, v11
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v19
-; GFX11-NEXT:    v_or_b32_e32 v15, v18, v17
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v30, 16, v32
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v30
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v13
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v12
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v14
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v11
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v15
-; GFX11-NEXT:    s_clause 0x2
-; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off
-; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
-; GFX11-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v5i64_to_v40i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB27_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v18, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v20, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v22, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB27_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB27_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v3, vcc_lo, v3, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v4, null, 0, v4, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v5, vcc_lo, v5, 3
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v6, null, 0, v6, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v7, vcc_lo, v7, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v8, null, 0, v8, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v9, vcc_lo, v9, 3
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v10, null, 0, v10, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v1, vcc_lo, v1, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v2, null, 0, v2, vcc_lo
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v18, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v20, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v22, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB27_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v16.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.l, 8, v28.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v11.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v30.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v29.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v1.h, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v15.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v29, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v13.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v26.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v28.l, v2.h, v14.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v30, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v5.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v24.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v15, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.l, 8, v22.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.l, 8, v12.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v13.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v13.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v14, v25
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v6.h, v12.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v20.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v29, v16
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v7.h, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v18.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v10.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v30, v28
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v26, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v15, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v16, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v13, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v17, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v19, v10
+; GFX11-TRUE16-NEXT:    s_clause 0x2
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-TRUE16-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v5i64_to_v40i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB27_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB27_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB27_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v3, vcc_lo, v3, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v4, null, 0, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v5, vcc_lo, v5, 3
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v6, null, 0, v6, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v7, vcc_lo, v7, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v8, null, 0, v8, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v9, vcc_lo, v9, 3
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v10, null, 0, v10, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v1, vcc_lo, v1, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v2, null, 0, v2, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[12:13], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[15:16], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v19, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v20, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB27_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v48, 0xff, v48
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v36, 8, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v35, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v14, 8, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v31, 8, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v39
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v38, 0xff, v38
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v37, 8, v37
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v48, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v36
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v35, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v31
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v30, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v38, v37
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v34, 8, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v33, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v32, 8, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v12, 8, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v14, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v32, v33, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v25, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v20, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v18, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v15
+; GFX11-FAKE16-NEXT:    s_clause 0x2
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-FAKE16-NEXT:    scratch_store_b64 v0, v[9:10], off offset:32
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -16371,14 +14659,14 @@ define <5 x i64> @bitcast_v5f64_to_v5i64(<5 x double> %a, i32 %b) {
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB40_2
+; GCN-NEXT:    s_cbranch_execz .LBB28_2
 ; GCN-NEXT:  ; %bb.1: ; %cmp.true
 ; GCN-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
 ; GCN-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
 ; GCN-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
 ; GCN-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
 ; GCN-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
-; GCN-NEXT:  .LBB40_2: ; %end
+; GCN-NEXT:  .LBB28_2: ; %end
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -16389,14 +14677,14 @@ define <5 x i64> @bitcast_v5f64_to_v5i64(<5 x double> %a, i32 %b) {
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB40_2
+; VI-NEXT:    s_cbranch_execz .LBB28_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.true
 ; VI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
 ; VI-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
 ; VI-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
 ; VI-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
 ; VI-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
-; VI-NEXT:  .LBB40_2: ; %end
+; VI-NEXT:  .LBB28_2: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -16407,14 +14695,14 @@ define <5 x i64> @bitcast_v5f64_to_v5i64(<5 x double> %a, i32 %b) {
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB40_2
+; GFX9-NEXT:    s_cbranch_execz .LBB28_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX9-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
 ; GFX9-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
 ; GFX9-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
 ; GFX9-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
 ; GFX9-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
-; GFX9-NEXT:  .LBB40_2: ; %end
+; GFX9-NEXT:  .LBB28_2: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -16426,14 +14714,14 @@ define <5 x i64> @bitcast_v5f64_to_v5i64(<5 x double> %a, i32 %b) {
 ; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB40_2
+; GFX11-NEXT:    s_cbranch_execz .LBB28_2
 ; GFX11-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX11-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0
 ; GFX11-NEXT:    v_add_f64 v[2:3], v[2:3], 1.0
 ; GFX11-NEXT:    v_add_f64 v[4:5], v[4:5], 1.0
 ; GFX11-NEXT:    v_add_f64 v[6:7], v[6:7], 1.0
 ; GFX11-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
-; GFX11-NEXT:  .LBB40_2: ; %end
+; GFX11-NEXT:  .LBB28_2: ; %end
 ; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
@@ -16461,7 +14749,7 @@ define <5 x double> @bitcast_v5i64_to_v5f64(<5 x i64> %a, i32 %b) {
 ; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GCN-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; GCN-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GCN-NEXT:    s_cbranch_execz .LBB41_2
+; GCN-NEXT:    s_cbranch_execz .LBB29_2
 ; GCN-NEXT:  ; %bb.1: ; %cmp.true
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, 3, v0
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
@@ -16473,7 +14761,7 @@ define <5 x double> @bitcast_v5i64_to_v5f64(<5 x i64> %a, i32 %b) {
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, 3, v8
 ; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
-; GCN-NEXT:  .LBB41_2: ; %end
+; GCN-NEXT:  .LBB29_2: ; %end
 ; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -16484,7 +14772,7 @@ define <5 x double> @bitcast_v5i64_to_v5f64(<5 x i64> %a, i32 %b) {
 ; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; VI-NEXT:    s_cbranch_execz .LBB41_2
+; VI-NEXT:    s_cbranch_execz .LBB29_2
 ; VI-NEXT:  ; %bb.1: ; %cmp.true
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0
 ; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
@@ -16496,7 +14784,7 @@ define <5 x double> @bitcast_v5i64_to_v5f64(<5 x i64> %a, i32 %b) {
 ; VI-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
 ; VI-NEXT:    v_add_u32_e32 v8, vcc, 3, v8
 ; VI-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
-; VI-NEXT:  .LBB41_2: ; %end
+; VI-NEXT:  .LBB29_2: ; %end
 ; VI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -16507,7 +14795,7 @@ define <5 x double> @bitcast_v5i64_to_v5f64(<5 x i64> %a, i32 %b) {
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
 ; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9-NEXT:    s_cbranch_execz .LBB41_2
+; GFX9-NEXT:    s_cbranch_execz .LBB29_2
 ; GFX9-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 3, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
@@ -16519,7 +14807,7 @@ define <5 x double> @bitcast_v5i64_to_v5f64(<5 x i64> %a, i32 %b) {
 ; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, 3, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
-; GFX9-NEXT:  .LBB41_2: ; %end
+; GFX9-NEXT:  .LBB29_2: ; %end
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -16531,7 +14819,7 @@ define <5 x double> @bitcast_v5i64_to_v5f64(<5 x i64> %a, i32 %b) {
 ; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB41_2
+; GFX11-NEXT:    s_cbranch_execz .LBB29_2
 ; GFX11-NEXT:  ; %bb.1: ; %cmp.true
 ; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, v0, 3
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
@@ -16546,7 +14834,7 @@ define <5 x double> @bitcast_v5i64_to_v5f64(<5 x i64> %a, i32 %b) {
 ; GFX11-NEXT:    v_add_co_u32 v8, vcc_lo, v8, 3
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX11-NEXT:    v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
-; GFX11-NEXT:  .LBB41_2: ; %end
+; GFX11-NEXT:  .LBB29_2: ; %end
 ; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
index 332c971e5709f..7f8b733038f1e 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
@@ -3,7 +3,8 @@
 ; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define float @bitcast_i32_to_f32(i32 %a, i32 %b) {
 ; GCN-LABEL: bitcast_i32_to_f32:
@@ -684,37 +685,70 @@ define i32 @bitcast_v2bf16_to_i32(<2 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v2bf16_to_i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v1
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB7_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_bfe_u32 v2, v1, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v3, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v4, 0x400000, v1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_or_b32_e32 v5, 0x400000, v0
-; GFX11-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v0, v0, v1, 0x7060302
-; GFX11-NEXT:  .LBB7_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_i32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v1
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB7_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v2, v1, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v1, v0
+; GFX11-TRUE16-NEXT:  .LBB7_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_i32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v1
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB7_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v2, v1, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v1, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB7_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -965,37 +999,64 @@ define <4 x i8> @bitcast_i32_to_v4i8(i32 %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_i32_to_v4i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB10_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB10_4
-; GFX11-NEXT:  .LBB10_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB10_3: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB10_2
-; GFX11-NEXT:  .LBB10_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_i32_to_v4i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 3, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-TRUE16-NEXT:  ; %bb.4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_i32_to_v4i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB10_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB10_4
+; GFX11-FAKE16-NEXT:  .LBB10_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB10_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB10_2
+; GFX11-FAKE16-NEXT:  .LBB10_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v0, 3, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -1138,59 +1199,113 @@ define i32 @bitcast_v4i8_to_i32(<4 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v4i8_to_i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mov_b32_e32 v5, v0
-; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v3, 8, v3
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    ; implicit-def: $vgpr0
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v4
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB11_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB11_4
-; GFX11-NEXT:  .LBB11_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB11_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v5
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB11_2
-; GFX11-NEXT:  .LBB11_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v5, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v2, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v3, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v4i8_to_i32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB11_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB11_4
+; GFX11-TRUE16-NEXT:  .LBB11_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB11_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v0.h, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB11_2
+; GFX11-TRUE16-NEXT:  .LBB11_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v2.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v2.l, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v1.h, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v4i8_to_i32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB11_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB11_4
+; GFX11-FAKE16-NEXT:  .LBB11_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB11_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB11_2
+; GFX11-FAKE16-NEXT:  .LBB11_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v5, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v2, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -1745,37 +1860,70 @@ define float @bitcast_v2bf16_to_f32(<2 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v2bf16_to_f32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v1
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB17_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_bfe_u32 v2, v1, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v3, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v4, 0x400000, v1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_or_b32_e32 v5, 0x400000, v0
-; GFX11-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v0, v0, v1, 0x7060302
-; GFX11-NEXT:  .LBB17_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_f32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v1
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB17_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v2, v1, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v1, v0
+; GFX11-TRUE16-NEXT:  .LBB17_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_f32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v1
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB17_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v2, v1, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v1, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB17_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -2026,37 +2174,64 @@ define <4 x i8> @bitcast_f32_to_v4i8(float %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_f32_to_v4i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB20_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB20_4
-; GFX11-NEXT:  .LBB20_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB20_3: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB20_2
-; GFX11-NEXT:  .LBB20_4: ; %cmp.true
-; GFX11-NEXT:    v_add_f32_e32 v0, 1.0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_f32_to_v4i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 1.0, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-TRUE16-NEXT:  ; %bb.4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_f32_to_v4i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB20_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB20_4
+; GFX11-FAKE16-NEXT:  .LBB20_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB20_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB20_2
+; GFX11-FAKE16-NEXT:  .LBB20_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, 1.0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -2199,59 +2374,113 @@ define float @bitcast_v4i8_to_f32(<4 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v4i8_to_f32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mov_b32_e32 v5, v0
-; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v3, 8, v3
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    ; implicit-def: $vgpr0
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v4
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB21_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB21_4
-; GFX11-NEXT:  .LBB21_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB21_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v5
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB21_2
-; GFX11-NEXT:  .LBB21_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v5, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v2, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v3, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v4i8_to_f32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB21_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB21_4
+; GFX11-TRUE16-NEXT:  .LBB21_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB21_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v0.h, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB21_2
+; GFX11-TRUE16-NEXT:  .LBB21_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v2.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v2.l, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v1.h, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v4i8_to_f32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB21_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB21_4
+; GFX11-FAKE16-NEXT:  .LBB21_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB21_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB21_2
+; GFX11-FAKE16-NEXT:  .LBB21_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v5, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v2, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -2618,37 +2847,72 @@ define <2 x i16> @bitcast_v2bf16_to_v2i16(<2 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v2bf16_to_v2i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v1
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB25_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_bfe_u32 v2, v1, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v3, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v4, 0x400000, v1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_or_b32_e32 v5, 0x400000, v0
-; GFX11-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v0, v0, v1, 0x7060302
-; GFX11-NEXT:  .LBB25_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_v2i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v1
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB25_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v2, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT:  .LBB25_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_v2i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v1
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB25_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v2, v1, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v1, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB25_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -2947,37 +3211,64 @@ define <4 x i8> @bitcast_v2i16_to_v4i8(<2 x i16> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v2i16_to_v4i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB28_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB28_4
-; GFX11-NEXT:  .LBB28_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB28_3: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB28_2
-; GFX11-NEXT:  .LBB28_4: ; %cmp.true
-; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v2i16_to_v4i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-TRUE16-NEXT:  ; %bb.4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v2i16_to_v4i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB28_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB28_4
+; GFX11-FAKE16-NEXT:  .LBB28_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB28_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB28_2
+; GFX11-FAKE16-NEXT:  .LBB28_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -3123,59 +3414,113 @@ define <2 x i16> @bitcast_v4i8_to_v2i16(<4 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v4i8_to_v2i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mov_b32_e32 v5, v0
-; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v3, 8, v3
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    ; implicit-def: $vgpr0
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v4
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB29_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB29_4
-; GFX11-NEXT:  .LBB29_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB29_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v5
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB29_2
-; GFX11-NEXT:  .LBB29_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v5, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v2, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v3, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v4i8_to_v2i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB29_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB29_4
+; GFX11-TRUE16-NEXT:  .LBB29_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB29_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v0.h, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB29_2
+; GFX11-TRUE16-NEXT:  .LBB29_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v2.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v2.l, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v1.h, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v4i8_to_v2i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB29_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB29_4
+; GFX11-FAKE16-NEXT:  .LBB29_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB29_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB29_2
+; GFX11-FAKE16-NEXT:  .LBB29_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v5, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v2, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -3390,37 +3735,70 @@ define <2 x half> @bitcast_v2bf16_to_v2f16(<2 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v2bf16_to_v2f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v1
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB31_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_bfe_u32 v2, v1, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v3, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v4, 0x400000, v1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_or_b32_e32 v5, 0x400000, v0
-; GFX11-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v0, v0, v1, 0x7060302
-; GFX11-NEXT:  .LBB31_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_v2f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v1
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB31_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v2, v1, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v1, v0
+; GFX11-TRUE16-NEXT:  .LBB31_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_v2f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v1
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB31_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v2, v1, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v1, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB31_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -3726,37 +4104,64 @@ define <4 x i8> @bitcast_v2f16_to_v4i8(<2 x half> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v2f16_to_v4i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB34_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB34_4
-; GFX11-NEXT:  .LBB34_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB34_3: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB34_2
-; GFX11-NEXT:  .LBB34_4: ; %cmp.true
-; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v2f16_to_v4i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-TRUE16-NEXT:  ; %bb.4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v2f16_to_v4i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB34_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB34_4
+; GFX11-FAKE16-NEXT:  .LBB34_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB34_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB34_2
+; GFX11-FAKE16-NEXT:  .LBB34_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -3898,59 +4303,113 @@ define <2 x half> @bitcast_v4i8_to_v2f16(<4 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v4i8_to_v2f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mov_b32_e32 v5, v0
-; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v3, 8, v3
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    ; implicit-def: $vgpr0
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v4
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB35_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB35_4
-; GFX11-NEXT:  .LBB35_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB35_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v5
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB35_2
-; GFX11-NEXT:  .LBB35_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v5, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v2, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v3, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v4i8_to_v2f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB35_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB35_4
+; GFX11-TRUE16-NEXT:  .LBB35_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB35_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v0.h, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB35_2
+; GFX11-TRUE16-NEXT:  .LBB35_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v2.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v2.l, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v1.h, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v4i8_to_v2f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB35_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB35_4
+; GFX11-FAKE16-NEXT:  .LBB35_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB35_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB35_2
+; GFX11-FAKE16-NEXT:  .LBB35_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v5, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v2, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -4063,37 +4522,70 @@ define <1 x i32> @bitcast_v2bf16_to_v1i32(<2 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v2bf16_to_v1i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v1
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB36_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_bfe_u32 v2, v1, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v3, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v4, 0x400000, v1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_or_b32_e32 v5, 0x400000, v0
-; GFX11-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v0, v0, v1, 0x7060302
-; GFX11-NEXT:  .LBB36_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_v1i32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v1
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB36_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v2, v1, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v1, v0
+; GFX11-TRUE16-NEXT:  .LBB36_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_v1i32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v1
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB36_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v2, v1, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v1, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB36_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -4332,54 +4824,104 @@ define <4 x i8> @bitcast_v2bf16_to_v4i8(<2 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v2bf16_to_v4i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB38_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB38_4
-; GFX11-NEXT:  .LBB38_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB38_3: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB38_2
-; GFX11-NEXT:  .LBB38_4: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_bfe_u32 v2, v1, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v3, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v4, 0x400000, v1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_or_b32_e32 v5, 0x400000, v0
-; GFX11-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v4, v0, v1, 0x7060302
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v0, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v4
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_v4i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v4, v0
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v4.h
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB38_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v4
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v2, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v2, v2, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v3, v5, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v1
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB38_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_v4i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB38_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB38_4
+; GFX11-FAKE16-NEXT:  .LBB38_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB38_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB38_2
+; GFX11-FAKE16-NEXT:  .LBB38_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v2, v1, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v0, v1, 0x7060302
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v4
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -4521,59 +5063,113 @@ define <2 x bfloat> @bitcast_v4i8_to_v2bf16(<4 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v4i8_to_v2bf16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mov_b32_e32 v5, v0
-; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v3, 8, v3
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    ; implicit-def: $vgpr0
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v4
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB39_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB39_4
-; GFX11-NEXT:  .LBB39_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB39_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v5
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB39_2
-; GFX11-NEXT:  .LBB39_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v5, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v2, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v3, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v4i8_to_v2bf16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB39_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB39_4
+; GFX11-TRUE16-NEXT:  .LBB39_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB39_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v0.h, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB39_2
+; GFX11-TRUE16-NEXT:  .LBB39_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v2.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v2.l, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v1.h, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v4i8_to_v2bf16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB39_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB39_4
+; GFX11-FAKE16-NEXT:  .LBB39_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB39_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB39_2
+; GFX11-FAKE16-NEXT:  .LBB39_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v5, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v2, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -4682,37 +5278,64 @@ define <4 x i8> @bitcast_v1i32_to_v4i8(<1 x i32> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v1i32_to_v4i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB40_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB40_4
-; GFX11-NEXT:  .LBB40_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB40_3: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB40_2
-; GFX11-NEXT:  .LBB40_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v1i32_to_v4i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 3, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-TRUE16-NEXT:  ; %bb.4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v1i32_to_v4i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB40_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB40_4
+; GFX11-FAKE16-NEXT:  .LBB40_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB40_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB40_2
+; GFX11-FAKE16-NEXT:  .LBB40_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v0, 3, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -4855,59 +5478,113 @@ define <1 x i32> @bitcast_v4i8_to_v1i32(<4 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v4i8_to_v1i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mov_b32_e32 v5, v0
-; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v3, 8, v3
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    ; implicit-def: $vgpr0
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v4
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB41_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB41_4
-; GFX11-NEXT:  .LBB41_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB41_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v5
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB41_2
-; GFX11-NEXT:  .LBB41_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v5, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v2, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v3, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v4i8_to_v1i32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB41_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB41_4
+; GFX11-TRUE16-NEXT:  .LBB41_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB41_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v0.h, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB41_2
+; GFX11-TRUE16-NEXT:  .LBB41_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v2.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v2.l, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v1.h, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v4i8_to_v1i32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v4
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB41_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB41_4
+; GFX11-FAKE16-NEXT:  .LBB41_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB41_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB41_2
+; GFX11-FAKE16-NEXT:  .LBB41_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v5, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v2, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
index 9bb360f2e3b09..b52128024fbc3 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
@@ -3,7 +3,8 @@
 ; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define <3 x half> @bitcast_v3bf16_to_v3f16(<3 x bfloat> %a, i32 %b) {
 ; GCN-LABEL: bitcast_v3bf16_to_v3f16:
@@ -134,47 +135,92 @@ define <3 x half> @bitcast_v3bf16_to_v3f16(<3 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v3bf16_to_v3f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v2
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB0_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v2, 16, v0
-; GFX11-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v4, v1, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v6, 0x400000, v1
-; GFX11-NEXT:    v_bfe_u32 v3, v2, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v7, 0x400000, v2
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_add3_u32 v4, v4, v1, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    v_add3_u32 v3, v3, v2, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v3, v7, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v5, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_add3_u32 v5, v5, v0, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v5, v8, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_perm_b32 v0, v0, v2, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v4, v6, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_alignbit_b32 v1, 0x7fc0, v1, 16
-; GFX11-NEXT:  .LBB0_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v3bf16_to_v3f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v2
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB0_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v4, v4, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v3, v3, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v2, v3, v7 :: v_dual_mov_b32 v3, 0x7fc0
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v1, v4, v5 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v3.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v2, v0
+; GFX11-TRUE16-NEXT:  .LBB0_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v3bf16_to_v3f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v2
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB0_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v4, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_add3_u32 v4, v4, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v3, v3, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v3, v7, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v5, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v5, v5, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v5, v8, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v2, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v4, v6, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v1, 0x7fc0, v1, 16
+; GFX11-FAKE16-NEXT:  .LBB0_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -426,47 +472,95 @@ define <3 x i16> @bitcast_v3bf16_to_v3i16(<3 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v3bf16_to_v3i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v2
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB2_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v2, 16, v0
-; GFX11-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v4, v1, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v6, 0x400000, v1
-; GFX11-NEXT:    v_bfe_u32 v3, v2, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v7, 0x400000, v2
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_add3_u32 v4, v4, v1, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    v_add3_u32 v3, v3, v2, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v3, v7, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v5, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_add3_u32 v5, v5, v0, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v5, v8, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_perm_b32 v0, v0, v2, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v4, v6, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_alignbit_b32 v1, 0x7fc0, v1, 16
-; GFX11-NEXT:  .LBB2_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v3bf16_to_v3i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v2
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB2_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v5, v2, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v4, v4, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v5, v5, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v5, v8, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v4, v6, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v0, v0, 16, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v1, 0x7fc0, 16, v1
+; GFX11-TRUE16-NEXT:  .LBB2_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v3bf16_to_v3i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v2
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB2_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v4, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_add3_u32 v4, v4, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v3, v3, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v3, v7, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v5, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v5, v5, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v5, v8, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v2, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v4, v6, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v1, 0x7fc0, v1, 16
+; GFX11-FAKE16-NEXT:  .LBB2_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
index 0d1008082f586..c48a8459fdc3c 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
@@ -3,7 +3,8 @@
 ; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define <16 x float> @bitcast_v16i32_to_v16f32(<16 x i32> %a, i32 %b) {
 ; GCN-LABEL: bitcast_v16i32_to_v16f32:
@@ -3069,295 +3070,581 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v32bf16_to_v16i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v16
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB11_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
-; GFX11-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v21, v17, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v18, v16, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v19, 0x400000, v16
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_bfe_u32 v23, v14, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-NEXT:    v_add3_u32 v21, v21, v17, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v18, v18, v16, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v16, v18, v19, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v19, v23, v14, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-NEXT:    v_or_b32_e32 v18, 0x400000, v17
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-NEXT:    v_bfe_u32 v20, v15, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v15
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v20, v20, v15, 0x7fff
-; GFX11-NEXT:    v_dual_cndmask_b32 v15, v20, v22 :: v_dual_lshlrev_b32 v20, 16, v13
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v15, v15, v16, 0x7060302
-; GFX11-NEXT:    v_dual_cndmask_b32 v17, v21, v18 :: v_dual_add_f32 v18, 0x40c00000, v20
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v16, v18, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v18
-; GFX11-NEXT:    v_add3_u32 v16, v16, v18, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v14
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_cndmask_b32 v14, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v12
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_perm_b32 v14, v14, v17, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v17, v13, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_cndmask_b32 v16, v16, v20
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-NEXT:    v_add3_u32 v17, v17, v13, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v22, v19, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v19
-; GFX11-NEXT:    v_cndmask_b32_e32 v13, v17, v21, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v11
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v17, v22, v19, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-NEXT:    v_perm_b32 v13, v13, v16, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v19, 0x40c00000, v21
-; GFX11-NEXT:    v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v16, v19, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v19
-; GFX11-NEXT:    v_add3_u32 v16, v16, v19, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-NEXT:    v_bfe_u32 v18, v12, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v12
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v18, v18, v12, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v12, v18, v22, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v12, v12, v17, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v17, v11, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-NEXT:    v_add3_u32 v17, v17, v11, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v22, v18, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v19, v10, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v16, v16, v20, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v19, v19, v10, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v11, v17, v21, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v17, v22, v18, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v10
-; GFX11-NEXT:    v_perm_b32 v11, v11, v16, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    v_dual_cndmask_b32 v10, v19, v22 :: v_dual_lshlrev_b32 v21, 16, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_lshlrev_b32 v19, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-NEXT:    v_perm_b32 v10, v10, v17, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v16, v18, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v18
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_add_f32 v8, 0x40c00000, v8
-; GFX11-NEXT:    v_add3_u32 v16, v16, v18, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v22, v19, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v18, v8, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v9, 0x40c00000, v9
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v19
-; GFX11-NEXT:    v_add3_u32 v18, v18, v8, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v17, v9, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v9
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    v_add3_u32 v17, v17, v9, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v9, v17, v21, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v17, v22, v19, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v8
-; GFX11-NEXT:    v_perm_b32 v9, v9, v16, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-NEXT:    v_cndmask_b32_e32 v8, v18, v22, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v8, v8, v17, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_add_f32 v19, 0x40c00000, v21
-; GFX11-NEXT:    v_bfe_u32 v22, v18, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v16, v19, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v19
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-NEXT:    v_add3_u32 v16, v16, v19, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-NEXT:    v_bfe_u32 v19, v6, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v7, 0x40c00000, v7
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v18
-; GFX11-NEXT:    v_add3_u32 v19, v19, v6, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v17, v7, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v7
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    v_add3_u32 v17, v17, v7, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v7, v17, v21, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v17, v22, v18, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v5
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v6
-; GFX11-NEXT:    v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_cndmask_b32 v17, v17, v20
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v20, v18, 16, 1
-; GFX11-NEXT:    v_dual_cndmask_b32 v6, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT:    v_perm_b32 v7, v7, v16, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v6, v6, v17, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v17, 0x40c00000, v19
-; GFX11-NEXT:    v_add3_u32 v19, v20, v18, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v18
-; GFX11-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-NEXT:    v_bfe_u32 v22, v17, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v18, v19, v20, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v19, 0x400000, v17
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v16, v5, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v5
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    v_add3_u32 v16, v16, v5, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v5, v16, v21, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v16, v22, v17, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-NEXT:    v_perm_b32 v5, v5, v18, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v18, v4, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v16, v16, v19, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v19, 0x400000, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    v_add3_u32 v18, v18, v4, 0x7fff
-; GFX11-NEXT:    v_dual_add_f32 v17, 0x40c00000, v20 :: v_dual_lshlrev_b32 v20, 16, v2
-; GFX11-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v4, v18, v19, vcc_lo
-; GFX11-NEXT:    v_bfe_u32 v21, v17, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v18, 0x40c00000, v20
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v17
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-NEXT:    v_perm_b32 v4, v4, v16, 0x7060302
-; GFX11-NEXT:    v_add3_u32 v19, v21, v17, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v21, v3, 16, 1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT:    v_bfe_u32 v22, v18, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v23, 0x400000, v18
-; GFX11-NEXT:    v_cndmask_b32_e32 v17, v19, v20, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v19, v21, v3, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v3
-; GFX11-NEXT:    v_add3_u32 v21, v22, v18, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v1
-; GFX11-NEXT:    v_bfe_u32 v24, v2, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v19, v20, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v19, 0x40c00000, v22
-; GFX11-NEXT:    v_add3_u32 v20, v24, v2, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v3, v3, v17, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v18, v21, v23, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v2
-; GFX11-NEXT:    v_bfe_u32 v22, v19, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_dual_cndmask_b32 v2, v20, v21 :: v_dual_lshlrev_b32 v23, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_add3_u32 v21, v22, v19, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v19
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    v_add_f32_e32 v20, 0x40c00000, v23
-; GFX11-NEXT:    v_perm_b32 v2, v2, v18, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v19, v21, v22 :: v_dual_add_f32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_bfe_u32 v24, v20, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v25, 0x400000, v20
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v21, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v26, 0x400000, v0
-; GFX11-NEXT:    v_add3_u32 v24, v24, v20, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v21, v21, v0, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v23, v1, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_add3_u32 v22, v23, v1, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v23, 0x400000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v22, v23, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-NEXT:    v_perm_b32 v1, v1, v19, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v20, v24, v25, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v21, v26, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v0, v0, v20, 0x7060302
-; GFX11-NEXT:  .LBB11_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v32bf16_to_v16i32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v16
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB11_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff0000, v15
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v15, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v15
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v20, v20, v15, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v15, v20, v22 :: v_dual_add_f32 v16, 0x40c00000, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v15.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v16, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v16
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v19, v16, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v16, v19, v21 :: v_dual_and_b32 v17, 0xffff0000, v14
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_lshlrev_b32 v14, 16, v14
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v15, 0xffff, v15, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v23, v17, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, 0x400000, v17
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v25, v14, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v26, 0x400000, v14
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT:    v_add3_u32 v20, v23, v17, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v22, v25, v14, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v14, v22, v26, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v17, v20, v24 :: v_dual_and_b32 v18, 0xffff0000, v13
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_lshlrev_b32 v13, 16, v13
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v14.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v18, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v18
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v13, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, 0x400000, v13
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v14, 0xffff, v14, v17
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v19, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v16, v16, v13, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v13, v16, v20 :: v_dual_and_b32 v20, 0xffff0000, v11
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff0000, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v16, v17, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_lshlrev_b32 v12, 16, v12
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, 0x400000, v20
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v13, 0xffff, v13, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v19
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v18, v12, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v12
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v18, v18, v12, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v12, v18, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v21, v11, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v18, v20, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v21, v11, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v17, v17, v22, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v11
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT:    v_add3_u32 v18, v18, v20, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff0000, v10
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v11, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v22
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v12, 0xffff, v12, v17
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v18, v18, v23, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v19
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v11, 0xffff, v11, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v18, 0xffff0000, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v20, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_lshlrev_b32 v10, 16, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v18
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v10, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, 0x400000, v10
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v16, v16, v10, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v10, v16, v20, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v9, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff0000, v8
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v16, v17, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v18, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v19, v9, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v9
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v9, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v20, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, 0x400000, v20
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v17, v17, v22 :: v_dual_and_b32 v22, 0xffff0000, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT:    v_add3_u32 v18, v19, v20, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v9, 0xffff, v9, v17
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v7, 0x40c00000, v7 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v21, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v21, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v22
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v10, 0xffff, v10, v16
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v18, v18, v23 :: v_dual_and_b32 v23, 0xffff0000, v4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v19, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v16, v16, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v19
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v8, 0xffff, v8, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v18, 0xffff0000, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v20, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v7, v16, v20
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff0000, v5
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v6, 16, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v18
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v16, v17, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v18, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v19, v6, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v6
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v20, 0x40c00000, v20 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v20, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v21, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v7, 0xffff, v7, v16
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v18, v19, v20, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v21, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v17, v17, v22, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v20
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v6, 0xffff, v6, v17
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v4, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v18, v18, v22, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v19
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v5, 0xffff, v5, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v18, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_add3_u32 v16, v16, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v17, v20, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_add_f32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v16, v16, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v18, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v18
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v20, v20, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v23, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v4.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v20, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    v_add3_u32 v18, v23, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, 0x400000, v19
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v21, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v17, v17, v22 :: v_dual_and_b32 v22, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v21, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v4, 0xffff, v4, v16
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v21, 0x40c00000, v22 :: v_dual_cndmask_b32 v18, v18, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v0
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, 0x400000, v21
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v3, 0xffff, v3, v17
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v19, v20, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v22
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v22, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v25, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v21, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v23, v20, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v22, v22, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v27, 0x400000, v20
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v19, v21, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v23, v23, v20, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v22, v25, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v26, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v25, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v20, v23, v27, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT:    v_add3_u32 v22, v26, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v2, v18
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.l, v20.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v19, v19, v24, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v19
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v22, v25, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v20, v0
+; GFX11-TRUE16-NEXT:  .LBB11_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v32bf16_to_v16i32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v16
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB11_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v17, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v18, v16, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, 0x400000, v16
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v23, v14, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v18, v18, v16, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v18, v19, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v23, v14, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, 0x400000, v17
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v20, v15, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v15
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v20, v20, v15, 0x7fff
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v15, v20, v22 :: v_dual_lshlrev_b32 v20, 16, v13
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v15, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v17, v21, v18 :: v_dual_add_f32 v18, 0x40c00000, v20
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v14
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v14, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v12
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v14, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v17, v13, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_cndmask_b32 v16, v16, v20
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v17, v13, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v19, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v19
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v13, v17, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v22, v19, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v13, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v21
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v17, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v19, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v19
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v19, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v18, v12, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v12
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v18, v18, v12, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v18, v22, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v12, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v17, v11, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v17, v11, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v19, v10, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v16, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v19, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v17, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v22, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v10
+; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v11, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v17, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v19, v22 :: v_dual_lshlrev_b32 v21, 16, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_lshlrev_b32 v19, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v10, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v19, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v18, v8, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v19
+; GFX11-FAKE16-NEXT:    v_add3_u32 v18, v18, v8, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v17, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v17, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v17, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v22, v19, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v8
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v9, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v17, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v18, v22, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v8, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_add_f32 v19, 0x40c00000, v21
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v18, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v19, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v19
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v19, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v19, v6, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v7, 0x40c00000, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v19, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v17, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v17, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v17, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v22, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v5
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_cndmask_b32 v17, v17, v20
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v20, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v6, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v6, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v17, 0x40c00000, v19
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v20, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v17, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v19, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, 0x400000, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v5
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v16, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v22, v17, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v5, v18, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v18, v4, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v16, v19, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    v_add3_u32 v18, v18, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v17, 0x40c00000, v20 :: v_dual_lshlrev_b32 v20, 16, v2
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v18, v19, vcc_lo
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v17, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v17
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v4, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v19, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v21, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v22, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v24, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v19, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v22
+; GFX11-FAKE16-NEXT:    v_add3_u32 v20, v24, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v3, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v21, v23, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v19, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v20, v21 :: v_dual_lshlrev_b32 v23, 16, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v22, v19, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v19
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v23
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v18, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v19, v21, v22 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v24, v20, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, 0x400000, v20
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v24, v24, v20, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v21, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v23, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v22, v23, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, 0x400000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v22, v23, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v19, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v20, v24, v25, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v21, v26, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v20, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB11_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -4430,332 +4717,614 @@ define <64 x i8> @bitcast_v16i32_to_v64i8(<16 x i32> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v16i32_to_v64i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v17
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr67
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB12_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
-; GFX11-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
-; GFX11-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 8, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 8, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 24, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 8, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 16, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 8, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v49, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v51, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v52, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v53, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v54, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v64, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v66, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v67, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v68, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v69, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v71, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v80, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v81, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v82, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v83, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v84, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v85, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v86, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v87, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v96, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
-; GFX11-NEXT:  .LBB12_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB12_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u32_e32 v16, 3, v16
-; GFX11-NEXT:    v_add_nc_u32_e32 v15, 3, v15
-; GFX11-NEXT:    v_add_nc_u32_e32 v14, 3, v14
-; GFX11-NEXT:    v_add_nc_u32_e32 v13, 3, v13
-; GFX11-NEXT:    v_add_nc_u32_e32 v12, 3, v12
-; GFX11-NEXT:    v_add_nc_u32_e32 v11, 3, v11
-; GFX11-NEXT:    v_add_nc_u32_e32 v10, 3, v10
-; GFX11-NEXT:    v_add_nc_u32_e32 v9, 3, v9
-; GFX11-NEXT:    v_add_nc_u32_e32 v8, 3, v8
-; GFX11-NEXT:    v_add_nc_u32_e32 v7, 3, v7
-; GFX11-NEXT:    v_add_nc_u32_e32 v6, 3, v6
-; GFX11-NEXT:    v_add_nc_u32_e32 v5, 3, v5
-; GFX11-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
-; GFX11-NEXT:    v_add_nc_u32_e32 v4, 3, v4
-; GFX11-NEXT:    v_add_nc_u32_e32 v3, 3, v3
-; GFX11-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
-; GFX11-NEXT:    v_add_nc_u32_e32 v2, 3, v2
-; GFX11-NEXT:    v_add_nc_u32_e32 v1, 3, v1
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
-; GFX11-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 8, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 8, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 24, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 8, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 16, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 8, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v49, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v51, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v52, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v53, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v54, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v64, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v66, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v67, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v68, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v69, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v71, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v80, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v81, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v82, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v83, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v84, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v85, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v86, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v87, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v96, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
-; GFX11-NEXT:  .LBB12_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v25
-; GFX11-NEXT:    v_and_b32_e32 v96, 0xff, v96
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v24
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v86, 0xff, v86
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v25
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v87
-; GFX11-NEXT:    v_or_b32_e32 v24, v96, v24
-; GFX11-NEXT:    v_lshlrev_b16 v85, 8, v85
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v25
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT:    v_or_b32_e32 v25, v86, v85
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_lshlrev_b16 v84, 8, v84
-; GFX11-NEXT:    v_and_b32_e32 v83, 0xff, v83
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v24
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v82
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v80, 8, v80
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_lshlrev_b16 v71, 8, v71
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v24
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v81
-; GFX11-NEXT:    v_and_b32_e32 v70, 0xff, v70
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v22
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v84
-; GFX11-NEXT:    v_or_b32_e32 v23, v83, v23
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v80
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v71
-; GFX11-NEXT:    v_or_b32_e32 v22, v70, v22
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v24
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v23
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v25
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v22
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v66
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v65
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v21
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v64
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v55
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v54
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v53
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v22
-; GFX11-NEXT:    v_or_b32_e32 v21, v23, v21
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v24
-; GFX11-NEXT:    v_or_b32_e32 v22, v25, v54
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v52
-; GFX11-NEXT:    v_lshlrev_b16 v20, 8, v20
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v51
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v50
-; GFX11-NEXT:    v_lshlrev_b16 v49, 8, v49
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_lshlrev_b16 v48, 8, v48
-; GFX11-NEXT:    v_and_b32_e32 v39, 0xff, v39
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v19
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v53
-; GFX11-NEXT:    v_or_b32_e32 v20, v23, v20
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v24
-; GFX11-NEXT:    v_or_b32_e32 v23, v25, v49
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v48
-; GFX11-NEXT:    v_or_b32_e32 v19, v39, v19
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v21
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v22
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v20
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v23
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v19
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v38
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v37
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v36
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v35
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v34
-; GFX11-NEXT:    v_lshlrev_b16 v18, 8, v18
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v33
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_lshlrev_b16 v69, 8, v69
-; GFX11-NEXT:    v_and_b32_e32 v68, 0xff, v68
-; GFX11-NEXT:    v_lshlrev_b16 v67, 8, v67
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v19
-; GFX11-NEXT:    v_or_b32_e32 v19, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v22
-; GFX11-NEXT:    v_or_b32_e32 v18, v23, v18
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v24
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v32
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v31
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v30
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v29
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v17
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v28
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v27
-; GFX11-NEXT:    v_lshlrev_b16 v26, 8, v26
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v69
-; GFX11-NEXT:    v_or_b32_e32 v67, v68, v67
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v22
-; GFX11-NEXT:    v_or_b32_e32 v17, v23, v17
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v24
-; GFX11-NEXT:    v_or_b32_e32 v21, v25, v26
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v67, 16, v67
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v67
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v19
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v18
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v20
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v17
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v21
-; GFX11-NEXT:    s_clause 0x3
-; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off
-; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
-; GFX11-NEXT:    scratch_store_b128 v0, v[9:12], off offset:32
-; GFX11-NEXT:    scratch_store_b128 v0, v[13:16], off offset:48
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v16i32_to_v64i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v17
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB12_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 24, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v33, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v35, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v37, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v38, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v48, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v49, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v50, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v51, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v52, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v53, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v54, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v55, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v64, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB12_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB12_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v16, 3, v16
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v15, 3, v15
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v14, 3, v14
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v13, 3, v13
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v12, 3, v12
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v11, 3, v11
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v10, 3, v10
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v9, 3, v9
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, 3, v8
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v7, 3, v7
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, 3, v6
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v5, 3, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v4, 3, v4
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 3, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 3, v2
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v1, 3, v1
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 24, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v33, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v35, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v37, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v38, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v48, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v49, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v50, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v51, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v52, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v53, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v54, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v55, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v64, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB12_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v17.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v64.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v1.h, v18.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v55.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v54.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.h, 8, v53.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v17.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v2.h, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v19.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v21.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v53, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v52.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v24
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v3.h, v20.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v25.l, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v54, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v51.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v5.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v22.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v48.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v25
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.l, 8, v37.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v17.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v50.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v49.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v49, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v50, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v54, v24
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v25, v22
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v39.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v7.h, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v20.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v38.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v19.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.l, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v10.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v35.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v53, v23
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v8.h, v20.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v36.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v11.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v34.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v21, v19
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v33.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.l, 8, v31.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v30.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v32.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.l, 8, v18.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v19.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v19.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v35, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v24, v22
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v20, v34
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v12.h, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v13.h, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v14.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v29.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v15.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.l, 0xff, v16.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v16.l, 0xff, v16.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v26.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v14.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v15.l, v15.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v16.l, v16.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v51, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v25, v23
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v23, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v14
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v49, v50
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v51, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v35, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v21, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v22, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v19, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v23, v24
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, v25, v16
+; GFX11-TRUE16-NEXT:    s_clause 0x3
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[9:12], off offset:32
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[13:16], off offset:48
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v16i32_to_v64i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB12_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 24, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 16, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 16, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v49, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v50, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v51, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v52, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v53, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v54, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v55, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v64, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v65, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v66, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v67, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v68, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v69, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v70, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v81, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v82, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v85, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v86, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB12_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB12_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v16, 3, v16
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v15, 3, v15
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v14, 3, v14
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v13, 3, v13
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v12, 3, v12
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v11, 3, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v10, 3, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v9, 3, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, 3, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v7, 3, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, 3, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v5, 3, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, 3, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, 3, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, 3, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v1, 3, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 24, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 16, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 16, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v49, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v50, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v51, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v52, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v53, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v54, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v55, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v64, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v65, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v66, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v67, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v68, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v69, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v70, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v81, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v82, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v85, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v86, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB12_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v96, 0xff, v96
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v86, 0xff, v86
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v87
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v96, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v85, 8, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v86, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v84, 8, v84
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v83, 0xff, v83
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v82
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v80, 8, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v71, 8, v71
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v81
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v70, 0xff, v70
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v84
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v83, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v80
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v71
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v70, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v66
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v65
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v64
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v55
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v53, 8, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v23, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v25, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v52
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v51
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v50
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v49, 8, v49
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v48, 8, v48
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v39, 0xff, v39
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v23, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v25, v49
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v48
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v39, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v38
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v37
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v18, 8, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v69, 8, v69
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v68, 0xff, v68
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v67, 8, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v23, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v29
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v26, 8, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v69
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v67, v68, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v23, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v25, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v67, 16, v67
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v21
+; GFX11-FAKE16-NEXT:    s_clause 0x3
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[9:12], off offset:32
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[13:16], off offset:48
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -6282,471 +6851,950 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v64i8_to_v16i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v38, v14 :: v_dual_mov_b32 v37, v12
-; GFX11-NEXT:    v_dual_mov_b32 v36, v10 :: v_dual_mov_b32 v35, v8
-; GFX11-NEXT:    v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v4
-; GFX11-NEXT:    v_dual_mov_b32 v32, v2 :: v_dual_mov_b32 v31, v0
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v0, off, s32 offset:128
-; GFX11-NEXT:    scratch_load_u16 v39, off, s32 offset:124
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32 offset:120
-; GFX11-NEXT:    scratch_load_u16 v48, off, s32 offset:116
-; GFX11-NEXT:    scratch_load_u16 v4, off, s32 offset:112
-; GFX11-NEXT:    scratch_load_u16 v49, off, s32 offset:108
-; GFX11-NEXT:    scratch_load_u16 v6, off, s32 offset:104
-; GFX11-NEXT:    scratch_load_u16 v50, off, s32 offset:100
-; GFX11-NEXT:    scratch_load_u16 v8, off, s32 offset:96
-; GFX11-NEXT:    scratch_load_u16 v51, off, s32 offset:92
-; GFX11-NEXT:    scratch_load_u16 v10, off, s32 offset:88
-; GFX11-NEXT:    scratch_load_b32 v12, off, s32 offset:132
-; GFX11-NEXT:    scratch_load_u16 v14, off, s32
-; GFX11-NEXT:    scratch_load_u16 v65, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_u16 v66, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_u16 v67, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_u16 v83, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_u16 v84, off, s32 offset:40
-; GFX11-NEXT:    scratch_load_u16 v85, off, s32 offset:48
-; GFX11-NEXT:    scratch_load_u16 v128, off, s32 offset:56
-; GFX11-NEXT:    scratch_load_u16 v129, off, s32 offset:64
-; GFX11-NEXT:    scratch_load_u16 v130, off, s32 offset:72
-; GFX11-NEXT:    scratch_load_u16 v131, off, s32 offset:80
-; GFX11-NEXT:    scratch_load_u16 v52, off, s32 offset:84
-; GFX11-NEXT:    scratch_load_u16 v53, off, s32 offset:76
-; GFX11-NEXT:    scratch_load_u16 v54, off, s32 offset:68
-; GFX11-NEXT:    scratch_load_u16 v55, off, s32 offset:60
-; GFX11-NEXT:    scratch_load_u16 v64, off, s32 offset:52
-; GFX11-NEXT:    scratch_load_u16 v68, off, s32 offset:44
-; GFX11-NEXT:    scratch_load_u16 v69, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_u16 v70, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_u16 v71, off, s32 offset:20
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_u16 v80, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_u16 v86, off, s32 offset:4
-; GFX11-NEXT:    v_lshlrev_b16 v118, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v119, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v117, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v114, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v115, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v116, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v113, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v100, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v101, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v102, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v103, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v112, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v87, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v96, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v97, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(33)
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(31)
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(29)
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v4
-; GFX11-NEXT:    s_waitcnt vmcnt(27)
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v6
-; GFX11-NEXT:    s_waitcnt vmcnt(25)
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v8
-; GFX11-NEXT:    s_waitcnt vmcnt(22)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v12
-; GFX11-NEXT:    s_waitcnt vmcnt(21)
-; GFX11-NEXT:    v_lshlrev_b16 v98, 8, v14
-; GFX11-NEXT:    s_waitcnt vmcnt(20)
-; GFX11-NEXT:    v_lshlrev_b16 v99, 8, v65
-; GFX11-NEXT:    s_waitcnt vmcnt(19)
-; GFX11-NEXT:    v_lshlrev_b16 v81, 8, v66
-; GFX11-NEXT:    s_waitcnt vmcnt(18)
-; GFX11-NEXT:    v_lshlrev_b16 v82, 8, v67
-; GFX11-NEXT:    s_waitcnt vmcnt(17)
-; GFX11-NEXT:    v_lshlrev_b16 v83, 8, v83
-; GFX11-NEXT:    s_waitcnt vmcnt(16)
-; GFX11-NEXT:    v_lshlrev_b16 v84, 8, v84
-; GFX11-NEXT:    s_waitcnt vmcnt(15)
-; GFX11-NEXT:    v_lshlrev_b16 v85, 8, v85
-; GFX11-NEXT:    s_waitcnt vmcnt(14)
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v128
-; GFX11-NEXT:    s_waitcnt vmcnt(13)
-; GFX11-NEXT:    v_lshlrev_b16 v29, 8, v129
-; GFX11-NEXT:    s_waitcnt vmcnt(12)
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v130
-; GFX11-NEXT:    s_waitcnt vmcnt(11)
-; GFX11-NEXT:    v_lshlrev_b16 v66, 8, v131
-; GFX11-NEXT:    v_lshlrev_b16 v67, 8, v10
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB13_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB13_4
-; GFX11-NEXT:  .LBB13_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB13_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v31
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v37
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v34
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v118
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v119
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v35
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v36
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v18
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v22
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v117
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v6, v113
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v114
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v115
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v116
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v101
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v1
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v38
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v102
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v103
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v112
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v100
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v11
-; GFX11-NEXT:    v_or_b32_e32 v4, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v5, v9, v10
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v24
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v26
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v30
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v86
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v80
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v71
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v70
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v69
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v68
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v87
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v96
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v97
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v98
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v99
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v81
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v82
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v83
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v84
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v85
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v7
-; GFX11-NEXT:    v_or_b32_e32 v7, v8, v9
-; GFX11-NEXT:    v_or_b32_e32 v8, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v9, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v10, v14, v15
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v64
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v55
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v54
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v53
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v52
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v51
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v50
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v49
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v48
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v39
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v27
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v29
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v65
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v66
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v67
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v17, v18, v19
-; GFX11-NEXT:    v_or_b32_e32 v18, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v19, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v20, v24, v25
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff, v19
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v12, v13, v14
-; GFX11-NEXT:    v_or_b32_e32 v13, v15, v16
-; GFX11-NEXT:    v_or_b32_e32 v14, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v15, v19, v20
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr118
-; GFX11-NEXT:    ; implicit-def: $vgpr119
-; GFX11-NEXT:    ; implicit-def: $vgpr117
-; GFX11-NEXT:    ; implicit-def: $vgpr114
-; GFX11-NEXT:    ; implicit-def: $vgpr115
-; GFX11-NEXT:    ; implicit-def: $vgpr116
-; GFX11-NEXT:    ; implicit-def: $vgpr113
-; GFX11-NEXT:    ; implicit-def: $vgpr100
-; GFX11-NEXT:    ; implicit-def: $vgpr101
-; GFX11-NEXT:    ; implicit-def: $vgpr102
-; GFX11-NEXT:    ; implicit-def: $vgpr103
-; GFX11-NEXT:    ; implicit-def: $vgpr112
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr97
-; GFX11-NEXT:    ; implicit-def: $vgpr98
-; GFX11-NEXT:    ; implicit-def: $vgpr99
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr67
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB13_2
-; GFX11-NEXT:  .LBB13_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v31, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v32, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v33, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v34, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v35, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v5, v36, 3
-; GFX11-NEXT:    v_add_nc_u16 v6, v37, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_or_b32_e32 v0, v118, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v119, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_or_b32_e32 v2, v117, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v114, v3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_or_b32_e32 v4, v115, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v116, v5
-; GFX11-NEXT:    v_or_b32_e32 v6, v113, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, v16, 3
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v5
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v6, v38, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v18, 3
-; GFX11-NEXT:    v_add_nc_u16 v9, v20, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, v22, 3
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v7, v101, v7
-; GFX11-NEXT:    v_or_b32_e32 v6, v100, v6
-; GFX11-NEXT:    v_or_b32_e32 v8, v102, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v103, v9
-; GFX11-NEXT:    v_or_b32_e32 v10, v112, v10
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v10
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v3, v4
-; GFX11-NEXT:    v_or_b32_e32 v3, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v4, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v5, v9, v10
-; GFX11-NEXT:    v_add_nc_u16 v6, v24, 3
-; GFX11-NEXT:    v_add_nc_u16 v7, v26, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v28, 3
-; GFX11-NEXT:    v_add_nc_u16 v9, v30, 3
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_nc_u16 v10, v86, 3
-; GFX11-NEXT:    v_add_nc_u16 v11, v80, 3
-; GFX11-NEXT:    v_add_nc_u16 v12, v71, 3
-; GFX11-NEXT:    v_add_nc_u16 v13, v70, 3
-; GFX11-NEXT:    v_add_nc_u16 v14, v69, 3
-; GFX11-NEXT:    v_add_nc_u16 v15, v68, 3
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX11-NEXT:    v_or_b32_e32 v6, v87, v6
-; GFX11-NEXT:    v_or_b32_e32 v7, v96, v7
-; GFX11-NEXT:    v_or_b32_e32 v8, v97, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v98, v9
-; GFX11-NEXT:    v_or_b32_e32 v10, v99, v10
-; GFX11-NEXT:    v_or_b32_e32 v11, v81, v11
-; GFX11-NEXT:    v_or_b32_e32 v12, v82, v12
-; GFX11-NEXT:    v_or_b32_e32 v13, v83, v13
-; GFX11-NEXT:    v_or_b32_e32 v14, v84, v14
-; GFX11-NEXT:    v_or_b32_e32 v15, v85, v15
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v10
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v11
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v12
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v13
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v14
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v15
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v7
-; GFX11-NEXT:    v_or_b32_e32 v7, v8, v9
-; GFX11-NEXT:    v_or_b32_e32 v8, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v9, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v10, v14, v15
-; GFX11-NEXT:    v_add_nc_u16 v11, v64, 3
-; GFX11-NEXT:    v_add_nc_u16 v12, v55, 3
-; GFX11-NEXT:    v_add_nc_u16 v13, v54, 3
-; GFX11-NEXT:    v_add_nc_u16 v14, v53, 3
-; GFX11-NEXT:    v_add_nc_u16 v15, v52, 3
-; GFX11-NEXT:    v_add_nc_u16 v16, v51, 3
-; GFX11-NEXT:    v_add_nc_u16 v18, v50, 3
-; GFX11-NEXT:    v_add_nc_u16 v20, v49, 3
-; GFX11-NEXT:    v_add_nc_u16 v22, v48, 3
-; GFX11-NEXT:    v_add_nc_u16 v24, v39, 3
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v18
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v24
-; GFX11-NEXT:    v_or_b32_e32 v11, v27, v11
-; GFX11-NEXT:    v_or_b32_e32 v12, v29, v12
-; GFX11-NEXT:    v_or_b32_e32 v13, v65, v13
-; GFX11-NEXT:    v_or_b32_e32 v14, v66, v14
-; GFX11-NEXT:    v_or_b32_e32 v15, v67, v15
-; GFX11-NEXT:    v_or_b32_e32 v16, v17, v16
-; GFX11-NEXT:    v_or_b32_e32 v17, v19, v18
-; GFX11-NEXT:    v_or_b32_e32 v18, v21, v20
-; GFX11-NEXT:    v_or_b32_e32 v19, v23, v22
-; GFX11-NEXT:    v_or_b32_e32 v20, v25, v24
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v11
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v12
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v13
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v14
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v15
-; GFX11-NEXT:    v_add_nc_u16 v16, 0x300, v16
-; GFX11-NEXT:    v_add_nc_u16 v17, 0x300, v17
-; GFX11-NEXT:    v_add_nc_u16 v18, 0x300, v18
-; GFX11-NEXT:    v_add_nc_u16 v19, 0x300, v19
-; GFX11-NEXT:    v_add_nc_u16 v20, 0x300, v20
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff, v19
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v12, v13, v14
-; GFX11-NEXT:    v_or_b32_e32 v13, v15, v16
-; GFX11-NEXT:    v_or_b32_e32 v14, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v15, v19, v20
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v64i8_to_v16i32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v64, off, s32 offset:128
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32 offset:124
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v64, off, s32 offset:120
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v31, off, s32 offset:116
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v65, off, s32 offset:112
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v32, off, s32 offset:108
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v65, off, s32 offset:104
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v32, off, s32 offset:100
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v66, off, s32 offset:96
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v33, off, s32 offset:92
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v66, off, s32 offset:88
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v82, off, s32 offset:132
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v67, off, s32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v67, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v68, off, s32 offset:16
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v68, off, s32 offset:24
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v69, off, s32 offset:32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v69, off, s32 offset:40
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v70, off, s32 offset:48
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v70, off, s32 offset:56
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v71, off, s32 offset:64
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v71, off, s32 offset:72
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v80, off, s32 offset:80
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v33, off, s32 offset:84
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v34, off, s32 offset:76
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v34, off, s32 offset:68
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v35, off, s32 offset:60
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v35, off, s32 offset:52
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v36, off, s32 offset:44
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v36, off, s32 offset:36
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v37, off, s32 offset:28
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v37, off, s32 offset:20
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v38, off, s32 offset:12
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v38, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v80.h, v29.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v81.l, v27.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.l, v22.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.h, v20.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.h, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.l, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.h, v14.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v49.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v49.h, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v50.l, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v54.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v54.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v52.h, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v51.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v52.l, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v51.l, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v50.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v30.h, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v39.l, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v39.h, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v48.l, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v48.h, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.h, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v24.h, 8, v81.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v25.l, 8, v80.h
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.l, 8, v64.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v64.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(29)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.l, 8, v65.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(27)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v65.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(25)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.l, 8, v66.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(23)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v66.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(21)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v25.h, 8, v67.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(20)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v26.h, 8, v67.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(19)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.l, 8, v68.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(18)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.h, 8, v68.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(17)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v22.l, 8, v69.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(16)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v22.h, 8, v69.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(15)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.l, 8, v70.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(14)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v70.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(13)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.l, 8, v71.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(12)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v71.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(11)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.l, 8, v80.l
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v82
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB13_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB13_4
+; GFX11-TRUE16-NEXT:  .LBB13_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB13_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v55.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v55.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v53.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v53.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v49.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v54.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v0.h, v54.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v50.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v49.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v50.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v0.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v52.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.h, v51.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v0.h, v52.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v2.h, v51.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v6, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v1
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v29.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v29.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v28.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v27.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v27.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v30.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v1.h, v39.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v39.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v2.h, v48.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v48.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v6, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v8, v9
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v26.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v30.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v38.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v25.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v10, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v6.h, v24.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v7.h, v25.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v26.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v38.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v37.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v4, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v10
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v37.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v36.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v36.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v21.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v22.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v6.h, v21.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v7.h, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v11, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v13, v14
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v35.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v34.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v8
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.h, 0xff, v35.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v34.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v19.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v20.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v15, v21
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v10, v23
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v11.h, v19.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v12.h, v20.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v11
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v23, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v33.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.h, 0xff, v32.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v32.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v31.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v31.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v9, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v15
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v16.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v11.h, v16.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v17.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v12.h, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v18.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v11
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v19, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v21, v22
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v23, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v14, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v15, v18
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB13_2
+; GFX11-TRUE16-NEXT:  .LBB13_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v55.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v55.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v53.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v53.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v50.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v49.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v49.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v54.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v54.h, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v52.h, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v51.h, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v52.l, v2.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v51.l, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v50.h, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v5, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v29.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v29.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v2.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v28.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v27.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v27.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v30.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v39.l, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v39.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v48.l, v2.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v6, v7
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, v24.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v28.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v48.h, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, v26.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, v30.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v23.h, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v25.l, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v8, v9
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, v38.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v24.h, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v25.h, v7.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v6.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v10, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, v38.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v37.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v26.h, v8.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v6.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.l, 0x300, v7.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, v37.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, v36.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v21.l, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v22.l, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v4, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v10
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, v36.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v21.h, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v22.h, v7.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v6.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v6.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.l, 0x300, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v11, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v13, v14
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, v35.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, v34.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, v33.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v23.l, v8.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.h, v35.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.h, v34.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v11.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.h, 0xff, v11.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v18.h, v11.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v19.h, v12.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v20.h, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v8
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.h, v19.l, v11.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.h, v20.l, v12.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, 0x300, v11.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, 0x300, v12.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, 0x300, v13.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v15, v21
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v10, v23
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, 0x300, v11.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.l, 0x300, v12.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v11
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v23, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, v33.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.h, v32.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, v32.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.h, v31.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, v31.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v11.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.h, 0xff, v11.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v16.l, v11.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.h, v16.h, v11.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v17.l, v12.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.h, v17.h, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v18.l, v13.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v9, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v15
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, 0x300, v11.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, 0x300, v11.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, 0x300, v12.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.l, 0x300, v12.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, 0x300, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v11
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v19, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v21, v22
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v23, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v14, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v15, v18
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v16i32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v38, v14 :: v_dual_mov_b32 v37, v12
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v36, v10 :: v_dual_mov_b32 v35, v8
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v32, v2 :: v_dual_mov_b32 v31, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v0, off, s32 offset:128
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v39, off, s32 offset:124
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32 offset:120
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v48, off, s32 offset:116
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v4, off, s32 offset:112
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v49, off, s32 offset:108
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v6, off, s32 offset:104
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v50, off, s32 offset:100
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v8, off, s32 offset:96
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v51, off, s32 offset:92
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v10, off, s32 offset:88
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v12, off, s32 offset:132
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v14, off, s32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v65, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v66, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v67, off, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v83, off, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v84, off, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v85, off, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v128, off, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v129, off, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v130, off, s32 offset:72
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v131, off, s32 offset:80
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v52, off, s32 offset:84
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v53, off, s32 offset:76
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v54, off, s32 offset:68
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v55, off, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v64, off, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v68, off, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v69, off, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v70, off, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v71, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v80, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v86, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v118, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v119, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v117, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v114, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v115, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v116, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v113, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v100, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v101, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v102, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v103, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v112, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v87, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v96, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v97, 8, v29
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(29)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(27)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v6
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(25)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v8
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(22)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v12
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(21)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v98, 8, v14
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(20)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v99, 8, v65
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(19)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v81, 8, v66
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(18)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v82, 8, v67
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(17)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v83, 8, v83
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(16)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v84, 8, v84
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(15)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v85, 8, v85
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(14)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v128
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(13)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v29, 8, v129
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(12)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v130
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(11)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v66, 8, v131
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v67, 8, v10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB13_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB13_4
+; GFX11-FAKE16-NEXT:  .LBB13_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB13_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v37
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v118
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v119
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v117
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v6, v113
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v114
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v115
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v116
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v101
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v38
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v102
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v103
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v112
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v100
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v9, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v30
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v86
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v71
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v70
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v69
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v68
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v87
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v96
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v97
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v98
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v99
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v81
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v82
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v83
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v84
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v8, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v14, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v64
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v53
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v52
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v51
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v50
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v49
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v48
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v66
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v18, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v24, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v13, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v15, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v19, v20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB13_2
+; GFX11-FAKE16-NEXT:  .LBB13_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v31, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v32, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v33, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v34, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v35, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v36, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v37, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v118, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v119, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v117, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v114, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v115, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v116, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v113, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v16, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v38, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v18, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v20, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v22, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v101, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v100, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v102, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v103, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v112, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v3, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v9, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v24, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v26, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v28, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v30, 3
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v86, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, v80, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v71, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v70, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v69, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, v68, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v87, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v96, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v97, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v98, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v99, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v81, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v82, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v83, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v84, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v85, v15
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v13
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, 0x300, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v8, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v14, v15
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, v64, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v55, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v54, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v53, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, v52, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, v51, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, v50, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, v49, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, v48, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v24, v39, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v27, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v29, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v65, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v66, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v67, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v17, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v19, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v21, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v23, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v25, v24
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v13
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, 0x300, v15
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, 0x300, v16
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, 0x300, v17
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, 0x300, v18
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, 0x300, v19
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, 0x300, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v13, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v15, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v19, v20
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -9528,295 +10576,581 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v32bf16_to_v16f32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v16
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB23_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
-; GFX11-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v21, v17, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v18, v16, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v19, 0x400000, v16
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_bfe_u32 v23, v14, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-NEXT:    v_add3_u32 v21, v21, v17, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v18, v18, v16, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v16, v18, v19, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v19, v23, v14, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-NEXT:    v_or_b32_e32 v18, 0x400000, v17
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-NEXT:    v_bfe_u32 v20, v15, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v15
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v20, v20, v15, 0x7fff
-; GFX11-NEXT:    v_dual_cndmask_b32 v15, v20, v22 :: v_dual_lshlrev_b32 v20, 16, v13
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v15, v15, v16, 0x7060302
-; GFX11-NEXT:    v_dual_cndmask_b32 v17, v21, v18 :: v_dual_add_f32 v18, 0x40c00000, v20
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v16, v18, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v18
-; GFX11-NEXT:    v_add3_u32 v16, v16, v18, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v14
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_cndmask_b32 v14, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v12
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_perm_b32 v14, v14, v17, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v17, v13, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_cndmask_b32 v16, v16, v20
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-NEXT:    v_add3_u32 v17, v17, v13, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v22, v19, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v19
-; GFX11-NEXT:    v_cndmask_b32_e32 v13, v17, v21, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v11
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v17, v22, v19, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-NEXT:    v_perm_b32 v13, v13, v16, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v19, 0x40c00000, v21
-; GFX11-NEXT:    v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v16, v19, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v19
-; GFX11-NEXT:    v_add3_u32 v16, v16, v19, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-NEXT:    v_bfe_u32 v18, v12, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v12
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v18, v18, v12, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v12, v18, v22, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v12, v12, v17, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v17, v11, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-NEXT:    v_add3_u32 v17, v17, v11, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v22, v18, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v19, v10, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v16, v16, v20, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v19, v19, v10, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v11, v17, v21, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v17, v22, v18, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v10
-; GFX11-NEXT:    v_perm_b32 v11, v11, v16, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    v_dual_cndmask_b32 v10, v19, v22 :: v_dual_lshlrev_b32 v21, 16, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_lshlrev_b32 v19, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-NEXT:    v_perm_b32 v10, v10, v17, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v16, v18, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v18
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_add_f32 v8, 0x40c00000, v8
-; GFX11-NEXT:    v_add3_u32 v16, v16, v18, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v22, v19, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v18, v8, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v9, 0x40c00000, v9
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v19
-; GFX11-NEXT:    v_add3_u32 v18, v18, v8, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v17, v9, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v9
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    v_add3_u32 v17, v17, v9, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v9, v17, v21, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v17, v22, v19, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v8
-; GFX11-NEXT:    v_perm_b32 v9, v9, v16, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-NEXT:    v_cndmask_b32_e32 v8, v18, v22, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v8, v8, v17, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_add_f32 v19, 0x40c00000, v21
-; GFX11-NEXT:    v_bfe_u32 v22, v18, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v16, v19, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v19
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-NEXT:    v_add3_u32 v16, v16, v19, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-NEXT:    v_bfe_u32 v19, v6, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v7, 0x40c00000, v7
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v18
-; GFX11-NEXT:    v_add3_u32 v19, v19, v6, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v17, v7, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v7
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    v_add3_u32 v17, v17, v7, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v7, v17, v21, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v17, v22, v18, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v5
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v6
-; GFX11-NEXT:    v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_cndmask_b32 v17, v17, v20
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v20, v18, 16, 1
-; GFX11-NEXT:    v_dual_cndmask_b32 v6, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT:    v_perm_b32 v7, v7, v16, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v6, v6, v17, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v17, 0x40c00000, v19
-; GFX11-NEXT:    v_add3_u32 v19, v20, v18, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v18
-; GFX11-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-NEXT:    v_bfe_u32 v22, v17, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v18, v19, v20, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v19, 0x400000, v17
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v16, v5, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v5
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    v_add3_u32 v16, v16, v5, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v5, v16, v21, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v16, v22, v17, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-NEXT:    v_perm_b32 v5, v5, v18, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v18, v4, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v16, v16, v19, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v19, 0x400000, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    v_add3_u32 v18, v18, v4, 0x7fff
-; GFX11-NEXT:    v_dual_add_f32 v17, 0x40c00000, v20 :: v_dual_lshlrev_b32 v20, 16, v2
-; GFX11-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v4, v18, v19, vcc_lo
-; GFX11-NEXT:    v_bfe_u32 v21, v17, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v18, 0x40c00000, v20
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v17
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-NEXT:    v_perm_b32 v4, v4, v16, 0x7060302
-; GFX11-NEXT:    v_add3_u32 v19, v21, v17, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v21, v3, 16, 1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT:    v_bfe_u32 v22, v18, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v23, 0x400000, v18
-; GFX11-NEXT:    v_cndmask_b32_e32 v17, v19, v20, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v19, v21, v3, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v3
-; GFX11-NEXT:    v_add3_u32 v21, v22, v18, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v1
-; GFX11-NEXT:    v_bfe_u32 v24, v2, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v19, v20, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v19, 0x40c00000, v22
-; GFX11-NEXT:    v_add3_u32 v20, v24, v2, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v3, v3, v17, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v18, v21, v23, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v2
-; GFX11-NEXT:    v_bfe_u32 v22, v19, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_dual_cndmask_b32 v2, v20, v21 :: v_dual_lshlrev_b32 v23, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_add3_u32 v21, v22, v19, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v19
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    v_add_f32_e32 v20, 0x40c00000, v23
-; GFX11-NEXT:    v_perm_b32 v2, v2, v18, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v19, v21, v22 :: v_dual_add_f32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_bfe_u32 v24, v20, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v25, 0x400000, v20
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v21, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v26, 0x400000, v0
-; GFX11-NEXT:    v_add3_u32 v24, v24, v20, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v21, v21, v0, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v23, v1, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_add3_u32 v22, v23, v1, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v23, 0x400000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v22, v23, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-NEXT:    v_perm_b32 v1, v1, v19, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v20, v24, v25, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v21, v26, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v0, v0, v20, 0x7060302
-; GFX11-NEXT:  .LBB23_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v32bf16_to_v16f32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v16
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB23_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff0000, v15
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v15, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v15
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v20, v20, v15, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v15, v20, v22 :: v_dual_add_f32 v16, 0x40c00000, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v15.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v16, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v16
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v19, v16, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v16, v19, v21 :: v_dual_and_b32 v17, 0xffff0000, v14
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_lshlrev_b32 v14, 16, v14
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v15, 0xffff, v15, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v23, v17, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, 0x400000, v17
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v25, v14, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v26, 0x400000, v14
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT:    v_add3_u32 v20, v23, v17, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v22, v25, v14, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v14, v22, v26, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v17, v20, v24 :: v_dual_and_b32 v18, 0xffff0000, v13
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_lshlrev_b32 v13, 16, v13
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v14.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v18, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v18
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v13, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, 0x400000, v13
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v14, 0xffff, v14, v17
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v19, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v16, v16, v13, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v13, v16, v20 :: v_dual_and_b32 v20, 0xffff0000, v11
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff0000, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v16, v17, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_lshlrev_b32 v12, 16, v12
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, 0x400000, v20
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v13, 0xffff, v13, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v19
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v18, v12, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v12
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v18, v18, v12, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v12, v18, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v21, v11, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v18, v20, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v21, v11, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v17, v17, v22, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v11
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT:    v_add3_u32 v18, v18, v20, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff0000, v10
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v11, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v22
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v12, 0xffff, v12, v17
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v18, v18, v23, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v19
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v11, 0xffff, v11, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v18, 0xffff0000, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v20, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_lshlrev_b32 v10, 16, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v18
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v10, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, 0x400000, v10
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v16, v16, v10, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v10, v16, v20, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v9, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff0000, v8
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v16, v17, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v18, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v19, v9, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v9
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v9, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v20, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, 0x400000, v20
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v17, v17, v22 :: v_dual_and_b32 v22, 0xffff0000, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT:    v_add3_u32 v18, v19, v20, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v9, 0xffff, v9, v17
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v7, 0x40c00000, v7 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v21, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v21, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v22
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v10, 0xffff, v10, v16
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v18, v18, v23 :: v_dual_and_b32 v23, 0xffff0000, v4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v19, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v16, v16, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v19
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v8, 0xffff, v8, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v18, 0xffff0000, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v20, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v7, v16, v20
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff0000, v5
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v6, 16, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v18
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v16, v17, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v18, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v19, v6, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v6
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v20, 0x40c00000, v20 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v20, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v21, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v7, 0xffff, v7, v16
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v18, v19, v20, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v21, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v17, v17, v22, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v20
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v6, 0xffff, v6, v17
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v4, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v18, v18, v22, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v19
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v5, 0xffff, v5, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v18, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_add3_u32 v16, v16, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v17, v20, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_add_f32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v16, v16, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v18, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v18
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v20, v20, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v23, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v4.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v20, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    v_add3_u32 v18, v23, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, 0x400000, v19
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v21, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v17, v17, v22 :: v_dual_and_b32 v22, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v21, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v4, 0xffff, v4, v16
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v21, 0x40c00000, v22 :: v_dual_cndmask_b32 v18, v18, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v0
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, 0x400000, v21
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v3, 0xffff, v3, v17
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v19, v20, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v22
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v22, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v25, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v21, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v23, v20, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v22, v22, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v27, 0x400000, v20
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v19, v21, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v23, v23, v20, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v22, v25, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v26, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v25, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v20, v23, v27, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT:    v_add3_u32 v22, v26, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v2, v18
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.l, v20.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v19, v19, v24, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v19
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v22, v25, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v20, v0
+; GFX11-TRUE16-NEXT:  .LBB23_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v32bf16_to_v16f32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v16
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB23_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v17, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v18, v16, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, 0x400000, v16
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v23, v14, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v18, v18, v16, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v18, v19, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v23, v14, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, 0x400000, v17
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v20, v15, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v15
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v20, v20, v15, 0x7fff
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v15, v20, v22 :: v_dual_lshlrev_b32 v20, 16, v13
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v15, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v17, v21, v18 :: v_dual_add_f32 v18, 0x40c00000, v20
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v14
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v14, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v12
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v14, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v17, v13, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_cndmask_b32 v16, v16, v20
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v17, v13, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v19, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v19
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v13, v17, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v22, v19, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v13, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v21
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v17, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v19, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v19
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v19, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v18, v12, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v12
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v18, v18, v12, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v18, v22, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v12, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v17, v11, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v17, v11, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v19, v10, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v16, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v19, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v17, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v22, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v10
+; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v11, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v17, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v19, v22 :: v_dual_lshlrev_b32 v21, 16, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_lshlrev_b32 v19, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v10, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v19, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v18, v8, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v19
+; GFX11-FAKE16-NEXT:    v_add3_u32 v18, v18, v8, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v17, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v17, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v17, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v22, v19, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v8
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v9, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v17, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v18, v22, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v8, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_add_f32 v19, 0x40c00000, v21
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v18, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v19, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v19
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v19, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v19, v6, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v7, 0x40c00000, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v19, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v17, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v17, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v17, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v22, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v5
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_cndmask_b32 v17, v17, v20
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v20, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v6, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v6, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v17, 0x40c00000, v19
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v20, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v17, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v19, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, 0x400000, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v5
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v16, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v22, v17, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v5, v18, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v18, v4, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v16, v19, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    v_add3_u32 v18, v18, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v17, 0x40c00000, v20 :: v_dual_lshlrev_b32 v20, 16, v2
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v18, v19, vcc_lo
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v17, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v17
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v4, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v19, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v21, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v22, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v24, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v19, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v22
+; GFX11-FAKE16-NEXT:    v_add3_u32 v20, v24, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v3, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v21, v23, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v19, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v20, v21 :: v_dual_lshlrev_b32 v23, 16, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v22, v19, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v19
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v23
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v18, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v19, v21, v22 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v24, v20, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, 0x400000, v20
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v24, v24, v20, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v21, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v23, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v22, v23, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, 0x400000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v22, v23, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v19, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v20, v24, v25, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v21, v26, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v20, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB23_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -10889,324 +12223,598 @@ define <64 x i8> @bitcast_v16f32_to_v64i8(<16 x float> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v16f32_to_v64i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v17
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr67
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB24_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
-; GFX11-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
-; GFX11-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 8, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 8, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 24, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 8, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 16, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 8, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v49, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v51, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v52, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v53, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v54, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v64, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v66, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v67, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v68, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v69, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v71, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v80, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v81, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v82, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v83, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v84, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v85, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v86, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v87, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v96, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
-; GFX11-NEXT:  .LBB24_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB24_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_dual_add_f32 v8, 1.0, v8 :: v_dual_add_f32 v15, 1.0, v15
-; GFX11-NEXT:    v_dual_add_f32 v16, 1.0, v16 :: v_dual_add_f32 v7, 1.0, v7
-; GFX11-NEXT:    v_dual_add_f32 v10, 1.0, v10 :: v_dual_add_f32 v13, 1.0, v13
-; GFX11-NEXT:    v_dual_add_f32 v14, 1.0, v14 :: v_dual_add_f32 v9, 1.0, v9
-; GFX11-NEXT:    v_dual_add_f32 v12, 1.0, v12 :: v_dual_add_f32 v11, 1.0, v11
-; GFX11-NEXT:    v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v5
-; GFX11-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
-; GFX11-NEXT:    v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v3
-; GFX11-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
-; GFX11-NEXT:    v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
-; GFX11-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 8, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 8, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 24, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 8, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 16, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 8, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v49, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v51, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v52, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v53, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v54, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v64, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v66, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v67, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v68, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v69, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v71, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v80, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v81, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v82, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v83, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v84, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v85, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v86, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v87, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v96, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
-; GFX11-NEXT:  .LBB24_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v25
-; GFX11-NEXT:    v_and_b32_e32 v96, 0xff, v96
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v24
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v86, 0xff, v86
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v25
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v87
-; GFX11-NEXT:    v_or_b32_e32 v24, v96, v24
-; GFX11-NEXT:    v_lshlrev_b16 v85, 8, v85
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v25
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT:    v_or_b32_e32 v25, v86, v85
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_lshlrev_b16 v84, 8, v84
-; GFX11-NEXT:    v_and_b32_e32 v83, 0xff, v83
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v24
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v82
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v80, 8, v80
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_lshlrev_b16 v71, 8, v71
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v24
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v81
-; GFX11-NEXT:    v_and_b32_e32 v70, 0xff, v70
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v22
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v84
-; GFX11-NEXT:    v_or_b32_e32 v23, v83, v23
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v80
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v71
-; GFX11-NEXT:    v_or_b32_e32 v22, v70, v22
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v24
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v23
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v25
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v22
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v66
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v65
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v21
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v64
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v55
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v54
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v53
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v22
-; GFX11-NEXT:    v_or_b32_e32 v21, v23, v21
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v24
-; GFX11-NEXT:    v_or_b32_e32 v22, v25, v54
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v52
-; GFX11-NEXT:    v_lshlrev_b16 v20, 8, v20
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v51
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v50
-; GFX11-NEXT:    v_lshlrev_b16 v49, 8, v49
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_lshlrev_b16 v48, 8, v48
-; GFX11-NEXT:    v_and_b32_e32 v39, 0xff, v39
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v19
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v53
-; GFX11-NEXT:    v_or_b32_e32 v20, v23, v20
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v24
-; GFX11-NEXT:    v_or_b32_e32 v23, v25, v49
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v48
-; GFX11-NEXT:    v_or_b32_e32 v19, v39, v19
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v21
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v22
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v20
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v23
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v19
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v38
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v37
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v36
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v35
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v34
-; GFX11-NEXT:    v_lshlrev_b16 v18, 8, v18
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v33
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_lshlrev_b16 v69, 8, v69
-; GFX11-NEXT:    v_and_b32_e32 v68, 0xff, v68
-; GFX11-NEXT:    v_lshlrev_b16 v67, 8, v67
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v19
-; GFX11-NEXT:    v_or_b32_e32 v19, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v22
-; GFX11-NEXT:    v_or_b32_e32 v18, v23, v18
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v24
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v32
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v31
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v30
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v29
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v17
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v28
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v27
-; GFX11-NEXT:    v_lshlrev_b16 v26, 8, v26
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v69
-; GFX11-NEXT:    v_or_b32_e32 v67, v68, v67
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v22
-; GFX11-NEXT:    v_or_b32_e32 v17, v23, v17
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v24
-; GFX11-NEXT:    v_or_b32_e32 v21, v25, v26
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v67, 16, v67
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v67
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v19
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v18
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v20
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v17
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v21
-; GFX11-NEXT:    s_clause 0x3
-; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off
-; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
-; GFX11-NEXT:    scratch_store_b128 v0, v[9:12], off offset:32
-; GFX11-NEXT:    scratch_store_b128 v0, v[13:16], off offset:48
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v16f32_to_v64i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v17
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB24_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 24, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v33, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v35, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v37, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v38, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v48, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v49, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v50, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v51, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v52, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v53, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v54, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v55, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v64, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB24_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB24_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v8, 1.0, v8 :: v_dual_add_f32 v15, 1.0, v15
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v16, 1.0, v16 :: v_dual_add_f32 v7, 1.0, v7
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v10, 1.0, v10 :: v_dual_add_f32 v13, 1.0, v13
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v14, 1.0, v14 :: v_dual_add_f32 v9, 1.0, v9
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v12, 1.0, v12 :: v_dual_add_f32 v11, 1.0, v11
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 24, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v33, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v35, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v37, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v38, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v48, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v49, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v50, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v51, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v52, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v53, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v54, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v55, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v64, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB24_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v17.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v64.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v1.h, v18.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v55.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v54.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.h, 8, v53.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v17.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v2.h, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v19.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v21.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v53, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v52.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v24
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v3.h, v20.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v25.l, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v54, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v51.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v5.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v22.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v48.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v25
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.l, 8, v37.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v17.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v50.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v49.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v49, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v50, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v54, v24
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v25, v22
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v39.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v7.h, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v20.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v38.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v19.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.l, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v10.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v35.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v53, v23
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v8.h, v20.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v36.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v11.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v34.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v21, v19
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v33.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.l, 8, v31.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v30.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v32.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.l, 8, v18.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v19.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v19.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v35, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v24, v22
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v20, v34
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v12.h, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v13.h, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v14.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v29.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v15.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.l, 0xff, v16.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v16.l, 0xff, v16.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v26.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v14.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v15.l, v15.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v16.l, v16.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v51, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v25, v23
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v23, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v14
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v49, v50
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v51, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v35, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v21, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v22, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v19, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v23, v24
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, v25, v16
+; GFX11-TRUE16-NEXT:    s_clause 0x3
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[9:12], off offset:32
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[13:16], off offset:48
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v16f32_to_v64i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB24_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 24, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 16, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 16, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v49, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v50, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v51, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v52, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v53, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v54, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v55, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v64, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v65, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v66, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v67, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v68, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v69, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v70, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v81, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v82, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v85, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v86, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB24_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB24_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v8, 1.0, v8 :: v_dual_add_f32 v15, 1.0, v15
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v16, 1.0, v16 :: v_dual_add_f32 v7, 1.0, v7
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v10, 1.0, v10 :: v_dual_add_f32 v13, 1.0, v13
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v14, 1.0, v14 :: v_dual_add_f32 v9, 1.0, v9
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v12, 1.0, v12 :: v_dual_add_f32 v11, 1.0, v11
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 24, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 16, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 16, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v49, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v50, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v51, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v52, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v53, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v54, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v55, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v64, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v65, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v66, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v67, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v68, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v69, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v70, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v81, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v82, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v85, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v86, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB24_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v96, 0xff, v96
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v86, 0xff, v86
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v87
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v96, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v85, 8, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v86, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v84, 8, v84
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v83, 0xff, v83
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v82
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v80, 8, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v71, 8, v71
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v81
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v70, 0xff, v70
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v84
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v83, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v80
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v71
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v70, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v66
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v65
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v64
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v55
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v53, 8, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v23, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v25, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v52
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v51
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v50
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v49, 8, v49
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v48, 8, v48
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v39, 0xff, v39
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v23, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v25, v49
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v48
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v39, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v38
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v37
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v18, 8, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v69, 8, v69
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v68, 0xff, v68
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v67, 8, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v23, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v29
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v26, 8, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v69
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v67, v68, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v23, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v25, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v67, 16, v67
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v21
+; GFX11-FAKE16-NEXT:    s_clause 0x3
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[9:12], off offset:32
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[13:16], off offset:48
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -12733,471 +14341,950 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v64i8_to_v16f32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v38, v14 :: v_dual_mov_b32 v37, v12
-; GFX11-NEXT:    v_dual_mov_b32 v36, v10 :: v_dual_mov_b32 v35, v8
-; GFX11-NEXT:    v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v4
-; GFX11-NEXT:    v_dual_mov_b32 v32, v2 :: v_dual_mov_b32 v31, v0
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v0, off, s32 offset:128
-; GFX11-NEXT:    scratch_load_u16 v39, off, s32 offset:124
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32 offset:120
-; GFX11-NEXT:    scratch_load_u16 v48, off, s32 offset:116
-; GFX11-NEXT:    scratch_load_u16 v4, off, s32 offset:112
-; GFX11-NEXT:    scratch_load_u16 v49, off, s32 offset:108
-; GFX11-NEXT:    scratch_load_u16 v6, off, s32 offset:104
-; GFX11-NEXT:    scratch_load_u16 v50, off, s32 offset:100
-; GFX11-NEXT:    scratch_load_u16 v8, off, s32 offset:96
-; GFX11-NEXT:    scratch_load_u16 v51, off, s32 offset:92
-; GFX11-NEXT:    scratch_load_u16 v10, off, s32 offset:88
-; GFX11-NEXT:    scratch_load_b32 v12, off, s32 offset:132
-; GFX11-NEXT:    scratch_load_u16 v14, off, s32
-; GFX11-NEXT:    scratch_load_u16 v65, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_u16 v66, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_u16 v67, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_u16 v83, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_u16 v84, off, s32 offset:40
-; GFX11-NEXT:    scratch_load_u16 v85, off, s32 offset:48
-; GFX11-NEXT:    scratch_load_u16 v128, off, s32 offset:56
-; GFX11-NEXT:    scratch_load_u16 v129, off, s32 offset:64
-; GFX11-NEXT:    scratch_load_u16 v130, off, s32 offset:72
-; GFX11-NEXT:    scratch_load_u16 v131, off, s32 offset:80
-; GFX11-NEXT:    scratch_load_u16 v52, off, s32 offset:84
-; GFX11-NEXT:    scratch_load_u16 v53, off, s32 offset:76
-; GFX11-NEXT:    scratch_load_u16 v54, off, s32 offset:68
-; GFX11-NEXT:    scratch_load_u16 v55, off, s32 offset:60
-; GFX11-NEXT:    scratch_load_u16 v64, off, s32 offset:52
-; GFX11-NEXT:    scratch_load_u16 v68, off, s32 offset:44
-; GFX11-NEXT:    scratch_load_u16 v69, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_u16 v70, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_u16 v71, off, s32 offset:20
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_u16 v80, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_u16 v86, off, s32 offset:4
-; GFX11-NEXT:    v_lshlrev_b16 v118, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v119, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v117, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v114, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v115, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v116, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v113, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v100, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v101, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v102, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v103, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v112, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v87, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v96, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v97, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(33)
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(31)
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(29)
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v4
-; GFX11-NEXT:    s_waitcnt vmcnt(27)
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v6
-; GFX11-NEXT:    s_waitcnt vmcnt(25)
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v8
-; GFX11-NEXT:    s_waitcnt vmcnt(22)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v12
-; GFX11-NEXT:    s_waitcnt vmcnt(21)
-; GFX11-NEXT:    v_lshlrev_b16 v98, 8, v14
-; GFX11-NEXT:    s_waitcnt vmcnt(20)
-; GFX11-NEXT:    v_lshlrev_b16 v99, 8, v65
-; GFX11-NEXT:    s_waitcnt vmcnt(19)
-; GFX11-NEXT:    v_lshlrev_b16 v81, 8, v66
-; GFX11-NEXT:    s_waitcnt vmcnt(18)
-; GFX11-NEXT:    v_lshlrev_b16 v82, 8, v67
-; GFX11-NEXT:    s_waitcnt vmcnt(17)
-; GFX11-NEXT:    v_lshlrev_b16 v83, 8, v83
-; GFX11-NEXT:    s_waitcnt vmcnt(16)
-; GFX11-NEXT:    v_lshlrev_b16 v84, 8, v84
-; GFX11-NEXT:    s_waitcnt vmcnt(15)
-; GFX11-NEXT:    v_lshlrev_b16 v85, 8, v85
-; GFX11-NEXT:    s_waitcnt vmcnt(14)
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v128
-; GFX11-NEXT:    s_waitcnt vmcnt(13)
-; GFX11-NEXT:    v_lshlrev_b16 v29, 8, v129
-; GFX11-NEXT:    s_waitcnt vmcnt(12)
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v130
-; GFX11-NEXT:    s_waitcnt vmcnt(11)
-; GFX11-NEXT:    v_lshlrev_b16 v66, 8, v131
-; GFX11-NEXT:    v_lshlrev_b16 v67, 8, v10
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB25_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB25_4
-; GFX11-NEXT:  .LBB25_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB25_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v31
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v37
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v34
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v118
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v119
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v35
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v36
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v18
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v22
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v117
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v6, v113
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v114
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v115
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v116
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v101
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v1
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v38
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v102
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v103
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v112
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v100
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v11
-; GFX11-NEXT:    v_or_b32_e32 v4, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v5, v9, v10
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v24
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v26
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v30
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v86
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v80
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v71
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v70
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v69
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v68
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v87
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v96
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v97
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v98
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v99
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v81
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v82
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v83
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v84
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v85
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v7
-; GFX11-NEXT:    v_or_b32_e32 v7, v8, v9
-; GFX11-NEXT:    v_or_b32_e32 v8, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v9, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v10, v14, v15
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v64
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v55
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v54
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v53
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v52
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v51
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v50
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v49
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v48
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v39
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v27
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v29
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v65
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v66
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v67
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v17, v18, v19
-; GFX11-NEXT:    v_or_b32_e32 v18, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v19, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v20, v24, v25
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff, v19
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v12, v13, v14
-; GFX11-NEXT:    v_or_b32_e32 v13, v15, v16
-; GFX11-NEXT:    v_or_b32_e32 v14, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v15, v19, v20
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr118
-; GFX11-NEXT:    ; implicit-def: $vgpr119
-; GFX11-NEXT:    ; implicit-def: $vgpr117
-; GFX11-NEXT:    ; implicit-def: $vgpr114
-; GFX11-NEXT:    ; implicit-def: $vgpr115
-; GFX11-NEXT:    ; implicit-def: $vgpr116
-; GFX11-NEXT:    ; implicit-def: $vgpr113
-; GFX11-NEXT:    ; implicit-def: $vgpr100
-; GFX11-NEXT:    ; implicit-def: $vgpr101
-; GFX11-NEXT:    ; implicit-def: $vgpr102
-; GFX11-NEXT:    ; implicit-def: $vgpr103
-; GFX11-NEXT:    ; implicit-def: $vgpr112
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr97
-; GFX11-NEXT:    ; implicit-def: $vgpr98
-; GFX11-NEXT:    ; implicit-def: $vgpr99
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr67
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB25_2
-; GFX11-NEXT:  .LBB25_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v31, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v32, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v33, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v34, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v35, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v5, v36, 3
-; GFX11-NEXT:    v_add_nc_u16 v6, v37, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_or_b32_e32 v0, v118, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v119, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_or_b32_e32 v2, v117, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v114, v3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_or_b32_e32 v4, v115, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v116, v5
-; GFX11-NEXT:    v_or_b32_e32 v6, v113, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, v16, 3
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v5
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v6, v38, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v18, 3
-; GFX11-NEXT:    v_add_nc_u16 v9, v20, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, v22, 3
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v7, v101, v7
-; GFX11-NEXT:    v_or_b32_e32 v6, v100, v6
-; GFX11-NEXT:    v_or_b32_e32 v8, v102, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v103, v9
-; GFX11-NEXT:    v_or_b32_e32 v10, v112, v10
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v10
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v3, v4
-; GFX11-NEXT:    v_or_b32_e32 v3, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v4, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v5, v9, v10
-; GFX11-NEXT:    v_add_nc_u16 v6, v24, 3
-; GFX11-NEXT:    v_add_nc_u16 v7, v26, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v28, 3
-; GFX11-NEXT:    v_add_nc_u16 v9, v30, 3
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_nc_u16 v10, v86, 3
-; GFX11-NEXT:    v_add_nc_u16 v11, v80, 3
-; GFX11-NEXT:    v_add_nc_u16 v12, v71, 3
-; GFX11-NEXT:    v_add_nc_u16 v13, v70, 3
-; GFX11-NEXT:    v_add_nc_u16 v14, v69, 3
-; GFX11-NEXT:    v_add_nc_u16 v15, v68, 3
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX11-NEXT:    v_or_b32_e32 v6, v87, v6
-; GFX11-NEXT:    v_or_b32_e32 v7, v96, v7
-; GFX11-NEXT:    v_or_b32_e32 v8, v97, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v98, v9
-; GFX11-NEXT:    v_or_b32_e32 v10, v99, v10
-; GFX11-NEXT:    v_or_b32_e32 v11, v81, v11
-; GFX11-NEXT:    v_or_b32_e32 v12, v82, v12
-; GFX11-NEXT:    v_or_b32_e32 v13, v83, v13
-; GFX11-NEXT:    v_or_b32_e32 v14, v84, v14
-; GFX11-NEXT:    v_or_b32_e32 v15, v85, v15
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v10
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v11
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v12
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v13
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v14
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v15
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v7
-; GFX11-NEXT:    v_or_b32_e32 v7, v8, v9
-; GFX11-NEXT:    v_or_b32_e32 v8, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v9, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v10, v14, v15
-; GFX11-NEXT:    v_add_nc_u16 v11, v64, 3
-; GFX11-NEXT:    v_add_nc_u16 v12, v55, 3
-; GFX11-NEXT:    v_add_nc_u16 v13, v54, 3
-; GFX11-NEXT:    v_add_nc_u16 v14, v53, 3
-; GFX11-NEXT:    v_add_nc_u16 v15, v52, 3
-; GFX11-NEXT:    v_add_nc_u16 v16, v51, 3
-; GFX11-NEXT:    v_add_nc_u16 v18, v50, 3
-; GFX11-NEXT:    v_add_nc_u16 v20, v49, 3
-; GFX11-NEXT:    v_add_nc_u16 v22, v48, 3
-; GFX11-NEXT:    v_add_nc_u16 v24, v39, 3
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v18
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v24
-; GFX11-NEXT:    v_or_b32_e32 v11, v27, v11
-; GFX11-NEXT:    v_or_b32_e32 v12, v29, v12
-; GFX11-NEXT:    v_or_b32_e32 v13, v65, v13
-; GFX11-NEXT:    v_or_b32_e32 v14, v66, v14
-; GFX11-NEXT:    v_or_b32_e32 v15, v67, v15
-; GFX11-NEXT:    v_or_b32_e32 v16, v17, v16
-; GFX11-NEXT:    v_or_b32_e32 v17, v19, v18
-; GFX11-NEXT:    v_or_b32_e32 v18, v21, v20
-; GFX11-NEXT:    v_or_b32_e32 v19, v23, v22
-; GFX11-NEXT:    v_or_b32_e32 v20, v25, v24
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v11
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v12
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v13
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v14
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v15
-; GFX11-NEXT:    v_add_nc_u16 v16, 0x300, v16
-; GFX11-NEXT:    v_add_nc_u16 v17, 0x300, v17
-; GFX11-NEXT:    v_add_nc_u16 v18, 0x300, v18
-; GFX11-NEXT:    v_add_nc_u16 v19, 0x300, v19
-; GFX11-NEXT:    v_add_nc_u16 v20, 0x300, v20
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff, v19
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v12, v13, v14
-; GFX11-NEXT:    v_or_b32_e32 v13, v15, v16
-; GFX11-NEXT:    v_or_b32_e32 v14, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v15, v19, v20
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v64i8_to_v16f32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v64, off, s32 offset:128
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32 offset:124
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v64, off, s32 offset:120
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v31, off, s32 offset:116
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v65, off, s32 offset:112
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v32, off, s32 offset:108
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v65, off, s32 offset:104
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v32, off, s32 offset:100
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v66, off, s32 offset:96
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v33, off, s32 offset:92
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v66, off, s32 offset:88
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v82, off, s32 offset:132
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v67, off, s32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v67, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v68, off, s32 offset:16
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v68, off, s32 offset:24
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v69, off, s32 offset:32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v69, off, s32 offset:40
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v70, off, s32 offset:48
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v70, off, s32 offset:56
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v71, off, s32 offset:64
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v71, off, s32 offset:72
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v80, off, s32 offset:80
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v33, off, s32 offset:84
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v34, off, s32 offset:76
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v34, off, s32 offset:68
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v35, off, s32 offset:60
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v35, off, s32 offset:52
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v36, off, s32 offset:44
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v36, off, s32 offset:36
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v37, off, s32 offset:28
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v37, off, s32 offset:20
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v38, off, s32 offset:12
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v38, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v80.h, v29.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v81.l, v27.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.l, v22.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.h, v20.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.h, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.l, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.h, v14.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v49.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v49.h, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v50.l, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v54.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v54.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v52.h, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v51.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v52.l, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v51.l, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v50.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v30.h, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v39.l, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v39.h, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v48.l, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v48.h, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.h, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v24.h, 8, v81.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v25.l, 8, v80.h
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.l, 8, v64.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v64.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(29)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.l, 8, v65.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(27)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v65.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(25)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.l, 8, v66.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(23)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v66.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(21)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v25.h, 8, v67.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(20)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v26.h, 8, v67.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(19)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.l, 8, v68.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(18)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.h, 8, v68.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(17)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v22.l, 8, v69.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(16)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v22.h, 8, v69.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(15)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.l, 8, v70.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(14)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v70.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(13)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.l, 8, v71.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(12)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v71.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(11)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.l, 8, v80.l
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v82
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB25_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB25_4
+; GFX11-TRUE16-NEXT:  .LBB25_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB25_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v55.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v55.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v53.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v53.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v49.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v54.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v0.h, v54.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v50.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v49.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v50.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v0.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v52.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.h, v51.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v0.h, v52.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v2.h, v51.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v6, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v1
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v29.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v29.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v28.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v27.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v27.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v30.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v1.h, v39.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v39.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v2.h, v48.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v48.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v6, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v8, v9
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v26.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v30.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v38.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v25.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v10, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v6.h, v24.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v7.h, v25.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v26.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v38.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v37.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v4, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v10
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v37.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v36.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v36.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v21.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v22.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v6.h, v21.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v7.h, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v11, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v13, v14
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v35.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v34.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v8
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.h, 0xff, v35.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v34.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v19.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v20.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v15, v21
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v10, v23
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v11.h, v19.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v12.h, v20.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v11
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v23, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v33.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.h, 0xff, v32.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v32.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v31.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v31.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v9, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v15
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v16.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v11.h, v16.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v17.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v12.h, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v18.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v11
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v19, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v21, v22
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v23, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v14, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v15, v18
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB25_2
+; GFX11-TRUE16-NEXT:  .LBB25_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v55.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v55.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v53.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v53.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v50.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v49.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v49.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v54.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v54.h, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v52.h, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v51.h, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v52.l, v2.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v51.l, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v50.h, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v5, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v29.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v29.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v2.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v28.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v27.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v27.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v30.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v39.l, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v39.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v48.l, v2.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v6, v7
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, v24.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v28.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v48.h, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, v26.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, v30.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v23.h, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v25.l, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v8, v9
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, v38.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v24.h, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v25.h, v7.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v6.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v10, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, v38.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v37.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v26.h, v8.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v6.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.l, 0x300, v7.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, v37.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, v36.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v21.l, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v22.l, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v4, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v10
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, v36.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v21.h, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v22.h, v7.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v6.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v6.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.l, 0x300, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v11, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v13, v14
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, v35.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, v34.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, v33.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v23.l, v8.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.h, v35.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.h, v34.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v11.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.h, 0xff, v11.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v18.h, v11.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v19.h, v12.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v20.h, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v8
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.h, v19.l, v11.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.h, v20.l, v12.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, 0x300, v11.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, 0x300, v12.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, 0x300, v13.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v15, v21
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v10, v23
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, 0x300, v11.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.l, 0x300, v12.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v11
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v23, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, v33.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.h, v32.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, v32.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.h, v31.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, v31.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v11.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.h, 0xff, v11.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v16.l, v11.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.h, v16.h, v11.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v17.l, v12.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.h, v17.h, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v18.l, v13.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v9, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v15
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, 0x300, v11.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, 0x300, v11.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, 0x300, v12.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.l, 0x300, v12.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, 0x300, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v11
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v19, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v21, v22
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v23, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v14, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v15, v18
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v16f32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v38, v14 :: v_dual_mov_b32 v37, v12
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v36, v10 :: v_dual_mov_b32 v35, v8
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v32, v2 :: v_dual_mov_b32 v31, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v0, off, s32 offset:128
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v39, off, s32 offset:124
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32 offset:120
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v48, off, s32 offset:116
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v4, off, s32 offset:112
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v49, off, s32 offset:108
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v6, off, s32 offset:104
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v50, off, s32 offset:100
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v8, off, s32 offset:96
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v51, off, s32 offset:92
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v10, off, s32 offset:88
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v12, off, s32 offset:132
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v14, off, s32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v65, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v66, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v67, off, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v83, off, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v84, off, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v85, off, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v128, off, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v129, off, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v130, off, s32 offset:72
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v131, off, s32 offset:80
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v52, off, s32 offset:84
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v53, off, s32 offset:76
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v54, off, s32 offset:68
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v55, off, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v64, off, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v68, off, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v69, off, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v70, off, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v71, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v80, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v86, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v118, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v119, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v117, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v114, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v115, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v116, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v113, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v100, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v101, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v102, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v103, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v112, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v87, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v96, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v97, 8, v29
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(29)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(27)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v6
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(25)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v8
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(22)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v12
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(21)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v98, 8, v14
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(20)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v99, 8, v65
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(19)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v81, 8, v66
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(18)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v82, 8, v67
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(17)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v83, 8, v83
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(16)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v84, 8, v84
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(15)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v85, 8, v85
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(14)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v128
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(13)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v29, 8, v129
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(12)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v130
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(11)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v66, 8, v131
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v67, 8, v10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB25_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB25_4
+; GFX11-FAKE16-NEXT:  .LBB25_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB25_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v37
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v118
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v119
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v117
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v6, v113
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v114
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v115
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v116
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v101
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v38
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v102
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v103
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v112
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v100
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v9, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v30
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v86
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v71
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v70
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v69
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v68
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v87
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v96
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v97
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v98
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v99
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v81
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v82
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v83
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v84
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v8, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v14, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v64
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v53
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v52
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v51
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v50
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v49
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v48
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v66
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v18, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v24, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v13, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v15, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v19, v20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB25_2
+; GFX11-FAKE16-NEXT:  .LBB25_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v31, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v32, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v33, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v34, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v35, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v36, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v37, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v118, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v119, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v117, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v114, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v115, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v116, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v113, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v16, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v38, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v18, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v20, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v22, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v101, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v100, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v102, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v103, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v112, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v3, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v9, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v24, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v26, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v28, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v30, 3
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v86, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, v80, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v71, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v70, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v69, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, v68, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v87, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v96, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v97, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v98, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v99, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v81, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v82, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v83, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v84, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v85, v15
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v13
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, 0x300, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v8, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v14, v15
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, v64, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v55, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v54, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v53, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, v52, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, v51, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, v50, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, v49, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, v48, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v24, v39, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v27, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v29, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v65, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v66, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v67, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v17, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v19, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v21, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v23, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v25, v24
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v13
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, 0x300, v15
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, 0x300, v16
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, 0x300, v17
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, 0x300, v18
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, 0x300, v19
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, 0x300, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v13, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v15, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v19, v20
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -15763,295 +17850,581 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v32bf16_to_v8i64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v16
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB33_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
-; GFX11-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v21, v17, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v18, v16, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v19, 0x400000, v16
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_bfe_u32 v23, v14, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-NEXT:    v_add3_u32 v21, v21, v17, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v18, v18, v16, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v16, v18, v19, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v19, v23, v14, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-NEXT:    v_or_b32_e32 v18, 0x400000, v17
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-NEXT:    v_bfe_u32 v20, v15, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v15
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v20, v20, v15, 0x7fff
-; GFX11-NEXT:    v_dual_cndmask_b32 v15, v20, v22 :: v_dual_lshlrev_b32 v20, 16, v13
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v15, v15, v16, 0x7060302
-; GFX11-NEXT:    v_dual_cndmask_b32 v17, v21, v18 :: v_dual_add_f32 v18, 0x40c00000, v20
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v16, v18, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v18
-; GFX11-NEXT:    v_add3_u32 v16, v16, v18, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v14
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_cndmask_b32 v14, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v12
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_perm_b32 v14, v14, v17, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v17, v13, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_cndmask_b32 v16, v16, v20
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-NEXT:    v_add3_u32 v17, v17, v13, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v22, v19, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v19
-; GFX11-NEXT:    v_cndmask_b32_e32 v13, v17, v21, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v11
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v17, v22, v19, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-NEXT:    v_perm_b32 v13, v13, v16, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v19, 0x40c00000, v21
-; GFX11-NEXT:    v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v16, v19, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v19
-; GFX11-NEXT:    v_add3_u32 v16, v16, v19, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-NEXT:    v_bfe_u32 v18, v12, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v12
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v18, v18, v12, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v12, v18, v22, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v12, v12, v17, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v17, v11, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-NEXT:    v_add3_u32 v17, v17, v11, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v22, v18, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v19, v10, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v16, v16, v20, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v19, v19, v10, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v11, v17, v21, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v17, v22, v18, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v10
-; GFX11-NEXT:    v_perm_b32 v11, v11, v16, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    v_dual_cndmask_b32 v10, v19, v22 :: v_dual_lshlrev_b32 v21, 16, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_lshlrev_b32 v19, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-NEXT:    v_perm_b32 v10, v10, v17, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v16, v18, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v18
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_add_f32 v8, 0x40c00000, v8
-; GFX11-NEXT:    v_add3_u32 v16, v16, v18, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v22, v19, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v18, v8, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v9, 0x40c00000, v9
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v19
-; GFX11-NEXT:    v_add3_u32 v18, v18, v8, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v17, v9, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v9
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    v_add3_u32 v17, v17, v9, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v9, v17, v21, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v17, v22, v19, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v8
-; GFX11-NEXT:    v_perm_b32 v9, v9, v16, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-NEXT:    v_cndmask_b32_e32 v8, v18, v22, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v8, v8, v17, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_add_f32 v19, 0x40c00000, v21
-; GFX11-NEXT:    v_bfe_u32 v22, v18, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v16, v19, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v19
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-NEXT:    v_add3_u32 v16, v16, v19, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-NEXT:    v_bfe_u32 v19, v6, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v7, 0x40c00000, v7
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v18
-; GFX11-NEXT:    v_add3_u32 v19, v19, v6, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v17, v7, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v7
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    v_add3_u32 v17, v17, v7, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v7, v17, v21, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v17, v22, v18, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v5
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v6
-; GFX11-NEXT:    v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_cndmask_b32 v17, v17, v20
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v20, v18, 16, 1
-; GFX11-NEXT:    v_dual_cndmask_b32 v6, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT:    v_perm_b32 v7, v7, v16, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v6, v6, v17, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v17, 0x40c00000, v19
-; GFX11-NEXT:    v_add3_u32 v19, v20, v18, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v18
-; GFX11-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-NEXT:    v_bfe_u32 v22, v17, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v18, v19, v20, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v19, 0x400000, v17
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v16, v5, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v5
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    v_add3_u32 v16, v16, v5, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v5, v16, v21, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v16, v22, v17, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-NEXT:    v_perm_b32 v5, v5, v18, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v18, v4, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v16, v16, v19, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v19, 0x400000, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    v_add3_u32 v18, v18, v4, 0x7fff
-; GFX11-NEXT:    v_dual_add_f32 v17, 0x40c00000, v20 :: v_dual_lshlrev_b32 v20, 16, v2
-; GFX11-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v4, v18, v19, vcc_lo
-; GFX11-NEXT:    v_bfe_u32 v21, v17, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v18, 0x40c00000, v20
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v17
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-NEXT:    v_perm_b32 v4, v4, v16, 0x7060302
-; GFX11-NEXT:    v_add3_u32 v19, v21, v17, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v21, v3, 16, 1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT:    v_bfe_u32 v22, v18, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v23, 0x400000, v18
-; GFX11-NEXT:    v_cndmask_b32_e32 v17, v19, v20, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v19, v21, v3, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v3
-; GFX11-NEXT:    v_add3_u32 v21, v22, v18, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v1
-; GFX11-NEXT:    v_bfe_u32 v24, v2, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v19, v20, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v19, 0x40c00000, v22
-; GFX11-NEXT:    v_add3_u32 v20, v24, v2, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v3, v3, v17, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v18, v21, v23, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v2
-; GFX11-NEXT:    v_bfe_u32 v22, v19, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_dual_cndmask_b32 v2, v20, v21 :: v_dual_lshlrev_b32 v23, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_add3_u32 v21, v22, v19, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v19
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    v_add_f32_e32 v20, 0x40c00000, v23
-; GFX11-NEXT:    v_perm_b32 v2, v2, v18, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v19, v21, v22 :: v_dual_add_f32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_bfe_u32 v24, v20, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v25, 0x400000, v20
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v21, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v26, 0x400000, v0
-; GFX11-NEXT:    v_add3_u32 v24, v24, v20, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v21, v21, v0, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v23, v1, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_add3_u32 v22, v23, v1, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v23, 0x400000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v22, v23, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-NEXT:    v_perm_b32 v1, v1, v19, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v20, v24, v25, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v21, v26, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v0, v0, v20, 0x7060302
-; GFX11-NEXT:  .LBB33_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v32bf16_to_v8i64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v16
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB33_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff0000, v15
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v15, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v15
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v20, v20, v15, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v15, v20, v22 :: v_dual_add_f32 v16, 0x40c00000, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v15.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v16, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v16
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v19, v16, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v16, v19, v21 :: v_dual_and_b32 v17, 0xffff0000, v14
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_lshlrev_b32 v14, 16, v14
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v15, 0xffff, v15, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v23, v17, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, 0x400000, v17
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v25, v14, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v26, 0x400000, v14
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT:    v_add3_u32 v20, v23, v17, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v22, v25, v14, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v14, v22, v26, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v17, v20, v24 :: v_dual_and_b32 v18, 0xffff0000, v13
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_lshlrev_b32 v13, 16, v13
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v14.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v18, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v18
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v13, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, 0x400000, v13
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v14, 0xffff, v14, v17
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v19, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v16, v16, v13, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v13, v16, v20 :: v_dual_and_b32 v20, 0xffff0000, v11
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff0000, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v16, v17, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_lshlrev_b32 v12, 16, v12
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, 0x400000, v20
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v13, 0xffff, v13, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v19
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v18, v12, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v12
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v18, v18, v12, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v12, v18, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v21, v11, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v18, v20, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v21, v11, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v17, v17, v22, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v11
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT:    v_add3_u32 v18, v18, v20, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff0000, v10
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v11, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v22
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v12, 0xffff, v12, v17
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v18, v18, v23, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v19
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v11, 0xffff, v11, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v18, 0xffff0000, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v20, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_lshlrev_b32 v10, 16, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v18
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v10, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, 0x400000, v10
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v16, v16, v10, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v10, v16, v20, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v9, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff0000, v8
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v16, v17, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v18, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v19, v9, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v9
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v9, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v20, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, 0x400000, v20
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v17, v17, v22 :: v_dual_and_b32 v22, 0xffff0000, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT:    v_add3_u32 v18, v19, v20, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v9, 0xffff, v9, v17
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v7, 0x40c00000, v7 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v21, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v21, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v22
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v10, 0xffff, v10, v16
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v18, v18, v23 :: v_dual_and_b32 v23, 0xffff0000, v4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v19, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v16, v16, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v19
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v8, 0xffff, v8, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v18, 0xffff0000, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v20, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v7, v16, v20
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff0000, v5
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v6, 16, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v18
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v16, v17, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v18, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v19, v6, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v6
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v20, 0x40c00000, v20 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v20, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v21, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v7, 0xffff, v7, v16
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v18, v19, v20, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v21, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v17, v17, v22, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v20
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v6, 0xffff, v6, v17
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v4, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v18, v18, v22, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v19
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v5, 0xffff, v5, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v18, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_add3_u32 v16, v16, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v17, v20, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_add_f32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v16, v16, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v18, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v18
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v20, v20, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v23, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v4.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v20, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    v_add3_u32 v18, v23, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, 0x400000, v19
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v21, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v17, v17, v22 :: v_dual_and_b32 v22, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v21, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v4, 0xffff, v4, v16
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v21, 0x40c00000, v22 :: v_dual_cndmask_b32 v18, v18, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v0
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, 0x400000, v21
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v3, 0xffff, v3, v17
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v19, v20, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v22
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v22, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v25, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v21, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v23, v20, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v22, v22, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v27, 0x400000, v20
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v19, v21, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v23, v23, v20, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v22, v25, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v26, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v25, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v20, v23, v27, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT:    v_add3_u32 v22, v26, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v2, v18
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.l, v20.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v19, v19, v24, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v19
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v22, v25, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v20, v0
+; GFX11-TRUE16-NEXT:  .LBB33_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v32bf16_to_v8i64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v16
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB33_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v17, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v18, v16, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, 0x400000, v16
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v23, v14, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v18, v18, v16, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v18, v19, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v23, v14, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, 0x400000, v17
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v20, v15, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v15
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v20, v20, v15, 0x7fff
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v15, v20, v22 :: v_dual_lshlrev_b32 v20, 16, v13
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v15, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v17, v21, v18 :: v_dual_add_f32 v18, 0x40c00000, v20
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v14
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v14, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v12
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v14, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v17, v13, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_cndmask_b32 v16, v16, v20
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v17, v13, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v19, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v19
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v13, v17, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v22, v19, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v13, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v21
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v17, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v19, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v19
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v19, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v18, v12, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v12
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v18, v18, v12, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v18, v22, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v12, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v17, v11, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v17, v11, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v19, v10, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v16, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v19, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v17, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v22, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v10
+; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v11, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v17, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v19, v22 :: v_dual_lshlrev_b32 v21, 16, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_lshlrev_b32 v19, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v10, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v19, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v18, v8, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v19
+; GFX11-FAKE16-NEXT:    v_add3_u32 v18, v18, v8, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v17, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v17, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v17, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v22, v19, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v8
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v9, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v17, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v18, v22, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v8, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_add_f32 v19, 0x40c00000, v21
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v18, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v19, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v19
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v19, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v19, v6, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v7, 0x40c00000, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v19, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v17, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v17, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v17, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v22, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v5
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_cndmask_b32 v17, v17, v20
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v20, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v6, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v6, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v17, 0x40c00000, v19
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v20, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v17, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v19, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, 0x400000, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v5
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v16, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v22, v17, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v5, v18, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v18, v4, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v16, v19, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    v_add3_u32 v18, v18, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v17, 0x40c00000, v20 :: v_dual_lshlrev_b32 v20, 16, v2
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v18, v19, vcc_lo
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v17, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v17
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v4, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v19, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v21, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v22, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v24, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v19, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v22
+; GFX11-FAKE16-NEXT:    v_add3_u32 v20, v24, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v3, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v21, v23, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v19, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v20, v21 :: v_dual_lshlrev_b32 v23, 16, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v22, v19, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v19
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v23
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v18, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v19, v21, v22 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v24, v20, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, 0x400000, v20
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v24, v24, v20, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v21, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v23, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v22, v23, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, 0x400000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v22, v23, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v19, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v20, v24, v25, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v21, v26, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v20, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB33_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -17124,337 +19497,624 @@ define <64 x i8> @bitcast_v8i64_to_v64i8(<8 x i64> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v8i64_to_v64i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v17
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr67
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB34_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
-; GFX11-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
-; GFX11-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 8, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 8, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 24, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 8, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 16, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 8, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v49, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v51, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v52, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v53, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v54, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v64, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v66, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v67, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v68, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v69, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v71, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v80, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v81, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v82, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v83, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v84, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v85, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v86, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v87, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v96, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
-; GFX11-NEXT:  .LBB34_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB34_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_co_u32 v1, vcc_lo, v1, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v2, null, 0, v2, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v3, vcc_lo, v3, 3
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v4, null, 0, v4, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v5, vcc_lo, v5, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v6, null, 0, v6, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v9, vcc_lo, v9, 3
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v10, null, 0, v10, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v11, vcc_lo, v11, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v12, null, 0, v12, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v13, vcc_lo, v13, 3
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v14, null, 0, v14, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v15, vcc_lo, v15, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v16, null, 0, v16, vcc_lo
-; GFX11-NEXT:    v_add_co_u32 v7, vcc_lo, v7, 3
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v8, null, 0, v8, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
-; GFX11-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
-; GFX11-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 8, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 8, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 24, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 8, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 16, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 8, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v49, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v51, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v52, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v53, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v54, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v64, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v66, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v67, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v68, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v69, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v71, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v80, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v81, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v82, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v83, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v84, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v85, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v86, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v87, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v96, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
-; GFX11-NEXT:  .LBB34_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v25
-; GFX11-NEXT:    v_and_b32_e32 v96, 0xff, v96
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v24
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v86, 0xff, v86
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v25
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v87
-; GFX11-NEXT:    v_or_b32_e32 v24, v96, v24
-; GFX11-NEXT:    v_lshlrev_b16 v85, 8, v85
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v25
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT:    v_or_b32_e32 v25, v86, v85
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_lshlrev_b16 v84, 8, v84
-; GFX11-NEXT:    v_and_b32_e32 v83, 0xff, v83
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v24
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v82
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v80, 8, v80
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_lshlrev_b16 v71, 8, v71
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v24
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v81
-; GFX11-NEXT:    v_and_b32_e32 v70, 0xff, v70
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v22
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v84
-; GFX11-NEXT:    v_or_b32_e32 v23, v83, v23
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v80
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v71
-; GFX11-NEXT:    v_or_b32_e32 v22, v70, v22
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v24
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v23
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v25
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v22
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v66
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v65
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v21
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v64
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v55
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v54
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v53
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v22
-; GFX11-NEXT:    v_or_b32_e32 v21, v23, v21
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v24
-; GFX11-NEXT:    v_or_b32_e32 v22, v25, v54
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v52
-; GFX11-NEXT:    v_lshlrev_b16 v20, 8, v20
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v51
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v50
-; GFX11-NEXT:    v_lshlrev_b16 v49, 8, v49
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_lshlrev_b16 v48, 8, v48
-; GFX11-NEXT:    v_and_b32_e32 v39, 0xff, v39
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v19
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v53
-; GFX11-NEXT:    v_or_b32_e32 v20, v23, v20
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v24
-; GFX11-NEXT:    v_or_b32_e32 v23, v25, v49
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v48
-; GFX11-NEXT:    v_or_b32_e32 v19, v39, v19
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v21
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v22
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v20
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v23
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v19
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v38
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v37
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v36
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v35
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v34
-; GFX11-NEXT:    v_lshlrev_b16 v18, 8, v18
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v33
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_lshlrev_b16 v69, 8, v69
-; GFX11-NEXT:    v_and_b32_e32 v68, 0xff, v68
-; GFX11-NEXT:    v_lshlrev_b16 v67, 8, v67
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v19
-; GFX11-NEXT:    v_or_b32_e32 v19, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v22
-; GFX11-NEXT:    v_or_b32_e32 v18, v23, v18
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v24
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v32
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v31
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v30
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v29
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v17
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v28
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v27
-; GFX11-NEXT:    v_lshlrev_b16 v26, 8, v26
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v69
-; GFX11-NEXT:    v_or_b32_e32 v67, v68, v67
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v22
-; GFX11-NEXT:    v_or_b32_e32 v17, v23, v17
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v24
-; GFX11-NEXT:    v_or_b32_e32 v21, v25, v26
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v67, 16, v67
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v67
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v19
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v18
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v20
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v17
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v21
-; GFX11-NEXT:    s_clause 0x3
-; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off
-; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
-; GFX11-NEXT:    scratch_store_b128 v0, v[9:12], off offset:32
-; GFX11-NEXT:    scratch_store_b128 v0, v[13:16], off offset:48
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v8i64_to_v64i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v17
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB34_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 24, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v33, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v35, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v37, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v38, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v48, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v49, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v50, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v51, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v52, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v53, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v54, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v55, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v64, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB34_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB34_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v1, vcc_lo, v1, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v2, null, 0, v2, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v3, vcc_lo, v3, 3
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v4, null, 0, v4, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v5, vcc_lo, v5, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v6, null, 0, v6, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v9, vcc_lo, v9, 3
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v10, null, 0, v10, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v11, vcc_lo, v11, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v12, null, 0, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v13, vcc_lo, v13, 3
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v14, null, 0, v14, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v15, vcc_lo, v15, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v16, null, 0, v16, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v7, vcc_lo, v7, 3
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v8, null, 0, v8, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 24, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v33, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v35, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v37, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v38, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v48, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v49, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v50, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v51, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v52, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v53, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v54, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v55, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v64, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB34_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v17.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v64.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v1.h, v18.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v55.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v54.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.h, 8, v53.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v17.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v2.h, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v19.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v21.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v53, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v52.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v24
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v3.h, v20.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v25.l, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v54, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v51.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v5.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v22.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v48.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v25
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.l, 8, v37.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v17.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v50.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v49.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v49, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v50, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v54, v24
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v25, v22
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v39.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v7.h, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v20.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v38.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v19.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.l, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v10.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v35.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v53, v23
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v8.h, v20.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v36.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v11.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v34.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v21, v19
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v33.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.l, 8, v31.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v30.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v32.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.l, 8, v18.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v19.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v19.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v35, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v24, v22
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v20, v34
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v12.h, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v13.h, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v14.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v29.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v15.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.l, 0xff, v16.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v16.l, 0xff, v16.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v26.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v14.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v15.l, v15.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v16.l, v16.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v51, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v25, v23
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v23, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v14
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v49, v50
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v51, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v35, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v21, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v22, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v19, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v23, v24
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, v25, v16
+; GFX11-TRUE16-NEXT:    s_clause 0x3
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[9:12], off offset:32
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[13:16], off offset:48
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v8i64_to_v64i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB34_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 24, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 16, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 16, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v49, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v50, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v51, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v52, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v53, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v54, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v55, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v64, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v65, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v66, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v67, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v68, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v69, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v70, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v81, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v82, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v85, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v86, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB34_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB34_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v1, vcc_lo, v1, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v2, null, 0, v2, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v3, vcc_lo, v3, 3
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v4, null, 0, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v5, vcc_lo, v5, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v6, null, 0, v6, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v9, vcc_lo, v9, 3
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v10, null, 0, v10, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v11, vcc_lo, v11, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v12, null, 0, v12, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v13, vcc_lo, v13, 3
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v14, null, 0, v14, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v15, vcc_lo, v15, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v16, null, 0, v16, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v7, vcc_lo, v7, 3
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v8, null, 0, v8, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 24, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 16, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 16, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v49, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v50, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v51, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v52, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v53, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v54, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v55, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v64, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v65, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v66, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v67, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v68, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v69, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v70, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v81, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v82, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v85, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v86, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB34_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v96, 0xff, v96
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v86, 0xff, v86
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v87
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v96, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v85, 8, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v86, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v84, 8, v84
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v83, 0xff, v83
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v82
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v80, 8, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v71, 8, v71
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v81
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v70, 0xff, v70
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v84
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v83, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v80
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v71
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v70, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v66
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v65
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v64
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v55
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v53, 8, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v23, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v25, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v52
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v51
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v50
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v49, 8, v49
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v48, 8, v48
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v39, 0xff, v39
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v23, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v25, v49
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v48
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v39, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v38
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v37
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v18, 8, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v69, 8, v69
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v68, 0xff, v68
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v67, 8, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v23, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v29
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v26, 8, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v69
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v67, v68, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v23, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v25, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v67, 16, v67
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v21
+; GFX11-FAKE16-NEXT:    s_clause 0x3
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[9:12], off offset:32
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[13:16], off offset:48
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -18981,471 +21641,950 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v64i8_to_v8i64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v38, v14 :: v_dual_mov_b32 v37, v12
-; GFX11-NEXT:    v_dual_mov_b32 v36, v10 :: v_dual_mov_b32 v35, v8
-; GFX11-NEXT:    v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v4
-; GFX11-NEXT:    v_dual_mov_b32 v32, v2 :: v_dual_mov_b32 v31, v0
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v0, off, s32 offset:128
-; GFX11-NEXT:    scratch_load_u16 v39, off, s32 offset:124
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32 offset:120
-; GFX11-NEXT:    scratch_load_u16 v48, off, s32 offset:116
-; GFX11-NEXT:    scratch_load_u16 v4, off, s32 offset:112
-; GFX11-NEXT:    scratch_load_u16 v49, off, s32 offset:108
-; GFX11-NEXT:    scratch_load_u16 v6, off, s32 offset:104
-; GFX11-NEXT:    scratch_load_u16 v50, off, s32 offset:100
-; GFX11-NEXT:    scratch_load_u16 v8, off, s32 offset:96
-; GFX11-NEXT:    scratch_load_u16 v51, off, s32 offset:92
-; GFX11-NEXT:    scratch_load_u16 v10, off, s32 offset:88
-; GFX11-NEXT:    scratch_load_b32 v12, off, s32 offset:132
-; GFX11-NEXT:    scratch_load_u16 v14, off, s32
-; GFX11-NEXT:    scratch_load_u16 v65, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_u16 v66, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_u16 v67, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_u16 v83, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_u16 v84, off, s32 offset:40
-; GFX11-NEXT:    scratch_load_u16 v85, off, s32 offset:48
-; GFX11-NEXT:    scratch_load_u16 v128, off, s32 offset:56
-; GFX11-NEXT:    scratch_load_u16 v129, off, s32 offset:64
-; GFX11-NEXT:    scratch_load_u16 v130, off, s32 offset:72
-; GFX11-NEXT:    scratch_load_u16 v131, off, s32 offset:80
-; GFX11-NEXT:    scratch_load_u16 v52, off, s32 offset:84
-; GFX11-NEXT:    scratch_load_u16 v53, off, s32 offset:76
-; GFX11-NEXT:    scratch_load_u16 v54, off, s32 offset:68
-; GFX11-NEXT:    scratch_load_u16 v55, off, s32 offset:60
-; GFX11-NEXT:    scratch_load_u16 v64, off, s32 offset:52
-; GFX11-NEXT:    scratch_load_u16 v68, off, s32 offset:44
-; GFX11-NEXT:    scratch_load_u16 v69, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_u16 v70, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_u16 v71, off, s32 offset:20
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_u16 v80, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_u16 v86, off, s32 offset:4
-; GFX11-NEXT:    v_lshlrev_b16 v118, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v119, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v117, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v114, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v115, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v116, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v113, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v100, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v101, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v102, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v103, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v112, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v87, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v96, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v97, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(33)
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(31)
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(29)
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v4
-; GFX11-NEXT:    s_waitcnt vmcnt(27)
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v6
-; GFX11-NEXT:    s_waitcnt vmcnt(25)
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v8
-; GFX11-NEXT:    s_waitcnt vmcnt(22)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v12
-; GFX11-NEXT:    s_waitcnt vmcnt(21)
-; GFX11-NEXT:    v_lshlrev_b16 v98, 8, v14
-; GFX11-NEXT:    s_waitcnt vmcnt(20)
-; GFX11-NEXT:    v_lshlrev_b16 v99, 8, v65
-; GFX11-NEXT:    s_waitcnt vmcnt(19)
-; GFX11-NEXT:    v_lshlrev_b16 v81, 8, v66
-; GFX11-NEXT:    s_waitcnt vmcnt(18)
-; GFX11-NEXT:    v_lshlrev_b16 v82, 8, v67
-; GFX11-NEXT:    s_waitcnt vmcnt(17)
-; GFX11-NEXT:    v_lshlrev_b16 v83, 8, v83
-; GFX11-NEXT:    s_waitcnt vmcnt(16)
-; GFX11-NEXT:    v_lshlrev_b16 v84, 8, v84
-; GFX11-NEXT:    s_waitcnt vmcnt(15)
-; GFX11-NEXT:    v_lshlrev_b16 v85, 8, v85
-; GFX11-NEXT:    s_waitcnt vmcnt(14)
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v128
-; GFX11-NEXT:    s_waitcnt vmcnt(13)
-; GFX11-NEXT:    v_lshlrev_b16 v29, 8, v129
-; GFX11-NEXT:    s_waitcnt vmcnt(12)
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v130
-; GFX11-NEXT:    s_waitcnt vmcnt(11)
-; GFX11-NEXT:    v_lshlrev_b16 v66, 8, v131
-; GFX11-NEXT:    v_lshlrev_b16 v67, 8, v10
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB35_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB35_4
-; GFX11-NEXT:  .LBB35_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB35_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v31
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v37
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v34
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v118
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v119
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v35
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v36
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v18
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v22
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v117
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v6, v113
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v114
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v115
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v116
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v101
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v1
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v38
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v102
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v103
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v112
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v100
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v11
-; GFX11-NEXT:    v_or_b32_e32 v4, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v5, v9, v10
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v24
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v26
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v30
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v86
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v80
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v71
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v70
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v69
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v68
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v87
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v96
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v97
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v98
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v99
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v81
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v82
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v83
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v84
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v85
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v7
-; GFX11-NEXT:    v_or_b32_e32 v7, v8, v9
-; GFX11-NEXT:    v_or_b32_e32 v8, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v9, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v10, v14, v15
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v64
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v55
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v54
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v53
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v52
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v51
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v50
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v49
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v48
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v39
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v27
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v29
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v65
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v66
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v67
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v17, v18, v19
-; GFX11-NEXT:    v_or_b32_e32 v18, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v19, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v20, v24, v25
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff, v19
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v12, v13, v14
-; GFX11-NEXT:    v_or_b32_e32 v13, v15, v16
-; GFX11-NEXT:    v_or_b32_e32 v14, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v15, v19, v20
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr118
-; GFX11-NEXT:    ; implicit-def: $vgpr119
-; GFX11-NEXT:    ; implicit-def: $vgpr117
-; GFX11-NEXT:    ; implicit-def: $vgpr114
-; GFX11-NEXT:    ; implicit-def: $vgpr115
-; GFX11-NEXT:    ; implicit-def: $vgpr116
-; GFX11-NEXT:    ; implicit-def: $vgpr113
-; GFX11-NEXT:    ; implicit-def: $vgpr100
-; GFX11-NEXT:    ; implicit-def: $vgpr101
-; GFX11-NEXT:    ; implicit-def: $vgpr102
-; GFX11-NEXT:    ; implicit-def: $vgpr103
-; GFX11-NEXT:    ; implicit-def: $vgpr112
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr97
-; GFX11-NEXT:    ; implicit-def: $vgpr98
-; GFX11-NEXT:    ; implicit-def: $vgpr99
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr67
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB35_2
-; GFX11-NEXT:  .LBB35_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v31, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v32, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v33, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v34, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v35, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v5, v36, 3
-; GFX11-NEXT:    v_add_nc_u16 v6, v37, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_or_b32_e32 v0, v118, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v119, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_or_b32_e32 v2, v117, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v114, v3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_or_b32_e32 v4, v115, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v116, v5
-; GFX11-NEXT:    v_or_b32_e32 v6, v113, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, v16, 3
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v5
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v6, v38, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v18, 3
-; GFX11-NEXT:    v_add_nc_u16 v9, v20, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, v22, 3
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v7, v101, v7
-; GFX11-NEXT:    v_or_b32_e32 v6, v100, v6
-; GFX11-NEXT:    v_or_b32_e32 v8, v102, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v103, v9
-; GFX11-NEXT:    v_or_b32_e32 v10, v112, v10
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v10
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v3, v4
-; GFX11-NEXT:    v_or_b32_e32 v3, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v4, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v5, v9, v10
-; GFX11-NEXT:    v_add_nc_u16 v6, v24, 3
-; GFX11-NEXT:    v_add_nc_u16 v7, v26, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v28, 3
-; GFX11-NEXT:    v_add_nc_u16 v9, v30, 3
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_nc_u16 v10, v86, 3
-; GFX11-NEXT:    v_add_nc_u16 v11, v80, 3
-; GFX11-NEXT:    v_add_nc_u16 v12, v71, 3
-; GFX11-NEXT:    v_add_nc_u16 v13, v70, 3
-; GFX11-NEXT:    v_add_nc_u16 v14, v69, 3
-; GFX11-NEXT:    v_add_nc_u16 v15, v68, 3
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX11-NEXT:    v_or_b32_e32 v6, v87, v6
-; GFX11-NEXT:    v_or_b32_e32 v7, v96, v7
-; GFX11-NEXT:    v_or_b32_e32 v8, v97, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v98, v9
-; GFX11-NEXT:    v_or_b32_e32 v10, v99, v10
-; GFX11-NEXT:    v_or_b32_e32 v11, v81, v11
-; GFX11-NEXT:    v_or_b32_e32 v12, v82, v12
-; GFX11-NEXT:    v_or_b32_e32 v13, v83, v13
-; GFX11-NEXT:    v_or_b32_e32 v14, v84, v14
-; GFX11-NEXT:    v_or_b32_e32 v15, v85, v15
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v10
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v11
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v12
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v13
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v14
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v15
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v7
-; GFX11-NEXT:    v_or_b32_e32 v7, v8, v9
-; GFX11-NEXT:    v_or_b32_e32 v8, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v9, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v10, v14, v15
-; GFX11-NEXT:    v_add_nc_u16 v11, v64, 3
-; GFX11-NEXT:    v_add_nc_u16 v12, v55, 3
-; GFX11-NEXT:    v_add_nc_u16 v13, v54, 3
-; GFX11-NEXT:    v_add_nc_u16 v14, v53, 3
-; GFX11-NEXT:    v_add_nc_u16 v15, v52, 3
-; GFX11-NEXT:    v_add_nc_u16 v16, v51, 3
-; GFX11-NEXT:    v_add_nc_u16 v18, v50, 3
-; GFX11-NEXT:    v_add_nc_u16 v20, v49, 3
-; GFX11-NEXT:    v_add_nc_u16 v22, v48, 3
-; GFX11-NEXT:    v_add_nc_u16 v24, v39, 3
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v18
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v24
-; GFX11-NEXT:    v_or_b32_e32 v11, v27, v11
-; GFX11-NEXT:    v_or_b32_e32 v12, v29, v12
-; GFX11-NEXT:    v_or_b32_e32 v13, v65, v13
-; GFX11-NEXT:    v_or_b32_e32 v14, v66, v14
-; GFX11-NEXT:    v_or_b32_e32 v15, v67, v15
-; GFX11-NEXT:    v_or_b32_e32 v16, v17, v16
-; GFX11-NEXT:    v_or_b32_e32 v17, v19, v18
-; GFX11-NEXT:    v_or_b32_e32 v18, v21, v20
-; GFX11-NEXT:    v_or_b32_e32 v19, v23, v22
-; GFX11-NEXT:    v_or_b32_e32 v20, v25, v24
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v11
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v12
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v13
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v14
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v15
-; GFX11-NEXT:    v_add_nc_u16 v16, 0x300, v16
-; GFX11-NEXT:    v_add_nc_u16 v17, 0x300, v17
-; GFX11-NEXT:    v_add_nc_u16 v18, 0x300, v18
-; GFX11-NEXT:    v_add_nc_u16 v19, 0x300, v19
-; GFX11-NEXT:    v_add_nc_u16 v20, 0x300, v20
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff, v19
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v12, v13, v14
-; GFX11-NEXT:    v_or_b32_e32 v13, v15, v16
-; GFX11-NEXT:    v_or_b32_e32 v14, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v15, v19, v20
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v64i8_to_v8i64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v64, off, s32 offset:128
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32 offset:124
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v64, off, s32 offset:120
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v31, off, s32 offset:116
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v65, off, s32 offset:112
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v32, off, s32 offset:108
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v65, off, s32 offset:104
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v32, off, s32 offset:100
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v66, off, s32 offset:96
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v33, off, s32 offset:92
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v66, off, s32 offset:88
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v82, off, s32 offset:132
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v67, off, s32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v67, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v68, off, s32 offset:16
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v68, off, s32 offset:24
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v69, off, s32 offset:32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v69, off, s32 offset:40
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v70, off, s32 offset:48
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v70, off, s32 offset:56
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v71, off, s32 offset:64
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v71, off, s32 offset:72
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v80, off, s32 offset:80
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v33, off, s32 offset:84
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v34, off, s32 offset:76
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v34, off, s32 offset:68
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v35, off, s32 offset:60
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v35, off, s32 offset:52
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v36, off, s32 offset:44
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v36, off, s32 offset:36
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v37, off, s32 offset:28
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v37, off, s32 offset:20
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v38, off, s32 offset:12
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v38, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v80.h, v29.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v81.l, v27.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.l, v22.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.h, v20.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.h, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.l, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.h, v14.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v49.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v49.h, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v50.l, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v54.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v54.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v52.h, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v51.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v52.l, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v51.l, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v50.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v30.h, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v39.l, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v39.h, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v48.l, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v48.h, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.h, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v24.h, 8, v81.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v25.l, 8, v80.h
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.l, 8, v64.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v64.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(29)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.l, 8, v65.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(27)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v65.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(25)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.l, 8, v66.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(23)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v66.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(21)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v25.h, 8, v67.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(20)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v26.h, 8, v67.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(19)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.l, 8, v68.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(18)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.h, 8, v68.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(17)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v22.l, 8, v69.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(16)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v22.h, 8, v69.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(15)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.l, 8, v70.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(14)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v70.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(13)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.l, 8, v71.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(12)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v71.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(11)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.l, 8, v80.l
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v82
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB35_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB35_4
+; GFX11-TRUE16-NEXT:  .LBB35_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB35_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v55.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v55.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v53.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v53.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v49.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v54.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v0.h, v54.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v50.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v49.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v50.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v0.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v52.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.h, v51.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v0.h, v52.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v2.h, v51.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v6, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v1
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v29.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v29.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v28.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v27.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v27.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v30.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v1.h, v39.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v39.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v2.h, v48.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v48.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v6, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v8, v9
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v26.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v30.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v38.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v25.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v10, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v6.h, v24.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v7.h, v25.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v26.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v38.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v37.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v4, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v10
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v37.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v36.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v36.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v21.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v22.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v6.h, v21.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v7.h, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v11, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v13, v14
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v35.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v34.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v8
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.h, 0xff, v35.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v34.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v19.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v20.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v15, v21
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v10, v23
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v11.h, v19.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v12.h, v20.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v11
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v23, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v33.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.h, 0xff, v32.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v32.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v31.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v31.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v9, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v15
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v16.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v11.h, v16.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v17.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v12.h, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v18.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v11
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v19, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v21, v22
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v23, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v14, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v15, v18
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB35_2
+; GFX11-TRUE16-NEXT:  .LBB35_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v55.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v55.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v53.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v53.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v50.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v49.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v49.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v54.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v54.h, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v52.h, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v51.h, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v52.l, v2.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v51.l, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v50.h, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v5, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v29.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v29.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v2.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v28.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v27.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v27.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v30.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v39.l, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v39.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v48.l, v2.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v6, v7
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, v24.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v28.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v48.h, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, v26.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, v30.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v23.h, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v25.l, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v8, v9
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, v38.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v24.h, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v25.h, v7.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v6.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v10, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, v38.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v37.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v26.h, v8.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v6.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.l, 0x300, v7.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, v37.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, v36.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v21.l, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v22.l, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v4, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v10
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, v36.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v21.h, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v22.h, v7.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v6.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v6.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.l, 0x300, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v11, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v13, v14
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, v35.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, v34.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, v33.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v23.l, v8.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.h, v35.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.h, v34.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v11.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.h, 0xff, v11.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v18.h, v11.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v19.h, v12.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v20.h, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v8
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.h, v19.l, v11.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.h, v20.l, v12.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, 0x300, v11.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, 0x300, v12.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, 0x300, v13.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v15, v21
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v10, v23
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, 0x300, v11.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.l, 0x300, v12.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v11
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v23, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, v33.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.h, v32.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, v32.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.h, v31.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, v31.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v11.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.h, 0xff, v11.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v16.l, v11.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.h, v16.h, v11.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v17.l, v12.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.h, v17.h, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v18.l, v13.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v9, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v15
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, 0x300, v11.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, 0x300, v11.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, 0x300, v12.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.l, 0x300, v12.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, 0x300, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v11
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v19, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v21, v22
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v23, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v14, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v15, v18
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v8i64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v38, v14 :: v_dual_mov_b32 v37, v12
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v36, v10 :: v_dual_mov_b32 v35, v8
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v32, v2 :: v_dual_mov_b32 v31, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v0, off, s32 offset:128
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v39, off, s32 offset:124
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32 offset:120
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v48, off, s32 offset:116
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v4, off, s32 offset:112
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v49, off, s32 offset:108
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v6, off, s32 offset:104
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v50, off, s32 offset:100
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v8, off, s32 offset:96
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v51, off, s32 offset:92
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v10, off, s32 offset:88
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v12, off, s32 offset:132
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v14, off, s32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v65, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v66, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v67, off, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v83, off, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v84, off, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v85, off, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v128, off, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v129, off, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v130, off, s32 offset:72
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v131, off, s32 offset:80
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v52, off, s32 offset:84
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v53, off, s32 offset:76
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v54, off, s32 offset:68
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v55, off, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v64, off, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v68, off, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v69, off, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v70, off, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v71, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v80, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v86, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v118, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v119, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v117, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v114, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v115, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v116, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v113, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v100, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v101, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v102, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v103, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v112, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v87, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v96, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v97, 8, v29
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(29)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(27)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v6
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(25)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v8
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(22)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v12
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(21)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v98, 8, v14
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(20)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v99, 8, v65
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(19)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v81, 8, v66
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(18)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v82, 8, v67
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(17)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v83, 8, v83
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(16)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v84, 8, v84
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(15)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v85, 8, v85
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(14)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v128
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(13)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v29, 8, v129
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(12)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v130
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(11)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v66, 8, v131
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v67, 8, v10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB35_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB35_4
+; GFX11-FAKE16-NEXT:  .LBB35_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB35_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v37
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v118
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v119
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v117
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v6, v113
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v114
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v115
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v116
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v101
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v38
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v102
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v103
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v112
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v100
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v9, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v30
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v86
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v71
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v70
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v69
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v68
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v87
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v96
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v97
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v98
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v99
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v81
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v82
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v83
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v84
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v8, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v14, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v64
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v53
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v52
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v51
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v50
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v49
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v48
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v66
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v18, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v24, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v13, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v15, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v19, v20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB35_2
+; GFX11-FAKE16-NEXT:  .LBB35_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v31, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v32, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v33, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v34, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v35, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v36, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v37, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v118, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v119, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v117, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v114, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v115, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v116, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v113, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v16, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v38, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v18, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v20, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v22, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v101, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v100, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v102, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v103, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v112, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v3, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v9, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v24, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v26, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v28, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v30, 3
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v86, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, v80, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v71, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v70, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v69, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, v68, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v87, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v96, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v97, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v98, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v99, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v81, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v82, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v83, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v84, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v85, v15
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v13
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, 0x300, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v8, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v14, v15
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, v64, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v55, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v54, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v53, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, v52, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, v51, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, v50, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, v49, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, v48, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v24, v39, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v27, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v29, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v65, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v66, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v67, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v17, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v19, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v21, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v23, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v25, v24
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v13
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, 0x300, v15
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, 0x300, v16
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, 0x300, v17
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, 0x300, v18
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, 0x300, v19
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, 0x300, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v13, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v15, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v19, v20
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -21645,295 +24784,581 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v32bf16_to_v8f64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v16
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB41_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v15
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
-; GFX11-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v21, v17, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v18, v16, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v19, 0x400000, v16
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_bfe_u32 v23, v14, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-NEXT:    v_add3_u32 v21, v21, v17, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v18, v18, v16, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v16, v18, v19, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v19, v23, v14, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-NEXT:    v_or_b32_e32 v18, 0x400000, v17
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-NEXT:    v_bfe_u32 v20, v15, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v15
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v20, v20, v15, 0x7fff
-; GFX11-NEXT:    v_dual_cndmask_b32 v15, v20, v22 :: v_dual_lshlrev_b32 v20, 16, v13
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v15, v15, v16, 0x7060302
-; GFX11-NEXT:    v_dual_cndmask_b32 v17, v21, v18 :: v_dual_add_f32 v18, 0x40c00000, v20
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v16, v18, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v18
-; GFX11-NEXT:    v_add3_u32 v16, v16, v18, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v14
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_cndmask_b32 v14, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v12
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_perm_b32 v14, v14, v17, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v17, v13, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_cndmask_b32 v16, v16, v20
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-NEXT:    v_add3_u32 v17, v17, v13, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v22, v19, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v19
-; GFX11-NEXT:    v_cndmask_b32_e32 v13, v17, v21, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v11
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v17, v22, v19, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-NEXT:    v_perm_b32 v13, v13, v16, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v19, 0x40c00000, v21
-; GFX11-NEXT:    v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v16, v19, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v19
-; GFX11-NEXT:    v_add3_u32 v16, v16, v19, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-NEXT:    v_bfe_u32 v18, v12, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v12
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v18, v18, v12, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v12, v18, v22, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v12, v12, v17, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v17, v11, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-NEXT:    v_add3_u32 v17, v17, v11, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v22, v18, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v19, v10, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v16, v16, v20, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v19, v19, v10, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v11, v17, v21, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v17, v22, v18, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v10
-; GFX11-NEXT:    v_perm_b32 v11, v11, v16, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    v_dual_cndmask_b32 v10, v19, v22 :: v_dual_lshlrev_b32 v21, 16, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_lshlrev_b32 v19, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-NEXT:    v_perm_b32 v10, v10, v17, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v16, v18, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v18
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_add_f32 v8, 0x40c00000, v8
-; GFX11-NEXT:    v_add3_u32 v16, v16, v18, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v22, v19, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v18, v8, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v9, 0x40c00000, v9
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v19
-; GFX11-NEXT:    v_add3_u32 v18, v18, v8, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v17, v9, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v9
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    v_add3_u32 v17, v17, v9, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v9, v17, v21, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v17, v22, v19, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v8
-; GFX11-NEXT:    v_perm_b32 v9, v9, v16, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-NEXT:    v_cndmask_b32_e32 v8, v18, v22, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v8, v8, v17, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_add_f32 v19, 0x40c00000, v21
-; GFX11-NEXT:    v_bfe_u32 v22, v18, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v16, v19, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v19
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-NEXT:    v_add3_u32 v16, v16, v19, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-NEXT:    v_bfe_u32 v19, v6, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v7, 0x40c00000, v7
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v18
-; GFX11-NEXT:    v_add3_u32 v19, v19, v6, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v17, v7, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v7
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    v_add3_u32 v17, v17, v7, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v7, v17, v21, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v17, v22, v18, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v5
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v6
-; GFX11-NEXT:    v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_cndmask_b32 v17, v17, v20
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v20, v18, 16, 1
-; GFX11-NEXT:    v_dual_cndmask_b32 v6, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT:    v_perm_b32 v7, v7, v16, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v6, v6, v17, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v17, 0x40c00000, v19
-; GFX11-NEXT:    v_add3_u32 v19, v20, v18, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v18
-; GFX11-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-NEXT:    v_bfe_u32 v22, v17, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v18, v19, v20, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v19, 0x400000, v17
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v16, v5, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v5
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    v_add3_u32 v16, v16, v5, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v5, v16, v21, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v16, v22, v17, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-NEXT:    v_perm_b32 v5, v5, v18, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v18, v4, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v16, v16, v19, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v19, 0x400000, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    v_add3_u32 v18, v18, v4, 0x7fff
-; GFX11-NEXT:    v_dual_add_f32 v17, 0x40c00000, v20 :: v_dual_lshlrev_b32 v20, 16, v2
-; GFX11-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v4, v18, v19, vcc_lo
-; GFX11-NEXT:    v_bfe_u32 v21, v17, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v18, 0x40c00000, v20
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v17
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-NEXT:    v_perm_b32 v4, v4, v16, 0x7060302
-; GFX11-NEXT:    v_add3_u32 v19, v21, v17, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v21, v3, 16, 1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT:    v_bfe_u32 v22, v18, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v23, 0x400000, v18
-; GFX11-NEXT:    v_cndmask_b32_e32 v17, v19, v20, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v19, v21, v3, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v3
-; GFX11-NEXT:    v_add3_u32 v21, v22, v18, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v1
-; GFX11-NEXT:    v_bfe_u32 v24, v2, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v19, v20, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v19, 0x40c00000, v22
-; GFX11-NEXT:    v_add3_u32 v20, v24, v2, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v3, v3, v17, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v18, v21, v23, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v2
-; GFX11-NEXT:    v_bfe_u32 v22, v19, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_dual_cndmask_b32 v2, v20, v21 :: v_dual_lshlrev_b32 v23, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_add3_u32 v21, v22, v19, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v19
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    v_add_f32_e32 v20, 0x40c00000, v23
-; GFX11-NEXT:    v_perm_b32 v2, v2, v18, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v19, v21, v22 :: v_dual_add_f32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_bfe_u32 v24, v20, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v25, 0x400000, v20
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v21, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v26, 0x400000, v0
-; GFX11-NEXT:    v_add3_u32 v24, v24, v20, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v21, v21, v0, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v23, v1, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_add3_u32 v22, v23, v1, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v23, 0x400000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v22, v23, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-NEXT:    v_perm_b32 v1, v1, v19, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v20, v24, v25, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v21, v26, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v0, v0, v20, 0x7060302
-; GFX11-NEXT:  .LBB41_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v32bf16_to_v8f64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v16
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB41_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff0000, v15
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v15, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v15
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v20, v20, v15, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v15, v20, v22 :: v_dual_add_f32 v16, 0x40c00000, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v15.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v16, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v16
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v19, v16, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v16, v19, v21 :: v_dual_and_b32 v17, 0xffff0000, v14
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_lshlrev_b32 v14, 16, v14
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v15, 0xffff, v15, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v23, v17, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, 0x400000, v17
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v25, v14, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v26, 0x400000, v14
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT:    v_add3_u32 v20, v23, v17, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v22, v25, v14, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v14, v22, v26, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v17, v20, v24 :: v_dual_and_b32 v18, 0xffff0000, v13
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_lshlrev_b32 v13, 16, v13
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v14.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v18, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v18
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v13, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, 0x400000, v13
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v14, 0xffff, v14, v17
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v19, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v16, v16, v13, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v13, v16, v20 :: v_dual_and_b32 v20, 0xffff0000, v11
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff0000, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v16, v17, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_lshlrev_b32 v12, 16, v12
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, 0x400000, v20
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v13, 0xffff, v13, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v19
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v18, v12, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v12
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v18, v18, v12, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v12, v18, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v21, v11, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v18, v20, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v21, v11, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v17, v17, v22, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v11
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT:    v_add3_u32 v18, v18, v20, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff0000, v10
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v11, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v22
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v12, 0xffff, v12, v17
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v18, v18, v23, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v19
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v11, 0xffff, v11, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v18, 0xffff0000, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v20, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_lshlrev_b32 v10, 16, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v18
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v10, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, 0x400000, v10
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v16, v16, v10, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v10, v16, v20, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v9, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff0000, v8
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v16, v17, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v18, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v19, v9, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v9
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v9, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v20, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, 0x400000, v20
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v17, v17, v22 :: v_dual_and_b32 v22, 0xffff0000, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT:    v_add3_u32 v18, v19, v20, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v9, 0xffff, v9, v17
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v7, 0x40c00000, v7 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v21, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v21, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v22
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v10, 0xffff, v10, v16
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v18, v18, v23 :: v_dual_and_b32 v23, 0xffff0000, v4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v19, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v16, v16, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v19
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v8, 0xffff, v8, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v18, 0xffff0000, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v20, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v7, v16, v20
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff0000, v5
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v6, 16, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v18
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v16, v17, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v18, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v19, v6, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v6
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v20, 0x40c00000, v20 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v20, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v21, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v7, 0xffff, v7, v16
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v18, v19, v20, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v21, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v17, v17, v22, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v20
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v6, 0xffff, v6, v17
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v4, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v23
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v18, v18, v22, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v16, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v19
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v5, 0xffff, v5, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v18, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_add3_u32 v16, v16, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v17, v20, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_add_f32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v16, v16, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v18, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v18
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v20, v20, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v23, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v4.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v20, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    v_add3_u32 v18, v23, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, 0x400000, v19
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v21, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v17, v17, v22 :: v_dual_and_b32 v22, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v21, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v4, 0xffff, v4, v16
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v21, 0x40c00000, v22 :: v_dual_cndmask_b32 v18, v18, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v0
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, 0x400000, v21
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v3, 0xffff, v3, v17
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v19, v20, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v22
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v22, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v25, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v21, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v23, v20, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v22, v22, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v27, 0x400000, v20
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v19, v21, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v23, v23, v20, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v22, v25, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v26, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v25, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v20, v23, v27, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT:    v_add3_u32 v22, v26, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v2, v18
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.l, v20.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v19, v19, v24, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v19
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v22, v25, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v20, v0
+; GFX11-TRUE16-NEXT:  .LBB41_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v32bf16_to_v8f64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v16
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB41_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v17, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v18, v16, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, 0x400000, v16
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v23, v14, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v18, v18, v16, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v18, v19, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v23, v14, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, 0x400000, v17
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v20, v15, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v15
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v20, v20, v15, 0x7fff
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v15, v20, v22 :: v_dual_lshlrev_b32 v20, 16, v13
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v15, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v17, v21, v18 :: v_dual_add_f32 v18, 0x40c00000, v20
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v14
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v14, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v12
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v14, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v17, v13, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_cndmask_b32 v16, v16, v20
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v17, v13, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v19, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v19
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v13, v17, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v22, v19, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v13, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v21
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v17, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v19, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v19
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v19, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v18, v12, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v12
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v18, v18, v12, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v18, v22, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v12, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v17, v11, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v17, v11, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v19, v10, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v16, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v19, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v17, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v22, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v10
+; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v11, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v17, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v19, v22 :: v_dual_lshlrev_b32 v21, 16, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_lshlrev_b32 v19, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v10, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v19, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v18, v8, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v19
+; GFX11-FAKE16-NEXT:    v_add3_u32 v18, v18, v8, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v17, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v17, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v17, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v22, v19, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v8
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v9, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v17, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v18, v22, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v8, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_add_f32 v19, 0x40c00000, v21
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v18, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v19, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v19
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v19, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v19, v6, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v7, 0x40c00000, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v19, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v17, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v17, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v17, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v17, v22, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v5
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_cndmask_b32 v17, v17, v20
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v20, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v6, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v6, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v17, 0x40c00000, v19
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v20, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v17, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v19, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, 0x400000, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v16, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v5
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v16, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v16, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v16, v22, v17, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v5, v18, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v18, v4, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v16, v19, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    v_add3_u32 v18, v18, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v17, 0x40c00000, v20 :: v_dual_lshlrev_b32 v20, 16, v2
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v18, v19, vcc_lo
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v17, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v18, 0x40c00000, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v17
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v4, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v19, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v21, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v22, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v24, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v19, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v22
+; GFX11-FAKE16-NEXT:    v_add3_u32 v20, v24, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v3, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v21, v23, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v19, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v20, v21 :: v_dual_lshlrev_b32 v23, 16, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v22, v19, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v19
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v23
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v18, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v19, v21, v22 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v24, v20, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, 0x400000, v20
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v24, v24, v20, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v21, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v23, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v22, v23, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, 0x400000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v22, v23, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v19, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v20, v24, v25, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v21, v26, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v20, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB41_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -23002,324 +26427,598 @@ define <64 x i8> @bitcast_v8f64_to_v64i8(<8 x double> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v8f64_to_v64i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v17
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr67
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB42_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
-; GFX11-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
-; GFX11-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 8, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 8, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 24, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 8, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 16, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 8, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v49, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v51, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v52, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v53, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v54, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v64, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v66, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v67, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v68, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v69, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v71, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v80, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v81, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v82, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v83, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v84, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v85, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v86, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v87, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v96, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
-; GFX11-NEXT:  .LBB42_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB42_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_f64 v[15:16], v[15:16], 1.0
-; GFX11-NEXT:    v_add_f64 v[13:14], v[13:14], 1.0
-; GFX11-NEXT:    v_add_f64 v[11:12], v[11:12], 1.0
-; GFX11-NEXT:    v_add_f64 v[9:10], v[9:10], 1.0
-; GFX11-NEXT:    v_add_f64 v[7:8], v[7:8], 1.0
-; GFX11-NEXT:    v_add_f64 v[5:6], v[5:6], 1.0
-; GFX11-NEXT:    v_add_f64 v[3:4], v[3:4], 1.0
-; GFX11-NEXT:    v_add_f64 v[1:2], v[1:2], 1.0
-; GFX11-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
-; GFX11-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
-; GFX11-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 8, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 8, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 24, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 8, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 16, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 8, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v49, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v51, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v52, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v53, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v54, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v64, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v66, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v67, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v68, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v69, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v71, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v80, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v81, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v82, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v83, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v84, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v85, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v86, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v87, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v96, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
-; GFX11-NEXT:  .LBB42_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v25
-; GFX11-NEXT:    v_and_b32_e32 v96, 0xff, v96
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v24
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v86, 0xff, v86
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v25
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v87
-; GFX11-NEXT:    v_or_b32_e32 v24, v96, v24
-; GFX11-NEXT:    v_lshlrev_b16 v85, 8, v85
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v25
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT:    v_or_b32_e32 v25, v86, v85
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_lshlrev_b16 v84, 8, v84
-; GFX11-NEXT:    v_and_b32_e32 v83, 0xff, v83
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v24
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v82
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v80, 8, v80
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_lshlrev_b16 v71, 8, v71
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v24
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v81
-; GFX11-NEXT:    v_and_b32_e32 v70, 0xff, v70
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v22
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v84
-; GFX11-NEXT:    v_or_b32_e32 v23, v83, v23
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v80
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v71
-; GFX11-NEXT:    v_or_b32_e32 v22, v70, v22
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v24
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v23
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v25
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v22
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v66
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v65
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v21
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v64
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v55
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v54
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v53
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v22
-; GFX11-NEXT:    v_or_b32_e32 v21, v23, v21
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v24
-; GFX11-NEXT:    v_or_b32_e32 v22, v25, v54
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v52
-; GFX11-NEXT:    v_lshlrev_b16 v20, 8, v20
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v51
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v50
-; GFX11-NEXT:    v_lshlrev_b16 v49, 8, v49
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_lshlrev_b16 v48, 8, v48
-; GFX11-NEXT:    v_and_b32_e32 v39, 0xff, v39
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v19
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v53
-; GFX11-NEXT:    v_or_b32_e32 v20, v23, v20
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v24
-; GFX11-NEXT:    v_or_b32_e32 v23, v25, v49
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v48
-; GFX11-NEXT:    v_or_b32_e32 v19, v39, v19
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v21
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v22
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v20
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v23
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v19
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v38
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v37
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v36
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v35
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v34
-; GFX11-NEXT:    v_lshlrev_b16 v18, 8, v18
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v33
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_lshlrev_b16 v69, 8, v69
-; GFX11-NEXT:    v_and_b32_e32 v68, 0xff, v68
-; GFX11-NEXT:    v_lshlrev_b16 v67, 8, v67
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v19
-; GFX11-NEXT:    v_or_b32_e32 v19, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v22
-; GFX11-NEXT:    v_or_b32_e32 v18, v23, v18
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v24
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v32
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v31
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v30
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v29
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v17
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v28
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v27
-; GFX11-NEXT:    v_lshlrev_b16 v26, 8, v26
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v69
-; GFX11-NEXT:    v_or_b32_e32 v67, v68, v67
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v22
-; GFX11-NEXT:    v_or_b32_e32 v17, v23, v17
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v24
-; GFX11-NEXT:    v_or_b32_e32 v21, v25, v26
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v67, 16, v67
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v67
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v19
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v18
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v20
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v17
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v21
-; GFX11-NEXT:    s_clause 0x3
-; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off
-; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
-; GFX11-NEXT:    scratch_store_b128 v0, v[9:12], off offset:32
-; GFX11-NEXT:    scratch_store_b128 v0, v[13:16], off offset:48
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v8f64_to_v64i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v17
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB42_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 24, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v33, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v35, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v37, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v38, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v48, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v49, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v50, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v51, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v52, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v53, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v54, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v55, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v64, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB42_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB42_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_f64 v[15:16], v[15:16], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[13:14], v[13:14], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[11:12], v[11:12], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[9:10], v[9:10], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[7:8], v[7:8], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[5:6], v[5:6], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[3:4], v[3:4], 1.0
+; GFX11-TRUE16-NEXT:    v_add_f64 v[1:2], v[1:2], 1.0
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 24, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v33, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v35, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v37, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v38, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v48, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v49, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v50, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v51, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v52, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v53, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v54, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v55, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v64, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB42_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v17.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v64.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v1.h, v18.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v55.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v54.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.h, 8, v53.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v17.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v2.h, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v19.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v21.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v53, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v52.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v24
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v3.h, v20.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v25.l, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v54, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v51.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v5.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v22.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v48.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v25
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.l, 8, v37.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v17.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v50.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v49.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v49, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v50, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v54, v24
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v25, v22
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v39.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v7.h, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v20.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v38.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v19.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.l, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v10.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v35.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v53, v23
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v8.h, v20.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v36.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v11.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v34.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v21, v19
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v33.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.l, 8, v31.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v30.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v32.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.l, 8, v18.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v19.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v19.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v35, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v24, v22
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v20, v34
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v12.h, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v13.h, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v14.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v29.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v15.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.l, 0xff, v16.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v16.l, 0xff, v16.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v26.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v14.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v15.l, v15.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v16.l, v16.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v51, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v25, v23
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v23, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v14
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v49, v50
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v51, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v35, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v21, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v22, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v19, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v23, v24
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, v25, v16
+; GFX11-TRUE16-NEXT:    s_clause 0x3
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[9:12], off offset:32
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[13:16], off offset:48
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v8f64_to_v64i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB42_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 24, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 16, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 16, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v49, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v50, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v51, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v52, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v53, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v54, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v55, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v64, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v65, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v66, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v67, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v68, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v69, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v70, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v81, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v82, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v85, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v86, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB42_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB42_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_f64 v[15:16], v[15:16], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[13:14], v[13:14], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[11:12], v[11:12], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[9:10], v[9:10], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[7:8], v[7:8], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[5:6], v[5:6], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[3:4], v[3:4], 1.0
+; GFX11-FAKE16-NEXT:    v_add_f64 v[1:2], v[1:2], 1.0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 24, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 16, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 16, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v49, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v50, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v51, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v52, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v53, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v54, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v55, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v64, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v65, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v66, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v67, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v68, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v69, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v70, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v81, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v82, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v85, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v86, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB42_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v96, 0xff, v96
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v86, 0xff, v86
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v87
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v96, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v85, 8, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v86, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v84, 8, v84
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v83, 0xff, v83
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v82
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v80, 8, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v71, 8, v71
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v81
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v70, 0xff, v70
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v84
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v83, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v80
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v71
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v70, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v66
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v65
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v64
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v55
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v53, 8, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v23, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v25, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v52
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v51
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v50
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v49, 8, v49
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v48, 8, v48
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v39, 0xff, v39
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v23, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v25, v49
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v48
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v39, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v38
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v37
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v18, 8, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v69, 8, v69
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v68, 0xff, v68
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v67, 8, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v23, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v29
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v26, 8, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v69
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v67, v68, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v23, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v25, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v67, 16, v67
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v21
+; GFX11-FAKE16-NEXT:    s_clause 0x3
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[9:12], off offset:32
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[13:16], off offset:48
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -24846,471 +28545,950 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v64i8_to_v8f64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v38, v14 :: v_dual_mov_b32 v37, v12
-; GFX11-NEXT:    v_dual_mov_b32 v36, v10 :: v_dual_mov_b32 v35, v8
-; GFX11-NEXT:    v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v4
-; GFX11-NEXT:    v_dual_mov_b32 v32, v2 :: v_dual_mov_b32 v31, v0
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v0, off, s32 offset:128
-; GFX11-NEXT:    scratch_load_u16 v39, off, s32 offset:124
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32 offset:120
-; GFX11-NEXT:    scratch_load_u16 v48, off, s32 offset:116
-; GFX11-NEXT:    scratch_load_u16 v4, off, s32 offset:112
-; GFX11-NEXT:    scratch_load_u16 v49, off, s32 offset:108
-; GFX11-NEXT:    scratch_load_u16 v6, off, s32 offset:104
-; GFX11-NEXT:    scratch_load_u16 v50, off, s32 offset:100
-; GFX11-NEXT:    scratch_load_u16 v8, off, s32 offset:96
-; GFX11-NEXT:    scratch_load_u16 v51, off, s32 offset:92
-; GFX11-NEXT:    scratch_load_u16 v10, off, s32 offset:88
-; GFX11-NEXT:    scratch_load_b32 v12, off, s32 offset:132
-; GFX11-NEXT:    scratch_load_u16 v14, off, s32
-; GFX11-NEXT:    scratch_load_u16 v65, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_u16 v66, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_u16 v67, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_u16 v83, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_u16 v84, off, s32 offset:40
-; GFX11-NEXT:    scratch_load_u16 v85, off, s32 offset:48
-; GFX11-NEXT:    scratch_load_u16 v128, off, s32 offset:56
-; GFX11-NEXT:    scratch_load_u16 v129, off, s32 offset:64
-; GFX11-NEXT:    scratch_load_u16 v130, off, s32 offset:72
-; GFX11-NEXT:    scratch_load_u16 v131, off, s32 offset:80
-; GFX11-NEXT:    scratch_load_u16 v52, off, s32 offset:84
-; GFX11-NEXT:    scratch_load_u16 v53, off, s32 offset:76
-; GFX11-NEXT:    scratch_load_u16 v54, off, s32 offset:68
-; GFX11-NEXT:    scratch_load_u16 v55, off, s32 offset:60
-; GFX11-NEXT:    scratch_load_u16 v64, off, s32 offset:52
-; GFX11-NEXT:    scratch_load_u16 v68, off, s32 offset:44
-; GFX11-NEXT:    scratch_load_u16 v69, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_u16 v70, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_u16 v71, off, s32 offset:20
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_u16 v80, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_u16 v86, off, s32 offset:4
-; GFX11-NEXT:    v_lshlrev_b16 v118, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v119, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v117, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v114, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v115, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v116, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v113, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v100, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v101, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v102, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v103, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v112, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v87, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v96, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v97, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(33)
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(31)
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(29)
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v4
-; GFX11-NEXT:    s_waitcnt vmcnt(27)
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v6
-; GFX11-NEXT:    s_waitcnt vmcnt(25)
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v8
-; GFX11-NEXT:    s_waitcnt vmcnt(22)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v12
-; GFX11-NEXT:    s_waitcnt vmcnt(21)
-; GFX11-NEXT:    v_lshlrev_b16 v98, 8, v14
-; GFX11-NEXT:    s_waitcnt vmcnt(20)
-; GFX11-NEXT:    v_lshlrev_b16 v99, 8, v65
-; GFX11-NEXT:    s_waitcnt vmcnt(19)
-; GFX11-NEXT:    v_lshlrev_b16 v81, 8, v66
-; GFX11-NEXT:    s_waitcnt vmcnt(18)
-; GFX11-NEXT:    v_lshlrev_b16 v82, 8, v67
-; GFX11-NEXT:    s_waitcnt vmcnt(17)
-; GFX11-NEXT:    v_lshlrev_b16 v83, 8, v83
-; GFX11-NEXT:    s_waitcnt vmcnt(16)
-; GFX11-NEXT:    v_lshlrev_b16 v84, 8, v84
-; GFX11-NEXT:    s_waitcnt vmcnt(15)
-; GFX11-NEXT:    v_lshlrev_b16 v85, 8, v85
-; GFX11-NEXT:    s_waitcnt vmcnt(14)
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v128
-; GFX11-NEXT:    s_waitcnt vmcnt(13)
-; GFX11-NEXT:    v_lshlrev_b16 v29, 8, v129
-; GFX11-NEXT:    s_waitcnt vmcnt(12)
-; GFX11-NEXT:    v_lshlrev_b16 v65, 8, v130
-; GFX11-NEXT:    s_waitcnt vmcnt(11)
-; GFX11-NEXT:    v_lshlrev_b16 v66, 8, v131
-; GFX11-NEXT:    v_lshlrev_b16 v67, 8, v10
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB43_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB43_4
-; GFX11-NEXT:  .LBB43_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB43_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v31
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v37
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v34
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v118
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v119
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v35
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v36
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v18
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v22
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v117
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v6, v113
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v114
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v115
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v116
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v101
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v1
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v38
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v102
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v103
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v112
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v100
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v11
-; GFX11-NEXT:    v_or_b32_e32 v4, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v5, v9, v10
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v24
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v26
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v30
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v86
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v80
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v71
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v70
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v69
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v68
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v87
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v96
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v97
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v98
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v99
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v81
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v82
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v83
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v84
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v85
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v7
-; GFX11-NEXT:    v_or_b32_e32 v7, v8, v9
-; GFX11-NEXT:    v_or_b32_e32 v8, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v9, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v10, v14, v15
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v64
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v55
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v54
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v53
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v52
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v51
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v50
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v49
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v48
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v39
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v27
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v29
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v65
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v66
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v67
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v17
-; GFX11-NEXT:    v_or_b32_e32 v17, v18, v19
-; GFX11-NEXT:    v_or_b32_e32 v18, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v19, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v20, v24, v25
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff, v19
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v12, v13, v14
-; GFX11-NEXT:    v_or_b32_e32 v13, v15, v16
-; GFX11-NEXT:    v_or_b32_e32 v14, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v15, v19, v20
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr118
-; GFX11-NEXT:    ; implicit-def: $vgpr119
-; GFX11-NEXT:    ; implicit-def: $vgpr117
-; GFX11-NEXT:    ; implicit-def: $vgpr114
-; GFX11-NEXT:    ; implicit-def: $vgpr115
-; GFX11-NEXT:    ; implicit-def: $vgpr116
-; GFX11-NEXT:    ; implicit-def: $vgpr113
-; GFX11-NEXT:    ; implicit-def: $vgpr100
-; GFX11-NEXT:    ; implicit-def: $vgpr101
-; GFX11-NEXT:    ; implicit-def: $vgpr102
-; GFX11-NEXT:    ; implicit-def: $vgpr103
-; GFX11-NEXT:    ; implicit-def: $vgpr112
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr97
-; GFX11-NEXT:    ; implicit-def: $vgpr98
-; GFX11-NEXT:    ; implicit-def: $vgpr99
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr67
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB43_2
-; GFX11-NEXT:  .LBB43_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v31, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v32, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v33, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v34, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v35, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v5, v36, 3
-; GFX11-NEXT:    v_add_nc_u16 v6, v37, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_or_b32_e32 v0, v118, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v119, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_or_b32_e32 v2, v117, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v114, v3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_or_b32_e32 v4, v115, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v116, v5
-; GFX11-NEXT:    v_or_b32_e32 v6, v113, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, v16, 3
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v5
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v6, v38, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v18, 3
-; GFX11-NEXT:    v_add_nc_u16 v9, v20, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, v22, 3
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v7, v101, v7
-; GFX11-NEXT:    v_or_b32_e32 v6, v100, v6
-; GFX11-NEXT:    v_or_b32_e32 v8, v102, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v103, v9
-; GFX11-NEXT:    v_or_b32_e32 v10, v112, v10
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v10
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v3, v4
-; GFX11-NEXT:    v_or_b32_e32 v3, v5, v6
-; GFX11-NEXT:    v_or_b32_e32 v4, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v5, v9, v10
-; GFX11-NEXT:    v_add_nc_u16 v6, v24, 3
-; GFX11-NEXT:    v_add_nc_u16 v7, v26, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v28, 3
-; GFX11-NEXT:    v_add_nc_u16 v9, v30, 3
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_nc_u16 v10, v86, 3
-; GFX11-NEXT:    v_add_nc_u16 v11, v80, 3
-; GFX11-NEXT:    v_add_nc_u16 v12, v71, 3
-; GFX11-NEXT:    v_add_nc_u16 v13, v70, 3
-; GFX11-NEXT:    v_add_nc_u16 v14, v69, 3
-; GFX11-NEXT:    v_add_nc_u16 v15, v68, 3
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX11-NEXT:    v_or_b32_e32 v6, v87, v6
-; GFX11-NEXT:    v_or_b32_e32 v7, v96, v7
-; GFX11-NEXT:    v_or_b32_e32 v8, v97, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v98, v9
-; GFX11-NEXT:    v_or_b32_e32 v10, v99, v10
-; GFX11-NEXT:    v_or_b32_e32 v11, v81, v11
-; GFX11-NEXT:    v_or_b32_e32 v12, v82, v12
-; GFX11-NEXT:    v_or_b32_e32 v13, v83, v13
-; GFX11-NEXT:    v_or_b32_e32 v14, v84, v14
-; GFX11-NEXT:    v_or_b32_e32 v15, v85, v15
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v6
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v7
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v8
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v9
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v10
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v11
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v12
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v13
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v14
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v15
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v7
-; GFX11-NEXT:    v_or_b32_e32 v7, v8, v9
-; GFX11-NEXT:    v_or_b32_e32 v8, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v9, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v10, v14, v15
-; GFX11-NEXT:    v_add_nc_u16 v11, v64, 3
-; GFX11-NEXT:    v_add_nc_u16 v12, v55, 3
-; GFX11-NEXT:    v_add_nc_u16 v13, v54, 3
-; GFX11-NEXT:    v_add_nc_u16 v14, v53, 3
-; GFX11-NEXT:    v_add_nc_u16 v15, v52, 3
-; GFX11-NEXT:    v_add_nc_u16 v16, v51, 3
-; GFX11-NEXT:    v_add_nc_u16 v18, v50, 3
-; GFX11-NEXT:    v_add_nc_u16 v20, v49, 3
-; GFX11-NEXT:    v_add_nc_u16 v22, v48, 3
-; GFX11-NEXT:    v_add_nc_u16 v24, v39, 3
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v18
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v24
-; GFX11-NEXT:    v_or_b32_e32 v11, v27, v11
-; GFX11-NEXT:    v_or_b32_e32 v12, v29, v12
-; GFX11-NEXT:    v_or_b32_e32 v13, v65, v13
-; GFX11-NEXT:    v_or_b32_e32 v14, v66, v14
-; GFX11-NEXT:    v_or_b32_e32 v15, v67, v15
-; GFX11-NEXT:    v_or_b32_e32 v16, v17, v16
-; GFX11-NEXT:    v_or_b32_e32 v17, v19, v18
-; GFX11-NEXT:    v_or_b32_e32 v18, v21, v20
-; GFX11-NEXT:    v_or_b32_e32 v19, v23, v22
-; GFX11-NEXT:    v_or_b32_e32 v20, v25, v24
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v11
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v12
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v13
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v14
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v15
-; GFX11-NEXT:    v_add_nc_u16 v16, 0x300, v16
-; GFX11-NEXT:    v_add_nc_u16 v17, 0x300, v17
-; GFX11-NEXT:    v_add_nc_u16 v18, 0x300, v18
-; GFX11-NEXT:    v_add_nc_u16 v19, 0x300, v19
-; GFX11-NEXT:    v_add_nc_u16 v20, 0x300, v20
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xffff, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xffff, v19
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v12, v13, v14
-; GFX11-NEXT:    v_or_b32_e32 v13, v15, v16
-; GFX11-NEXT:    v_or_b32_e32 v14, v17, v18
-; GFX11-NEXT:    v_or_b32_e32 v15, v19, v20
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v64i8_to_v8f64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v64, off, s32 offset:128
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32 offset:124
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v64, off, s32 offset:120
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v31, off, s32 offset:116
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v65, off, s32 offset:112
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v32, off, s32 offset:108
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v65, off, s32 offset:104
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v32, off, s32 offset:100
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v66, off, s32 offset:96
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v33, off, s32 offset:92
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v66, off, s32 offset:88
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v82, off, s32 offset:132
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v67, off, s32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v67, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v68, off, s32 offset:16
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v68, off, s32 offset:24
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v69, off, s32 offset:32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v69, off, s32 offset:40
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v70, off, s32 offset:48
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v70, off, s32 offset:56
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v71, off, s32 offset:64
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v71, off, s32 offset:72
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v80, off, s32 offset:80
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v33, off, s32 offset:84
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v34, off, s32 offset:76
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v34, off, s32 offset:68
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v35, off, s32 offset:60
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v35, off, s32 offset:52
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v36, off, s32 offset:44
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v36, off, s32 offset:36
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v37, off, s32 offset:28
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v37, off, s32 offset:20
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v38, off, s32 offset:12
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v38, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v80.h, v29.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v81.l, v27.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.l, v22.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.h, v20.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.h, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.l, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.h, v14.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v49.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v49.h, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v50.l, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v54.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v54.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v52.h, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v51.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v52.l, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v51.l, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v50.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v30.h, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v39.l, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v39.h, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v48.l, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v48.h, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.h, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v24.h, 8, v81.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v25.l, 8, v80.h
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.l, 8, v64.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v64.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(29)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.l, 8, v65.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(27)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v65.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(25)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.l, 8, v66.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(23)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v66.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(21)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v25.h, 8, v67.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(20)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v26.h, 8, v67.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(19)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.l, 8, v68.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(18)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.h, 8, v68.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(17)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v22.l, 8, v69.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(16)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v22.h, 8, v69.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(15)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.l, 8, v70.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(14)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v70.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(13)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.l, 8, v71.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(12)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v71.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(11)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.l, 8, v80.l
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v82
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB43_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB43_4
+; GFX11-TRUE16-NEXT:  .LBB43_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB43_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v55.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v55.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v53.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v53.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v49.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v54.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v0.h, v54.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v50.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v49.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v50.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v0.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v52.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.h, v51.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v0.h, v52.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v2.h, v51.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v6, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v1
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v29.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v29.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v28.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v27.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v27.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v30.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v1.h, v39.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v39.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v2.h, v48.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v48.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v6, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v8, v9
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v26.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v30.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v38.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v25.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v10, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v6.h, v24.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v7.h, v25.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v26.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v38.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v37.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v4, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v10
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v37.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v36.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v36.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v21.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v22.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v6.h, v21.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v7.h, v22.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v11, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v13, v14
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v35.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v34.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v8
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.h, 0xff, v35.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v34.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v19.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v20.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v15, v21
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v10, v23
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v11.h, v19.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v12.h, v20.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v11
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v23, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v33.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.h, 0xff, v32.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v32.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v31.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v31.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v9, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v15
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v16.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v11.h, v16.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v17.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v12.h, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v18.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v11
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v19, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v21, v22
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v23, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v14, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v15, v18
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB43_2
+; GFX11-TRUE16-NEXT:  .LBB43_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v55.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v55.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v53.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v53.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v50.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v49.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v49.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v54.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v54.h, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v52.h, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v51.h, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v52.l, v2.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v51.l, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v50.h, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v5, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v29.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v29.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v2.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v28.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v27.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v27.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v30.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v39.l, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v39.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v48.l, v2.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v6, v7
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, v24.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v28.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v48.h, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, v26.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, v30.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v23.h, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v25.l, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v8, v9
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, v38.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v24.h, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v25.h, v7.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v6.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v10, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, v38.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, v37.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v26.h, v8.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v6.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.l, 0x300, v7.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, v37.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, v36.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v21.l, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v22.l, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v4, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v10
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, v36.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v21.h, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v22.h, v7.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v6.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v6.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.l, 0x300, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v11, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v13, v14
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, v35.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, v34.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, v33.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v23.l, v8.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.h, v35.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.h, v34.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v11.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.h, 0xff, v11.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v18.h, v11.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v19.h, v12.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v20.h, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v8
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.h, v19.l, v11.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.h, v20.l, v12.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, 0x300, v11.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, 0x300, v12.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, 0x300, v13.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v15, v21
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v10, v23
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, 0x300, v11.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.l, 0x300, v12.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v11
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v23, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, v33.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.h, v32.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, v32.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.h, v31.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, v31.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v11.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.h, 0xff, v11.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v16.l, v11.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.h, v16.h, v11.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v17.l, v12.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.h, v17.h, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v18.l, v13.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v9, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v15
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, 0x300, v11.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, 0x300, v11.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, 0x300, v12.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.l, 0x300, v12.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, 0x300, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v11
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v19, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v21, v22
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v23, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v14, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v15, v18
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v8f64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v38, v14 :: v_dual_mov_b32 v37, v12
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v36, v10 :: v_dual_mov_b32 v35, v8
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v34, v6 :: v_dual_mov_b32 v33, v4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v32, v2 :: v_dual_mov_b32 v31, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v0, off, s32 offset:128
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v39, off, s32 offset:124
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32 offset:120
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v48, off, s32 offset:116
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v4, off, s32 offset:112
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v49, off, s32 offset:108
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v6, off, s32 offset:104
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v50, off, s32 offset:100
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v8, off, s32 offset:96
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v51, off, s32 offset:92
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v10, off, s32 offset:88
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v12, off, s32 offset:132
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v14, off, s32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v65, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v66, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v67, off, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v83, off, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v84, off, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v85, off, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v128, off, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v129, off, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v130, off, s32 offset:72
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v131, off, s32 offset:80
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v52, off, s32 offset:84
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v53, off, s32 offset:76
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v54, off, s32 offset:68
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v55, off, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v64, off, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v68, off, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v69, off, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v70, off, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v71, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v80, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v86, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v118, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v119, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v117, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v114, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v115, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v116, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v113, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v100, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v101, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v102, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v103, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v112, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v87, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v96, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v97, 8, v29
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(29)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(27)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v6
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(25)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v8
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(22)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v12
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(21)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v98, 8, v14
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(20)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v99, 8, v65
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(19)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v81, 8, v66
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(18)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v82, 8, v67
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(17)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v83, 8, v83
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(16)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v84, 8, v84
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(15)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v85, 8, v85
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(14)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v128
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(13)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v29, 8, v129
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(12)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v65, 8, v130
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(11)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v66, 8, v131
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v67, 8, v10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB43_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB43_4
+; GFX11-FAKE16-NEXT:  .LBB43_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB43_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v37
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v118
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v119
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v117
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v6, v113
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v114
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v115
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v116
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v101
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v38
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v102
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v103
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v112
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v100
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v9, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v30
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v86
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v71
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v70
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v69
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v68
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v87
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v96
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v97
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v98
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v99
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v81
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v82
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v83
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v84
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v8, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v14, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v64
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v53
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v52
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v51
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v50
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v49
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v48
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v65
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v66
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v18, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v24, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v13, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v15, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v19, v20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB43_2
+; GFX11-FAKE16-NEXT:  .LBB43_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v31, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v32, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v33, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v34, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v35, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v36, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v37, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v118, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v119, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v117, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v114, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v115, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v116, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v113, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v16, 3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v38, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v18, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v20, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v22, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v101, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v100, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v102, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v103, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v112, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v3, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v5, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v9, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v24, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, v26, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v28, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, v30, 3
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, v86, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, v80, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v71, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v70, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v69, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, v68, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v87, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v96, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v97, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v98, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v99, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v81, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v82, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v83, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v84, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v85, v15
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v13
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, 0x300, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v8, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v14, v15
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, v64, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, v55, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, v54, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, v53, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, v52, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, v51, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, v50, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, v49, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, v48, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v24, v39, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v27, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v29, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v65, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v66, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v67, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v17, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v19, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v21, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v23, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v25, v24
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v13
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, 0x300, v15
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, 0x300, v16
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, 0x300, v17
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, 0x300, v18
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, 0x300, v19
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, 0x300, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v13, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v15, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v17, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v19, v20
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -27227,267 +31405,563 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v32bf16_to_v32i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v16
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB47_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v26, 16, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v28, 16, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v30, 16, v11
-; GFX11-NEXT:    v_dual_add_f32 v24, 0x40c00000, v24 :: v_dual_lshlrev_b32 v25, 16, v6
-; GFX11-NEXT:    v_bfe_u32 v21, v17, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v19, v16, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v16
-; GFX11-NEXT:    v_add_f32_e32 v25, 0x40c00000, v25
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-NEXT:    v_add3_u32 v21, v21, v17, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v19, v19, v16, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT:    v_dual_add_f32 v26, 0x40c00000, v26 :: v_dual_lshlrev_b32 v27, 16, v8
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v16, v19, v22, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v19, 0x400000, v17
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v22, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-NEXT:    v_add_f32_e32 v27, 0x40c00000, v27
-; GFX11-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v29, 16, v10
-; GFX11-NEXT:    v_bfe_u32 v20, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v23, 0x400000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_add_f32_e32 v8, 0x40c00000, v8
-; GFX11-NEXT:    v_dual_add_f32 v28, 0x40c00000, v28 :: v_dual_add_f32 v29, 0x40c00000, v29
-; GFX11-NEXT:    v_add3_u32 v20, v20, v0, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-NEXT:    v_dual_add_f32 v30, 0x40c00000, v30 :: v_dual_lshlrev_b32 v31, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v0, v20, v23 :: v_dual_lshlrev_b32 v23, 16, v4
-; GFX11-NEXT:    v_bfe_u32 v20, v1, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT:    v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_add_f32 v23, 0x40c00000, v23
-; GFX11-NEXT:    v_perm_b32 v0, v0, v16, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v17, v21, v19, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v19, v20, v1, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v2
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT:    v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_add_f32 v31, 0x40c00000, v31
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v1, v19, v20 :: v_dual_add_f32 v18, 0x40c00000, v18
-; GFX11-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT:    v_add_f32_e32 v22, 0x40c00000, v22
-; GFX11-NEXT:    v_bfe_u32 v21, v18, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v18
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-NEXT:    v_or_b32_e32 v33, 0x400000, v31
-; GFX11-NEXT:    v_add3_u32 v19, v21, v18, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v21, v2, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v34, v12, 16, 1
-; GFX11-NEXT:    v_perm_b32 v1, v1, v17, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v18, v19, v20 :: v_dual_and_b32 v7, 0xffff0000, v7
-; GFX11-NEXT:    v_add3_u32 v19, v21, v2, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v2
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_bfe_u32 v21, v22, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-NEXT:    v_dual_cndmask_b32 v2, v19, v20 :: v_dual_and_b32 v11, 0xffff0000, v11
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v19, v21, v22, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v22
-; GFX11-NEXT:    v_bfe_u32 v21, v3, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-NEXT:    v_bfe_u32 v22, v23, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-NEXT:    v_perm_b32 v2, v2, v18, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-NEXT:    v_cndmask_b32_e32 v19, v19, v20, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v20, v21, v3, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v3
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_or_b32_e32 v32, 0x400000, v11
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v20, v21, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v20, v22, v23, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v23
-; GFX11-NEXT:    v_bfe_u32 v22, v4, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-NEXT:    v_bfe_u32 v23, v24, 16, 1
-; GFX11-NEXT:    v_perm_b32 v3, v3, v19, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v20, v20, v21, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v21, v22, v4, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v4, v21, v22, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v21, v23, v24, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v24
-; GFX11-NEXT:    v_bfe_u32 v23, v5, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-NEXT:    v_bfe_u32 v24, v25, 16, 1
-; GFX11-NEXT:    v_perm_b32 v4, v4, v20, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v21, v21, v22, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v22, v23, v5, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v23, 0x400000, v5
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v5, v22, v23, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v22, v24, v25, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v23, 0x400000, v25
-; GFX11-NEXT:    v_bfe_u32 v24, v6, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-NEXT:    v_bfe_u32 v25, v26, 16, 1
-; GFX11-NEXT:    v_perm_b32 v5, v5, v21, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v22, v22, v23, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v23, v24, v6, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v24, 0x400000, v6
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v6, v23, v24, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v23, v25, v26, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v24, 0x400000, v26
-; GFX11-NEXT:    v_bfe_u32 v25, v7, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-NEXT:    v_bfe_u32 v26, v27, 16, 1
-; GFX11-NEXT:    v_perm_b32 v6, v6, v22, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v23, v23, v24, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v24, v25, v7, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v25, 0x400000, v7
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v7, v24, v25, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v24, v26, v27, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v25, 0x400000, v27
-; GFX11-NEXT:    v_bfe_u32 v26, v8, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11-NEXT:    v_bfe_u32 v27, v28, 16, 1
-; GFX11-NEXT:    v_perm_b32 v7, v7, v23, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v24, v24, v25, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v25, v26, v8, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v26, 0x400000, v8
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v8, v25, v26, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v25, v27, v28, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v26, 0x400000, v28
-; GFX11-NEXT:    v_bfe_u32 v27, v9, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11-NEXT:    v_bfe_u32 v28, v29, 16, 1
-; GFX11-NEXT:    v_perm_b32 v8, v8, v24, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v25, v25, v26, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v26, v27, v9, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v27, 0x400000, v9
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v9, v26, v27, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v26, v28, v29, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v27, 0x400000, v29
-; GFX11-NEXT:    v_bfe_u32 v28, v10, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11-NEXT:    v_bfe_u32 v29, v30, 16, 1
-; GFX11-NEXT:    v_perm_b32 v9, v9, v25, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v26, v26, v27, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v27, v28, v10, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v28, 0x400000, v10
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v10, v27, v28, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v27, v29, v30, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v28, 0x400000, v30
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-NEXT:    v_bfe_u32 v30, v31, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v29, v11, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v27, v27, v28 :: v_dual_lshlrev_b32 v28, 16, v13
-; GFX11-NEXT:    v_add3_u32 v30, v30, v31, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-NEXT:    v_add3_u32 v31, v34, v12, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v28, 0x40c00000, v28
-; GFX11-NEXT:    v_add3_u32 v29, v29, v11, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v30, v30, v33, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v33, 0x400000, v12
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-NEXT:    v_bfe_u32 v35, v28, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v28
-; GFX11-NEXT:    v_cndmask_b32_e32 v12, v31, v33, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v34, v35, v28, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v35, 16, v14
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-NEXT:    v_bfe_u32 v37, v13, 16, 1
-; GFX11-NEXT:    v_perm_b32 v10, v10, v26, 0x7060302
-; GFX11-NEXT:    v_dual_add_f32 v31, 0x40c00000, v35 :: v_dual_cndmask_b32 v28, v34, v36
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v15
-; GFX11-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-NEXT:    v_add3_u32 v33, v37, v13, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v35, v31, 16, 1
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v31
-; GFX11-NEXT:    v_bfe_u32 v38, v14, 16, 1
-; GFX11-NEXT:    v_add3_u32 v35, v35, v31, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-NEXT:    v_bfe_u32 v39, v34, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v48, 0x400000, v34
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v13
-; GFX11-NEXT:    v_cndmask_b32_e32 v31, v35, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v37, v38, v14, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v14
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-NEXT:    v_bfe_u32 v35, v15, 16, 1
-; GFX11-NEXT:    v_add3_u32 v39, v39, v34, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v49, 0x400000, v15
-; GFX11-NEXT:    v_cndmask_b32_e32 v14, v37, v38, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add3_u32 v35, v35, v15, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v14, v14, v31, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v34, v39, v48, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-NEXT:    v_cndmask_b32_e32 v15, v35, v49, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v15, v15, v34, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v13, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-NEXT:    v_perm_b32 v12, v12, v30, 0x7060302
-; GFX11-NEXT:    v_perm_b32 v13, v13, v28, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v11, v29, v32, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v11, v11, v27, 0x7060302
-; GFX11-NEXT:  .LBB47_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v32bf16_to_v32i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v16
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB47_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v16, 0x40c00000, v16
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v19, 0x40c00000, v1 :: v_dual_lshlrev_b32 v34, 16, v15
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v1, v16, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v16
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v23, v17, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v24, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT:    v_add3_u32 v1, v1, v16, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v25, 0x400000, v19
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v16, v1, v22 :: v_dual_and_b32 v15, 0xffff0000, v15
+; GFX11-TRUE16-NEXT:    v_add3_u32 v22, v23, v17, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v23, v24, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v34
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v15, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v48, 0x400000, v15
+; GFX11-TRUE16-NEXT:    v_add3_u32 v20, v20, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v16.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, 0x400000, v17
+; GFX11-TRUE16-NEXT:    v_add3_u32 v37, v37, v15, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v20, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v20, 0x40c00000, v2 :: v_dual_cndmask_b32 v19, v23, v25
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v22, v16, vcc_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v19.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_add_f32 v19, 0x40c00000, v19
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v20, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v21, v18, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v20
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, 0x400000, v18
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v20, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v21, v21, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, 0x400000, v19
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v17, v17, v22 :: v_dual_lshlrev_b32 v22, 16, v4
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    v_add3_u32 v20, v20, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v17.l, v17.h
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v18, v21, v23, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v21, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v21, v21, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v21, v23, vcc_lo
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v5
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v21, v22, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v25, 0x400000, v22
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v23, 0x40c00000, v23
+; GFX11-TRUE16-NEXT:    v_add3_u32 v21, v21, v22, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v19, v20, v24, vcc_lo
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v26, 0x400000, v23
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v19, 16, v19
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v4, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v3, v3, 16, v19
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v20, v20, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v20, v24, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v23, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v20, v20, v23, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v21, v21, v25 :: v_dual_add_f32 v24, 0x40c00000, v24
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v22, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v25, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_add3_u32 v22, v22, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v5, v22, v25 :: v_dual_and_b32 v6, 0xffff0000, v6
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v25, 16, v7
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v22, v24, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v27, 0x400000, v24
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v25, 0x40c00000, v25
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v23, v6, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v20, v20, v26, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v26, 0x400000, v6
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT:    v_add3_u32 v22, v22, v24, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v23, v23, v6, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v28, 0x400000, v25
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v20, 16, v20
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v6, v23, v26 :: v_dual_add_f32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v8
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v23, v25, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v24, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v26, 0x40c00000, v26
+; GFX11-TRUE16-NEXT:    v_add3_u32 v23, v23, v25, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v22, v22, v27, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v27, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_add3_u32 v24, v24, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v5, v5, 16, v20
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v20, 16, v21
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 16, v2
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v7, v24, v27, vcc_lo
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v27, 16, v9
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v24, v26, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v29, 0x400000, v26
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v27, 0x40c00000, v27
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v25, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v23, v23, v28, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v28, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    v_add3_u32 v24, v24, v26, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v25, v25, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v30, 0x400000, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v22, 16, v22
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v7.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v8, v25, v28 :: v_dual_add_f32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v10
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v25, v27, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v26, v9, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v28, 0x40c00000, v28
+; GFX11-TRUE16-NEXT:    v_add3_u32 v25, v25, v27, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v24, v24, v29, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v29, 0x400000, v9
+; GFX11-TRUE16-NEXT:    v_add3_u32 v26, v26, v9, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 16, v23
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v6, v6, 16, v22
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v22, 16, v1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v9, v26, v29, vcc_lo
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v29, 16, v11
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v26, v28, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v31, 0x400000, v28
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v29, 0x40c00000, v29
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v27, v10, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v25, v25, v30, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v30, 0x400000, v10
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT:    v_add3_u32 v26, v26, v28, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v27, v27, v10, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v32, 0x400000, v29
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v25
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v10, v27, v30 :: v_dual_add_f32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v12
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v27, v29, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v28, v11, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v30, 0x40c00000, v30
+; GFX11-TRUE16-NEXT:    v_add3_u32 v27, v27, v29, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v26, v26, v31, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v31, 0x400000, v11
+; GFX11-TRUE16-NEXT:    v_add3_u32 v28, v28, v11, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v9, v9, 16, v25
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v7, v7, 16, v23
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v11, v28, v31, vcc_lo
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v31, 16, v13
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v28, v30, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v33, 0x400000, v30
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v31, 0x40c00000, v31
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v29, v12, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v27, v27, v32, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v32, 0x400000, v12
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT:    v_add3_u32 v28, v28, v30, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v29, v29, v12, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 16, v27
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 16, v26
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v12, v29, v32 :: v_dual_add_f32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v14
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v29, v31, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v30, v13, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v35, 0x400000, v13
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v28, v28, v33, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v32, 0x40c00000, v32
+; GFX11-TRUE16-NEXT:    v_add3_u32 v30, v30, v13, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-TRUE16-NEXT:    v_add3_u32 v29, v29, v31, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v33, 0x400000, v31
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v32, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v13, v30, v35, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v34, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-TRUE16-NEXT:    v_add3_u32 v36, v36, v32, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v38, 0x400000, v32
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v34, 0x7fff
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 16, v28
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v30, v14, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v49, 0x400000, v14
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v11, v11, 16, v27
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v34, v35, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT:    v_add3_u32 v30, v30, v14, 0x7fff
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v12, v12, 16, v28
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v10, v10, 16, v26
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v8, v8, 16, v24
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v15, v37, v48, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v32
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v4, v4, 16, v20
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v2, v17, 16, v18
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v1, v16, 16, v21
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v15.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v36, v38, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 16, v34
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v0, v0, 16, v22
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v14, v30, v49, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.l, v13.h
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v15, v13, 16, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 16, v32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v14.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v29, v29, v33, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v14, v14, 16, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 16, v29
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v13, v30, 16, v29
+; GFX11-TRUE16-NEXT:  .LBB47_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v32bf16_to_v32i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v16
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB47_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v11
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v24, 0x40c00000, v24 :: v_dual_lshlrev_b32 v25, 16, v6
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v17, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v19, v16, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v16
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v25, 0x40c00000, v25
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v19, v16, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v26, 0x40c00000, v26 :: v_dual_lshlrev_b32 v27, 16, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v19, v22, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, 0x400000, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v22, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v27, 0x40c00000, v27
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v10
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v20, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v28, 0x40c00000, v28 :: v_dual_add_f32 v29, 0x40c00000, v29
+; GFX11-FAKE16-NEXT:    v_add3_u32 v20, v20, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v30, 0x40c00000, v30 :: v_dual_lshlrev_b32 v31, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v20, v23 :: v_dual_lshlrev_b32 v23, 16, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v20, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_add_f32 v23, 0x40c00000, v23
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v21, v19, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v20, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_add_f32 v31, 0x40c00000, v31
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v19, v20 :: v_dual_add_f32 v18, 0x40c00000, v18
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v33, 0x400000, v31
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v21, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v12, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v18, v19, v20 :: v_dual_and_b32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v21, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v22, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v19, v20 :: v_dual_and_b32 v11, 0xffff0000, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v21, v22, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v22
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v23, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v18, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v19, v19, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v20, v21, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v32, 0x400000, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v20, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v20, v22, v23, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v23
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v23, v24, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v3, v19, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v20, v20, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v22, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v21, v22, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v23, v24, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v24
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v23, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v24, v25, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v4, v20, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v21, v21, v22, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v22, v23, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, 0x400000, v5
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v22, v23, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v22, v24, v25, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, 0x400000, v25
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v24, v6, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v25, v26, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v5, v21, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v22, v22, v23, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v23, v24, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v23, v24, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v23, v25, v26, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, 0x400000, v26
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v25, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v26, v27, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v6, v22, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v23, v23, v24, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v24, v25, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v24, v25, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v24, v26, v27, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, 0x400000, v27
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v26, v8, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v27, v28, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v23, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v24, v24, v25, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v25, v26, v8, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, 0x400000, v8
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v25, v26, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v25, v27, v28, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, 0x400000, v28
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v27, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v28, v29, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v8, v24, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v25, v25, v26, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v26, v27, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v26, v27, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v26, v28, v29, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, 0x400000, v29
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v28, v10, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v29, v30, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v9, v25, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v26, v26, v27, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v27, v28, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, 0x400000, v10
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v27, v28, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v27, v29, v30, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, 0x400000, v30
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v30, v31, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v29, v11, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v27, v27, v28 :: v_dual_lshlrev_b32 v28, 16, v13
+; GFX11-FAKE16-NEXT:    v_add3_u32 v30, v30, v31, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11-FAKE16-NEXT:    v_add3_u32 v31, v34, v12, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v28, 0x40c00000, v28
+; GFX11-FAKE16-NEXT:    v_add3_u32 v29, v29, v11, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v30, v30, v33, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v33, 0x400000, v12
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v28, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v28
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v31, v33, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v35, v28, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v35, 16, v14
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v13, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v10, v26, 0x7060302
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v31, 0x40c00000, v35 :: v_dual_cndmask_b32 v28, v34, v36
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v15
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v37, v13, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v31, 16, 1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v31
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v14, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v31, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v39, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v48, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v13
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v31, v35, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v38, v14, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v14
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v15, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v39, v39, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v49, 0x400000, v15
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v14, v37, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v15, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v14, v31, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v34, v39, v48, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v15, v35, v49, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v15, v34, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v13, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v12, v30, 0x7060302
+; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v13, v28, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v29, v32, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v11, v27, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB47_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -29097,332 +33571,614 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v32i16_to_v64i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v17
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr67
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB48_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
-; GFX11-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
-; GFX11-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 8, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 8, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 24, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 8, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 16, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 8, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v49, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v51, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v52, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v53, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v54, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v64, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v66, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v67, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v68, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v69, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v71, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v80, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v81, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v82, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v83, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v84, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v85, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v86, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v87, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v96, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
-; GFX11-NEXT:  .LBB48_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB48_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
-; GFX11-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
-; GFX11-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
-; GFX11-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 8, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 8, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 24, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 8, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 16, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 8, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v49, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v51, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v52, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v53, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v54, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v64, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v66, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v67, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v68, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v69, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v71, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v80, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v81, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v82, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v83, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v84, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v85, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v86, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v87, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v96, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
-; GFX11-NEXT:  .LBB48_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v25
-; GFX11-NEXT:    v_and_b32_e32 v96, 0xff, v96
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v24
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v86, 0xff, v86
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v25
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v87
-; GFX11-NEXT:    v_or_b32_e32 v24, v96, v24
-; GFX11-NEXT:    v_lshlrev_b16 v85, 8, v85
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v25
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT:    v_or_b32_e32 v25, v86, v85
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_lshlrev_b16 v84, 8, v84
-; GFX11-NEXT:    v_and_b32_e32 v83, 0xff, v83
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v24
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v82
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v80, 8, v80
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_lshlrev_b16 v71, 8, v71
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v24
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v81
-; GFX11-NEXT:    v_and_b32_e32 v70, 0xff, v70
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v22
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v84
-; GFX11-NEXT:    v_or_b32_e32 v23, v83, v23
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v80
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v71
-; GFX11-NEXT:    v_or_b32_e32 v22, v70, v22
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v24
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v23
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v25
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v22
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v66
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v65
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v21
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v64
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v55
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v54
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v53
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v22
-; GFX11-NEXT:    v_or_b32_e32 v21, v23, v21
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v24
-; GFX11-NEXT:    v_or_b32_e32 v22, v25, v54
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v52
-; GFX11-NEXT:    v_lshlrev_b16 v20, 8, v20
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v51
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v50
-; GFX11-NEXT:    v_lshlrev_b16 v49, 8, v49
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_lshlrev_b16 v48, 8, v48
-; GFX11-NEXT:    v_and_b32_e32 v39, 0xff, v39
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v19
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v53
-; GFX11-NEXT:    v_or_b32_e32 v20, v23, v20
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v24
-; GFX11-NEXT:    v_or_b32_e32 v23, v25, v49
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v48
-; GFX11-NEXT:    v_or_b32_e32 v19, v39, v19
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v21
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v22
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v20
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v23
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v19
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v38
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v37
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v36
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v35
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v34
-; GFX11-NEXT:    v_lshlrev_b16 v18, 8, v18
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v33
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_lshlrev_b16 v69, 8, v69
-; GFX11-NEXT:    v_and_b32_e32 v68, 0xff, v68
-; GFX11-NEXT:    v_lshlrev_b16 v67, 8, v67
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v19
-; GFX11-NEXT:    v_or_b32_e32 v19, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v22
-; GFX11-NEXT:    v_or_b32_e32 v18, v23, v18
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v24
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v32
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v31
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v30
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v29
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v17
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v28
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v27
-; GFX11-NEXT:    v_lshlrev_b16 v26, 8, v26
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v69
-; GFX11-NEXT:    v_or_b32_e32 v67, v68, v67
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v22
-; GFX11-NEXT:    v_or_b32_e32 v17, v23, v17
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v24
-; GFX11-NEXT:    v_or_b32_e32 v21, v25, v26
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v67, 16, v67
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v67
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v19
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v18
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v20
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v17
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v21
-; GFX11-NEXT:    s_clause 0x3
-; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off
-; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
-; GFX11-NEXT:    scratch_store_b128 v0, v[9:12], off offset:32
-; GFX11-NEXT:    scratch_store_b128 v0, v[13:16], off offset:48
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v32i16_to_v64i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v17
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB48_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 24, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v33, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v35, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v37, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v38, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v48, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v49, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v50, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v51, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v52, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v53, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v54, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v55, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v64, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB48_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB48_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 24, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v33, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v35, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v37, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v38, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v48, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v49, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v50, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v51, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v52, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v53, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v54, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v55, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v64, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB48_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v17.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v64.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v1.h, v18.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v55.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v54.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.h, 8, v53.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v17.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v2.h, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v19.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v21.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v53, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v52.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v24
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v3.h, v20.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v25.l, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v54, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v51.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v5.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v22.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v48.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v25
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.l, 8, v37.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v17.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v50.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v49.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v49, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v50, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v54, v24
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v25, v22
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v39.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v7.h, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v20.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v38.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v19.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.l, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v10.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v35.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v53, v23
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v8.h, v20.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v36.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v11.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v34.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v21, v19
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v33.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.l, 8, v31.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v30.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v32.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.l, 8, v18.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v19.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v19.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v35, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v24, v22
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v20, v34
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v12.h, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v13.h, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v14.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v29.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v15.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.l, 0xff, v16.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v16.l, 0xff, v16.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v26.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v14.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v15.l, v15.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v16.l, v16.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v51, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v25, v23
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v23, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v14
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v49, v50
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v51, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v35, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v21, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v22, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v19, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v23, v24
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, v25, v16
+; GFX11-TRUE16-NEXT:    s_clause 0x3
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[9:12], off offset:32
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[13:16], off offset:48
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v32i16_to_v64i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB48_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 24, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 16, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 16, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v49, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v50, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v51, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v52, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v53, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v54, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v55, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v64, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v65, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v66, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v67, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v68, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v69, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v70, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v81, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v82, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v85, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v86, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB48_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB48_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 24, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 16, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 16, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v49, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v50, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v51, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v52, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v53, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v54, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v55, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v64, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v65, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v66, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v67, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v68, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v69, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v70, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v81, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v82, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v85, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v86, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB48_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v96, 0xff, v96
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v86, 0xff, v86
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v87
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v96, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v85, 8, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v86, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v84, 8, v84
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v83, 0xff, v83
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v82
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v80, 8, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v71, 8, v71
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v81
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v70, 0xff, v70
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v84
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v83, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v80
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v71
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v70, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v66
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v65
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v64
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v55
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v53, 8, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v23, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v25, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v52
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v51
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v50
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v49, 8, v49
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v48, 8, v48
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v39, 0xff, v39
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v23, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v25, v49
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v48
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v39, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v38
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v37
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v18, 8, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v69, 8, v69
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v68, 0xff, v68
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v67, 8, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v23, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v29
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v26, 8, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v69
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v67, v68, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v23, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v25, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v67, 16, v67
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v21
+; GFX11-FAKE16-NEXT:    s_clause 0x3
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[9:12], off offset:32
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[13:16], off offset:48
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -31132,409 +35888,795 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v64i8_to_v32i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v32, v14 :: v_dual_mov_b32 v31, v8
-; GFX11-NEXT:    v_dual_mov_b32 v34, v12 :: v_dual_mov_b32 v35, v10
-; GFX11-NEXT:    v_dual_mov_b32 v38, v6 :: v_dual_mov_b32 v33, v4
-; GFX11-NEXT:    v_dual_mov_b32 v37, v2 :: v_dual_mov_b32 v36, v0
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v0, off, s32 offset:128
-; GFX11-NEXT:    scratch_load_u16 v67, off, s32 offset:124
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32 offset:120
-; GFX11-NEXT:    scratch_load_u16 v70, off, s32 offset:116
-; GFX11-NEXT:    scratch_load_u16 v4, off, s32 offset:112
-; GFX11-NEXT:    scratch_load_u16 v66, off, s32 offset:108
-; GFX11-NEXT:    scratch_load_u16 v6, off, s32 offset:104
-; GFX11-NEXT:    scratch_load_u16 v69, off, s32 offset:100
-; GFX11-NEXT:    scratch_load_u16 v8, off, s32 offset:96
-; GFX11-NEXT:    scratch_load_u16 v64, off, s32 offset:92
-; GFX11-NEXT:    scratch_load_u16 v10, off, s32 offset:88
-; GFX11-NEXT:    scratch_load_b32 v12, off, s32 offset:132
-; GFX11-NEXT:    scratch_load_u16 v14, off, s32
-; GFX11-NEXT:    scratch_load_u16 v96, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_u16 v100, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_u16 v101, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_u16 v102, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_u16 v103, off, s32 offset:40
-; GFX11-NEXT:    scratch_load_u16 v113, off, s32 offset:48
-; GFX11-NEXT:    scratch_load_u16 v114, off, s32 offset:56
-; GFX11-NEXT:    scratch_load_u16 v115, off, s32 offset:64
-; GFX11-NEXT:    scratch_load_u16 v116, off, s32 offset:72
-; GFX11-NEXT:    scratch_load_u16 v117, off, s32 offset:80
-; GFX11-NEXT:    scratch_load_u16 v99, off, s32 offset:84
-; GFX11-NEXT:    scratch_load_u16 v85, off, s32 offset:76
-; GFX11-NEXT:    scratch_load_u16 v97, off, s32 offset:68
-; GFX11-NEXT:    scratch_load_u16 v82, off, s32 offset:60
-; GFX11-NEXT:    scratch_load_u16 v86, off, s32 offset:52
-; GFX11-NEXT:    scratch_load_u16 v84, off, s32 offset:44
-; GFX11-NEXT:    scratch_load_u16 v87, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_u16 v68, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_u16 v80, off, s32 offset:20
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_u16 v65, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_u16 v71, off, s32 offset:4
-; GFX11-NEXT:    v_lshlrev_b16 v50, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v51, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v49, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v48, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v52, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v83, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v81, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(33)
-; GFX11-NEXT:    v_lshlrev_b16 v119, 8, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(31)
-; GFX11-NEXT:    v_lshlrev_b16 v118, 8, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(22)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v12
-; GFX11-NEXT:    s_waitcnt vmcnt(21)
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v14
-; GFX11-NEXT:    s_waitcnt vmcnt(20)
-; GFX11-NEXT:    v_lshlrev_b16 v98, 8, v96
-; GFX11-NEXT:    s_waitcnt vmcnt(19)
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v100
-; GFX11-NEXT:    s_waitcnt vmcnt(18)
-; GFX11-NEXT:    v_lshlrev_b16 v96, 8, v101
-; GFX11-NEXT:    s_waitcnt vmcnt(17)
-; GFX11-NEXT:    v_lshlrev_b16 v29, 8, v102
-; GFX11-NEXT:    s_waitcnt vmcnt(16)
-; GFX11-NEXT:    v_lshlrev_b16 v112, 8, v103
-; GFX11-NEXT:    s_waitcnt vmcnt(15)
-; GFX11-NEXT:    v_lshlrev_b16 v103, 8, v113
-; GFX11-NEXT:    s_waitcnt vmcnt(14)
-; GFX11-NEXT:    v_lshlrev_b16 v101, 8, v114
-; GFX11-NEXT:    s_waitcnt vmcnt(13)
-; GFX11-NEXT:    v_lshlrev_b16 v100, 8, v115
-; GFX11-NEXT:    s_waitcnt vmcnt(12)
-; GFX11-NEXT:    v_lshlrev_b16 v114, 8, v116
-; GFX11-NEXT:    s_waitcnt vmcnt(11)
-; GFX11-NEXT:    v_lshlrev_b16 v102, 8, v117
-; GFX11-NEXT:    v_lshlrev_b16 v117, 8, v10
-; GFX11-NEXT:    v_lshlrev_b16 v113, 8, v8
-; GFX11-NEXT:    v_lshlrev_b16 v116, 8, v6
-; GFX11-NEXT:    v_lshlrev_b16 v115, 8, v4
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB49_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB49_4
-; GFX11-NEXT:  .LBB49_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB49_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v36
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v37
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v38
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v31
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v35
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v50
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v51
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v34
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v18
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    v_or_b32_e32 v1, v3, v39
-; GFX11-NEXT:    v_or_b32_e32 v3, v4, v54
-; GFX11-NEXT:    v_or_b32_e32 v4, v5, v48
-; GFX11-NEXT:    v_or_b32_e32 v5, v6, v55
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v22
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v49
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v53
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v52
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v17
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v83
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v81
-; GFX11-NEXT:    v_perm_b32 v1, v1, v2, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v2, v4, v3, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v3, v6, v5, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v4, v8, v7, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v5, v10, v9, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v24
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v26
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v30
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v71
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v65
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v80
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v68
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v87
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v84
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v21
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v19
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v27
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v23
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v98
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v25
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v96
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v29
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v112
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v103
-; GFX11-NEXT:    v_perm_b32 v6, v7, v6, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v7, v9, v8, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v8, v11, v10, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v9, v13, v12, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v10, v15, v14, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v86
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v82
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v97
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v85
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v99
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v64
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v69
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v66
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v70
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v67
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v101
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v100
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v114
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v102
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v117
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v113
-; GFX11-NEXT:    v_or_b32_e32 v17, v17, v116
-; GFX11-NEXT:    v_or_b32_e32 v18, v18, v115
-; GFX11-NEXT:    v_or_b32_e32 v19, v19, v118
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v119
-; GFX11-NEXT:    v_perm_b32 v11, v12, v11, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v12, v14, v13, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v13, v16, v15, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v14, v18, v17, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v15, v20, v19, 0x5040100
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr97
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr99
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr67
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr98
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr112
-; GFX11-NEXT:    ; implicit-def: $vgpr103
-; GFX11-NEXT:    ; implicit-def: $vgpr101
-; GFX11-NEXT:    ; implicit-def: $vgpr100
-; GFX11-NEXT:    ; implicit-def: $vgpr114
-; GFX11-NEXT:    ; implicit-def: $vgpr102
-; GFX11-NEXT:    ; implicit-def: $vgpr117
-; GFX11-NEXT:    ; implicit-def: $vgpr113
-; GFX11-NEXT:    ; implicit-def: $vgpr116
-; GFX11-NEXT:    ; implicit-def: $vgpr115
-; GFX11-NEXT:    ; implicit-def: $vgpr118
-; GFX11-NEXT:    ; implicit-def: $vgpr119
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB49_2
-; GFX11-NEXT:  .LBB49_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v70, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v67, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v69, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v66, 3
-; GFX11-NEXT:    v_add_nc_u16 v5, v64, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    s_waitcnt vmcnt(8)
-; GFX11-NEXT:    v_add_nc_u16 v6, v97, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v0, v118, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v119, v1
-; GFX11-NEXT:    v_add_nc_u16 v4, v99, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v64, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v0, v116, v2
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v5
-; GFX11-NEXT:    v_or_b32_e32 v2, v115, v3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v113, v1
-; GFX11-NEXT:    v_add_nc_u16 v66, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v1, v114, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v117, v4
-; GFX11-NEXT:    v_add_nc_u16 v2, v85, 3
-; GFX11-NEXT:    v_add_nc_u16 v67, 0x300, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(6)
-; GFX11-NEXT:    v_add_nc_u16 v0, v86, 3
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v82, 3
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v4
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(4)
-; GFX11-NEXT:    v_add_nc_u16 v3, v87, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v4, v84, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v102, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v0, v101, v0
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v1, v100, v1
-; GFX11-NEXT:    v_add_nc_u16 v69, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v112, v3
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v103, v4
-; GFX11-NEXT:    v_add_nc_u16 v70, 0x300, v1
-; GFX11-NEXT:    s_waitcnt vmcnt(2)
-; GFX11-NEXT:    v_add_nc_u16 v1, v80, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v68, 3
-; GFX11-NEXT:    v_add_nc_u16 v68, 0x300, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_nc_u16 v0, v71, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v3, v65, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v4, v28, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v96, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v29, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v0, v98, v0
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v25, v3
-; GFX11-NEXT:    v_add_nc_u16 v25, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v27, v4
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v30, 3
-; GFX11-NEXT:    v_add_nc_u16 v27, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v24, 3
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v26, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v3, v20, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v4, v22, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_or_b32_e32 v0, v23, v0
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v1, v21, v1
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v2, v19, v2
-; GFX11-NEXT:    v_add_nc_u16 v19, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v83, v3
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v81, v4
-; GFX11-NEXT:    v_add_nc_u16 v20, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v16, 3
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v34, 3
-; GFX11-NEXT:    v_add_nc_u16 v16, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v31, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, v18, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v4, v32, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v53, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v0, v55, v0
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v1, v54, v1
-; GFX11-NEXT:    v_add_nc_u16 v18, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v17, v3
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v52, v4
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v33, 3
-; GFX11-NEXT:    v_add_nc_u16 v17, v36, 3
-; GFX11-NEXT:    v_add_nc_u16 v21, v37, 3
-; GFX11-NEXT:    v_add_nc_u16 v22, v38, 3
-; GFX11-NEXT:    v_add_nc_u16 v23, v35, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v17
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v21
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v23
-; GFX11-NEXT:    v_or_b32_e32 v1, v49, v1
-; GFX11-NEXT:    v_or_b32_e32 v17, v50, v17
-; GFX11-NEXT:    v_or_b32_e32 v21, v51, v21
-; GFX11-NEXT:    v_or_b32_e32 v22, v39, v22
-; GFX11-NEXT:    v_or_b32_e32 v23, v48, v23
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v17, 0x300, v17
-; GFX11-NEXT:    v_add_nc_u16 v21, 0x300, v21
-; GFX11-NEXT:    v_add_nc_u16 v22, 0x300, v22
-; GFX11-NEXT:    v_add_nc_u16 v23, 0x300, v23
-; GFX11-NEXT:    v_add_nc_u16 v24, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v26, 0x300, v2
-; GFX11-NEXT:    v_perm_b32 v0, v21, v17, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v1, v22, v1, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v2, v23, v4, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v3, v24, v3, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v4, v26, v18, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v5, v16, v5, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v6, v20, v6, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v7, v19, v7, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v8, v27, v8, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v9, v25, v9, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v10, v68, v10, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v11, v70, v11, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v12, v69, v12, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v13, v67, v13, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v14, v66, v14, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v15, v64, v15, 0x5040100
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v64i8_to_v32i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v55, off, s32 offset:128
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v32, off, s32 offset:124
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v55, off, s32 offset:120
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v33, off, s32 offset:116
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v53, off, s32 offset:112
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v31, off, s32 offset:108
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v53, off, s32 offset:104
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v32, off, s32 offset:100
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v52, off, s32 offset:96
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32 offset:92
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v54, off, s32 offset:88
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v66, off, s32 offset:132
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v39, off, s32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v48, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v48, off, s32 offset:16
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v50, off, s32 offset:24
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v50, off, s32 offset:32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v51, off, s32 offset:40
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v52, off, s32 offset:48
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v54, off, s32 offset:56
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v64, off, s32 offset:64
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v64, off, s32 offset:72
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v65, off, s32 offset:80
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v38, off, s32 offset:84
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v36, off, s32 offset:76
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v38, off, s32 offset:68
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v35, off, s32 offset:60
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v37, off, s32 offset:52
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v36, off, s32 offset:44
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v37, off, s32 offset:36
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v34, off, s32 offset:28
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v34, off, s32 offset:20
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v33, off, s32 offset:12
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v35, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.h, v29.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.l, v27.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.h, v25.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v39.l, v23.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.h, v21.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v26.h, v19.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v25.h, v17.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.h, v22.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v24.h, v20.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.h, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v17.h, v14.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.h, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.l, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v17.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v18.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.l, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v27.l, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v22.l, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v27.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v25.l, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v25.h, 8, v25.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v26.h, 8, v26.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v30.h, 8, v30.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v39.l, 8, v39.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v28.h, 8, v28.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v29.l, 8, v29.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v49.l, 8, v29.h
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v55.h, 8, v55.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v55.l, 8, v55.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(29)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v53.h, 8, v53.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(27)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v53.l, 8, v53.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(25)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v52.h, 8, v52.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(23)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v54.h, 8, v54.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(21)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v29.h, 8, v39.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(20)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v49.h, 8, v48.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(19)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v39.h, 8, v48.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(18)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v48.l, 8, v50.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(17)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v48.h, 8, v50.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(16)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v51.h, 8, v51.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(15)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v52.l, 8, v52.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(14)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v50.l, 8, v54.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(13)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v50.h, 8, v64.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(12)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v54.l, 8, v64.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(11)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v51.l, 8, v65.l
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v66
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB49_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB49_4
+; GFX11-TRUE16-NEXT:  .LBB49_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB49_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v18.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v17.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v16.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v16.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v21.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v17.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v19.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v24.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v22.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v26.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v30.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v35.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v34.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.h, 0xff, v34.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v37.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.h, 0xff, v36.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v37.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.h, 0xff, v35.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v38.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v36.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v38.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v31.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v32.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.h, 0xff, v31.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.l, 0xff, v33.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.h, 0xff, v32.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v23.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v20.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v1.h, v20.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v27.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v2.h, v22.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v27.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v3.h, v25.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v25.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.h, v4.h, v26.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v30.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.h, v5.h, v39.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v28.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v6.h, v29.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v49.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v7.h, v29.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v49.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.h, v8.h, v39.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v48.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.h, v9.h, v48.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v51.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.h, v10.h, v52.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v50.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.h, v11.h, v50.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v54.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.h, v12.h, v51.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v54.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.h, v13.h, v52.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v53.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.h, v14.h, v53.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v15.l, v55.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.h, v15.h, v55.h
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB49_2
+; GFX11-TRUE16-NEXT:  .LBB49_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v33.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v32.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v32.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v31.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v31.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(8)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v38.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v55.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v55.h, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v38.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v53.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v53.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v35.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v52.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v54.l, v0.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v37.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v36.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v37.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v54.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v50.h, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v51.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v36.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v51.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v50.l, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v35.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v34.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v34.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v33.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v52.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v49.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v48.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v48.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v39.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.h, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v28.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v30.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v24.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v26.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v24.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v49.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v29.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v28.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v29.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v30.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v22.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v19.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v18.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v21.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v17.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v39.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v25.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v26.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v27.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v25.l, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v21.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v16.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v19.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v16.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v18.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v17.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v27.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v22.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v20.l, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v20.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.h, v23.l, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v23.h, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, 0x300, v16.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v16.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, 0x300, v17.l
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v32i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v32, v14 :: v_dual_mov_b32 v31, v8
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v34, v12 :: v_dual_mov_b32 v35, v10
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v38, v6 :: v_dual_mov_b32 v33, v4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v37, v2 :: v_dual_mov_b32 v36, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v0, off, s32 offset:128
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v67, off, s32 offset:124
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32 offset:120
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v70, off, s32 offset:116
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v4, off, s32 offset:112
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v66, off, s32 offset:108
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v6, off, s32 offset:104
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v69, off, s32 offset:100
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v8, off, s32 offset:96
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v64, off, s32 offset:92
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v10, off, s32 offset:88
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v12, off, s32 offset:132
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v14, off, s32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v96, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v100, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v101, off, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v102, off, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v103, off, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v113, off, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v114, off, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v115, off, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v116, off, s32 offset:72
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v117, off, s32 offset:80
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v99, off, s32 offset:84
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v85, off, s32 offset:76
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v97, off, s32 offset:68
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v82, off, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v86, off, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v84, off, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v87, off, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v68, off, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v80, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v65, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v71, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v50, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v51, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v49, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v48, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v52, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v53, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v83, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v81, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v29
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v119, 8, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v118, 8, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(22)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v12
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(21)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v14
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(20)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v98, 8, v96
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(19)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v100
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(18)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v96, 8, v101
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(17)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v29, 8, v102
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(16)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v112, 8, v103
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(15)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v103, 8, v113
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(14)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v101, 8, v114
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(13)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v100, 8, v115
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(12)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v114, 8, v116
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(11)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v102, 8, v117
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v117, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v113, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v116, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v115, 8, v4
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB49_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB49_4
+; GFX11-FAKE16-NEXT:  .LBB49_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB49_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v37
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v38
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v50
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v51
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v4, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v5, v48
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v49
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v52
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v83
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v81
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v4, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v6, v5, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v8, v7, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v10, v9, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v30
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v71
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v65
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v68
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v87
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v84
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v98
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v96
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v112
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v103
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v7, v6, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v9, v8, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v11, v10, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v13, v12, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v15, v14, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v86
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v82
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v97
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v99
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v64
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v69
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v66
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v70
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v101
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v100
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v114
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v102
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v117
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v113
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v17, v116
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v18, v115
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v19, v118
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v119
+; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v12, v11, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v14, v13, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v16, v15, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v18, v17, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v20, v19, 0x5040100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB49_2
+; GFX11-FAKE16-NEXT:  .LBB49_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v70, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v67, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v69, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v66, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v64, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(8)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v97, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v118, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v119, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v99, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v64, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v116, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v115, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v113, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v66, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v114, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v117, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v85, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v67, 0x300, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(6)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v86, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v82, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(4)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v87, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v84, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v102, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v101, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v100, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v69, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v112, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v103, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v70, 0x300, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v80, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v68, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v68, 0x300, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v71, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v65, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v28, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v96, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v29, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v98, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v25, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v25, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v27, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v30, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v27, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v24, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v26, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v20, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v22, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v23, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v21, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v19, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v83, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v81, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v16, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v34, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v31, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v18, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v32, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v53, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v55, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v54, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v17, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v52, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v33, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, v36, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, v37, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, v38, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v23, v35, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v49, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v50, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v51, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v39, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v48, v23
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, 0x300, v17
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, 0x300, v21
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, 0x300, v22
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v23, 0x300, v23
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v24, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v26, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v21, v17, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v22, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v23, v4, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v24, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v26, v18, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v16, v5, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v20, v6, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v19, v7, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v27, v8, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v25, v9, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v68, v10, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v70, v11, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v69, v12, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v67, v13, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v66, v14, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v64, v15, 0x5040100
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -32899,267 +38041,550 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v32bf16_to_v32f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v16
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB51_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v26, 16, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v28, 16, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v30, 16, v11
-; GFX11-NEXT:    v_dual_add_f32 v24, 0x40c00000, v24 :: v_dual_lshlrev_b32 v25, 16, v6
-; GFX11-NEXT:    v_bfe_u32 v21, v17, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v19, v16, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v16
-; GFX11-NEXT:    v_add_f32_e32 v25, 0x40c00000, v25
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-NEXT:    v_add3_u32 v21, v21, v17, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v19, v19, v16, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT:    v_dual_add_f32 v26, 0x40c00000, v26 :: v_dual_lshlrev_b32 v27, 16, v8
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v16, v19, v22, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v19, 0x400000, v17
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v22, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-NEXT:    v_add_f32_e32 v27, 0x40c00000, v27
-; GFX11-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v29, 16, v10
-; GFX11-NEXT:    v_bfe_u32 v20, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v23, 0x400000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_add_f32_e32 v8, 0x40c00000, v8
-; GFX11-NEXT:    v_dual_add_f32 v28, 0x40c00000, v28 :: v_dual_add_f32 v29, 0x40c00000, v29
-; GFX11-NEXT:    v_add3_u32 v20, v20, v0, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-NEXT:    v_dual_add_f32 v30, 0x40c00000, v30 :: v_dual_lshlrev_b32 v31, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v0, v20, v23 :: v_dual_lshlrev_b32 v23, 16, v4
-; GFX11-NEXT:    v_bfe_u32 v20, v1, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT:    v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_add_f32 v23, 0x40c00000, v23
-; GFX11-NEXT:    v_perm_b32 v0, v0, v16, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v17, v21, v19, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v19, v20, v1, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v2
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT:    v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_add_f32 v31, 0x40c00000, v31
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v1, v19, v20 :: v_dual_add_f32 v18, 0x40c00000, v18
-; GFX11-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT:    v_add_f32_e32 v22, 0x40c00000, v22
-; GFX11-NEXT:    v_bfe_u32 v21, v18, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v18
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-NEXT:    v_or_b32_e32 v33, 0x400000, v31
-; GFX11-NEXT:    v_add3_u32 v19, v21, v18, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v21, v2, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v34, v12, 16, 1
-; GFX11-NEXT:    v_perm_b32 v1, v1, v17, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v18, v19, v20 :: v_dual_and_b32 v7, 0xffff0000, v7
-; GFX11-NEXT:    v_add3_u32 v19, v21, v2, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v2
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_bfe_u32 v21, v22, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-NEXT:    v_dual_cndmask_b32 v2, v19, v20 :: v_dual_and_b32 v11, 0xffff0000, v11
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v19, v21, v22, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v22
-; GFX11-NEXT:    v_bfe_u32 v21, v3, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-NEXT:    v_bfe_u32 v22, v23, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-NEXT:    v_perm_b32 v2, v2, v18, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-NEXT:    v_cndmask_b32_e32 v19, v19, v20, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v20, v21, v3, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v3
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_or_b32_e32 v32, 0x400000, v11
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v20, v21, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v20, v22, v23, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v21, 0x400000, v23
-; GFX11-NEXT:    v_bfe_u32 v22, v4, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-NEXT:    v_bfe_u32 v23, v24, 16, 1
-; GFX11-NEXT:    v_perm_b32 v3, v3, v19, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v20, v20, v21, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v21, v22, v4, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v4, v21, v22, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v21, v23, v24, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v24
-; GFX11-NEXT:    v_bfe_u32 v23, v5, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-NEXT:    v_bfe_u32 v24, v25, 16, 1
-; GFX11-NEXT:    v_perm_b32 v4, v4, v20, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v21, v21, v22, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v22, v23, v5, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v23, 0x400000, v5
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v5, v22, v23, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v22, v24, v25, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v23, 0x400000, v25
-; GFX11-NEXT:    v_bfe_u32 v24, v6, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-NEXT:    v_bfe_u32 v25, v26, 16, 1
-; GFX11-NEXT:    v_perm_b32 v5, v5, v21, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v22, v22, v23, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v23, v24, v6, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v24, 0x400000, v6
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v6, v23, v24, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v23, v25, v26, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v24, 0x400000, v26
-; GFX11-NEXT:    v_bfe_u32 v25, v7, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-NEXT:    v_bfe_u32 v26, v27, 16, 1
-; GFX11-NEXT:    v_perm_b32 v6, v6, v22, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v23, v23, v24, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v24, v25, v7, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v25, 0x400000, v7
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v7, v24, v25, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v24, v26, v27, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v25, 0x400000, v27
-; GFX11-NEXT:    v_bfe_u32 v26, v8, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11-NEXT:    v_bfe_u32 v27, v28, 16, 1
-; GFX11-NEXT:    v_perm_b32 v7, v7, v23, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v24, v24, v25, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v25, v26, v8, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v26, 0x400000, v8
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v8, v25, v26, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v25, v27, v28, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v26, 0x400000, v28
-; GFX11-NEXT:    v_bfe_u32 v27, v9, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11-NEXT:    v_bfe_u32 v28, v29, 16, 1
-; GFX11-NEXT:    v_perm_b32 v8, v8, v24, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v25, v25, v26, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v26, v27, v9, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v27, 0x400000, v9
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v9, v26, v27, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v26, v28, v29, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v27, 0x400000, v29
-; GFX11-NEXT:    v_bfe_u32 v28, v10, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11-NEXT:    v_bfe_u32 v29, v30, 16, 1
-; GFX11-NEXT:    v_perm_b32 v9, v9, v25, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v26, v26, v27, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v27, v28, v10, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v28, 0x400000, v10
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v10, v27, v28, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v27, v29, v30, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v28, 0x400000, v30
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-NEXT:    v_bfe_u32 v30, v31, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v29, v11, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v27, v27, v28 :: v_dual_lshlrev_b32 v28, 16, v13
-; GFX11-NEXT:    v_add3_u32 v30, v30, v31, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-NEXT:    v_add3_u32 v31, v34, v12, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v28, 0x40c00000, v28
-; GFX11-NEXT:    v_add3_u32 v29, v29, v11, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v30, v30, v33, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v33, 0x400000, v12
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-NEXT:    v_bfe_u32 v35, v28, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v28
-; GFX11-NEXT:    v_cndmask_b32_e32 v12, v31, v33, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v34, v35, v28, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v35, 16, v14
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-NEXT:    v_bfe_u32 v37, v13, 16, 1
-; GFX11-NEXT:    v_perm_b32 v10, v10, v26, 0x7060302
-; GFX11-NEXT:    v_dual_add_f32 v31, 0x40c00000, v35 :: v_dual_cndmask_b32 v28, v34, v36
-; GFX11-NEXT:    v_lshlrev_b32_e32 v34, 16, v15
-; GFX11-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-NEXT:    v_add3_u32 v33, v37, v13, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v35, v31, 16, 1
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v31
-; GFX11-NEXT:    v_bfe_u32 v38, v14, 16, 1
-; GFX11-NEXT:    v_add3_u32 v35, v35, v31, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-NEXT:    v_bfe_u32 v39, v34, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v48, 0x400000, v34
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v13
-; GFX11-NEXT:    v_cndmask_b32_e32 v31, v35, v37, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v37, v38, v14, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v38, 0x400000, v14
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-NEXT:    v_bfe_u32 v35, v15, 16, 1
-; GFX11-NEXT:    v_add3_u32 v39, v39, v34, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v49, 0x400000, v15
-; GFX11-NEXT:    v_cndmask_b32_e32 v14, v37, v38, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-NEXT:    v_add3_u32 v35, v35, v15, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v14, v14, v31, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v34, v39, v48, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-NEXT:    v_cndmask_b32_e32 v15, v35, v49, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v15, v15, v34, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v13, v33, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-NEXT:    v_perm_b32 v12, v12, v30, 0x7060302
-; GFX11-NEXT:    v_perm_b32 v13, v13, v28, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v11, v29, v32, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v11, v11, v27, 0x7060302
-; GFX11-NEXT:  .LBB51_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v32bf16_to_v32f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v16
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB51_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff0000, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v28, 0xffff0000, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v30, 0xffff0000, v10
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v16, 0x40c00000, v16
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v32, 0xffff0000, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v20, 0x400000, v16
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_lshlrev_b32 v12, 16, v12
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v0, v16, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v22, v17, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v21, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v0, v0, v16, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, 0x400000, v19
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, 0x400000, v17
+; GFX11-TRUE16-NEXT:    v_add3_u32 v22, v22, v17, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v21, v21, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v0, v20, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v16, v21, v23 :: v_dual_add_f32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v18, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v17, v22, v24 :: v_dual_add_f32 v18, 0x40c00000, v18
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v19, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v22, v18, 16, 1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff0000, v4
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v23, v20, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v22, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v18
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v22, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v16.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v18, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v22, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v22, v23, v20, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, 0x400000, v20
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v17
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v16, v0
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v19, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v20, v22, v23, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff0000, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v19, v23, vcc_lo
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v21, 0x40c00000, v24 :: v_dual_add_f32 v22, 0x40c00000, v22
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v24, v21, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, 0x400000, v21
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v25, v22, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v3, 0xffff, v3, v20
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v24, v21, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v19, v19, v23 :: v_dual_lshlrev_b32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v24, v4, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    v_add3_u32 v21, v24, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v24, v25, v22, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v25, 0x400000, v22
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v21, v23, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v21, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v23, 0x40c00000, v26
+; GFX11-TRUE16-NEXT:    v_add3_u32 v21, v21, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v22, v24, v25, vcc_lo
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff0000, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v25, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v26, v23, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v24, 0x40c00000, v24 :: v_dual_lshlrev_b32 v7, 16, v7
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v21, v25, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v21, v26, v23, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v25, 0x400000, v23
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v26, v6, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v27, v24, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v23, v26, v6, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v21, v21, v25, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v25, 0x400000, v6
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT:    v_add3_u32 v26, v27, v24, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v27, 0x400000, v24
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v5, 0xffff, v5, v22
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v2, v18
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v23, v25, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v23, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v25, 0x40c00000, v28
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v4.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v23, v23, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v24, v26, v27, vcc_lo
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v26, 0xffff0000, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v27, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v28, v25, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v26, 0x40c00000, v26 :: v_dual_lshlrev_b32 v9, 16, v9
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v4, 0xffff, v4, v19
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v7, v23, v27, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v23, v28, v25, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v27, 0x400000, v25
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v28, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v29, v26, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v25, v28, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v23, v23, v27, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v27, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    v_add3_u32 v28, v29, v26, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v29, 0x400000, v26
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v25, v27, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v25, v9, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v27, 0x40c00000, v30
+; GFX11-TRUE16-NEXT:    v_add3_u32 v25, v25, v9, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v26, v28, v29, vcc_lo
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v28, 0xffff0000, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v29, 0x400000, v9
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v30, v27, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v28, 0x40c00000, v28 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v9, v25, v29, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v25, v30, v27, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v29, 0x400000, v27
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v30, v10, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v31, v28, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v27, v30, v10, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v25, v25, v29, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v29, 0x400000, v10
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT:    v_add3_u32 v30, v31, v28, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v31, 0x400000, v28
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v6, 0xffff, v6, v21
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v10, v27, v29, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v27, v11, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v29, 0x40c00000, v32
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v7, 0xffff, v7, v24
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v27, v27, v11, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v28, v30, v31, vcc_lo
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v30, 0xffff0000, v13
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v31, 0x400000, v11
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v29, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v30, 0x40c00000, v30 :: v_dual_lshlrev_b32 v13, 16, v13
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v11, v27, v31, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v27, v32, v29, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v31, 0x400000, v29
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v32, v12, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v30, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v29, v32, v12, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v27, v27, v31, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v31, 0x400000, v12
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT:    v_add3_u32 v32, v33, v30, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v33, 0x400000, v30
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v34, 0x400000, v13
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v12, v29, v31, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff0000, v14
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v29, v13, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v30, v32, v33, vcc_lo
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v15
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_add_f32 v31, 0x40c00000, v31
+; GFX11-TRUE16-NEXT:    v_add3_u32 v29, v29, v13, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v32, 0x40c00000, v32 :: v_dual_add_f32 v15, 0x40c00000, v15
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v35, v14, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v48, 0x400000, v14
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v33, v31, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v36, v32, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v32
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v32
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v38, v15, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v35, v35, v14, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v36, v36, v32, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v49, 0x400000, v15
+; GFX11-TRUE16-NEXT:    v_add3_u32 v33, v33, v31, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v38, v38, v15, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v31
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v36, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v12, 0xffff, v12, v27
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v11, 0xffff, v11, v28
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v32.l, v32.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v14, v35, v48, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v10, 0xffff, v10, v25
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v9, 0xffff, v9, v26
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v8, 0xffff, v8, v23
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v14.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v15, v38, v49, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v15, 0xffff, v32, v15
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v13, v29, v34, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v29, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v13, 0xffff, v13, v30
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v14, 0xffff, v14, v29
+; GFX11-TRUE16-NEXT:  .LBB51_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v32bf16_to_v32f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v16
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB51_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v11
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v24, 0x40c00000, v24 :: v_dual_lshlrev_b32 v25, 16, v6
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v17, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v19, v16, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v16
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v25, 0x40c00000, v25
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v21, v17, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v19, v16, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v26, 0x40c00000, v26 :: v_dual_lshlrev_b32 v27, 16, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v19, v22, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, 0x400000, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v22, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v27, 0x40c00000, v27
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v10
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v20, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v28, 0x40c00000, v28 :: v_dual_add_f32 v29, 0x40c00000, v29
+; GFX11-FAKE16-NEXT:    v_add3_u32 v20, v20, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v30, 0x40c00000, v30 :: v_dual_lshlrev_b32 v31, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v20, v23 :: v_dual_lshlrev_b32 v23, 16, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v20, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_add_f32 v23, 0x40c00000, v23
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v16, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v21, v19, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v20, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_add_f32 v31, 0x40c00000, v31
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v19, v20 :: v_dual_add_f32 v18, 0x40c00000, v18
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v33, 0x400000, v31
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v21, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v12, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v18, v19, v20 :: v_dual_and_b32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v21, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v22, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v19, v20 :: v_dual_and_b32 v11, 0xffff0000, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v21, v22, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v22
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v23, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v2, v18, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v19, v19, v20, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v20, v21, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v32, 0x400000, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v20, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v20, v22, v23, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, 0x400000, v23
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v23, v24, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v3, v19, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v20, v20, v21, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v22, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v21, v22, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v23, v24, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v24
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v23, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v24, v25, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v4, v20, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v21, v21, v22, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v22, v23, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, 0x400000, v5
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v22, v23, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v22, v24, v25, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, 0x400000, v25
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v24, v6, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v25, v26, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v5, v21, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v22, v22, v23, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v23, v24, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v23, v24, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v23, v25, v26, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, 0x400000, v26
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v25, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v26, v27, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v6, v22, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v23, v23, v24, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v24, v25, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v24, v25, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v24, v26, v27, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, 0x400000, v27
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v26, v8, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v27, v28, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v23, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v24, v24, v25, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v25, v26, v8, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, 0x400000, v8
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v25, v26, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v25, v27, v28, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, 0x400000, v28
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v27, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v28, v29, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v8, v24, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v25, v25, v26, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v26, v27, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v26, v27, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v26, v28, v29, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v27, 0x400000, v29
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v28, v10, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v29, v30, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v9, v25, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v26, v26, v27, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v27, v28, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, 0x400000, v10
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v27, v28, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v27, v29, v30, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v28, 0x400000, v30
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v30, v31, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v29, v11, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v27, v27, v28 :: v_dual_lshlrev_b32 v28, 16, v13
+; GFX11-FAKE16-NEXT:    v_add3_u32 v30, v30, v31, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11-FAKE16-NEXT:    v_add3_u32 v31, v34, v12, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v28, 0x40c00000, v28
+; GFX11-FAKE16-NEXT:    v_add3_u32 v29, v29, v11, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v30, v30, v33, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v33, 0x400000, v12
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v28, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v28
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v31, v33, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v34, v35, v28, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v35, 16, v14
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v37, v13, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v10, v26, 0x7060302
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v31, 0x40c00000, v35 :: v_dual_cndmask_b32 v28, v34, v36
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v15
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v37, v13, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v31, 16, 1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v31
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v38, v14, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v31, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v39, v34, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v48, 0x400000, v34
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v13
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v31, v35, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v37, v38, v14, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v38, 0x400000, v14
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v15, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v39, v39, v34, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v49, 0x400000, v15
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v14, v37, v38, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v15, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v14, v31, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v34, v39, v48, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v15, v35, v49, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v15, v34, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v13, v33, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v12, v30, 0x7060302
+; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v13, v28, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v29, v32, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v11, v27, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB51_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -34602,332 +40027,614 @@ define <64 x i8> @bitcast_v32f16_to_v64i8(<32 x half> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v32f16_to_v64i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v17
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr67
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB52_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
-; GFX11-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
-; GFX11-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 8, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 8, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 24, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 8, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 16, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 8, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v49, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v51, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v52, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v53, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v54, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v64, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v66, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v67, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v68, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v69, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v71, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v80, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v81, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v82, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v83, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v84, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v85, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v86, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v87, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v96, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
-; GFX11-NEXT:  .LBB52_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB52_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
-; GFX11-NEXT:    v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
-; GFX11-NEXT:    v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
-; GFX11-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 8, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 8, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 24, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 8, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 16, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 8, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v49, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v51, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v52, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v53, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v54, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v64, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v66, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v67, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v68, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v69, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v71, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v80, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v81, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v82, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v83, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v84, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v85, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v86, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v87, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v96, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
-; GFX11-NEXT:  .LBB52_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v25
-; GFX11-NEXT:    v_and_b32_e32 v96, 0xff, v96
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v24
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v86, 0xff, v86
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v25
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v87
-; GFX11-NEXT:    v_or_b32_e32 v24, v96, v24
-; GFX11-NEXT:    v_lshlrev_b16 v85, 8, v85
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v25
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT:    v_or_b32_e32 v25, v86, v85
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_lshlrev_b16 v84, 8, v84
-; GFX11-NEXT:    v_and_b32_e32 v83, 0xff, v83
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v24
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v82
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v80, 8, v80
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_lshlrev_b16 v71, 8, v71
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v24
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v81
-; GFX11-NEXT:    v_and_b32_e32 v70, 0xff, v70
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v22
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v84
-; GFX11-NEXT:    v_or_b32_e32 v23, v83, v23
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v80
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v71
-; GFX11-NEXT:    v_or_b32_e32 v22, v70, v22
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v24
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v23
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v25
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v22
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v66
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v65
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v21
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v64
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v55
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v54
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v53
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v22
-; GFX11-NEXT:    v_or_b32_e32 v21, v23, v21
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v24
-; GFX11-NEXT:    v_or_b32_e32 v22, v25, v54
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v52
-; GFX11-NEXT:    v_lshlrev_b16 v20, 8, v20
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v51
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v50
-; GFX11-NEXT:    v_lshlrev_b16 v49, 8, v49
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_lshlrev_b16 v48, 8, v48
-; GFX11-NEXT:    v_and_b32_e32 v39, 0xff, v39
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v19
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v53
-; GFX11-NEXT:    v_or_b32_e32 v20, v23, v20
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v24
-; GFX11-NEXT:    v_or_b32_e32 v23, v25, v49
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v48
-; GFX11-NEXT:    v_or_b32_e32 v19, v39, v19
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v21
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v22
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v20
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v23
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v19
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v38
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v37
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v36
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v35
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v34
-; GFX11-NEXT:    v_lshlrev_b16 v18, 8, v18
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v33
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_lshlrev_b16 v69, 8, v69
-; GFX11-NEXT:    v_and_b32_e32 v68, 0xff, v68
-; GFX11-NEXT:    v_lshlrev_b16 v67, 8, v67
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v19
-; GFX11-NEXT:    v_or_b32_e32 v19, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v22
-; GFX11-NEXT:    v_or_b32_e32 v18, v23, v18
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v24
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v32
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v31
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v30
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v29
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v17
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v28
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v27
-; GFX11-NEXT:    v_lshlrev_b16 v26, 8, v26
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v69
-; GFX11-NEXT:    v_or_b32_e32 v67, v68, v67
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v22
-; GFX11-NEXT:    v_or_b32_e32 v17, v23, v17
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v24
-; GFX11-NEXT:    v_or_b32_e32 v21, v25, v26
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v67, 16, v67
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v67
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v19
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v18
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v20
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v17
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v21
-; GFX11-NEXT:    s_clause 0x3
-; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off
-; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
-; GFX11-NEXT:    scratch_store_b128 v0, v[9:12], off offset:32
-; GFX11-NEXT:    scratch_store_b128 v0, v[13:16], off offset:48
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v32f16_to_v64i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v17
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB52_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 24, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v33, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v35, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v37, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v38, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v48, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v49, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v50, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v51, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v52, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v53, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v54, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v55, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v64, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB52_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB52_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 24, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v33, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v35, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v37, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v38, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v48, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v49, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v50, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v51, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v52, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v53, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v54, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v55, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v64, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-TRUE16-NEXT:  .LBB52_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v17.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v64.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v1.h, v18.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v55.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v54.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.h, 8, v53.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v17.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v2.h, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v19.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v21.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v53, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v52.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v24
+; GFX11-TRUE16-NEXT:    v_or_b16 v24.l, v3.h, v20.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v25.l, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v54, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v51.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v5.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v22.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v48.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v25
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v21.l, 8, v37.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v17.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v50.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v49.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v49, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v50, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v54, v24
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v25, v22
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v39.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v22.l, v7.h, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v20.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v38.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v19.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.l, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v10.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v35.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v53, v23
+; GFX11-TRUE16-NEXT:    v_or_b16 v23.l, v8.h, v20.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v21
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v36.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v11.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v34.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v34, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v21, v19
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v33.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.l, 8, v31.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v19.h, 8, v30.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v12.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.h, 8, v32.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v18.l, 8, v18.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v19.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v19.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v35, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v24, v22
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v20, v34
+; GFX11-TRUE16-NEXT:    v_or_b16 v20.l, v12.h, v18.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v13.h, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v14.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v14.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v29.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v15.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.l, 0xff, v16.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v16.l, 0xff, v16.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v26.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v14.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v15.l, v15.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v16.l, v16.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v51, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v25, v23
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v19
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v23, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v14
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v49, v50
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v51, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v35, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v21, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v22, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v19, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v23, v24
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, v25, v16
+; GFX11-TRUE16-NEXT:    s_clause 0x3
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[9:12], off offset:32
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[13:16], off offset:48
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v32f16_to_v64i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB52_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 24, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 16, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 16, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v49, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v50, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v51, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v52, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v53, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v54, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v55, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v64, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v65, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v66, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v67, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v68, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v69, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v70, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v81, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v82, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v85, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v86, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB52_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB52_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 24, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 16, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 16, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v49, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v50, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v51, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v52, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v53, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v54, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v55, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v64, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v65, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v66, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v67, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v68, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v69, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v70, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v81, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v82, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v85, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v86, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB52_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v96, 0xff, v96
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v86, 0xff, v86
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v87
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v96, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v85, 8, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v86, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v84, 8, v84
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v83, 0xff, v83
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v82
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v80, 8, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v71, 8, v71
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v81
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v70, 0xff, v70
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v84
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v83, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v80
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v71
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v70, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v66
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v65
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v64
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v55
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v53, 8, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v23, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v25, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v52
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v51
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v50
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v49, 8, v49
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v48, 8, v48
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v39, 0xff, v39
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v23, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v25, v49
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v48
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v39, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v38
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v37
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v35
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v18, 8, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v69, 8, v69
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v68, 0xff, v68
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v67, 8, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v23, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v30
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v29
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v26, 8, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v69
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v67, v68, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v23, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v25, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v67, 16, v67
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v21
+; GFX11-FAKE16-NEXT:    s_clause 0x3
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[9:12], off offset:32
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[13:16], off offset:48
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -36575,409 +42282,795 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v64i8_to_v32f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v32, v14 :: v_dual_mov_b32 v31, v8
-; GFX11-NEXT:    v_dual_mov_b32 v34, v12 :: v_dual_mov_b32 v35, v10
-; GFX11-NEXT:    v_dual_mov_b32 v38, v6 :: v_dual_mov_b32 v33, v4
-; GFX11-NEXT:    v_dual_mov_b32 v37, v2 :: v_dual_mov_b32 v36, v0
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v0, off, s32 offset:128
-; GFX11-NEXT:    scratch_load_u16 v67, off, s32 offset:124
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32 offset:120
-; GFX11-NEXT:    scratch_load_u16 v70, off, s32 offset:116
-; GFX11-NEXT:    scratch_load_u16 v4, off, s32 offset:112
-; GFX11-NEXT:    scratch_load_u16 v66, off, s32 offset:108
-; GFX11-NEXT:    scratch_load_u16 v6, off, s32 offset:104
-; GFX11-NEXT:    scratch_load_u16 v69, off, s32 offset:100
-; GFX11-NEXT:    scratch_load_u16 v8, off, s32 offset:96
-; GFX11-NEXT:    scratch_load_u16 v64, off, s32 offset:92
-; GFX11-NEXT:    scratch_load_u16 v10, off, s32 offset:88
-; GFX11-NEXT:    scratch_load_b32 v12, off, s32 offset:132
-; GFX11-NEXT:    scratch_load_u16 v14, off, s32
-; GFX11-NEXT:    scratch_load_u16 v96, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_u16 v100, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_u16 v101, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_u16 v102, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_u16 v103, off, s32 offset:40
-; GFX11-NEXT:    scratch_load_u16 v113, off, s32 offset:48
-; GFX11-NEXT:    scratch_load_u16 v114, off, s32 offset:56
-; GFX11-NEXT:    scratch_load_u16 v115, off, s32 offset:64
-; GFX11-NEXT:    scratch_load_u16 v116, off, s32 offset:72
-; GFX11-NEXT:    scratch_load_u16 v117, off, s32 offset:80
-; GFX11-NEXT:    scratch_load_u16 v99, off, s32 offset:84
-; GFX11-NEXT:    scratch_load_u16 v85, off, s32 offset:76
-; GFX11-NEXT:    scratch_load_u16 v97, off, s32 offset:68
-; GFX11-NEXT:    scratch_load_u16 v82, off, s32 offset:60
-; GFX11-NEXT:    scratch_load_u16 v86, off, s32 offset:52
-; GFX11-NEXT:    scratch_load_u16 v84, off, s32 offset:44
-; GFX11-NEXT:    scratch_load_u16 v87, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_u16 v68, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_u16 v80, off, s32 offset:20
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_u16 v65, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_u16 v71, off, s32 offset:4
-; GFX11-NEXT:    v_lshlrev_b16 v50, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v51, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v49, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v48, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v52, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v83, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v81, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(33)
-; GFX11-NEXT:    v_lshlrev_b16 v119, 8, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(31)
-; GFX11-NEXT:    v_lshlrev_b16 v118, 8, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(22)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v12
-; GFX11-NEXT:    s_waitcnt vmcnt(21)
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v14
-; GFX11-NEXT:    s_waitcnt vmcnt(20)
-; GFX11-NEXT:    v_lshlrev_b16 v98, 8, v96
-; GFX11-NEXT:    s_waitcnt vmcnt(19)
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v100
-; GFX11-NEXT:    s_waitcnt vmcnt(18)
-; GFX11-NEXT:    v_lshlrev_b16 v96, 8, v101
-; GFX11-NEXT:    s_waitcnt vmcnt(17)
-; GFX11-NEXT:    v_lshlrev_b16 v29, 8, v102
-; GFX11-NEXT:    s_waitcnt vmcnt(16)
-; GFX11-NEXT:    v_lshlrev_b16 v112, 8, v103
-; GFX11-NEXT:    s_waitcnt vmcnt(15)
-; GFX11-NEXT:    v_lshlrev_b16 v103, 8, v113
-; GFX11-NEXT:    s_waitcnt vmcnt(14)
-; GFX11-NEXT:    v_lshlrev_b16 v101, 8, v114
-; GFX11-NEXT:    s_waitcnt vmcnt(13)
-; GFX11-NEXT:    v_lshlrev_b16 v100, 8, v115
-; GFX11-NEXT:    s_waitcnt vmcnt(12)
-; GFX11-NEXT:    v_lshlrev_b16 v114, 8, v116
-; GFX11-NEXT:    s_waitcnt vmcnt(11)
-; GFX11-NEXT:    v_lshlrev_b16 v102, 8, v117
-; GFX11-NEXT:    v_lshlrev_b16 v117, 8, v10
-; GFX11-NEXT:    v_lshlrev_b16 v113, 8, v8
-; GFX11-NEXT:    v_lshlrev_b16 v116, 8, v6
-; GFX11-NEXT:    v_lshlrev_b16 v115, 8, v4
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB53_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB53_4
-; GFX11-NEXT:  .LBB53_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB53_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v36
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v37
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v38
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v31
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v35
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v50
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v51
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v34
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v18
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    v_or_b32_e32 v1, v3, v39
-; GFX11-NEXT:    v_or_b32_e32 v3, v4, v54
-; GFX11-NEXT:    v_or_b32_e32 v4, v5, v48
-; GFX11-NEXT:    v_or_b32_e32 v5, v6, v55
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v22
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v49
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v53
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v52
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v17
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v83
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v81
-; GFX11-NEXT:    v_perm_b32 v1, v1, v2, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v2, v4, v3, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v3, v6, v5, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v4, v8, v7, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v5, v10, v9, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v24
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v26
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v30
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v71
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v65
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v80
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v68
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v87
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v84
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v21
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v19
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v27
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v23
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v98
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v25
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v96
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v29
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v112
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v103
-; GFX11-NEXT:    v_perm_b32 v6, v7, v6, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v7, v9, v8, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v8, v11, v10, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v9, v13, v12, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v10, v15, v14, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v86
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v82
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v97
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v85
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v99
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v64
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v69
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v66
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v70
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v67
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v101
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v100
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v114
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v102
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v117
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v113
-; GFX11-NEXT:    v_or_b32_e32 v17, v17, v116
-; GFX11-NEXT:    v_or_b32_e32 v18, v18, v115
-; GFX11-NEXT:    v_or_b32_e32 v19, v19, v118
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v119
-; GFX11-NEXT:    v_perm_b32 v11, v12, v11, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v12, v14, v13, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v13, v16, v15, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v14, v18, v17, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v15, v20, v19, 0x5040100
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr97
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr99
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr67
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr98
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr112
-; GFX11-NEXT:    ; implicit-def: $vgpr103
-; GFX11-NEXT:    ; implicit-def: $vgpr101
-; GFX11-NEXT:    ; implicit-def: $vgpr100
-; GFX11-NEXT:    ; implicit-def: $vgpr114
-; GFX11-NEXT:    ; implicit-def: $vgpr102
-; GFX11-NEXT:    ; implicit-def: $vgpr117
-; GFX11-NEXT:    ; implicit-def: $vgpr113
-; GFX11-NEXT:    ; implicit-def: $vgpr116
-; GFX11-NEXT:    ; implicit-def: $vgpr115
-; GFX11-NEXT:    ; implicit-def: $vgpr118
-; GFX11-NEXT:    ; implicit-def: $vgpr119
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB53_2
-; GFX11-NEXT:  .LBB53_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v70, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v67, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v69, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v66, 3
-; GFX11-NEXT:    v_add_nc_u16 v5, v64, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    s_waitcnt vmcnt(8)
-; GFX11-NEXT:    v_add_nc_u16 v6, v97, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v0, v118, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v119, v1
-; GFX11-NEXT:    v_add_nc_u16 v4, v99, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v64, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v0, v116, v2
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v5
-; GFX11-NEXT:    v_or_b32_e32 v2, v115, v3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v113, v1
-; GFX11-NEXT:    v_add_nc_u16 v66, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v1, v114, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v117, v4
-; GFX11-NEXT:    v_add_nc_u16 v2, v85, 3
-; GFX11-NEXT:    v_add_nc_u16 v67, 0x300, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(6)
-; GFX11-NEXT:    v_add_nc_u16 v0, v86, 3
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v82, 3
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v4
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(4)
-; GFX11-NEXT:    v_add_nc_u16 v3, v87, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v4, v84, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v102, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v0, v101, v0
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v1, v100, v1
-; GFX11-NEXT:    v_add_nc_u16 v69, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v112, v3
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v103, v4
-; GFX11-NEXT:    v_add_nc_u16 v70, 0x300, v1
-; GFX11-NEXT:    s_waitcnt vmcnt(2)
-; GFX11-NEXT:    v_add_nc_u16 v1, v80, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v68, 3
-; GFX11-NEXT:    v_add_nc_u16 v68, 0x300, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_nc_u16 v0, v71, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v3, v65, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v4, v28, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v96, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v29, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v0, v98, v0
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v25, v3
-; GFX11-NEXT:    v_add_nc_u16 v25, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v27, v4
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v30, 3
-; GFX11-NEXT:    v_add_nc_u16 v27, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v24, 3
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v26, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v3, v20, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v4, v22, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_or_b32_e32 v0, v23, v0
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v1, v21, v1
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v2, v19, v2
-; GFX11-NEXT:    v_add_nc_u16 v19, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v83, v3
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v81, v4
-; GFX11-NEXT:    v_add_nc_u16 v20, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v16, 3
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v34, 3
-; GFX11-NEXT:    v_add_nc_u16 v16, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v31, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, v18, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v4, v32, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v53, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v0, v55, v0
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v1, v54, v1
-; GFX11-NEXT:    v_add_nc_u16 v18, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v17, v3
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v52, v4
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v33, 3
-; GFX11-NEXT:    v_add_nc_u16 v17, v36, 3
-; GFX11-NEXT:    v_add_nc_u16 v21, v37, 3
-; GFX11-NEXT:    v_add_nc_u16 v22, v38, 3
-; GFX11-NEXT:    v_add_nc_u16 v23, v35, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v17
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v21
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v23
-; GFX11-NEXT:    v_or_b32_e32 v1, v49, v1
-; GFX11-NEXT:    v_or_b32_e32 v17, v50, v17
-; GFX11-NEXT:    v_or_b32_e32 v21, v51, v21
-; GFX11-NEXT:    v_or_b32_e32 v22, v39, v22
-; GFX11-NEXT:    v_or_b32_e32 v23, v48, v23
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v17, 0x300, v17
-; GFX11-NEXT:    v_add_nc_u16 v21, 0x300, v21
-; GFX11-NEXT:    v_add_nc_u16 v22, 0x300, v22
-; GFX11-NEXT:    v_add_nc_u16 v23, 0x300, v23
-; GFX11-NEXT:    v_add_nc_u16 v24, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v26, 0x300, v2
-; GFX11-NEXT:    v_perm_b32 v0, v21, v17, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v1, v22, v1, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v2, v23, v4, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v3, v24, v3, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v4, v26, v18, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v5, v16, v5, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v6, v20, v6, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v7, v19, v7, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v8, v27, v8, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v9, v25, v9, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v10, v68, v10, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v11, v70, v11, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v12, v69, v12, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v13, v67, v13, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v14, v66, v14, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v15, v64, v15, 0x5040100
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v64i8_to_v32f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v55, off, s32 offset:128
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v32, off, s32 offset:124
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v55, off, s32 offset:120
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v33, off, s32 offset:116
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v53, off, s32 offset:112
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v31, off, s32 offset:108
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v53, off, s32 offset:104
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v32, off, s32 offset:100
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v52, off, s32 offset:96
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32 offset:92
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v54, off, s32 offset:88
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v66, off, s32 offset:132
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v39, off, s32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v48, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v48, off, s32 offset:16
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v50, off, s32 offset:24
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v50, off, s32 offset:32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v51, off, s32 offset:40
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v52, off, s32 offset:48
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v54, off, s32 offset:56
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v64, off, s32 offset:64
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v64, off, s32 offset:72
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v65, off, s32 offset:80
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v38, off, s32 offset:84
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v36, off, s32 offset:76
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v38, off, s32 offset:68
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v35, off, s32 offset:60
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v37, off, s32 offset:52
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v36, off, s32 offset:44
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v37, off, s32 offset:36
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v34, off, s32 offset:28
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v34, off, s32 offset:20
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v33, off, s32 offset:12
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v35, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.h, v29.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.l, v27.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.h, v25.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v39.l, v23.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.h, v21.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v26.h, v19.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v25.h, v17.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.h, v22.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v24.h, v20.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.h, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v17.h, v14.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.h, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.l, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v17.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v18.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.l, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v27.l, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v22.l, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v27.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v25.l, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v25.h, 8, v25.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v26.h, 8, v26.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v30.h, 8, v30.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v39.l, 8, v39.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v28.h, 8, v28.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v29.l, 8, v29.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v49.l, 8, v29.h
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v55.h, 8, v55.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v55.l, 8, v55.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(29)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v53.h, 8, v53.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(27)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v53.l, 8, v53.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(25)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v52.h, 8, v52.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(23)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v54.h, 8, v54.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(21)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v29.h, 8, v39.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(20)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v49.h, 8, v48.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(19)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v39.h, 8, v48.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(18)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v48.l, 8, v50.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(17)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v48.h, 8, v50.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(16)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v51.h, 8, v51.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(15)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v52.l, 8, v52.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(14)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v50.l, 8, v54.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(13)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v50.h, 8, v64.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(12)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v54.l, 8, v64.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(11)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v51.l, 8, v65.l
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v66
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB53_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB53_4
+; GFX11-TRUE16-NEXT:  .LBB53_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB53_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v18.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v17.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v16.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v16.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v21.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v17.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v19.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v24.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v22.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v26.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v30.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v35.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v34.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.h, 0xff, v34.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v37.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.h, 0xff, v36.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v37.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.h, 0xff, v35.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v38.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v36.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v38.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v31.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v32.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.h, 0xff, v31.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.l, 0xff, v33.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.h, 0xff, v32.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v23.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v20.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v1.h, v20.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v27.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v2.h, v22.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v27.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v3.h, v25.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v25.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.h, v4.h, v26.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v30.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.h, v5.h, v39.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v28.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v6.h, v29.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v49.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v7.h, v29.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v49.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.h, v8.h, v39.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v48.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.h, v9.h, v48.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v51.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.h, v10.h, v52.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v50.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.h, v11.h, v50.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v54.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.h, v12.h, v51.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v54.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.h, v13.h, v52.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v53.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.h, v14.h, v53.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v15.l, v55.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.h, v15.h, v55.h
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB53_2
+; GFX11-TRUE16-NEXT:  .LBB53_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v33.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v32.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v32.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v31.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v31.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(8)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v38.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v55.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v55.h, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v38.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v53.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v53.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v35.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v52.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v54.l, v0.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v37.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v36.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v37.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v54.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v50.h, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v51.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v36.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v51.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v50.l, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v35.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v34.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v34.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v33.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v52.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v49.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v48.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v48.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v39.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.h, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v28.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v30.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v24.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v26.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v24.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v49.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v29.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v28.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v29.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v30.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v22.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v19.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v18.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v21.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v17.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v39.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v25.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v26.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v27.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v25.l, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v21.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v16.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v19.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v16.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v18.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v17.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v27.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v22.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v20.l, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v20.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.h, v23.l, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v23.h, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, 0x300, v16.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v16.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, 0x300, v17.l
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v32f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v32, v14 :: v_dual_mov_b32 v31, v8
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v34, v12 :: v_dual_mov_b32 v35, v10
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v38, v6 :: v_dual_mov_b32 v33, v4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v37, v2 :: v_dual_mov_b32 v36, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v0, off, s32 offset:128
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v67, off, s32 offset:124
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32 offset:120
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v70, off, s32 offset:116
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v4, off, s32 offset:112
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v66, off, s32 offset:108
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v6, off, s32 offset:104
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v69, off, s32 offset:100
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v8, off, s32 offset:96
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v64, off, s32 offset:92
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v10, off, s32 offset:88
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v12, off, s32 offset:132
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v14, off, s32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v96, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v100, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v101, off, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v102, off, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v103, off, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v113, off, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v114, off, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v115, off, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v116, off, s32 offset:72
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v117, off, s32 offset:80
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v99, off, s32 offset:84
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v85, off, s32 offset:76
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v97, off, s32 offset:68
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v82, off, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v86, off, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v84, off, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v87, off, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v68, off, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v80, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v65, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v71, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v50, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v51, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v49, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v48, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v52, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v53, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v83, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v81, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v29
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v119, 8, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v118, 8, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(22)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v12
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(21)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v14
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(20)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v98, 8, v96
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(19)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v100
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(18)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v96, 8, v101
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(17)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v29, 8, v102
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(16)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v112, 8, v103
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(15)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v103, 8, v113
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(14)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v101, 8, v114
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(13)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v100, 8, v115
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(12)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v114, 8, v116
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(11)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v102, 8, v117
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v117, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v113, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v116, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v115, 8, v4
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB53_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB53_4
+; GFX11-FAKE16-NEXT:  .LBB53_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB53_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v37
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v38
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v50
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v51
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v4, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v5, v48
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v49
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v52
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v83
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v81
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v4, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v6, v5, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v8, v7, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v10, v9, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v30
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v71
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v65
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v68
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v87
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v84
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v98
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v96
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v112
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v103
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v7, v6, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v9, v8, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v11, v10, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v13, v12, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v15, v14, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v86
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v82
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v97
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v99
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v64
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v69
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v66
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v70
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v101
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v100
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v114
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v102
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v117
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v113
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v17, v116
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v18, v115
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v19, v118
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v119
+; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v12, v11, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v14, v13, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v16, v15, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v18, v17, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v20, v19, 0x5040100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB53_2
+; GFX11-FAKE16-NEXT:  .LBB53_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v70, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v67, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v69, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v66, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v64, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(8)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v97, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v118, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v119, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v99, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v64, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v116, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v115, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v113, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v66, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v114, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v117, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v85, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v67, 0x300, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(6)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v86, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v82, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(4)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v87, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v84, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v102, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v101, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v100, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v69, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v112, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v103, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v70, 0x300, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v80, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v68, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v68, 0x300, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v71, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v65, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v28, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v96, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v29, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v98, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v25, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v25, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v27, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v30, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v27, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v24, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v26, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v20, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v22, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v23, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v21, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v19, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v83, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v81, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v16, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v34, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v31, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v18, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v32, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v53, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v55, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v54, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v17, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v52, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v33, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, v36, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, v37, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, v38, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v23, v35, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v49, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v50, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v51, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v39, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v48, v23
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, 0x300, v17
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, 0x300, v21
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, 0x300, v22
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v23, 0x300, v23
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v24, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v26, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v21, v17, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v22, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v23, v4, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v24, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v26, v18, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v16, v5, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v20, v6, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v19, v7, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v27, v8, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v25, v9, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v68, v10, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v70, v11, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v69, v12, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v67, v13, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v66, v14, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v64, v15, 0x5040100
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -38952,587 +45045,1166 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v32bf16_to_v64i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v17
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr97
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr67
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB54_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
-; GFX11-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
-; GFX11-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
-; GFX11-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
-; GFX11-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
-; GFX11-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 16, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 8, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v49, 8, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v50, 24, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 16, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v51, 8, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v53, 16, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v54, 8, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v55, 24, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v64, 8, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v66, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v67, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v69, 24, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v52, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v70, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v71, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v80, 8, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v82, 24, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v65, 16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v83, 8, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v84, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v85, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v86, 24, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v68, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v87, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v96, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v81, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v97, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
-; GFX11-NEXT:  .LBB54_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB54_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v18, 0x40c00000, v18
-; GFX11-NEXT:    v_add_f32_e32 v19, 0x40c00000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v1, v17, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v20, 0x400000, v17
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-NEXT:    v_bfe_u32 v22, v18, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v24, v19, 16, 1
-; GFX11-NEXT:    v_add3_u32 v1, v1, v17, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT:    v_or_b32_e32 v17, 0x400000, v18
-; GFX11-NEXT:    v_add3_u32 v22, v22, v18, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_cndmask_b32 v1, v1, v20 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-NEXT:    v_add3_u32 v20, v24, v19, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v21, v2, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v23, 0x400000, v2
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v21, v21, v2, 0x7fff
-; GFX11-NEXT:    v_dual_cndmask_b32 v2, v21, v23 :: v_dual_lshlrev_b32 v21, 16, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_or_b32_e32 v23, 0x400000, v19
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v27, v2, v1, 0x7060302
-; GFX11-NEXT:    v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_lshlrev_b32 v21, 16, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v17, v22, v17, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v18
-; GFX11-NEXT:    v_add_f32_e32 v21, 0x40c00000, v21
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v19, v20, v23, vcc_lo
-; GFX11-NEXT:    v_bfe_u32 v20, v18, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-NEXT:    v_or_b32_e32 v23, 0x400000, v4
-; GFX11-NEXT:    v_bfe_u32 v24, v21, 16, 1
-; GFX11-NEXT:    v_perm_b32 v26, v19, v17, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v19, v4, 16, 1
-; GFX11-NEXT:    v_add3_u32 v20, v20, v18, 0x7fff
-; GFX11-NEXT:    v_lshrrev_b32_e32 v81, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v17
-; GFX11-NEXT:    v_add3_u32 v19, v19, v4, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v18, v20, v22, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    v_or_b32_e32 v22, 0x400000, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v96, 24, v27
-; GFX11-NEXT:    v_lshrrev_b32_e32 v97, 16, v26
-; GFX11-NEXT:    v_dual_cndmask_b32 v4, v19, v23 :: v_dual_lshlrev_b32 v23, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-NEXT:    v_add3_u32 v19, v24, v21, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-NEXT:    v_perm_b32 v29, v4, v18, 0x7060302
-; GFX11-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-NEXT:    v_bfe_u32 v20, v3, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v24, 0x400000, v3
-; GFX11-NEXT:    v_dual_cndmask_b32 v19, v19, v22 :: v_dual_lshlrev_b32 v22, 16, v5
-; GFX11-NEXT:    v_add_f32_e32 v21, 0x40c00000, v23
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v20, v20, v3, 0x7fff
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v68, 16, v4
-; GFX11-NEXT:    v_add_f32_e32 v22, 0x40c00000, v22
-; GFX11-NEXT:    v_or_b32_e32 v23, 0x400000, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v4, 16, v18
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v20, v24, vcc_lo
-; GFX11-NEXT:    v_bfe_u32 v20, v21, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-NEXT:    v_or_b32_e32 v24, 0x400000, v6
-; GFX11-NEXT:    v_bfe_u32 v25, v22, 16, 1
-; GFX11-NEXT:    v_perm_b32 v28, v3, v19, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v3, v6, 16, 1
-; GFX11-NEXT:    v_add3_u32 v20, v20, v21, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v87, 16, v28
-; GFX11-NEXT:    v_add3_u32 v3, v3, v6, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_dual_cndmask_b32 v20, v20, v23 :: v_dual_add_f32 v5, 0x40c00000, v5
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    v_add3_u32 v6, v25, v22, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v23, 0x400000, v22
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v3, v24, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v8
-; GFX11-NEXT:    v_bfe_u32 v21, v5, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-NEXT:    v_or_b32_e32 v25, 0x400000, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_add3_u32 v21, v21, v5, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v22, v6, v23, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v6, 0x40c00000, v24
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v7
-; GFX11-NEXT:    v_perm_b32 v86, v3, v20, 0x7060302
-; GFX11-NEXT:    v_or_b32_e32 v24, 0x400000, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v5, v21, v25 :: v_dual_add_f32 v8, 0x40c00000, v8
-; GFX11-NEXT:    v_bfe_u32 v21, v6, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v65, 16, v3
-; GFX11-NEXT:    v_perm_b32 v85, v5, v22, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v5, v8, 16, 1
-; GFX11-NEXT:    v_add3_u32 v21, v21, v6, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v25, 0x400000, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v84, 16, v85
-; GFX11-NEXT:    v_add3_u32 v5, v5, v8, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v6, v21, v24, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v5, v5, v25, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v25, 16, v10
-; GFX11-NEXT:    v_add_f32_e32 v23, 0x40c00000, v23
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-NEXT:    v_perm_b32 v83, v5, v6, 0x7060302
-; GFX11-NEXT:    v_lshrrev_b32_e32 v52, 16, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v30, v23, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v24, 0x400000, v23
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 16, v22
-; GFX11-NEXT:    v_add3_u32 v8, v30, v23, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_cndmask_b32 v23, v8, v24 :: v_dual_lshlrev_b32 v24, 16, v9
-; GFX11-NEXT:    v_add_f32_e32 v24, 0x40c00000, v24
-; GFX11-NEXT:    v_add_f32_e32 v8, 0x40c00000, v25
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v31, v24, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v25, 0x400000, v8
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-NEXT:    v_bfe_u32 v21, v7, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v30, 0x400000, v7
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v21, v21, v7, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v7, v21, v30, vcc_lo
-; GFX11-NEXT:    v_bfe_u32 v21, v8, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-NEXT:    v_or_b32_e32 v30, 0x400000, v10
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v82, v7, v23, 0x7060302
-; GFX11-NEXT:    v_bfe_u32 v7, v10, 16, 1
-; GFX11-NEXT:    v_add3_u32 v21, v21, v8, 0x7fff
-; GFX11-NEXT:    v_lshrrev_b32_e32 v71, 16, v82
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add3_u32 v7, v7, v10, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v8, v21, v25, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    v_add3_u32 v10, v31, v24, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v25, 0x400000, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v80, 8, v82
-; GFX11-NEXT:    v_dual_cndmask_b32 v7, v7, v30 :: v_dual_lshlrev_b32 v30, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v70, v7, v8, 0x7060302
-; GFX11-NEXT:    v_lshrrev_b32_e32 v38, 16, v7
-; GFX11-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-NEXT:    v_cndmask_b32_e32 v24, v10, v25, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v10, 0x40c00000, v30
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 16, v23
-; GFX11-NEXT:    v_lshrrev_b32_e32 v64, 8, v70
-; GFX11-NEXT:    v_bfe_u32 v30, v12, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v30, v30, v12, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-NEXT:    v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v21, v9, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v31, 0x400000, v9
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    v_add3_u32 v21, v21, v9, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v9, v21, v31, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v11
-; GFX11-NEXT:    v_bfe_u32 v25, v10, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-NEXT:    v_perm_b32 v69, v9, v24, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v9, 0x40c00000, v21
-; GFX11-NEXT:    v_add3_u32 v21, v25, v10, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v25, 0x400000, v10
-; GFX11-NEXT:    v_or_b32_e32 v31, 0x400000, v12
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11-NEXT:    v_bfe_u32 v32, v9, 16, 1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v66, 16, v69
-; GFX11-NEXT:    v_cndmask_b32_e32 v10, v21, v25, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-NEXT:    v_or_b32_e32 v25, 0x400000, v9
-; GFX11-NEXT:    v_add3_u32 v21, v32, v9, 0x7fff
-; GFX11-NEXT:    v_lshrrev_b32_e32 v67, 8, v69
-; GFX11-NEXT:    v_cndmask_b32_e32 v12, v30, v31, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v30, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-NEXT:    v_perm_b32 v55, v12, v10, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v9, v21, v25, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v21, 0x40c00000, v30
-; GFX11-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-NEXT:    v_bfe_u32 v31, v11, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v30, 0x400000, v11
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-NEXT:    v_bfe_u32 v32, v21, 16, 1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v51, 8, v55
-; GFX11-NEXT:    v_add3_u32 v25, v31, v11, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v31, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v11, v25, v30, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v25, 0x40c00000, v31
-; GFX11-NEXT:    v_add3_u32 v30, v32, v21, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v31, 0x400000, v21
-; GFX11-NEXT:    v_bfe_u32 v32, v14, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-NEXT:    v_bfe_u32 v33, v25, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-NEXT:    v_or_b32_e32 v34, 0x400000, v25
-; GFX11-NEXT:    v_cndmask_b32_e32 v21, v30, v31, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v30, v32, v14, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v31, 0x400000, v14
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-NEXT:    v_add3_u32 v32, v33, v25, 0x7fff
-; GFX11-NEXT:    v_lshlrev_b32_e32 v33, 16, v16
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff0000, v16
-; GFX11-NEXT:    v_cndmask_b32_e32 v14, v30, v31, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_f32_e32 v30, 0x40c00000, v33
-; GFX11-NEXT:    v_add_f32_e32 v16, 0x40c00000, v16
-; GFX11-NEXT:    v_perm_b32 v54, v11, v9, 0x7060302
-; GFX11-NEXT:    v_perm_b32 v50, v14, v21, 0x7060302
-; GFX11-NEXT:    v_dual_cndmask_b32 v25, v32, v34 :: v_dual_lshlrev_b32 v34, 16, v15
-; GFX11-NEXT:    v_bfe_u32 v35, v13, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v32, 0x400000, v13
-; GFX11-NEXT:    v_bfe_u32 v33, v30, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-NEXT:    v_add3_u32 v31, v35, v13, 0x7fff
-; GFX11-NEXT:    v_lshrrev_b32_e32 v11, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 16, v24
-; GFX11-NEXT:    v_lshrrev_b32_e32 v39, 8, v50
-; GFX11-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-NEXT:    v_cndmask_b32_e32 v13, v31, v32, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v31, 0x40c00000, v34
-; GFX11-NEXT:    v_add3_u32 v32, v33, v30, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v33, 0x400000, v30
-; GFX11-NEXT:    v_bfe_u32 v34, v16, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-NEXT:    v_bfe_u32 v35, v31, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v30, v15, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v36, 0x400000, v31
-; GFX11-NEXT:    v_or_b32_e32 v37, 0x400000, v15
-; GFX11-NEXT:    v_cndmask_b32_e32 v32, v32, v33, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v33, v34, v16, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v34, 0x400000, v16
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-NEXT:    v_add3_u32 v35, v35, v31, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v30, v30, v15, 0x7fff
-; GFX11-NEXT:    v_perm_b32 v49, v13, v25, 0x7060302
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 16, v25
-; GFX11-NEXT:    v_cndmask_b32_e32 v16, v33, v34, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 16, v12
-; GFX11-NEXT:    v_lshrrev_b32_e32 v12, 16, v10
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v8, 16, v6
-; GFX11-NEXT:    v_cndmask_b32_e32 v31, v35, v36, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v20
-; GFX11-NEXT:    v_lshrrev_b32_e32 v48, 16, v49
-; GFX11-NEXT:    v_lshrrev_b32_e32 v53, 16, v54
-; GFX11-NEXT:    v_cndmask_b32_e32 v15, v30, v37, vcc_lo
-; GFX11-NEXT:    v_perm_b32 v37, v16, v32, 0x7060302
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v16, 16, v32
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v36, v15, v31, 0x7060302
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 16, v31
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v21
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 24, v37
-; GFX11-NEXT:    v_lshrrev_b64 v[17:18], 24, v[36:37]
-; GFX11-NEXT:    v_lshrrev_b64 v[18:19], 24, v[49:50]
-; GFX11-NEXT:    v_lshrrev_b64 v[19:20], 24, v[54:55]
-; GFX11-NEXT:    v_lshrrev_b64 v[20:21], 24, v[69:70]
-; GFX11-NEXT:    v_lshrrev_b64 v[21:22], 24, v[82:83]
-; GFX11-NEXT:    v_lshrrev_b64 v[22:23], 24, v[85:86]
-; GFX11-NEXT:    v_lshrrev_b64 v[23:24], 24, v[28:29]
-; GFX11-NEXT:    v_lshrrev_b64 v[24:25], 24, v[26:27]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 8, v37
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 16, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 8, v36
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 24, v50
-; GFX11-NEXT:    v_lshrrev_b32_e32 v49, 8, v49
-; GFX11-NEXT:    v_lshrrev_b32_e32 v50, 24, v55
-; GFX11-NEXT:    v_lshrrev_b32_e32 v54, 8, v54
-; GFX11-NEXT:    v_lshrrev_b32_e32 v55, 24, v70
-; GFX11-NEXT:    v_lshrrev_b32_e32 v69, 24, v83
-; GFX11-NEXT:    v_lshrrev_b32_e32 v70, 8, v83
-; GFX11-NEXT:    v_lshrrev_b32_e32 v82, 24, v86
-; GFX11-NEXT:    v_lshrrev_b32_e32 v83, 8, v86
-; GFX11-NEXT:    v_lshrrev_b32_e32 v85, 8, v85
-; GFX11-NEXT:    v_lshrrev_b32_e32 v86, 24, v29
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v29
-; GFX11-NEXT:    v_lshrrev_b32_e32 v28, 8, v28
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 8, v27
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v26
-; GFX11-NEXT:  .LBB54_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v25
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v97
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v24
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v25
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v27
-; GFX11-NEXT:    v_or_b32_e32 v24, v26, v24
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v81
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v96
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_lshlrev_b16 v28, 8, v28
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v25
-; GFX11-NEXT:    v_or_b32_e32 v25, v26, v27
-; GFX11-NEXT:    v_and_b32_e32 v81, 0xff, v87
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v24
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v29
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v23
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v28
-; GFX11-NEXT:    v_lshlrev_b16 v26, 8, v86
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v24
-; GFX11-NEXT:    v_lshlrev_b32_e32 v24, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v68
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v85
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v84
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v22
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_lshlrev_b16 v29, 8, v83
-; GFX11-NEXT:    v_and_b32_e32 v65, 0xff, v65
-; GFX11-NEXT:    v_lshlrev_b16 v68, 8, v82
-; GFX11-NEXT:    v_or_b32_e32 v23, v81, v23
-; GFX11-NEXT:    v_or_b32_e32 v25, v25, v26
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v27
-; GFX11-NEXT:    v_or_b32_e32 v22, v28, v22
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v29
-; GFX11-NEXT:    v_or_b32_e32 v26, v65, v68
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xffff, v6
-; GFX11-NEXT:    v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v24
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v23
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v25
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v22
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v26
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v80
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v71
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v21
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v70
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v52
-; GFX11-NEXT:    v_lshlrev_b16 v26, 8, v69
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v67
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v22
-; GFX11-NEXT:    v_or_b32_e32 v21, v23, v21
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v24
-; GFX11-NEXT:    v_or_b32_e32 v22, v25, v26
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v27
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v66
-; GFX11-NEXT:    v_lshlrev_b16 v20, 8, v20
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v64
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v38
-; GFX11-NEXT:    v_lshlrev_b16 v26, 8, v55
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v54
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v53
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v19
-; GFX11-NEXT:    v_or_b32_e32 v20, v23, v20
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v24
-; GFX11-NEXT:    v_or_b32_e32 v23, v25, v26
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v27
-; GFX11-NEXT:    v_or_b32_e32 v19, v28, v19
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xffff, v10
-; GFX11-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v21
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v22
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v20
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v23
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v19
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v51
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v33
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v50
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v49
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v48
-; GFX11-NEXT:    v_lshlrev_b16 v18, 8, v18
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v39
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v19
-; GFX11-NEXT:    v_or_b32_e32 v19, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v22
-; GFX11-NEXT:    v_or_b32_e32 v18, v23, v18
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v24
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v31
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v37
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX11-NEXT:    v_lshlrev_b16 v22, 8, v36
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v35
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v17
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_lshlrev_b16 v24, 8, v34
-; GFX11-NEXT:    v_and_b32_e32 v25, 0xff, v30
-; GFX11-NEXT:    v_lshlrev_b16 v26, 8, v32
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v22
-; GFX11-NEXT:    v_or_b32_e32 v17, v23, v17
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v24
-; GFX11-NEXT:    v_or_b32_e32 v21, v25, v26
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v13
-; GFX11-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xffff, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v15
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xffff, v16
-; GFX11-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v19
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v18
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v20
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v17
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v21
-; GFX11-NEXT:    s_clause 0x3
-; GFX11-NEXT:    scratch_store_b128 v0, v[1:4], off
-; GFX11-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
-; GFX11-NEXT:    scratch_store_b128 v0, v[9:12], off offset:32
-; GFX11-NEXT:    scratch_store_b128 v0, v[13:16], off offset:48
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v32bf16_to_v64i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v17
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr113_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr103_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr101_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr100_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr99_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr97_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr86_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr83_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr80_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr71_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr64_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr85_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr84_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr81_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB54_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v50, 8, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v51, 24, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v54, 8, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v55, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v64, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v66, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v69, 8, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v71, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v80, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v83, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v86, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v87, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v96, 8, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v97, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v98, 8, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v99, 8, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v100, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v101, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v102, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v103, 24, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v112, 8, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v113, 8, v1
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.h, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v26.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.h, v2.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v31.h, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.h, v4.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v35.h, v5.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v32.h, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v33.h, v6.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v49.h, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v34.h, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v8.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.h, v9.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v38.h, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v48.h, v10.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v70.h, v11.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v52.h, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.h, v12.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v85.h, v13.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v68.h, v14.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v67.h, v14.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v84.h, v15.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v81.h, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v82.h, v16.h
+; GFX11-TRUE16-NEXT:  .LBB54_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB54_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v18, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff0000, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff0000, v11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_add_f32 v17, 0x40c00000, v17
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v21, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, 0x400000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v17, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v17
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT:    v_add3_u32 v21, v21, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v20, v20, v17, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v18, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v26, v20, v22, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v18
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v26.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v20, v20, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v27, v21, v23, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v19
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v2, v27
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v28, v20, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v18, v4, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, 0x400000, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v103, 24, v2
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.l, v28.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v17, v22, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v18, v18, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v20, v1
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v112, 8, v2
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v30, v18, v22, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff0000, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v21, 0x40c00000, v21 :: v_dual_lshlrev_b32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v29, v17, v23, vcc_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v17.l, v30.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v4, v21, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, 0x400000, v21
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff0000, v5
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v18, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v19, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    v_add3_u32 v4, v4, v21, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT:    v_add3_u32 v18, v18, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v113, 8, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v31, v18, v19 :: v_dual_add_f32 v18, 0x40c00000, v22
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v31.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v21, v18, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v4, v23, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v4, 0xffff, v17, v29
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v6, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v18
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v3, 0xffff, v19, v3
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v21, v18, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v6, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v6
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v20, 16, 1
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v100, 24, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v101, 8, v4
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v102, 8, v3
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v32, v17, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v6, v20, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v33, v19, v22, vcc_lo
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff0000, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v20
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v18.l, v32.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v17, v17, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v35, v17, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v17, v8, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.l, v35.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v20, v6, v22, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v17, v8, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v17, 0x400000, v8
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v34, v6, v17 :: v_dual_add_f32 v19, 0x40c00000, v19
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v6, 0xffff, v18, v33
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v34.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v5, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v19
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v97, 24, v6
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v98, 8, v6
+; GFX11-TRUE16-NEXT:    v_add3_u32 v5, v5, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v36, v5, v22 :: v_dual_and_b32 v23, 0xffff0000, v7
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v5, 0xffff, v21, v20
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v10
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v8, 0xffff, v8, v36
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v99, 8, v5
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v20, 0x40c00000, v20 :: v_dual_add_f32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v86, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v87, 8, v8
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v19, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v7, v20, 16, 1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v49, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v17, 0x40c00000, v23 :: v_dual_add_f32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v7, v20, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v21, 0x400000, v20
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v23, 0xffff0000, v9
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v18, v17, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v17
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v10, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v18, v18, v17, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v19, v10, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v17, v18, v22, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v10
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v18.l, v49.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v38, v7, v21, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v48, v19, v22 :: v_dual_lshlrev_b32 v7, 16, v9
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v38.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_add_f32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v21, 0x40c00000, v10
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v10, 0xffff, v19, v48
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v24, v12, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v7, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v22, v21, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v37, 0x400000, v21
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v25, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v19, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v22, v22, v21, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v9, 0x40c00000, v23
+; GFX11-TRUE16-NEXT:    v_add3_u32 v24, v24, v12, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v50, 0x400000, v12
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v21, 0x40c00000, v39 :: v_dual_cndmask_b32 v52, v22, v37
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v20, v9, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, 0x400000, v9
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff0000, v14
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v65, v19, v25 :: v_dual_lshlrev_b32 v14, 16, v14
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT:    v_add3_u32 v20, v20, v9, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v52.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v19, v21, 16, 1
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v53, v24, v50, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v71, 24, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v80, 8, v10
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v25, v14, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v12, 0xffff, v7, v53
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v9, v20, v23, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v7, 0x40c00000, v11
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v19, v21, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v19, 0x400000, v21
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.l, v65.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v23, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v64, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v66, 8, v12
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v11, v11, v19, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v22
+; GFX11-TRUE16-NEXT:    v_add3_u32 v21, v23, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v23, 0xffff0000, v13
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v24, v19, 16, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v9, 0xffff, v20, v9
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v7, 0x40c00000, v23 :: v_dual_cndmask_b32 v70, v21, v22
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v21, v24, v19, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v22, 0x400000, v19
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT:    v_add3_u32 v23, v25, v14, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, 0x400000, v14
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v25, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v67, v21, v22, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v19, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_add3_u32 v14, v25, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff0000, v16
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v68, v23, v24, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v23, v13, 16, 1
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v83, 8, v9
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v16, 0x40c00000, v16
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.l, v68.h
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v7, v14, v19 :: v_dual_add_f32 v14, 0x40c00000, v21
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v15
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v23, v13, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v23, 0x400000, v13
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v16, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v21, 0x40c00000, v21
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v25, 0x400000, v16
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v85, v19, v23, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v13, v13, v16, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v23, v21, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v24, v14, 16, 1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v39, 0x400000, v21
+; GFX11-TRUE16-NEXT:    v_add3_u32 v23, v23, v21, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v81, v13, v25, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT:    v_add3_u32 v19, v24, v14, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v24, 0x400000, v14
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v37, v15, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, 0x400000, v15
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v84, v23, v39, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.l, v85.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v13, v37, v15, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v23.l, v70.h
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v14, 0xffff, v22, v67
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v82, v19, v24, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v81.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v84.h
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v11, 0xffff, v23, v11
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v51, 24, v14
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v13, v13, v16, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v16, 0xffff, v19, v82
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v54, 8, v14
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v69, 8, v11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v15, 0xffff, v15, v13
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v13, 0xffff, v21, v7
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v7, 0xffff, v18, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v50, 8, v15
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v55, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v96, 8, v7
+; GFX11-TRUE16-NEXT:  .LBB54_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v28.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v113.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v24.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v112.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v27.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v31.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v1.h, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v26.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v102.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v3.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v2.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v103.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v2.h, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.l, 8, v101.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.l, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v4.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.h, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v8
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v3.h, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v35.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v99.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v30.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v29.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v100.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.h, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v5.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v22.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v23, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v14, v8
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v49.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.l, 8, v96.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v10, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v34.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.l, 8, v87.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.h, 0xff, v36.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.l, 8, v86.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v65.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v83.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v8.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v16, v22
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v7.h, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v10.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.h, v11.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.h, 8, v20.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v32.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v98.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v9.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v8
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v38.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.h, 8, v80.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v48.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v71.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v7.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v5.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v10
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v11.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v7
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v23, v24
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v70.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v69.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v16, v21
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v12, v22
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v14, v19
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v52.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v66.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v53.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.l, 8, v64.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.h, 0xff, v85.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.l, 8, v55.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v13.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.l, 8, v18.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v16.h, 0xff, v68.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v17.h, 8, v54.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v33.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v97.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v14.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.h, v15.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v13.h, v16.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v16.h, v17.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v11.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v20, v23
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v18.l, v15.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v19, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v13
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff, v14
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff, v16
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v67.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v51.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v84.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v50.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v15.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.l, 0xff, v81.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v15.h, 8, v39.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v16.l, 0xff, v82.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v16.h, 8, v37.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v13.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v14.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v15.l, v15.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v16.l, v16.h
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v25, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, v24, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v23, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v14
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v25, 0xffff, v15
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, v19, v20
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, v21, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, v22, v17
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v15, v23, v24
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, v25, v16
+; GFX11-TRUE16-NEXT:    s_clause 0x3
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[9:12], off offset:32
+; GFX11-TRUE16-NEXT:    scratch_store_b128 v0, v[13:16], off offset:48
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v32bf16_to_v64i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB54_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[3:4]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[1:2]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v49, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v50, 24, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v51, 8, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v53, 16, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v54, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v55, 24, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v64, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v66, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v67, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v69, 24, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v52, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v70, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v82, 24, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v65, 16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v85, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v86, 24, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v68, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v81, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v97, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-FAKE16-NEXT:  .LBB54_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB54_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v18, 0x40c00000, v18
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v19, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v1, v17, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, 0x400000, v17
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v22, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v24, v19, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v1, v1, v17, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_add3_u32 v22, v22, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v1, v20 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    v_add3_u32 v20, v24, v19, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v21, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v21, v23 :: v_dual_lshlrev_b32 v21, 16, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, 0x400000, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v27, v2, v1, 0x7060302
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_lshlrev_b32 v21, 16, v3
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v22, v17, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v18
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v21, 0x40c00000, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v19, v20, v23, vcc_lo
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v20, v18, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v24, v21, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v26, v19, v17, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v19, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v20, v20, v18, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v81, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v17
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v19, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v20, v22, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, 0x400000, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 24, v27
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v97, 16, v26
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v19, v23 :: v_dual_lshlrev_b32 v23, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    v_add3_u32 v19, v24, v21, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-FAKE16-NEXT:    v_perm_b32 v29, v4, v18, 0x7060302
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v20, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v19, v19, v22 :: v_dual_lshlrev_b32 v22, 16, v5
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v21, 0x40c00000, v23
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v20, v20, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v68, 16, v4
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, 0x400000, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v18
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v20, v24, vcc_lo
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v20, v21, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, 0x400000, v6
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v25, v22, 16, 1
+; GFX11-FAKE16-NEXT:    v_perm_b32 v28, v3, v19, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v6, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v20, v20, v21, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 16, v28
+; GFX11-FAKE16-NEXT:    v_add3_u32 v3, v3, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v20, v20, v23 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v25, v22, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, 0x400000, v22
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v24, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v8
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, 0x400000, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v21, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v22, v6, v23, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v6, 0x40c00000, v24
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v7
+; GFX11-FAKE16-NEXT:    v_perm_b32 v86, v3, v20, 0x7060302
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, 0x400000, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v5, v21, v25 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v6, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v65, 16, v3
+; GFX11-FAKE16-NEXT:    v_perm_b32 v85, v5, v22, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v5, v8, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v21, v6, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, 0x400000, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 16, v85
+; GFX11-FAKE16-NEXT:    v_add3_u32 v5, v5, v8, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v21, v24, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v5, v25, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v10
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v23, 0x40c00000, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-FAKE16-NEXT:    v_perm_b32 v83, v5, v6, 0x7060302
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v52, 16, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v30, v23, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, 0x400000, v23
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v22
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v30, v23, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v23, v8, v24 :: v_dual_lshlrev_b32 v24, 16, v9
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v24, 0x40c00000, v24
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v8, 0x40c00000, v25
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v31, v24, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, 0x400000, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v21, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v21, v30, vcc_lo
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v8, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, 0x400000, v10
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v82, v7, v23, 0x7060302
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v7, v10, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v21, v8, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 16, v82
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v7, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v21, v25, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    v_add3_u32 v10, v31, v24, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, 0x400000, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 8, v82
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v7, v7, v30 :: v_dual_lshlrev_b32 v30, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v70, v7, v8, 0x7060302
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v38, 16, v7
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v24, v10, v25, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v10, 0x40c00000, v30
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v23
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v64, 8, v70
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v30, v12, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v30, v30, v12, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v21, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v21, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v21, v31, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v11
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v25, v10, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-FAKE16-NEXT:    v_perm_b32 v69, v9, v24, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v9, 0x40c00000, v21
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v25, v10, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, 0x400000, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, 0x400000, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v9, 16, 1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v66, 16, v69
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v21, v25, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, 0x400000, v9
+; GFX11-FAKE16-NEXT:    v_add3_u32 v21, v32, v9, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v67, 8, v69
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v30, v31, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-FAKE16-NEXT:    v_perm_b32 v55, v12, v10, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v21, v25, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v21, 0x40c00000, v30
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v31, v11, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v30, 0x400000, v11
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v21, 16, 1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v51, 8, v55
+; GFX11-FAKE16-NEXT:    v_add3_u32 v25, v31, v11, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v25, v30, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v25, 0x40c00000, v31
+; GFX11-FAKE16-NEXT:    v_add3_u32 v30, v32, v21, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, 0x400000, v21
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v32, v14, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v25, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v34, 0x400000, v25
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v21, v30, v31, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v30, v32, v14, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v31, 0x400000, v14
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v33, v25, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v33, 16, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v14, v30, v31, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v30, 0x40c00000, v33
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v16, 0x40c00000, v16
+; GFX11-FAKE16-NEXT:    v_perm_b32 v54, v11, v9, 0x7060302
+; GFX11-FAKE16-NEXT:    v_perm_b32 v50, v14, v21, 0x7060302
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v25, v32, v34 :: v_dual_lshlrev_b32 v34, 16, v15
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v13, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v32, 0x400000, v13
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v33, v30, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-FAKE16-NEXT:    v_add3_u32 v31, v35, v13, 0x7fff
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v11, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v24
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 8, v50
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v13, v31, v32, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v31, 0x40c00000, v34
+; GFX11-FAKE16-NEXT:    v_add3_u32 v32, v33, v30, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v33, 0x400000, v30
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v34, v16, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v35, v31, 16, 1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v30, v15, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v36, 0x400000, v31
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v37, 0x400000, v15
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v32, v33, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v33, v34, v16, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v34, 0x400000, v16
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-FAKE16-NEXT:    v_add3_u32 v35, v35, v31, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add3_u32 v30, v30, v15, 0x7fff
+; GFX11-FAKE16-NEXT:    v_perm_b32 v49, v13, v25, 0x7060302
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 16, v25
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v33, v34, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v12
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v12, 16, v10
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v6
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v31, v35, v36, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v20
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v49
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v53, 16, v54
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v15, v30, v37, vcc_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v37, v16, v32, 0x7060302
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 16, v32
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v36, v15, v31, 0x7060302
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 16, v31
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v21
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 24, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[17:18], 24, v[36:37]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[18:19], 24, v[49:50]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[19:20], 24, v[54:55]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[20:21], 24, v[69:70]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[21:22], 24, v[82:83]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[22:23], 24, v[85:86]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[23:24], 24, v[28:29]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[24:25], 24, v[26:27]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 8, v37
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 8, v36
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v50
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v49, 8, v49
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v50, 24, v55
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v54, 8, v54
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v55, 24, v70
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v69, 24, v83
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v70, 8, v83
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v82, 24, v86
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 8, v86
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v85, 8, v85
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v86, 24, v29
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v29
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 8, v28
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v26
+; GFX11-FAKE16-NEXT:  .LBB54_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v97
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v24, v26, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v81
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v96
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v28, 8, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v26, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v81, 0xff, v87
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v29
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v26, 8, v86
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v68
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v84
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v29, 8, v83
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v65, 0xff, v65
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v68, 8, v82
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v81, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v25, v25, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v28, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v26, v65, v68
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v71
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v70
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v52
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v26, 8, v69
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v23, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v25, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v66
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v20, 8, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v64
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v38
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v26, 8, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v54
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v53
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v23, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v25, v26
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v28, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v51
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v50
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v49
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v48
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v18, 8, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v23, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v37
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v22, 8, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v24, 8, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v26, 8, v32
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v23, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v24
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v25, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v20
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v21
+; GFX11-FAKE16-NEXT:    s_clause 0x3
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[1:4], off
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[5:8], off offset:16
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[9:12], off offset:32
+; GFX11-FAKE16-NEXT:    scratch_store_b128 v0, v[13:16], off offset:48
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -41241,409 +47913,795 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v64i8_to_v32bf16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v32, v14 :: v_dual_mov_b32 v31, v8
-; GFX11-NEXT:    v_dual_mov_b32 v34, v12 :: v_dual_mov_b32 v35, v10
-; GFX11-NEXT:    v_dual_mov_b32 v38, v6 :: v_dual_mov_b32 v33, v4
-; GFX11-NEXT:    v_dual_mov_b32 v37, v2 :: v_dual_mov_b32 v36, v0
-; GFX11-NEXT:    s_clause 0x1f
-; GFX11-NEXT:    scratch_load_u16 v0, off, s32 offset:128
-; GFX11-NEXT:    scratch_load_u16 v67, off, s32 offset:124
-; GFX11-NEXT:    scratch_load_u16 v2, off, s32 offset:120
-; GFX11-NEXT:    scratch_load_u16 v70, off, s32 offset:116
-; GFX11-NEXT:    scratch_load_u16 v4, off, s32 offset:112
-; GFX11-NEXT:    scratch_load_u16 v66, off, s32 offset:108
-; GFX11-NEXT:    scratch_load_u16 v6, off, s32 offset:104
-; GFX11-NEXT:    scratch_load_u16 v69, off, s32 offset:100
-; GFX11-NEXT:    scratch_load_u16 v8, off, s32 offset:96
-; GFX11-NEXT:    scratch_load_u16 v64, off, s32 offset:92
-; GFX11-NEXT:    scratch_load_u16 v10, off, s32 offset:88
-; GFX11-NEXT:    scratch_load_b32 v12, off, s32 offset:132
-; GFX11-NEXT:    scratch_load_u16 v14, off, s32
-; GFX11-NEXT:    scratch_load_u16 v96, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_u16 v100, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_u16 v101, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_u16 v102, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_u16 v103, off, s32 offset:40
-; GFX11-NEXT:    scratch_load_u16 v113, off, s32 offset:48
-; GFX11-NEXT:    scratch_load_u16 v114, off, s32 offset:56
-; GFX11-NEXT:    scratch_load_u16 v115, off, s32 offset:64
-; GFX11-NEXT:    scratch_load_u16 v116, off, s32 offset:72
-; GFX11-NEXT:    scratch_load_u16 v117, off, s32 offset:80
-; GFX11-NEXT:    scratch_load_u16 v99, off, s32 offset:84
-; GFX11-NEXT:    scratch_load_u16 v85, off, s32 offset:76
-; GFX11-NEXT:    scratch_load_u16 v97, off, s32 offset:68
-; GFX11-NEXT:    scratch_load_u16 v82, off, s32 offset:60
-; GFX11-NEXT:    scratch_load_u16 v86, off, s32 offset:52
-; GFX11-NEXT:    scratch_load_u16 v84, off, s32 offset:44
-; GFX11-NEXT:    scratch_load_u16 v87, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_u16 v68, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_u16 v80, off, s32 offset:20
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_u16 v65, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_u16 v71, off, s32 offset:4
-; GFX11-NEXT:    v_lshlrev_b16 v50, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v51, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v49, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v39, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v54, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v48, 8, v11
-; GFX11-NEXT:    v_lshlrev_b16 v55, 8, v13
-; GFX11-NEXT:    v_lshlrev_b16 v52, 8, v15
-; GFX11-NEXT:    v_lshlrev_b16 v53, 8, v17
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v19
-; GFX11-NEXT:    v_lshlrev_b16 v83, 8, v21
-; GFX11-NEXT:    v_lshlrev_b16 v81, 8, v23
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v25
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v29
-; GFX11-NEXT:    s_waitcnt vmcnt(33)
-; GFX11-NEXT:    v_lshlrev_b16 v119, 8, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(31)
-; GFX11-NEXT:    v_lshlrev_b16 v118, 8, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(22)
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v12
-; GFX11-NEXT:    s_waitcnt vmcnt(21)
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v14
-; GFX11-NEXT:    s_waitcnt vmcnt(20)
-; GFX11-NEXT:    v_lshlrev_b16 v98, 8, v96
-; GFX11-NEXT:    s_waitcnt vmcnt(19)
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v100
-; GFX11-NEXT:    s_waitcnt vmcnt(18)
-; GFX11-NEXT:    v_lshlrev_b16 v96, 8, v101
-; GFX11-NEXT:    s_waitcnt vmcnt(17)
-; GFX11-NEXT:    v_lshlrev_b16 v29, 8, v102
-; GFX11-NEXT:    s_waitcnt vmcnt(16)
-; GFX11-NEXT:    v_lshlrev_b16 v112, 8, v103
-; GFX11-NEXT:    s_waitcnt vmcnt(15)
-; GFX11-NEXT:    v_lshlrev_b16 v103, 8, v113
-; GFX11-NEXT:    s_waitcnt vmcnt(14)
-; GFX11-NEXT:    v_lshlrev_b16 v101, 8, v114
-; GFX11-NEXT:    s_waitcnt vmcnt(13)
-; GFX11-NEXT:    v_lshlrev_b16 v100, 8, v115
-; GFX11-NEXT:    s_waitcnt vmcnt(12)
-; GFX11-NEXT:    v_lshlrev_b16 v114, 8, v116
-; GFX11-NEXT:    s_waitcnt vmcnt(11)
-; GFX11-NEXT:    v_lshlrev_b16 v102, 8, v117
-; GFX11-NEXT:    v_lshlrev_b16 v117, 8, v10
-; GFX11-NEXT:    v_lshlrev_b16 v113, 8, v8
-; GFX11-NEXT:    v_lshlrev_b16 v116, 8, v6
-; GFX11-NEXT:    v_lshlrev_b16 v115, 8, v4
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB55_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB55_4
-; GFX11-NEXT:  .LBB55_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB55_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v36
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v37
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v38
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v31
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff, v35
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v50
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v51
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v34
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v33
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v16
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v18
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    v_or_b32_e32 v1, v3, v39
-; GFX11-NEXT:    v_or_b32_e32 v3, v4, v54
-; GFX11-NEXT:    v_or_b32_e32 v4, v5, v48
-; GFX11-NEXT:    v_or_b32_e32 v5, v6, v55
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v32
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v20
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v22
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v49
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v53
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v52
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v17
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v83
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v81
-; GFX11-NEXT:    v_perm_b32 v1, v1, v2, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v2, v4, v3, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v3, v6, v5, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v4, v8, v7, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v5, v10, v9, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v24
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v26
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v30
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v71
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v65
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v80
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v68
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v87
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v84
-; GFX11-NEXT:    v_or_b32_e32 v6, v6, v21
-; GFX11-NEXT:    v_or_b32_e32 v7, v7, v19
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v27
-; GFX11-NEXT:    v_or_b32_e32 v9, v9, v23
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v98
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v25
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v96
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v29
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v112
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v103
-; GFX11-NEXT:    v_perm_b32 v6, v7, v6, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v7, v9, v8, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v8, v11, v10, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v9, v13, v12, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v10, v15, v14, 0x5040100
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v86
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v82
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v97
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v85
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v99
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v64
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v69
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v66
-; GFX11-NEXT:    v_and_b32_e32 v19, 0xff, v70
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v67
-; GFX11-NEXT:    v_or_b32_e32 v11, v11, v101
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v100
-; GFX11-NEXT:    v_or_b32_e32 v13, v13, v114
-; GFX11-NEXT:    v_or_b32_e32 v14, v14, v102
-; GFX11-NEXT:    v_or_b32_e32 v15, v15, v117
-; GFX11-NEXT:    v_or_b32_e32 v16, v16, v113
-; GFX11-NEXT:    v_or_b32_e32 v17, v17, v116
-; GFX11-NEXT:    v_or_b32_e32 v18, v18, v115
-; GFX11-NEXT:    v_or_b32_e32 v19, v19, v118
-; GFX11-NEXT:    v_or_b32_e32 v20, v20, v119
-; GFX11-NEXT:    v_perm_b32 v11, v12, v11, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v12, v14, v13, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v13, v16, v15, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v14, v18, v17, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v15, v20, v19, 0x5040100
-; GFX11-NEXT:    ; implicit-def: $vgpr36
-; GFX11-NEXT:    ; implicit-def: $vgpr37
-; GFX11-NEXT:    ; implicit-def: $vgpr33
-; GFX11-NEXT:    ; implicit-def: $vgpr38
-; GFX11-NEXT:    ; implicit-def: $vgpr31
-; GFX11-NEXT:    ; implicit-def: $vgpr35
-; GFX11-NEXT:    ; implicit-def: $vgpr34
-; GFX11-NEXT:    ; implicit-def: $vgpr32
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr18
-; GFX11-NEXT:    ; implicit-def: $vgpr20
-; GFX11-NEXT:    ; implicit-def: $vgpr22
-; GFX11-NEXT:    ; implicit-def: $vgpr24
-; GFX11-NEXT:    ; implicit-def: $vgpr26
-; GFX11-NEXT:    ; implicit-def: $vgpr28
-; GFX11-NEXT:    ; implicit-def: $vgpr30
-; GFX11-NEXT:    ; implicit-def: $vgpr71
-; GFX11-NEXT:    ; implicit-def: $vgpr65
-; GFX11-NEXT:    ; implicit-def: $vgpr80
-; GFX11-NEXT:    ; implicit-def: $vgpr68
-; GFX11-NEXT:    ; implicit-def: $vgpr87
-; GFX11-NEXT:    ; implicit-def: $vgpr84
-; GFX11-NEXT:    ; implicit-def: $vgpr86
-; GFX11-NEXT:    ; implicit-def: $vgpr82
-; GFX11-NEXT:    ; implicit-def: $vgpr97
-; GFX11-NEXT:    ; implicit-def: $vgpr85
-; GFX11-NEXT:    ; implicit-def: $vgpr99
-; GFX11-NEXT:    ; implicit-def: $vgpr64
-; GFX11-NEXT:    ; implicit-def: $vgpr69
-; GFX11-NEXT:    ; implicit-def: $vgpr66
-; GFX11-NEXT:    ; implicit-def: $vgpr70
-; GFX11-NEXT:    ; implicit-def: $vgpr67
-; GFX11-NEXT:    ; implicit-def: $vgpr50
-; GFX11-NEXT:    ; implicit-def: $vgpr51
-; GFX11-NEXT:    ; implicit-def: $vgpr49
-; GFX11-NEXT:    ; implicit-def: $vgpr39
-; GFX11-NEXT:    ; implicit-def: $vgpr54
-; GFX11-NEXT:    ; implicit-def: $vgpr48
-; GFX11-NEXT:    ; implicit-def: $vgpr55
-; GFX11-NEXT:    ; implicit-def: $vgpr52
-; GFX11-NEXT:    ; implicit-def: $vgpr53
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr83
-; GFX11-NEXT:    ; implicit-def: $vgpr81
-; GFX11-NEXT:    ; implicit-def: $vgpr21
-; GFX11-NEXT:    ; implicit-def: $vgpr19
-; GFX11-NEXT:    ; implicit-def: $vgpr27
-; GFX11-NEXT:    ; implicit-def: $vgpr23
-; GFX11-NEXT:    ; implicit-def: $vgpr98
-; GFX11-NEXT:    ; implicit-def: $vgpr25
-; GFX11-NEXT:    ; implicit-def: $vgpr96
-; GFX11-NEXT:    ; implicit-def: $vgpr29
-; GFX11-NEXT:    ; implicit-def: $vgpr112
-; GFX11-NEXT:    ; implicit-def: $vgpr103
-; GFX11-NEXT:    ; implicit-def: $vgpr101
-; GFX11-NEXT:    ; implicit-def: $vgpr100
-; GFX11-NEXT:    ; implicit-def: $vgpr114
-; GFX11-NEXT:    ; implicit-def: $vgpr102
-; GFX11-NEXT:    ; implicit-def: $vgpr117
-; GFX11-NEXT:    ; implicit-def: $vgpr113
-; GFX11-NEXT:    ; implicit-def: $vgpr116
-; GFX11-NEXT:    ; implicit-def: $vgpr115
-; GFX11-NEXT:    ; implicit-def: $vgpr118
-; GFX11-NEXT:    ; implicit-def: $vgpr119
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB55_2
-; GFX11-NEXT:  .LBB55_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v70, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v67, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v69, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v66, 3
-; GFX11-NEXT:    v_add_nc_u16 v5, v64, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    s_waitcnt vmcnt(8)
-; GFX11-NEXT:    v_add_nc_u16 v6, v97, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v0, v118, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v119, v1
-; GFX11-NEXT:    v_add_nc_u16 v4, v99, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add_nc_u16 v15, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v64, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v0, v116, v2
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v5
-; GFX11-NEXT:    v_or_b32_e32 v2, v115, v3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_add_nc_u16 v14, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v113, v1
-; GFX11-NEXT:    v_add_nc_u16 v66, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v1, v114, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v117, v4
-; GFX11-NEXT:    v_add_nc_u16 v2, v85, 3
-; GFX11-NEXT:    v_add_nc_u16 v67, 0x300, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(6)
-; GFX11-NEXT:    v_add_nc_u16 v0, v86, 3
-; GFX11-NEXT:    v_add_nc_u16 v12, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v82, 3
-; GFX11-NEXT:    v_add_nc_u16 v13, 0x300, v4
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(4)
-; GFX11-NEXT:    v_add_nc_u16 v3, v87, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v4, v84, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v102, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v0, v101, v0
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v1, v100, v1
-; GFX11-NEXT:    v_add_nc_u16 v69, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v112, v3
-; GFX11-NEXT:    v_add_nc_u16 v11, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v103, v4
-; GFX11-NEXT:    v_add_nc_u16 v70, 0x300, v1
-; GFX11-NEXT:    s_waitcnt vmcnt(2)
-; GFX11-NEXT:    v_add_nc_u16 v1, v80, 3
-; GFX11-NEXT:    v_add_nc_u16 v10, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v68, 3
-; GFX11-NEXT:    v_add_nc_u16 v68, 0x300, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_nc_u16 v0, v71, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v3, v65, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v4, v28, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v96, v1
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v29, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v0, v98, v0
-; GFX11-NEXT:    v_add_nc_u16 v9, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v25, v3
-; GFX11-NEXT:    v_add_nc_u16 v25, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v27, v4
-; GFX11-NEXT:    v_add_nc_u16 v8, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v30, 3
-; GFX11-NEXT:    v_add_nc_u16 v27, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v24, 3
-; GFX11-NEXT:    v_add_nc_u16 v7, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v26, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v3, v20, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_add_nc_u16 v4, v22, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_or_b32_e32 v0, v23, v0
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v1, v21, v1
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v2, v19, v2
-; GFX11-NEXT:    v_add_nc_u16 v19, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v83, v3
-; GFX11-NEXT:    v_add_nc_u16 v6, 0x300, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v81, v4
-; GFX11-NEXT:    v_add_nc_u16 v20, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v2, v16, 3
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v0, v34, 3
-; GFX11-NEXT:    v_add_nc_u16 v16, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v31, 3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, v18, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_add_nc_u16 v4, v32, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v53, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v0, v55, v0
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_or_b32_e32 v1, v54, v1
-; GFX11-NEXT:    v_add_nc_u16 v18, 0x300, v2
-; GFX11-NEXT:    v_or_b32_e32 v2, v17, v3
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v52, v4
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v1, v33, 3
-; GFX11-NEXT:    v_add_nc_u16 v17, v36, 3
-; GFX11-NEXT:    v_add_nc_u16 v21, v37, 3
-; GFX11-NEXT:    v_add_nc_u16 v22, v38, 3
-; GFX11-NEXT:    v_add_nc_u16 v23, v35, 3
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v17
-; GFX11-NEXT:    v_and_b32_e32 v21, 0xff, v21
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v22
-; GFX11-NEXT:    v_and_b32_e32 v23, 0xff, v23
-; GFX11-NEXT:    v_or_b32_e32 v1, v49, v1
-; GFX11-NEXT:    v_or_b32_e32 v17, v50, v17
-; GFX11-NEXT:    v_or_b32_e32 v21, v51, v21
-; GFX11-NEXT:    v_or_b32_e32 v22, v39, v22
-; GFX11-NEXT:    v_or_b32_e32 v23, v48, v23
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v17, 0x300, v17
-; GFX11-NEXT:    v_add_nc_u16 v21, 0x300, v21
-; GFX11-NEXT:    v_add_nc_u16 v22, 0x300, v22
-; GFX11-NEXT:    v_add_nc_u16 v23, 0x300, v23
-; GFX11-NEXT:    v_add_nc_u16 v24, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v26, 0x300, v2
-; GFX11-NEXT:    v_perm_b32 v0, v21, v17, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v1, v22, v1, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v2, v23, v4, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v3, v24, v3, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v4, v26, v18, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v5, v16, v5, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v6, v20, v6, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v7, v19, v7, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v8, v27, v8, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v9, v25, v9, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v10, v68, v10, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v11, v70, v11, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v12, v69, v12, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v13, v67, v13, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v14, v66, v14, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v15, v64, v15, 0x5040100
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v64i8_to_v32bf16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1f
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v55, off, s32 offset:128
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v32, off, s32 offset:124
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v55, off, s32 offset:120
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v33, off, s32 offset:116
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v53, off, s32 offset:112
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v31, off, s32 offset:108
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v53, off, s32 offset:104
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v32, off, s32 offset:100
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v52, off, s32 offset:96
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v31, off, s32 offset:92
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v54, off, s32 offset:88
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v66, off, s32 offset:132
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v39, off, s32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v48, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v48, off, s32 offset:16
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v50, off, s32 offset:24
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v50, off, s32 offset:32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v51, off, s32 offset:40
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v52, off, s32 offset:48
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v54, off, s32 offset:56
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v64, off, s32 offset:64
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v64, off, s32 offset:72
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v65, off, s32 offset:80
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v38, off, s32 offset:84
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v36, off, s32 offset:76
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v38, off, s32 offset:68
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v35, off, s32 offset:60
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v37, off, s32 offset:52
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v36, off, s32 offset:44
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v37, off, s32 offset:36
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v34, off, s32 offset:28
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v34, off, s32 offset:20
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_d16_hi_b16 v33, off, s32 offset:12
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v35, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.h, v29.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.l, v27.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.h, v25.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v39.l, v23.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.h, v21.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v26.h, v19.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v25.h, v17.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.h, v22.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v24.h, v20.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.h, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v17.h, v14.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.h, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.l, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v17.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v18.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v23.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.l, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v20.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v27.l, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v22.l, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v27.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v25.l, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v25.h, 8, v25.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v26.h, 8, v26.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v30.h, 8, v30.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v39.l, 8, v39.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v28.h, 8, v28.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v29.l, 8, v29.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v49.l, 8, v29.h
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v55.h, 8, v55.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v55.l, 8, v55.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(29)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v53.h, 8, v53.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(27)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v53.l, 8, v53.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(25)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v52.h, 8, v52.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(23)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v54.h, 8, v54.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(21)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v29.h, 8, v39.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(20)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v49.h, 8, v48.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(19)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v39.h, 8, v48.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(18)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v48.l, 8, v50.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(17)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v48.h, 8, v50.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(16)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v51.h, 8, v51.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(15)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v52.l, 8, v52.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(14)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v50.l, 8, v54.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(13)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v50.h, 8, v64.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(12)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v54.l, 8, v64.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(11)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v51.l, 8, v65.l
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v66
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB55_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB55_4
+; GFX11-TRUE16-NEXT:  .LBB55_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB55_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v18.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v17.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v16.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v16.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v21.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v17.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v19.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v24.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v22.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v26.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v30.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v35.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v33.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v34.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.h, 0xff, v34.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v37.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.h, 0xff, v36.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v37.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.h, 0xff, v35.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v38.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.h, 0xff, v36.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v38.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.h, 0xff, v31.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v32.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.h, 0xff, v31.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.l, 0xff, v33.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.h, 0xff, v32.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v23.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v23.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v20.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v1.h, v20.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v27.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v2.h, v22.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.l, v27.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v3.h, v25.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v25.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.h, v4.h, v26.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v5.l, v30.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.h, v5.h, v39.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v6.l, v28.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v6.h, v29.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v49.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.h, v7.h, v29.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v49.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.h, v8.h, v39.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v9.l, v48.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.h, v9.h, v48.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v10.l, v51.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.h, v10.h, v52.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v11.l, v50.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.h, v11.h, v50.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v54.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.h, v12.h, v51.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v13.l, v54.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.h, v13.h, v52.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.l, v14.l, v53.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v14.h, v14.h, v53.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.l, v15.l, v55.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v15.h, v15.h, v55.h
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr36_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr38_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr31_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr20_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr30_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr28_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr29_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB55_2
+; GFX11-TRUE16-NEXT:  .LBB55_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v33.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v32.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v32.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v31.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v31.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(8)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, v38.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v55.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v55.h, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v38.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v53.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v53.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v15.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v3.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v14.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v35.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v52.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v54.l, v0.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v37.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v36.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v37.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v54.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v50.h, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v51.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v13.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v36.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v51.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v50.l, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v35.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v12.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v11.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v34.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v34.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v33.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v52.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v49.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v48.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v48.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v39.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v10.h, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v28.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v9.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v8.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v30.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v24.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v26.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v24.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v49.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v29.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v28.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v29.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v30.h, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v22.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v7.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v6.h, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v19.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v18.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v21.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v17.h, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v39.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v25.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v26.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v27.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v25.l, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v5.h, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v21.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.h, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.h, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v16.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v19.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v16.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v18.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v17.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v27.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v22.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v20.l, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v20.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.h, v23.l, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v23.h, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, 0x300, v16.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v16.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, 0x300, v17.l
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v32bf16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v32, v14 :: v_dual_mov_b32 v31, v8
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v34, v12 :: v_dual_mov_b32 v35, v10
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v38, v6 :: v_dual_mov_b32 v33, v4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v37, v2 :: v_dual_mov_b32 v36, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x1f
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v0, off, s32 offset:128
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v67, off, s32 offset:124
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s32 offset:120
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v70, off, s32 offset:116
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v4, off, s32 offset:112
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v66, off, s32 offset:108
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v6, off, s32 offset:104
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v69, off, s32 offset:100
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v8, off, s32 offset:96
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v64, off, s32 offset:92
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v10, off, s32 offset:88
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v12, off, s32 offset:132
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v14, off, s32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v96, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v100, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v101, off, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v102, off, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v103, off, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v113, off, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v114, off, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v115, off, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v116, off, s32 offset:72
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v117, off, s32 offset:80
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v99, off, s32 offset:84
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v85, off, s32 offset:76
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v97, off, s32 offset:68
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v82, off, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v86, off, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v84, off, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v87, off, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v68, off, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v80, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v65, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v71, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v50, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v51, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v49, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v39, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v54, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v48, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v55, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v52, 8, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v53, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v83, 8, v21
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v81, 8, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v25
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v29
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(33)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v119, 8, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(31)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v118, 8, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(22)
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v12
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(21)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v14
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(20)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v98, 8, v96
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(19)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v100
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(18)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v96, 8, v101
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(17)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v29, 8, v102
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(16)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v112, 8, v103
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(15)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v103, 8, v113
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(14)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v101, 8, v114
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(13)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v100, 8, v115
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(12)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v114, 8, v116
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(11)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v102, 8, v117
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v117, 8, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v113, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v116, 8, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v115, 8, v4
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB55_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB55_4
+; GFX11-FAKE16-NEXT:  .LBB55_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB55_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v36
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v37
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v38
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v35
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v50
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v51
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v33
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v39
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v4, v54
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v5, v48
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v55
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v32
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v49
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v53
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v52
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v83
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v81
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v4, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v6, v5, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v8, v7, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v10, v9, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v30
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v71
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v65
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v80
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v68
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v87
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v84
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v19
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v9, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v98
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v96
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v112
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v103
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v7, v6, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v9, v8, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v11, v10, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v13, v12, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v15, v14, 0x5040100
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v86
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v82
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v97
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v85
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v99
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v64
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v69
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v66
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xff, v70
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v67
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v11, v101
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v100
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v13, v114
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v14, v102
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v15, v15, v117
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, v16, v113
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v17, v116
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v18, v18, v115
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v19, v19, v118
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v20, v20, v119
+; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v12, v11, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v14, v13, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v16, v15, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v18, v17, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v20, v19, 0x5040100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr35
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr71
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr68
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr87
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr86
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr82
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr85
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr99
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr66
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr70
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr67
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr50
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr49
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr83
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr21
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr23
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr98
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr25
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr112
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr103
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr114
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr102
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr117
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr115
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr118
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr119
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB55_2
+; GFX11-FAKE16-NEXT:  .LBB55_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v70, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v67, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v69, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v66, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, v64, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(8)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v97, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v118, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v119, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v99, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v15, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v64, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v116, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v115, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v14, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v113, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v66, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v114, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v117, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v85, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v67, 0x300, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(6)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v86, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v12, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v82, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v13, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(4)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v87, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v84, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v102, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v101, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v100, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v69, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v112, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v11, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v103, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v70, 0x300, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v80, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v10, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v68, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v68, 0x300, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v71, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v65, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v28, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v96, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v29, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v98, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v9, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v25, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v25, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v27, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v30, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v27, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v24, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v7, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v26, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v20, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v22, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v23, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v21, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v19, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v19, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v83, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v81, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v20, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v16, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v34, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v16, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v31, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v18, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v32, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v53, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v55, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v54, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v18, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v17, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v52, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v33, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, v36, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, v37, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, v38, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v23, v35, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v21, 0xff, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xff, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v49, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v17, v50, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v21, v51, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v22, v39, v22
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v23, v48, v23
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v17, 0x300, v17
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v21, 0x300, v21
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v22, 0x300, v22
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v23, 0x300, v23
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v24, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v26, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v21, v17, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v22, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v23, v4, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v24, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v26, v18, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v16, v5, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v20, v6, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v19, v7, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v27, v8, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v25, v9, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v68, v10, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v70, v11, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v69, v12, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v67, v13, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v66, v14, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v64, v15, 0x5040100
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
index 26ce1771e220d..42b2f9a168cb3 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
@@ -3,7 +3,8 @@
 ; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define double @bitcast_i64_to_f64(i64 %a, i32 %b) {
 ; GCN-LABEL: bitcast_i64_to_f64:
@@ -1104,52 +1105,106 @@ define i64 @bitcast_v4bf16_to_i64(<4 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v4bf16_to_i64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v2
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB11_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v0
-; GFX11-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v8, v3, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v3
-; GFX11-NEXT:    v_bfe_u32 v4, v2, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v5, 0x400000, v2
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_add3_u32 v8, v8, v3, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_bfe_u32 v9, v1, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v6, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v7, 0x400000, v0
-; GFX11-NEXT:    v_add3_u32 v9, v9, v1, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_add3_u32 v6, v6, v0, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v4, 0x400000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v6, v7, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v8, v10, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc_lo
-; GFX11-NEXT:    v_perm_b32 v0, v0, v2, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_perm_b32 v1, v3, v1, 0x7060302
-; GFX11-NEXT:  .LBB11_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_i64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v2
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB11_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v7, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v7, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v1, v7, v10 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v4, v2, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v0, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v3
+; GFX11-TRUE16-NEXT:  .LBB11_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_i64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v2
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB11_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v4, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v8, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v1, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v6, v7, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v2, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v1, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB11_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -1285,47 +1340,83 @@ define <8 x i8> @bitcast_i64_to_v8i8(i64 %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v4, v9
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_i64_to_v8i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
-; GFX11-NEXT:  ; %bb.2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB12_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_co_u32 v8, vcc_lo, v8, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
-; GFX11-NEXT:  .LBB12_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_mov_b32_e32 v0, v8
-; GFX11-NEXT:    v_mov_b32_e32 v4, v9
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_i64_to_v8i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v2
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v8, vcc_lo, v8, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT:  ; %bb.4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v8.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v9.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v9.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_i64_to_v8i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-FAKE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB12_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v8, vcc_lo, v8, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-FAKE16-NEXT:  .LBB12_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v8
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v9
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -1524,90 +1615,176 @@ define i64 @bitcast_v8i8_to_i64(<8 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v8i8_to_i64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mov_b32_e32 v9, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
-; GFX11-NEXT:    v_lshlrev_b16 v8, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v3, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v5, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v7, 8, v7
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB13_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB13_4
-; GFX11-NEXT:  .LBB13_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB13_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v6
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v8
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v5
-; GFX11-NEXT:    v_or_b32_e32 v3, v4, v7
-; GFX11-NEXT:    ; implicit-def: $vgpr8
-; GFX11-NEXT:    ; implicit-def: $vgpr4
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB13_2
-; GFX11-NEXT:  .LBB13_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v9, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v2, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v4, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v6, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v0, v8, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v3, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v2, v5, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v7, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v8i8_to_i64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v5.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v5.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v8
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB13_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB13_4
+; GFX11-TRUE16-NEXT:  .LBB13_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB13_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v0.h, v2.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v1.h, v3.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB13_2
+; GFX11-TRUE16-NEXT:  .LBB13_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v5.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v4.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v4.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v6.l, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v3.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v3.h, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v8i8_to_i64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB13_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB13_4
+; GFX11-FAKE16-NEXT:  .LBB13_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB13_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v4, v7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB13_2
+; GFX11-FAKE16-NEXT:  .LBB13_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v9, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v2, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v4, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v6, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v8, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v5, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -2548,52 +2725,106 @@ define double @bitcast_v4bf16_to_f64(<4 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v4bf16_to_f64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v2
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB23_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v0
-; GFX11-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v8, v3, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v3
-; GFX11-NEXT:    v_bfe_u32 v4, v2, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v5, 0x400000, v2
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_add3_u32 v8, v8, v3, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_bfe_u32 v9, v1, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v6, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v7, 0x400000, v0
-; GFX11-NEXT:    v_add3_u32 v9, v9, v1, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_add3_u32 v6, v6, v0, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v4, 0x400000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v6, v7, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v8, v10, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc_lo
-; GFX11-NEXT:    v_perm_b32 v0, v0, v2, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_perm_b32 v1, v3, v1, 0x7060302
-; GFX11-NEXT:  .LBB23_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_f64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v2
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB23_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v7, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v7, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v1, v7, v10 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v4, v2, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v0, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v3
+; GFX11-TRUE16-NEXT:  .LBB23_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_f64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v2
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB23_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v4, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v8, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v1, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v6, v7, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v2, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v1, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB23_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -2727,45 +2958,80 @@ define <8 x i8> @bitcast_f64_to_v8i8(double %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v4, v9
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_f64_to_v8i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
-; GFX11-NEXT:  ; %bb.2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB24_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
-; GFX11-NEXT:  .LBB24_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_mov_b32_e32 v0, v8
-; GFX11-NEXT:    v_mov_b32_e32 v4, v9
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_f64_to_v8i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v2
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB24_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-TRUE16-NEXT:  .LBB24_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v8.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v9.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v9.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_f64_to_v8i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-FAKE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB24_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_f64 v[8:9], v[8:9], 1.0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-FAKE16-NEXT:  .LBB24_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v8
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v9
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -2964,90 +3230,176 @@ define double @bitcast_v8i8_to_f64(<8 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v8i8_to_f64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mov_b32_e32 v9, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
-; GFX11-NEXT:    v_lshlrev_b16 v8, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v3, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v5, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v7, 8, v7
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB25_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB25_4
-; GFX11-NEXT:  .LBB25_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB25_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v6
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v8
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v5
-; GFX11-NEXT:    v_or_b32_e32 v3, v4, v7
-; GFX11-NEXT:    ; implicit-def: $vgpr8
-; GFX11-NEXT:    ; implicit-def: $vgpr4
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB25_2
-; GFX11-NEXT:  .LBB25_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v9, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v2, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v4, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v6, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v0, v8, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v3, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v2, v5, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v7, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v8i8_to_f64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v5.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v5.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v8
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB25_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB25_4
+; GFX11-TRUE16-NEXT:  .LBB25_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB25_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v0.h, v2.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v1.h, v3.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB25_2
+; GFX11-TRUE16-NEXT:  .LBB25_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v5.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v4.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v4.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v6.l, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v3.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v3.h, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v8i8_to_f64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB25_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB25_4
+; GFX11-FAKE16-NEXT:  .LBB25_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB25_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v4, v7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB25_2
+; GFX11-FAKE16-NEXT:  .LBB25_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v9, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v2, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v4, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v6, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v8, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v5, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -3861,52 +4213,106 @@ define <2 x i32> @bitcast_v4bf16_to_v2i32(<4 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v4bf16_to_v2i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v2
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB33_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v0
-; GFX11-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v8, v3, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v3
-; GFX11-NEXT:    v_bfe_u32 v4, v2, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v5, 0x400000, v2
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_add3_u32 v8, v8, v3, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_bfe_u32 v9, v1, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v6, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v7, 0x400000, v0
-; GFX11-NEXT:    v_add3_u32 v9, v9, v1, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_add3_u32 v6, v6, v0, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v4, 0x400000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v6, v7, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v8, v10, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc_lo
-; GFX11-NEXT:    v_perm_b32 v0, v0, v2, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_perm_b32 v1, v3, v1, 0x7060302
-; GFX11-NEXT:  .LBB33_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_v2i32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v2
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB33_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v7, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v7, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v1, v7, v10 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v4, v2, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v0, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v3
+; GFX11-TRUE16-NEXT:  .LBB33_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_v2i32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v2
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB33_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v4, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v8, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v1, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v6, v7, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v2, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v1, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB33_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -4042,46 +4448,81 @@ define <8 x i8> @bitcast_v2i32_to_v8i8(<2 x i32> %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v4, v9
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v2i32_to_v8i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
-; GFX11-NEXT:  ; %bb.2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB34_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u32_e32 v9, 3, v9
-; GFX11-NEXT:    v_add_nc_u32_e32 v8, 3, v8
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
-; GFX11-NEXT:  .LBB34_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_mov_b32_e32 v0, v8
-; GFX11-NEXT:    v_mov_b32_e32 v4, v9
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v2i32_to_v8i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v2
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v9, 3, v9
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, 3, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-TRUE16-NEXT:  ; %bb.4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v8.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v9.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v9.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v2i32_to_v8i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-FAKE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB34_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v9, 3, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, 3, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-FAKE16-NEXT:  .LBB34_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v8
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v9
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -4280,90 +4721,176 @@ define <2 x i32> @bitcast_v8i8_to_v2i32(<8 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v8i8_to_v2i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mov_b32_e32 v9, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
-; GFX11-NEXT:    v_lshlrev_b16 v8, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v3, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v5, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v7, 8, v7
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB35_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB35_4
-; GFX11-NEXT:  .LBB35_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB35_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v6
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v8
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v5
-; GFX11-NEXT:    v_or_b32_e32 v3, v4, v7
-; GFX11-NEXT:    ; implicit-def: $vgpr8
-; GFX11-NEXT:    ; implicit-def: $vgpr4
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB35_2
-; GFX11-NEXT:  .LBB35_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v9, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v2, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v4, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v6, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v0, v8, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v3, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v2, v5, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v7, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v8i8_to_v2i32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v5.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v5.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v8
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB35_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB35_4
+; GFX11-TRUE16-NEXT:  .LBB35_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB35_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v0.h, v2.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v1.h, v3.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB35_2
+; GFX11-TRUE16-NEXT:  .LBB35_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v5.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v4.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v4.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v6.l, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v3.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v3.h, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v8i8_to_v2i32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB35_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB35_4
+; GFX11-FAKE16-NEXT:  .LBB35_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB35_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v4, v7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB35_2
+; GFX11-FAKE16-NEXT:  .LBB35_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v9, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v2, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v4, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v6, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v8, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v5, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -5025,52 +5552,106 @@ define <2 x float> @bitcast_v4bf16_to_v2f32(<4 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v4bf16_to_v2f32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v2
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB41_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v0
-; GFX11-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v8, v3, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v3
-; GFX11-NEXT:    v_bfe_u32 v4, v2, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v5, 0x400000, v2
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_add3_u32 v8, v8, v3, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_bfe_u32 v9, v1, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v6, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v7, 0x400000, v0
-; GFX11-NEXT:    v_add3_u32 v9, v9, v1, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_add3_u32 v6, v6, v0, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v4, 0x400000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v6, v7, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v8, v10, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc_lo
-; GFX11-NEXT:    v_perm_b32 v0, v0, v2, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_perm_b32 v1, v3, v1, 0x7060302
-; GFX11-NEXT:  .LBB41_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_v2f32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v2
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB41_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v7, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v7, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v1, v7, v10 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v4, v2, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v0, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v3
+; GFX11-TRUE16-NEXT:  .LBB41_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_v2f32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v2
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB41_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v4, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v8, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v1, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v6, v7, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v2, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v1, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB41_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -5206,45 +5787,79 @@ define <8 x i8> @bitcast_v2f32_to_v8i8(<2 x float> %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v4, v9
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v2f32_to_v8i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
-; GFX11-NEXT:  ; %bb.2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB42_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
-; GFX11-NEXT:  .LBB42_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_mov_b32_e32 v0, v8
-; GFX11-NEXT:    v_mov_b32_e32 v4, v9
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v2f32_to_v8i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v2
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-TRUE16-NEXT:  ; %bb.4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v8.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v9.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v9.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v2f32_to_v8i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-FAKE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB42_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-FAKE16-NEXT:  .LBB42_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v8
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v9
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -5443,90 +6058,176 @@ define <2 x float> @bitcast_v8i8_to_v2f32(<8 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v8i8_to_v2f32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mov_b32_e32 v9, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
-; GFX11-NEXT:    v_lshlrev_b16 v8, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v3, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v5, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v7, 8, v7
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB43_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB43_4
-; GFX11-NEXT:  .LBB43_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB43_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v6
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v8
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v5
-; GFX11-NEXT:    v_or_b32_e32 v3, v4, v7
-; GFX11-NEXT:    ; implicit-def: $vgpr8
-; GFX11-NEXT:    ; implicit-def: $vgpr4
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB43_2
-; GFX11-NEXT:  .LBB43_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v9, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v2, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v4, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v6, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v0, v8, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v3, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v2, v5, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v7, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v8i8_to_v2f32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v5.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v5.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v8
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB43_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB43_4
+; GFX11-TRUE16-NEXT:  .LBB43_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB43_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v0.h, v2.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v1.h, v3.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB43_2
+; GFX11-TRUE16-NEXT:  .LBB43_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v5.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v4.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v4.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v6.l, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v3.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v3.h, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v8i8_to_v2f32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB43_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB43_4
+; GFX11-FAKE16-NEXT:  .LBB43_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB43_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v4, v7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB43_2
+; GFX11-FAKE16-NEXT:  .LBB43_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v9, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v2, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v4, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v6, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v8, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v5, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -6006,53 +6707,109 @@ define <4 x i16> @bitcast_v4bf16_to_v4i16(<4 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v4bf16_to_v4i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v2
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB47_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_add_f32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_bfe_u32 v7, v3, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v9, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v0
-; GFX11-NEXT:    v_add3_u32 v7, v7, v3, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_add3_u32 v9, v9, v0, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v1, 0x40c00000, v1
-; GFX11-NEXT:    v_bfe_u32 v4, v2, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v5, 0x400000, v2
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v6, v1, 16, 1
-; GFX11-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v6, v6, v1, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, 0x400000, v1
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v7, v8, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v9, v10, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v0, v0, v3, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v6, v4, vcc_lo
-; GFX11-NEXT:    v_perm_b32 v1, v2, v1, 0x7060302
-; GFX11-NEXT:  .LBB47_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_v4i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v2
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB47_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v10, v2, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v10, v10, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_add_f32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v4, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, 0x400000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v8, v8, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v6, v7, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v8, v9, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v10, v11, vcc_lo
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v1, v1, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v0, v0, 16, v2
+; GFX11-TRUE16-NEXT:  .LBB47_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_v4i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v2
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB47_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v7, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v4, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v7, v8, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v9, v10, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v3, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v6, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB47_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -6216,46 +6973,81 @@ define <8 x i8> @bitcast_v4i16_to_v8i8(<4 x i16> %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v4, v9
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v4i16_to_v8i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
-; GFX11-NEXT:  ; %bb.2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB48_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
-; GFX11-NEXT:  .LBB48_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_mov_b32_e32 v0, v8
-; GFX11-NEXT:    v_mov_b32_e32 v4, v9
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v4i16_to_v8i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v2
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-TRUE16-NEXT:  ; %bb.4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v8.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v9.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v9.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v4i16_to_v8i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-FAKE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB48_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-FAKE16-NEXT:  .LBB48_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v8
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v9
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -6462,90 +7254,176 @@ define <4 x i16> @bitcast_v8i8_to_v4i16(<8 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v8i8_to_v4i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mov_b32_e32 v9, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
-; GFX11-NEXT:    v_lshlrev_b16 v8, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v3, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v5, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v7, 8, v7
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB49_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB49_4
-; GFX11-NEXT:  .LBB49_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB49_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v6
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v8
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v5
-; GFX11-NEXT:    v_or_b32_e32 v3, v4, v7
-; GFX11-NEXT:    ; implicit-def: $vgpr8
-; GFX11-NEXT:    ; implicit-def: $vgpr4
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB49_2
-; GFX11-NEXT:  .LBB49_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v9, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v2, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v4, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v6, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v0, v8, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v3, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v2, v5, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v7, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v8i8_to_v4i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v5.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v5.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v8
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB49_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB49_4
+; GFX11-TRUE16-NEXT:  .LBB49_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB49_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v0.h, v2.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v1.h, v3.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB49_2
+; GFX11-TRUE16-NEXT:  .LBB49_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v5.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v4.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v4.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v6.l, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v3.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v3.h, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v8i8_to_v4i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB49_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB49_4
+; GFX11-FAKE16-NEXT:  .LBB49_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB49_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v4, v7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB49_2
+; GFX11-FAKE16-NEXT:  .LBB49_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v9, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v2, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v4, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v6, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v8, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v5, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -6833,53 +7711,107 @@ define <4 x half> @bitcast_v4bf16_to_v4f16(<4 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v4bf16_to_v4f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v2
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB51_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_add_f32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_bfe_u32 v7, v3, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v9, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v0
-; GFX11-NEXT:    v_add3_u32 v7, v7, v3, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_add3_u32 v9, v9, v0, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v1, 0x40c00000, v1
-; GFX11-NEXT:    v_bfe_u32 v4, v2, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v5, 0x400000, v2
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v6, v1, 16, 1
-; GFX11-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v6, v6, v1, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, 0x400000, v1
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v7, v8, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v9, v10, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v0, v0, v3, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v6, v4, vcc_lo
-; GFX11-NEXT:    v_perm_b32 v1, v2, v1, 0x7060302
-; GFX11-NEXT:  .LBB51_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_v4f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v2
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB51_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v1, v6, v7 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v4, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v3, v9, v11 :: v_dual_and_b32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v8, v8, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v8, v10, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v3, v0
+; GFX11-TRUE16-NEXT:  .LBB51_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_v4f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v2
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB51_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v7, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v4, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v7, v8, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v9, v10, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v3, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v6, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB51_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -7044,46 +7976,81 @@ define <8 x i8> @bitcast_v4f16_to_v8i8(<4 x half> %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v4, v9
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v4f16_to_v8i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
-; GFX11-NEXT:  ; %bb.2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB52_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
-; GFX11-NEXT:  .LBB52_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_mov_b32_e32 v0, v8
-; GFX11-NEXT:    v_mov_b32_e32 v4, v9
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v4f16_to_v8i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v2
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-TRUE16-NEXT:  ; %bb.4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v8.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v9.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v9.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v4f16_to_v8i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-FAKE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB52_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-FAKE16-NEXT:  .LBB52_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v8
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v9
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -7282,90 +8249,176 @@ define <4 x half> @bitcast_v8i8_to_v4f16(<8 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v8i8_to_v4f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mov_b32_e32 v9, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
-; GFX11-NEXT:    v_lshlrev_b16 v8, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v3, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v5, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v7, 8, v7
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB53_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB53_4
-; GFX11-NEXT:  .LBB53_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB53_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v6
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v8
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v5
-; GFX11-NEXT:    v_or_b32_e32 v3, v4, v7
-; GFX11-NEXT:    ; implicit-def: $vgpr8
-; GFX11-NEXT:    ; implicit-def: $vgpr4
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB53_2
-; GFX11-NEXT:  .LBB53_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v9, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v2, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v4, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v6, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v0, v8, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v3, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v2, v5, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v7, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v8i8_to_v4f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v5.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v5.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v8
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB53_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB53_4
+; GFX11-TRUE16-NEXT:  .LBB53_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB53_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v0.h, v2.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v1.h, v3.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB53_2
+; GFX11-TRUE16-NEXT:  .LBB53_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v5.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v4.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v4.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v6.l, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v3.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v3.h, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v8i8_to_v4f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB53_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB53_4
+; GFX11-FAKE16-NEXT:  .LBB53_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB53_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v4, v7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB53_2
+; GFX11-FAKE16-NEXT:  .LBB53_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v9, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v2, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v4, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v6, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v8, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v5, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -7592,79 +8645,157 @@ define <8 x i8> @bitcast_v4bf16_to_v8i8(<4 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v4, v9
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v4bf16_to_v8i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
-; GFX11-NEXT:  ; %bb.2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB54_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff0000, v8
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v8
-; GFX11-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v3, 16, v9
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v6, v1, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v7, 0x400000, v1
-; GFX11-NEXT:    v_bfe_u32 v4, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v5, 0x400000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_add3_u32 v6, v6, v1, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-NEXT:    v_add3_u32 v4, v4, v0, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v9
-; GFX11-NEXT:    v_bfe_u32 v9, v3, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v4, 0x400000, v3
-; GFX11-NEXT:    v_dual_cndmask_b32 v1, v6, v7 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add3_u32 v9, v9, v3, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v8, v2, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v2
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v8, v8, v2, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_perm_b32 v10, v1, v0, 0x7060302
-; GFX11-NEXT:    v_lshrrev_b32_e32 v8, 16, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v9, v4, vcc_lo
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v10
-; GFX11-NEXT:    v_perm_b32 v11, v2, v3, 0x7060302
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v10
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v11
-; GFX11-NEXT:  .LBB54_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_mov_b32_e32 v0, v8
-; GFX11-NEXT:    v_mov_b32_e32 v4, v9
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_v8i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v2
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB54_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[10:11], 24, v[8:9]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v9.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v9.h
+; GFX11-TRUE16-NEXT:  .LBB54_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB54_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v8
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v8.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v9
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v5, 0x40c00000, v0 :: v_dual_lshlrev_b32 v0, 16, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, 0x400000, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_add_f32 v1, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v5, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v7, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v12, v4, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v3, v3, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v7, v10, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v3, v6, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v4.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v12, v8, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v8, 0xffff, v3, v2
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v9, 0xffff, v1, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[10:11], 24, v[8:9]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT:  .LBB54_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v8.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v6.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_v8i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-FAKE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB54_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v8
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v3, 16, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v4, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    v_add3_u32 v4, v4, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v9
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v6, v7 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v8, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v8, v10, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v1, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v9, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v10
+; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v2, v3, 0x7060302
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v10
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-FAKE16-NEXT:  .LBB54_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v8
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v9
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -7867,90 +8998,176 @@ define <4 x bfloat> @bitcast_v8i8_to_v4bf16(<8 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v8i8_to_v4bf16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mov_b32_e32 v9, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
-; GFX11-NEXT:    v_lshlrev_b16 v8, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v3, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v5, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v7, 8, v7
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB55_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB55_4
-; GFX11-NEXT:  .LBB55_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB55_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v9
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v6
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v8
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v5
-; GFX11-NEXT:    v_or_b32_e32 v3, v4, v7
-; GFX11-NEXT:    ; implicit-def: $vgpr8
-; GFX11-NEXT:    ; implicit-def: $vgpr4
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB55_2
-; GFX11-NEXT:  .LBB55_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v9, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v2, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v4, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v6, 3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v0, v8, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v3, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v2, v5, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v7, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v8i8_to_v4bf16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v5.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v5.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v8
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB55_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB55_4
+; GFX11-TRUE16-NEXT:  .LBB55_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB55_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v0.h, v2.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v1.h, v3.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB55_2
+; GFX11-TRUE16-NEXT:  .LBB55_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v5.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v4.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v4.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v6.l, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v2.h, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v3.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v3.h, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v8i8_to_v4bf16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB55_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB55_4
+; GFX11-FAKE16-NEXT:  .LBB55_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB55_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v4, v7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB55_2
+; GFX11-FAKE16-NEXT:  .LBB55_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v9, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v2, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v4, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v6, 3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v8, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v5, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v7, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
index b87e7b0916032..852114f2ba12f 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
@@ -3,7 +3,8 @@
 ; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define <3 x float> @bitcast_v3i32_to_v3f32(<3 x i32> %a, i32 %b) {
 ; GCN-LABEL: bitcast_v3i32_to_v3f32:
@@ -317,57 +318,105 @@ define <12 x i8> @bitcast_v3i32_to_v12i8(<3 x i32> %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v4, v14
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v3i32_to_v12i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v13, v0
-; GFX11-NEXT:    v_mov_b32_e32 v14, v1
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v3
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB2_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v13
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[8:9]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v13
-; GFX11-NEXT:  .LBB2_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB2_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u32_e32 v8, 3, v8
-; GFX11-NEXT:    v_add_nc_u32_e32 v14, 3, v14
-; GFX11-NEXT:    v_add_nc_u32_e32 v13, 3, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v8
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v14
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[8:9]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v13
-; GFX11-NEXT:  .LBB2_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_mov_b32_e32 v0, v13
-; GFX11-NEXT:    v_mov_b32_e32 v4, v14
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v3i32_to_v12i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v11, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v12, v1
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v3
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v11
+; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB2_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v12, 3, v12
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v11, 3, v11
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v10, 3, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v11
+; GFX11-TRUE16-NEXT:  .LBB2_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v11.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v11.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v12.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v13.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v3i32_to_v12i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v13, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v14, v1
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB2_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[8:9]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v13
+; GFX11-FAKE16-NEXT:  .LBB2_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB2_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, 3, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v14, 3, v14
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v13, 3, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[8:9]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v13
+; GFX11-FAKE16-NEXT:  .LBB2_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v13
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v14
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -627,102 +676,203 @@ define <3 x i32> @bitcast_v12i8_to_v3i32(<12 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v12i8_to_v3i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v14, v2 :: v_dual_mov_b32 v13, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v12
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v12, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v7, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v3, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v5, 8, v11
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB3_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB3_4
-; GFX11-NEXT:  .LBB3_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB3_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v13
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v16
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v12
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v15
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v7
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v3
-; GFX11-NEXT:    v_or_b32_e32 v5, v8, v5
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr8
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v4
-; GFX11-NEXT:    ; implicit-def: $vgpr4
-; GFX11-NEXT:    v_or_b32_e32 v2, v3, v5
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB3_2
-; GFX11-NEXT:  .LBB3_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v13, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v14, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v4, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v6, 3
-; GFX11-NEXT:    v_add_nc_u16 v6, v8, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v10, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_or_b32_e32 v0, v16, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v12, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v15, v2
-; GFX11-NEXT:    v_or_b32_e32 v4, v7, v4
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v6
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v8
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v4
-; GFX11-NEXT:    v_or_b32_e32 v2, v3, v5
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v12i8_to_v3i32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.h, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 8, v8.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v11.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v12
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB3_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB3_4
+; GFX11-TRUE16-NEXT:  .LBB3_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB3_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v5.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v0.h, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v1.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.l, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.h, v3.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v3, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v6, v2
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB3_2
+; GFX11-TRUE16-NEXT:  .LBB3_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v7.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v7.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v6.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v6.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v8.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v10.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v5.h, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v4.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v5.l, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v4.l, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v3.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v3.h, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v5, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v6, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v2, v4
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v12i8_to_v3i32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v14, v2 :: v_dual_mov_b32 v13, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v12, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB3_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB3_4
+; GFX11-FAKE16-NEXT:  .LBB3_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB3_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v8, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v4
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v3, v5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB3_2
+; GFX11-FAKE16-NEXT:  .LBB3_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v13, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v14, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v4, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v6, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v8, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v10, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v16, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v12, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v15, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v3, v5
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -1036,70 +1186,140 @@ define <3 x i32> @bitcast_v6bf16_to_v3i32(<6 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v6bf16_to_v3i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v3
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB5_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v2
-; GFX11-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v6, v3, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v3
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_bfe_u32 v7, v2, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v9, 0x400000, v2
-; GFX11-NEXT:    v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v6, v8, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v10, v4, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v7, v9, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v7, 0x400000, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    v_bfe_u32 v8, v1, 16, 1
-; GFX11-NEXT:    v_add3_u32 v6, v10, v4, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT:    v_perm_b32 v2, v3, v2, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v4, v6, v7 :: v_dual_add_f32 v5, 0x40c00000, v5
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_add3_u32 v7, v8, v1, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v1
-; GFX11-NEXT:    v_bfe_u32 v9, v5, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v7, v8, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    v_add3_u32 v9, v9, v5, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_cndmask_b32 v5, v9, v10
-; GFX11-NEXT:    v_bfe_u32 v6, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v11, 0x400000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v6, v6, v0, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v6, v11, vcc_lo
-; GFX11-NEXT:    v_perm_b32 v1, v4, v1, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_perm_b32 v0, v5, v0, 0x7060302
-; GFX11-NEXT:  .LBB5_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v6bf16_to_v3i32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v3
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB5_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v3, 16, v2
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v10, v4, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v3, v6, v8 :: v_dual_and_b32 v2, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v8, v10, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v7, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v3, v2
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v7, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v7, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v6, v10, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v7, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v11, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v11, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v8, v9, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v6, v10, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v0, v5
+; GFX11-TRUE16-NEXT:  .LBB5_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v6bf16_to_v3i32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v3
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB5_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v7, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v7, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v6, v8, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v10, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v10, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v6, v7 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v8, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v7, v8, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_cndmask_b32 v5, v9, v10
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v6, v11, vcc_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v4, v1, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v5, v0, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB5_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -1741,56 +1961,103 @@ define <12 x i8> @bitcast_v3f32_to_v12i8(<3 x float> %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v4, v14
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v3f32_to_v12i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v13, v0
-; GFX11-NEXT:    v_mov_b32_e32 v14, v1
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v3
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB10_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v13
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[8:9]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v13
-; GFX11-NEXT:  .LBB10_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB10_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_add_f32_e32 v8, 1.0, v8
-; GFX11-NEXT:    v_dual_add_f32 v14, 1.0, v14 :: v_dual_add_f32 v13, 1.0, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v8
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v14
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[8:9]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v13
-; GFX11-NEXT:  .LBB10_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_mov_b32_e32 v0, v13
-; GFX11-NEXT:    v_mov_b32_e32 v4, v14
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v3f32_to_v12i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v11, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v12, v1
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v3
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v11
+; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB10_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v12, 1.0, v12 :: v_dual_add_f32 v11, 1.0, v11
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v10, 1.0, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v11
+; GFX11-TRUE16-NEXT:  .LBB10_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v11.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v11.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v12.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v13.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v3f32_to_v12i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v13, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v14, v1
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB10_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[8:9]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v13
+; GFX11-FAKE16-NEXT:  .LBB10_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB10_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v8, 1.0, v8
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v14, 1.0, v14 :: v_dual_add_f32 v13, 1.0, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[8:9]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v13
+; GFX11-FAKE16-NEXT:  .LBB10_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v13
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v14
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -2050,102 +2317,203 @@ define <3 x float> @bitcast_v12i8_to_v3f32(<12 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v12i8_to_v3f32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v14, v2 :: v_dual_mov_b32 v13, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v12
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v12, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v7, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v3, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v5, 8, v11
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB11_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB11_4
-; GFX11-NEXT:  .LBB11_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB11_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v13
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v16
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v12
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v15
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v7
-; GFX11-NEXT:    v_or_b32_e32 v3, v6, v3
-; GFX11-NEXT:    v_or_b32_e32 v5, v8, v5
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr8
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v4
-; GFX11-NEXT:    ; implicit-def: $vgpr4
-; GFX11-NEXT:    v_or_b32_e32 v2, v3, v5
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB11_2
-; GFX11-NEXT:  .LBB11_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v13, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v14, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v4, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v6, 3
-; GFX11-NEXT:    v_add_nc_u16 v6, v8, 3
-; GFX11-NEXT:    v_add_nc_u16 v8, v10, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_or_b32_e32 v0, v16, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v12, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v15, v2
-; GFX11-NEXT:    v_or_b32_e32 v4, v7, v4
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v6
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v8
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v4
-; GFX11-NEXT:    v_or_b32_e32 v2, v3, v5
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v12i8_to_v3f32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.h, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.h, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 8, v8.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v11.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v12
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB11_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB11_4
+; GFX11-TRUE16-NEXT:  .LBB11_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB11_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v5.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v0.h, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v1.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.l, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.h, v3.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v3, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v6, v2
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB11_2
+; GFX11-TRUE16-NEXT:  .LBB11_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v7.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v7.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v6.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v6.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v8.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v10.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v5.h, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v4.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v5.l, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v4.l, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v3.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v3.h, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v5, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v6, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v2, v4
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v12i8_to_v3f32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v14, v2 :: v_dual_mov_b32 v13, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v12, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB11_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB11_4
+; GFX11-FAKE16-NEXT:  .LBB11_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB11_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v6, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v8, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v4
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v3, v5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB11_2
+; GFX11-FAKE16-NEXT:  .LBB11_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v13, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v14, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v4, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v6, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v8, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v8, v10, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v16, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v12, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v15, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v7, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v3, v5
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -2458,70 +2826,140 @@ define <3 x float> @bitcast_v6bf16_to_v3f32(<6 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v6bf16_to_v3f32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v3
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB13_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v2
-; GFX11-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_bfe_u32 v6, v3, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v3
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_bfe_u32 v7, v2, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v9, 0x400000, v2
-; GFX11-NEXT:    v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v6, v8, vcc_lo
-; GFX11-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v10, v4, 16, 1
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v7, v9, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v7, 0x400000, v4
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    v_bfe_u32 v8, v1, 16, 1
-; GFX11-NEXT:    v_add3_u32 v6, v10, v4, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT:    v_perm_b32 v2, v3, v2, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_dual_cndmask_b32 v4, v6, v7 :: v_dual_add_f32 v5, 0x40c00000, v5
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_add3_u32 v7, v8, v1, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v1
-; GFX11-NEXT:    v_bfe_u32 v9, v5, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v7, v8, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    v_add3_u32 v9, v9, v5, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_cndmask_b32 v5, v9, v10
-; GFX11-NEXT:    v_bfe_u32 v6, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v11, 0x400000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v6, v6, v0, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v6, v11, vcc_lo
-; GFX11-NEXT:    v_perm_b32 v1, v4, v1, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_perm_b32 v0, v5, v0, 0x7060302
-; GFX11-NEXT:  .LBB13_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v6bf16_to_v3f32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v3
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB13_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v3, 16, v2
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v10, v4, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v3, v6, v8 :: v_dual_and_b32 v2, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v8, v10, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v7, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v3, v2
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v7, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v7, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v6, v10, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v7, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v11, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v11, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v8, v9, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v6, v10, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v0, v5
+; GFX11-TRUE16-NEXT:  .LBB13_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v6bf16_to_v3f32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v3
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB13_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v7, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v7, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v6, v8, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v10, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v10, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v6, v7 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v8, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v7, v8, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_cndmask_b32 v5, v9, v10
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v6, v11, vcc_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v4, v1, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v5, v0, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB13_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -3256,102 +3694,206 @@ define <6 x bfloat> @bitcast_v12i8_to_v6bf16(<12 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v12i8_to_v6bf16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v14, v2 :: v_dual_mov_b32 v13, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v12
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v12, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v5, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v7, 8, v11
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB18_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB18_4
-; GFX11-NEXT:  .LBB18_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB18_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v13
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v17
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v15
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v16
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v12
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v5, v6, v7
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr8
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    ; implicit-def: $vgpr4
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB18_2
-; GFX11-NEXT:  .LBB18_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v13, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v14, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v4, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v6, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v8, 3
-; GFX11-NEXT:    v_add_nc_u16 v6, v10, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_or_b32_e32 v0, v17, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v15, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v16, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v12, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v5, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v7, v6
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v12i8_to_v6bf16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v9.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.h, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.l, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v10.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 8, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v11.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v12
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB18_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB18_4
+; GFX11-TRUE16-NEXT:  .LBB18_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB18_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v0.h, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v1.h, v5.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.l, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.h, v4.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v4, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v6, v2
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB18_2
+; GFX11-TRUE16-NEXT:  .LBB18_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v9.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v8.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v7.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v7.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v8.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v10.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v6.h, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v5.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v6.l, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v5.l, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v4.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v4.h, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v5, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v6, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v2, v4
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v12i8_to_v6bf16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v14, v2 :: v_dual_mov_b32 v13, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v12, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB18_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB18_4
+; GFX11-FAKE16-NEXT:  .LBB18_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB18_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB18_2
+; GFX11-FAKE16-NEXT:  .LBB18_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v13, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v14, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v4, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v6, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v8, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v10, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v17, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v15, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v16, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v12, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v5, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v7, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -3656,108 +4198,217 @@ define <12 x i8> @bitcast_v6bf16_to_v12i8(<6 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v4, v14
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v6bf16_to_v12i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v13, v0
-; GFX11-NEXT:    v_mov_b32_e32 v14, v1
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v3
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB19_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v13
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[8:9]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v13
-; GFX11-NEXT:  .LBB19_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB19_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v14
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v13
-; GFX11-NEXT:    v_dual_mov_b32 v12, 0x7fc07fc0 :: v_dual_lshlrev_b32 v3, 16, v13
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-NEXT:    v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v7, v1, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v9, 0x400000, v1
-; GFX11-NEXT:    v_or_b32_e32 v11, 0x400000, v5
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v8
-; GFX11-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-NEXT:    v_add3_u32 v7, v7, v1, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v14
-; GFX11-NEXT:    v_bfe_u32 v10, v2, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-NEXT:    v_bfe_u32 v6, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add3_u32 v6, v6, v0, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v0, 0x40c00000, v4
-; GFX11-NEXT:    v_or_b32_e32 v4, 0x400000, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_add3_u32 v1, v10, v2, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v8, v3, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_bfe_u32 v9, v0, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v7
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v1, v4, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v4, v8, v3, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v3
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_bfe_u32 v1, v5, 16, 1
-; GFX11-NEXT:    v_add3_u32 v9, v9, v0, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v4, v8, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_add3_u32 v1, v1, v5, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_perm_b32 v0, v2, v3, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v4, v9, v10, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v5, v1, v11, vcc_lo
-; GFX11-NEXT:    v_perm_b32 v1, v6, v7, 0x7060302
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v11, v4, v5, 0x7060302
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[0:1]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v8, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[11:12]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
-; GFX11-NEXT:  .LBB19_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_mov_b32_e32 v0, v13
-; GFX11-NEXT:    v_mov_b32_e32 v4, v14
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v6bf16_to_v12i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v13, v1
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v12, v0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr16_lo16
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v3
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB19_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[16:17], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[12:13]
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v13.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v13.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.h, v10.l
+; GFX11-TRUE16-NEXT:  .LBB19_2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB19_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v12
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v13
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v10
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v13
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v0, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v0, v0, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v7, 0x40c00000, v4
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v11, v4, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v4.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v11, v9, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v0, v11, vcc_lo
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v12
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v12, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v8, v13, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v3, v12, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v13, 0xffff, v1, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v10, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v10, v10, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v10, v9, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v12, 0xffff, v5, v2
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v3, v11, vcc_lo
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v11, 0x7fc07fc0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v8.h
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[12:13]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v12
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v10, 0xffff, v7, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[16:17], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v10
+; GFX11-TRUE16-NEXT:  .LBB19_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v12.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v14.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v8.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v16.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v6bf16_to_v12i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v13, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v14, v1
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB19_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[8:9]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v13
+; GFX11-FAKE16-NEXT:  .LBB19_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB19_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v13
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v12, 0x7fc07fc0 :: v_dual_lshlrev_b32 v3, 16, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v7, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, 0x400000, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v8
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v7, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v14
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v10, v2, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v1, v10, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v0, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v7
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v1, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v4, v8, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v1, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v4, v8, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_add3_u32 v1, v1, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v2, v3, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v9, v10, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v1, v11, vcc_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v6, v7, 0x7060302
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v4, v5, 0x7060302
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[0:1]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v11
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[11:12]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-FAKE16-NEXT:  .LBB19_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v13
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v14
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -4012,102 +4663,206 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v12i8_to_v6f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v14, v2 :: v_dual_mov_b32 v13, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v12
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v12, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v5, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v7, 8, v11
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB20_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB20_4
-; GFX11-NEXT:  .LBB20_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB20_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v13
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v17
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v15
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v16
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v12
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v5, v6, v7
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr8
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    ; implicit-def: $vgpr4
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB20_2
-; GFX11-NEXT:  .LBB20_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v13, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v14, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v4, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v6, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v8, 3
-; GFX11-NEXT:    v_add_nc_u16 v6, v10, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_or_b32_e32 v0, v17, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v15, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v16, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v12, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v5, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v7, v6
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v12i8_to_v6f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v9.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.h, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.l, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v10.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 8, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v11.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v12
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB20_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB20_4
+; GFX11-TRUE16-NEXT:  .LBB20_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB20_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v0.h, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v1.h, v5.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.l, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.h, v4.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v4, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v6, v2
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB20_2
+; GFX11-TRUE16-NEXT:  .LBB20_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v9.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v8.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v7.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v7.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v8.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v10.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v6.h, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v5.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v6.l, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v5.l, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v4.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v4.h, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v5, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v6, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v2, v4
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v12i8_to_v6f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v14, v2 :: v_dual_mov_b32 v13, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v12, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB20_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB20_4
+; GFX11-FAKE16-NEXT:  .LBB20_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB20_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB20_2
+; GFX11-FAKE16-NEXT:  .LBB20_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v13, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v14, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v4, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v6, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v8, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v10, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v17, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v15, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v16, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v12, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v5, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v7, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -4319,60 +5074,109 @@ define <12 x i8> @bitcast_v6f16_to_v12i8(<6 x half> %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v8, v13
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v6f16_to_v12i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v13, v2 :: v_dual_mov_b32 v16, v1
-; GFX11-NEXT:    v_mov_b32_e32 v15, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v3
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB21_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v15
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[15:16]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v15
-; GFX11-NEXT:  .LBB21_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB21_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_mov_b32_e32 v14, 0x7e007e00
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v16
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[15:16]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v13
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v15
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v15
-; GFX11-NEXT:  .LBB21_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_mov_b32_e32 v0, v15
-; GFX11-NEXT:    v_mov_b32_e32 v4, v16
-; GFX11-NEXT:    v_mov_b32_e32 v8, v13
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v6f16_to_v12i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v13, v1
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v12, v0
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v3
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[12:13]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v12
+; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB21_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v11, 0x7e007e00
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[12:13]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[14:15], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v13
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v12
+; GFX11-TRUE16-NEXT:  .LBB21_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v12.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v13.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v13.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v14.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v6f16_to_v12i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v13, v2 :: v_dual_mov_b32 v16, v1
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v15, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB21_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v15
+; GFX11-FAKE16-NEXT:  .LBB21_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB21_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v14, 0x7e007e00
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[15:16]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v15
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v15
+; GFX11-FAKE16-NEXT:  .LBB21_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v15
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v16
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v13
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -4644,102 +5448,206 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v12i8_to_v6i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v14, v2 :: v_dual_mov_b32 v13, v0
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v12
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v1
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v3
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v5
-; GFX11-NEXT:    v_lshlrev_b16 v12, 8, v7
-; GFX11-NEXT:    v_lshlrev_b16 v5, 8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v7, 8, v11
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB22_3
-; GFX11-NEXT:  ; %bb.1: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB22_4
-; GFX11-NEXT:  .LBB22_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB22_3: ; %cmp.false
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v13
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v6
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v8
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v10
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v17
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v15
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v16
-; GFX11-NEXT:    v_or_b32_e32 v3, v3, v12
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v5, v6, v7
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    ; implicit-def: $vgpr13
-; GFX11-NEXT:    ; implicit-def: $vgpr14
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr8
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr17
-; GFX11-NEXT:    ; implicit-def: $vgpr15
-; GFX11-NEXT:    ; implicit-def: $vgpr16
-; GFX11-NEXT:    ; implicit-def: $vgpr12
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    ; implicit-def: $vgpr4
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB22_2
-; GFX11-NEXT:  .LBB22_4: ; %cmp.true
-; GFX11-NEXT:    v_add_nc_u16 v0, v13, 3
-; GFX11-NEXT:    v_add_nc_u16 v1, v14, 3
-; GFX11-NEXT:    v_add_nc_u16 v2, v4, 3
-; GFX11-NEXT:    v_add_nc_u16 v3, v6, 3
-; GFX11-NEXT:    v_add_nc_u16 v4, v8, 3
-; GFX11-NEXT:    v_add_nc_u16 v6, v10, 3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_or_b32_e32 v0, v17, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v15, v1
-; GFX11-NEXT:    v_or_b32_e32 v2, v16, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, v12, v3
-; GFX11-NEXT:    v_or_b32_e32 v4, v5, v4
-; GFX11-NEXT:    v_or_b32_e32 v5, v7, v6
-; GFX11-NEXT:    v_add_nc_u16 v0, 0x300, v0
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x300, v1
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x300, v2
-; GFX11-NEXT:    v_add_nc_u16 v3, 0x300, v3
-; GFX11-NEXT:    v_add_nc_u16 v4, 0x300, v4
-; GFX11-NEXT:    v_add_nc_u16 v5, 0x300, v5
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v12i8_to_v6i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v9.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.h, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.l, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v10.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 8, v9.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v11.l
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v12
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB22_3
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB22_4
+; GFX11-TRUE16-NEXT:  .LBB22_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB22_3: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v8.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v7.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v0.h, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v1.h, v5.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.l, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.h, v4.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v6
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v4, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v6, v2
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_hi16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr6_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB22_2
+; GFX11-TRUE16-NEXT:  .LBB22_4: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v9.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v8.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, v7.h, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.h, v7.l, 3
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, v8.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.h, v10.l, 3
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v6.h, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v5.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v6.l, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v5.l, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v4.l, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v4.h, v2.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v3.l, 0x300, v0.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v1.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x300, v1.h
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v2.l, 0x300, v2.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v4.l, 0x300, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v5, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v6, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v2, v4
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v12i8_to_v6i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v14, v2 :: v_dual_mov_b32 v13, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v12, 8, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v11
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB22_3
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB22_4
+; GFX11-FAKE16-NEXT:  .LBB22_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB22_3: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v17
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr13
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr15
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB22_2
+; GFX11-FAKE16-NEXT:  .LBB22_4: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v13, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, v14, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v4, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v6, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, v8, 3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v6, v10, 3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v17, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v15, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v16, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v12, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v5, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v7, v6
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -4954,57 +5862,105 @@ define <12 x i8> @bitcast_v6i16_to_v12i8(<6 x i16> %a, i32 %b) {
 ; GFX9-NEXT:    v_mov_b32_e32 v4, v14
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v6i16_to_v12i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v13, v0
-; GFX11-NEXT:    v_mov_b32_e32 v14, v1
-; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v3
-; GFX11-NEXT:    ; implicit-def: $vgpr1
-; GFX11-NEXT:    ; implicit-def: $vgpr2
-; GFX11-NEXT:    ; implicit-def: $vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr5
-; GFX11-NEXT:    ; implicit-def: $vgpr6
-; GFX11-NEXT:    ; implicit-def: $vgpr7
-; GFX11-NEXT:    ; implicit-def: $vgpr9
-; GFX11-NEXT:    ; implicit-def: $vgpr10
-; GFX11-NEXT:    ; implicit-def: $vgpr11
-; GFX11-NEXT:    s_and_saveexec_b32 s0, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB23_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.false
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v13
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[8:9]
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v13
-; GFX11-NEXT:  .LBB23_2: ; %Flow
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB23_4
-; GFX11-NEXT:  ; %bb.3: ; %cmp.true
-; GFX11-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v8
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v8
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[13:14]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v14
-; GFX11-NEXT:    v_lshrrev_b64 v[11:12], 24, v[8:9]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v14
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v13
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v13
-; GFX11-NEXT:  .LBB23_4: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    v_mov_b32_e32 v0, v13
-; GFX11-NEXT:    v_mov_b32_e32 v4, v14
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v6i16_to_v12i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v11, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v12, v1
+; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v3
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr9_lo16
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v11
+; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB23_4
+; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[11:12]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[13:14], 24, v[10:11]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v10
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v12
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v11
+; GFX11-TRUE16-NEXT:  .LBB23_4: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v11.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v11.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v12.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v12.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v10.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v10.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v13.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v6i16_to_v12i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v13, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v14, v1
+; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr9
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr10
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB23_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[8:9]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v13
+; GFX11-FAKE16-NEXT:  .LBB23_2: ; %Flow
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB23_4
+; GFX11-FAKE16-NEXT:  ; %bb.3: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v8
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[13:14]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], 24, v[8:9]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v14
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v13
+; GFX11-FAKE16-NEXT:  .LBB23_4: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v13
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v14
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -5225,72 +6181,140 @@ define <6 x half> @bitcast_v6bf16_to_v6f16(<6 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v6bf16_to_v6f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v3
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB24_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-NEXT:    v_bfe_u32 v11, v5, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v11, v11, v5, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v1
-; GFX11-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_bfe_u32 v8, v4, 16, 1
-; GFX11-NEXT:    v_add3_u32 v8, v8, v4, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v6, v3, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-NEXT:    v_or_b32_e32 v9, 0x400000, v3
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_bfe_u32 v7, v0, 16, 1
-; GFX11-NEXT:    v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v7, v7, v0, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v6, v9, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v6, 0x400000, v4
-; GFX11-NEXT:    v_bfe_u32 v9, v1, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    v_or_b32_e32 v13, 0x400000, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v4, v8, v6, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v8, v9, v1, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v9, 0x400000, v1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_bfe_u32 v6, v2, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v8, v9, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    v_add3_u32 v6, v6, v2, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v5, v11, v12, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v6, v13, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_perm_b32 v2, v5, v2, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v7, v10, vcc_lo
-; GFX11-NEXT:    v_perm_b32 v1, v4, v1, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_perm_b32 v0, v3, v0, 0x7060302
-; GFX11-NEXT:  .LBB24_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v6bf16_to_v6f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v3
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB24_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v7, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v7, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_add_f32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v10, v4, 16, 1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v1, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v10, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v8, v8, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v6, v10, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v0, v3
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v2, v8, v12 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v11, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v11, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v4
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v6, v10, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v2, v5
+; GFX11-TRUE16-NEXT:  .LBB24_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v6bf16_to_v6f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v3
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB24_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v11, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v11, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v8, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v7, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v7, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v6, v9, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, 0x400000, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v8, v6, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v9, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v2, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v8, v9, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v6, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v11, v12, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v6, v13, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v5, v2, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v7, v10, vcc_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v4, v1, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v3, v0, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB24_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
@@ -5641,72 +6665,146 @@ define <6 x i16> @bitcast_v6bf16_to_v6i16(<6 x bfloat> %a, i32 %b) {
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: bitcast_v6bf16_to_v6i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, exec_lo
-; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v3
-; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB26_2
-; GFX11-NEXT:  ; %bb.1: ; %cmp.true
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-NEXT:    v_bfe_u32 v11, v5, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v11, v11, v5, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v1
-; GFX11-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_bfe_u32 v8, v4, 16, 1
-; GFX11-NEXT:    v_add3_u32 v8, v8, v4, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v6, v3, 16, 1
-; GFX11-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-NEXT:    v_or_b32_e32 v9, 0x400000, v3
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_bfe_u32 v7, v0, 16, 1
-; GFX11-NEXT:    v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v7, v7, v0, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v6, v9, vcc_lo
-; GFX11-NEXT:    v_or_b32_e32 v6, 0x400000, v4
-; GFX11-NEXT:    v_bfe_u32 v9, v1, 16, 1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    v_or_b32_e32 v13, 0x400000, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v4, v8, v6, vcc_lo
-; GFX11-NEXT:    v_add3_u32 v8, v9, v1, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v9, 0x400000, v1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_bfe_u32 v6, v2, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v8, v9, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-NEXT:    v_add3_u32 v6, v6, v2, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v5, v11, v12, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v6, v13, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_perm_b32 v2, v5, v2, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v7, v10, vcc_lo
-; GFX11-NEXT:    v_perm_b32 v1, v4, v1, 0x7060302
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_perm_b32 v0, v3, v0, 0x7060302
-; GFX11-NEXT:  .LBB26_2: ; %end
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: bitcast_v6bf16_to_v6i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v3
+; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB26_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v3, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, 0x400000, v3
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, 0x400000, v1
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v10, v4, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v6, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v5, 16, v2
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v7, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, 0x400000, v0
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v5
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v7, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v7, v10, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, 0x400000, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v6, v11, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v5, v8, v12 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v10, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v13, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v10, v10, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v10, v13, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v2, v2, 16, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v0, v0, 16, v3
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v1, v1, 16, v4
+; GFX11-TRUE16-NEXT:  .LBB26_2: ; %end
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: bitcast_v6bf16_to_v6i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v3
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB26_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v11, v5, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v11, v5, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v8, v4, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v8, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-FAKE16-NEXT:    v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v3, 16, 1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, 0x400000, v3
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v7, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v7, v7, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v6, v9, vcc_lo
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, 0x400000, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v8, v6, vcc_lo
+; GFX11-FAKE16-NEXT:    v_add3_u32 v8, v9, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v6, v2, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v8, v9, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-FAKE16-NEXT:    v_add3_u32 v6, v6, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v11, v12, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v6, v13, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v5, v2, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v7, v10, vcc_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v4, v1, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v3, v0, 0x7060302
+; GFX11-FAKE16-NEXT:  .LBB26_2: ; %end
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = icmp eq i32 %b, 0
   br i1 %cmp, label %cmp.true, label %cmp.false
 
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
index 5bda853b76727..0329f23ea434f 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
@@ -769,5 +769,3 @@ define double @test_pown_fast_f64_known_odd(double %x, i32 %y.arg) {
   ret double %call
 }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
index 8389a8e86cb44..dfa645c8379d5 100644
--- a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
@@ -689,8 +689,6 @@ attributes #5 = { nounwind sanitize_address "amdgpu-no-implicitarg-ptr" }
 attributes #6 = { "enqueued-block" }
 
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
 ;.
 ;.
 ; ATTRIBUTOR_HSA: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
@@ -722,7 +720,3 @@ attributes #6 = { "enqueued-block" }
 ; ATTRIBUTOR_HSA: attributes #[[ATTR26]] = { nounwind }
 ; ATTRIBUTOR_HSA: attributes #[[ATTR27]] = { "enqueued-block" }
 ;.
-; AKF_HSA: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 500}
-;.
-; ATTRIBUTOR_HSA: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 500}
-;.
diff --git a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
index 0e387716dda99..6f7193064641c 100644
--- a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
+++ b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
@@ -472,8 +472,6 @@ define void @use_alloca_func() #1 {
 attributes #0 = { nounwind readnone speculatable }
 attributes #1 = { nounwind }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
 
 ; AKF_HSA: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 500}
 ;.
@@ -492,5 +490,3 @@ attributes #1 = { nounwind }
 ; HSA: attributes #[[ATTR12]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
 ; HSA: attributes #[[ATTR13]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
 ;.
-; HSA: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 500}
-;.
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
index c019c83da5ef8..f979d01e495ba 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
@@ -4,19 +4,27 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=Iterative -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9_ITERATIVE %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=Iterative -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1064,GFX1064_ITERATIVE %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=Iterative -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1032,GFX1032_ITERATIVE %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=Iterative -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1164,GFX1164_ITERATIVE %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=Iterative -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1132,GFX1132_ITERATIVE %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=Iterative -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1264,GFX1264_ITERATIVE %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=Iterative -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1232,GFX1232_ITERATIVE %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=Iterative -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1164,GFX1164-TRUE16,GFX1164_ITERATIVE,GFX1164_ITERATIVE-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=Iterative -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1164,GFX1164-FAKE16,GFX1164_ITERATIVE,GFX1164_ITERATIVE-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=+wavefrontsize32 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=Iterative -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1132,GFX1132-TRUE16,GFX1132_ITERATIVE,GFX1132_ITERATIVE-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=+wavefrontsize32 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=Iterative -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1132,GFX1132-FAKE16,GFX1132_ITERATIVE,GFX1132_ITERATIVE-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -mattr=+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=Iterative -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1264,GFX1264-TRUE16,GFX1264_ITERATIVE,GFX1264_ITERATIVE-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -mattr=+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=Iterative -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1264,GFX1264-FAKE16,GFX1264_ITERATIVE,GFX1264_ITERATIVE-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -mattr=+wavefrontsize32 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=Iterative -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1232,GFX1232-TRUE16,GFX1232_ITERATIVE,GFX1232_ITERATIVE-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -mattr=+wavefrontsize32 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=Iterative -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1232,GFX1232-FAKE16,GFX1232_ITERATIVE,GFX1232_ITERATIVE-FAKE16 %s
 ; RUN: llc -mtriple=amdgcn -amdgpu-atomic-optimizer-strategy=DPP -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX7LESS,GFX7LESS_DPP %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX8,GFX8_DPP %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9_DPP %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1064,GFX1064_DPP %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1032,GFX1032_DPP %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1164,GFX1164_DPP %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1132,GFX1132_DPP %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1264,GFX1264_DPP %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1232,GFX1232_DPP %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1164,GFX1164-TRUE16,GFX1164_DPP,GFX1164_DPP-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1164,GFX1164-FAKE16,GFX1164_DPP,GFX1164_DPP-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=+wavefrontsize32 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1132,GFX1132-TRUE16,GFX1132_DPP,GFX1132_DPP-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=+wavefrontsize32 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1132,GFX1132-FAKE16,GFX1132_DPP,GFX1132_DPP-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -mattr=+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1264,GFX1264-TRUE16,GFX1264_DPP,GFX1264_DPP-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -mattr=+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1264,GFX1264-FAKE16,GFX1264_DPP,GFX1264_DPP-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -mattr=+wavefrontsize32 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1232,GFX1232-TRUE16,GFX1232_DPP,GFX1232_DPP-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -mattr=+wavefrontsize32 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1232,GFX1232-FAKE16,GFX1232_DPP,GFX1232_DPP-FAKE16 %s
 
 declare i32 @llvm.amdgcn.workitem.id.x()
 
@@ -7289,163 +7297,325 @@ define amdgpu_kernel void @uniform_or_i8(ptr addrspace(1) %result, ptr addrspace
 ; GFX1032-NEXT:    buffer_store_byte v0, off, s[0:3], 0
 ; GFX1032-NEXT:    s_endpgm
 ;
-; GFX1164-LABEL: uniform_or_i8:
-; GFX1164:       ; %bb.0:
-; GFX1164-NEXT:    s_clause 0x1
-; GFX1164-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1164-NEXT:    s_load_b32 s6, s[4:5], 0x34
-; GFX1164-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1164-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
-; GFX1164-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX1164-NEXT:    ; implicit-def: $vgpr0
-; GFX1164-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GFX1164-NEXT:    s_cbranch_execz .LBB12_2
-; GFX1164-NEXT:  ; %bb.1:
-; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_and_b32 s7, s2, 3
-; GFX1164-NEXT:    s_and_b32 s8, s6, 0xff
-; GFX1164-NEXT:    s_lshl_b32 s7, s7, 3
-; GFX1164-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX1164-NEXT:    s_lshl_b32 s9, s8, s7
-; GFX1164-NEXT:    s_and_b32 s8, s2, -4
-; GFX1164-NEXT:    v_mov_b32_e32 v0, s9
-; GFX1164-NEXT:    s_mov_b32 s10, -1
-; GFX1164-NEXT:    s_mov_b32 s9, s3
-; GFX1164-NEXT:    buffer_atomic_or_b32 v0, off, s[8:11], 0 glc
-; GFX1164-NEXT:    s_waitcnt vmcnt(0)
-; GFX1164-NEXT:    v_lshrrev_b32_e32 v0, s7, v0
-; GFX1164-NEXT:  .LBB12_2:
-; GFX1164-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1164-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX1164-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX1164-NEXT:    v_cndmask_b32_e64 v0, s6, 0, vcc
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1164-NEXT:    v_or_b32_e32 v0, s2, v0
-; GFX1164-NEXT:    s_mov_b32 s2, -1
-; GFX1164-NEXT:    buffer_store_b8 v0, off, s[0:3], 0
-; GFX1164-NEXT:    s_endpgm
-;
-; GFX1132-LABEL: uniform_or_i8:
-; GFX1132:       ; %bb.0:
-; GFX1132-NEXT:    s_clause 0x1
-; GFX1132-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1132-NEXT:    s_load_b32 s4, s[4:5], 0x34
-; GFX1132-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1132-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX1132-NEXT:    ; implicit-def: $vgpr0
-; GFX1132-NEXT:    s_and_saveexec_b32 s5, vcc_lo
-; GFX1132-NEXT:    s_cbranch_execz .LBB12_2
-; GFX1132-NEXT:  ; %bb.1:
-; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_and_b32 s6, s2, 3
-; GFX1132-NEXT:    s_and_b32 s7, s4, 0xff
-; GFX1132-NEXT:    s_lshl_b32 s6, s6, 3
-; GFX1132-NEXT:    s_and_b32 s8, s2, -4
-; GFX1132-NEXT:    s_lshl_b32 s7, s7, s6
-; GFX1132-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX1132-NEXT:    v_mov_b32_e32 v0, s7
-; GFX1132-NEXT:    s_mov_b32 s10, -1
-; GFX1132-NEXT:    s_mov_b32 s9, s3
-; GFX1132-NEXT:    buffer_atomic_or_b32 v0, off, s[8:11], 0 glc
-; GFX1132-NEXT:    s_waitcnt vmcnt(0)
-; GFX1132-NEXT:    v_lshrrev_b32_e32 v0, s6, v0
-; GFX1132-NEXT:  .LBB12_2:
-; GFX1132-NEXT:    s_or_b32 exec_lo, exec_lo, s5
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1132-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX1132-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX1132-NEXT:    v_cndmask_b32_e64 v0, s4, 0, vcc_lo
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1132-NEXT:    v_or_b32_e32 v0, s2, v0
-; GFX1132-NEXT:    s_mov_b32 s2, -1
-; GFX1132-NEXT:    buffer_store_b8 v0, off, s[0:3], 0
-; GFX1132-NEXT:    s_endpgm
-;
-; GFX1264-LABEL: uniform_or_i8:
-; GFX1264:       ; %bb.0:
-; GFX1264-NEXT:    s_clause 0x1
-; GFX1264-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1264-NEXT:    s_load_b32 s6, s[4:5], 0x34
-; GFX1264-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1264-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1264-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
-; GFX1264-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX1264-NEXT:    ; implicit-def: $vgpr0
-; GFX1264-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GFX1264-NEXT:    s_cbranch_execz .LBB12_2
-; GFX1264-NEXT:  ; %bb.1:
-; GFX1264-NEXT:    s_wait_kmcnt 0x0
-; GFX1264-NEXT:    s_and_b32 s7, s2, 3
-; GFX1264-NEXT:    s_and_b32 s8, s6, 0xff
-; GFX1264-NEXT:    s_lshl_b32 s7, s7, 3
-; GFX1264-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX1264-NEXT:    s_lshl_b32 s9, s8, s7
-; GFX1264-NEXT:    s_and_b32 s8, s2, -4
-; GFX1264-NEXT:    v_mov_b32_e32 v0, s9
-; GFX1264-NEXT:    s_mov_b32 s10, -1
-; GFX1264-NEXT:    s_mov_b32 s9, s3
-; GFX1264-NEXT:    buffer_atomic_or_b32 v0, off, s[8:11], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
-; GFX1264-NEXT:    s_wait_loadcnt 0x0
-; GFX1264-NEXT:    v_lshrrev_b32_e32 v0, s7, v0
-; GFX1264-NEXT:  .LBB12_2:
-; GFX1264-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GFX1264-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1264-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX1264-NEXT:    s_wait_kmcnt 0x0
-; GFX1264-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX1264-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX1264-NEXT:    v_cndmask_b32_e64 v0, s6, 0, vcc
-; GFX1264-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1264-NEXT:    v_or_b32_e32 v0, s2, v0
-; GFX1264-NEXT:    s_mov_b32 s2, -1
-; GFX1264-NEXT:    buffer_store_b8 v0, off, s[0:3], null
-; GFX1264-NEXT:    s_endpgm
-;
-; GFX1232-LABEL: uniform_or_i8:
-; GFX1232:       ; %bb.0:
-; GFX1232-NEXT:    s_clause 0x1
-; GFX1232-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1232-NEXT:    s_load_b32 s4, s[4:5], 0x34
-; GFX1232-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1232-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1232-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX1232-NEXT:    ; implicit-def: $vgpr0
-; GFX1232-NEXT:    s_and_saveexec_b32 s5, vcc_lo
-; GFX1232-NEXT:    s_cbranch_execz .LBB12_2
-; GFX1232-NEXT:  ; %bb.1:
-; GFX1232-NEXT:    s_wait_kmcnt 0x0
-; GFX1232-NEXT:    s_and_b32 s6, s2, 3
-; GFX1232-NEXT:    s_and_b32 s7, s4, 0xff
-; GFX1232-NEXT:    s_lshl_b32 s6, s6, 3
-; GFX1232-NEXT:    s_and_b32 s8, s2, -4
-; GFX1232-NEXT:    s_lshl_b32 s7, s7, s6
-; GFX1232-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX1232-NEXT:    v_mov_b32_e32 v0, s7
-; GFX1232-NEXT:    s_mov_b32 s10, -1
-; GFX1232-NEXT:    s_mov_b32 s9, s3
-; GFX1232-NEXT:    buffer_atomic_or_b32 v0, off, s[8:11], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
-; GFX1232-NEXT:    s_wait_loadcnt 0x0
-; GFX1232-NEXT:    v_lshrrev_b32_e32 v0, s6, v0
-; GFX1232-NEXT:  .LBB12_2:
-; GFX1232-NEXT:    s_or_b32 exec_lo, exec_lo, s5
-; GFX1232-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1232-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX1232-NEXT:    s_wait_kmcnt 0x0
-; GFX1232-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX1232-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX1232-NEXT:    v_cndmask_b32_e64 v0, s4, 0, vcc_lo
-; GFX1232-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1232-NEXT:    v_or_b32_e32 v0, s2, v0
-; GFX1232-NEXT:    s_mov_b32 s2, -1
-; GFX1232-NEXT:    buffer_store_b8 v0, off, s[0:3], null
-; GFX1232-NEXT:    s_endpgm
+; GFX1164-TRUE16-LABEL: uniform_or_i8:
+; GFX1164-TRUE16:       ; %bb.0:
+; GFX1164-TRUE16-NEXT:    s_clause 0x1
+; GFX1164-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1164-TRUE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; GFX1164-TRUE16-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164-TRUE16-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1164-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1164-TRUE16-NEXT:    ; implicit-def: $vgpr0_lo16
+; GFX1164-TRUE16-NEXT:    s_and_saveexec_b64 s[4:5], vcc
+; GFX1164-TRUE16-NEXT:    s_cbranch_execz .LBB12_2
+; GFX1164-TRUE16-NEXT:  ; %bb.1:
+; GFX1164-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-TRUE16-NEXT:    s_and_b32 s7, s2, 3
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s8, s6
+; GFX1164-TRUE16-NEXT:    s_lshl_b32 s7, s7, 3
+; GFX1164-TRUE16-NEXT:    s_and_b32 s8, s8, 0xff
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX1164-TRUE16-NEXT:    s_lshl_b32 s9, s8, s7
+; GFX1164-TRUE16-NEXT:    s_and_b32 s8, s2, -4
+; GFX1164-TRUE16-NEXT:    v_mov_b32_e32 v0, s9
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s9, s3
+; GFX1164-TRUE16-NEXT:    buffer_atomic_or_b32 v0, off, s[8:11], 0 glc
+; GFX1164-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1164-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s7, v0
+; GFX1164-TRUE16-NEXT:  .LBB12_2:
+; GFX1164-TRUE16-NEXT:    s_or_b64 exec, exec, s[4:5]
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1164-TRUE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX1164-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1164-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1164-TRUE16-NEXT:    v_cndmask_b16 v0.l, s6, 0, vcc
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1164-TRUE16-NEXT:    v_or_b16 v0.l, s2, v0.l
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1164-TRUE16-NEXT:    buffer_store_b8 v0, off, s[0:3], 0
+; GFX1164-TRUE16-NEXT:    s_endpgm
+;
+; GFX1164-FAKE16-LABEL: uniform_or_i8:
+; GFX1164-FAKE16:       ; %bb.0:
+; GFX1164-FAKE16-NEXT:    s_clause 0x1
+; GFX1164-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1164-FAKE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; GFX1164-FAKE16-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164-FAKE16-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1164-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1164-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; GFX1164-FAKE16-NEXT:    s_and_saveexec_b64 s[4:5], vcc
+; GFX1164-FAKE16-NEXT:    s_cbranch_execz .LBB12_2
+; GFX1164-FAKE16-NEXT:  ; %bb.1:
+; GFX1164-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-FAKE16-NEXT:    s_and_b32 s7, s2, 3
+; GFX1164-FAKE16-NEXT:    s_and_b32 s8, s6, 0xff
+; GFX1164-FAKE16-NEXT:    s_lshl_b32 s7, s7, 3
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX1164-FAKE16-NEXT:    s_lshl_b32 s9, s8, s7
+; GFX1164-FAKE16-NEXT:    s_and_b32 s8, s2, -4
+; GFX1164-FAKE16-NEXT:    v_mov_b32_e32 v0, s9
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s9, s3
+; GFX1164-FAKE16-NEXT:    buffer_atomic_or_b32 v0, off, s[8:11], 0 glc
+; GFX1164-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1164-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s7, v0
+; GFX1164-FAKE16-NEXT:  .LBB12_2:
+; GFX1164-FAKE16-NEXT:    s_or_b64 exec, exec, s[4:5]
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1164-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX1164-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1164-FAKE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1164-FAKE16-NEXT:    v_cndmask_b32_e64 v0, s6, 0, vcc
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1164-FAKE16-NEXT:    v_or_b32_e32 v0, s2, v0
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1164-FAKE16-NEXT:    buffer_store_b8 v0, off, s[0:3], 0
+; GFX1164-FAKE16-NEXT:    s_endpgm
+;
+; GFX1132-TRUE16-LABEL: uniform_or_i8:
+; GFX1132-TRUE16:       ; %bb.0:
+; GFX1132-TRUE16-NEXT:    s_clause 0x1
+; GFX1132-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1132-TRUE16-NEXT:    s_load_b32 s4, s[4:5], 0x34
+; GFX1132-TRUE16-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1132-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1132-TRUE16-NEXT:    ; implicit-def: $vgpr0_lo16
+; GFX1132-TRUE16-NEXT:    s_and_saveexec_b32 s5, vcc_lo
+; GFX1132-TRUE16-NEXT:    s_cbranch_execz .LBB12_2
+; GFX1132-TRUE16-NEXT:  ; %bb.1:
+; GFX1132-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-TRUE16-NEXT:    s_and_b32 s6, s2, 3
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s7, s4
+; GFX1132-TRUE16-NEXT:    s_lshl_b32 s6, s6, 3
+; GFX1132-TRUE16-NEXT:    s_and_b32 s7, s7, 0xff
+; GFX1132-TRUE16-NEXT:    s_and_b32 s8, s2, -4
+; GFX1132-TRUE16-NEXT:    s_lshl_b32 s7, s7, s6
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX1132-TRUE16-NEXT:    v_mov_b32_e32 v0, s7
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s9, s3
+; GFX1132-TRUE16-NEXT:    buffer_atomic_or_b32 v0, off, s[8:11], 0 glc
+; GFX1132-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1132-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s6, v0
+; GFX1132-TRUE16-NEXT:  .LBB12_2:
+; GFX1132-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s5
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1132-TRUE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX1132-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1132-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1132-TRUE16-NEXT:    v_cndmask_b16 v0.l, s4, 0, vcc_lo
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1132-TRUE16-NEXT:    v_or_b16 v0.l, s2, v0.l
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1132-TRUE16-NEXT:    buffer_store_b8 v0, off, s[0:3], 0
+; GFX1132-TRUE16-NEXT:    s_endpgm
+;
+; GFX1132-FAKE16-LABEL: uniform_or_i8:
+; GFX1132-FAKE16:       ; %bb.0:
+; GFX1132-FAKE16-NEXT:    s_clause 0x1
+; GFX1132-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1132-FAKE16-NEXT:    s_load_b32 s4, s[4:5], 0x34
+; GFX1132-FAKE16-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1132-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1132-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; GFX1132-FAKE16-NEXT:    s_and_saveexec_b32 s5, vcc_lo
+; GFX1132-FAKE16-NEXT:    s_cbranch_execz .LBB12_2
+; GFX1132-FAKE16-NEXT:  ; %bb.1:
+; GFX1132-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-FAKE16-NEXT:    s_and_b32 s6, s2, 3
+; GFX1132-FAKE16-NEXT:    s_and_b32 s7, s4, 0xff
+; GFX1132-FAKE16-NEXT:    s_lshl_b32 s6, s6, 3
+; GFX1132-FAKE16-NEXT:    s_and_b32 s8, s2, -4
+; GFX1132-FAKE16-NEXT:    s_lshl_b32 s7, s7, s6
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX1132-FAKE16-NEXT:    v_mov_b32_e32 v0, s7
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s9, s3
+; GFX1132-FAKE16-NEXT:    buffer_atomic_or_b32 v0, off, s[8:11], 0 glc
+; GFX1132-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1132-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s6, v0
+; GFX1132-FAKE16-NEXT:  .LBB12_2:
+; GFX1132-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s5
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1132-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX1132-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1132-FAKE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1132-FAKE16-NEXT:    v_cndmask_b32_e64 v0, s4, 0, vcc_lo
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1132-FAKE16-NEXT:    v_or_b32_e32 v0, s2, v0
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1132-FAKE16-NEXT:    buffer_store_b8 v0, off, s[0:3], 0
+; GFX1132-FAKE16-NEXT:    s_endpgm
+;
+; GFX1264-TRUE16-LABEL: uniform_or_i8:
+; GFX1264-TRUE16:       ; %bb.0:
+; GFX1264-TRUE16-NEXT:    s_clause 0x1
+; GFX1264-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1264-TRUE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; GFX1264-TRUE16-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1264-TRUE16-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1264-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1264-TRUE16-NEXT:    ; implicit-def: $vgpr0_lo16
+; GFX1264-TRUE16-NEXT:    s_and_saveexec_b64 s[4:5], vcc
+; GFX1264-TRUE16-NEXT:    s_cbranch_execz .LBB12_2
+; GFX1264-TRUE16-NEXT:  ; %bb.1:
+; GFX1264-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-TRUE16-NEXT:    s_and_b32 s7, s2, 3
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s8, s6
+; GFX1264-TRUE16-NEXT:    s_lshl_b32 s7, s7, 3
+; GFX1264-TRUE16-NEXT:    s_and_b32 s8, s8, 0xff
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX1264-TRUE16-NEXT:    s_lshl_b32 s9, s8, s7
+; GFX1264-TRUE16-NEXT:    s_and_b32 s8, s2, -4
+; GFX1264-TRUE16-NEXT:    v_mov_b32_e32 v0, s9
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s9, s3
+; GFX1264-TRUE16-NEXT:    buffer_atomic_or_b32 v0, off, s[8:11], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1264-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1264-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s7, v0
+; GFX1264-TRUE16-NEXT:  .LBB12_2:
+; GFX1264-TRUE16-NEXT:    s_or_b64 exec, exec, s[4:5]
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1264-TRUE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX1264-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1264-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1264-TRUE16-NEXT:    v_cndmask_b16 v0.l, s6, 0, vcc
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1264-TRUE16-NEXT:    v_or_b16 v0.l, s2, v0.l
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1264-TRUE16-NEXT:    buffer_store_b8 v0, off, s[0:3], null
+; GFX1264-TRUE16-NEXT:    s_endpgm
+;
+; GFX1264-FAKE16-LABEL: uniform_or_i8:
+; GFX1264-FAKE16:       ; %bb.0:
+; GFX1264-FAKE16-NEXT:    s_clause 0x1
+; GFX1264-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1264-FAKE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; GFX1264-FAKE16-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1264-FAKE16-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1264-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1264-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; GFX1264-FAKE16-NEXT:    s_and_saveexec_b64 s[4:5], vcc
+; GFX1264-FAKE16-NEXT:    s_cbranch_execz .LBB12_2
+; GFX1264-FAKE16-NEXT:  ; %bb.1:
+; GFX1264-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-FAKE16-NEXT:    s_and_b32 s7, s2, 3
+; GFX1264-FAKE16-NEXT:    s_and_b32 s8, s6, 0xff
+; GFX1264-FAKE16-NEXT:    s_lshl_b32 s7, s7, 3
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX1264-FAKE16-NEXT:    s_lshl_b32 s9, s8, s7
+; GFX1264-FAKE16-NEXT:    s_and_b32 s8, s2, -4
+; GFX1264-FAKE16-NEXT:    v_mov_b32_e32 v0, s9
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s9, s3
+; GFX1264-FAKE16-NEXT:    buffer_atomic_or_b32 v0, off, s[8:11], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1264-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1264-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s7, v0
+; GFX1264-FAKE16-NEXT:  .LBB12_2:
+; GFX1264-FAKE16-NEXT:    s_or_b64 exec, exec, s[4:5]
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1264-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX1264-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1264-FAKE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1264-FAKE16-NEXT:    v_cndmask_b32_e64 v0, s6, 0, vcc
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1264-FAKE16-NEXT:    v_or_b32_e32 v0, s2, v0
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1264-FAKE16-NEXT:    buffer_store_b8 v0, off, s[0:3], null
+; GFX1264-FAKE16-NEXT:    s_endpgm
+;
+; GFX1232-TRUE16-LABEL: uniform_or_i8:
+; GFX1232-TRUE16:       ; %bb.0:
+; GFX1232-TRUE16-NEXT:    s_clause 0x1
+; GFX1232-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1232-TRUE16-NEXT:    s_load_b32 s4, s[4:5], 0x34
+; GFX1232-TRUE16-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1232-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1232-TRUE16-NEXT:    ; implicit-def: $vgpr0_lo16
+; GFX1232-TRUE16-NEXT:    s_and_saveexec_b32 s5, vcc_lo
+; GFX1232-TRUE16-NEXT:    s_cbranch_execz .LBB12_2
+; GFX1232-TRUE16-NEXT:  ; %bb.1:
+; GFX1232-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-TRUE16-NEXT:    s_and_b32 s6, s2, 3
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s7, s4
+; GFX1232-TRUE16-NEXT:    s_lshl_b32 s6, s6, 3
+; GFX1232-TRUE16-NEXT:    s_and_b32 s7, s7, 0xff
+; GFX1232-TRUE16-NEXT:    s_and_b32 s8, s2, -4
+; GFX1232-TRUE16-NEXT:    s_lshl_b32 s7, s7, s6
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX1232-TRUE16-NEXT:    v_mov_b32_e32 v0, s7
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s9, s3
+; GFX1232-TRUE16-NEXT:    buffer_atomic_or_b32 v0, off, s[8:11], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1232-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1232-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s6, v0
+; GFX1232-TRUE16-NEXT:  .LBB12_2:
+; GFX1232-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s5
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1232-TRUE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX1232-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1232-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1232-TRUE16-NEXT:    v_cndmask_b16 v0.l, s4, 0, vcc_lo
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1232-TRUE16-NEXT:    v_or_b16 v0.l, s2, v0.l
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1232-TRUE16-NEXT:    buffer_store_b8 v0, off, s[0:3], null
+; GFX1232-TRUE16-NEXT:    s_endpgm
+;
+; GFX1232-FAKE16-LABEL: uniform_or_i8:
+; GFX1232-FAKE16:       ; %bb.0:
+; GFX1232-FAKE16-NEXT:    s_clause 0x1
+; GFX1232-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1232-FAKE16-NEXT:    s_load_b32 s4, s[4:5], 0x34
+; GFX1232-FAKE16-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1232-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1232-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; GFX1232-FAKE16-NEXT:    s_and_saveexec_b32 s5, vcc_lo
+; GFX1232-FAKE16-NEXT:    s_cbranch_execz .LBB12_2
+; GFX1232-FAKE16-NEXT:  ; %bb.1:
+; GFX1232-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-FAKE16-NEXT:    s_and_b32 s6, s2, 3
+; GFX1232-FAKE16-NEXT:    s_and_b32 s7, s4, 0xff
+; GFX1232-FAKE16-NEXT:    s_lshl_b32 s6, s6, 3
+; GFX1232-FAKE16-NEXT:    s_and_b32 s8, s2, -4
+; GFX1232-FAKE16-NEXT:    s_lshl_b32 s7, s7, s6
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX1232-FAKE16-NEXT:    v_mov_b32_e32 v0, s7
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s9, s3
+; GFX1232-FAKE16-NEXT:    buffer_atomic_or_b32 v0, off, s[8:11], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1232-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1232-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s6, v0
+; GFX1232-FAKE16-NEXT:  .LBB12_2:
+; GFX1232-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s5
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1232-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX1232-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1232-FAKE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1232-FAKE16-NEXT:    v_cndmask_b32_e64 v0, s4, 0, vcc_lo
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1232-FAKE16-NEXT:    v_or_b32_e32 v0, s2, v0
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1232-FAKE16-NEXT:    buffer_store_b8 v0, off, s[0:3], null
+; GFX1232-FAKE16-NEXT:    s_endpgm
   %rmw = atomicrmw or ptr addrspace(1) %uniform.ptr, i8 %val monotonic, align 1
   store i8 %rmw, ptr addrspace(1) %result
   ret void
@@ -7745,262 +7915,524 @@ define amdgpu_kernel void @uniform_add_i8(ptr addrspace(1) %result, ptr addrspac
 ; GFX1032-NEXT:    buffer_store_byte v0, off, s[0:3], 0
 ; GFX1032-NEXT:    s_endpgm
 ;
-; GFX1164-LABEL: uniform_add_i8:
-; GFX1164:       ; %bb.0:
-; GFX1164-NEXT:    s_clause 0x1
-; GFX1164-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1164-NEXT:    s_load_b32 s10, s[4:5], 0x34
-; GFX1164-NEXT:    s_mov_b64 s[6:7], exec
-; GFX1164-NEXT:    s_mov_b64 s[8:9], exec
-; GFX1164-NEXT:    v_mbcnt_lo_u32_b32 v0, s6, 0
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1164-NEXT:    v_mbcnt_hi_u32_b32 v4, s7, v0
-; GFX1164-NEXT:    ; implicit-def: $vgpr0
-; GFX1164-NEXT:    v_cmpx_eq_u32_e32 0, v4
-; GFX1164-NEXT:    s_cbranch_execz .LBB13_4
-; GFX1164-NEXT:  ; %bb.1:
-; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_and_b32 s4, s2, -4
-; GFX1164-NEXT:    s_mov_b32 s5, s3
-; GFX1164-NEXT:    s_and_b32 s2, s2, 3
-; GFX1164-NEXT:    s_load_b32 s3, s[4:5], 0x0
-; GFX1164-NEXT:    s_bcnt1_i32_b64 s6, s[6:7]
-; GFX1164-NEXT:    s_lshl_b32 s11, s2, 3
-; GFX1164-NEXT:    s_mul_i32 s2, s10, s6
-; GFX1164-NEXT:    s_lshl_b32 s12, 0xff, s11
-; GFX1164-NEXT:    s_and_b32 s2, s2, 0xff
-; GFX1164-NEXT:    s_not_b32 s13, s12
-; GFX1164-NEXT:    s_lshl_b32 s14, s2, s11
-; GFX1164-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1164-NEXT:    s_mov_b32 s6, -1
-; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    v_mov_b32_e32 v1, s3
-; GFX1164-NEXT:    s_mov_b64 s[2:3], 0
-; GFX1164-NEXT:  .LBB13_2: ; %atomicrmw.start
-; GFX1164-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1164-NEXT:    v_add_nc_u32_e32 v0, s14, v1
-; GFX1164-NEXT:    v_and_b32_e32 v0, s12, v0
-; GFX1164-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1164-NEXT:    v_and_or_b32 v0, v1, s13, v0
-; GFX1164-NEXT:    v_mov_b32_e32 v3, v1
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX1164-NEXT:    v_mov_b32_e32 v2, v0
-; GFX1164-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
-; GFX1164-NEXT:    s_waitcnt vmcnt(0)
-; GFX1164-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
-; GFX1164-NEXT:    v_mov_b32_e32 v1, v2
-; GFX1164-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
-; GFX1164-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
-; GFX1164-NEXT:    s_cbranch_execnz .LBB13_2
-; GFX1164-NEXT:  ; %bb.3: ; %atomicrmw.end
-; GFX1164-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX1164-NEXT:    v_lshrrev_b32_e32 v0, s11, v2
-; GFX1164-NEXT:  .LBB13_4: ; %Flow
-; GFX1164-NEXT:    s_or_b64 exec, exec, s[8:9]
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1164-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX1164-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1164-NEXT:    v_mad_u16 v0, s10, v4, s2
-; GFX1164-NEXT:    s_mov_b32 s2, -1
-; GFX1164-NEXT:    buffer_store_b8 v0, off, s[0:3], 0
-; GFX1164-NEXT:    s_endpgm
-;
-; GFX1132-LABEL: uniform_add_i8:
-; GFX1132:       ; %bb.0:
-; GFX1132-NEXT:    s_clause 0x1
-; GFX1132-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1132-NEXT:    s_load_b32 s8, s[4:5], 0x34
-; GFX1132-NEXT:    s_mov_b32 s6, exec_lo
-; GFX1132-NEXT:    s_mov_b32 s10, 0
-; GFX1132-NEXT:    v_mbcnt_lo_u32_b32 v4, s6, 0
-; GFX1132-NEXT:    s_mov_b32 s9, exec_lo
-; GFX1132-NEXT:    ; implicit-def: $vgpr0
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1132-NEXT:    v_cmpx_eq_u32_e32 0, v4
-; GFX1132-NEXT:    s_cbranch_execz .LBB13_4
-; GFX1132-NEXT:  ; %bb.1:
-; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_and_b32 s4, s2, -4
-; GFX1132-NEXT:    s_mov_b32 s5, s3
-; GFX1132-NEXT:    s_and_b32 s2, s2, 3
-; GFX1132-NEXT:    s_load_b32 s7, s[4:5], 0x0
-; GFX1132-NEXT:    s_bcnt1_i32_b32 s6, s6
-; GFX1132-NEXT:    s_lshl_b32 s2, s2, 3
-; GFX1132-NEXT:    s_mul_i32 s6, s8, s6
-; GFX1132-NEXT:    s_lshl_b32 s3, 0xff, s2
-; GFX1132-NEXT:    s_and_b32 s6, s6, 0xff
-; GFX1132-NEXT:    s_not_b32 s11, s3
-; GFX1132-NEXT:    s_lshl_b32 s12, s6, s2
-; GFX1132-NEXT:    s_mov_b32 s6, -1
-; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    v_mov_b32_e32 v1, s7
-; GFX1132-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1132-NEXT:  .LBB13_2: ; %atomicrmw.start
-; GFX1132-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1132-NEXT:    v_add_nc_u32_e32 v0, s12, v1
-; GFX1132-NEXT:    v_and_b32_e32 v0, s3, v0
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1132-NEXT:    v_and_or_b32 v0, v1, s11, v0
-; GFX1132-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
-; GFX1132-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
-; GFX1132-NEXT:    s_waitcnt vmcnt(0)
-; GFX1132-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
-; GFX1132-NEXT:    v_mov_b32_e32 v1, v2
-; GFX1132-NEXT:    s_or_b32 s10, vcc_lo, s10
-; GFX1132-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s10
-; GFX1132-NEXT:    s_cbranch_execnz .LBB13_2
-; GFX1132-NEXT:  ; %bb.3: ; %atomicrmw.end
-; GFX1132-NEXT:    s_or_b32 exec_lo, exec_lo, s10
-; GFX1132-NEXT:    v_lshrrev_b32_e32 v0, s2, v2
-; GFX1132-NEXT:  .LBB13_4: ; %Flow
-; GFX1132-NEXT:    s_or_b32 exec_lo, exec_lo, s9
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1132-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX1132-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1132-NEXT:    v_mad_u16 v0, s8, v4, s2
-; GFX1132-NEXT:    s_mov_b32 s2, -1
-; GFX1132-NEXT:    buffer_store_b8 v0, off, s[0:3], 0
-; GFX1132-NEXT:    s_endpgm
-;
-; GFX1264-LABEL: uniform_add_i8:
-; GFX1264:       ; %bb.0:
-; GFX1264-NEXT:    s_clause 0x1
-; GFX1264-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1264-NEXT:    s_load_b32 s10, s[4:5], 0x34
-; GFX1264-NEXT:    s_mov_b64 s[6:7], exec
-; GFX1264-NEXT:    s_mov_b64 s[8:9], exec
-; GFX1264-NEXT:    v_mbcnt_lo_u32_b32 v0, s6, 0
-; GFX1264-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1264-NEXT:    v_mbcnt_hi_u32_b32 v4, s7, v0
-; GFX1264-NEXT:    ; implicit-def: $vgpr0
-; GFX1264-NEXT:    v_cmpx_eq_u32_e32 0, v4
-; GFX1264-NEXT:    s_cbranch_execz .LBB13_4
-; GFX1264-NEXT:  ; %bb.1:
-; GFX1264-NEXT:    s_wait_kmcnt 0x0
-; GFX1264-NEXT:    s_and_b32 s4, s2, -4
-; GFX1264-NEXT:    s_mov_b32 s5, s3
-; GFX1264-NEXT:    s_and_b32 s2, s2, 3
-; GFX1264-NEXT:    s_load_b32 s3, s[4:5], 0x0
-; GFX1264-NEXT:    s_bcnt1_i32_b64 s6, s[6:7]
-; GFX1264-NEXT:    s_lshl_b32 s11, s2, 3
-; GFX1264-NEXT:    s_wait_alu 0xfffe
-; GFX1264-NEXT:    s_mul_i32 s2, s10, s6
-; GFX1264-NEXT:    s_lshl_b32 s12, 0xff, s11
-; GFX1264-NEXT:    s_and_b32 s2, s2, 0xff
-; GFX1264-NEXT:    s_not_b32 s13, s12
-; GFX1264-NEXT:    s_lshl_b32 s14, s2, s11
-; GFX1264-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1264-NEXT:    s_mov_b32 s6, -1
-; GFX1264-NEXT:    s_wait_kmcnt 0x0
-; GFX1264-NEXT:    v_mov_b32_e32 v1, s3
-; GFX1264-NEXT:    s_mov_b64 s[2:3], 0
-; GFX1264-NEXT:  .LBB13_2: ; %atomicrmw.start
-; GFX1264-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX1264-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1264-NEXT:    v_add_nc_u32_e32 v0, s14, v1
-; GFX1264-NEXT:    v_and_b32_e32 v0, s12, v0
-; GFX1264-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1264-NEXT:    v_and_or_b32 v0, v1, s13, v0
-; GFX1264-NEXT:    v_mov_b32_e32 v3, v1
-; GFX1264-NEXT:    v_mov_b32_e32 v2, v0
-; GFX1264-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
-; GFX1264-NEXT:    s_wait_loadcnt 0x0
-; GFX1264-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
-; GFX1264-NEXT:    v_mov_b32_e32 v1, v2
-; GFX1264-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
-; GFX1264-NEXT:    s_wait_alu 0xfffe
-; GFX1264-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
-; GFX1264-NEXT:    s_cbranch_execnz .LBB13_2
-; GFX1264-NEXT:  ; %bb.3: ; %atomicrmw.end
-; GFX1264-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX1264-NEXT:    v_lshrrev_b32_e32 v0, s11, v2
-; GFX1264-NEXT:  .LBB13_4: ; %Flow
-; GFX1264-NEXT:    s_or_b64 exec, exec, s[8:9]
-; GFX1264-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1264-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX1264-NEXT:    s_wait_kmcnt 0x0
-; GFX1264-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX1264-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX1264-NEXT:    s_wait_alu 0xf1ff
-; GFX1264-NEXT:    v_mad_u16 v0, s10, v4, s2
-; GFX1264-NEXT:    s_mov_b32 s2, -1
-; GFX1264-NEXT:    buffer_store_b8 v0, off, s[0:3], null
-; GFX1264-NEXT:    s_endpgm
-;
-; GFX1232-LABEL: uniform_add_i8:
-; GFX1232:       ; %bb.0:
-; GFX1232-NEXT:    s_clause 0x1
-; GFX1232-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1232-NEXT:    s_load_b32 s8, s[4:5], 0x34
-; GFX1232-NEXT:    s_mov_b32 s6, exec_lo
-; GFX1232-NEXT:    s_mov_b32 s10, 0
-; GFX1232-NEXT:    v_mbcnt_lo_u32_b32 v4, s6, 0
-; GFX1232-NEXT:    s_mov_b32 s9, exec_lo
-; GFX1232-NEXT:    ; implicit-def: $vgpr0
-; GFX1232-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1232-NEXT:    v_cmpx_eq_u32_e32 0, v4
-; GFX1232-NEXT:    s_cbranch_execz .LBB13_4
-; GFX1232-NEXT:  ; %bb.1:
-; GFX1232-NEXT:    s_wait_kmcnt 0x0
-; GFX1232-NEXT:    s_and_b32 s4, s2, -4
-; GFX1232-NEXT:    s_mov_b32 s5, s3
-; GFX1232-NEXT:    s_and_b32 s2, s2, 3
-; GFX1232-NEXT:    s_load_b32 s7, s[4:5], 0x0
-; GFX1232-NEXT:    s_bcnt1_i32_b32 s6, s6
-; GFX1232-NEXT:    s_lshl_b32 s2, s2, 3
-; GFX1232-NEXT:    s_wait_alu 0xfffe
-; GFX1232-NEXT:    s_mul_i32 s6, s8, s6
-; GFX1232-NEXT:    s_lshl_b32 s3, 0xff, s2
-; GFX1232-NEXT:    s_wait_alu 0xfffe
-; GFX1232-NEXT:    s_and_b32 s6, s6, 0xff
-; GFX1232-NEXT:    s_not_b32 s11, s3
-; GFX1232-NEXT:    s_wait_alu 0xfffe
-; GFX1232-NEXT:    s_lshl_b32 s12, s6, s2
-; GFX1232-NEXT:    s_mov_b32 s6, -1
-; GFX1232-NEXT:    s_wait_kmcnt 0x0
-; GFX1232-NEXT:    v_mov_b32_e32 v1, s7
-; GFX1232-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1232-NEXT:  .LBB13_2: ; %atomicrmw.start
-; GFX1232-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX1232-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1232-NEXT:    v_add_nc_u32_e32 v0, s12, v1
-; GFX1232-NEXT:    v_and_b32_e32 v0, s3, v0
-; GFX1232-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1232-NEXT:    v_and_or_b32 v0, v1, s11, v0
-; GFX1232-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
-; GFX1232-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
-; GFX1232-NEXT:    s_wait_loadcnt 0x0
-; GFX1232-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
-; GFX1232-NEXT:    v_mov_b32_e32 v1, v2
-; GFX1232-NEXT:    s_or_b32 s10, vcc_lo, s10
-; GFX1232-NEXT:    s_wait_alu 0xfffe
-; GFX1232-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s10
-; GFX1232-NEXT:    s_cbranch_execnz .LBB13_2
-; GFX1232-NEXT:  ; %bb.3: ; %atomicrmw.end
-; GFX1232-NEXT:    s_or_b32 exec_lo, exec_lo, s10
-; GFX1232-NEXT:    v_lshrrev_b32_e32 v0, s2, v2
-; GFX1232-NEXT:  .LBB13_4: ; %Flow
-; GFX1232-NEXT:    s_or_b32 exec_lo, exec_lo, s9
-; GFX1232-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1232-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX1232-NEXT:    s_wait_kmcnt 0x0
-; GFX1232-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX1232-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX1232-NEXT:    s_wait_alu 0xf1ff
-; GFX1232-NEXT:    v_mad_u16 v0, s8, v4, s2
-; GFX1232-NEXT:    s_mov_b32 s2, -1
-; GFX1232-NEXT:    buffer_store_b8 v0, off, s[0:3], null
-; GFX1232-NEXT:    s_endpgm
+; GFX1164-TRUE16-LABEL: uniform_add_i8:
+; GFX1164-TRUE16:       ; %bb.0:
+; GFX1164-TRUE16-NEXT:    s_clause 0x1
+; GFX1164-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1164-TRUE16-NEXT:    s_load_b32 s10, s[4:5], 0x34
+; GFX1164-TRUE16-NEXT:    s_mov_b64 s[6:7], exec
+; GFX1164-TRUE16-NEXT:    s_mov_b64 s[8:9], exec
+; GFX1164-TRUE16-NEXT:    v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164-TRUE16-NEXT:    v_mbcnt_hi_u32_b32 v4, s7, v0
+; GFX1164-TRUE16-NEXT:    ; implicit-def: $vgpr0_lo16
+; GFX1164-TRUE16-NEXT:    v_cmpx_eq_u32_e32 0, v4
+; GFX1164-TRUE16-NEXT:    s_cbranch_execz .LBB13_4
+; GFX1164-TRUE16-NEXT:  ; %bb.1:
+; GFX1164-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-TRUE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s5, s3
+; GFX1164-TRUE16-NEXT:    s_bcnt1_i32_b64 s6, s[6:7]
+; GFX1164-TRUE16-NEXT:    s_load_b32 s3, s[4:5], 0x0
+; GFX1164-TRUE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s7, s10
+; GFX1164-TRUE16-NEXT:    s_lshl_b32 s11, s2, 3
+; GFX1164-TRUE16-NEXT:    s_mul_i32 s7, s7, s6
+; GFX1164-TRUE16-NEXT:    s_lshl_b32 s12, 0xff, s11
+; GFX1164-TRUE16-NEXT:    s_and_b32 s2, s7, 0xff
+; GFX1164-TRUE16-NEXT:    s_not_b32 s13, s12
+; GFX1164-TRUE16-NEXT:    s_lshl_b32 s14, s2, s11
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s6, -1
+; GFX1164-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-TRUE16-NEXT:    v_mov_b32_e32 v1, s3
+; GFX1164-TRUE16-NEXT:    s_mov_b64 s[2:3], 0
+; GFX1164-TRUE16-NEXT:  .LBB13_2: ; %atomicrmw.start
+; GFX1164-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164-TRUE16-NEXT:    v_add_nc_u32_e32 v0, s14, v1
+; GFX1164-TRUE16-NEXT:    v_and_b32_e32 v0, s12, v0
+; GFX1164-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1164-TRUE16-NEXT:    v_and_or_b32 v0, v1, s13, v0
+; GFX1164-TRUE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1164-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX1164-TRUE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
+; GFX1164-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1164-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1164-TRUE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1164-TRUE16-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164-TRUE16-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
+; GFX1164-TRUE16-NEXT:    s_cbranch_execnz .LBB13_2
+; GFX1164-TRUE16-NEXT:  ; %bb.3: ; %atomicrmw.end
+; GFX1164-TRUE16-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX1164-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s11, v2
+; GFX1164-TRUE16-NEXT:  .LBB13_4: ; %Flow
+; GFX1164-TRUE16-NEXT:    s_or_b64 exec, exec, s[8:9]
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1164-TRUE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX1164-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1164-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1164-TRUE16-NEXT:    v_mad_u16 v0.l, s10, v4.l, s2
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1164-TRUE16-NEXT:    buffer_store_b8 v0, off, s[0:3], 0
+; GFX1164-TRUE16-NEXT:    s_endpgm
+;
+; GFX1164-FAKE16-LABEL: uniform_add_i8:
+; GFX1164-FAKE16:       ; %bb.0:
+; GFX1164-FAKE16-NEXT:    s_clause 0x1
+; GFX1164-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1164-FAKE16-NEXT:    s_load_b32 s10, s[4:5], 0x34
+; GFX1164-FAKE16-NEXT:    s_mov_b64 s[6:7], exec
+; GFX1164-FAKE16-NEXT:    s_mov_b64 s[8:9], exec
+; GFX1164-FAKE16-NEXT:    v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164-FAKE16-NEXT:    v_mbcnt_hi_u32_b32 v4, s7, v0
+; GFX1164-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; GFX1164-FAKE16-NEXT:    v_cmpx_eq_u32_e32 0, v4
+; GFX1164-FAKE16-NEXT:    s_cbranch_execz .LBB13_4
+; GFX1164-FAKE16-NEXT:  ; %bb.1:
+; GFX1164-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-FAKE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s5, s3
+; GFX1164-FAKE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1164-FAKE16-NEXT:    s_load_b32 s3, s[4:5], 0x0
+; GFX1164-FAKE16-NEXT:    s_bcnt1_i32_b64 s6, s[6:7]
+; GFX1164-FAKE16-NEXT:    s_lshl_b32 s11, s2, 3
+; GFX1164-FAKE16-NEXT:    s_mul_i32 s2, s10, s6
+; GFX1164-FAKE16-NEXT:    s_lshl_b32 s12, 0xff, s11
+; GFX1164-FAKE16-NEXT:    s_and_b32 s2, s2, 0xff
+; GFX1164-FAKE16-NEXT:    s_not_b32 s13, s12
+; GFX1164-FAKE16-NEXT:    s_lshl_b32 s14, s2, s11
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s6, -1
+; GFX1164-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-FAKE16-NEXT:    v_mov_b32_e32 v1, s3
+; GFX1164-FAKE16-NEXT:    s_mov_b64 s[2:3], 0
+; GFX1164-FAKE16-NEXT:  .LBB13_2: ; %atomicrmw.start
+; GFX1164-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164-FAKE16-NEXT:    v_add_nc_u32_e32 v0, s14, v1
+; GFX1164-FAKE16-NEXT:    v_and_b32_e32 v0, s12, v0
+; GFX1164-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1164-FAKE16-NEXT:    v_and_or_b32 v0, v1, s13, v0
+; GFX1164-FAKE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1164-FAKE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX1164-FAKE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
+; GFX1164-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1164-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1164-FAKE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1164-FAKE16-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164-FAKE16-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
+; GFX1164-FAKE16-NEXT:    s_cbranch_execnz .LBB13_2
+; GFX1164-FAKE16-NEXT:  ; %bb.3: ; %atomicrmw.end
+; GFX1164-FAKE16-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX1164-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s11, v2
+; GFX1164-FAKE16-NEXT:  .LBB13_4: ; %Flow
+; GFX1164-FAKE16-NEXT:    s_or_b64 exec, exec, s[8:9]
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1164-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX1164-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1164-FAKE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1164-FAKE16-NEXT:    v_mad_u16 v0, s10, v4, s2
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1164-FAKE16-NEXT:    buffer_store_b8 v0, off, s[0:3], 0
+; GFX1164-FAKE16-NEXT:    s_endpgm
+;
+; GFX1132-TRUE16-LABEL: uniform_add_i8:
+; GFX1132-TRUE16:       ; %bb.0:
+; GFX1132-TRUE16-NEXT:    s_clause 0x1
+; GFX1132-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1132-TRUE16-NEXT:    s_load_b32 s8, s[4:5], 0x34
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s6, exec_lo
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s10, 0
+; GFX1132-TRUE16-NEXT:    v_mbcnt_lo_u32_b32 v4, s6, 0
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s9, exec_lo
+; GFX1132-TRUE16-NEXT:    ; implicit-def: $vgpr0_lo16
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1132-TRUE16-NEXT:    v_cmpx_eq_u32_e32 0, v4
+; GFX1132-TRUE16-NEXT:    s_cbranch_execz .LBB13_4
+; GFX1132-TRUE16-NEXT:  ; %bb.1:
+; GFX1132-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-TRUE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s5, s3
+; GFX1132-TRUE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1132-TRUE16-NEXT:    s_load_b32 s7, s[4:5], 0x0
+; GFX1132-TRUE16-NEXT:    s_bcnt1_i32_b32 s6, s6
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s11, s8
+; GFX1132-TRUE16-NEXT:    s_lshl_b32 s2, s2, 3
+; GFX1132-TRUE16-NEXT:    s_mul_i32 s6, s11, s6
+; GFX1132-TRUE16-NEXT:    s_lshl_b32 s3, 0xff, s2
+; GFX1132-TRUE16-NEXT:    s_and_b32 s6, s6, 0xff
+; GFX1132-TRUE16-NEXT:    s_not_b32 s11, s3
+; GFX1132-TRUE16-NEXT:    s_lshl_b32 s12, s6, s2
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s6, -1
+; GFX1132-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-TRUE16-NEXT:    v_mov_b32_e32 v1, s7
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1132-TRUE16-NEXT:  .LBB13_2: ; %atomicrmw.start
+; GFX1132-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132-TRUE16-NEXT:    v_add_nc_u32_e32 v0, s12, v1
+; GFX1132-TRUE16-NEXT:    v_and_b32_e32 v0, s3, v0
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132-TRUE16-NEXT:    v_and_or_b32 v0, v1, s11, v0
+; GFX1132-TRUE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1132-TRUE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
+; GFX1132-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1132-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1132-TRUE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1132-TRUE16-NEXT:    s_or_b32 s10, vcc_lo, s10
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s10
+; GFX1132-TRUE16-NEXT:    s_cbranch_execnz .LBB13_2
+; GFX1132-TRUE16-NEXT:  ; %bb.3: ; %atomicrmw.end
+; GFX1132-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s10
+; GFX1132-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s2, v2
+; GFX1132-TRUE16-NEXT:  .LBB13_4: ; %Flow
+; GFX1132-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s9
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1132-TRUE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX1132-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1132-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1132-TRUE16-NEXT:    v_mad_u16 v0.l, s8, v4.l, s2
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1132-TRUE16-NEXT:    buffer_store_b8 v0, off, s[0:3], 0
+; GFX1132-TRUE16-NEXT:    s_endpgm
+;
+; GFX1132-FAKE16-LABEL: uniform_add_i8:
+; GFX1132-FAKE16:       ; %bb.0:
+; GFX1132-FAKE16-NEXT:    s_clause 0x1
+; GFX1132-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1132-FAKE16-NEXT:    s_load_b32 s8, s[4:5], 0x34
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s6, exec_lo
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s10, 0
+; GFX1132-FAKE16-NEXT:    v_mbcnt_lo_u32_b32 v4, s6, 0
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s9, exec_lo
+; GFX1132-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1132-FAKE16-NEXT:    v_cmpx_eq_u32_e32 0, v4
+; GFX1132-FAKE16-NEXT:    s_cbranch_execz .LBB13_4
+; GFX1132-FAKE16-NEXT:  ; %bb.1:
+; GFX1132-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-FAKE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s5, s3
+; GFX1132-FAKE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1132-FAKE16-NEXT:    s_load_b32 s7, s[4:5], 0x0
+; GFX1132-FAKE16-NEXT:    s_bcnt1_i32_b32 s6, s6
+; GFX1132-FAKE16-NEXT:    s_lshl_b32 s2, s2, 3
+; GFX1132-FAKE16-NEXT:    s_mul_i32 s6, s8, s6
+; GFX1132-FAKE16-NEXT:    s_lshl_b32 s3, 0xff, s2
+; GFX1132-FAKE16-NEXT:    s_and_b32 s6, s6, 0xff
+; GFX1132-FAKE16-NEXT:    s_not_b32 s11, s3
+; GFX1132-FAKE16-NEXT:    s_lshl_b32 s12, s6, s2
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s6, -1
+; GFX1132-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-FAKE16-NEXT:    v_mov_b32_e32 v1, s7
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1132-FAKE16-NEXT:  .LBB13_2: ; %atomicrmw.start
+; GFX1132-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132-FAKE16-NEXT:    v_add_nc_u32_e32 v0, s12, v1
+; GFX1132-FAKE16-NEXT:    v_and_b32_e32 v0, s3, v0
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132-FAKE16-NEXT:    v_and_or_b32 v0, v1, s11, v0
+; GFX1132-FAKE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1132-FAKE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
+; GFX1132-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1132-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1132-FAKE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1132-FAKE16-NEXT:    s_or_b32 s10, vcc_lo, s10
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s10
+; GFX1132-FAKE16-NEXT:    s_cbranch_execnz .LBB13_2
+; GFX1132-FAKE16-NEXT:  ; %bb.3: ; %atomicrmw.end
+; GFX1132-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s10
+; GFX1132-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s2, v2
+; GFX1132-FAKE16-NEXT:  .LBB13_4: ; %Flow
+; GFX1132-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s9
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1132-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX1132-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1132-FAKE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1132-FAKE16-NEXT:    v_mad_u16 v0, s8, v4, s2
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1132-FAKE16-NEXT:    buffer_store_b8 v0, off, s[0:3], 0
+; GFX1132-FAKE16-NEXT:    s_endpgm
+;
+; GFX1264-TRUE16-LABEL: uniform_add_i8:
+; GFX1264-TRUE16:       ; %bb.0:
+; GFX1264-TRUE16-NEXT:    s_clause 0x1
+; GFX1264-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1264-TRUE16-NEXT:    s_load_b32 s10, s[4:5], 0x34
+; GFX1264-TRUE16-NEXT:    s_mov_b64 s[6:7], exec
+; GFX1264-TRUE16-NEXT:    s_mov_b64 s[8:9], exec
+; GFX1264-TRUE16-NEXT:    v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1264-TRUE16-NEXT:    v_mbcnt_hi_u32_b32 v4, s7, v0
+; GFX1264-TRUE16-NEXT:    ; implicit-def: $vgpr0_lo16
+; GFX1264-TRUE16-NEXT:    v_cmpx_eq_u32_e32 0, v4
+; GFX1264-TRUE16-NEXT:    s_cbranch_execz .LBB13_4
+; GFX1264-TRUE16-NEXT:  ; %bb.1:
+; GFX1264-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-TRUE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s5, s3
+; GFX1264-TRUE16-NEXT:    s_bcnt1_i32_b64 s6, s[6:7]
+; GFX1264-TRUE16-NEXT:    s_load_b32 s3, s[4:5], 0x0
+; GFX1264-TRUE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s7, s10
+; GFX1264-TRUE16-NEXT:    s_lshl_b32 s11, s2, 3
+; GFX1264-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1264-TRUE16-NEXT:    s_mul_i32 s7, s7, s6
+; GFX1264-TRUE16-NEXT:    s_lshl_b32 s12, 0xff, s11
+; GFX1264-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1264-TRUE16-NEXT:    s_and_b32 s2, s7, 0xff
+; GFX1264-TRUE16-NEXT:    s_not_b32 s13, s12
+; GFX1264-TRUE16-NEXT:    s_lshl_b32 s14, s2, s11
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s6, -1
+; GFX1264-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-TRUE16-NEXT:    v_mov_b32_e32 v1, s3
+; GFX1264-TRUE16-NEXT:    s_mov_b64 s[2:3], 0
+; GFX1264-TRUE16-NEXT:  .LBB13_2: ; %atomicrmw.start
+; GFX1264-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1264-TRUE16-NEXT:    v_add_nc_u32_e32 v0, s14, v1
+; GFX1264-TRUE16-NEXT:    v_and_b32_e32 v0, s12, v0
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1264-TRUE16-NEXT:    v_and_or_b32 v0, v1, s13, v0
+; GFX1264-TRUE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX1264-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX1264-TRUE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1264-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1264-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1264-TRUE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1264-TRUE16-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1264-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1264-TRUE16-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
+; GFX1264-TRUE16-NEXT:    s_cbranch_execnz .LBB13_2
+; GFX1264-TRUE16-NEXT:  ; %bb.3: ; %atomicrmw.end
+; GFX1264-TRUE16-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX1264-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s11, v2
+; GFX1264-TRUE16-NEXT:  .LBB13_4: ; %Flow
+; GFX1264-TRUE16-NEXT:    s_or_b64 exec, exec, s[8:9]
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1264-TRUE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX1264-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1264-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1264-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX1264-TRUE16-NEXT:    v_mad_u16 v0.l, s10, v4.l, s2
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1264-TRUE16-NEXT:    buffer_store_b8 v0, off, s[0:3], null
+; GFX1264-TRUE16-NEXT:    s_endpgm
+;
+; GFX1264-FAKE16-LABEL: uniform_add_i8:
+; GFX1264-FAKE16:       ; %bb.0:
+; GFX1264-FAKE16-NEXT:    s_clause 0x1
+; GFX1264-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1264-FAKE16-NEXT:    s_load_b32 s10, s[4:5], 0x34
+; GFX1264-FAKE16-NEXT:    s_mov_b64 s[6:7], exec
+; GFX1264-FAKE16-NEXT:    s_mov_b64 s[8:9], exec
+; GFX1264-FAKE16-NEXT:    v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1264-FAKE16-NEXT:    v_mbcnt_hi_u32_b32 v4, s7, v0
+; GFX1264-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; GFX1264-FAKE16-NEXT:    v_cmpx_eq_u32_e32 0, v4
+; GFX1264-FAKE16-NEXT:    s_cbranch_execz .LBB13_4
+; GFX1264-FAKE16-NEXT:  ; %bb.1:
+; GFX1264-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-FAKE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s5, s3
+; GFX1264-FAKE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1264-FAKE16-NEXT:    s_load_b32 s3, s[4:5], 0x0
+; GFX1264-FAKE16-NEXT:    s_bcnt1_i32_b64 s6, s[6:7]
+; GFX1264-FAKE16-NEXT:    s_lshl_b32 s11, s2, 3
+; GFX1264-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1264-FAKE16-NEXT:    s_mul_i32 s2, s10, s6
+; GFX1264-FAKE16-NEXT:    s_lshl_b32 s12, 0xff, s11
+; GFX1264-FAKE16-NEXT:    s_and_b32 s2, s2, 0xff
+; GFX1264-FAKE16-NEXT:    s_not_b32 s13, s12
+; GFX1264-FAKE16-NEXT:    s_lshl_b32 s14, s2, s11
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s6, -1
+; GFX1264-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-FAKE16-NEXT:    v_mov_b32_e32 v1, s3
+; GFX1264-FAKE16-NEXT:    s_mov_b64 s[2:3], 0
+; GFX1264-FAKE16-NEXT:  .LBB13_2: ; %atomicrmw.start
+; GFX1264-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1264-FAKE16-NEXT:    v_add_nc_u32_e32 v0, s14, v1
+; GFX1264-FAKE16-NEXT:    v_and_b32_e32 v0, s12, v0
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1264-FAKE16-NEXT:    v_and_or_b32 v0, v1, s13, v0
+; GFX1264-FAKE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX1264-FAKE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX1264-FAKE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1264-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1264-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1264-FAKE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1264-FAKE16-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1264-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1264-FAKE16-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
+; GFX1264-FAKE16-NEXT:    s_cbranch_execnz .LBB13_2
+; GFX1264-FAKE16-NEXT:  ; %bb.3: ; %atomicrmw.end
+; GFX1264-FAKE16-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX1264-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s11, v2
+; GFX1264-FAKE16-NEXT:  .LBB13_4: ; %Flow
+; GFX1264-FAKE16-NEXT:    s_or_b64 exec, exec, s[8:9]
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1264-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX1264-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1264-FAKE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1264-FAKE16-NEXT:    s_wait_alu 0xf1ff
+; GFX1264-FAKE16-NEXT:    v_mad_u16 v0, s10, v4, s2
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1264-FAKE16-NEXT:    buffer_store_b8 v0, off, s[0:3], null
+; GFX1264-FAKE16-NEXT:    s_endpgm
+;
+; GFX1232-TRUE16-LABEL: uniform_add_i8:
+; GFX1232-TRUE16:       ; %bb.0:
+; GFX1232-TRUE16-NEXT:    s_clause 0x1
+; GFX1232-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1232-TRUE16-NEXT:    s_load_b32 s8, s[4:5], 0x34
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s6, exec_lo
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s10, 0
+; GFX1232-TRUE16-NEXT:    v_mbcnt_lo_u32_b32 v4, s6, 0
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s9, exec_lo
+; GFX1232-TRUE16-NEXT:    ; implicit-def: $vgpr0_lo16
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1232-TRUE16-NEXT:    v_cmpx_eq_u32_e32 0, v4
+; GFX1232-TRUE16-NEXT:    s_cbranch_execz .LBB13_4
+; GFX1232-TRUE16-NEXT:  ; %bb.1:
+; GFX1232-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-TRUE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s5, s3
+; GFX1232-TRUE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1232-TRUE16-NEXT:    s_load_b32 s7, s[4:5], 0x0
+; GFX1232-TRUE16-NEXT:    s_bcnt1_i32_b32 s6, s6
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s11, s8
+; GFX1232-TRUE16-NEXT:    s_lshl_b32 s2, s2, 3
+; GFX1232-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1232-TRUE16-NEXT:    s_mul_i32 s6, s11, s6
+; GFX1232-TRUE16-NEXT:    s_lshl_b32 s3, 0xff, s2
+; GFX1232-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1232-TRUE16-NEXT:    s_and_b32 s6, s6, 0xff
+; GFX1232-TRUE16-NEXT:    s_not_b32 s11, s3
+; GFX1232-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1232-TRUE16-NEXT:    s_lshl_b32 s12, s6, s2
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s6, -1
+; GFX1232-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-TRUE16-NEXT:    v_mov_b32_e32 v1, s7
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1232-TRUE16-NEXT:  .LBB13_2: ; %atomicrmw.start
+; GFX1232-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1232-TRUE16-NEXT:    v_add_nc_u32_e32 v0, s12, v1
+; GFX1232-TRUE16-NEXT:    v_and_b32_e32 v0, s3, v0
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1232-TRUE16-NEXT:    v_and_or_b32 v0, v1, s11, v0
+; GFX1232-TRUE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1232-TRUE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1232-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1232-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1232-TRUE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1232-TRUE16-NEXT:    s_or_b32 s10, vcc_lo, s10
+; GFX1232-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1232-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s10
+; GFX1232-TRUE16-NEXT:    s_cbranch_execnz .LBB13_2
+; GFX1232-TRUE16-NEXT:  ; %bb.3: ; %atomicrmw.end
+; GFX1232-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s10
+; GFX1232-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s2, v2
+; GFX1232-TRUE16-NEXT:  .LBB13_4: ; %Flow
+; GFX1232-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s9
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1232-TRUE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX1232-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1232-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1232-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX1232-TRUE16-NEXT:    v_mad_u16 v0.l, s8, v4.l, s2
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1232-TRUE16-NEXT:    buffer_store_b8 v0, off, s[0:3], null
+; GFX1232-TRUE16-NEXT:    s_endpgm
+;
+; GFX1232-FAKE16-LABEL: uniform_add_i8:
+; GFX1232-FAKE16:       ; %bb.0:
+; GFX1232-FAKE16-NEXT:    s_clause 0x1
+; GFX1232-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1232-FAKE16-NEXT:    s_load_b32 s8, s[4:5], 0x34
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s6, exec_lo
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s10, 0
+; GFX1232-FAKE16-NEXT:    v_mbcnt_lo_u32_b32 v4, s6, 0
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s9, exec_lo
+; GFX1232-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1232-FAKE16-NEXT:    v_cmpx_eq_u32_e32 0, v4
+; GFX1232-FAKE16-NEXT:    s_cbranch_execz .LBB13_4
+; GFX1232-FAKE16-NEXT:  ; %bb.1:
+; GFX1232-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-FAKE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s5, s3
+; GFX1232-FAKE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1232-FAKE16-NEXT:    s_load_b32 s7, s[4:5], 0x0
+; GFX1232-FAKE16-NEXT:    s_bcnt1_i32_b32 s6, s6
+; GFX1232-FAKE16-NEXT:    s_lshl_b32 s2, s2, 3
+; GFX1232-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1232-FAKE16-NEXT:    s_mul_i32 s6, s8, s6
+; GFX1232-FAKE16-NEXT:    s_lshl_b32 s3, 0xff, s2
+; GFX1232-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1232-FAKE16-NEXT:    s_and_b32 s6, s6, 0xff
+; GFX1232-FAKE16-NEXT:    s_not_b32 s11, s3
+; GFX1232-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1232-FAKE16-NEXT:    s_lshl_b32 s12, s6, s2
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s6, -1
+; GFX1232-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-FAKE16-NEXT:    v_mov_b32_e32 v1, s7
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1232-FAKE16-NEXT:  .LBB13_2: ; %atomicrmw.start
+; GFX1232-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1232-FAKE16-NEXT:    v_add_nc_u32_e32 v0, s12, v1
+; GFX1232-FAKE16-NEXT:    v_and_b32_e32 v0, s3, v0
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1232-FAKE16-NEXT:    v_and_or_b32 v0, v1, s11, v0
+; GFX1232-FAKE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1232-FAKE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1232-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1232-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1232-FAKE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1232-FAKE16-NEXT:    s_or_b32 s10, vcc_lo, s10
+; GFX1232-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1232-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s10
+; GFX1232-FAKE16-NEXT:    s_cbranch_execnz .LBB13_2
+; GFX1232-FAKE16-NEXT:  ; %bb.3: ; %atomicrmw.end
+; GFX1232-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s10
+; GFX1232-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s2, v2
+; GFX1232-FAKE16-NEXT:  .LBB13_4: ; %Flow
+; GFX1232-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s9
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1232-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX1232-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1232-FAKE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1232-FAKE16-NEXT:    s_wait_alu 0xf1ff
+; GFX1232-FAKE16-NEXT:    v_mad_u16 v0, s8, v4, s2
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1232-FAKE16-NEXT:    buffer_store_b8 v0, off, s[0:3], null
+; GFX1232-FAKE16-NEXT:    s_endpgm
   %rmw = atomicrmw add ptr addrspace(1) %uniform.ptr, i8 %val monotonic, align 1
   store i8 %rmw, ptr addrspace(1) %result
   ret void
@@ -8563,163 +8995,325 @@ define amdgpu_kernel void @uniform_or_i16(ptr addrspace(1) %result, ptr addrspac
 ; GFX1032-NEXT:    buffer_store_short v0, off, s[0:3], 0
 ; GFX1032-NEXT:    s_endpgm
 ;
-; GFX1164-LABEL: uniform_or_i16:
-; GFX1164:       ; %bb.0:
-; GFX1164-NEXT:    s_clause 0x1
-; GFX1164-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1164-NEXT:    s_load_b32 s6, s[4:5], 0x34
-; GFX1164-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1164-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
-; GFX1164-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX1164-NEXT:    ; implicit-def: $vgpr0
-; GFX1164-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GFX1164-NEXT:    s_cbranch_execz .LBB15_2
-; GFX1164-NEXT:  ; %bb.1:
-; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_and_b32 s7, s2, 3
-; GFX1164-NEXT:    s_and_b32 s8, 0xffff, s6
-; GFX1164-NEXT:    s_lshl_b32 s7, s7, 3
-; GFX1164-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX1164-NEXT:    s_lshl_b32 s9, s8, s7
-; GFX1164-NEXT:    s_and_b32 s8, s2, -4
-; GFX1164-NEXT:    v_mov_b32_e32 v0, s9
-; GFX1164-NEXT:    s_mov_b32 s10, -1
-; GFX1164-NEXT:    s_mov_b32 s9, s3
-; GFX1164-NEXT:    buffer_atomic_or_b32 v0, off, s[8:11], 0 glc
-; GFX1164-NEXT:    s_waitcnt vmcnt(0)
-; GFX1164-NEXT:    v_lshrrev_b32_e32 v0, s7, v0
-; GFX1164-NEXT:  .LBB15_2:
-; GFX1164-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1164-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX1164-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX1164-NEXT:    v_cndmask_b32_e64 v0, s6, 0, vcc
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1164-NEXT:    v_or_b32_e32 v0, s2, v0
-; GFX1164-NEXT:    s_mov_b32 s2, -1
-; GFX1164-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
-; GFX1164-NEXT:    s_endpgm
-;
-; GFX1132-LABEL: uniform_or_i16:
-; GFX1132:       ; %bb.0:
-; GFX1132-NEXT:    s_clause 0x1
-; GFX1132-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1132-NEXT:    s_load_b32 s4, s[4:5], 0x34
-; GFX1132-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1132-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX1132-NEXT:    ; implicit-def: $vgpr0
-; GFX1132-NEXT:    s_and_saveexec_b32 s5, vcc_lo
-; GFX1132-NEXT:    s_cbranch_execz .LBB15_2
-; GFX1132-NEXT:  ; %bb.1:
-; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_and_b32 s6, s2, 3
-; GFX1132-NEXT:    s_and_b32 s7, 0xffff, s4
-; GFX1132-NEXT:    s_lshl_b32 s6, s6, 3
-; GFX1132-NEXT:    s_and_b32 s8, s2, -4
-; GFX1132-NEXT:    s_lshl_b32 s7, s7, s6
-; GFX1132-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX1132-NEXT:    v_mov_b32_e32 v0, s7
-; GFX1132-NEXT:    s_mov_b32 s10, -1
-; GFX1132-NEXT:    s_mov_b32 s9, s3
-; GFX1132-NEXT:    buffer_atomic_or_b32 v0, off, s[8:11], 0 glc
-; GFX1132-NEXT:    s_waitcnt vmcnt(0)
-; GFX1132-NEXT:    v_lshrrev_b32_e32 v0, s6, v0
-; GFX1132-NEXT:  .LBB15_2:
-; GFX1132-NEXT:    s_or_b32 exec_lo, exec_lo, s5
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1132-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX1132-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX1132-NEXT:    v_cndmask_b32_e64 v0, s4, 0, vcc_lo
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1132-NEXT:    v_or_b32_e32 v0, s2, v0
-; GFX1132-NEXT:    s_mov_b32 s2, -1
-; GFX1132-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
-; GFX1132-NEXT:    s_endpgm
-;
-; GFX1264-LABEL: uniform_or_i16:
-; GFX1264:       ; %bb.0:
-; GFX1264-NEXT:    s_clause 0x1
-; GFX1264-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1264-NEXT:    s_load_b32 s6, s[4:5], 0x34
-; GFX1264-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1264-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1264-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
-; GFX1264-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX1264-NEXT:    ; implicit-def: $vgpr0
-; GFX1264-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; GFX1264-NEXT:    s_cbranch_execz .LBB15_2
-; GFX1264-NEXT:  ; %bb.1:
-; GFX1264-NEXT:    s_wait_kmcnt 0x0
-; GFX1264-NEXT:    s_and_b32 s7, s2, 3
-; GFX1264-NEXT:    s_and_b32 s8, 0xffff, s6
-; GFX1264-NEXT:    s_lshl_b32 s7, s7, 3
-; GFX1264-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX1264-NEXT:    s_lshl_b32 s9, s8, s7
-; GFX1264-NEXT:    s_and_b32 s8, s2, -4
-; GFX1264-NEXT:    v_mov_b32_e32 v0, s9
-; GFX1264-NEXT:    s_mov_b32 s10, -1
-; GFX1264-NEXT:    s_mov_b32 s9, s3
-; GFX1264-NEXT:    buffer_atomic_or_b32 v0, off, s[8:11], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
-; GFX1264-NEXT:    s_wait_loadcnt 0x0
-; GFX1264-NEXT:    v_lshrrev_b32_e32 v0, s7, v0
-; GFX1264-NEXT:  .LBB15_2:
-; GFX1264-NEXT:    s_or_b64 exec, exec, s[4:5]
-; GFX1264-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1264-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX1264-NEXT:    s_wait_kmcnt 0x0
-; GFX1264-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX1264-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX1264-NEXT:    v_cndmask_b32_e64 v0, s6, 0, vcc
-; GFX1264-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1264-NEXT:    v_or_b32_e32 v0, s2, v0
-; GFX1264-NEXT:    s_mov_b32 s2, -1
-; GFX1264-NEXT:    buffer_store_b16 v0, off, s[0:3], null
-; GFX1264-NEXT:    s_endpgm
-;
-; GFX1232-LABEL: uniform_or_i16:
-; GFX1232:       ; %bb.0:
-; GFX1232-NEXT:    s_clause 0x1
-; GFX1232-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1232-NEXT:    s_load_b32 s4, s[4:5], 0x34
-; GFX1232-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
-; GFX1232-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1232-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX1232-NEXT:    ; implicit-def: $vgpr0
-; GFX1232-NEXT:    s_and_saveexec_b32 s5, vcc_lo
-; GFX1232-NEXT:    s_cbranch_execz .LBB15_2
-; GFX1232-NEXT:  ; %bb.1:
-; GFX1232-NEXT:    s_wait_kmcnt 0x0
-; GFX1232-NEXT:    s_and_b32 s6, s2, 3
-; GFX1232-NEXT:    s_and_b32 s7, 0xffff, s4
-; GFX1232-NEXT:    s_lshl_b32 s6, s6, 3
-; GFX1232-NEXT:    s_and_b32 s8, s2, -4
-; GFX1232-NEXT:    s_lshl_b32 s7, s7, s6
-; GFX1232-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX1232-NEXT:    v_mov_b32_e32 v0, s7
-; GFX1232-NEXT:    s_mov_b32 s10, -1
-; GFX1232-NEXT:    s_mov_b32 s9, s3
-; GFX1232-NEXT:    buffer_atomic_or_b32 v0, off, s[8:11], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
-; GFX1232-NEXT:    s_wait_loadcnt 0x0
-; GFX1232-NEXT:    v_lshrrev_b32_e32 v0, s6, v0
-; GFX1232-NEXT:  .LBB15_2:
-; GFX1232-NEXT:    s_or_b32 exec_lo, exec_lo, s5
-; GFX1232-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1232-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX1232-NEXT:    s_wait_kmcnt 0x0
-; GFX1232-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX1232-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX1232-NEXT:    v_cndmask_b32_e64 v0, s4, 0, vcc_lo
-; GFX1232-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1232-NEXT:    v_or_b32_e32 v0, s2, v0
-; GFX1232-NEXT:    s_mov_b32 s2, -1
-; GFX1232-NEXT:    buffer_store_b16 v0, off, s[0:3], null
-; GFX1232-NEXT:    s_endpgm
+; GFX1164-TRUE16-LABEL: uniform_or_i16:
+; GFX1164-TRUE16:       ; %bb.0:
+; GFX1164-TRUE16-NEXT:    s_clause 0x1
+; GFX1164-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1164-TRUE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; GFX1164-TRUE16-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164-TRUE16-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1164-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1164-TRUE16-NEXT:    ; implicit-def: $vgpr0_lo16
+; GFX1164-TRUE16-NEXT:    s_and_saveexec_b64 s[4:5], vcc
+; GFX1164-TRUE16-NEXT:    s_cbranch_execz .LBB15_2
+; GFX1164-TRUE16-NEXT:  ; %bb.1:
+; GFX1164-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-TRUE16-NEXT:    s_and_b32 s7, s2, 3
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s8, s6
+; GFX1164-TRUE16-NEXT:    s_lshl_b32 s7, s7, 3
+; GFX1164-TRUE16-NEXT:    s_and_b32 s8, 0xffff, s8
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX1164-TRUE16-NEXT:    s_lshl_b32 s9, s8, s7
+; GFX1164-TRUE16-NEXT:    s_and_b32 s8, s2, -4
+; GFX1164-TRUE16-NEXT:    v_mov_b32_e32 v0, s9
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s9, s3
+; GFX1164-TRUE16-NEXT:    buffer_atomic_or_b32 v0, off, s[8:11], 0 glc
+; GFX1164-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1164-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s7, v0
+; GFX1164-TRUE16-NEXT:  .LBB15_2:
+; GFX1164-TRUE16-NEXT:    s_or_b64 exec, exec, s[4:5]
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1164-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1164-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1164-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1164-TRUE16-NEXT:    v_cndmask_b16 v0.l, s6, 0, vcc
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1164-TRUE16-NEXT:    v_or_b16 v0.l, s2, v0.l
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1164-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX1164-TRUE16-NEXT:    s_endpgm
+;
+; GFX1164-FAKE16-LABEL: uniform_or_i16:
+; GFX1164-FAKE16:       ; %bb.0:
+; GFX1164-FAKE16-NEXT:    s_clause 0x1
+; GFX1164-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1164-FAKE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; GFX1164-FAKE16-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164-FAKE16-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1164-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1164-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; GFX1164-FAKE16-NEXT:    s_and_saveexec_b64 s[4:5], vcc
+; GFX1164-FAKE16-NEXT:    s_cbranch_execz .LBB15_2
+; GFX1164-FAKE16-NEXT:  ; %bb.1:
+; GFX1164-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-FAKE16-NEXT:    s_and_b32 s7, s2, 3
+; GFX1164-FAKE16-NEXT:    s_and_b32 s8, 0xffff, s6
+; GFX1164-FAKE16-NEXT:    s_lshl_b32 s7, s7, 3
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX1164-FAKE16-NEXT:    s_lshl_b32 s9, s8, s7
+; GFX1164-FAKE16-NEXT:    s_and_b32 s8, s2, -4
+; GFX1164-FAKE16-NEXT:    v_mov_b32_e32 v0, s9
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s9, s3
+; GFX1164-FAKE16-NEXT:    buffer_atomic_or_b32 v0, off, s[8:11], 0 glc
+; GFX1164-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1164-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s7, v0
+; GFX1164-FAKE16-NEXT:  .LBB15_2:
+; GFX1164-FAKE16-NEXT:    s_or_b64 exec, exec, s[4:5]
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1164-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1164-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1164-FAKE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1164-FAKE16-NEXT:    v_cndmask_b32_e64 v0, s6, 0, vcc
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1164-FAKE16-NEXT:    v_or_b32_e32 v0, s2, v0
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1164-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX1164-FAKE16-NEXT:    s_endpgm
+;
+; GFX1132-TRUE16-LABEL: uniform_or_i16:
+; GFX1132-TRUE16:       ; %bb.0:
+; GFX1132-TRUE16-NEXT:    s_clause 0x1
+; GFX1132-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1132-TRUE16-NEXT:    s_load_b32 s4, s[4:5], 0x34
+; GFX1132-TRUE16-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1132-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1132-TRUE16-NEXT:    ; implicit-def: $vgpr0_lo16
+; GFX1132-TRUE16-NEXT:    s_and_saveexec_b32 s5, vcc_lo
+; GFX1132-TRUE16-NEXT:    s_cbranch_execz .LBB15_2
+; GFX1132-TRUE16-NEXT:  ; %bb.1:
+; GFX1132-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-TRUE16-NEXT:    s_and_b32 s6, s2, 3
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s7, s4
+; GFX1132-TRUE16-NEXT:    s_lshl_b32 s6, s6, 3
+; GFX1132-TRUE16-NEXT:    s_and_b32 s7, 0xffff, s7
+; GFX1132-TRUE16-NEXT:    s_and_b32 s8, s2, -4
+; GFX1132-TRUE16-NEXT:    s_lshl_b32 s7, s7, s6
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX1132-TRUE16-NEXT:    v_mov_b32_e32 v0, s7
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s9, s3
+; GFX1132-TRUE16-NEXT:    buffer_atomic_or_b32 v0, off, s[8:11], 0 glc
+; GFX1132-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1132-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s6, v0
+; GFX1132-TRUE16-NEXT:  .LBB15_2:
+; GFX1132-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s5
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1132-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1132-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1132-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1132-TRUE16-NEXT:    v_cndmask_b16 v0.l, s4, 0, vcc_lo
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1132-TRUE16-NEXT:    v_or_b16 v0.l, s2, v0.l
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1132-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX1132-TRUE16-NEXT:    s_endpgm
+;
+; GFX1132-FAKE16-LABEL: uniform_or_i16:
+; GFX1132-FAKE16:       ; %bb.0:
+; GFX1132-FAKE16-NEXT:    s_clause 0x1
+; GFX1132-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1132-FAKE16-NEXT:    s_load_b32 s4, s[4:5], 0x34
+; GFX1132-FAKE16-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1132-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1132-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; GFX1132-FAKE16-NEXT:    s_and_saveexec_b32 s5, vcc_lo
+; GFX1132-FAKE16-NEXT:    s_cbranch_execz .LBB15_2
+; GFX1132-FAKE16-NEXT:  ; %bb.1:
+; GFX1132-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-FAKE16-NEXT:    s_and_b32 s6, s2, 3
+; GFX1132-FAKE16-NEXT:    s_and_b32 s7, 0xffff, s4
+; GFX1132-FAKE16-NEXT:    s_lshl_b32 s6, s6, 3
+; GFX1132-FAKE16-NEXT:    s_and_b32 s8, s2, -4
+; GFX1132-FAKE16-NEXT:    s_lshl_b32 s7, s7, s6
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX1132-FAKE16-NEXT:    v_mov_b32_e32 v0, s7
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s9, s3
+; GFX1132-FAKE16-NEXT:    buffer_atomic_or_b32 v0, off, s[8:11], 0 glc
+; GFX1132-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1132-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s6, v0
+; GFX1132-FAKE16-NEXT:  .LBB15_2:
+; GFX1132-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s5
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1132-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1132-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1132-FAKE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1132-FAKE16-NEXT:    v_cndmask_b32_e64 v0, s4, 0, vcc_lo
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1132-FAKE16-NEXT:    v_or_b32_e32 v0, s2, v0
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1132-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX1132-FAKE16-NEXT:    s_endpgm
+;
+; GFX1264-TRUE16-LABEL: uniform_or_i16:
+; GFX1264-TRUE16:       ; %bb.0:
+; GFX1264-TRUE16-NEXT:    s_clause 0x1
+; GFX1264-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1264-TRUE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; GFX1264-TRUE16-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1264-TRUE16-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1264-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1264-TRUE16-NEXT:    ; implicit-def: $vgpr0_lo16
+; GFX1264-TRUE16-NEXT:    s_and_saveexec_b64 s[4:5], vcc
+; GFX1264-TRUE16-NEXT:    s_cbranch_execz .LBB15_2
+; GFX1264-TRUE16-NEXT:  ; %bb.1:
+; GFX1264-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-TRUE16-NEXT:    s_and_b32 s7, s2, 3
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s8, s6
+; GFX1264-TRUE16-NEXT:    s_lshl_b32 s7, s7, 3
+; GFX1264-TRUE16-NEXT:    s_and_b32 s8, 0xffff, s8
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX1264-TRUE16-NEXT:    s_lshl_b32 s9, s8, s7
+; GFX1264-TRUE16-NEXT:    s_and_b32 s8, s2, -4
+; GFX1264-TRUE16-NEXT:    v_mov_b32_e32 v0, s9
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s9, s3
+; GFX1264-TRUE16-NEXT:    buffer_atomic_or_b32 v0, off, s[8:11], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1264-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1264-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s7, v0
+; GFX1264-TRUE16-NEXT:  .LBB15_2:
+; GFX1264-TRUE16-NEXT:    s_or_b64 exec, exec, s[4:5]
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1264-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1264-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1264-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1264-TRUE16-NEXT:    v_cndmask_b16 v0.l, s6, 0, vcc
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1264-TRUE16-NEXT:    v_or_b16 v0.l, s2, v0.l
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1264-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], null
+; GFX1264-TRUE16-NEXT:    s_endpgm
+;
+; GFX1264-FAKE16-LABEL: uniform_or_i16:
+; GFX1264-FAKE16:       ; %bb.0:
+; GFX1264-FAKE16-NEXT:    s_clause 0x1
+; GFX1264-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1264-FAKE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; GFX1264-FAKE16-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1264-FAKE16-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1264-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1264-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; GFX1264-FAKE16-NEXT:    s_and_saveexec_b64 s[4:5], vcc
+; GFX1264-FAKE16-NEXT:    s_cbranch_execz .LBB15_2
+; GFX1264-FAKE16-NEXT:  ; %bb.1:
+; GFX1264-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-FAKE16-NEXT:    s_and_b32 s7, s2, 3
+; GFX1264-FAKE16-NEXT:    s_and_b32 s8, 0xffff, s6
+; GFX1264-FAKE16-NEXT:    s_lshl_b32 s7, s7, 3
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX1264-FAKE16-NEXT:    s_lshl_b32 s9, s8, s7
+; GFX1264-FAKE16-NEXT:    s_and_b32 s8, s2, -4
+; GFX1264-FAKE16-NEXT:    v_mov_b32_e32 v0, s9
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s9, s3
+; GFX1264-FAKE16-NEXT:    buffer_atomic_or_b32 v0, off, s[8:11], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1264-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1264-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s7, v0
+; GFX1264-FAKE16-NEXT:  .LBB15_2:
+; GFX1264-FAKE16-NEXT:    s_or_b64 exec, exec, s[4:5]
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1264-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1264-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1264-FAKE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1264-FAKE16-NEXT:    v_cndmask_b32_e64 v0, s6, 0, vcc
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1264-FAKE16-NEXT:    v_or_b32_e32 v0, s2, v0
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1264-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], null
+; GFX1264-FAKE16-NEXT:    s_endpgm
+;
+; GFX1232-TRUE16-LABEL: uniform_or_i16:
+; GFX1232-TRUE16:       ; %bb.0:
+; GFX1232-TRUE16-NEXT:    s_clause 0x1
+; GFX1232-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1232-TRUE16-NEXT:    s_load_b32 s4, s[4:5], 0x34
+; GFX1232-TRUE16-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1232-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1232-TRUE16-NEXT:    ; implicit-def: $vgpr0_lo16
+; GFX1232-TRUE16-NEXT:    s_and_saveexec_b32 s5, vcc_lo
+; GFX1232-TRUE16-NEXT:    s_cbranch_execz .LBB15_2
+; GFX1232-TRUE16-NEXT:  ; %bb.1:
+; GFX1232-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-TRUE16-NEXT:    s_and_b32 s6, s2, 3
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s7, s4
+; GFX1232-TRUE16-NEXT:    s_lshl_b32 s6, s6, 3
+; GFX1232-TRUE16-NEXT:    s_and_b32 s7, 0xffff, s7
+; GFX1232-TRUE16-NEXT:    s_and_b32 s8, s2, -4
+; GFX1232-TRUE16-NEXT:    s_lshl_b32 s7, s7, s6
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX1232-TRUE16-NEXT:    v_mov_b32_e32 v0, s7
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s9, s3
+; GFX1232-TRUE16-NEXT:    buffer_atomic_or_b32 v0, off, s[8:11], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1232-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1232-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s6, v0
+; GFX1232-TRUE16-NEXT:  .LBB15_2:
+; GFX1232-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s5
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1232-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1232-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1232-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1232-TRUE16-NEXT:    v_cndmask_b16 v0.l, s4, 0, vcc_lo
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1232-TRUE16-NEXT:    v_or_b16 v0.l, s2, v0.l
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1232-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], null
+; GFX1232-TRUE16-NEXT:    s_endpgm
+;
+; GFX1232-FAKE16-LABEL: uniform_or_i16:
+; GFX1232-FAKE16:       ; %bb.0:
+; GFX1232-FAKE16-NEXT:    s_clause 0x1
+; GFX1232-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1232-FAKE16-NEXT:    s_load_b32 s4, s[4:5], 0x34
+; GFX1232-FAKE16-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1232-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1232-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; GFX1232-FAKE16-NEXT:    s_and_saveexec_b32 s5, vcc_lo
+; GFX1232-FAKE16-NEXT:    s_cbranch_execz .LBB15_2
+; GFX1232-FAKE16-NEXT:  ; %bb.1:
+; GFX1232-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-FAKE16-NEXT:    s_and_b32 s6, s2, 3
+; GFX1232-FAKE16-NEXT:    s_and_b32 s7, 0xffff, s4
+; GFX1232-FAKE16-NEXT:    s_lshl_b32 s6, s6, 3
+; GFX1232-FAKE16-NEXT:    s_and_b32 s8, s2, -4
+; GFX1232-FAKE16-NEXT:    s_lshl_b32 s7, s7, s6
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX1232-FAKE16-NEXT:    v_mov_b32_e32 v0, s7
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s9, s3
+; GFX1232-FAKE16-NEXT:    buffer_atomic_or_b32 v0, off, s[8:11], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1232-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1232-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s6, v0
+; GFX1232-FAKE16-NEXT:  .LBB15_2:
+; GFX1232-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s5
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1232-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1232-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1232-FAKE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1232-FAKE16-NEXT:    v_cndmask_b32_e64 v0, s4, 0, vcc_lo
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1232-FAKE16-NEXT:    v_or_b32_e32 v0, s2, v0
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1232-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], null
+; GFX1232-FAKE16-NEXT:    s_endpgm
   %rmw = atomicrmw or ptr addrspace(1) %uniform.ptr, i16 %val monotonic, align 2
   store i16 %rmw, ptr addrspace(1) %result
   ret void
@@ -9019,262 +9613,524 @@ define amdgpu_kernel void @uniform_add_i16(ptr addrspace(1) %result, ptr addrspa
 ; GFX1032-NEXT:    buffer_store_short v0, off, s[0:3], 0
 ; GFX1032-NEXT:    s_endpgm
 ;
-; GFX1164-LABEL: uniform_add_i16:
-; GFX1164:       ; %bb.0:
-; GFX1164-NEXT:    s_clause 0x1
-; GFX1164-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1164-NEXT:    s_load_b32 s10, s[4:5], 0x34
-; GFX1164-NEXT:    s_mov_b64 s[6:7], exec
-; GFX1164-NEXT:    s_mov_b64 s[8:9], exec
-; GFX1164-NEXT:    v_mbcnt_lo_u32_b32 v0, s6, 0
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1164-NEXT:    v_mbcnt_hi_u32_b32 v4, s7, v0
-; GFX1164-NEXT:    ; implicit-def: $vgpr0
-; GFX1164-NEXT:    v_cmpx_eq_u32_e32 0, v4
-; GFX1164-NEXT:    s_cbranch_execz .LBB16_4
-; GFX1164-NEXT:  ; %bb.1:
-; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_and_b32 s4, s2, -4
-; GFX1164-NEXT:    s_mov_b32 s5, s3
-; GFX1164-NEXT:    s_and_b32 s2, s2, 3
-; GFX1164-NEXT:    s_load_b32 s3, s[4:5], 0x0
-; GFX1164-NEXT:    s_bcnt1_i32_b64 s6, s[6:7]
-; GFX1164-NEXT:    s_lshl_b32 s11, s2, 3
-; GFX1164-NEXT:    s_mul_i32 s2, s10, s6
-; GFX1164-NEXT:    s_lshl_b32 s12, 0xffff, s11
-; GFX1164-NEXT:    s_and_b32 s2, s2, 0xffff
-; GFX1164-NEXT:    s_not_b32 s13, s12
-; GFX1164-NEXT:    s_lshl_b32 s14, s2, s11
-; GFX1164-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1164-NEXT:    s_mov_b32 s6, -1
-; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    v_mov_b32_e32 v1, s3
-; GFX1164-NEXT:    s_mov_b64 s[2:3], 0
-; GFX1164-NEXT:  .LBB16_2: ; %atomicrmw.start
-; GFX1164-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1164-NEXT:    v_add_nc_u32_e32 v0, s14, v1
-; GFX1164-NEXT:    v_and_b32_e32 v0, s12, v0
-; GFX1164-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1164-NEXT:    v_and_or_b32 v0, v1, s13, v0
-; GFX1164-NEXT:    v_mov_b32_e32 v3, v1
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX1164-NEXT:    v_mov_b32_e32 v2, v0
-; GFX1164-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
-; GFX1164-NEXT:    s_waitcnt vmcnt(0)
-; GFX1164-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
-; GFX1164-NEXT:    v_mov_b32_e32 v1, v2
-; GFX1164-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
-; GFX1164-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
-; GFX1164-NEXT:    s_cbranch_execnz .LBB16_2
-; GFX1164-NEXT:  ; %bb.3: ; %atomicrmw.end
-; GFX1164-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX1164-NEXT:    v_lshrrev_b32_e32 v0, s11, v2
-; GFX1164-NEXT:  .LBB16_4: ; %Flow
-; GFX1164-NEXT:    s_or_b64 exec, exec, s[8:9]
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1164-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX1164-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1164-NEXT:    v_mad_u16 v0, s10, v4, s2
-; GFX1164-NEXT:    s_mov_b32 s2, -1
-; GFX1164-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
-; GFX1164-NEXT:    s_endpgm
-;
-; GFX1132-LABEL: uniform_add_i16:
-; GFX1132:       ; %bb.0:
-; GFX1132-NEXT:    s_clause 0x1
-; GFX1132-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1132-NEXT:    s_load_b32 s8, s[4:5], 0x34
-; GFX1132-NEXT:    s_mov_b32 s6, exec_lo
-; GFX1132-NEXT:    s_mov_b32 s10, 0
-; GFX1132-NEXT:    v_mbcnt_lo_u32_b32 v4, s6, 0
-; GFX1132-NEXT:    s_mov_b32 s9, exec_lo
-; GFX1132-NEXT:    ; implicit-def: $vgpr0
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1132-NEXT:    v_cmpx_eq_u32_e32 0, v4
-; GFX1132-NEXT:    s_cbranch_execz .LBB16_4
-; GFX1132-NEXT:  ; %bb.1:
-; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_and_b32 s4, s2, -4
-; GFX1132-NEXT:    s_mov_b32 s5, s3
-; GFX1132-NEXT:    s_and_b32 s2, s2, 3
-; GFX1132-NEXT:    s_load_b32 s7, s[4:5], 0x0
-; GFX1132-NEXT:    s_bcnt1_i32_b32 s6, s6
-; GFX1132-NEXT:    s_lshl_b32 s2, s2, 3
-; GFX1132-NEXT:    s_mul_i32 s6, s8, s6
-; GFX1132-NEXT:    s_lshl_b32 s3, 0xffff, s2
-; GFX1132-NEXT:    s_and_b32 s6, s6, 0xffff
-; GFX1132-NEXT:    s_not_b32 s11, s3
-; GFX1132-NEXT:    s_lshl_b32 s12, s6, s2
-; GFX1132-NEXT:    s_mov_b32 s6, -1
-; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    v_mov_b32_e32 v1, s7
-; GFX1132-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1132-NEXT:  .LBB16_2: ; %atomicrmw.start
-; GFX1132-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1132-NEXT:    v_add_nc_u32_e32 v0, s12, v1
-; GFX1132-NEXT:    v_and_b32_e32 v0, s3, v0
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1132-NEXT:    v_and_or_b32 v0, v1, s11, v0
-; GFX1132-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
-; GFX1132-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
-; GFX1132-NEXT:    s_waitcnt vmcnt(0)
-; GFX1132-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
-; GFX1132-NEXT:    v_mov_b32_e32 v1, v2
-; GFX1132-NEXT:    s_or_b32 s10, vcc_lo, s10
-; GFX1132-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s10
-; GFX1132-NEXT:    s_cbranch_execnz .LBB16_2
-; GFX1132-NEXT:  ; %bb.3: ; %atomicrmw.end
-; GFX1132-NEXT:    s_or_b32 exec_lo, exec_lo, s10
-; GFX1132-NEXT:    v_lshrrev_b32_e32 v0, s2, v2
-; GFX1132-NEXT:  .LBB16_4: ; %Flow
-; GFX1132-NEXT:    s_or_b32 exec_lo, exec_lo, s9
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1132-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX1132-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1132-NEXT:    v_mad_u16 v0, s8, v4, s2
-; GFX1132-NEXT:    s_mov_b32 s2, -1
-; GFX1132-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
-; GFX1132-NEXT:    s_endpgm
-;
-; GFX1264-LABEL: uniform_add_i16:
-; GFX1264:       ; %bb.0:
-; GFX1264-NEXT:    s_clause 0x1
-; GFX1264-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1264-NEXT:    s_load_b32 s10, s[4:5], 0x34
-; GFX1264-NEXT:    s_mov_b64 s[6:7], exec
-; GFX1264-NEXT:    s_mov_b64 s[8:9], exec
-; GFX1264-NEXT:    v_mbcnt_lo_u32_b32 v0, s6, 0
-; GFX1264-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1264-NEXT:    v_mbcnt_hi_u32_b32 v4, s7, v0
-; GFX1264-NEXT:    ; implicit-def: $vgpr0
-; GFX1264-NEXT:    v_cmpx_eq_u32_e32 0, v4
-; GFX1264-NEXT:    s_cbranch_execz .LBB16_4
-; GFX1264-NEXT:  ; %bb.1:
-; GFX1264-NEXT:    s_wait_kmcnt 0x0
-; GFX1264-NEXT:    s_and_b32 s4, s2, -4
-; GFX1264-NEXT:    s_mov_b32 s5, s3
-; GFX1264-NEXT:    s_and_b32 s2, s2, 3
-; GFX1264-NEXT:    s_load_b32 s3, s[4:5], 0x0
-; GFX1264-NEXT:    s_bcnt1_i32_b64 s6, s[6:7]
-; GFX1264-NEXT:    s_lshl_b32 s11, s2, 3
-; GFX1264-NEXT:    s_wait_alu 0xfffe
-; GFX1264-NEXT:    s_mul_i32 s2, s10, s6
-; GFX1264-NEXT:    s_lshl_b32 s12, 0xffff, s11
-; GFX1264-NEXT:    s_and_b32 s2, s2, 0xffff
-; GFX1264-NEXT:    s_not_b32 s13, s12
-; GFX1264-NEXT:    s_lshl_b32 s14, s2, s11
-; GFX1264-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1264-NEXT:    s_mov_b32 s6, -1
-; GFX1264-NEXT:    s_wait_kmcnt 0x0
-; GFX1264-NEXT:    v_mov_b32_e32 v1, s3
-; GFX1264-NEXT:    s_mov_b64 s[2:3], 0
-; GFX1264-NEXT:  .LBB16_2: ; %atomicrmw.start
-; GFX1264-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX1264-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1264-NEXT:    v_add_nc_u32_e32 v0, s14, v1
-; GFX1264-NEXT:    v_and_b32_e32 v0, s12, v0
-; GFX1264-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1264-NEXT:    v_and_or_b32 v0, v1, s13, v0
-; GFX1264-NEXT:    v_mov_b32_e32 v3, v1
-; GFX1264-NEXT:    v_mov_b32_e32 v2, v0
-; GFX1264-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
-; GFX1264-NEXT:    s_wait_loadcnt 0x0
-; GFX1264-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
-; GFX1264-NEXT:    v_mov_b32_e32 v1, v2
-; GFX1264-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
-; GFX1264-NEXT:    s_wait_alu 0xfffe
-; GFX1264-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
-; GFX1264-NEXT:    s_cbranch_execnz .LBB16_2
-; GFX1264-NEXT:  ; %bb.3: ; %atomicrmw.end
-; GFX1264-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX1264-NEXT:    v_lshrrev_b32_e32 v0, s11, v2
-; GFX1264-NEXT:  .LBB16_4: ; %Flow
-; GFX1264-NEXT:    s_or_b64 exec, exec, s[8:9]
-; GFX1264-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1264-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX1264-NEXT:    s_wait_kmcnt 0x0
-; GFX1264-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX1264-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX1264-NEXT:    s_wait_alu 0xf1ff
-; GFX1264-NEXT:    v_mad_u16 v0, s10, v4, s2
-; GFX1264-NEXT:    s_mov_b32 s2, -1
-; GFX1264-NEXT:    buffer_store_b16 v0, off, s[0:3], null
-; GFX1264-NEXT:    s_endpgm
-;
-; GFX1232-LABEL: uniform_add_i16:
-; GFX1232:       ; %bb.0:
-; GFX1232-NEXT:    s_clause 0x1
-; GFX1232-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1232-NEXT:    s_load_b32 s8, s[4:5], 0x34
-; GFX1232-NEXT:    s_mov_b32 s6, exec_lo
-; GFX1232-NEXT:    s_mov_b32 s10, 0
-; GFX1232-NEXT:    v_mbcnt_lo_u32_b32 v4, s6, 0
-; GFX1232-NEXT:    s_mov_b32 s9, exec_lo
-; GFX1232-NEXT:    ; implicit-def: $vgpr0
-; GFX1232-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1232-NEXT:    v_cmpx_eq_u32_e32 0, v4
-; GFX1232-NEXT:    s_cbranch_execz .LBB16_4
-; GFX1232-NEXT:  ; %bb.1:
-; GFX1232-NEXT:    s_wait_kmcnt 0x0
-; GFX1232-NEXT:    s_and_b32 s4, s2, -4
-; GFX1232-NEXT:    s_mov_b32 s5, s3
-; GFX1232-NEXT:    s_and_b32 s2, s2, 3
-; GFX1232-NEXT:    s_load_b32 s7, s[4:5], 0x0
-; GFX1232-NEXT:    s_bcnt1_i32_b32 s6, s6
-; GFX1232-NEXT:    s_lshl_b32 s2, s2, 3
-; GFX1232-NEXT:    s_wait_alu 0xfffe
-; GFX1232-NEXT:    s_mul_i32 s6, s8, s6
-; GFX1232-NEXT:    s_lshl_b32 s3, 0xffff, s2
-; GFX1232-NEXT:    s_wait_alu 0xfffe
-; GFX1232-NEXT:    s_and_b32 s6, s6, 0xffff
-; GFX1232-NEXT:    s_not_b32 s11, s3
-; GFX1232-NEXT:    s_wait_alu 0xfffe
-; GFX1232-NEXT:    s_lshl_b32 s12, s6, s2
-; GFX1232-NEXT:    s_mov_b32 s6, -1
-; GFX1232-NEXT:    s_wait_kmcnt 0x0
-; GFX1232-NEXT:    v_mov_b32_e32 v1, s7
-; GFX1232-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1232-NEXT:  .LBB16_2: ; %atomicrmw.start
-; GFX1232-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX1232-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1232-NEXT:    v_add_nc_u32_e32 v0, s12, v1
-; GFX1232-NEXT:    v_and_b32_e32 v0, s3, v0
-; GFX1232-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1232-NEXT:    v_and_or_b32 v0, v1, s11, v0
-; GFX1232-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
-; GFX1232-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
-; GFX1232-NEXT:    s_wait_loadcnt 0x0
-; GFX1232-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
-; GFX1232-NEXT:    v_mov_b32_e32 v1, v2
-; GFX1232-NEXT:    s_or_b32 s10, vcc_lo, s10
-; GFX1232-NEXT:    s_wait_alu 0xfffe
-; GFX1232-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s10
-; GFX1232-NEXT:    s_cbranch_execnz .LBB16_2
-; GFX1232-NEXT:  ; %bb.3: ; %atomicrmw.end
-; GFX1232-NEXT:    s_or_b32 exec_lo, exec_lo, s10
-; GFX1232-NEXT:    v_lshrrev_b32_e32 v0, s2, v2
-; GFX1232-NEXT:  .LBB16_4: ; %Flow
-; GFX1232-NEXT:    s_or_b32 exec_lo, exec_lo, s9
-; GFX1232-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1232-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX1232-NEXT:    s_wait_kmcnt 0x0
-; GFX1232-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX1232-NEXT:    v_readfirstlane_b32 s2, v0
-; GFX1232-NEXT:    s_wait_alu 0xf1ff
-; GFX1232-NEXT:    v_mad_u16 v0, s8, v4, s2
-; GFX1232-NEXT:    s_mov_b32 s2, -1
-; GFX1232-NEXT:    buffer_store_b16 v0, off, s[0:3], null
-; GFX1232-NEXT:    s_endpgm
+; GFX1164-TRUE16-LABEL: uniform_add_i16:
+; GFX1164-TRUE16:       ; %bb.0:
+; GFX1164-TRUE16-NEXT:    s_clause 0x1
+; GFX1164-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1164-TRUE16-NEXT:    s_load_b32 s10, s[4:5], 0x34
+; GFX1164-TRUE16-NEXT:    s_mov_b64 s[6:7], exec
+; GFX1164-TRUE16-NEXT:    s_mov_b64 s[8:9], exec
+; GFX1164-TRUE16-NEXT:    v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164-TRUE16-NEXT:    v_mbcnt_hi_u32_b32 v4, s7, v0
+; GFX1164-TRUE16-NEXT:    ; implicit-def: $vgpr0_lo16
+; GFX1164-TRUE16-NEXT:    v_cmpx_eq_u32_e32 0, v4
+; GFX1164-TRUE16-NEXT:    s_cbranch_execz .LBB16_4
+; GFX1164-TRUE16-NEXT:  ; %bb.1:
+; GFX1164-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-TRUE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s5, s3
+; GFX1164-TRUE16-NEXT:    s_bcnt1_i32_b64 s6, s[6:7]
+; GFX1164-TRUE16-NEXT:    s_load_b32 s3, s[4:5], 0x0
+; GFX1164-TRUE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s7, s10
+; GFX1164-TRUE16-NEXT:    s_lshl_b32 s11, s2, 3
+; GFX1164-TRUE16-NEXT:    s_mul_i32 s7, s7, s6
+; GFX1164-TRUE16-NEXT:    s_lshl_b32 s12, 0xffff, s11
+; GFX1164-TRUE16-NEXT:    s_and_b32 s2, s7, 0xffff
+; GFX1164-TRUE16-NEXT:    s_not_b32 s13, s12
+; GFX1164-TRUE16-NEXT:    s_lshl_b32 s14, s2, s11
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s6, -1
+; GFX1164-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-TRUE16-NEXT:    v_mov_b32_e32 v1, s3
+; GFX1164-TRUE16-NEXT:    s_mov_b64 s[2:3], 0
+; GFX1164-TRUE16-NEXT:  .LBB16_2: ; %atomicrmw.start
+; GFX1164-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164-TRUE16-NEXT:    v_add_nc_u32_e32 v0, s14, v1
+; GFX1164-TRUE16-NEXT:    v_and_b32_e32 v0, s12, v0
+; GFX1164-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1164-TRUE16-NEXT:    v_and_or_b32 v0, v1, s13, v0
+; GFX1164-TRUE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1164-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX1164-TRUE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
+; GFX1164-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1164-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1164-TRUE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1164-TRUE16-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164-TRUE16-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
+; GFX1164-TRUE16-NEXT:    s_cbranch_execnz .LBB16_2
+; GFX1164-TRUE16-NEXT:  ; %bb.3: ; %atomicrmw.end
+; GFX1164-TRUE16-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX1164-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s11, v2
+; GFX1164-TRUE16-NEXT:  .LBB16_4: ; %Flow
+; GFX1164-TRUE16-NEXT:    s_or_b64 exec, exec, s[8:9]
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1164-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1164-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1164-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1164-TRUE16-NEXT:    v_mad_u16 v0.l, s10, v4.l, s2
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1164-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX1164-TRUE16-NEXT:    s_endpgm
+;
+; GFX1164-FAKE16-LABEL: uniform_add_i16:
+; GFX1164-FAKE16:       ; %bb.0:
+; GFX1164-FAKE16-NEXT:    s_clause 0x1
+; GFX1164-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1164-FAKE16-NEXT:    s_load_b32 s10, s[4:5], 0x34
+; GFX1164-FAKE16-NEXT:    s_mov_b64 s[6:7], exec
+; GFX1164-FAKE16-NEXT:    s_mov_b64 s[8:9], exec
+; GFX1164-FAKE16-NEXT:    v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164-FAKE16-NEXT:    v_mbcnt_hi_u32_b32 v4, s7, v0
+; GFX1164-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; GFX1164-FAKE16-NEXT:    v_cmpx_eq_u32_e32 0, v4
+; GFX1164-FAKE16-NEXT:    s_cbranch_execz .LBB16_4
+; GFX1164-FAKE16-NEXT:  ; %bb.1:
+; GFX1164-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-FAKE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s5, s3
+; GFX1164-FAKE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1164-FAKE16-NEXT:    s_load_b32 s3, s[4:5], 0x0
+; GFX1164-FAKE16-NEXT:    s_bcnt1_i32_b64 s6, s[6:7]
+; GFX1164-FAKE16-NEXT:    s_lshl_b32 s11, s2, 3
+; GFX1164-FAKE16-NEXT:    s_mul_i32 s2, s10, s6
+; GFX1164-FAKE16-NEXT:    s_lshl_b32 s12, 0xffff, s11
+; GFX1164-FAKE16-NEXT:    s_and_b32 s2, s2, 0xffff
+; GFX1164-FAKE16-NEXT:    s_not_b32 s13, s12
+; GFX1164-FAKE16-NEXT:    s_lshl_b32 s14, s2, s11
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s6, -1
+; GFX1164-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-FAKE16-NEXT:    v_mov_b32_e32 v1, s3
+; GFX1164-FAKE16-NEXT:    s_mov_b64 s[2:3], 0
+; GFX1164-FAKE16-NEXT:  .LBB16_2: ; %atomicrmw.start
+; GFX1164-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164-FAKE16-NEXT:    v_add_nc_u32_e32 v0, s14, v1
+; GFX1164-FAKE16-NEXT:    v_and_b32_e32 v0, s12, v0
+; GFX1164-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1164-FAKE16-NEXT:    v_and_or_b32 v0, v1, s13, v0
+; GFX1164-FAKE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1164-FAKE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX1164-FAKE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
+; GFX1164-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1164-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1164-FAKE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1164-FAKE16-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164-FAKE16-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
+; GFX1164-FAKE16-NEXT:    s_cbranch_execnz .LBB16_2
+; GFX1164-FAKE16-NEXT:  ; %bb.3: ; %atomicrmw.end
+; GFX1164-FAKE16-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX1164-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s11, v2
+; GFX1164-FAKE16-NEXT:  .LBB16_4: ; %Flow
+; GFX1164-FAKE16-NEXT:    s_or_b64 exec, exec, s[8:9]
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1164-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1164-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1164-FAKE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1164-FAKE16-NEXT:    v_mad_u16 v0, s10, v4, s2
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1164-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX1164-FAKE16-NEXT:    s_endpgm
+;
+; GFX1132-TRUE16-LABEL: uniform_add_i16:
+; GFX1132-TRUE16:       ; %bb.0:
+; GFX1132-TRUE16-NEXT:    s_clause 0x1
+; GFX1132-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1132-TRUE16-NEXT:    s_load_b32 s8, s[4:5], 0x34
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s6, exec_lo
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s10, 0
+; GFX1132-TRUE16-NEXT:    v_mbcnt_lo_u32_b32 v4, s6, 0
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s9, exec_lo
+; GFX1132-TRUE16-NEXT:    ; implicit-def: $vgpr0_lo16
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1132-TRUE16-NEXT:    v_cmpx_eq_u32_e32 0, v4
+; GFX1132-TRUE16-NEXT:    s_cbranch_execz .LBB16_4
+; GFX1132-TRUE16-NEXT:  ; %bb.1:
+; GFX1132-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-TRUE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s5, s3
+; GFX1132-TRUE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1132-TRUE16-NEXT:    s_load_b32 s7, s[4:5], 0x0
+; GFX1132-TRUE16-NEXT:    s_bcnt1_i32_b32 s6, s6
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s11, s8
+; GFX1132-TRUE16-NEXT:    s_lshl_b32 s2, s2, 3
+; GFX1132-TRUE16-NEXT:    s_mul_i32 s6, s11, s6
+; GFX1132-TRUE16-NEXT:    s_lshl_b32 s3, 0xffff, s2
+; GFX1132-TRUE16-NEXT:    s_and_b32 s6, s6, 0xffff
+; GFX1132-TRUE16-NEXT:    s_not_b32 s11, s3
+; GFX1132-TRUE16-NEXT:    s_lshl_b32 s12, s6, s2
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s6, -1
+; GFX1132-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-TRUE16-NEXT:    v_mov_b32_e32 v1, s7
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1132-TRUE16-NEXT:  .LBB16_2: ; %atomicrmw.start
+; GFX1132-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132-TRUE16-NEXT:    v_add_nc_u32_e32 v0, s12, v1
+; GFX1132-TRUE16-NEXT:    v_and_b32_e32 v0, s3, v0
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132-TRUE16-NEXT:    v_and_or_b32 v0, v1, s11, v0
+; GFX1132-TRUE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1132-TRUE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
+; GFX1132-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1132-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1132-TRUE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1132-TRUE16-NEXT:    s_or_b32 s10, vcc_lo, s10
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s10
+; GFX1132-TRUE16-NEXT:    s_cbranch_execnz .LBB16_2
+; GFX1132-TRUE16-NEXT:  ; %bb.3: ; %atomicrmw.end
+; GFX1132-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s10
+; GFX1132-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s2, v2
+; GFX1132-TRUE16-NEXT:  .LBB16_4: ; %Flow
+; GFX1132-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s9
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1132-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1132-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1132-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1132-TRUE16-NEXT:    v_mad_u16 v0.l, s8, v4.l, s2
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1132-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX1132-TRUE16-NEXT:    s_endpgm
+;
+; GFX1132-FAKE16-LABEL: uniform_add_i16:
+; GFX1132-FAKE16:       ; %bb.0:
+; GFX1132-FAKE16-NEXT:    s_clause 0x1
+; GFX1132-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1132-FAKE16-NEXT:    s_load_b32 s8, s[4:5], 0x34
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s6, exec_lo
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s10, 0
+; GFX1132-FAKE16-NEXT:    v_mbcnt_lo_u32_b32 v4, s6, 0
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s9, exec_lo
+; GFX1132-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1132-FAKE16-NEXT:    v_cmpx_eq_u32_e32 0, v4
+; GFX1132-FAKE16-NEXT:    s_cbranch_execz .LBB16_4
+; GFX1132-FAKE16-NEXT:  ; %bb.1:
+; GFX1132-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-FAKE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s5, s3
+; GFX1132-FAKE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1132-FAKE16-NEXT:    s_load_b32 s7, s[4:5], 0x0
+; GFX1132-FAKE16-NEXT:    s_bcnt1_i32_b32 s6, s6
+; GFX1132-FAKE16-NEXT:    s_lshl_b32 s2, s2, 3
+; GFX1132-FAKE16-NEXT:    s_mul_i32 s6, s8, s6
+; GFX1132-FAKE16-NEXT:    s_lshl_b32 s3, 0xffff, s2
+; GFX1132-FAKE16-NEXT:    s_and_b32 s6, s6, 0xffff
+; GFX1132-FAKE16-NEXT:    s_not_b32 s11, s3
+; GFX1132-FAKE16-NEXT:    s_lshl_b32 s12, s6, s2
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s6, -1
+; GFX1132-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-FAKE16-NEXT:    v_mov_b32_e32 v1, s7
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1132-FAKE16-NEXT:  .LBB16_2: ; %atomicrmw.start
+; GFX1132-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132-FAKE16-NEXT:    v_add_nc_u32_e32 v0, s12, v1
+; GFX1132-FAKE16-NEXT:    v_and_b32_e32 v0, s3, v0
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132-FAKE16-NEXT:    v_and_or_b32 v0, v1, s11, v0
+; GFX1132-FAKE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1132-FAKE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
+; GFX1132-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1132-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1132-FAKE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1132-FAKE16-NEXT:    s_or_b32 s10, vcc_lo, s10
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s10
+; GFX1132-FAKE16-NEXT:    s_cbranch_execnz .LBB16_2
+; GFX1132-FAKE16-NEXT:  ; %bb.3: ; %atomicrmw.end
+; GFX1132-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s10
+; GFX1132-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s2, v2
+; GFX1132-FAKE16-NEXT:  .LBB16_4: ; %Flow
+; GFX1132-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s9
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1132-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1132-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1132-FAKE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1132-FAKE16-NEXT:    v_mad_u16 v0, s8, v4, s2
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1132-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX1132-FAKE16-NEXT:    s_endpgm
+;
+; GFX1264-TRUE16-LABEL: uniform_add_i16:
+; GFX1264-TRUE16:       ; %bb.0:
+; GFX1264-TRUE16-NEXT:    s_clause 0x1
+; GFX1264-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1264-TRUE16-NEXT:    s_load_b32 s10, s[4:5], 0x34
+; GFX1264-TRUE16-NEXT:    s_mov_b64 s[6:7], exec
+; GFX1264-TRUE16-NEXT:    s_mov_b64 s[8:9], exec
+; GFX1264-TRUE16-NEXT:    v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1264-TRUE16-NEXT:    v_mbcnt_hi_u32_b32 v4, s7, v0
+; GFX1264-TRUE16-NEXT:    ; implicit-def: $vgpr0_lo16
+; GFX1264-TRUE16-NEXT:    v_cmpx_eq_u32_e32 0, v4
+; GFX1264-TRUE16-NEXT:    s_cbranch_execz .LBB16_4
+; GFX1264-TRUE16-NEXT:  ; %bb.1:
+; GFX1264-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-TRUE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s5, s3
+; GFX1264-TRUE16-NEXT:    s_bcnt1_i32_b64 s6, s[6:7]
+; GFX1264-TRUE16-NEXT:    s_load_b32 s3, s[4:5], 0x0
+; GFX1264-TRUE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s7, s10
+; GFX1264-TRUE16-NEXT:    s_lshl_b32 s11, s2, 3
+; GFX1264-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1264-TRUE16-NEXT:    s_mul_i32 s7, s7, s6
+; GFX1264-TRUE16-NEXT:    s_lshl_b32 s12, 0xffff, s11
+; GFX1264-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1264-TRUE16-NEXT:    s_and_b32 s2, s7, 0xffff
+; GFX1264-TRUE16-NEXT:    s_not_b32 s13, s12
+; GFX1264-TRUE16-NEXT:    s_lshl_b32 s14, s2, s11
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s6, -1
+; GFX1264-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-TRUE16-NEXT:    v_mov_b32_e32 v1, s3
+; GFX1264-TRUE16-NEXT:    s_mov_b64 s[2:3], 0
+; GFX1264-TRUE16-NEXT:  .LBB16_2: ; %atomicrmw.start
+; GFX1264-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1264-TRUE16-NEXT:    v_add_nc_u32_e32 v0, s14, v1
+; GFX1264-TRUE16-NEXT:    v_and_b32_e32 v0, s12, v0
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1264-TRUE16-NEXT:    v_and_or_b32 v0, v1, s13, v0
+; GFX1264-TRUE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX1264-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX1264-TRUE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1264-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1264-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1264-TRUE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1264-TRUE16-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1264-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1264-TRUE16-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
+; GFX1264-TRUE16-NEXT:    s_cbranch_execnz .LBB16_2
+; GFX1264-TRUE16-NEXT:  ; %bb.3: ; %atomicrmw.end
+; GFX1264-TRUE16-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX1264-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s11, v2
+; GFX1264-TRUE16-NEXT:  .LBB16_4: ; %Flow
+; GFX1264-TRUE16-NEXT:    s_or_b64 exec, exec, s[8:9]
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1264-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1264-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1264-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1264-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX1264-TRUE16-NEXT:    v_mad_u16 v0.l, s10, v4.l, s2
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1264-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], null
+; GFX1264-TRUE16-NEXT:    s_endpgm
+;
+; GFX1264-FAKE16-LABEL: uniform_add_i16:
+; GFX1264-FAKE16:       ; %bb.0:
+; GFX1264-FAKE16-NEXT:    s_clause 0x1
+; GFX1264-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1264-FAKE16-NEXT:    s_load_b32 s10, s[4:5], 0x34
+; GFX1264-FAKE16-NEXT:    s_mov_b64 s[6:7], exec
+; GFX1264-FAKE16-NEXT:    s_mov_b64 s[8:9], exec
+; GFX1264-FAKE16-NEXT:    v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1264-FAKE16-NEXT:    v_mbcnt_hi_u32_b32 v4, s7, v0
+; GFX1264-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; GFX1264-FAKE16-NEXT:    v_cmpx_eq_u32_e32 0, v4
+; GFX1264-FAKE16-NEXT:    s_cbranch_execz .LBB16_4
+; GFX1264-FAKE16-NEXT:  ; %bb.1:
+; GFX1264-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-FAKE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s5, s3
+; GFX1264-FAKE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1264-FAKE16-NEXT:    s_load_b32 s3, s[4:5], 0x0
+; GFX1264-FAKE16-NEXT:    s_bcnt1_i32_b64 s6, s[6:7]
+; GFX1264-FAKE16-NEXT:    s_lshl_b32 s11, s2, 3
+; GFX1264-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1264-FAKE16-NEXT:    s_mul_i32 s2, s10, s6
+; GFX1264-FAKE16-NEXT:    s_lshl_b32 s12, 0xffff, s11
+; GFX1264-FAKE16-NEXT:    s_and_b32 s2, s2, 0xffff
+; GFX1264-FAKE16-NEXT:    s_not_b32 s13, s12
+; GFX1264-FAKE16-NEXT:    s_lshl_b32 s14, s2, s11
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s6, -1
+; GFX1264-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-FAKE16-NEXT:    v_mov_b32_e32 v1, s3
+; GFX1264-FAKE16-NEXT:    s_mov_b64 s[2:3], 0
+; GFX1264-FAKE16-NEXT:  .LBB16_2: ; %atomicrmw.start
+; GFX1264-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1264-FAKE16-NEXT:    v_add_nc_u32_e32 v0, s14, v1
+; GFX1264-FAKE16-NEXT:    v_and_b32_e32 v0, s12, v0
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1264-FAKE16-NEXT:    v_and_or_b32 v0, v1, s13, v0
+; GFX1264-FAKE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX1264-FAKE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX1264-FAKE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1264-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1264-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1264-FAKE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1264-FAKE16-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1264-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1264-FAKE16-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
+; GFX1264-FAKE16-NEXT:    s_cbranch_execnz .LBB16_2
+; GFX1264-FAKE16-NEXT:  ; %bb.3: ; %atomicrmw.end
+; GFX1264-FAKE16-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX1264-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s11, v2
+; GFX1264-FAKE16-NEXT:  .LBB16_4: ; %Flow
+; GFX1264-FAKE16-NEXT:    s_or_b64 exec, exec, s[8:9]
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1264-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1264-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1264-FAKE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1264-FAKE16-NEXT:    s_wait_alu 0xf1ff
+; GFX1264-FAKE16-NEXT:    v_mad_u16 v0, s10, v4, s2
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1264-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], null
+; GFX1264-FAKE16-NEXT:    s_endpgm
+;
+; GFX1232-TRUE16-LABEL: uniform_add_i16:
+; GFX1232-TRUE16:       ; %bb.0:
+; GFX1232-TRUE16-NEXT:    s_clause 0x1
+; GFX1232-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1232-TRUE16-NEXT:    s_load_b32 s8, s[4:5], 0x34
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s6, exec_lo
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s10, 0
+; GFX1232-TRUE16-NEXT:    v_mbcnt_lo_u32_b32 v4, s6, 0
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s9, exec_lo
+; GFX1232-TRUE16-NEXT:    ; implicit-def: $vgpr0_lo16
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1232-TRUE16-NEXT:    v_cmpx_eq_u32_e32 0, v4
+; GFX1232-TRUE16-NEXT:    s_cbranch_execz .LBB16_4
+; GFX1232-TRUE16-NEXT:  ; %bb.1:
+; GFX1232-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-TRUE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s5, s3
+; GFX1232-TRUE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1232-TRUE16-NEXT:    s_load_b32 s7, s[4:5], 0x0
+; GFX1232-TRUE16-NEXT:    s_bcnt1_i32_b32 s6, s6
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s11, s8
+; GFX1232-TRUE16-NEXT:    s_lshl_b32 s2, s2, 3
+; GFX1232-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1232-TRUE16-NEXT:    s_mul_i32 s6, s11, s6
+; GFX1232-TRUE16-NEXT:    s_lshl_b32 s3, 0xffff, s2
+; GFX1232-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1232-TRUE16-NEXT:    s_and_b32 s6, s6, 0xffff
+; GFX1232-TRUE16-NEXT:    s_not_b32 s11, s3
+; GFX1232-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1232-TRUE16-NEXT:    s_lshl_b32 s12, s6, s2
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s6, -1
+; GFX1232-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-TRUE16-NEXT:    v_mov_b32_e32 v1, s7
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1232-TRUE16-NEXT:  .LBB16_2: ; %atomicrmw.start
+; GFX1232-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1232-TRUE16-NEXT:    v_add_nc_u32_e32 v0, s12, v1
+; GFX1232-TRUE16-NEXT:    v_and_b32_e32 v0, s3, v0
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1232-TRUE16-NEXT:    v_and_or_b32 v0, v1, s11, v0
+; GFX1232-TRUE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1232-TRUE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1232-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1232-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1232-TRUE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1232-TRUE16-NEXT:    s_or_b32 s10, vcc_lo, s10
+; GFX1232-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1232-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s10
+; GFX1232-TRUE16-NEXT:    s_cbranch_execnz .LBB16_2
+; GFX1232-TRUE16-NEXT:  ; %bb.3: ; %atomicrmw.end
+; GFX1232-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s10
+; GFX1232-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s2, v2
+; GFX1232-TRUE16-NEXT:  .LBB16_4: ; %Flow
+; GFX1232-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s9
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1232-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1232-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1232-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1232-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX1232-TRUE16-NEXT:    v_mad_u16 v0.l, s8, v4.l, s2
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1232-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], null
+; GFX1232-TRUE16-NEXT:    s_endpgm
+;
+; GFX1232-FAKE16-LABEL: uniform_add_i16:
+; GFX1232-FAKE16:       ; %bb.0:
+; GFX1232-FAKE16-NEXT:    s_clause 0x1
+; GFX1232-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1232-FAKE16-NEXT:    s_load_b32 s8, s[4:5], 0x34
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s6, exec_lo
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s10, 0
+; GFX1232-FAKE16-NEXT:    v_mbcnt_lo_u32_b32 v4, s6, 0
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s9, exec_lo
+; GFX1232-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1232-FAKE16-NEXT:    v_cmpx_eq_u32_e32 0, v4
+; GFX1232-FAKE16-NEXT:    s_cbranch_execz .LBB16_4
+; GFX1232-FAKE16-NEXT:  ; %bb.1:
+; GFX1232-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-FAKE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s5, s3
+; GFX1232-FAKE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1232-FAKE16-NEXT:    s_load_b32 s7, s[4:5], 0x0
+; GFX1232-FAKE16-NEXT:    s_bcnt1_i32_b32 s6, s6
+; GFX1232-FAKE16-NEXT:    s_lshl_b32 s2, s2, 3
+; GFX1232-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1232-FAKE16-NEXT:    s_mul_i32 s6, s8, s6
+; GFX1232-FAKE16-NEXT:    s_lshl_b32 s3, 0xffff, s2
+; GFX1232-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1232-FAKE16-NEXT:    s_and_b32 s6, s6, 0xffff
+; GFX1232-FAKE16-NEXT:    s_not_b32 s11, s3
+; GFX1232-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1232-FAKE16-NEXT:    s_lshl_b32 s12, s6, s2
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s6, -1
+; GFX1232-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-FAKE16-NEXT:    v_mov_b32_e32 v1, s7
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1232-FAKE16-NEXT:  .LBB16_2: ; %atomicrmw.start
+; GFX1232-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1232-FAKE16-NEXT:    v_add_nc_u32_e32 v0, s12, v1
+; GFX1232-FAKE16-NEXT:    v_and_b32_e32 v0, s3, v0
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1232-FAKE16-NEXT:    v_and_or_b32 v0, v1, s11, v0
+; GFX1232-FAKE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1232-FAKE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1232-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1232-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1232-FAKE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1232-FAKE16-NEXT:    s_or_b32 s10, vcc_lo, s10
+; GFX1232-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1232-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s10
+; GFX1232-FAKE16-NEXT:    s_cbranch_execnz .LBB16_2
+; GFX1232-FAKE16-NEXT:  ; %bb.3: ; %atomicrmw.end
+; GFX1232-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s10
+; GFX1232-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s2, v2
+; GFX1232-FAKE16-NEXT:  .LBB16_4: ; %Flow
+; GFX1232-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s9
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1232-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1232-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1232-FAKE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1232-FAKE16-NEXT:    s_wait_alu 0xf1ff
+; GFX1232-FAKE16-NEXT:    v_mad_u16 v0, s8, v4, s2
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1232-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], null
+; GFX1232-FAKE16-NEXT:    s_endpgm
   %rmw = atomicrmw add ptr addrspace(1) %uniform.ptr, i16 %val monotonic, align 2
   store i16 %rmw, ptr addrspace(1) %result
   ret void
@@ -9863,191 +10719,377 @@ define amdgpu_kernel void @uniform_fadd_f16(ptr addrspace(1) %result, ptr addrsp
 ; GFX1032-NEXT:    buffer_store_short v0, off, s[0:3], 0
 ; GFX1032-NEXT:    s_endpgm
 ;
-; GFX1164-LABEL: uniform_fadd_f16:
-; GFX1164:       ; %bb.0:
-; GFX1164-NEXT:    s_clause 0x1
-; GFX1164-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1164-NEXT:    s_load_b32 s8, s[4:5], 0x34
-; GFX1164-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1164-NEXT:    s_mov_b32 s6, -1
-; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_and_b32 s4, s2, -4
-; GFX1164-NEXT:    s_mov_b32 s5, s3
-; GFX1164-NEXT:    s_and_b32 s2, s2, 3
-; GFX1164-NEXT:    s_load_b32 s3, s[4:5], 0x0
-; GFX1164-NEXT:    s_lshl_b32 s9, s2, 3
-; GFX1164-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1164-NEXT:    s_lshl_b32 s2, 0xffff, s9
-; GFX1164-NEXT:    s_not_b32 s10, s2
-; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    v_mov_b32_e32 v1, s3
-; GFX1164-NEXT:    s_mov_b64 s[2:3], 0
-; GFX1164-NEXT:  .LBB18_1: ; %atomicrmw.start
-; GFX1164-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1164-NEXT:    v_lshrrev_b32_e32 v0, s9, v1
-; GFX1164-NEXT:    v_add_f16_e32 v0, s8, v0
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1164-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX1164-NEXT:    v_lshlrev_b32_e32 v0, s9, v0
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1164-NEXT:    v_and_or_b32 v0, v1, s10, v0
-; GFX1164-NEXT:    v_mov_b32_e32 v3, v1
-; GFX1164-NEXT:    v_mov_b32_e32 v2, v0
-; GFX1164-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
-; GFX1164-NEXT:    s_waitcnt vmcnt(0)
-; GFX1164-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
-; GFX1164-NEXT:    v_mov_b32_e32 v1, v2
-; GFX1164-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
-; GFX1164-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
-; GFX1164-NEXT:    s_cbranch_execnz .LBB18_1
-; GFX1164-NEXT:  ; %bb.2: ; %atomicrmw.end
-; GFX1164-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX1164-NEXT:    v_lshrrev_b32_e32 v0, s9, v2
-; GFX1164-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX1164-NEXT:    s_mov_b32 s2, -1
-; GFX1164-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
-; GFX1164-NEXT:    s_endpgm
-;
-; GFX1132-LABEL: uniform_fadd_f16:
-; GFX1132:       ; %bb.0:
-; GFX1132-NEXT:    s_clause 0x1
-; GFX1132-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1132-NEXT:    s_load_b32 s8, s[4:5], 0x34
-; GFX1132-NEXT:    s_mov_b32 s9, 0
-; GFX1132-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_and_b32 s4, s2, -4
-; GFX1132-NEXT:    s_mov_b32 s5, s3
-; GFX1132-NEXT:    s_and_b32 s2, s2, 3
-; GFX1132-NEXT:    s_load_b32 s6, s[4:5], 0x0
-; GFX1132-NEXT:    s_lshl_b32 s2, s2, 3
-; GFX1132-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1132-NEXT:    s_lshl_b32 s3, 0xffff, s2
-; GFX1132-NEXT:    s_not_b32 s3, s3
-; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    v_mov_b32_e32 v1, s6
-; GFX1132-NEXT:    s_mov_b32 s6, -1
-; GFX1132-NEXT:  .LBB18_1: ; %atomicrmw.start
-; GFX1132-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1132-NEXT:    v_lshrrev_b32_e32 v0, s2, v1
-; GFX1132-NEXT:    v_add_f16_e32 v0, s8, v0
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1132-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX1132-NEXT:    v_lshlrev_b32_e32 v0, s2, v0
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1132-NEXT:    v_and_or_b32 v0, v1, s3, v0
-; GFX1132-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
-; GFX1132-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
-; GFX1132-NEXT:    s_waitcnt vmcnt(0)
-; GFX1132-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
-; GFX1132-NEXT:    v_mov_b32_e32 v1, v2
-; GFX1132-NEXT:    s_or_b32 s9, vcc_lo, s9
-; GFX1132-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s9
-; GFX1132-NEXT:    s_cbranch_execnz .LBB18_1
-; GFX1132-NEXT:  ; %bb.2: ; %atomicrmw.end
-; GFX1132-NEXT:    s_or_b32 exec_lo, exec_lo, s9
-; GFX1132-NEXT:    v_lshrrev_b32_e32 v0, s2, v2
-; GFX1132-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX1132-NEXT:    s_mov_b32 s2, -1
-; GFX1132-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
-; GFX1132-NEXT:    s_endpgm
-;
-; GFX1264-LABEL: uniform_fadd_f16:
-; GFX1264:       ; %bb.0:
-; GFX1264-NEXT:    s_clause 0x1
-; GFX1264-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1264-NEXT:    s_load_b32 s8, s[4:5], 0x34
-; GFX1264-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1264-NEXT:    s_mov_b32 s6, -1
-; GFX1264-NEXT:    s_wait_kmcnt 0x0
-; GFX1264-NEXT:    s_and_b32 s4, s2, -4
-; GFX1264-NEXT:    s_mov_b32 s5, s3
-; GFX1264-NEXT:    s_and_b32 s2, s2, 3
-; GFX1264-NEXT:    s_load_b32 s3, s[4:5], 0x0
-; GFX1264-NEXT:    s_lshl_b32 s9, s2, 3
-; GFX1264-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1264-NEXT:    s_lshl_b32 s2, 0xffff, s9
-; GFX1264-NEXT:    s_not_b32 s10, s2
-; GFX1264-NEXT:    s_wait_kmcnt 0x0
-; GFX1264-NEXT:    v_mov_b32_e32 v1, s3
-; GFX1264-NEXT:    s_mov_b64 s[2:3], 0
-; GFX1264-NEXT:  .LBB18_1: ; %atomicrmw.start
-; GFX1264-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX1264-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1264-NEXT:    v_lshrrev_b32_e32 v0, s9, v1
-; GFX1264-NEXT:    v_add_f16_e32 v0, s8, v0
-; GFX1264-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1264-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX1264-NEXT:    v_lshlrev_b32_e32 v0, s9, v0
-; GFX1264-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1264-NEXT:    v_and_or_b32 v0, v1, s10, v0
-; GFX1264-NEXT:    v_mov_b32_e32 v3, v1
-; GFX1264-NEXT:    v_mov_b32_e32 v2, v0
-; GFX1264-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
-; GFX1264-NEXT:    s_wait_loadcnt 0x0
-; GFX1264-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
-; GFX1264-NEXT:    v_mov_b32_e32 v1, v2
-; GFX1264-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
-; GFX1264-NEXT:    s_wait_alu 0xfffe
-; GFX1264-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
-; GFX1264-NEXT:    s_cbranch_execnz .LBB18_1
-; GFX1264-NEXT:  ; %bb.2: ; %atomicrmw.end
-; GFX1264-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX1264-NEXT:    v_lshrrev_b32_e32 v0, s9, v2
-; GFX1264-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX1264-NEXT:    s_mov_b32 s2, -1
-; GFX1264-NEXT:    buffer_store_b16 v0, off, s[0:3], null
-; GFX1264-NEXT:    s_endpgm
-;
-; GFX1232-LABEL: uniform_fadd_f16:
-; GFX1232:       ; %bb.0:
-; GFX1232-NEXT:    s_clause 0x1
-; GFX1232-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1232-NEXT:    s_load_b32 s8, s[4:5], 0x34
-; GFX1232-NEXT:    s_mov_b32 s9, 0
-; GFX1232-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1232-NEXT:    s_wait_kmcnt 0x0
-; GFX1232-NEXT:    s_and_b32 s4, s2, -4
-; GFX1232-NEXT:    s_mov_b32 s5, s3
-; GFX1232-NEXT:    s_and_b32 s2, s2, 3
-; GFX1232-NEXT:    s_load_b32 s6, s[4:5], 0x0
-; GFX1232-NEXT:    s_lshl_b32 s2, s2, 3
-; GFX1232-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1232-NEXT:    s_lshl_b32 s3, 0xffff, s2
-; GFX1232-NEXT:    s_not_b32 s3, s3
-; GFX1232-NEXT:    s_wait_kmcnt 0x0
-; GFX1232-NEXT:    v_mov_b32_e32 v1, s6
-; GFX1232-NEXT:    s_mov_b32 s6, -1
-; GFX1232-NEXT:  .LBB18_1: ; %atomicrmw.start
-; GFX1232-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX1232-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1232-NEXT:    v_lshrrev_b32_e32 v0, s2, v1
-; GFX1232-NEXT:    v_add_f16_e32 v0, s8, v0
-; GFX1232-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1232-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX1232-NEXT:    v_lshlrev_b32_e32 v0, s2, v0
-; GFX1232-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1232-NEXT:    v_and_or_b32 v0, v1, s3, v0
-; GFX1232-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
-; GFX1232-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
-; GFX1232-NEXT:    s_wait_loadcnt 0x0
-; GFX1232-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
-; GFX1232-NEXT:    v_mov_b32_e32 v1, v2
-; GFX1232-NEXT:    s_or_b32 s9, vcc_lo, s9
-; GFX1232-NEXT:    s_wait_alu 0xfffe
-; GFX1232-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s9
-; GFX1232-NEXT:    s_cbranch_execnz .LBB18_1
-; GFX1232-NEXT:  ; %bb.2: ; %atomicrmw.end
-; GFX1232-NEXT:    s_or_b32 exec_lo, exec_lo, s9
-; GFX1232-NEXT:    v_lshrrev_b32_e32 v0, s2, v2
-; GFX1232-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX1232-NEXT:    s_mov_b32 s2, -1
-; GFX1232-NEXT:    buffer_store_b16 v0, off, s[0:3], null
-; GFX1232-NEXT:    s_endpgm
+; GFX1164-TRUE16-LABEL: uniform_fadd_f16:
+; GFX1164-TRUE16:       ; %bb.0:
+; GFX1164-TRUE16-NEXT:    s_clause 0x1
+; GFX1164-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1164-TRUE16-NEXT:    s_load_b32 s8, s[4:5], 0x34
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s6, -1
+; GFX1164-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-TRUE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s5, s3
+; GFX1164-TRUE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1164-TRUE16-NEXT:    s_load_b32 s3, s[4:5], 0x0
+; GFX1164-TRUE16-NEXT:    s_lshl_b32 s9, s2, 3
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164-TRUE16-NEXT:    s_lshl_b32 s2, 0xffff, s9
+; GFX1164-TRUE16-NEXT:    s_not_b32 s10, s2
+; GFX1164-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-TRUE16-NEXT:    v_mov_b32_e32 v1, s3
+; GFX1164-TRUE16-NEXT:    s_mov_b64 s[2:3], 0
+; GFX1164-TRUE16-NEXT:  .LBB18_1: ; %atomicrmw.start
+; GFX1164-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s9, v1
+; GFX1164-TRUE16-NEXT:    v_add_f16_e32 v0.l, s8, v0.l
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1164-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, s9, v0
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1164-TRUE16-NEXT:    v_and_or_b32 v0, v1, s10, v0
+; GFX1164-TRUE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX1164-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX1164-TRUE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
+; GFX1164-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1164-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1164-TRUE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1164-TRUE16-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164-TRUE16-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
+; GFX1164-TRUE16-NEXT:    s_cbranch_execnz .LBB18_1
+; GFX1164-TRUE16-NEXT:  ; %bb.2: ; %atomicrmw.end
+; GFX1164-TRUE16-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX1164-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s9, v2
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1164-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX1164-TRUE16-NEXT:    s_endpgm
+;
+; GFX1164-FAKE16-LABEL: uniform_fadd_f16:
+; GFX1164-FAKE16:       ; %bb.0:
+; GFX1164-FAKE16-NEXT:    s_clause 0x1
+; GFX1164-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1164-FAKE16-NEXT:    s_load_b32 s8, s[4:5], 0x34
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s6, -1
+; GFX1164-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-FAKE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s5, s3
+; GFX1164-FAKE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1164-FAKE16-NEXT:    s_load_b32 s3, s[4:5], 0x0
+; GFX1164-FAKE16-NEXT:    s_lshl_b32 s9, s2, 3
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164-FAKE16-NEXT:    s_lshl_b32 s2, 0xffff, s9
+; GFX1164-FAKE16-NEXT:    s_not_b32 s10, s2
+; GFX1164-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-FAKE16-NEXT:    v_mov_b32_e32 v1, s3
+; GFX1164-FAKE16-NEXT:    s_mov_b64 s[2:3], 0
+; GFX1164-FAKE16-NEXT:  .LBB18_1: ; %atomicrmw.start
+; GFX1164-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s9, v1
+; GFX1164-FAKE16-NEXT:    v_add_f16_e32 v0, s8, v0
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1164-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, s9, v0
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1164-FAKE16-NEXT:    v_and_or_b32 v0, v1, s10, v0
+; GFX1164-FAKE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX1164-FAKE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX1164-FAKE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
+; GFX1164-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1164-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1164-FAKE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1164-FAKE16-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164-FAKE16-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
+; GFX1164-FAKE16-NEXT:    s_cbranch_execnz .LBB18_1
+; GFX1164-FAKE16-NEXT:  ; %bb.2: ; %atomicrmw.end
+; GFX1164-FAKE16-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX1164-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s9, v2
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1164-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX1164-FAKE16-NEXT:    s_endpgm
+;
+; GFX1132-TRUE16-LABEL: uniform_fadd_f16:
+; GFX1132-TRUE16:       ; %bb.0:
+; GFX1132-TRUE16-NEXT:    s_clause 0x1
+; GFX1132-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1132-TRUE16-NEXT:    s_load_b32 s8, s[4:5], 0x34
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s9, 0
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1132-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-TRUE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s5, s3
+; GFX1132-TRUE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1132-TRUE16-NEXT:    s_load_b32 s6, s[4:5], 0x0
+; GFX1132-TRUE16-NEXT:    s_lshl_b32 s2, s2, 3
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132-TRUE16-NEXT:    s_lshl_b32 s3, 0xffff, s2
+; GFX1132-TRUE16-NEXT:    s_not_b32 s3, s3
+; GFX1132-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-TRUE16-NEXT:    v_mov_b32_e32 v1, s6
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s6, -1
+; GFX1132-TRUE16-NEXT:  .LBB18_1: ; %atomicrmw.start
+; GFX1132-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s2, v1
+; GFX1132-TRUE16-NEXT:    v_add_f16_e32 v0.l, s8, v0.l
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1132-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, s2, v0
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132-TRUE16-NEXT:    v_and_or_b32 v0, v1, s3, v0
+; GFX1132-TRUE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1132-TRUE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
+; GFX1132-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1132-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1132-TRUE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1132-TRUE16-NEXT:    s_or_b32 s9, vcc_lo, s9
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s9
+; GFX1132-TRUE16-NEXT:    s_cbranch_execnz .LBB18_1
+; GFX1132-TRUE16-NEXT:  ; %bb.2: ; %atomicrmw.end
+; GFX1132-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s9
+; GFX1132-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s2, v2
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1132-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX1132-TRUE16-NEXT:    s_endpgm
+;
+; GFX1132-FAKE16-LABEL: uniform_fadd_f16:
+; GFX1132-FAKE16:       ; %bb.0:
+; GFX1132-FAKE16-NEXT:    s_clause 0x1
+; GFX1132-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1132-FAKE16-NEXT:    s_load_b32 s8, s[4:5], 0x34
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s9, 0
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1132-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-FAKE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s5, s3
+; GFX1132-FAKE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1132-FAKE16-NEXT:    s_load_b32 s6, s[4:5], 0x0
+; GFX1132-FAKE16-NEXT:    s_lshl_b32 s2, s2, 3
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132-FAKE16-NEXT:    s_lshl_b32 s3, 0xffff, s2
+; GFX1132-FAKE16-NEXT:    s_not_b32 s3, s3
+; GFX1132-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-FAKE16-NEXT:    v_mov_b32_e32 v1, s6
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s6, -1
+; GFX1132-FAKE16-NEXT:  .LBB18_1: ; %atomicrmw.start
+; GFX1132-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s2, v1
+; GFX1132-FAKE16-NEXT:    v_add_f16_e32 v0, s8, v0
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1132-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, s2, v0
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132-FAKE16-NEXT:    v_and_or_b32 v0, v1, s3, v0
+; GFX1132-FAKE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1132-FAKE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
+; GFX1132-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1132-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1132-FAKE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1132-FAKE16-NEXT:    s_or_b32 s9, vcc_lo, s9
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s9
+; GFX1132-FAKE16-NEXT:    s_cbranch_execnz .LBB18_1
+; GFX1132-FAKE16-NEXT:  ; %bb.2: ; %atomicrmw.end
+; GFX1132-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s9
+; GFX1132-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s2, v2
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1132-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX1132-FAKE16-NEXT:    s_endpgm
+;
+; GFX1264-TRUE16-LABEL: uniform_fadd_f16:
+; GFX1264-TRUE16:       ; %bb.0:
+; GFX1264-TRUE16-NEXT:    s_clause 0x1
+; GFX1264-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1264-TRUE16-NEXT:    s_load_b32 s8, s[4:5], 0x34
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s6, -1
+; GFX1264-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-TRUE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s5, s3
+; GFX1264-TRUE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1264-TRUE16-NEXT:    s_load_b32 s3, s[4:5], 0x0
+; GFX1264-TRUE16-NEXT:    s_lshl_b32 s9, s2, 3
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1264-TRUE16-NEXT:    s_lshl_b32 s2, 0xffff, s9
+; GFX1264-TRUE16-NEXT:    s_not_b32 s10, s2
+; GFX1264-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-TRUE16-NEXT:    v_mov_b32_e32 v1, s3
+; GFX1264-TRUE16-NEXT:    s_mov_b64 s[2:3], 0
+; GFX1264-TRUE16-NEXT:  .LBB18_1: ; %atomicrmw.start
+; GFX1264-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1264-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s9, v1
+; GFX1264-TRUE16-NEXT:    v_add_f16_e32 v0.l, s8, v0.l
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1264-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1264-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, s9, v0
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1264-TRUE16-NEXT:    v_and_or_b32 v0, v1, s10, v0
+; GFX1264-TRUE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX1264-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX1264-TRUE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1264-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1264-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1264-TRUE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1264-TRUE16-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1264-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1264-TRUE16-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
+; GFX1264-TRUE16-NEXT:    s_cbranch_execnz .LBB18_1
+; GFX1264-TRUE16-NEXT:  ; %bb.2: ; %atomicrmw.end
+; GFX1264-TRUE16-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX1264-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s9, v2
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1264-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], null
+; GFX1264-TRUE16-NEXT:    s_endpgm
+;
+; GFX1264-FAKE16-LABEL: uniform_fadd_f16:
+; GFX1264-FAKE16:       ; %bb.0:
+; GFX1264-FAKE16-NEXT:    s_clause 0x1
+; GFX1264-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1264-FAKE16-NEXT:    s_load_b32 s8, s[4:5], 0x34
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s6, -1
+; GFX1264-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-FAKE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s5, s3
+; GFX1264-FAKE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1264-FAKE16-NEXT:    s_load_b32 s3, s[4:5], 0x0
+; GFX1264-FAKE16-NEXT:    s_lshl_b32 s9, s2, 3
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1264-FAKE16-NEXT:    s_lshl_b32 s2, 0xffff, s9
+; GFX1264-FAKE16-NEXT:    s_not_b32 s10, s2
+; GFX1264-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-FAKE16-NEXT:    v_mov_b32_e32 v1, s3
+; GFX1264-FAKE16-NEXT:    s_mov_b64 s[2:3], 0
+; GFX1264-FAKE16-NEXT:  .LBB18_1: ; %atomicrmw.start
+; GFX1264-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1264-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s9, v1
+; GFX1264-FAKE16-NEXT:    v_add_f16_e32 v0, s8, v0
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1264-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1264-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, s9, v0
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1264-FAKE16-NEXT:    v_and_or_b32 v0, v1, s10, v0
+; GFX1264-FAKE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX1264-FAKE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX1264-FAKE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1264-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1264-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1264-FAKE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1264-FAKE16-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1264-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1264-FAKE16-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
+; GFX1264-FAKE16-NEXT:    s_cbranch_execnz .LBB18_1
+; GFX1264-FAKE16-NEXT:  ; %bb.2: ; %atomicrmw.end
+; GFX1264-FAKE16-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX1264-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s9, v2
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1264-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], null
+; GFX1264-FAKE16-NEXT:    s_endpgm
+;
+; GFX1232-TRUE16-LABEL: uniform_fadd_f16:
+; GFX1232-TRUE16:       ; %bb.0:
+; GFX1232-TRUE16-NEXT:    s_clause 0x1
+; GFX1232-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1232-TRUE16-NEXT:    s_load_b32 s8, s[4:5], 0x34
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s9, 0
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1232-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-TRUE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s5, s3
+; GFX1232-TRUE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1232-TRUE16-NEXT:    s_load_b32 s6, s[4:5], 0x0
+; GFX1232-TRUE16-NEXT:    s_lshl_b32 s2, s2, 3
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1232-TRUE16-NEXT:    s_lshl_b32 s3, 0xffff, s2
+; GFX1232-TRUE16-NEXT:    s_not_b32 s3, s3
+; GFX1232-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-TRUE16-NEXT:    v_mov_b32_e32 v1, s6
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s6, -1
+; GFX1232-TRUE16-NEXT:  .LBB18_1: ; %atomicrmw.start
+; GFX1232-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1232-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s2, v1
+; GFX1232-TRUE16-NEXT:    v_add_f16_e32 v0.l, s8, v0.l
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1232-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1232-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, s2, v0
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1232-TRUE16-NEXT:    v_and_or_b32 v0, v1, s3, v0
+; GFX1232-TRUE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1232-TRUE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1232-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1232-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1232-TRUE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1232-TRUE16-NEXT:    s_or_b32 s9, vcc_lo, s9
+; GFX1232-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1232-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s9
+; GFX1232-TRUE16-NEXT:    s_cbranch_execnz .LBB18_1
+; GFX1232-TRUE16-NEXT:  ; %bb.2: ; %atomicrmw.end
+; GFX1232-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s9
+; GFX1232-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s2, v2
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1232-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], null
+; GFX1232-TRUE16-NEXT:    s_endpgm
+;
+; GFX1232-FAKE16-LABEL: uniform_fadd_f16:
+; GFX1232-FAKE16:       ; %bb.0:
+; GFX1232-FAKE16-NEXT:    s_clause 0x1
+; GFX1232-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1232-FAKE16-NEXT:    s_load_b32 s8, s[4:5], 0x34
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s9, 0
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1232-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-FAKE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s5, s3
+; GFX1232-FAKE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1232-FAKE16-NEXT:    s_load_b32 s6, s[4:5], 0x0
+; GFX1232-FAKE16-NEXT:    s_lshl_b32 s2, s2, 3
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1232-FAKE16-NEXT:    s_lshl_b32 s3, 0xffff, s2
+; GFX1232-FAKE16-NEXT:    s_not_b32 s3, s3
+; GFX1232-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-FAKE16-NEXT:    v_mov_b32_e32 v1, s6
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s6, -1
+; GFX1232-FAKE16-NEXT:  .LBB18_1: ; %atomicrmw.start
+; GFX1232-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1232-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s2, v1
+; GFX1232-FAKE16-NEXT:    v_add_f16_e32 v0, s8, v0
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1232-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1232-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, s2, v0
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1232-FAKE16-NEXT:    v_and_or_b32 v0, v1, s3, v0
+; GFX1232-FAKE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1232-FAKE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1232-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1232-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1232-FAKE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1232-FAKE16-NEXT:    s_or_b32 s9, vcc_lo, s9
+; GFX1232-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1232-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s9
+; GFX1232-FAKE16-NEXT:    s_cbranch_execnz .LBB18_1
+; GFX1232-FAKE16-NEXT:  ; %bb.2: ; %atomicrmw.end
+; GFX1232-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s9
+; GFX1232-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s2, v2
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1232-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], null
+; GFX1232-FAKE16-NEXT:    s_endpgm
   %rmw = atomicrmw fadd ptr addrspace(1) %uniform.ptr, half %val monotonic, align 2
   store half %rmw, ptr addrspace(1) %result
   ret void
@@ -10291,227 +11333,453 @@ define amdgpu_kernel void @uniform_fadd_bf16(ptr addrspace(1) %result, ptr addrs
 ; GFX1032-NEXT:    buffer_store_short v0, off, s[0:3], 0
 ; GFX1032-NEXT:    s_endpgm
 ;
-; GFX1164-LABEL: uniform_fadd_bf16:
-; GFX1164:       ; %bb.0:
-; GFX1164-NEXT:    s_clause 0x1
-; GFX1164-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1164-NEXT:    s_load_b32 s6, s[4:5], 0x34
-; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_and_b32 s4, s2, -4
-; GFX1164-NEXT:    s_mov_b32 s5, s3
-; GFX1164-NEXT:    s_and_b32 s2, s2, 3
-; GFX1164-NEXT:    s_load_b32 s7, s[4:5], 0x0
-; GFX1164-NEXT:    s_lshl_b32 s8, s2, 3
-; GFX1164-NEXT:    s_lshl_b32 s10, s6, 16
-; GFX1164-NEXT:    s_lshl_b32 s2, 0xffff, s8
-; GFX1164-NEXT:    s_mov_b32 s6, -1
-; GFX1164-NEXT:    s_not_b32 s9, s2
-; GFX1164-NEXT:    s_mov_b64 s[2:3], 0
-; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    v_mov_b32_e32 v1, s7
-; GFX1164-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1164-NEXT:    .p2align 6
-; GFX1164-NEXT:  .LBB19_1: ; %atomicrmw.start
-; GFX1164-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1164-NEXT:    v_lshrrev_b32_e32 v0, s8, v1
-; GFX1164-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1164-NEXT:    v_add_f32_e32 v0, s10, v0
-; GFX1164-NEXT:    v_bfe_u32 v2, v0, 16, 1
-; GFX1164-NEXT:    v_or_b32_e32 v3, 0x400000, v0
-; GFX1164-NEXT:    v_cmp_u_f32_e32 vcc, v0, v0
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1164-NEXT:    v_add3_u32 v2, v2, v0, 0x7fff
-; GFX1164-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1164-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
-; GFX1164-NEXT:    v_lshlrev_b32_e32 v0, s8, v0
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1164-NEXT:    v_and_or_b32 v0, v1, s9, v0
-; GFX1164-NEXT:    v_mov_b32_e32 v3, v1
-; GFX1164-NEXT:    v_mov_b32_e32 v2, v0
-; GFX1164-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
-; GFX1164-NEXT:    s_waitcnt vmcnt(0)
-; GFX1164-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
-; GFX1164-NEXT:    v_mov_b32_e32 v1, v2
-; GFX1164-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
-; GFX1164-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
-; GFX1164-NEXT:    s_cbranch_execnz .LBB19_1
-; GFX1164-NEXT:  ; %bb.2: ; %atomicrmw.end
-; GFX1164-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX1164-NEXT:    v_lshrrev_b32_e32 v0, s8, v2
-; GFX1164-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX1164-NEXT:    s_mov_b32 s2, -1
-; GFX1164-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
-; GFX1164-NEXT:    s_endpgm
-;
-; GFX1132-LABEL: uniform_fadd_bf16:
-; GFX1132:       ; %bb.0:
-; GFX1132-NEXT:    s_clause 0x1
-; GFX1132-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1132-NEXT:    s_load_b32 s6, s[4:5], 0x34
-; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_and_b32 s4, s2, -4
-; GFX1132-NEXT:    s_mov_b32 s5, s3
-; GFX1132-NEXT:    s_and_b32 s2, s2, 3
-; GFX1132-NEXT:    s_load_b32 s7, s[4:5], 0x0
-; GFX1132-NEXT:    s_lshl_b32 s2, s2, 3
-; GFX1132-NEXT:    s_lshl_b32 s9, s6, 16
-; GFX1132-NEXT:    s_lshl_b32 s3, 0xffff, s2
-; GFX1132-NEXT:    s_mov_b32 s6, -1
-; GFX1132-NEXT:    s_not_b32 s8, s3
-; GFX1132-NEXT:    s_mov_b32 s3, 0
-; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    v_mov_b32_e32 v1, s7
-; GFX1132-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1132-NEXT:    .p2align 6
-; GFX1132-NEXT:  .LBB19_1: ; %atomicrmw.start
-; GFX1132-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1132-NEXT:    v_lshrrev_b32_e32 v0, s2, v1
-; GFX1132-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1132-NEXT:    v_add_f32_e32 v0, s9, v0
-; GFX1132-NEXT:    v_bfe_u32 v2, v0, 16, 1
-; GFX1132-NEXT:    v_or_b32_e32 v3, 0x400000, v0
-; GFX1132-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1132-NEXT:    v_add3_u32 v2, v2, v0, 0x7fff
-; GFX1132-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc_lo
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1132-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
-; GFX1132-NEXT:    v_lshlrev_b32_e32 v0, s2, v0
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1132-NEXT:    v_and_or_b32 v0, v1, s8, v0
-; GFX1132-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
-; GFX1132-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
-; GFX1132-NEXT:    s_waitcnt vmcnt(0)
-; GFX1132-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
-; GFX1132-NEXT:    v_mov_b32_e32 v1, v2
-; GFX1132-NEXT:    s_or_b32 s3, vcc_lo, s3
-; GFX1132-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s3
-; GFX1132-NEXT:    s_cbranch_execnz .LBB19_1
-; GFX1132-NEXT:  ; %bb.2: ; %atomicrmw.end
-; GFX1132-NEXT:    s_or_b32 exec_lo, exec_lo, s3
-; GFX1132-NEXT:    v_lshrrev_b32_e32 v0, s2, v2
-; GFX1132-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX1132-NEXT:    s_mov_b32 s2, -1
-; GFX1132-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
-; GFX1132-NEXT:    s_endpgm
-;
-; GFX1264-LABEL: uniform_fadd_bf16:
-; GFX1264:       ; %bb.0:
-; GFX1264-NEXT:    s_clause 0x1
-; GFX1264-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1264-NEXT:    s_load_b32 s6, s[4:5], 0x34
-; GFX1264-NEXT:    s_wait_kmcnt 0x0
-; GFX1264-NEXT:    s_and_b32 s4, s2, -4
-; GFX1264-NEXT:    s_mov_b32 s5, s3
-; GFX1264-NEXT:    s_and_b32 s2, s2, 3
-; GFX1264-NEXT:    s_load_b32 s7, s[4:5], 0x0
-; GFX1264-NEXT:    s_lshl_b32 s8, s2, 3
-; GFX1264-NEXT:    s_lshl_b32 s10, s6, 16
-; GFX1264-NEXT:    s_lshl_b32 s2, 0xffff, s8
-; GFX1264-NEXT:    s_mov_b32 s6, -1
-; GFX1264-NEXT:    s_not_b32 s9, s2
-; GFX1264-NEXT:    s_mov_b64 s[2:3], 0
-; GFX1264-NEXT:    s_wait_kmcnt 0x0
-; GFX1264-NEXT:    v_mov_b32_e32 v1, s7
-; GFX1264-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1264-NEXT:  .LBB19_1: ; %atomicrmw.start
-; GFX1264-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX1264-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1264-NEXT:    v_lshrrev_b32_e32 v0, s8, v1
-; GFX1264-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
-; GFX1264-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1264-NEXT:    v_add_f32_e32 v0, s10, v0
-; GFX1264-NEXT:    v_bfe_u32 v2, v0, 16, 1
-; GFX1264-NEXT:    v_or_b32_e32 v3, 0x400000, v0
-; GFX1264-NEXT:    v_cmp_u_f32_e32 vcc, v0, v0
-; GFX1264-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1264-NEXT:    v_add3_u32 v2, v2, v0, 0x7fff
-; GFX1264-NEXT:    s_wait_alu 0xfffd
-; GFX1264-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc
-; GFX1264-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1264-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
-; GFX1264-NEXT:    v_lshlrev_b32_e32 v0, s8, v0
-; GFX1264-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1264-NEXT:    v_and_or_b32 v0, v1, s9, v0
-; GFX1264-NEXT:    v_mov_b32_e32 v3, v1
-; GFX1264-NEXT:    v_mov_b32_e32 v2, v0
-; GFX1264-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
-; GFX1264-NEXT:    s_wait_loadcnt 0x0
-; GFX1264-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
-; GFX1264-NEXT:    v_mov_b32_e32 v1, v2
-; GFX1264-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
-; GFX1264-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1264-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
-; GFX1264-NEXT:    s_cbranch_execnz .LBB19_1
-; GFX1264-NEXT:  ; %bb.2: ; %atomicrmw.end
-; GFX1264-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX1264-NEXT:    v_lshrrev_b32_e32 v0, s8, v2
-; GFX1264-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX1264-NEXT:    s_mov_b32 s2, -1
-; GFX1264-NEXT:    buffer_store_b16 v0, off, s[0:3], null
-; GFX1264-NEXT:    s_endpgm
-;
-; GFX1232-LABEL: uniform_fadd_bf16:
-; GFX1232:       ; %bb.0:
-; GFX1232-NEXT:    s_clause 0x1
-; GFX1232-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1232-NEXT:    s_load_b32 s6, s[4:5], 0x34
-; GFX1232-NEXT:    s_wait_kmcnt 0x0
-; GFX1232-NEXT:    s_and_b32 s4, s2, -4
-; GFX1232-NEXT:    s_mov_b32 s5, s3
-; GFX1232-NEXT:    s_and_b32 s2, s2, 3
-; GFX1232-NEXT:    s_load_b32 s7, s[4:5], 0x0
-; GFX1232-NEXT:    s_lshl_b32 s2, s2, 3
-; GFX1232-NEXT:    s_lshl_b32 s9, s6, 16
-; GFX1232-NEXT:    s_lshl_b32 s3, 0xffff, s2
-; GFX1232-NEXT:    s_mov_b32 s6, -1
-; GFX1232-NEXT:    s_not_b32 s8, s3
-; GFX1232-NEXT:    s_mov_b32 s3, 0
-; GFX1232-NEXT:    s_wait_kmcnt 0x0
-; GFX1232-NEXT:    v_mov_b32_e32 v1, s7
-; GFX1232-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1232-NEXT:  .LBB19_1: ; %atomicrmw.start
-; GFX1232-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX1232-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1232-NEXT:    v_lshrrev_b32_e32 v0, s2, v1
-; GFX1232-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
-; GFX1232-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1232-NEXT:    v_add_f32_e32 v0, s9, v0
-; GFX1232-NEXT:    v_bfe_u32 v2, v0, 16, 1
-; GFX1232-NEXT:    v_or_b32_e32 v3, 0x400000, v0
-; GFX1232-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX1232-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1232-NEXT:    v_add3_u32 v2, v2, v0, 0x7fff
-; GFX1232-NEXT:    s_wait_alu 0xfffd
-; GFX1232-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc_lo
-; GFX1232-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1232-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
-; GFX1232-NEXT:    v_lshlrev_b32_e32 v0, s2, v0
-; GFX1232-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1232-NEXT:    v_and_or_b32 v0, v1, s8, v0
-; GFX1232-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
-; GFX1232-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
-; GFX1232-NEXT:    s_wait_loadcnt 0x0
-; GFX1232-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
-; GFX1232-NEXT:    v_mov_b32_e32 v1, v2
-; GFX1232-NEXT:    s_or_b32 s3, vcc_lo, s3
-; GFX1232-NEXT:    s_wait_alu 0xfffe
-; GFX1232-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s3
-; GFX1232-NEXT:    s_cbranch_execnz .LBB19_1
-; GFX1232-NEXT:  ; %bb.2: ; %atomicrmw.end
-; GFX1232-NEXT:    s_or_b32 exec_lo, exec_lo, s3
-; GFX1232-NEXT:    v_lshrrev_b32_e32 v0, s2, v2
-; GFX1232-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX1232-NEXT:    s_mov_b32 s2, -1
-; GFX1232-NEXT:    buffer_store_b16 v0, off, s[0:3], null
-; GFX1232-NEXT:    s_endpgm
+; GFX1164-TRUE16-LABEL: uniform_fadd_bf16:
+; GFX1164-TRUE16:       ; %bb.0:
+; GFX1164-TRUE16-NEXT:    s_clause 0x1
+; GFX1164-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1164-TRUE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; GFX1164-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-TRUE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s5, s3
+; GFX1164-TRUE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1164-TRUE16-NEXT:    s_load_b32 s7, s[4:5], 0x0
+; GFX1164-TRUE16-NEXT:    s_lshl_b32 s8, s2, 3
+; GFX1164-TRUE16-NEXT:    s_lshl_b32 s10, s6, 16
+; GFX1164-TRUE16-NEXT:    s_lshl_b32 s2, 0xffff, s8
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s6, -1
+; GFX1164-TRUE16-NEXT:    s_not_b32 s9, s2
+; GFX1164-TRUE16-NEXT:    s_mov_b64 s[2:3], 0
+; GFX1164-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-TRUE16-NEXT:    v_mov_b32_e32 v1, s7
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1164-TRUE16-NEXT:    .p2align 6
+; GFX1164-TRUE16-NEXT:  .LBB19_1: ; %atomicrmw.start
+; GFX1164-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s8, v1
+; GFX1164-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164-TRUE16-NEXT:    v_add_f32_e32 v0, s10, v0
+; GFX1164-TRUE16-NEXT:    v_bfe_u32 v2, v0, 16, 1
+; GFX1164-TRUE16-NEXT:    v_or_b32_e32 v3, 0x400000, v0
+; GFX1164-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc, v0, v0
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164-TRUE16-NEXT:    v_add3_u32 v2, v2, v0, 0x7fff
+; GFX1164-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc
+; GFX1164-TRUE16-NEXT:    v_mov_b16_e32 v2.h, 0
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.h
+; GFX1164-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, s8, v2
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1164-TRUE16-NEXT:    v_and_or_b32 v0, v1, s9, v0
+; GFX1164-TRUE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX1164-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX1164-TRUE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
+; GFX1164-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1164-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1164-TRUE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1164-TRUE16-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164-TRUE16-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
+; GFX1164-TRUE16-NEXT:    s_cbranch_execnz .LBB19_1
+; GFX1164-TRUE16-NEXT:  ; %bb.2: ; %atomicrmw.end
+; GFX1164-TRUE16-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX1164-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s8, v2
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1164-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX1164-TRUE16-NEXT:    s_endpgm
+;
+; GFX1164-FAKE16-LABEL: uniform_fadd_bf16:
+; GFX1164-FAKE16:       ; %bb.0:
+; GFX1164-FAKE16-NEXT:    s_clause 0x1
+; GFX1164-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1164-FAKE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; GFX1164-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-FAKE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s5, s3
+; GFX1164-FAKE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1164-FAKE16-NEXT:    s_load_b32 s7, s[4:5], 0x0
+; GFX1164-FAKE16-NEXT:    s_lshl_b32 s8, s2, 3
+; GFX1164-FAKE16-NEXT:    s_lshl_b32 s10, s6, 16
+; GFX1164-FAKE16-NEXT:    s_lshl_b32 s2, 0xffff, s8
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s6, -1
+; GFX1164-FAKE16-NEXT:    s_not_b32 s9, s2
+; GFX1164-FAKE16-NEXT:    s_mov_b64 s[2:3], 0
+; GFX1164-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-FAKE16-NEXT:    v_mov_b32_e32 v1, s7
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1164-FAKE16-NEXT:    .p2align 6
+; GFX1164-FAKE16-NEXT:  .LBB19_1: ; %atomicrmw.start
+; GFX1164-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s8, v1
+; GFX1164-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164-FAKE16-NEXT:    v_add_f32_e32 v0, s10, v0
+; GFX1164-FAKE16-NEXT:    v_bfe_u32 v2, v0, 16, 1
+; GFX1164-FAKE16-NEXT:    v_or_b32_e32 v3, 0x400000, v0
+; GFX1164-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc, v0, v0
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164-FAKE16-NEXT:    v_add3_u32 v2, v2, v0, 0x7fff
+; GFX1164-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX1164-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, s8, v0
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1164-FAKE16-NEXT:    v_and_or_b32 v0, v1, s9, v0
+; GFX1164-FAKE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX1164-FAKE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX1164-FAKE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
+; GFX1164-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1164-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1164-FAKE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1164-FAKE16-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164-FAKE16-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
+; GFX1164-FAKE16-NEXT:    s_cbranch_execnz .LBB19_1
+; GFX1164-FAKE16-NEXT:  ; %bb.2: ; %atomicrmw.end
+; GFX1164-FAKE16-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX1164-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s8, v2
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1164-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX1164-FAKE16-NEXT:    s_endpgm
+;
+; GFX1132-TRUE16-LABEL: uniform_fadd_bf16:
+; GFX1132-TRUE16:       ; %bb.0:
+; GFX1132-TRUE16-NEXT:    s_clause 0x1
+; GFX1132-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1132-TRUE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; GFX1132-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-TRUE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s5, s3
+; GFX1132-TRUE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1132-TRUE16-NEXT:    s_load_b32 s7, s[4:5], 0x0
+; GFX1132-TRUE16-NEXT:    s_lshl_b32 s2, s2, 3
+; GFX1132-TRUE16-NEXT:    s_lshl_b32 s9, s6, 16
+; GFX1132-TRUE16-NEXT:    s_lshl_b32 s3, 0xffff, s2
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s6, -1
+; GFX1132-TRUE16-NEXT:    s_not_b32 s8, s3
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s3, 0
+; GFX1132-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-TRUE16-NEXT:    v_mov_b32_e32 v1, s7
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1132-TRUE16-NEXT:    .p2align 6
+; GFX1132-TRUE16-NEXT:  .LBB19_1: ; %atomicrmw.start
+; GFX1132-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s2, v1
+; GFX1132-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132-TRUE16-NEXT:    v_add_f32_e32 v0, s9, v0
+; GFX1132-TRUE16-NEXT:    v_bfe_u32 v2, v0, 16, 1
+; GFX1132-TRUE16-NEXT:    v_or_b32_e32 v3, 0x400000, v0
+; GFX1132-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132-TRUE16-NEXT:    v_add3_u32 v2, v2, v0, 0x7fff
+; GFX1132-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc_lo
+; GFX1132-TRUE16-NEXT:    v_mov_b16_e32 v2.h, 0
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.h
+; GFX1132-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, s2, v2
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132-TRUE16-NEXT:    v_and_or_b32 v0, v1, s8, v0
+; GFX1132-TRUE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1132-TRUE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
+; GFX1132-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1132-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1132-TRUE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1132-TRUE16-NEXT:    s_or_b32 s3, vcc_lo, s3
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s3
+; GFX1132-TRUE16-NEXT:    s_cbranch_execnz .LBB19_1
+; GFX1132-TRUE16-NEXT:  ; %bb.2: ; %atomicrmw.end
+; GFX1132-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s3
+; GFX1132-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s2, v2
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1132-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX1132-TRUE16-NEXT:    s_endpgm
+;
+; GFX1132-FAKE16-LABEL: uniform_fadd_bf16:
+; GFX1132-FAKE16:       ; %bb.0:
+; GFX1132-FAKE16-NEXT:    s_clause 0x1
+; GFX1132-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1132-FAKE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; GFX1132-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-FAKE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s5, s3
+; GFX1132-FAKE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1132-FAKE16-NEXT:    s_load_b32 s7, s[4:5], 0x0
+; GFX1132-FAKE16-NEXT:    s_lshl_b32 s2, s2, 3
+; GFX1132-FAKE16-NEXT:    s_lshl_b32 s9, s6, 16
+; GFX1132-FAKE16-NEXT:    s_lshl_b32 s3, 0xffff, s2
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s6, -1
+; GFX1132-FAKE16-NEXT:    s_not_b32 s8, s3
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s3, 0
+; GFX1132-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-FAKE16-NEXT:    v_mov_b32_e32 v1, s7
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1132-FAKE16-NEXT:    .p2align 6
+; GFX1132-FAKE16-NEXT:  .LBB19_1: ; %atomicrmw.start
+; GFX1132-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s2, v1
+; GFX1132-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132-FAKE16-NEXT:    v_add_f32_e32 v0, s9, v0
+; GFX1132-FAKE16-NEXT:    v_bfe_u32 v2, v0, 16, 1
+; GFX1132-FAKE16-NEXT:    v_or_b32_e32 v3, 0x400000, v0
+; GFX1132-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132-FAKE16-NEXT:    v_add3_u32 v2, v2, v0, 0x7fff
+; GFX1132-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc_lo
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX1132-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, s2, v0
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132-FAKE16-NEXT:    v_and_or_b32 v0, v1, s8, v0
+; GFX1132-FAKE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1132-FAKE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
+; GFX1132-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1132-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1132-FAKE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1132-FAKE16-NEXT:    s_or_b32 s3, vcc_lo, s3
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s3
+; GFX1132-FAKE16-NEXT:    s_cbranch_execnz .LBB19_1
+; GFX1132-FAKE16-NEXT:  ; %bb.2: ; %atomicrmw.end
+; GFX1132-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s3
+; GFX1132-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s2, v2
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1132-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX1132-FAKE16-NEXT:    s_endpgm
+;
+; GFX1264-TRUE16-LABEL: uniform_fadd_bf16:
+; GFX1264-TRUE16:       ; %bb.0:
+; GFX1264-TRUE16-NEXT:    s_clause 0x1
+; GFX1264-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1264-TRUE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; GFX1264-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-TRUE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s5, s3
+; GFX1264-TRUE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1264-TRUE16-NEXT:    s_load_b32 s7, s[4:5], 0x0
+; GFX1264-TRUE16-NEXT:    s_lshl_b32 s8, s2, 3
+; GFX1264-TRUE16-NEXT:    s_lshl_b32 s10, s6, 16
+; GFX1264-TRUE16-NEXT:    s_lshl_b32 s2, 0xffff, s8
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s6, -1
+; GFX1264-TRUE16-NEXT:    s_not_b32 s9, s2
+; GFX1264-TRUE16-NEXT:    s_mov_b64 s[2:3], 0
+; GFX1264-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-TRUE16-NEXT:    v_mov_b32_e32 v1, s7
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1264-TRUE16-NEXT:  .LBB19_1: ; %atomicrmw.start
+; GFX1264-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1264-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s8, v1
+; GFX1264-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1264-TRUE16-NEXT:    v_add_f32_e32 v0, s10, v0
+; GFX1264-TRUE16-NEXT:    v_bfe_u32 v2, v0, 16, 1
+; GFX1264-TRUE16-NEXT:    v_or_b32_e32 v3, 0x400000, v0
+; GFX1264-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc, v0, v0
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1264-TRUE16-NEXT:    v_add3_u32 v2, v2, v0, 0x7fff
+; GFX1264-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX1264-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc
+; GFX1264-TRUE16-NEXT:    v_mov_b16_e32 v2.h, 0
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1264-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.h
+; GFX1264-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, s8, v2
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1264-TRUE16-NEXT:    v_and_or_b32 v0, v1, s9, v0
+; GFX1264-TRUE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX1264-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX1264-TRUE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1264-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1264-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1264-TRUE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1264-TRUE16-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1264-TRUE16-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
+; GFX1264-TRUE16-NEXT:    s_cbranch_execnz .LBB19_1
+; GFX1264-TRUE16-NEXT:  ; %bb.2: ; %atomicrmw.end
+; GFX1264-TRUE16-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX1264-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s8, v2
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1264-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], null
+; GFX1264-TRUE16-NEXT:    s_endpgm
+;
+; GFX1264-FAKE16-LABEL: uniform_fadd_bf16:
+; GFX1264-FAKE16:       ; %bb.0:
+; GFX1264-FAKE16-NEXT:    s_clause 0x1
+; GFX1264-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1264-FAKE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; GFX1264-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-FAKE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s5, s3
+; GFX1264-FAKE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1264-FAKE16-NEXT:    s_load_b32 s7, s[4:5], 0x0
+; GFX1264-FAKE16-NEXT:    s_lshl_b32 s8, s2, 3
+; GFX1264-FAKE16-NEXT:    s_lshl_b32 s10, s6, 16
+; GFX1264-FAKE16-NEXT:    s_lshl_b32 s2, 0xffff, s8
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s6, -1
+; GFX1264-FAKE16-NEXT:    s_not_b32 s9, s2
+; GFX1264-FAKE16-NEXT:    s_mov_b64 s[2:3], 0
+; GFX1264-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-FAKE16-NEXT:    v_mov_b32_e32 v1, s7
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1264-FAKE16-NEXT:  .LBB19_1: ; %atomicrmw.start
+; GFX1264-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1264-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s8, v1
+; GFX1264-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1264-FAKE16-NEXT:    v_add_f32_e32 v0, s10, v0
+; GFX1264-FAKE16-NEXT:    v_bfe_u32 v2, v0, 16, 1
+; GFX1264-FAKE16-NEXT:    v_or_b32_e32 v3, 0x400000, v0
+; GFX1264-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc, v0, v0
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1264-FAKE16-NEXT:    v_add3_u32 v2, v2, v0, 0x7fff
+; GFX1264-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX1264-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1264-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX1264-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, s8, v0
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1264-FAKE16-NEXT:    v_and_or_b32 v0, v1, s9, v0
+; GFX1264-FAKE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX1264-FAKE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX1264-FAKE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1264-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1264-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1264-FAKE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1264-FAKE16-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1264-FAKE16-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
+; GFX1264-FAKE16-NEXT:    s_cbranch_execnz .LBB19_1
+; GFX1264-FAKE16-NEXT:  ; %bb.2: ; %atomicrmw.end
+; GFX1264-FAKE16-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX1264-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s8, v2
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1264-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], null
+; GFX1264-FAKE16-NEXT:    s_endpgm
+;
+; GFX1232-TRUE16-LABEL: uniform_fadd_bf16:
+; GFX1232-TRUE16:       ; %bb.0:
+; GFX1232-TRUE16-NEXT:    s_clause 0x1
+; GFX1232-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1232-TRUE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; GFX1232-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-TRUE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s5, s3
+; GFX1232-TRUE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1232-TRUE16-NEXT:    s_load_b32 s7, s[4:5], 0x0
+; GFX1232-TRUE16-NEXT:    s_lshl_b32 s2, s2, 3
+; GFX1232-TRUE16-NEXT:    s_lshl_b32 s9, s6, 16
+; GFX1232-TRUE16-NEXT:    s_lshl_b32 s3, 0xffff, s2
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s6, -1
+; GFX1232-TRUE16-NEXT:    s_not_b32 s8, s3
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s3, 0
+; GFX1232-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-TRUE16-NEXT:    v_mov_b32_e32 v1, s7
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1232-TRUE16-NEXT:  .LBB19_1: ; %atomicrmw.start
+; GFX1232-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1232-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s2, v1
+; GFX1232-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1232-TRUE16-NEXT:    v_add_f32_e32 v0, s9, v0
+; GFX1232-TRUE16-NEXT:    v_bfe_u32 v2, v0, 16, 1
+; GFX1232-TRUE16-NEXT:    v_or_b32_e32 v3, 0x400000, v0
+; GFX1232-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1232-TRUE16-NEXT:    v_add3_u32 v2, v2, v0, 0x7fff
+; GFX1232-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX1232-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc_lo
+; GFX1232-TRUE16-NEXT:    v_mov_b16_e32 v2.h, 0
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1232-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.h
+; GFX1232-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, s2, v2
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1232-TRUE16-NEXT:    v_and_or_b32 v0, v1, s8, v0
+; GFX1232-TRUE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1232-TRUE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1232-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1232-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1232-TRUE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1232-TRUE16-NEXT:    s_or_b32 s3, vcc_lo, s3
+; GFX1232-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1232-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s3
+; GFX1232-TRUE16-NEXT:    s_cbranch_execnz .LBB19_1
+; GFX1232-TRUE16-NEXT:  ; %bb.2: ; %atomicrmw.end
+; GFX1232-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s3
+; GFX1232-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, s2, v2
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1232-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], null
+; GFX1232-TRUE16-NEXT:    s_endpgm
+;
+; GFX1232-FAKE16-LABEL: uniform_fadd_bf16:
+; GFX1232-FAKE16:       ; %bb.0:
+; GFX1232-FAKE16-NEXT:    s_clause 0x1
+; GFX1232-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1232-FAKE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; GFX1232-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-FAKE16-NEXT:    s_and_b32 s4, s2, -4
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s5, s3
+; GFX1232-FAKE16-NEXT:    s_and_b32 s2, s2, 3
+; GFX1232-FAKE16-NEXT:    s_load_b32 s7, s[4:5], 0x0
+; GFX1232-FAKE16-NEXT:    s_lshl_b32 s2, s2, 3
+; GFX1232-FAKE16-NEXT:    s_lshl_b32 s9, s6, 16
+; GFX1232-FAKE16-NEXT:    s_lshl_b32 s3, 0xffff, s2
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s6, -1
+; GFX1232-FAKE16-NEXT:    s_not_b32 s8, s3
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s3, 0
+; GFX1232-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-FAKE16-NEXT:    v_mov_b32_e32 v1, s7
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1232-FAKE16-NEXT:  .LBB19_1: ; %atomicrmw.start
+; GFX1232-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1232-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s2, v1
+; GFX1232-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1232-FAKE16-NEXT:    v_add_f32_e32 v0, s9, v0
+; GFX1232-FAKE16-NEXT:    v_bfe_u32 v2, v0, 16, 1
+; GFX1232-FAKE16-NEXT:    v_or_b32_e32 v3, 0x400000, v0
+; GFX1232-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1232-FAKE16-NEXT:    v_add3_u32 v2, v2, v0, 0x7fff
+; GFX1232-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX1232-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc_lo
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1232-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX1232-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, s2, v0
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1232-FAKE16-NEXT:    v_and_or_b32 v0, v1, s8, v0
+; GFX1232-FAKE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1232-FAKE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1232-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1232-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1232-FAKE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1232-FAKE16-NEXT:    s_or_b32 s3, vcc_lo, s3
+; GFX1232-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1232-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s3
+; GFX1232-FAKE16-NEXT:    s_cbranch_execnz .LBB19_1
+; GFX1232-FAKE16-NEXT:  ; %bb.2: ; %atomicrmw.end
+; GFX1232-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s3
+; GFX1232-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, s2, v2
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1232-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], null
+; GFX1232-FAKE16-NEXT:    s_endpgm
   %rmw = atomicrmw fadd ptr addrspace(1) %uniform.ptr, bfloat %val monotonic, align 2
   store bfloat %rmw, ptr addrspace(1) %result
   ret void
@@ -11109,232 +12377,483 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
 ; GFX1032-NEXT:    buffer_store_dword v2, off, s[8:11], 0
 ; GFX1032-NEXT:    s_endpgm
 ;
-; GFX1164-LABEL: uniform_fadd_v2bf16:
-; GFX1164:       ; %bb.0:
-; GFX1164-NEXT:    s_clause 0x1
-; GFX1164-NEXT:    s_load_b128 s[8:11], s[4:5], 0x24
-; GFX1164-NEXT:    s_load_b32 s0, s[4:5], 0x34
-; GFX1164-NEXT:    s_mov_b64 s[2:3], 0
-; GFX1164-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1164-NEXT:    s_mov_b32 s6, -1
-; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    s_load_b32 s1, s[10:11], 0x0
-; GFX1164-NEXT:    s_lshl_b32 s12, s0, 16
-; GFX1164-NEXT:    s_and_b32 s13, s0, 0xffff0000
-; GFX1164-NEXT:    s_mov_b32 s4, s10
-; GFX1164-NEXT:    s_mov_b32 s5, s11
-; GFX1164-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1164-NEXT:    v_mov_b32_e32 v1, s1
-; GFX1164-NEXT:    s_set_inst_prefetch_distance 0x1
-; GFX1164-NEXT:    .p2align 6
-; GFX1164-NEXT:  .LBB21_1: ; %atomicrmw.start
-; GFX1164-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1164-NEXT:    v_lshlrev_b32_e32 v0, 16, v1
-; GFX1164-NEXT:    v_and_b32_e32 v2, 0xffff0000, v1
-; GFX1164-NEXT:    v_add_f32_e32 v0, s12, v0
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1164-NEXT:    v_add_f32_e32 v2, s13, v2
-; GFX1164-NEXT:    v_bfe_u32 v3, v0, 16, 1
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX1164-NEXT:    v_bfe_u32 v4, v2, 16, 1
-; GFX1164-NEXT:    v_or_b32_e32 v5, 0x400000, v0
-; GFX1164-NEXT:    v_or_b32_e32 v6, 0x400000, v2
-; GFX1164-NEXT:    v_cmp_u_f32_e32 vcc, v2, v2
-; GFX1164-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
-; GFX1164-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
-; GFX1164-NEXT:    v_cmp_u_f32_e64 s[0:1], v0, v0
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1164-NEXT:    v_cndmask_b32_e32 v2, v4, v6, vcc
-; GFX1164-NEXT:    v_cndmask_b32_e64 v0, v3, v5, s[0:1]
-; GFX1164-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1164-NEXT:    v_perm_b32 v0, v2, v0, 0x7060302
-; GFX1164-NEXT:    v_mov_b32_e32 v3, v1
-; GFX1164-NEXT:    v_mov_b32_e32 v2, v0
-; GFX1164-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
-; GFX1164-NEXT:    s_waitcnt vmcnt(0)
-; GFX1164-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
-; GFX1164-NEXT:    v_mov_b32_e32 v1, v2
-; GFX1164-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
-; GFX1164-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
-; GFX1164-NEXT:    s_cbranch_execnz .LBB21_1
-; GFX1164-NEXT:  ; %bb.2: ; %atomicrmw.end
-; GFX1164-NEXT:    s_set_inst_prefetch_distance 0x2
-; GFX1164-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX1164-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX1164-NEXT:    s_mov_b32 s10, -1
-; GFX1164-NEXT:    buffer_store_b32 v2, off, s[8:11], 0
-; GFX1164-NEXT:    s_endpgm
-;
-; GFX1132-LABEL: uniform_fadd_v2bf16:
-; GFX1132:       ; %bb.0:
-; GFX1132-NEXT:    s_clause 0x1
-; GFX1132-NEXT:    s_load_b128 s[8:11], s[4:5], 0x24
-; GFX1132-NEXT:    s_load_b32 s0, s[4:5], 0x34
-; GFX1132-NEXT:    s_mov_b32 s1, 0
-; GFX1132-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1132-NEXT:    s_mov_b32 s6, -1
-; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    s_load_b32 s4, s[10:11], 0x0
-; GFX1132-NEXT:    s_lshl_b32 s2, s0, 16
-; GFX1132-NEXT:    s_and_b32 s3, s0, 0xffff0000
-; GFX1132-NEXT:    s_mov_b32 s5, s11
-; GFX1132-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1132-NEXT:    v_mov_b32_e32 v1, s4
-; GFX1132-NEXT:    s_mov_b32 s4, s10
-; GFX1132-NEXT:    s_set_inst_prefetch_distance 0x1
-; GFX1132-NEXT:    .p2align 6
-; GFX1132-NEXT:  .LBB21_1: ; %atomicrmw.start
-; GFX1132-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1132-NEXT:    v_lshlrev_b32_e32 v0, 16, v1
-; GFX1132-NEXT:    v_and_b32_e32 v2, 0xffff0000, v1
-; GFX1132-NEXT:    v_add_f32_e32 v0, s2, v0
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1132-NEXT:    v_add_f32_e32 v2, s3, v2
-; GFX1132-NEXT:    v_bfe_u32 v3, v0, 16, 1
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX1132-NEXT:    v_bfe_u32 v4, v2, 16, 1
-; GFX1132-NEXT:    v_or_b32_e32 v5, 0x400000, v0
-; GFX1132-NEXT:    v_or_b32_e32 v6, 0x400000, v2
-; GFX1132-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX1132-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
-; GFX1132-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
-; GFX1132-NEXT:    v_cmp_u_f32_e64 s0, v0, v0
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1132-NEXT:    v_cndmask_b32_e32 v2, v4, v6, vcc_lo
-; GFX1132-NEXT:    v_cndmask_b32_e64 v0, v3, v5, s0
-; GFX1132-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1132-NEXT:    v_perm_b32 v0, v2, v0, 0x7060302
-; GFX1132-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
-; GFX1132-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
-; GFX1132-NEXT:    s_waitcnt vmcnt(0)
-; GFX1132-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
-; GFX1132-NEXT:    v_mov_b32_e32 v1, v2
-; GFX1132-NEXT:    s_or_b32 s1, vcc_lo, s1
-; GFX1132-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s1
-; GFX1132-NEXT:    s_cbranch_execnz .LBB21_1
-; GFX1132-NEXT:  ; %bb.2: ; %atomicrmw.end
-; GFX1132-NEXT:    s_set_inst_prefetch_distance 0x2
-; GFX1132-NEXT:    s_or_b32 exec_lo, exec_lo, s1
-; GFX1132-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX1132-NEXT:    s_mov_b32 s10, -1
-; GFX1132-NEXT:    buffer_store_b32 v2, off, s[8:11], 0
-; GFX1132-NEXT:    s_endpgm
-;
-; GFX1264-LABEL: uniform_fadd_v2bf16:
-; GFX1264:       ; %bb.0:
-; GFX1264-NEXT:    s_clause 0x1
-; GFX1264-NEXT:    s_load_b128 s[8:11], s[4:5], 0x24
-; GFX1264-NEXT:    s_load_b32 s0, s[4:5], 0x34
-; GFX1264-NEXT:    s_mov_b64 s[2:3], 0
-; GFX1264-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1264-NEXT:    s_mov_b32 s6, -1
-; GFX1264-NEXT:    s_wait_kmcnt 0x0
-; GFX1264-NEXT:    s_load_b32 s1, s[10:11], 0x0
-; GFX1264-NEXT:    s_lshl_b32 s12, s0, 16
-; GFX1264-NEXT:    s_and_b32 s13, s0, 0xffff0000
-; GFX1264-NEXT:    s_mov_b32 s4, s10
-; GFX1264-NEXT:    s_mov_b32 s5, s11
-; GFX1264-NEXT:    s_wait_kmcnt 0x0
-; GFX1264-NEXT:    v_mov_b32_e32 v1, s1
-; GFX1264-NEXT:  .LBB21_1: ; %atomicrmw.start
-; GFX1264-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX1264-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1264-NEXT:    v_lshlrev_b32_e32 v0, 16, v1
-; GFX1264-NEXT:    v_and_b32_e32 v2, 0xffff0000, v1
-; GFX1264-NEXT:    v_add_f32_e32 v0, s12, v0
-; GFX1264-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1264-NEXT:    v_add_f32_e32 v2, s13, v2
-; GFX1264-NEXT:    v_bfe_u32 v3, v0, 16, 1
-; GFX1264-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX1264-NEXT:    v_bfe_u32 v4, v2, 16, 1
-; GFX1264-NEXT:    v_or_b32_e32 v5, 0x400000, v0
-; GFX1264-NEXT:    v_or_b32_e32 v6, 0x400000, v2
-; GFX1264-NEXT:    v_cmp_u_f32_e32 vcc, v2, v2
-; GFX1264-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
-; GFX1264-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
-; GFX1264-NEXT:    v_cmp_u_f32_e64 s[0:1], v0, v0
-; GFX1264-NEXT:    s_wait_alu 0xfffd
-; GFX1264-NEXT:    v_cndmask_b32_e32 v2, v4, v6, vcc
-; GFX1264-NEXT:    s_wait_alu 0xf1ff
-; GFX1264-NEXT:    v_cndmask_b32_e64 v0, v3, v5, s[0:1]
-; GFX1264-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1264-NEXT:    v_perm_b32 v0, v2, v0, 0x7060302
-; GFX1264-NEXT:    v_mov_b32_e32 v3, v1
-; GFX1264-NEXT:    v_mov_b32_e32 v2, v0
-; GFX1264-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
-; GFX1264-NEXT:    s_wait_loadcnt 0x0
-; GFX1264-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
-; GFX1264-NEXT:    v_mov_b32_e32 v1, v2
-; GFX1264-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
-; GFX1264-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1264-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
-; GFX1264-NEXT:    s_cbranch_execnz .LBB21_1
-; GFX1264-NEXT:  ; %bb.2: ; %atomicrmw.end
-; GFX1264-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX1264-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX1264-NEXT:    s_mov_b32 s10, -1
-; GFX1264-NEXT:    buffer_store_b32 v2, off, s[8:11], null
-; GFX1264-NEXT:    s_endpgm
-;
-; GFX1232-LABEL: uniform_fadd_v2bf16:
-; GFX1232:       ; %bb.0:
-; GFX1232-NEXT:    s_clause 0x1
-; GFX1232-NEXT:    s_load_b128 s[8:11], s[4:5], 0x24
-; GFX1232-NEXT:    s_load_b32 s0, s[4:5], 0x34
-; GFX1232-NEXT:    s_mov_b32 s1, 0
-; GFX1232-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1232-NEXT:    s_mov_b32 s6, -1
-; GFX1232-NEXT:    s_wait_kmcnt 0x0
-; GFX1232-NEXT:    s_load_b32 s4, s[10:11], 0x0
-; GFX1232-NEXT:    s_lshl_b32 s2, s0, 16
-; GFX1232-NEXT:    s_and_b32 s3, s0, 0xffff0000
-; GFX1232-NEXT:    s_mov_b32 s5, s11
-; GFX1232-NEXT:    s_wait_kmcnt 0x0
-; GFX1232-NEXT:    v_mov_b32_e32 v1, s4
-; GFX1232-NEXT:    s_mov_b32 s4, s10
-; GFX1232-NEXT:  .LBB21_1: ; %atomicrmw.start
-; GFX1232-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX1232-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1232-NEXT:    v_lshlrev_b32_e32 v0, 16, v1
-; GFX1232-NEXT:    v_and_b32_e32 v2, 0xffff0000, v1
-; GFX1232-NEXT:    v_add_f32_e32 v0, s2, v0
-; GFX1232-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1232-NEXT:    v_add_f32_e32 v2, s3, v2
-; GFX1232-NEXT:    v_bfe_u32 v3, v0, 16, 1
-; GFX1232-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX1232-NEXT:    v_bfe_u32 v4, v2, 16, 1
-; GFX1232-NEXT:    v_or_b32_e32 v5, 0x400000, v0
-; GFX1232-NEXT:    v_or_b32_e32 v6, 0x400000, v2
-; GFX1232-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX1232-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
-; GFX1232-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
-; GFX1232-NEXT:    v_cmp_u_f32_e64 s0, v0, v0
-; GFX1232-NEXT:    s_wait_alu 0xfffd
-; GFX1232-NEXT:    v_cndmask_b32_e32 v2, v4, v6, vcc_lo
-; GFX1232-NEXT:    s_wait_alu 0xf1ff
-; GFX1232-NEXT:    v_cndmask_b32_e64 v0, v3, v5, s0
-; GFX1232-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1232-NEXT:    v_perm_b32 v0, v2, v0, 0x7060302
-; GFX1232-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
-; GFX1232-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
-; GFX1232-NEXT:    s_wait_loadcnt 0x0
-; GFX1232-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
-; GFX1232-NEXT:    v_mov_b32_e32 v1, v2
-; GFX1232-NEXT:    s_or_b32 s1, vcc_lo, s1
-; GFX1232-NEXT:    s_wait_alu 0xfffe
-; GFX1232-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s1
-; GFX1232-NEXT:    s_cbranch_execnz .LBB21_1
-; GFX1232-NEXT:  ; %bb.2: ; %atomicrmw.end
-; GFX1232-NEXT:    s_or_b32 exec_lo, exec_lo, s1
-; GFX1232-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX1232-NEXT:    s_mov_b32 s10, -1
-; GFX1232-NEXT:    buffer_store_b32 v2, off, s[8:11], null
-; GFX1232-NEXT:    s_endpgm
+; GFX1164-TRUE16-LABEL: uniform_fadd_v2bf16:
+; GFX1164-TRUE16:       ; %bb.0:
+; GFX1164-TRUE16-NEXT:    s_clause 0x1
+; GFX1164-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1164-TRUE16-NEXT:    s_load_b32 s4, s[4:5], 0x34
+; GFX1164-TRUE16-NEXT:    s_mov_b64 s[8:9], 0
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s6, -1
+; GFX1164-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-TRUE16-NEXT:    s_load_b32 s5, s[2:3], 0x0
+; GFX1164-TRUE16-NEXT:    s_and_b32 s10, s4, 0xffff0000
+; GFX1164-TRUE16-NEXT:    s_lshl_b32 s11, s4, 16
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s4, s2
+; GFX1164-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-TRUE16-NEXT:    v_mov_b32_e32 v1, s5
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s5, s3
+; GFX1164-TRUE16-NEXT:    s_set_inst_prefetch_distance 0x1
+; GFX1164-TRUE16-NEXT:    .p2align 6
+; GFX1164-TRUE16-NEXT:  .LBB21_1: ; %atomicrmw.start
+; GFX1164-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1164-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v1
+; GFX1164-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v1
+; GFX1164-TRUE16-NEXT:    v_add_f32_e32 v0, s11, v0
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1164-TRUE16-NEXT:    v_add_f32_e32 v2, s10, v2
+; GFX1164-TRUE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1164-TRUE16-NEXT:    v_bfe_u32 v4, v2, 16, 1
+; GFX1164-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX1164-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc, v0, v0
+; GFX1164-TRUE16-NEXT:    v_or_b32_e32 v6, 0x400000, v2
+; GFX1164-TRUE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX1164-TRUE16-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1164-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc
+; GFX1164-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc, v2, v2
+; GFX1164-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v4, v6, vcc
+; GFX1164-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v0, v2
+; GFX1164-TRUE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1164-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX1164-TRUE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
+; GFX1164-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1164-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1164-TRUE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1164-TRUE16-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
+; GFX1164-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164-TRUE16-NEXT:    s_and_not1_b64 exec, exec, s[8:9]
+; GFX1164-TRUE16-NEXT:    s_cbranch_execnz .LBB21_1
+; GFX1164-TRUE16-NEXT:  ; %bb.2: ; %atomicrmw.end
+; GFX1164-TRUE16-NEXT:    s_set_inst_prefetch_distance 0x2
+; GFX1164-TRUE16-NEXT:    s_or_b64 exec, exec, s[8:9]
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1164-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1164-TRUE16-NEXT:    buffer_store_b32 v2, off, s[0:3], 0
+; GFX1164-TRUE16-NEXT:    s_endpgm
+;
+; GFX1164-FAKE16-LABEL: uniform_fadd_v2bf16:
+; GFX1164-FAKE16:       ; %bb.0:
+; GFX1164-FAKE16-NEXT:    s_clause 0x1
+; GFX1164-FAKE16-NEXT:    s_load_b128 s[8:11], s[4:5], 0x24
+; GFX1164-FAKE16-NEXT:    s_load_b32 s0, s[4:5], 0x34
+; GFX1164-FAKE16-NEXT:    s_mov_b64 s[2:3], 0
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s6, -1
+; GFX1164-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-FAKE16-NEXT:    s_load_b32 s1, s[10:11], 0x0
+; GFX1164-FAKE16-NEXT:    s_lshl_b32 s12, s0, 16
+; GFX1164-FAKE16-NEXT:    s_and_b32 s13, s0, 0xffff0000
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s4, s10
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s5, s11
+; GFX1164-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1164-FAKE16-NEXT:    v_mov_b32_e32 v1, s1
+; GFX1164-FAKE16-NEXT:    s_set_inst_prefetch_distance 0x1
+; GFX1164-FAKE16-NEXT:    .p2align 6
+; GFX1164-FAKE16-NEXT:  .LBB21_1: ; %atomicrmw.start
+; GFX1164-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1164-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v1
+; GFX1164-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v1
+; GFX1164-FAKE16-NEXT:    v_add_f32_e32 v0, s12, v0
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1164-FAKE16-NEXT:    v_add_f32_e32 v2, s13, v2
+; GFX1164-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1164-FAKE16-NEXT:    v_bfe_u32 v4, v2, 16, 1
+; GFX1164-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX1164-FAKE16-NEXT:    v_or_b32_e32 v6, 0x400000, v2
+; GFX1164-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc, v2, v2
+; GFX1164-FAKE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX1164-FAKE16-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
+; GFX1164-FAKE16-NEXT:    v_cmp_u_f32_e64 s[0:1], v0, v0
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1164-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v4, v6, vcc
+; GFX1164-FAKE16-NEXT:    v_cndmask_b32_e64 v0, v3, v5, s[0:1]
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1164-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x7060302
+; GFX1164-FAKE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX1164-FAKE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX1164-FAKE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
+; GFX1164-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1164-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1164-FAKE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1164-FAKE16-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1164-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164-FAKE16-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
+; GFX1164-FAKE16-NEXT:    s_cbranch_execnz .LBB21_1
+; GFX1164-FAKE16-NEXT:  ; %bb.2: ; %atomicrmw.end
+; GFX1164-FAKE16-NEXT:    s_set_inst_prefetch_distance 0x2
+; GFX1164-FAKE16-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX1164-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX1164-FAKE16-NEXT:    buffer_store_b32 v2, off, s[8:11], 0
+; GFX1164-FAKE16-NEXT:    s_endpgm
+;
+; GFX1132-TRUE16-LABEL: uniform_fadd_v2bf16:
+; GFX1132-TRUE16:       ; %bb.0:
+; GFX1132-TRUE16-NEXT:    s_clause 0x1
+; GFX1132-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1132-TRUE16-NEXT:    s_load_b32 s4, s[4:5], 0x34
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s8, 0
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s6, -1
+; GFX1132-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-TRUE16-NEXT:    s_load_b32 s5, s[2:3], 0x0
+; GFX1132-TRUE16-NEXT:    s_and_b32 s9, s4, 0xffff0000
+; GFX1132-TRUE16-NEXT:    s_lshl_b32 s10, s4, 16
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s4, s2
+; GFX1132-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-TRUE16-NEXT:    v_mov_b32_e32 v1, s5
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s5, s3
+; GFX1132-TRUE16-NEXT:    s_set_inst_prefetch_distance 0x1
+; GFX1132-TRUE16-NEXT:    .p2align 6
+; GFX1132-TRUE16-NEXT:  .LBB21_1: ; %atomicrmw.start
+; GFX1132-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1132-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v1
+; GFX1132-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v1
+; GFX1132-TRUE16-NEXT:    v_add_f32_e32 v0, s10, v0
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1132-TRUE16-NEXT:    v_add_f32_e32 v2, s9, v2
+; GFX1132-TRUE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1132-TRUE16-NEXT:    v_bfe_u32 v4, v2, 16, 1
+; GFX1132-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX1132-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX1132-TRUE16-NEXT:    v_or_b32_e32 v6, 0x400000, v2
+; GFX1132-TRUE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX1132-TRUE16-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1132-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX1132-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX1132-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v4, v6, vcc_lo
+; GFX1132-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v0, v2
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1132-TRUE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1132-TRUE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
+; GFX1132-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1132-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1132-TRUE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1132-TRUE16-NEXT:    s_or_b32 s8, vcc_lo, s8
+; GFX1132-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s8
+; GFX1132-TRUE16-NEXT:    s_cbranch_execnz .LBB21_1
+; GFX1132-TRUE16-NEXT:  ; %bb.2: ; %atomicrmw.end
+; GFX1132-TRUE16-NEXT:    s_set_inst_prefetch_distance 0x2
+; GFX1132-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s8
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1132-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1132-TRUE16-NEXT:    buffer_store_b32 v2, off, s[0:3], 0
+; GFX1132-TRUE16-NEXT:    s_endpgm
+;
+; GFX1132-FAKE16-LABEL: uniform_fadd_v2bf16:
+; GFX1132-FAKE16:       ; %bb.0:
+; GFX1132-FAKE16-NEXT:    s_clause 0x1
+; GFX1132-FAKE16-NEXT:    s_load_b128 s[8:11], s[4:5], 0x24
+; GFX1132-FAKE16-NEXT:    s_load_b32 s0, s[4:5], 0x34
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s1, 0
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s6, -1
+; GFX1132-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-FAKE16-NEXT:    s_load_b32 s4, s[10:11], 0x0
+; GFX1132-FAKE16-NEXT:    s_lshl_b32 s2, s0, 16
+; GFX1132-FAKE16-NEXT:    s_and_b32 s3, s0, 0xffff0000
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s5, s11
+; GFX1132-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1132-FAKE16-NEXT:    v_mov_b32_e32 v1, s4
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s4, s10
+; GFX1132-FAKE16-NEXT:    s_set_inst_prefetch_distance 0x1
+; GFX1132-FAKE16-NEXT:    .p2align 6
+; GFX1132-FAKE16-NEXT:  .LBB21_1: ; %atomicrmw.start
+; GFX1132-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1132-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v1
+; GFX1132-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v1
+; GFX1132-FAKE16-NEXT:    v_add_f32_e32 v0, s2, v0
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1132-FAKE16-NEXT:    v_add_f32_e32 v2, s3, v2
+; GFX1132-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1132-FAKE16-NEXT:    v_bfe_u32 v4, v2, 16, 1
+; GFX1132-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX1132-FAKE16-NEXT:    v_or_b32_e32 v6, 0x400000, v2
+; GFX1132-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX1132-FAKE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX1132-FAKE16-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
+; GFX1132-FAKE16-NEXT:    v_cmp_u_f32_e64 s0, v0, v0
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1132-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v4, v6, vcc_lo
+; GFX1132-FAKE16-NEXT:    v_cndmask_b32_e64 v0, v3, v5, s0
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x7060302
+; GFX1132-FAKE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1132-FAKE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
+; GFX1132-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1132-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1132-FAKE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1132-FAKE16-NEXT:    s_or_b32 s1, vcc_lo, s1
+; GFX1132-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s1
+; GFX1132-FAKE16-NEXT:    s_cbranch_execnz .LBB21_1
+; GFX1132-FAKE16-NEXT:  ; %bb.2: ; %atomicrmw.end
+; GFX1132-FAKE16-NEXT:    s_set_inst_prefetch_distance 0x2
+; GFX1132-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX1132-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX1132-FAKE16-NEXT:    buffer_store_b32 v2, off, s[8:11], 0
+; GFX1132-FAKE16-NEXT:    s_endpgm
+;
+; GFX1264-TRUE16-LABEL: uniform_fadd_v2bf16:
+; GFX1264-TRUE16:       ; %bb.0:
+; GFX1264-TRUE16-NEXT:    s_clause 0x1
+; GFX1264-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1264-TRUE16-NEXT:    s_load_b32 s4, s[4:5], 0x34
+; GFX1264-TRUE16-NEXT:    s_mov_b64 s[8:9], 0
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s6, -1
+; GFX1264-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-TRUE16-NEXT:    s_load_b32 s5, s[2:3], 0x0
+; GFX1264-TRUE16-NEXT:    s_and_b32 s10, s4, 0xffff0000
+; GFX1264-TRUE16-NEXT:    s_lshl_b32 s11, s4, 16
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s4, s2
+; GFX1264-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-TRUE16-NEXT:    v_mov_b32_e32 v1, s5
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s5, s3
+; GFX1264-TRUE16-NEXT:  .LBB21_1: ; %atomicrmw.start
+; GFX1264-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1264-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v1
+; GFX1264-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v1
+; GFX1264-TRUE16-NEXT:    v_add_f32_e32 v0, s11, v0
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1264-TRUE16-NEXT:    v_add_f32_e32 v2, s10, v2
+; GFX1264-TRUE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1264-TRUE16-NEXT:    v_bfe_u32 v4, v2, 16, 1
+; GFX1264-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX1264-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc, v0, v0
+; GFX1264-TRUE16-NEXT:    v_or_b32_e32 v6, 0x400000, v2
+; GFX1264-TRUE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX1264-TRUE16-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
+; GFX1264-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1264-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc
+; GFX1264-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc, v2, v2
+; GFX1264-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX1264-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX1264-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v4, v6, vcc
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1264-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v0, v2
+; GFX1264-TRUE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX1264-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX1264-TRUE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1264-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1264-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1264-TRUE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1264-TRUE16-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
+; GFX1264-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1264-TRUE16-NEXT:    s_and_not1_b64 exec, exec, s[8:9]
+; GFX1264-TRUE16-NEXT:    s_cbranch_execnz .LBB21_1
+; GFX1264-TRUE16-NEXT:  ; %bb.2: ; %atomicrmw.end
+; GFX1264-TRUE16-NEXT:    s_or_b64 exec, exec, s[8:9]
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1264-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1264-TRUE16-NEXT:    buffer_store_b32 v2, off, s[0:3], null
+; GFX1264-TRUE16-NEXT:    s_endpgm
+;
+; GFX1264-FAKE16-LABEL: uniform_fadd_v2bf16:
+; GFX1264-FAKE16:       ; %bb.0:
+; GFX1264-FAKE16-NEXT:    s_clause 0x1
+; GFX1264-FAKE16-NEXT:    s_load_b128 s[8:11], s[4:5], 0x24
+; GFX1264-FAKE16-NEXT:    s_load_b32 s0, s[4:5], 0x34
+; GFX1264-FAKE16-NEXT:    s_mov_b64 s[2:3], 0
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s6, -1
+; GFX1264-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-FAKE16-NEXT:    s_load_b32 s1, s[10:11], 0x0
+; GFX1264-FAKE16-NEXT:    s_lshl_b32 s12, s0, 16
+; GFX1264-FAKE16-NEXT:    s_and_b32 s13, s0, 0xffff0000
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s4, s10
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s5, s11
+; GFX1264-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1264-FAKE16-NEXT:    v_mov_b32_e32 v1, s1
+; GFX1264-FAKE16-NEXT:  .LBB21_1: ; %atomicrmw.start
+; GFX1264-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1264-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v1
+; GFX1264-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v1
+; GFX1264-FAKE16-NEXT:    v_add_f32_e32 v0, s12, v0
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1264-FAKE16-NEXT:    v_add_f32_e32 v2, s13, v2
+; GFX1264-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1264-FAKE16-NEXT:    v_bfe_u32 v4, v2, 16, 1
+; GFX1264-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX1264-FAKE16-NEXT:    v_or_b32_e32 v6, 0x400000, v2
+; GFX1264-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc, v2, v2
+; GFX1264-FAKE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX1264-FAKE16-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
+; GFX1264-FAKE16-NEXT:    v_cmp_u_f32_e64 s[0:1], v0, v0
+; GFX1264-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX1264-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v4, v6, vcc
+; GFX1264-FAKE16-NEXT:    s_wait_alu 0xf1ff
+; GFX1264-FAKE16-NEXT:    v_cndmask_b32_e64 v0, v3, v5, s[0:1]
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1264-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x7060302
+; GFX1264-FAKE16-NEXT:    v_mov_b32_e32 v3, v1
+; GFX1264-FAKE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX1264-FAKE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1264-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1264-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1264-FAKE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1264-FAKE16-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1264-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1264-FAKE16-NEXT:    s_and_not1_b64 exec, exec, s[2:3]
+; GFX1264-FAKE16-NEXT:    s_cbranch_execnz .LBB21_1
+; GFX1264-FAKE16-NEXT:  ; %bb.2: ; %atomicrmw.end
+; GFX1264-FAKE16-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX1264-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX1264-FAKE16-NEXT:    buffer_store_b32 v2, off, s[8:11], null
+; GFX1264-FAKE16-NEXT:    s_endpgm
+;
+; GFX1232-TRUE16-LABEL: uniform_fadd_v2bf16:
+; GFX1232-TRUE16:       ; %bb.0:
+; GFX1232-TRUE16-NEXT:    s_clause 0x1
+; GFX1232-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1232-TRUE16-NEXT:    s_load_b32 s4, s[4:5], 0x34
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s8, 0
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s6, -1
+; GFX1232-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-TRUE16-NEXT:    s_load_b32 s5, s[2:3], 0x0
+; GFX1232-TRUE16-NEXT:    s_and_b32 s9, s4, 0xffff0000
+; GFX1232-TRUE16-NEXT:    s_lshl_b32 s10, s4, 16
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s4, s2
+; GFX1232-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-TRUE16-NEXT:    v_mov_b32_e32 v1, s5
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s5, s3
+; GFX1232-TRUE16-NEXT:  .LBB21_1: ; %atomicrmw.start
+; GFX1232-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1232-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v1
+; GFX1232-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v1
+; GFX1232-TRUE16-NEXT:    v_add_f32_e32 v0, s10, v0
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1232-TRUE16-NEXT:    v_add_f32_e32 v2, s9, v2
+; GFX1232-TRUE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1232-TRUE16-NEXT:    v_bfe_u32 v4, v2, 16, 1
+; GFX1232-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX1232-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX1232-TRUE16-NEXT:    v_or_b32_e32 v6, 0x400000, v2
+; GFX1232-TRUE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX1232-TRUE16-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
+; GFX1232-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1232-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX1232-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX1232-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX1232-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX1232-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v4, v6, vcc_lo
+; GFX1232-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1232-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v0, v2
+; GFX1232-TRUE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1232-TRUE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1232-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1232-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1232-TRUE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1232-TRUE16-NEXT:    s_or_b32 s8, vcc_lo, s8
+; GFX1232-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1232-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s8
+; GFX1232-TRUE16-NEXT:    s_cbranch_execnz .LBB21_1
+; GFX1232-TRUE16-NEXT:  ; %bb.2: ; %atomicrmw.end
+; GFX1232-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s8
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1232-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1232-TRUE16-NEXT:    buffer_store_b32 v2, off, s[0:3], null
+; GFX1232-TRUE16-NEXT:    s_endpgm
+;
+; GFX1232-FAKE16-LABEL: uniform_fadd_v2bf16:
+; GFX1232-FAKE16:       ; %bb.0:
+; GFX1232-FAKE16-NEXT:    s_clause 0x1
+; GFX1232-FAKE16-NEXT:    s_load_b128 s[8:11], s[4:5], 0x24
+; GFX1232-FAKE16-NEXT:    s_load_b32 s0, s[4:5], 0x34
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s1, 0
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s6, -1
+; GFX1232-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-FAKE16-NEXT:    s_load_b32 s4, s[10:11], 0x0
+; GFX1232-FAKE16-NEXT:    s_lshl_b32 s2, s0, 16
+; GFX1232-FAKE16-NEXT:    s_and_b32 s3, s0, 0xffff0000
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s5, s11
+; GFX1232-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1232-FAKE16-NEXT:    v_mov_b32_e32 v1, s4
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s4, s10
+; GFX1232-FAKE16-NEXT:  .LBB21_1: ; %atomicrmw.start
+; GFX1232-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1232-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v1
+; GFX1232-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v1
+; GFX1232-FAKE16-NEXT:    v_add_f32_e32 v0, s2, v0
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1232-FAKE16-NEXT:    v_add_f32_e32 v2, s3, v2
+; GFX1232-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1232-FAKE16-NEXT:    v_bfe_u32 v4, v2, 16, 1
+; GFX1232-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX1232-FAKE16-NEXT:    v_or_b32_e32 v6, 0x400000, v2
+; GFX1232-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX1232-FAKE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX1232-FAKE16-NEXT:    v_add3_u32 v4, v4, v2, 0x7fff
+; GFX1232-FAKE16-NEXT:    v_cmp_u_f32_e64 s0, v0, v0
+; GFX1232-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX1232-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v4, v6, vcc_lo
+; GFX1232-FAKE16-NEXT:    s_wait_alu 0xf1ff
+; GFX1232-FAKE16-NEXT:    v_cndmask_b32_e64 v0, v3, v5, s0
+; GFX1232-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1232-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x7060302
+; GFX1232-FAKE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1232-FAKE16-NEXT:    buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1232-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1232-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1232-FAKE16-NEXT:    v_mov_b32_e32 v1, v2
+; GFX1232-FAKE16-NEXT:    s_or_b32 s1, vcc_lo, s1
+; GFX1232-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1232-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s1
+; GFX1232-FAKE16-NEXT:    s_cbranch_execnz .LBB21_1
+; GFX1232-FAKE16-NEXT:  ; %bb.2: ; %atomicrmw.end
+; GFX1232-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s1
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX1232-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX1232-FAKE16-NEXT:    buffer_store_b32 v2, off, s[8:11], null
+; GFX1232-FAKE16-NEXT:    s_endpgm
   %rmw = atomicrmw fadd ptr addrspace(1) %uniform.ptr, <2 x bfloat> %val monotonic, align 4
   store <2 x bfloat> %rmw, ptr addrspace(1) %result
   ret void
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX1132_DPP-FAKE16: {{.*}}
+; GFX1132_DPP-TRUE16: {{.*}}
+; GFX1132_ITERATIVE-FAKE16: {{.*}}
+; GFX1132_ITERATIVE-TRUE16: {{.*}}
+; GFX1164_DPP-FAKE16: {{.*}}
+; GFX1164_DPP-TRUE16: {{.*}}
+; GFX1164_ITERATIVE-FAKE16: {{.*}}
+; GFX1164_ITERATIVE-TRUE16: {{.*}}
+; GFX1232_DPP-FAKE16: {{.*}}
+; GFX1232_DPP-TRUE16: {{.*}}
+; GFX1232_ITERATIVE-FAKE16: {{.*}}
+; GFX1232_ITERATIVE-TRUE16: {{.*}}
+; GFX1264_DPP-FAKE16: {{.*}}
+; GFX1264_DPP-TRUE16: {{.*}}
+; GFX1264_ITERATIVE-FAKE16: {{.*}}
+; GFX1264_ITERATIVE-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll b/llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
index 2c6aabec76330..6b9016df5cd89 100644
--- a/llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
+++ b/llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
@@ -1,6 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
 
 ; Make sure stack use isn't introduced for these bitcasts.
 
@@ -193,16 +194,30 @@ define <10 x i16> @bitcast_i160_to_v10i16(i160 %int) {
 ; GFX9-NEXT:    v_bfi_b32 v2, s4, v2, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: bitcast_i160_to_v10i16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_bfi_b32 v0, 0xffff, v0, v0
-; GFX12-NEXT:    v_bfi_b32 v2, 0xffff, v2, v2
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: bitcast_i160_to_v10i16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v2.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v5, v0
+; GFX12-TRUE16-NEXT:    v_bfi_b32 v2, 0xffff, v6, v2
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: bitcast_i160_to_v10i16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_bfi_b32 v0, 0xffff, v0, v0
+; GFX12-FAKE16-NEXT:    v_bfi_b32 v2, 0xffff, v2, v2
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %bitcast = bitcast i160 %int to <10 x i16>
   ret <10 x i16> %bitcast
 }
@@ -235,19 +250,33 @@ define i12 @bitcast_v2i6_to_i12(<2 x i6> %vec) {
 ; GFX9-NEXT:    v_and_b32_e32 v0, 0xfff, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: bitcast_v2i6_to_i12:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshlrev_b16 v1, 6, v1
-; GFX12-NEXT:    v_and_b32_e32 v0, 63, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xfff, v0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: bitcast_v2i6_to_i12:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 6, v1.l
+; GFX12-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 63
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT:    v_and_b16 v0.l, 0xfff, v0.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: bitcast_v2i6_to_i12:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshlrev_b16 v1, 6, v1
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 63, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xfff, v0
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %bitcast = bitcast <2 x i6> %vec to i12
   ret i12 %bitcast
 }
@@ -262,18 +291,31 @@ define <2 x i6> @bitcast_i12_to_v2i6(i12 %int) {
 ; GFX9-NEXT:    v_mov_b32_e32 v0, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: bitcast_i12_to_v2i6:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b16 v1, 6, v0
-; GFX12-NEXT:    v_and_b32_e32 v0, 63, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT:    v_and_b32_e32 v1, 63, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: bitcast_i12_to_v2i6:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_lshrrev_b16 v0.h, 6, v0.l
+; GFX12-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 63
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_and_b16 v1.l, v0.h, 63
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: bitcast_i12_to_v2i6:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b16 v1, 6, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 63, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 63, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %bitcast = bitcast i12 %int to <2 x i6>
   ret <2 x i6> %bitcast
 }
diff --git a/llvm/test/CodeGen/AMDGPU/bitreverse.ll b/llvm/test/CodeGen/AMDGPU/bitreverse.ll
index bb7974335bf28..a9358dc4a51d8 100644
--- a/llvm/test/CodeGen/AMDGPU/bitreverse.ll
+++ b/llvm/test/CodeGen/AMDGPU/bitreverse.ll
@@ -3,8 +3,10 @@
 ; RUN: llc < %s -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=FLAT
 ; RUN: llc < %s -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=FLAT
 ; RUN: llc < %s -mtriple=amdgcn-- -mcpu=fiji -global-isel -verify-machineinstrs | FileCheck %s --check-prefix=GISEL
-; RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=GFX11-FLAT
-; RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx1100 -global-isel -verify-machineinstrs | FileCheck %s --check-prefix=GFX11-GISEL
+; RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefixes=GFX11-FLAT,GFX11-FLAT-TRUE16
+; RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-real-true16 -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefixes=GFX11-FLAT,GFX11-FLAT-FAKE16
+; RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 -global-isel -verify-machineinstrs | FileCheck %s --check-prefixes=GFX11-GISEL,GFX11-GISEL-TRUE16
+; RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-real-true16 -global-isel -verify-machineinstrs | FileCheck %s --check-prefixes=GFX11-GISEL,GFX11-GISEL-FAKE16
 
 declare i32 @llvm.amdgcn.workitem.id.x() #1
 
@@ -71,21 +73,37 @@ define amdgpu_kernel void @s_brev_i16(ptr addrspace(1) noalias %out, i16 %val) #
 ; GFX11-FLAT-NEXT:    global_store_d16_hi_b16 v0, v1, s[0:1]
 ; GFX11-FLAT-NEXT:    s_endpgm
 ;
-; GFX11-GISEL-LABEL: s_brev_i16:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_clause 0x1
-; GFX11-GISEL-NEXT:    s_load_b32 s2, s[4:5], 0x2c
-; GFX11-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-GISEL-NEXT:    v_mov_b32_e32 v1, 0
-; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT:    s_and_b32 s2, s2, 0xffff
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-NEXT:    s_brev_b32 s2, s2
-; GFX11-GISEL-NEXT:    s_lshr_b32 s2, s2, 16
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-GISEL-NEXT:    v_mov_b32_e32 v0, s2
-; GFX11-GISEL-NEXT:    global_store_b16 v1, v0, s[0:1]
-; GFX11-GISEL-NEXT:    s_endpgm
+; GFX11-GISEL-TRUE16-LABEL: s_brev_i16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_clause 0x1
+; GFX11-GISEL-TRUE16-NEXT:    s_load_b32 s2, s[4:5], 0x2c
+; GFX11-GISEL-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    s_and_b32 s2, s2, 0xffff
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-TRUE16-NEXT:    s_brev_b32 s2, s2
+; GFX11-GISEL-TRUE16-NEXT:    s_lshr_b32 s2, s2, 16
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v0.l, s2
+; GFX11-GISEL-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX11-GISEL-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-GISEL-FAKE16-LABEL: s_brev_i16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_clause 0x1
+; GFX11-GISEL-FAKE16-NEXT:    s_load_b32 s2, s[4:5], 0x2c
+; GFX11-GISEL-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    s_and_b32 s2, s2, 0xffff
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-FAKE16-NEXT:    s_brev_b32 s2, s2
+; GFX11-GISEL-FAKE16-NEXT:    s_lshr_b32 s2, s2, 16
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v0, s2
+; GFX11-GISEL-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX11-GISEL-FAKE16-NEXT:    s_endpgm
   %brev = call i16 @llvm.bitreverse.i16(i16 %val) #1
   store i16 %brev, ptr addrspace(1) %out
   ret void
@@ -160,16 +178,29 @@ define amdgpu_kernel void @v_brev_i16(ptr addrspace(1) noalias %out, ptr addrspa
 ; GFX11-FLAT-NEXT:    global_store_d16_hi_b16 v1, v0, s[0:1]
 ; GFX11-FLAT-NEXT:    s_endpgm
 ;
-; GFX11-GISEL-LABEL: v_brev_i16:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-GISEL-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT:    global_load_u16 v1, v0, s[2:3]
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-GISEL-NEXT:    v_bfrev_b32_e32 v1, v1
-; GFX11-GISEL-NEXT:    global_store_d16_hi_b16 v0, v1, s[0:1]
-; GFX11-GISEL-NEXT:    s_endpgm
+; GFX11-GISEL-TRUE16-LABEL: v_brev_i16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    global_load_u16 v1, v0, s[2:3]
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_bfrev_b32_e32 v1, v1
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX11-GISEL-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-GISEL-FAKE16-LABEL: v_brev_i16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3]
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_bfrev_b32_e32 v1, v1
+; GFX11-GISEL-FAKE16-NEXT:    global_store_d16_hi_b16 v0, v1, s[0:1]
+; GFX11-GISEL-FAKE16-NEXT:    s_endpgm
   %val = load i16, ptr addrspace(1) %valptr
   %brev = call i16 @llvm.bitreverse.i16(i16 %val) #1
   store i16 %brev, ptr addrspace(1) %out
@@ -871,23 +902,40 @@ define float @missing_truncate_promote_bitreverse(i32 %arg) {
 ; GISEL-NEXT:    v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
 ; GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-FLAT-LABEL: missing_truncate_promote_bitreverse:
-; GFX11-FLAT:       ; %bb.0: ; %bb
-; GFX11-FLAT-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FLAT-NEXT:    v_bfrev_b32_e32 v0, v0
-; GFX11-FLAT-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FLAT-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-FLAT-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-FLAT-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: missing_truncate_promote_bitreverse:
-; GFX11-GISEL:       ; %bb.0: ; %bb
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_bfrev_b32_e32 v0, v0
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-GISEL-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FLAT-TRUE16-LABEL: missing_truncate_promote_bitreverse:
+; GFX11-FLAT-TRUE16:       ; %bb.0: ; %bb
+; GFX11-FLAT-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLAT-TRUE16-NEXT:    v_bfrev_b32_e32 v0, v0
+; GFX11-FLAT-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FLAT-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.h
+; GFX11-FLAT-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FLAT-FAKE16-LABEL: missing_truncate_promote_bitreverse:
+; GFX11-FLAT-FAKE16:       ; %bb.0: ; %bb
+; GFX11-FLAT-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FLAT-FAKE16-NEXT:    v_bfrev_b32_e32 v0, v0
+; GFX11-FLAT-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FLAT-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FLAT-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FLAT-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: missing_truncate_promote_bitreverse:
+; GFX11-GISEL-TRUE16:       ; %bb.0: ; %bb
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_bfrev_b32_e32 v0, v0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: missing_truncate_promote_bitreverse:
+; GFX11-GISEL-FAKE16:       ; %bb.0: ; %bb
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_bfrev_b32_e32 v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 bb:
   %tmp = trunc i32 %arg to i16
   %tmp1 = call i16 @llvm.bitreverse.i16(i16 %tmp)
diff --git a/llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll b/llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
index a6af63b816573..ad0d6d8016ad6 100644
--- a/llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
+++ b/llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
@@ -126,5 +126,3 @@ kernel_direct_lighting.exit:                      ; preds = %if.end294.i.i, %ent
 
 declare float @_Z3dotDv3_fS_(<3 x float>)
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll b/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
index 266216c4d8b50..d51e47bfb8d4f 100644
--- a/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
@@ -1294,5 +1294,3 @@ declare void @f2(i64)
 
 declare i32 @llvm.amdgcn.workitem.id.x()
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
index 9de6aea9385df..2e79d8bab46a6 100644
--- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
@@ -34,5 +34,3 @@ attributes #0 = { noinline norecurse nounwind optnone }
 attributes #1 = { noinline norecurse nounwind readnone willreturn }
 attributes #2 = { nounwind readnone willreturn }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
index f719f50ef6f13..337da5d0ecbe0 100644
--- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
@@ -29,5 +29,3 @@ attributes #0 = { noinline norecurse nounwind optnone }
 attributes #1 = { noinline norecurse nounwind readnone willreturn }
 attributes #2 = { nounwind readnone willreturn }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
index fe27859eb0afd..075eddd2763d3 100644
--- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
@@ -35,5 +35,3 @@ attributes #0 = { noinline norecurse nounwind optnone }
 attributes #1 = { noinline norecurse nounwind readnone willreturn "amdgpu-waves-per-eu"="8,10" }
 attributes #2 = { nounwind readnone willreturn }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
index 35b67351e85dd..4fd181d3c0f43 100644
--- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
@@ -32,5 +32,3 @@ attributes #0 = { noinline norecurse nounwind optnone }
 attributes #1 = { noinline norecurse nounwind readnone willreturn "amdgpu-waves-per-eu"="4,10" }
 attributes #2 = { nounwind readnone willreturn }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
index 3674d740b987b..00f72d5d8b1dd 100644
--- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
@@ -32,5 +32,3 @@ attributes #0 = { noinline norecurse nounwind optnone }
 attributes #1 = { noinline norecurse nounwind readnone willreturn "amdgpu-flat-work-group-size"="1,256" "amdgpu-waves-per-eu"="1,1" }
 attributes #2 = { nounwind readnone willreturn }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll b/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
index c10cb0ae6d336..d1cede64ce71d 100644
--- a/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
@@ -1529,5 +1529,3 @@ define void @test_call_external_void_func_a15i32_inreg_i32_inreg([13 x i32] inre
 attributes #0 = { nounwind }
 attributes #1 = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-queue-ptr" "amdgpu-no-work-group-id-x" "amdgpu-no-work-group-id-y" "amdgpu-no-work-group-id-z" "amdgpu-no-work-item-id-x" "amdgpu-no-work-item-id-y" "amdgpu-no-work-item-id-z" }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/call-argument-types.ll b/llvm/test/CodeGen/AMDGPU/call-argument-types.ll
index 6be80d2f5957b..178b138b57141 100644
--- a/llvm/test/CodeGen/AMDGPU/call-argument-types.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-argument-types.ll
@@ -2,7 +2,8 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global -amdgpu-scalarize-global-loads=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=hawaii -amdgpu-scalarize-global-loads=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-scalarize-global-loads=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -amdgpu-scalarize-global-loads=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=-flat-for-global -amdgpu-scalarize-global-loads=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=-flat-for-global -amdgpu-scalarize-global-loads=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -mattr=-flat-for-global -amdgpu-scalarize-global-loads=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=HSA %s
 
 declare hidden void @external_void_func_i1(i1) #0
@@ -4855,22 +4856,40 @@ define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0
 ; GFX9-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; GFX9-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: test_call_external_void_func_byval_struct_i8_i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 8
-; GFX11-NEXT:    s_mov_b32 s32, 16
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_byval_struct_i8_i32@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_byval_struct_i8_i32@rel32@hi+12
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_store_b8 off, v0, off
-; GFX11-NEXT:    scratch_store_b32 off, v1, off offset:4
-; GFX11-NEXT:    scratch_load_b64 v[0:1], off, off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    scratch_store_b64 off, v[0:1], s32
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: test_call_external_void_func_byval_struct_i8_i32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, 3
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s32, 16
+; GFX11-TRUE16-NEXT:    s_getpc_b64 s[2:3]
+; GFX11-TRUE16-NEXT:    s_add_u32 s2, s2, external_void_func_byval_struct_i8_i32@rel32@lo+4
+; GFX11-TRUE16-NEXT:    s_addc_u32 s3, s3, external_void_func_byval_struct_i8_i32@rel32@hi+12
+; GFX11-TRUE16-NEXT:    s_mov_b64 s[6:7], s[0:1]
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_store_b8 off, v0, off
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v1, off offset:4
+; GFX11-TRUE16-NEXT:    scratch_load_b64 v[0:1], off, off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    scratch_store_b64 off, v[0:1], s32
+; GFX11-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: test_call_external_void_func_byval_struct_i8_i32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s32, 16
+; GFX11-FAKE16-NEXT:    s_getpc_b64 s[2:3]
+; GFX11-FAKE16-NEXT:    s_add_u32 s2, s2, external_void_func_byval_struct_i8_i32@rel32@lo+4
+; GFX11-FAKE16-NEXT:    s_addc_u32 s3, s3, external_void_func_byval_struct_i8_i32@rel32@hi+12
+; GFX11-FAKE16-NEXT:    s_mov_b64 s[6:7], s[0:1]
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_store_b8 off, v0, off
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v1, off offset:4
+; GFX11-FAKE16-NEXT:    scratch_load_b64 v[0:1], off, off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    scratch_store_b64 off, v[0:1], s32
+; GFX11-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-FAKE16-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_byval_struct_i8_i32:
 ; HSA:       ; %bb.0:
@@ -5021,36 +5040,68 @@ define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 8
-; GFX11-NEXT:    s_mov_b32 s32, 32
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@rel32@hi+12
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_store_b8 off, v0, off
-; GFX11-NEXT:    scratch_store_b32 off, v1, off offset:4
-; GFX11-NEXT:    scratch_load_b64 v[0:1], off, off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    scratch_store_b64 off, v[0:1], s32
-; GFX11-NEXT:    v_mov_b32_e32 v0, 8
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_u8 v0, off, off offset:8
-; GFX11-NEXT:    scratch_load_b32 v1, off, off offset:12
-; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    buffer_store_b8 v0, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    buffer_store_b32 v1, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_nop 0
-; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, 3
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s32, 32
+; GFX11-TRUE16-NEXT:    s_getpc_b64 s[2:3]
+; GFX11-TRUE16-NEXT:    s_add_u32 s2, s2, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@rel32@lo+4
+; GFX11-TRUE16-NEXT:    s_addc_u32 s3, s3, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@rel32@hi+12
+; GFX11-TRUE16-NEXT:    s_mov_b64 s[6:7], s[0:1]
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_store_b8 off, v0, off
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v1, off offset:4
+; GFX11-TRUE16-NEXT:    scratch_load_b64 v[0:1], off, off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    scratch_store_b64 off, v[0:1], s32
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, 8
+; GFX11-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_d16_u8 v0, off, off offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v1, off, off offset:12
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    buffer_store_b8 v0, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    buffer_store_b32 v1, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_nop 0
+; GFX11-TRUE16-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s32, 32
+; GFX11-FAKE16-NEXT:    s_getpc_b64 s[2:3]
+; GFX11-FAKE16-NEXT:    s_add_u32 s2, s2, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@rel32@lo+4
+; GFX11-FAKE16-NEXT:    s_addc_u32 s3, s3, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@rel32@hi+12
+; GFX11-FAKE16-NEXT:    s_mov_b64 s[6:7], s[0:1]
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_store_b8 off, v0, off
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v1, off offset:4
+; GFX11-FAKE16-NEXT:    scratch_load_b64 v[0:1], off, off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    scratch_store_b64 off, v[0:1], s32
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 8
+; GFX11-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_u8 v0, off, off offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v1, off, off offset:12
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    buffer_store_b8 v0, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    buffer_store_b32 v1, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_nop 0
+; GFX11-FAKE16-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-FAKE16-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32:
 ; HSA:       ; %bb.0:
@@ -5230,37 +5281,69 @@ define amdgpu_kernel void @test_call_external_void_func_v16i8() #0 {
 ; GFX9-NEXT:    s_swappc_b64 s[30:31], s[4:5]
 ; GFX9-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: test_call_external_void_func_v16i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[4:5], s[0:1], 0x0
-; GFX11-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s6, -1
-; GFX11-NEXT:    s_getpc_b64 s[2:3]
-; GFX11-NEXT:    s_add_u32 s2, s2, external_void_func_v16i8@rel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s3, s3, external_void_func_v16i8@rel32@hi+12
-; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    buffer_load_b128 v[0:3], off, s[4:7], 0
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[0:1]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v16, 8, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 24, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v11, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v3
-; GFX11-NEXT:    v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v1, v16
-; GFX11-NEXT:    v_mov_b32_e32 v8, v2
-; GFX11-NEXT:    v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v3, v18
-; GFX11-NEXT:    v_mov_b32_e32 v2, v17
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[2:3]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: test_call_external_void_func_v16i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b64 s[4:5], s[0:1], 0x0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, -1
+; GFX11-TRUE16-NEXT:    s_getpc_b64 s[2:3]
+; GFX11-TRUE16-NEXT:    s_add_u32 s2, s2, external_void_func_v16i8@rel32@lo+4
+; GFX11-TRUE16-NEXT:    s_addc_u32 s3, s3, external_void_func_v16i8@rel32@hi+12
+; GFX11-TRUE16-NEXT:    s_mov_b32 s32, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    buffer_load_b128 v[16:19], off, s[4:7], 0
+; GFX11-TRUE16-NEXT:    s_mov_b64 s[6:7], s[0:1]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v11, 24, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v17.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v19.l
+; GFX11-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: test_call_external_void_func_v16i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b64 s[4:5], s[0:1], 0x0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, -1
+; GFX11-FAKE16-NEXT:    s_getpc_b64 s[2:3]
+; GFX11-FAKE16-NEXT:    s_add_u32 s2, s2, external_void_func_v16i8@rel32@lo+4
+; GFX11-FAKE16-NEXT:    s_addc_u32 s3, s3, external_void_func_v16i8@rel32@hi+12
+; GFX11-FAKE16-NEXT:    s_mov_b32 s32, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    buffer_load_b128 v[0:3], off, s[4:7], 0
+; GFX11-FAKE16-NEXT:    s_mov_b64 s[6:7], s[0:1]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 24, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v11, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v3
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v1, v16
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v2
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v3, v18
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, v17
+; GFX11-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[2:3]
+; GFX11-FAKE16-NEXT:    s_endpgm
 ;
 ; HSA-LABEL: test_call_external_void_func_v16i8:
 ; HSA:       ; %bb.0:
@@ -7203,5 +7286,3 @@ attributes #0 = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amd
 attributes #1 = { nounwind readnone }
 attributes #2 = { nounwind noinline }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/call-waitcnt.ll b/llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
index 15152409eacf9..9abb50651146a 100644
--- a/llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
@@ -156,5 +156,3 @@ declare void @got.func(i32) #0
 
 attributes #0 = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll b/llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
index 10ca3c9d5f2c8..67f2eb113d880 100644
--- a/llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
+++ b/llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
@@ -584,5 +584,3 @@ attributes #0 = { nounwind readnone speculatable }
 attributes #1 = { nounwind noinline }
 attributes #2 = { nounwind noinline "amdgpu-implicitarg-num-bytes"="0" }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
index da52474f08fbd..0c335e45c9e2f 100644
--- a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
+++ b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
@@ -1,7 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX11,GFX11-FAKE16 %s
 
 ; Make sure we don't crash or assert on spir_kernel calling convention.
 
@@ -60,10 +61,15 @@ define amdgpu_ps half @ps_ret_cc_f16(half %arg0) {
 ; VI-NEXT:    v_add_f16_e32 v0, 1.0, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: ps_ret_cc_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    v_add_f16_e32 v0, 1.0, v0
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: ps_ret_cc_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_add_f16_e32 v0.l, 1.0, v0.l
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: ps_ret_cc_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_add_f16_e32 v0, 1.0, v0
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
   %add = fadd half %arg0, 1.0
   ret half %add
 }
@@ -81,10 +87,15 @@ define amdgpu_ps half @ps_ret_cc_inreg_f16(half inreg %arg0) {
 ; VI-NEXT:    v_add_f16_e64 v0, s0, 1.0
 ; VI-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: ps_ret_cc_inreg_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    v_add_f16_e64 v0, s0, 1.0
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: ps_ret_cc_inreg_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_add_f16_e64 v0.l, s0, 1.0
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: ps_ret_cc_inreg_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_add_f16_e64 v0, s0, 1.0
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
   %add = fadd half %arg0, 1.0
   ret half %add
 }
@@ -311,10 +322,15 @@ define amdgpu_cs half @cs_mesa(half %arg0) {
 ; VI-NEXT:    v_add_f16_e32 v0, 1.0, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: cs_mesa:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    v_add_f16_e32 v0, 1.0, v0
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: cs_mesa:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_add_f16_e32 v0.l, 1.0, v0.l
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: cs_mesa:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_add_f16_e32 v0, 1.0, v0
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
   %add = fadd half %arg0, 1.0
   ret half %add
 }
@@ -333,10 +349,15 @@ define amdgpu_ps half @ps_mesa_f16(half %arg0) {
 ; VI-NEXT:    v_add_f16_e32 v0, 1.0, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: ps_mesa_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    v_add_f16_e32 v0, 1.0, v0
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: ps_mesa_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_add_f16_e32 v0.l, 1.0, v0.l
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: ps_mesa_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_add_f16_e32 v0, 1.0, v0
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
   %add = fadd half %arg0, 1.0
   ret half %add
 }
@@ -355,10 +376,15 @@ define amdgpu_vs half @vs_mesa(half %arg0) {
 ; VI-NEXT:    v_add_f16_e32 v0, 1.0, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: vs_mesa:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    v_add_f16_e32 v0, 1.0, v0
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: vs_mesa:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_add_f16_e32 v0.l, 1.0, v0.l
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: vs_mesa:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_add_f16_e32 v0, 1.0, v0
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
   %add = fadd half %arg0, 1.0
   ret half %add
 }
@@ -377,10 +403,15 @@ define amdgpu_gs half @gs_mesa(half %arg0) {
 ; VI-NEXT:    v_add_f16_e32 v0, 1.0, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: gs_mesa:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    v_add_f16_e32 v0, 1.0, v0
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gs_mesa:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_add_f16_e32 v0.l, 1.0, v0.l
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gs_mesa:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_add_f16_e32 v0, 1.0, v0
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
   %add = fadd half %arg0, 1.0
   ret half %add
 }
@@ -399,10 +430,15 @@ define amdgpu_hs half @hs_mesa(half %arg0) {
 ; VI-NEXT:    v_add_f16_e32 v0, 1.0, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: hs_mesa:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    v_add_f16_e32 v0, 1.0, v0
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: hs_mesa:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_add_f16_e32 v0.l, 1.0, v0.l
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: hs_mesa:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_add_f16_e32 v0, 1.0, v0
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
   %add = fadd half %arg0, 1.0
   ret half %add
 }
@@ -940,11 +976,17 @@ define amdgpu_ps void @ps_mesa_i16(i16 %arg0) {
 ; VI-NEXT:    flat_store_short v[0:1], v0
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: ps_mesa_i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    v_add_nc_u16 v0, v0, v0
-; GFX11-NEXT:    global_store_b16 v[0:1], v0, off
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: ps_mesa_i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v0.l
+; GFX11-TRUE16-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: ps_mesa_i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v0
+; GFX11-FAKE16-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX11-FAKE16-NEXT:    s_endpgm
   %add = add i16 %arg0, %arg0
   store i16 %add, ptr addrspace(1) poison
   ret void
@@ -2232,35 +2274,65 @@ define amdgpu_cs void @amdgpu_cs_v8i1(<8 x i1> %arg0) {
 ; VI-NEXT:    flat_store_byte v[0:1], v0
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: amdgpu_cs_v8i1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    v_and_b32_e32 v6, 1, v6
-; GFX11-NEXT:    v_lshlrev_b16 v5, 1, v5
-; GFX11-NEXT:    v_and_b32_e32 v4, 1, v4
-; GFX11-NEXT:    v_and_b32_e32 v2, 1, v2
-; GFX11-NEXT:    v_lshlrev_b16 v1, 1, v1
-; GFX11-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX11-NEXT:    v_lshlrev_b16 v7, 3, v7
-; GFX11-NEXT:    v_lshlrev_b16 v6, 2, v6
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v5
-; GFX11-NEXT:    v_lshlrev_b16 v3, 3, v3
-; GFX11-NEXT:    v_lshlrev_b16 v2, 2, v2
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v7, v6
-; GFX11-NEXT:    v_and_b32_e32 v4, 3, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v2, v3, v2
-; GFX11-NEXT:    v_and_b32_e32 v0, 3, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v1, v4, v1
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_lshlrev_b16 v1, 4, v1
-; GFX11-NEXT:    v_and_b32_e32 v0, 15, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: amdgpu_cs_v8i1:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, v6.l, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 1, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, v4.l, 1
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, v2.l, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 1, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 3, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 2, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v4.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 3, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 2, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v5.h, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, v0.h, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v2.h, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 4, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 15
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: amdgpu_cs_v8i1:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 1, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 1, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 1, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 1, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 1, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 3, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v6, 2, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 3, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v2, 2, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v7, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 3, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 3, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v4, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 4, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 15, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-FAKE16-NEXT:    s_endpgm
   store <8 x i1> %arg0, ptr addrspace(1) poison
   ret void
 }
@@ -2367,60 +2439,115 @@ define amdgpu_cs void @amdgpu_cs_v16i1(<16 x i1> %arg0) {
 ; VI-NEXT:    flat_store_short v[0:1], v0
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: amdgpu_cs_v16i1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    v_and_b32_e32 v10, 1, v10
-; GFX11-NEXT:    v_lshlrev_b16 v9, 1, v9
-; GFX11-NEXT:    v_and_b32_e32 v8, 1, v8
-; GFX11-NEXT:    v_and_b32_e32 v6, 1, v6
-; GFX11-NEXT:    v_lshlrev_b16 v5, 1, v5
-; GFX11-NEXT:    v_and_b32_e32 v4, 1, v4
-; GFX11-NEXT:    v_and_b32_e32 v2, 1, v2
-; GFX11-NEXT:    v_lshlrev_b16 v1, 1, v1
-; GFX11-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX11-NEXT:    v_and_b32_e32 v14, 1, v14
-; GFX11-NEXT:    v_lshlrev_b16 v13, 1, v13
-; GFX11-NEXT:    v_and_b32_e32 v12, 1, v12
-; GFX11-NEXT:    v_lshlrev_b16 v11, 3, v11
-; GFX11-NEXT:    v_lshlrev_b16 v10, 2, v10
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v7, 3, v7
-; GFX11-NEXT:    v_lshlrev_b16 v6, 2, v6
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v5
-; GFX11-NEXT:    v_lshlrev_b16 v3, 3, v3
-; GFX11-NEXT:    v_lshlrev_b16 v2, 2, v2
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshlrev_b16 v15, 3, v15
-; GFX11-NEXT:    v_lshlrev_b16 v14, 2, v14
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v10, v11, v10
-; GFX11-NEXT:    v_and_b32_e32 v1, 3, v8
-; GFX11-NEXT:    v_or_b32_e32 v5, v7, v6
-; GFX11-NEXT:    v_and_b32_e32 v4, 3, v4
-; GFX11-NEXT:    v_or_b32_e32 v2, v3, v2
-; GFX11-NEXT:    v_and_b32_e32 v0, 3, v0
-; GFX11-NEXT:    v_or_b32_e32 v3, v15, v14
-; GFX11-NEXT:    v_and_b32_e32 v6, 3, v12
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v10
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v2, v6, v3
-; GFX11-NEXT:    v_and_b32_e32 v1, 15, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshlrev_b16 v3, 4, v4
-; GFX11-NEXT:    v_and_b32_e32 v0, 15, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshlrev_b16 v2, 12, v2
-; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v3
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    global_store_b16 v[0:1], v0, off
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: amdgpu_cs_v16i1:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, v10.l, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.l, 1, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, v8.l, 1
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, v6.l, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 1, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, v4.l, 1
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, v2.l, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 1, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 1
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, v14.l, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.l, 1, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, v12.l, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 3, v11.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.l, 2, v10.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.h, v8.l, v9.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.l, 3, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 2, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v4.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 3, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 2, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 3, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 2, v14.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.h, v12.l, v13.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v9.h, v10.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, v5.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v7.l, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, v0.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v2.h, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v12.h, v10.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.l, v8.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v3.l, v2.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, v1.l, 15
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 4, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 15
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 12, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v1.h, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: amdgpu_cs_v16i1:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 1, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, 1, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 1, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 1, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 1, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 1, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 1, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 1, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 1, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 1, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 1, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 3, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v10, 2, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 3, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v6, 2, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 3, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v2, 2, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 3, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v14, 2, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v11, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 3, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v7, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 3, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 3, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v15, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 3, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v6, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 15, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 4, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 15, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v2, 12, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX11-FAKE16-NEXT:    s_endpgm
   store <16 x i1> %arg0, ptr addrspace(1) poison
   ret void
 }
@@ -2619,107 +2746,209 @@ define amdgpu_cs void @amdgpu_cs_v32i1(<32 x i1> %arg0) {
 ; VI-NEXT:    flat_store_dword v[0:1], v0
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: amdgpu_cs_v32i1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    v_and_b32_e32 v10, 1, v10
-; GFX11-NEXT:    v_lshlrev_b16 v9, 1, v9
-; GFX11-NEXT:    v_and_b32_e32 v8, 1, v8
-; GFX11-NEXT:    v_lshlrev_b16 v11, 3, v11
-; GFX11-NEXT:    v_and_b32_e32 v6, 1, v6
-; GFX11-NEXT:    v_lshlrev_b16 v10, 2, v10
-; GFX11-NEXT:    v_and_b32_e32 v2, 1, v2
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v9
-; GFX11-NEXT:    v_lshlrev_b16 v1, 1, v1
-; GFX11-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX11-NEXT:    v_and_b32_e32 v14, 1, v14
-; GFX11-NEXT:    v_lshlrev_b16 v13, 1, v13
-; GFX11-NEXT:    v_and_b32_e32 v12, 1, v12
-; GFX11-NEXT:    v_lshlrev_b16 v5, 1, v5
-; GFX11-NEXT:    v_and_b32_e32 v4, 1, v4
-; GFX11-NEXT:    v_or_b32_e32 v9, v11, v10
-; GFX11-NEXT:    v_and_b32_e32 v8, 3, v8
-; GFX11-NEXT:    v_lshlrev_b16 v7, 3, v7
-; GFX11-NEXT:    v_lshlrev_b16 v6, 2, v6
-; GFX11-NEXT:    v_lshlrev_b16 v3, 3, v3
-; GFX11-NEXT:    v_lshlrev_b16 v2, 2, v2
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshlrev_b16 v15, 3, v15
-; GFX11-NEXT:    v_lshlrev_b16 v14, 2, v14
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v5, v7, v6
-; GFX11-NEXT:    v_or_b32_e32 v6, v8, v9
-; GFX11-NEXT:    v_or_b32_e32 v2, v3, v2
-; GFX11-NEXT:    v_and_b32_e32 v0, 3, v0
-; GFX11-NEXT:    v_or_b32_e32 v13, v15, v14
-; GFX11-NEXT:    v_and_b32_e32 v12, 3, v12
-; GFX11-NEXT:    v_and_b32_e32 v3, 15, v6
-; GFX11-NEXT:    v_lshlrev_b16 v6, 1, v29
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v2
-; GFX11-NEXT:    v_and_b32_e32 v2, 1, v26
-; GFX11-NEXT:    v_and_b32_e32 v7, 1, v28
-; GFX11-NEXT:    v_lshlrev_b16 v9, 1, v25
-; GFX11-NEXT:    v_and_b32_e32 v10, 1, v24
-; GFX11-NEXT:    v_and_b32_e32 v4, 3, v4
-; GFX11-NEXT:    v_or_b32_e32 v1, v12, v13
-; GFX11-NEXT:    v_lshlrev_b16 v8, 3, v27
-; GFX11-NEXT:    v_lshlrev_b16 v2, 2, v2
-; GFX11-NEXT:    v_or_b32_e32 v6, v7, v6
-; GFX11-NEXT:    v_or_b32_e32 v7, v10, v9
-; GFX11-NEXT:    v_and_b32_e32 v9, 1, v22
-; GFX11-NEXT:    v_lshlrev_b16 v10, 1, v21
-; GFX11-NEXT:    v_and_b32_e32 v12, 1, v20
-; GFX11-NEXT:    v_and_b32_e32 v13, 1, v18
-; GFX11-NEXT:    v_lshlrev_b16 v14, 1, v17
-; GFX11-NEXT:    v_and_b32_e32 v15, 1, v16
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v5
-; GFX11-NEXT:    v_and_b32_e32 v5, 1, v30
-; GFX11-NEXT:    v_or_b32_e32 v2, v8, v2
-; GFX11-NEXT:    v_lshlrev_b16 v8, 3, v23
-; GFX11-NEXT:    v_lshlrev_b16 v9, 2, v9
-; GFX11-NEXT:    v_or_b32_e32 v10, v12, v10
-; GFX11-NEXT:    v_lshlrev_b16 v12, 3, v19
-; GFX11-NEXT:    v_lshlrev_b16 v13, 2, v13
-; GFX11-NEXT:    v_or_b32_e32 v14, v15, v14
-; GFX11-NEXT:    v_lshlrev_b16 v11, 3, v31
-; GFX11-NEXT:    v_lshlrev_b16 v5, 2, v5
-; GFX11-NEXT:    v_and_b32_e32 v7, 3, v7
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v9
-; GFX11-NEXT:    v_and_b32_e32 v9, 3, v10
-; GFX11-NEXT:    v_or_b32_e32 v10, v12, v13
-; GFX11-NEXT:    v_and_b32_e32 v12, 3, v14
-; GFX11-NEXT:    v_or_b32_e32 v5, v11, v5
-; GFX11-NEXT:    v_and_b32_e32 v6, 3, v6
-; GFX11-NEXT:    v_or_b32_e32 v2, v7, v2
-; GFX11-NEXT:    v_or_b32_e32 v7, v9, v8
-; GFX11-NEXT:    v_or_b32_e32 v8, v12, v10
-; GFX11-NEXT:    v_lshlrev_b16 v4, 4, v4
-; GFX11-NEXT:    v_and_b32_e32 v0, 15, v0
-; GFX11-NEXT:    v_or_b32_e32 v5, v6, v5
-; GFX11-NEXT:    v_and_b32_e32 v2, 15, v2
-; GFX11-NEXT:    v_lshlrev_b16 v6, 4, v7
-; GFX11-NEXT:    v_and_b32_e32 v7, 15, v8
-; GFX11-NEXT:    v_lshlrev_b16 v1, 12, v1
-; GFX11-NEXT:    v_lshlrev_b16 v3, 8, v3
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v4
-; GFX11-NEXT:    v_lshlrev_b16 v4, 12, v5
-; GFX11-NEXT:    v_lshlrev_b16 v2, 8, v2
-; GFX11-NEXT:    v_or_b32_e32 v5, v7, v6
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v3
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v2
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v3, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    global_store_b32 v[0:1], v0, off
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: amdgpu_cs_v32i1:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, v10.l, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.l, 1, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, v8.l, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 3, v11.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.h, v6.l, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.l, 2, v10.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 1, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.h, v8.l, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, v4.l, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.l, 3, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.h, v9.h, v10.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 2, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, v6.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v4.l, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, v2.l, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 3, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v6.l, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v5.h, v9.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, v0.h, 3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 1, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 1
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, v28.l, 1
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, v26.l, 1
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, v3.l, 15
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 1, v29.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 2, v1.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.l, 2, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 1, v25.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.h, v3.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 3, v27.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, v24.l, 1
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v2.h, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.h, 1, v21.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v3.h, v4.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v5.l, v4.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, v22.l, 1
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, v20.l, 1
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.h, v18.l, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.l, 1, v17.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, v16.l, 1
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, v14.l, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.l, 1, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, v12.l, 1
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, v30.l, 1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 3, v23.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 2, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.h, v6.l, v5.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.l, 3, v19.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 2, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.h, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 3, v15.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 2, v14.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 3, v31.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 2, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, v4.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.h, v4.h, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.l, v5.h, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.h, v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, v7.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.h, v12.h, v13.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, v12.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v2.h, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, v3.l, 3
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v4.l, v3.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.h, v5.l, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v6.l, v5.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.h, v8.h, v10.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 4, v0.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 15
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, v2.h, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, v3.l, 15
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 4, v3.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, v4.l, 15
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 12, v8.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 12, v1.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.h, v3.h, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.h, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT:    global_store_b32 v[0:1], v0, off
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: amdgpu_cs_v32i1:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 1, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, 1, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 1, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 3, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 1, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v10, 2, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 1, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 1, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 1, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 1, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 1, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 1, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 1, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v11, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 3, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 3, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v6, 2, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 3, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v2, 2, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 3, v15
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v14, 2, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v7, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v8, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 3, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v15, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 3, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 15, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v6, 1, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 1, v26
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 1, v28
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, 1, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 1, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 3, v4
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v12, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 3, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v2, 2, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v7, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v10, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 1, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v10, 1, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 1, v20
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 1, v18
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v14, 1, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 1, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 1, v30
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v8, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 3, v23
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, 2, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v12, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v12, 3, v19
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 2, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v15, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 3, v31
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 2, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 3, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 3, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v12, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 3, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v11, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 3, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v7, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v9, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v12, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v4, 4, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 15, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 15, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v6, 4, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 15, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 12, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v4, 12, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v2, 8, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v7, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    global_store_b32 v[0:1], v0, off
+; GFX11-FAKE16-NEXT:    s_endpgm
   store <32 x i1> %arg0, ptr addrspace(1) poison
   ret void
 }
diff --git a/llvm/test/CodeGen/AMDGPU/cc-update.ll b/llvm/test/CodeGen/AMDGPU/cc-update.ll
index fc24041fe771a..ee1feccc6334c 100644
--- a/llvm/test/CodeGen/AMDGPU/cc-update.ll
+++ b/llvm/test/CodeGen/AMDGPU/cc-update.ll
@@ -610,5 +610,3 @@ attributes #0 = { nounwind }
 attributes #1 = { nounwind "amdgpu-num-vgpr"="8" }
 attributes #2 = { nounwind "frame-pointer"="all" }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll b/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
index 7ce69fe2f4989..f78cb0daee5c9 100644
--- a/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
+++ b/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
@@ -473,5 +473,3 @@ for.body:
   br i1 %cond, label %for.body, label %for.exit
 }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/clamp-modifier.ll b/llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
index 81f79ea3c3fa8..f7c58ca9599b4 100644
--- a/llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
+++ b/llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
@@ -2,7 +2,8 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=SI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX8 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define amdgpu_kernel void @v_clamp_add_src_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
 ; SI-LABEL: v_clamp_add_src_f32:
@@ -482,18 +483,31 @@ define amdgpu_kernel void @v_clamp_add_src_f16_denorm(ptr addrspace(1) %out, ptr
 ; GFX9-NEXT:    global_store_short v0, v1, s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: v_clamp_add_src_f16_denorm:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u16 v1, v0, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_f16_e64 v1, v1, 1.0 clamp
-; GFX11-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: v_clamp_add_src_f16_denorm:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_f16_e64 v0.l, v0.l, 1.0 clamp
+; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: v_clamp_add_src_f16_denorm:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_f16_e64 v1, v1, 1.0 clamp
+; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %gep0 = getelementptr half, ptr addrspace(1) %aptr, i32 %tid
   %out.gep = getelementptr half, ptr addrspace(1) %out, i32 %tid
@@ -552,18 +566,31 @@ define amdgpu_kernel void @v_clamp_add_src_f16_no_denormals(ptr addrspace(1) %ou
 ; GFX9-NEXT:    global_store_short v0, v1, s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: v_clamp_add_src_f16_no_denormals:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u16 v1, v0, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_f16_e64 v1, v1, 1.0 clamp
-; GFX11-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: v_clamp_add_src_f16_no_denormals:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_f16_e64 v0.l, v0.l, 1.0 clamp
+; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: v_clamp_add_src_f16_no_denormals:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_f16_e64 v1, v1, 1.0 clamp
+; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %gep0 = getelementptr half, ptr addrspace(1) %aptr, i32 %tid
   %out.gep = getelementptr half, ptr addrspace(1) %out, i32 %tid
@@ -1525,22 +1552,39 @@ define amdgpu_kernel void @v_no_clamp_add_src_v2f16_f16_src(ptr addrspace(1) %ou
 ; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: v_no_clamp_add_src_v2f16_f16_src:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 1, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u16 v1, v1, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_f16_e32 v1, 1.0, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_pk_max_f16 v1, v1, v1 clamp
-; GFX11-NEXT:    global_store_b32 v0, v1, s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: v_no_clamp_add_src_v2f16_f16_src:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0x3ff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 2, v1
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v0, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_f16_e32 v0.l, 1.0, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_pk_max_f16 v0, v0, v0 clamp
+; GFX11-TRUE16-NEXT:    global_store_b32 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: v_no_clamp_add_src_v2f16_f16_src:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_u16 v1, v1, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_f16_e32 v1, 1.0, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_pk_max_f16 v1, v1, v1 clamp
+; GFX11-FAKE16-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %gep0 = getelementptr half, ptr addrspace(1) %aptr, i32 %tid
   %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid
diff --git a/llvm/test/CodeGen/AMDGPU/clamp.ll b/llvm/test/CodeGen/AMDGPU/clamp.ll
index 17c84d7371de1..3e0837b58aafc 100644
--- a/llvm/test/CodeGen/AMDGPU/clamp.ll
+++ b/llvm/test/CodeGen/AMDGPU/clamp.ll
@@ -2,8 +2,10 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX6 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
 
 define amdgpu_kernel void @v_clamp_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
 ; GFX6-LABEL: v_clamp_f32:
@@ -585,31 +587,57 @@ define amdgpu_kernel void @v_clamp_f16(ptr addrspace(1) %out, ptr addrspace(1) %
 ; GFX9-NEXT:    global_store_short v0, v1, s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: v_clamp_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u16 v1, v0, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_max_f16_e64 v1, v1, v1 clamp
-; GFX11-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX11-NEXT:    s_endpgm
-;
-; GFX12-LABEL: v_clamp_f16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u16 v1, v0, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_max_num_f16_e64 v1, v1, v1 clamp
-; GFX12-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: v_clamp_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e64 v0.l, v0.l, v0.l clamp
+; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: v_clamp_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e64 v1, v1, v1 clamp
+; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-TRUE16-LABEL: v_clamp_f16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e64 v0.l, v0.l, v0.l clamp
+; GFX12-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: v_clamp_f16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e64 v1, v1, v1 clamp
+; GFX12-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %gep0 = getelementptr half, ptr addrspace(1) %aptr, i32 %tid
   %out.gep = getelementptr half, ptr addrspace(1) %out, i32 %tid
@@ -667,31 +695,57 @@ define amdgpu_kernel void @v_clamp_neg_f16(ptr addrspace(1) %out, ptr addrspace(
 ; GFX9-NEXT:    global_store_short v0, v1, s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: v_clamp_neg_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u16 v1, v0, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_max_f16_e64 v1, -v1, -v1 clamp
-; GFX11-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX11-NEXT:    s_endpgm
-;
-; GFX12-LABEL: v_clamp_neg_f16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u16 v1, v0, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_max_num_f16_e64 v1, -v1, -v1 clamp
-; GFX12-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: v_clamp_neg_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l clamp
+; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: v_clamp_neg_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e64 v1, -v1, -v1 clamp
+; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-TRUE16-LABEL: v_clamp_neg_f16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e64 v0.l, -v0.l, -v0.l clamp
+; GFX12-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: v_clamp_neg_f16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e64 v1, -v1, -v1 clamp
+; GFX12-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %gep0 = getelementptr half, ptr addrspace(1) %aptr, i32 %tid
   %out.gep = getelementptr half, ptr addrspace(1) %out, i32 %tid
@@ -750,31 +804,57 @@ define amdgpu_kernel void @v_clamp_negabs_f16(ptr addrspace(1) %out, ptr addrspa
 ; GFX9-NEXT:    global_store_short v0, v1, s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: v_clamp_negabs_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u16 v1, v0, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_max_f16_e64 v1, -|v1|, -|v1| clamp
-; GFX11-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX11-NEXT:    s_endpgm
-;
-; GFX12-LABEL: v_clamp_negabs_f16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u16 v1, v0, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_max_num_f16_e64 v1, -|v1|, -|v1| clamp
-; GFX12-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: v_clamp_negabs_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e64 v0.l, -|v0.l|, -|v0.l| clamp
+; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: v_clamp_negabs_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e64 v1, -|v1|, -|v1| clamp
+; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-TRUE16-LABEL: v_clamp_negabs_f16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e64 v0.l, -|v0.l|, -|v0.l| clamp
+; GFX12-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: v_clamp_negabs_f16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e64 v1, -|v1|, -|v1| clamp
+; GFX12-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %gep0 = getelementptr half, ptr addrspace(1) %aptr, i32 %tid
   %out.gep = getelementptr half, ptr addrspace(1) %out, i32 %tid
diff --git a/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll b/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
index a60a16c9be47e..b93750114e191 100644
--- a/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
+++ b/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
@@ -1391,5 +1391,3 @@ attributes #0 = { nounwind readnone speculatable }
 attributes #1 = { nounwind convergent }
 attributes #2 = { nounwind }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll b/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
index 10d71a315fbf9..9d679779fed0e 100644
--- a/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
+++ b/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck %s -check-prefixes=GCN,GFX11
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-delay-alu=0 -enable-no-nans-fp-math < %s | FileCheck %s -check-prefixes=GCN,GFX11NONANS
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck %s -check-prefixes=GCN,GFX11,GFX11-TRUE16
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck %s -check-prefixes=GCN,GFX11,GFX11-FAKE16
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs -amdgpu-enable-delay-alu=0 -enable-no-nans-fp-math < %s | FileCheck %s -check-prefixes=GCN,GCN-TRUE16,GFX11NONANS,GFX11NONANS-TRUE16
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs -amdgpu-enable-delay-alu=0 -enable-no-nans-fp-math < %s | FileCheck %s -check-prefixes=GCN,GCN-FAKE16,GFX11NONANS,GFX11NONANS-FAKE16
 
 ; The tests check the following optimization of DAGCombiner:
 ; CMP(A,C)||CMP(B,C) => CMP(MIN/MAX(A,B), C)
@@ -861,13 +863,21 @@ define i1 @test58(double %arg1, double %arg2, double %arg3) #0 {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test58:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
-; GFX11NONANS-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test58:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GCN-TRUE16-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test58:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GCN-FAKE16-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ugt double %arg1, %arg3
   %cmp2 = fcmp ugt double %arg2, %arg3
   %and1  = and i1 %cmp1, %cmp2
@@ -883,13 +893,21 @@ define i1 @test59(float %arg1, float %arg2, float %arg3) #0 {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test59:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_min_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test59:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_min_f32_e32 v0, v0, v1
+; GCN-TRUE16-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test59:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_min_f32_e32 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp uge float %arg1, %arg3
   %cmp2 = fcmp uge float %arg2, %arg3
   %and1  = and i1 %cmp1, %cmp2
@@ -905,13 +923,21 @@ define i1 @test60(float %arg1, float %arg2, float %arg3) #0 {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test60:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test60:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_max_f32_e32 v0, v0, v1
+; GCN-TRUE16-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test60:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_max_f32_e32 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ule float %arg1, %arg3
   %cmp2 = fcmp ule float %arg2, %arg3
   %and1  = and i1 %cmp1, %cmp2
@@ -927,13 +953,21 @@ define i1 @test61(double %arg1, double %arg2, double %arg3) #0 {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test61:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
-; GFX11NONANS-NEXT:    v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test61:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GCN-TRUE16-NEXT:    v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test61:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GCN-FAKE16-NEXT:    v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ult double %arg1, %arg3
   %cmp2 = fcmp ult double %arg2, %arg3
   %and1 = and i1 %cmp1, %cmp2
@@ -1090,13 +1124,21 @@ define i1 @test70(float %arg1, float %arg2, float %arg3) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test70:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_min_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test70:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_min_f32_e32 v0, v0, v1
+; GCN-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test70:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_min_f32_e32 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp olt float %var1, %arg3
@@ -1151,13 +1193,21 @@ define i1 @test73(float %arg1, float %arg2, float %arg3) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test73:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test73:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_max_f32_e32 v0, v0, v1
+; GCN-TRUE16-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test73:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_max_f32_e32 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp oge float %var1, %arg3
@@ -1177,15 +1227,25 @@ define i1 @test74(double %arg1, double %arg2, double %arg3) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test74:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX11NONANS-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
-; GFX11NONANS-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
-; GFX11NONANS-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test74:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GCN-TRUE16-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GCN-TRUE16-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GCN-TRUE16-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test74:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GCN-FAKE16-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GCN-FAKE16-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GCN-FAKE16-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call double @llvm.canonicalize.f64(double %arg1)
   %var2 = call double @llvm.canonicalize.f64(double %arg2)
   %cmp1 = fcmp ugt double %var1, %arg3
@@ -1204,13 +1264,21 @@ define i1 @test75(float %arg1, float %arg2, float %arg3) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test75:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_min_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test75:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_min_f32_e32 v0, v0, v1
+; GCN-TRUE16-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test75:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_min_f32_e32 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp uge float %var1, %arg3
@@ -1229,13 +1297,21 @@ define i1 @test76(float %arg1, float %arg2, float %arg3) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test76:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test76:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_max_f32_e32 v0, v0, v1
+; GCN-TRUE16-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test76:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_max_f32_e32 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp ule float %var1, %arg3
@@ -1255,15 +1331,25 @@ define i1 @test77(double %arg1, double %arg2, double %arg3) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test77:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX11NONANS-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
-; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
-; GFX11NONANS-NEXT:    v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test77:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GCN-TRUE16-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GCN-TRUE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GCN-TRUE16-NEXT:    v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test77:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GCN-FAKE16-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GCN-FAKE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GCN-FAKE16-NEXT:    v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call double @llvm.canonicalize.f64(double %arg1)
   %var2 = call double @llvm.canonicalize.f64(double %arg2)
   %cmp1 = fcmp ult double %var1, %arg3
@@ -1295,13 +1381,21 @@ define i1 @test79(float %arg1, float %arg2, float %arg3) #0 {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test79:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test79:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_max_f32_e32 v0, v0, v1
+; GCN-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test79:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_max_f32_e32 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ult float %arg1, %arg3
   %cmp2 = fcmp ugt float %arg3, %arg2
   %and1  = and i1 %cmp1, %cmp2
@@ -1371,13 +1465,21 @@ define i1 @test83(float %arg1, float %arg2, float %arg3) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test83:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test83:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_max_f32_e32 v0, v0, v1
+; GCN-TRUE16-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test83:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_max_f32_e32 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp ule float %var1, %arg3
@@ -1387,23 +1489,41 @@ define i1 @test83(float %arg1, float %arg2, float %arg3) {
 }
 
 define i1 @test84(half %arg1, half %arg2, half %arg3) {
-; GFX11-LABEL: test84:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX11-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test84:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.h, v1.l, v1.l
+; GFX11-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0.l, v2.l
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test84:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX11NONANS-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-LABEL: test84:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX11-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-TRUE16-LABEL: test84:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v1.l
+; GCN-TRUE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0.l, v2.l
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test84:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call half @llvm.canonicalize.f16(half %arg1)
   %var2 = call half @llvm.canonicalize.f16(half %arg2)
   %cmp1 = fcmp olt half %var1, %arg3
@@ -1413,31 +1533,53 @@ define i1 @test84(half %arg1, half %arg2, half %arg3) {
 }
 
 define <2 x i1> @test85(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
-; GFX11-LABEL: test85:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_pk_max_f16 v0, v0, v0
-; GFX11-NEXT:    v_pk_max_f16 v1, v1, v1
-; GFX11-NEXT:    v_pk_min_f16 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-NEXT:    v_cmp_le_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT:    v_cmp_le_f16_e32 vcc_lo, v3, v1
-; GFX11-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test85:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_pk_max_f16 v0, v0, v0
+; GFX11-TRUE16-NEXT:    v_pk_max_f16 v1, v1, v1
+; GFX11-TRUE16-NEXT:    v_pk_min_f16 v1, v0, v1
+; GFX11-TRUE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v1.l, v2.l
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v1.h, v2.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test85:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_pk_min_f16 v0, v0, v1
-; GFX11NONANS-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
-; GFX11NONANS-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX11NONANS-NEXT:    v_cmp_le_f16_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    v_cmp_le_f16_e32 vcc_lo, v3, v1
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-LABEL: test85:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_pk_max_f16 v0, v0, v0
+; GFX11-FAKE16-NEXT:    v_pk_max_f16 v1, v1, v1
+; GFX11-FAKE16-NEXT:    v_pk_min_f16 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-FAKE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v0, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v3, v1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-TRUE16-LABEL: test85:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_pk_min_f16 v1, v0, v1
+; GCN-TRUE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v1.l, v2.l
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v1.h, v2.h
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test85:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_pk_min_f16 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GCN-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GCN-FAKE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v3, v1
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg1)
   %var2 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg2)
   %cmp1 = fcmp ole <2 x half> %var1, %arg3
@@ -1447,31 +1589,53 @@ define <2 x i1> @test85(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
 }
 
 define <2 x i1> @test86(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
-; GFX11-LABEL: test86:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_pk_max_f16 v0, v0, v0
-; GFX11-NEXT:    v_pk_max_f16 v1, v1, v1
-; GFX11-NEXT:    v_pk_max_f16 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v3, v1
-; GFX11-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test86:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_pk_max_f16 v0, v0, v0
+; GFX11-TRUE16-NEXT:    v_pk_max_f16 v1, v1, v1
+; GFX11-TRUE16-NEXT:    v_pk_max_f16 v1, v0, v1
+; GFX11-TRUE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v1.l, v2.l
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v1.h, v2.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test86:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_pk_max_f16 v0, v0, v1
-; GFX11NONANS-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
-; GFX11NONANS-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX11NONANS-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v3, v1
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-LABEL: test86:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_pk_max_f16 v0, v0, v0
+; GFX11-FAKE16-NEXT:    v_pk_max_f16 v1, v1, v1
+; GFX11-FAKE16-NEXT:    v_pk_max_f16 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-FAKE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v0, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v3, v1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-TRUE16-LABEL: test86:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_pk_max_f16 v1, v0, v1
+; GCN-TRUE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v1.l, v2.l
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v1.h, v2.h
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test86:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_pk_max_f16 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GCN-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GCN-FAKE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v3, v1
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg1)
   %var2 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg2)
   %cmp1 = fcmp ogt <2 x half> %var1, %arg3
@@ -1481,23 +1645,41 @@ define <2 x i1> @test86(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
 }
 
 define i1 @test87(half %arg1, half %arg2, half %arg3) {
-; GFX11-LABEL: test87:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test87:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.h, v1.l, v1.l
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0.l, v2.l
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test87:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX11NONANS-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-LABEL: test87:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-TRUE16-LABEL: test87:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v1.l
+; GCN-TRUE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0.l, v2.l
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test87:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call half @llvm.canonicalize.f16(half %arg1)
   %var2 = call half @llvm.canonicalize.f16(half %arg2)
   %cmp1 = fcmp oge half %var1, %arg3
@@ -1507,31 +1689,53 @@ define i1 @test87(half %arg1, half %arg2, half %arg3) {
 }
 
 define <2 x i1> @test88(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
-; GFX11-LABEL: test88:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_pk_max_f16 v0, v0, v0
-; GFX11-NEXT:    v_pk_max_f16 v1, v1, v1
-; GFX11-NEXT:    v_pk_min_f16 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v3, v1
-; GFX11-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test88:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_pk_max_f16 v0, v0, v0
+; GFX11-TRUE16-NEXT:    v_pk_max_f16 v1, v1, v1
+; GFX11-TRUE16-NEXT:    v_pk_min_f16 v1, v0, v1
+; GFX11-TRUE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v1.l, v2.l
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v1.h, v2.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test88:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_pk_min_f16 v0, v0, v1
-; GFX11NONANS-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
-; GFX11NONANS-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX11NONANS-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v3, v1
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-LABEL: test88:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_pk_max_f16 v0, v0, v0
+; GFX11-FAKE16-NEXT:    v_pk_max_f16 v1, v1, v1
+; GFX11-FAKE16-NEXT:    v_pk_min_f16 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-FAKE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v0, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v3, v1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-TRUE16-LABEL: test88:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_pk_min_f16 v1, v0, v1
+; GCN-TRUE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v1.l, v2.l
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v1.h, v2.h
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test88:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_pk_min_f16 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GCN-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GCN-FAKE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v3, v1
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg1)
   %var2 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg2)
   %cmp1 = fcmp ugt <2 x half> %var1, %arg3
@@ -1541,23 +1745,41 @@ define <2 x i1> @test88(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
 }
 
 define i1 @test89(half %arg1, half %arg2, half %arg3) {
-; GFX11-LABEL: test89:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX11-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test89:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.h, v1.l, v1.l
+; GFX11-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0.l, v2.l
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test89:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX11NONANS-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-LABEL: test89:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX11-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-TRUE16-LABEL: test89:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v1.l
+; GCN-TRUE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0.l, v2.l
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test89:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call half @llvm.canonicalize.f16(half %arg1)
   %var2 = call half @llvm.canonicalize.f16(half %arg2)
   %cmp1 = fcmp uge half %var1, %arg3
@@ -1567,23 +1789,41 @@ define i1 @test89(half %arg1, half %arg2, half %arg3) {
 }
 
 define i1 @test90(half %arg1, half %arg2, half %arg3) {
-; GFX11-LABEL: test90:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test90:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.h, v1.l, v1.l
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0.l, v2.l
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test90:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX11NONANS-NEXT:    v_cmp_le_f16_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-LABEL: test90:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-TRUE16-LABEL: test90:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v1.l
+; GCN-TRUE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v0.l, v2.l
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test90:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call half @llvm.canonicalize.f16(half %arg1)
   %var2 = call half @llvm.canonicalize.f16(half %arg2)
   %cmp1 = fcmp ule half %var1, %arg3
@@ -1593,31 +1833,53 @@ define i1 @test90(half %arg1, half %arg2, half %arg3) {
 }
 
 define <2 x i1> @test91(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
-; GFX11-LABEL: test91:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_pk_max_f16 v0, v0, v0
-; GFX11-NEXT:    v_pk_max_f16 v1, v1, v1
-; GFX11-NEXT:    v_pk_max_f16 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v3, v1
-; GFX11-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test91:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_pk_max_f16 v0, v0, v0
+; GFX11-TRUE16-NEXT:    v_pk_max_f16 v1, v1, v1
+; GFX11-TRUE16-NEXT:    v_pk_max_f16 v1, v0, v1
+; GFX11-TRUE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v1.l, v2.l
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v1.h, v2.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test91:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_pk_max_f16 v0, v0, v1
-; GFX11NONANS-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
-; GFX11NONANS-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX11NONANS-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v3, v1
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-LABEL: test91:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_pk_max_f16 v0, v0, v0
+; GFX11-FAKE16-NEXT:    v_pk_max_f16 v1, v1, v1
+; GFX11-FAKE16-NEXT:    v_pk_max_f16 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-FAKE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v0, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v3, v1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-TRUE16-LABEL: test91:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_pk_max_f16 v1, v0, v1
+; GCN-TRUE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v1.l, v2.l
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v1.h, v2.h
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test91:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_pk_max_f16 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GCN-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GCN-FAKE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v3, v1
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg1)
   %var2 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg2)
   %cmp1 = fcmp ult <2 x half> %var1, %arg3
@@ -2021,13 +2283,21 @@ define i1 @test108(float %arg1, float %arg2, float %arg3, float %C) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test108:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_max3_f32 v0, v0, v1, v2
-; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v3
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test108:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_max3_f32 v0, v0, v1, v2
+; GCN-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v3
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test108:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_max3_f32 v0, v0, v1, v2
+; GCN-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v3
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ult float %arg1, %C
   %cmp2 = fcmp ult float %arg2, %C
   %cmp3 = fcmp ult float %arg3, %C
@@ -2049,15 +2319,25 @@ define i1 @test109(float %arg1, float %arg2, float %arg3, float %arg4, float %C)
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test109:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v3
-; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v4
-; GFX11NONANS-NEXT:    v_cmp_gt_f32_e64 s0, v1, v4
-; GFX11NONANS-NEXT:    s_or_b32 s0, vcc_lo, s0
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test109:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v3
+; GCN-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v4
+; GCN-TRUE16-NEXT:    v_cmp_gt_f32_e64 s0, v1, v4
+; GCN-TRUE16-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test109:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v3
+; GCN-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v4
+; GCN-FAKE16-NEXT:    v_cmp_gt_f32_e64 s0, v1, v4
+; GCN-FAKE16-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %C
   %cmp2 = fcmp olt float %arg2, %C
   %cmp3 = fcmp ogt float %arg3, %C
@@ -2107,16 +2387,27 @@ define i1 @test111(float %arg1, float %arg2, float %arg3, float %arg4, float %ar
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test111:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_min_f32_e32 v2, v2, v3
-; GFX11NONANS-NEXT:    v_min3_f32 v0, v0, v1, v2
-; GFX11NONANS-NEXT:    v_min_f32_e32 v0, v0, v4
-; GFX11NONANS-NEXT:    v_min3_f32 v0, v5, v6, v0
-; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test111:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_min_f32_e32 v2, v2, v3
+; GCN-TRUE16-NEXT:    v_min3_f32 v0, v0, v1, v2
+; GCN-TRUE16-NEXT:    v_min_f32_e32 v0, v0, v4
+; GCN-TRUE16-NEXT:    v_min3_f32 v0, v5, v6, v0
+; GCN-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test111:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_min_f32_e32 v2, v2, v3
+; GCN-FAKE16-NEXT:    v_min3_f32 v0, v0, v1, v2
+; GCN-FAKE16-NEXT:    v_min_f32_e32 v0, v0, v4
+; GCN-FAKE16-NEXT:    v_min3_f32 v0, v5, v6, v0
+; GCN-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %C
   %cmp2 = fcmp olt float %arg2, %C
   %or1  = or i1 %cmp1, %cmp2
@@ -2150,16 +2441,27 @@ define i1 @test112(float %arg1, float %arg2, float %arg3, float %arg4, float %ar
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test112:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_min_f32_e32 v2, v2, v3
-; GFX11NONANS-NEXT:    v_min3_f32 v0, v0, v1, v2
-; GFX11NONANS-NEXT:    v_min_f32_e32 v0, v0, v4
-; GFX11NONANS-NEXT:    v_min3_f32 v0, v5, v6, v0
-; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test112:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_min_f32_e32 v2, v2, v3
+; GCN-TRUE16-NEXT:    v_min3_f32 v0, v0, v1, v2
+; GCN-TRUE16-NEXT:    v_min_f32_e32 v0, v0, v4
+; GCN-TRUE16-NEXT:    v_min3_f32 v0, v5, v6, v0
+; GCN-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test112:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_min_f32_e32 v2, v2, v3
+; GCN-FAKE16-NEXT:    v_min3_f32 v0, v0, v1, v2
+; GCN-FAKE16-NEXT:    v_min_f32_e32 v0, v0, v4
+; GCN-FAKE16-NEXT:    v_min3_f32 v0, v5, v6, v0
+; GCN-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v8
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %C
   %cmp2 = fcmp olt float %arg2, %C
   %or1  = or i1 %cmp1, %cmp2
@@ -2190,13 +2492,21 @@ define i1 @test113(float %arg1, float %arg2, float %arg3, float %C) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test113:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_maxmin_f32 v0, v0, v1, v2
-; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v3
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test113:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_maxmin_f32 v0, v0, v1, v2
+; GCN-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v3
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test113:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_maxmin_f32 v0, v0, v1, v2
+; GCN-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v3
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ult float %arg1, %C
   %cmp2 = fcmp ult float %arg2, %C
   %cmp3 = fcmp olt float %arg3, %C
@@ -2217,15 +2527,25 @@ define i1 @test114(float %arg1, float %arg2, float %arg3, float %C) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test114:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v2, v3
-; GFX11NONANS-NEXT:    v_cmp_gt_f32_e64 s0, v0, v3
-; GFX11NONANS-NEXT:    s_and_b32 s0, s0, vcc_lo
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test114:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_max_f32_e32 v0, v0, v1
+; GCN-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v2, v3
+; GCN-TRUE16-NEXT:    v_cmp_gt_f32_e64 s0, v0, v3
+; GCN-TRUE16-NEXT:    s_and_b32 s0, s0, vcc_lo
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test114:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_max_f32_e32 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v2, v3
+; GCN-FAKE16-NEXT:    v_cmp_gt_f32_e64 s0, v0, v3
+; GCN-FAKE16-NEXT:    s_and_b32 s0, s0, vcc_lo
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ogt float %arg1, %C
   %cmp2 = fcmp ogt float %arg2, %C
   %cmp3 = fcmp ult float %arg3, %C
@@ -2247,14 +2567,23 @@ define i1 @test115(float %arg1, float %arg2, float %arg3, float %arg4, float %C)
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test115:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_max_f32_e32 v2, v2, v3
-; GFX11NONANS-NEXT:    v_min3_f32 v0, v0, v1, v2
-; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v4
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test115:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_max_f32_e32 v2, v2, v3
+; GCN-TRUE16-NEXT:    v_min3_f32 v0, v0, v1, v2
+; GCN-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v4
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test115:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_max_f32_e32 v2, v2, v3
+; GCN-FAKE16-NEXT:    v_min3_f32 v0, v0, v1, v2
+; GCN-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v4
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %C
   %cmp2 = fcmp olt float %arg2, %C
   %var3 = call float @llvm.canonicalize.f32(float %arg3)
@@ -2290,22 +2619,39 @@ define i1 @test116(float %arg1, float %arg2, float %arg3, float %arg4, float %ar
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test116:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_min_f32_e32 v8, v8, v9
-; GFX11NONANS-NEXT:    v_dual_max_f32 v2, v2, v3 :: v_dual_min_f32 v3, v4, v5
-; GFX11NONANS-NEXT:    v_max_f32_e32 v4, v6, v7
-; GFX11NONANS-NEXT:    v_min3_f32 v0, v0, v1, v8
-; GFX11NONANS-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v10
-; GFX11NONANS-NEXT:    v_cmp_lt_f32_e64 s0, v3, v10
-; GFX11NONANS-NEXT:    v_cmp_gt_f32_e64 s1, v4, v10
-; GFX11NONANS-NEXT:    v_cmp_lt_f32_e64 s2, v0, v10
-; GFX11NONANS-NEXT:    s_or_b32 s0, s0, s1
-; GFX11NONANS-NEXT:    s_or_b32 s1, s2, vcc_lo
-; GFX11NONANS-NEXT:    s_or_b32 s0, s0, s1
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test116:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_min_f32_e32 v8, v8, v9
+; GCN-TRUE16-NEXT:    v_dual_max_f32 v2, v2, v3 :: v_dual_min_f32 v3, v4, v5
+; GCN-TRUE16-NEXT:    v_max_f32_e32 v4, v6, v7
+; GCN-TRUE16-NEXT:    v_min3_f32 v0, v0, v1, v8
+; GCN-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v10
+; GCN-TRUE16-NEXT:    v_cmp_lt_f32_e64 s0, v3, v10
+; GCN-TRUE16-NEXT:    v_cmp_gt_f32_e64 s1, v4, v10
+; GCN-TRUE16-NEXT:    v_cmp_lt_f32_e64 s2, v0, v10
+; GCN-TRUE16-NEXT:    s_or_b32 s0, s0, s1
+; GCN-TRUE16-NEXT:    s_or_b32 s1, s2, vcc_lo
+; GCN-TRUE16-NEXT:    s_or_b32 s0, s0, s1
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test116:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_min_f32_e32 v8, v8, v9
+; GCN-FAKE16-NEXT:    v_dual_max_f32 v2, v2, v3 :: v_dual_min_f32 v3, v4, v5
+; GCN-FAKE16-NEXT:    v_max_f32_e32 v4, v6, v7
+; GCN-FAKE16-NEXT:    v_min3_f32 v0, v0, v1, v8
+; GCN-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v10
+; GCN-FAKE16-NEXT:    v_cmp_lt_f32_e64 s0, v3, v10
+; GCN-FAKE16-NEXT:    v_cmp_gt_f32_e64 s1, v4, v10
+; GCN-FAKE16-NEXT:    v_cmp_lt_f32_e64 s2, v0, v10
+; GCN-FAKE16-NEXT:    s_or_b32 s0, s0, s1
+; GCN-FAKE16-NEXT:    s_or_b32 s1, s2, vcc_lo
+; GCN-FAKE16-NEXT:    s_or_b32 s0, s0, s1
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %C
   %cmp2 = fcmp olt float %arg2, %C
   %cmp3 = fcmp ogt float %arg3, %C
@@ -2351,23 +2697,41 @@ define i1 @test117(float %arg1, float %arg2, float %arg3, float %arg4, float %ar
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test117:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_min_f32_e32 v6, v6, v7
-; GFX11NONANS-NEXT:    v_dual_min_f32 v0, v0, v1 :: v_dual_min_f32 v1, v10, v11
-; GFX11NONANS-NEXT:    v_min_f32_e32 v2, v2, v3
-; GFX11NONANS-NEXT:    v_min3_f32 v3, v4, v5, v6
-; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v12
-; GFX11NONANS-NEXT:    v_min3_f32 v0, v8, v9, v1
-; GFX11NONANS-NEXT:    v_cmp_lt_f32_e64 s0, v2, v13
-; GFX11NONANS-NEXT:    v_cmp_lt_f32_e64 s1, v3, v13
-; GFX11NONANS-NEXT:    v_cmp_lt_f32_e64 s2, v0, v12
-; GFX11NONANS-NEXT:    s_or_b32 s0, vcc_lo, s0
-; GFX11NONANS-NEXT:    s_or_b32 s0, s0, s1
-; GFX11NONANS-NEXT:    s_or_b32 s0, s2, s0
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test117:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_min_f32_e32 v6, v6, v7
+; GCN-TRUE16-NEXT:    v_dual_min_f32 v0, v0, v1 :: v_dual_min_f32 v1, v10, v11
+; GCN-TRUE16-NEXT:    v_min_f32_e32 v2, v2, v3
+; GCN-TRUE16-NEXT:    v_min3_f32 v3, v4, v5, v6
+; GCN-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v12
+; GCN-TRUE16-NEXT:    v_min3_f32 v0, v8, v9, v1
+; GCN-TRUE16-NEXT:    v_cmp_lt_f32_e64 s0, v2, v13
+; GCN-TRUE16-NEXT:    v_cmp_lt_f32_e64 s1, v3, v13
+; GCN-TRUE16-NEXT:    v_cmp_lt_f32_e64 s2, v0, v12
+; GCN-TRUE16-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GCN-TRUE16-NEXT:    s_or_b32 s0, s0, s1
+; GCN-TRUE16-NEXT:    s_or_b32 s0, s2, s0
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test117:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_min_f32_e32 v6, v6, v7
+; GCN-FAKE16-NEXT:    v_dual_min_f32 v0, v0, v1 :: v_dual_min_f32 v1, v10, v11
+; GCN-FAKE16-NEXT:    v_min_f32_e32 v2, v2, v3
+; GCN-FAKE16-NEXT:    v_min3_f32 v3, v4, v5, v6
+; GCN-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v12
+; GCN-FAKE16-NEXT:    v_min3_f32 v0, v8, v9, v1
+; GCN-FAKE16-NEXT:    v_cmp_lt_f32_e64 s0, v2, v13
+; GCN-FAKE16-NEXT:    v_cmp_lt_f32_e64 s1, v3, v13
+; GCN-FAKE16-NEXT:    v_cmp_lt_f32_e64 s2, v0, v12
+; GCN-FAKE16-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GCN-FAKE16-NEXT:    s_or_b32 s0, s0, s1
+; GCN-FAKE16-NEXT:    s_or_b32 s0, s2, s0
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %C1
   %cmp2 = fcmp olt float %arg2, %C1
   %cmp3 = fcmp olt float %arg3, %C2
@@ -2635,14 +2999,41 @@ define i1 @test130(i32 %arg1, i32 %arg2, i32 %arg3) {
 }
 
 define i1 @test131(i16 %arg1, i32 %arg2) {
-; GCN-LABEL: test131:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 10, v0
-; GCN-NEXT:    v_cmp_gt_u32_e64 s0, 10, v1
-; GCN-NEXT:    s_or_b32 s0, vcc_lo, s0
-; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test131:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 10, v1
+; GFX11-TRUE16-NEXT:    v_cmp_gt_u16_e64 s0, 10, v0.l
+; GFX11-TRUE16-NEXT:    s_or_b32 s0, s0, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test131:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 10, v0
+; GFX11-FAKE16-NEXT:    v_cmp_gt_u32_e64 s0, 10, v1
+; GFX11-FAKE16-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-TRUE16-LABEL: test131:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 10, v1
+; GCN-TRUE16-NEXT:    v_cmp_gt_u16_e64 s0, 10, v0.l
+; GCN-TRUE16-NEXT:    s_or_b32 s0, s0, vcc_lo
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test131:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 10, v0
+; GCN-FAKE16-NEXT:    v_cmp_gt_u32_e64 s0, 10, v1
+; GCN-FAKE16-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = icmp ult i16 %arg1, 10
   %cmp2 = icmp ult i32 %arg2, 10
   %or = or i1 %cmp1, %cmp2
@@ -2695,13 +3086,21 @@ define i1 @test134(float %arg1, float %arg2, float %arg3) #0 {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test134:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test134:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_max_f32_e32 v0, v0, v1
+; GCN-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test134:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_max_f32_e32 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %arg3
   %cmp2 = fcmp ogt float %arg3, %arg2
   %and1  = and i1 %cmp1, %cmp2
@@ -2718,13 +3117,21 @@ define i1 @test135(float %arg1, float %arg2, float %arg3) #0 {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test135:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_min_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test135:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_min_f32_e32 v0, v0, v1
+; GCN-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test135:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_min_f32_e32 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ult float %arg1, %arg3
   %cmp2 = fcmp ugt float %arg3, %arg2
   %or1  = or i1 %cmp1, %cmp2
@@ -2743,15 +3150,25 @@ define i1 @test136(double %arg1, double %arg2, double %arg3) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test136:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX11NONANS-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
-; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
-; GFX11NONANS-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test136:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GCN-TRUE16-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GCN-TRUE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GCN-TRUE16-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test136:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GCN-FAKE16-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GCN-FAKE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GCN-FAKE16-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call double @llvm.canonicalize.f64(double %arg1)
   %var2 = call double @llvm.canonicalize.f64(double %arg2)
   %cmp1 = fcmp ole double %var1, %arg3
@@ -2771,13 +3188,21 @@ define i1 @test137(float %arg1, float %arg2, float %arg3) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test137:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_min_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test137:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_min_f32_e32 v0, v0, v1
+; GCN-TRUE16-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test137:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_min_f32_e32 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp ule float %var1, %arg3
@@ -2796,13 +3221,21 @@ define i1 @test138(float %arg1, float %arg2, float %arg3) #0 {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test138:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test138:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_max_f32_e32 v0, v0, v1
+; GCN-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test138:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_max_f32_e32 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp olt float %arg1, %arg3
   %cmp2 = fcmp olt float %arg2, %arg3
   %and1  = and i1 %cmp1, %cmp2
@@ -2819,13 +3252,21 @@ define i1 @test139(double %arg1, double %arg2, double %arg3) #0 {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test139:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
-; GFX11NONANS-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test139:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GCN-TRUE16-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test139:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GCN-FAKE16-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ole double %arg1, %arg3
   %cmp2 = fcmp ole double %arg2, %arg3
   %and1  = and i1 %cmp1, %cmp2
@@ -2842,13 +3283,21 @@ define i1 @test140(double %arg1, double %arg2, double %arg3) #0 {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test140:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
-; GFX11NONANS-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test140:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GCN-TRUE16-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test140:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GCN-FAKE16-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ogt double %arg1, %arg3
   %cmp2 = fcmp ogt double %arg2, %arg3
   %and1  = and i1 %cmp1, %cmp2
@@ -2865,13 +3314,21 @@ define i1 @test141(float %arg1, float %arg2, float %arg3) #0 {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test141:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_min_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test141:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_min_f32_e32 v0, v0, v1
+; GCN-TRUE16-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test141:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_min_f32_e32 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp oge float %arg1, %arg3
   %cmp2 = fcmp oge float %arg2, %arg3
   %and1  = and i1 %cmp1, %cmp2
@@ -2888,13 +3345,21 @@ define i1 @test142(double %arg1, double %arg2, double %arg3) #0 {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test142:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
-; GFX11NONANS-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test142:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GCN-TRUE16-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test142:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GCN-FAKE16-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ugt double %arg1, %arg3
   %cmp2 = fcmp ugt double %arg2, %arg3
   %or1  = or i1 %cmp1, %cmp2
@@ -2911,13 +3376,21 @@ define i1 @test143(float %arg1, float %arg2, float %arg3) #0 {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test143:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test143:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_max_f32_e32 v0, v0, v1
+; GCN-TRUE16-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test143:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_max_f32_e32 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp uge float %arg1, %arg3
   %cmp2 = fcmp uge float %arg2, %arg3
   %or1  = or i1 %cmp1, %cmp2
@@ -2934,13 +3407,21 @@ define i1 @test144(float %arg1, float %arg2, float %arg3) #0 {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test144:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_min_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test144:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_min_f32_e32 v0, v0, v1
+; GCN-TRUE16-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test144:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_min_f32_e32 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ule float %arg1, %arg3
   %cmp2 = fcmp ule float %arg2, %arg3
   %or1  = or i1 %cmp1, %cmp2
@@ -2957,13 +3438,21 @@ define i1 @test145(double %arg1, double %arg2, double %arg3) #0 {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test145:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
-; GFX11NONANS-NEXT:    v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test145:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GCN-TRUE16-NEXT:    v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test145:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GCN-FAKE16-NEXT:    v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp1 = fcmp ult double %arg1, %arg3
   %cmp2 = fcmp ult double %arg2, %arg3
   %or1 = or i1 %cmp1, %cmp2
@@ -2981,13 +3470,21 @@ define i1 @test146(float %arg1, float %arg2, float %arg3) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test146:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test146:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_max_f32_e32 v0, v0, v1
+; GCN-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test146:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_max_f32_e32 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp olt float %var1, %arg3
@@ -3008,15 +3505,25 @@ define i1 @test147(double %arg1, double %arg2, double %arg3) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test147:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX11NONANS-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
-; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
-; GFX11NONANS-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test147:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GCN-TRUE16-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GCN-TRUE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GCN-TRUE16-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test147:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GCN-FAKE16-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GCN-FAKE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GCN-FAKE16-NEXT:    v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call double @llvm.canonicalize.f64(double %arg1)
   %var2 = call double @llvm.canonicalize.f64(double %arg2)
   %cmp1 = fcmp ole double %var1, %arg3
@@ -3037,15 +3544,25 @@ define i1 @test148(double %arg1, double %arg2, double %arg3) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test148:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX11NONANS-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
-; GFX11NONANS-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
-; GFX11NONANS-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test148:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GCN-TRUE16-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GCN-TRUE16-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GCN-TRUE16-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test148:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GCN-FAKE16-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GCN-FAKE16-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GCN-FAKE16-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call double @llvm.canonicalize.f64(double %arg1)
   %var2 = call double @llvm.canonicalize.f64(double %arg2)
   %cmp1 = fcmp ogt double %var1, %arg3
@@ -3065,13 +3582,21 @@ define i1 @test149(float %arg1, float %arg2, float %arg3) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test149:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_min_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test149:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_min_f32_e32 v0, v0, v1
+; GCN-TRUE16-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test149:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_min_f32_e32 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp oge float %var1, %arg3
@@ -3092,15 +3617,25 @@ define i1 @test150(double %arg1, double %arg2, double %arg3) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test150:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX11NONANS-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
-; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
-; GFX11NONANS-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test150:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GCN-TRUE16-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GCN-TRUE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GCN-TRUE16-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test150:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GCN-FAKE16-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GCN-FAKE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[2:3]
+; GCN-FAKE16-NEXT:    v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call double @llvm.canonicalize.f64(double %arg1)
   %var2 = call double @llvm.canonicalize.f64(double %arg2)
   %cmp1 = fcmp ugt double %var1, %arg3
@@ -3120,13 +3655,21 @@ define i1 @test151(float %arg1, float %arg2, float %arg3) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test151:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_max_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test151:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_max_f32_e32 v0, v0, v1
+; GCN-TRUE16-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test151:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_max_f32_e32 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_cmp_ge_f32_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp uge float %var1, %arg3
@@ -3146,13 +3689,21 @@ define i1 @test152(float %arg1, float %arg2, float %arg3) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test152:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_min_f32_e32 v0, v0, v1
-; GFX11NONANS-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test152:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_min_f32_e32 v0, v0, v1
+; GCN-TRUE16-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test152:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_min_f32_e32 v0, v0, v1
+; GCN-FAKE16-NEXT:    v_cmp_le_f32_e32 vcc_lo, v0, v2
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call float @llvm.canonicalize.f32(float %arg1)
   %var2 = call float @llvm.canonicalize.f32(float %arg2)
   %cmp1 = fcmp ule float %var1, %arg3
@@ -3173,15 +3724,25 @@ define i1 @test153(double %arg1, double %arg2, double %arg3) {
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11NONANS-LABEL: test153:
-; GFX11NONANS:       ; %bb.0:
-; GFX11NONANS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11NONANS-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
-; GFX11NONANS-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
-; GFX11NONANS-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
-; GFX11NONANS-NEXT:    v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX11NONANS-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11NONANS-NEXT:    s_setpc_b64 s[30:31]
+; GCN-TRUE16-LABEL: test153:
+; GCN-TRUE16:       ; %bb.0:
+; GCN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-TRUE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GCN-TRUE16-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GCN-TRUE16-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GCN-TRUE16-NEXT:    v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-FAKE16-LABEL: test153:
+; GCN-FAKE16:       ; %bb.0:
+; GCN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-FAKE16-NEXT:    v_max_f64 v[0:1], v[0:1], v[0:1]
+; GCN-FAKE16-NEXT:    v_max_f64 v[2:3], v[2:3], v[2:3]
+; GCN-FAKE16-NEXT:    v_min_f64 v[0:1], v[0:1], v[2:3]
+; GCN-FAKE16-NEXT:    v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5]
+; GCN-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GCN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %var1 = call double @llvm.canonicalize.f64(double %arg1)
   %var2 = call double @llvm.canonicalize.f64(double %arg2)
   %cmp1 = fcmp ult double %var1, %arg3
@@ -3197,3 +3758,7 @@ declare <2 x half> @llvm.canonicalize.v2f16(<2 x half>)
 
 attributes #0 = { nounwind "amdgpu-ieee"="false" }
 attributes #1 = { nounwind "unsafe-fp-math"="true" "no-nans-fp-math"="true" }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11NONANS: {{.*}}
+; GFX11NONANS-FAKE16: {{.*}}
+; GFX11NONANS-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll b/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
index b3ef8ed129d33..93cb11b82e0ed 100644
--- a/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
+++ b/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
@@ -286,5 +286,3 @@ declare hidden { <4 x i32>, <4 x half> } @func_struct() #0
 
 attributes #0 = { nounwind}
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/ctlz.ll b/llvm/test/CodeGen/AMDGPU/ctlz.ll
index b4d450a90d595..00f74f50a4b8b 100644
--- a/llvm/test/CodeGen/AMDGPU/ctlz.ll
+++ b/llvm/test/CodeGen/AMDGPU/ctlz.ll
@@ -4,7 +4,8 @@
 ; RUN: llc < %s -mtriple=r600 -mcpu=cypress -verify-machineinstrs | FileCheck %s -enable-var-scope --check-prefix=EG
 ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck %s -enable-var-scope --check-prefix=GFX10
 ; RUN: llc < %s -global-isel -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck %s -enable-var-scope --check-prefix=GFX10-GISEL
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs | FileCheck %s -enable-var-scope --check-prefix=GFX11
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs | FileCheck %s -enable-var-scope --check-prefixes=GFX11,GFX11-TRUE16
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs | FileCheck %s -enable-var-scope --check-prefixes=GFX11,GFX11-FAKE16
 
 declare i7 @llvm.ctlz.i7(i7, i1) nounwind readnone
 declare i8 @llvm.ctlz.i8(i8, i1) nounwind readnone
@@ -1814,18 +1815,31 @@ define amdgpu_kernel void @v_ctlz_i7_sel_eq_neg1(ptr addrspace(1) noalias %out,
 ; GFX10-GISEL-NEXT:    global_store_byte v1, v0, s[0:1]
 ; GFX10-GISEL-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: v_ctlz_i7_sel_eq_neg1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u8 v0, v0, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_clz_i32_u32_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0x7f, v0
-; GFX11-NEXT:    global_store_b8 v1, v0, s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: v_ctlz_i7_sel_eq_neg1:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_u8 v0, v0, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_clz_i32_u32_e32 v0, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0x7f, v0.l
+; GFX11-TRUE16-NEXT:    global_store_b8 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: v_ctlz_i7_sel_eq_neg1:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_u8 v0, v0, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_clz_i32_u32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x7f, v0
+; GFX11-FAKE16-NEXT:    global_store_b8 v1, v0, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %valptr.gep = getelementptr i7, ptr addrspace(1) %valptr, i32 %tid
   %val = load i7, ptr addrspace(1) %valptr.gep
diff --git a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
index 2ec6f7ab7602b..d1090738e24a6 100644
--- a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
+++ b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
@@ -3,7 +3,8 @@
 ; RUN: llc -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,VI
 ; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX10
 ; RUN: llc -mtriple=amdgcn-- -mcpu=gfx908 -start-before=amdgpu-isel -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX9
-; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX11
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX11,GFX11-TRUE16
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX11,GFX11-FAKE16
 
 declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
 declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone
@@ -298,14 +299,23 @@ define <2 x float> @v_uitofp_v2i8_to_v2f32(i16 %arg0) nounwind {
 ; GFX9-NEXT:    v_mov_b32_e32 v0, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_uitofp_v2i8_to_v2f32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cvt_f32_ubyte0_e32 v2, v0
-; GFX11-NEXT:    v_cvt_f32_ubyte1_e32 v1, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_mov_b32_e32 v0, v2
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_uitofp_v2i8_to_v2f32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_ubyte0_e32 v0, v1
+; GFX11-TRUE16-NEXT:    v_cvt_f32_ubyte1_e32 v1, v1
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_uitofp_v2i8_to_v2f32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_ubyte0_e32 v2, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_ubyte1_e32 v1, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v2
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val = bitcast i16 %arg0 to <2 x i8>
   %cvt = uitofp <2 x i8> %val to <2 x float>
   ret <2 x float> %cvt
@@ -493,13 +503,21 @@ define half @v_uitofp_i32_to_f16_mask255(i32 %arg0) nounwind {
 ; GFX9-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_uitofp_i32_to_f16_mask255:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cvt_f32_ubyte0_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_uitofp_i32_to_f16_mask255:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_ubyte0_e32 v0, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_uitofp_i32_to_f16_mask255:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_ubyte0_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %masked = and i32 %arg0, 255
   %cvt = uitofp i32 %masked to half
   ret half %cvt
@@ -535,13 +553,21 @@ define half @v_sitofp_i32_to_f16_mask255(i32 %arg0) nounwind {
 ; GFX9-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_sitofp_i32_to_f16_mask255:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cvt_f32_ubyte0_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_sitofp_i32_to_f16_mask255:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_ubyte0_e32 v0, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_sitofp_i32_to_f16_mask255:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_ubyte0_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %masked = and i32 %arg0, 255
   %cvt = sitofp i32 %masked to half
   ret half %cvt
@@ -577,13 +603,21 @@ define half @v_uitofp_to_f16_lshr8_mask255(i32 %arg0) nounwind {
 ; GFX9-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_uitofp_to_f16_lshr8_mask255:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cvt_f32_ubyte1_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_uitofp_to_f16_lshr8_mask255:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_ubyte1_e32 v0, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_uitofp_to_f16_lshr8_mask255:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_ubyte1_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %lshr.8 = lshr i32 %arg0, 8
   %masked = and i32 %lshr.8, 255
   %cvt = uitofp i32 %masked to half
@@ -620,13 +654,21 @@ define half @v_uitofp_to_f16_lshr16_mask255(i32 %arg0) nounwind {
 ; GFX9-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_uitofp_to_f16_lshr16_mask255:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cvt_f32_ubyte2_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_uitofp_to_f16_lshr16_mask255:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_ubyte2_e32 v0, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_uitofp_to_f16_lshr16_mask255:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_ubyte2_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %lshr.16 = lshr i32 %arg0, 16
   %masked = and i32 %lshr.16, 255
   %cvt = uitofp i32 %masked to half
@@ -663,13 +705,21 @@ define half @v_uitofp_to_f16_lshr24_mask255(i32 %arg0) nounwind {
 ; GFX9-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_uitofp_to_f16_lshr24_mask255:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cvt_f32_ubyte3_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_uitofp_to_f16_lshr24_mask255:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_ubyte3_e32 v0, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_uitofp_to_f16_lshr24_mask255:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_ubyte3_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %lshr.16 = lshr i32 %arg0, 24
   %masked = and i32 %lshr.16, 255
   %cvt = uitofp i32 %masked to half
@@ -703,13 +753,21 @@ define half @v_uitofp_i8_to_f16(i8 %arg0) nounwind {
 ; GFX9-NEXT:    v_cvt_f16_u16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_uitofp_i8_to_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_cvt_f16_u16_e32 v0, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_uitofp_i8_to_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_u16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_uitofp_i8_to_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_u16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cvt = uitofp i8 %arg0 to half
   ret half %cvt
 }
@@ -885,14 +943,23 @@ define double @v_uitofp_i8_to_f64(i8 %arg0) nounwind {
 ; GFX9-NEXT:    v_cvt_f64_u32_e32 v[0:1], v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_uitofp_i8_to_f64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_cvt_f64_u32_e32 v[0:1], v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_uitofp_i8_to_f64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_cvt_f64_u32_e32 v[0:1], v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_uitofp_i8_to_f64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f64_u32_e32 v[0:1], v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cvt = uitofp i8 %arg0 to double
   ret double %cvt
 }
@@ -1700,45 +1767,82 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_2_uses(ptr addrspace(1) noalias %o
 ; GFX9-NEXT:    global_store_dword v5, v0, s[2:3]
 ; GFX9-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: load_v4i8_to_v4f32_2_uses:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x34
-; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v0, s[0:1]
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_add_nc_u16 v2, v0, 9
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffffff00, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add_nc_u16 v3, v1, 9
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffffff00, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT:    v_or_b32_e32 v2, v4, v2
-; GFX11-NEXT:    v_mov_b32_e32 v4, 0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v3
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x900, v2
-; GFX11-NEXT:    v_cvt_f32_ubyte3_e32 v3, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add_nc_u16 v1, 0x900, v1
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v2
-; GFX11-NEXT:    v_cvt_f32_ubyte2_e32 v2, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v1
-; GFX11-NEXT:    v_cvt_f32_ubyte1_e32 v1, v0
-; GFX11-NEXT:    v_cvt_f32_ubyte0_e32 v0, v0
-; GFX11-NEXT:    v_or_b32_e32 v5, v5, v6
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
-; GFX11-NEXT:    global_store_b32 v4, v5, s[2:3]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: load_v4i8_to_v4f32_2_uses:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x34
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v4, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v4.l, 9
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v4.h, 9
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff00, v4.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff00, v4.h
+; GFX11-TRUE16-NEXT:    v_cvt_f32_ubyte3_e32 v3, v4
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT:    v_cvt_f32_ubyte2_e32 v2, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v1.h, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x900, v0.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v1.l, 0x900, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v1
+; GFX11-TRUE16-NEXT:    v_cvt_f32_ubyte1_e32 v1, v4
+; GFX11-TRUE16-NEXT:    v_cvt_f32_ubyte0_e32 v0, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v6, v7
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    global_store_b128 v5, v[0:3], s[0:1]
+; GFX11-TRUE16-NEXT:    global_store_b32 v5, v4, s[2:3]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: load_v4i8_to_v4f32_2_uses:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v0, s[0:1]
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v0, 9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffffff00, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v3, v1, 9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffffff00, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v4, v2
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, 0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x900, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f32_ubyte3_e32 v3, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x900, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f32_ubyte2_e32 v2, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f32_ubyte1_e32 v1, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_ubyte0_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v6
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
+; GFX11-FAKE16-NEXT:    global_store_b32 v4, v5, s[2:3]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %tid.x = call i32 @llvm.amdgcn.workitem.id.x()
   %in.ptr = getelementptr <4 x i8>, ptr addrspace(1) %in, i32 %tid.x
   %load = load <4 x i8>, ptr addrspace(1) %in.ptr, align 4
@@ -3015,5 +3119,3 @@ for.body.i:                                       ; preds = %for.body.i, %entry
   ret void
 }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
index 993f162921663..ce7281702c108 100644
--- a/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+++ b/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
@@ -5,8 +5,10 @@
 ; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
 ; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
 
 define float @fmul_select_f32_test1(float %x, i32 %bool.arg1, i32 %bool.arg2) {
 ; GFX7-LABEL: fmul_select_f32_test1:
@@ -1594,25 +1596,45 @@ define half @fmul_select_f16_test1(half %x, i32 %bool.arg1, i32 %bool.arg2) {
 ; GFX10-GISEL-NEXT:    v_ldexp_f16_e32 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: fmul_select_f16_test1:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_ldexp_f16_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: fmul_select_f16_test1:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7fff
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v2
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v0, v1
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: fmul_select_f16_test1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: fmul_select_f16_test1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_f16_test1:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v2, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_f16_test1:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v2, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %bool = icmp eq i32 %bool.arg1, %bool.arg2
   %y = select i1 %bool, half 2.000000e+00, half 1.000000e+00
   %ldexp = fmul half %x, %y
@@ -1682,27 +1704,49 @@ define half @fmul_select_f16_test2(half %x, i32 %bool.arg1, i32 %bool.arg2) {
 ; GFX10-GISEL-NEXT:    v_ldexp_f16_e32 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: fmul_select_f16_test2:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-SDAG-NEXT:    s_movk_i32 s0, 0x8000
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_med3_i32 v1, v1, s0, 0x7fff
-; GFX11-SDAG-NEXT:    v_ldexp_f16_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: fmul_select_f16_test2:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7fff
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v2
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v0, v1
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: fmul_select_f16_test2:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-TRUE16-NEXT:    s_movk_i32 s0, 0x8000
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_med3_i32 v1, v1, s0, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: fmul_select_f16_test2:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_movk_i32 s0, 0x8000
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_med3_i32 v1, v1, s0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_f16_test2:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v2, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_f16_test2:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v2, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %bool = icmp eq i32 %bool.arg1, %bool.arg2
   %y = select i1 %bool, half 5.000000e-01, half 1.000000e+00
   %ldexp = fmul half %x, %y
@@ -1797,39 +1841,69 @@ define <2 x half> @fmul_select_v2f16_test3(<2 x half> %x, <2 x i32> %bool.arg1,
 ; GFX10-GISEL-NEXT:    v_lshl_or_b32 v0, v0, 16, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: fmul_select_v2f16_test3:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v5, 0x4000
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v2, 0x3c00, v5, vcc_lo
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v3
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0x3c00, v5, vcc_lo
-; GFX11-SDAG-NEXT:    v_pack_b32_f16 v1, v1, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_pk_mul_f16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: fmul_select_v2f16_test3:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v3
-; GFX11-GISEL-NEXT:    v_mov_b32_e32 v3, 0x7fff
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v3
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v0, v1
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT:    v_med3_i32 v2, 0xffff8000, v2, v3
-; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v1, v4, v2
-; GFX11-GISEL-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: fmul_select_v2f16_test3:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, 0x4000
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e64 s0, v1, v3
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0x3c00, v2.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v1.h, 0x3c00, v2.l, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.h, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_mul_f16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: fmul_select_v2f16_test3:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v5, 0x4000
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x3c00, v5, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x3c00, v5, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_mul_f16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_v2f16_test3:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v3
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v3, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v3
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_med3_i32 v2, 0xffff8000, v2, v3
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.h, v0.h, v2.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_v2f16_test3:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v3, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_med3_i32 v2, 0xffff8000, v2, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v1, v4, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
   %y = select <2 x i1> %bool, <2 x half> <half 2.000000e+00, half 2.000000e+00>, <2 x half> <half 1.000000e+00, half 1.000000e+00>
   %ldexp = fmul <2 x half> %x, %y
@@ -1924,39 +1998,69 @@ define <2 x half> @fmul_select_v2f16_test4(<2 x half> %x, <2 x i32> %bool.arg1,
 ; GFX10-GISEL-NEXT:    v_lshl_or_b32 v0, v0, 16, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: fmul_select_v2f16_test4:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v5, 0x3800
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v2, 0x3c00, v5, vcc_lo
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v3
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0x3c00, v5, vcc_lo
-; GFX11-SDAG-NEXT:    v_pack_b32_f16 v1, v1, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_pk_mul_f16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: fmul_select_v2f16_test4:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v3
-; GFX11-GISEL-NEXT:    v_mov_b32_e32 v3, 0x7fff
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v3
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v0, v1
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT:    v_med3_i32 v2, 0xffff8000, v2, v3
-; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v1, v4, v2
-; GFX11-GISEL-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: fmul_select_v2f16_test4:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, 0x3800
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e64 s0, v1, v3
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0x3c00, v2.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v1.h, 0x3c00, v2.l, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.h, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_mul_f16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: fmul_select_v2f16_test4:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v5, 0x3800
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x3c00, v5, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x3c00, v5, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_mul_f16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_v2f16_test4:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v3
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v3, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v3
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_med3_i32 v2, 0xffff8000, v2, v3
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.h, v0.h, v2.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_v2f16_test4:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v3, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_med3_i32 v2, 0xffff8000, v2, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v1, v4, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
   %y = select <2 x i1> %bool, <2 x half> <half 5.000000e-01, half 5.000000e-01>, <2 x half> <half 1.000000e+00, half 1.000000e+00>
   %ldexp = fmul <2 x half> %x, %y
@@ -2000,14 +2104,41 @@ define half @fmul_select_f16_test5(half %x, i32 %bool.arg1, i32 %bool.arg2) {
 ; GFX10-NEXT:    v_ldexp_f16_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fmul_select_f16_test5:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-NEXT:    v_cndmask_b32_e64 v1, 3, 1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_ldexp_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: fmul_select_f16_test5:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 3, 1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: fmul_select_f16_test5:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 3, 1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_f16_test5:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 3, 1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_f16_test5:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 3, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %bool = icmp eq i32 %bool.arg1, %bool.arg2
   %y = select i1 %bool, half 2.000000e+00, half 8.000000e+00
   %ldexp = fmul half %x, %y
@@ -2078,25 +2209,45 @@ define half @fmul_select_f16_test6(half %x, i32 %bool.arg1, i32 %bool.arg2) {
 ; GFX10-GISEL-NEXT:    v_mul_f16_e32 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: fmul_select_f16_test6:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v3, 0xc800
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0x4200, v3, vcc_lo
-; GFX11-SDAG-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: fmul_select_f16_test6:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_mov_b32_e32 v3, 0x4200
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v1, v3, 0xc800, vcc_lo
-; GFX11-GISEL-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: fmul_select_f16_test6:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0xc800
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0x4200, v3.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: fmul_select_f16_test6:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v3, 0xc800
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x4200, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_f16_test6:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v0.h, 0x4200
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.h, 0xc800, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_f16_test6:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v3, 0x4200
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v1, v3, 0xc800, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %bool = icmp eq i32 %bool.arg1, %bool.arg2
   %y = select i1 %bool, half -8.000000e+00, half 3.000000e+00
   %ldexp = fmul half %x, %y
@@ -2166,25 +2317,45 @@ define half @fmul_select_f16_test7(half %x, i32 %bool.arg1, i32 %bool.arg2) {
 ; GFX10-GISEL-NEXT:    v_mul_f16_e32 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: fmul_select_f16_test7:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v3, 0x4800
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0xc400, v3, vcc_lo
-; GFX11-SDAG-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: fmul_select_f16_test7:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_mov_b32_e32 v3, 0xc400
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v1, v3, 0x4800, vcc_lo
-; GFX11-GISEL-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: fmul_select_f16_test7:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0x4800
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0xc400, v3.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: fmul_select_f16_test7:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v3, 0x4800
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0xc400, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_f16_test7:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v0.h, 0xc400
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.h, 0x4800, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_f16_test7:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v3, 0xc400
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v1, v3, 0x4800, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %bool = icmp eq i32 %bool.arg1, %bool.arg2
   %y = select i1 %bool, half 8.000000e+00, half -4.000000e+00
   %ldexp = fmul half %x, %y
@@ -2232,14 +2403,41 @@ define half @fmul_select_f16_test8(half %x, i32 %bool.arg1, i32 %bool.arg2) {
 ; GFX10-NEXT:    v_mul_f16_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fmul_select_f16_test8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-NEXT:    v_cndmask_b32_e64 v1, 0, 0x8000, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: fmul_select_f16_test8:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0, 0x8000, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: fmul_select_f16_test8:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 0x8000, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_f16_test8:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0, 0x8000, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_f16_test8:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 0x8000, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %bool = icmp eq i32 %bool.arg1, %bool.arg2
   %y = select i1 %bool, half -0.000000e+00, half 0.000000e+00
   %ldexp = fmul half %x, %y
@@ -2307,27 +2505,49 @@ define half @fmul_select_f16_test9(half %x, i32 %bool.arg1, i32 %bool.arg2) {
 ; GFX10-GISEL-NEXT:    v_ldexp_f16_e64 v0, -v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: fmul_select_f16_test9:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e64 v1, 5, 4, vcc_lo
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_ldexp_f16_e64 v0, -v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: fmul_select_f16_test9:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7fff
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_add_nc_u32_e32 v1, 5, v1
-; GFX11-GISEL-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v2
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e64 v0, -v0, v1
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: fmul_select_f16_test9:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 5, 4, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_ldexp_f16_e64 v0.l, -v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: fmul_select_f16_test9:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 5, 4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_ldexp_f16_e64 v0, -v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_f16_test9:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v2, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_add_nc_u32_e32 v1, 5, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v2
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e64 v0.l, -v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_f16_test9:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v2, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_add_nc_u32_e32 v1, 5, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e64 v0, -v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %bool = icmp eq i32 %bool.arg1, %bool.arg2
   %y = select i1 %bool, half -1.600000e+01, half -3.200000e+01
   %ldexp = fmul half %x, %y
@@ -2392,25 +2612,45 @@ define half @fmul_select_f16_test10_sel_log2val_neg11_pos11(half %x, i32 %bool.a
 ; GFX10-GISEL-NEXT:    v_ldexp_f16_e32 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: fmul_select_f16_test10_sel_log2val_neg11_pos11:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-SDAG-NEXT:    s_movk_i32 s0, 0x8000
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e64 v1, 11, -11, vcc_lo
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_med3_i32 v1, v1, s0, 0x7fff
-; GFX11-SDAG-NEXT:    v_ldexp_f16_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: fmul_select_f16_test10_sel_log2val_neg11_pos11:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v1, 11, -11, vcc_lo
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v0, v1
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: fmul_select_f16_test10_sel_log2val_neg11_pos11:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-TRUE16-NEXT:    s_movk_i32 s0, 0x8000
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 11, -11, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_med3_i32 v1, v1, s0, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: fmul_select_f16_test10_sel_log2val_neg11_pos11:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_movk_i32 s0, 0x8000
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 11, -11, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_med3_i32 v1, v1, s0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_f16_test10_sel_log2val_neg11_pos11:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 11, -11, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_f16_test10_sel_log2val_neg11_pos11:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 11, -11, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %bool = icmp eq i32 %bool.arg1, %bool.arg2
   %y = select i1 %bool, half 0xH1000, half 0xH6800
   %ldexp = fmul half %x, %y
@@ -2475,25 +2715,45 @@ define half @fmul_select_f16_test11_sel_log2val_pos7_neg14(half %x, i32 %bool.ar
 ; GFX10-GISEL-NEXT:    v_ldexp_f16_e32 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: fmul_select_f16_test11_sel_log2val_pos7_neg14:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-SDAG-NEXT:    s_movk_i32 s0, 0x8000
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e64 v1, -14, 7, vcc_lo
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_med3_i32 v1, v1, s0, 0x7fff
-; GFX11-SDAG-NEXT:    v_ldexp_f16_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: fmul_select_f16_test11_sel_log2val_pos7_neg14:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v1, -14, 7, vcc_lo
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v0, v1
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: fmul_select_f16_test11_sel_log2val_pos7_neg14:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-TRUE16-NEXT:    s_movk_i32 s0, 0x8000
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v1, -14, 7, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_med3_i32 v1, v1, s0, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: fmul_select_f16_test11_sel_log2val_pos7_neg14:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_movk_i32 s0, 0x8000
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v1, -14, 7, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_med3_i32 v1, v1, s0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_f16_test11_sel_log2val_pos7_neg14:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v1, -14, 7, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_f16_test11_sel_log2val_pos7_neg14:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v1, -14, 7, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %bool = icmp eq i32 %bool.arg1, %bool.arg2
   %y = select i1 %bool, half 0xH5800, half 0xH0400
   %ldexp = fmul half %x, %y
@@ -2548,25 +2808,87 @@ define bfloat @fmul_select_bf16_test1(bfloat %x, i32 %bool.arg1, i32 %bool.arg2)
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fmul_select_bf16_test1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v3, 0x4000 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0x3f80, v3, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f32_e32 v0, v0, v1
-; GFX11-NEXT:    v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: fmul_select_bf16_test1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0x3f80
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, 0x4000, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: fmul_select_bf16_test1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v3, 0x4000 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x3f80, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_bf16_test1:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0x3f80
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, 0x4000, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-TRUE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_bf16_test1:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v3, 0x4000 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x3f80, v3, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-FAKE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %bool = icmp eq i32 %bool.arg1, %bool.arg2
   %y = select i1 %bool, bfloat 2.000000e+00, bfloat 1.000000e+00
   %ldexp = fmul bfloat %x, %y
@@ -2621,25 +2943,87 @@ define bfloat @fmul_select_bf16_test2(bfloat %x, i32 %bool.arg1, i32 %bool.arg2)
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fmul_select_bf16_test2:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v3, 0x3f00 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0x3f80, v3, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f32_e32 v0, v0, v1
-; GFX11-NEXT:    v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: fmul_select_bf16_test2:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0x3f80
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, 0x3f00, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: fmul_select_bf16_test2:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v3, 0x3f00 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x3f80, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_bf16_test2:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0x3f80
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, 0x3f00, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-TRUE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_bf16_test2:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v3, 0x3f00 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x3f80, v3, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-FAKE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %bool = icmp eq i32 %bool.arg1, %bool.arg2
   %y = select i1 %bool, bfloat 5.000000e-01, bfloat 1.000000e+00
   %ldexp = fmul bfloat %x, %y
@@ -2721,37 +3105,135 @@ define <2 x bfloat> @fmul_select_v2bf16_test3(<2 x bfloat> %x, <2 x i32> %bool.a
 ; GFX10-NEXT:    v_perm_b32 v0, v0, v1, 0x7060302
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fmul_select_v2bf16_test3:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mov_b32_e32 v5, 0x4000
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0x3f80, v5, vcc_lo
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, 0x3f80, v5, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_mul_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-NEXT:    v_or_b32_e32 v5, 0x400000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_mul_f32_e32 v1, v3, v1
-; GFX11-NEXT:    v_bfe_u32 v3, v0, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v2, v1, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v4, 0x400000, v1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v0, v0, v1, 0x7060302
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: fmul_select_v2bf16_test3:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v5.l, 0x3f80
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v3
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e64 s0, v2, v4
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v1.l, v5.l, 0x4000, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v2.l, v5.l, 0x4000, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v3, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_u32 v2, v1, 16, 1
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v4, 0x400000, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v1, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: fmul_select_v2bf16_test3:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v5, 0x4000
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x3f80, v5, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x3f80, v5, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_dual_mul_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f32_e32 v1, v3, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_u32 v2, v1, 16, 1
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-FAKE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_perm_b32 v0, v0, v1, 0x7060302
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_v2bf16_test3:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v5.l, 0x3f80
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v3
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e64 s0, v2, v4
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b16 v1.l, v5.l, 0x4000, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b16 v2.l, v5.l, 0x4000, s0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v3, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_bfe_u32 v2, v1, 16, 1
+; GFX11-GISEL-TRUE16-NEXT:    v_or_b32_e32 v4, 0x400000, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-GISEL-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v1, v0
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_v2bf16_test3:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v5, 0x4000
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x3f80, v5, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x3f80, v5, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_dual_mul_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f32_e32 v1, v3, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX11-GISEL-FAKE16-NEXT:    v_bfe_u32 v2, v1, 16, 1
+; GFX11-GISEL-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-FAKE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_perm_b32 v0, v0, v1, 0x7060302
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
   %y = select <2 x i1> %bool, <2 x bfloat> <bfloat 2.000000e+00, bfloat 2.000000e+00>, <2 x bfloat> <bfloat 1.000000e+00, bfloat 1.000000e+00>
   %ldexp = fmul <2 x bfloat> %x, %y
@@ -2833,37 +3315,135 @@ define <2 x bfloat> @fmul_select_v2bf16_test4(<2 x bfloat> %x, <2 x i32> %bool.a
 ; GFX10-NEXT:    v_perm_b32 v0, v0, v1, 0x7060302
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fmul_select_v2bf16_test4:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mov_b32_e32 v5, 0x3f00
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0x3f80, v5, vcc_lo
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, 0x3f80, v5, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_mul_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-NEXT:    v_or_b32_e32 v5, 0x400000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_mul_f32_e32 v1, v3, v1
-; GFX11-NEXT:    v_bfe_u32 v3, v0, 16, 1
-; GFX11-NEXT:    v_bfe_u32 v2, v1, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v4, 0x400000, v1
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v0, v0, v1, 0x7060302
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: fmul_select_v2bf16_test4:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v5.l, 0x3f80
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v3
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e64 s0, v2, v4
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v1.l, v5.l, 0x3f00, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v2.l, v5.l, 0x3f00, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v3, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_u32 v2, v1, 16, 1
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v4, 0x400000, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v1, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: fmul_select_v2bf16_test4:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v5, 0x3f00
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x3f80, v5, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x3f80, v5, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_dual_mul_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f32_e32 v1, v3, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_u32 v2, v1, 16, 1
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-FAKE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_perm_b32 v0, v0, v1, 0x7060302
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_v2bf16_test4:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v5.l, 0x3f80
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v3
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e64 s0, v2, v4
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b16 v1.l, v5.l, 0x3f00, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b16 v2.l, v5.l, 0x3f00, s0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v3, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_bfe_u32 v2, v1, 16, 1
+; GFX11-GISEL-TRUE16-NEXT:    v_or_b32_e32 v4, 0x400000, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-GISEL-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v1, v0
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_v2bf16_test4:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v5, 0x3f00
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x3f80, v5, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x3f80, v5, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_dual_mul_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f32_e32 v1, v3, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 1
+; GFX11-GISEL-FAKE16-NEXT:    v_bfe_u32 v2, v1, 16, 1
+; GFX11-GISEL-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-FAKE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_perm_b32 v0, v0, v1, 0x7060302
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
   %y = select <2 x i1> %bool, <2 x bfloat> <bfloat 5.000000e-01, bfloat 5.000000e-01>, <2 x bfloat> <bfloat 1.000000e+00, bfloat 1.000000e+00>
   %ldexp = fmul <2 x bfloat> %x, %y
@@ -2919,25 +3499,87 @@ define bfloat @fmul_select_bf16_test5(bfloat %x, i32 %bool.arg1, i32 %bool.arg2)
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fmul_select_bf16_test5:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v3, 0x4000 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0x4100, v3, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f32_e32 v0, v0, v1
-; GFX11-NEXT:    v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: fmul_select_bf16_test5:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0x4100
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, 0x4000, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: fmul_select_bf16_test5:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v3, 0x4000 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x4100, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_bf16_test5:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0x4100
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, 0x4000, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-TRUE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_bf16_test5:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v3, 0x4000 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x4100, v3, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-FAKE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %bool = icmp eq i32 %bool.arg1, %bool.arg2
   %y = select i1 %bool, bfloat 2.000000e+00, bfloat 8.000000e+00
   %ldexp = fmul bfloat %x, %y
@@ -2994,25 +3636,87 @@ define bfloat @fmul_select_bf16_test6(bfloat %x, i32 %bool.arg1, i32 %bool.arg2)
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fmul_select_bf16_test6:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v3, 0xffffc100 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0x4040, v3, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f32_e32 v0, v0, v1
-; GFX11-NEXT:    v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: fmul_select_bf16_test6:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0x4040
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, 0xc100, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: fmul_select_bf16_test6:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v3, 0xffffc100 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x4040, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_bf16_test6:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0x4040
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, 0xc100, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-TRUE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_bf16_test6:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v3, 0xffffc100 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x4040, v3, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-FAKE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %bool = icmp eq i32 %bool.arg1, %bool.arg2
   %y = select i1 %bool, bfloat -8.000000e+00, bfloat 3.000000e+00
   %ldexp = fmul bfloat %x, %y
@@ -3068,25 +3772,87 @@ define bfloat @fmul_select_bf16_test7(bfloat %x, i32 %bool.arg1, i32 %bool.arg2)
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fmul_select_bf16_test7:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v3, 0x4100 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0xffffc080, v3, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f32_e32 v0, v0, v1
-; GFX11-NEXT:    v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: fmul_select_bf16_test7:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0xc080
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, 0x4100, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: fmul_select_bf16_test7:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v3, 0x4100 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0xffffc080, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_bf16_test7:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0xc080
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, 0x4100, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-TRUE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_bf16_test7:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v3, 0x4100 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0xffffc080, v3, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-FAKE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %bool = icmp eq i32 %bool.arg1, %bool.arg2
   %y = select i1 %bool, bfloat 8.000000e+00, bfloat -4.000000e+00
   %ldexp = fmul bfloat %x, %y
@@ -3140,24 +3906,81 @@ define bfloat @fmul_select_bf16_test8(bfloat %x, i32 %bool.arg1, i32 %bool.arg2)
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fmul_select_bf16_test8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT:    v_cndmask_b32_e64 v1, 0, 0xffff8000, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_mul_f32_e32 v0, v0, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: fmul_select_bf16_test8:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0, 0x8000, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: fmul_select_bf16_test8:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 0xffff8000, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_bf16_test8:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0, 0x8000, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-GISEL-TRUE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-TRUE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_bf16_test8:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 0xffff8000, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-GISEL-FAKE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-FAKE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %bool = icmp eq i32 %bool.arg1, %bool.arg2
   %y = select i1 %bool, bfloat -0.000000e+00, bfloat 0.000000e+00
   %ldexp = fmul bfloat %x, %y
@@ -3214,25 +4037,87 @@ define bfloat @fmul_select_bf16_test9(bfloat %x, i32 %bool.arg1, i32 %bool.arg2)
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fmul_select_bf16_test9:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v3, 0xffffc180 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0xffffc200, v3, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f32_e32 v0, v0, v1
-; GFX11-NEXT:    v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: fmul_select_bf16_test9:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0xc200
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, 0xc180, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: fmul_select_bf16_test9:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v3, 0xffffc180 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0xffffc200, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_bf16_test9:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0xc200
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, 0xc180, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-TRUE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_bf16_test9:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v3, 0xffffc180 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0xffffc200, v3, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-FAKE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %bool = icmp eq i32 %bool.arg1, %bool.arg2
   %y = select i1 %bool, bfloat -1.600000e+01, bfloat -3.200000e+01
   %ldexp = fmul bfloat %x, %y
@@ -3289,25 +4174,87 @@ define bfloat @fmul_select_bf16_test10_sel_log2val_pos65_pos56(bfloat %x, i32 %b
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fmul_select_bf16_test10_sel_log2val_pos65_pos56:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v3, 0xffffe000 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0xffffdb80, v3, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f32_e32 v0, v0, v1
-; GFX11-NEXT:    v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: fmul_select_bf16_test10_sel_log2val_pos65_pos56:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0xdb80
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, 0xe000, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: fmul_select_bf16_test10_sel_log2val_pos65_pos56:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v3, 0xffffe000 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0xffffdb80, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_bf16_test10_sel_log2val_pos65_pos56:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0xdb80
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, 0xe000, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-TRUE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_bf16_test10_sel_log2val_pos65_pos56:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v3, 0xffffe000 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0xffffdb80, v3, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-FAKE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %bool = icmp eq i32 %bool.arg1, %bool.arg2
   %y = select i1 %bool, bfloat 0xRE000, bfloat 0xRDB80
   %ldexp = fmul bfloat %x, %y
@@ -3364,25 +4311,87 @@ define bfloat @fmul_select_bf16_test11_sel_log2val_neg22_pos25(bfloat %x, i32 %b
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fmul_select_bf16_test11_sel_log2val_neg22_pos25:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v3, 0x3480 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0x4c00, v3, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f32_e32 v0, v0, v1
-; GFX11-NEXT:    v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: fmul_select_bf16_test11_sel_log2val_neg22_pos25:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0x4c00
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, 0x3480, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: fmul_select_bf16_test11_sel_log2val_neg22_pos25:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v3, 0x3480 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x4c00, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_bf16_test11_sel_log2val_neg22_pos25:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0x4c00
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, 0x3480, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-TRUE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_bf16_test11_sel_log2val_neg22_pos25:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v3, 0x3480 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x4c00, v3, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-FAKE16-NEXT:    v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %bool = icmp eq i32 %bool.arg1, %bool.arg2
   %y = select i1 %bool, bfloat 0xR3480, bfloat 0xR4C00
   %ldexp = fmul bfloat %x, %y
diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
index 012f33952f990..0bda7e4a5e49a 100644
--- a/llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
+++ b/llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
@@ -95,5 +95,3 @@ out.else:
   ret void
 }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
index ada3f017f45cf..45fe2d07226a1 100644
--- a/llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
+++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
@@ -2,7 +2,8 @@
 ; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefix=GFX906 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define amdgpu_kernel void @uniform_vec_0_i16(ptr addrspace(1) %out, i16 %a) {
 ; GCN-LABEL: uniform_vec_0_i16:
@@ -341,11 +342,17 @@ define i32 @divergent_vec_i16_LL(i16 %a, i16 %b) {
 ; GFX906-NEXT:    v_perm_b32 v0, v1, v0, s4
 ; GFX906-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: divergent_vec_i16_LL:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: divergent_vec_i16_LL:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: divergent_vec_i16_LL:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %tmp = insertelement <2 x i16> poison, i16 %a, i32 0
   %vec = insertelement <2 x i16> %tmp, i16 %b, i32 1
   %val = bitcast <2 x i16> %vec to i32
@@ -518,11 +525,20 @@ define i32 @divergent_vec_i16_HH(i32 %a, i32 %b) {
 ; GFX906-NEXT:    v_perm_b32 v0, v1, v0, s4
 ; GFX906-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: divergent_vec_i16_HH:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x7060302
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: divergent_vec_i16_HH:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: divergent_vec_i16_HH:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %shift_a = lshr i32 %a, 16
   %tr_a = trunc i32 %shift_a to i16
   %shift_b = lshr i32 %b, 16
@@ -625,11 +641,17 @@ define float @divergent_vec_f16_LL(half %a, half %b) {
 ; GFX906-NEXT:    v_perm_b32 v0, v1, v0, s4
 ; GFX906-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: divergent_vec_f16_LL:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: divergent_vec_f16_LL:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: divergent_vec_f16_LL:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %tmp = insertelement <2 x half> poison, half %a, i32 0
   %vec = insertelement <2 x half> %tmp, half %b, i32 1
   %val = bitcast <2 x half> %vec to float
diff --git a/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir b/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
index 41b61f2e09a3d..fb20e72a77103 100644
--- a/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
+++ b/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
@@ -1,6 +1,6 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN,GFX1100
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN,GFX1150
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN,GFX1150
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN,GFX1100
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -mattr=-real-true16 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN,GFX1150
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN,GFX1150
 
 ---
 
diff --git a/llvm/test/CodeGen/AMDGPU/ds_read2.ll b/llvm/test/CodeGen/AMDGPU/ds_read2.ll
index 7bfd9ab8cadb2..06c30dfd36033 100644
--- a/llvm/test/CodeGen/AMDGPU/ds_read2.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds_read2.ll
@@ -1535,5 +1535,3 @@ attributes #1 = { nounwind readnone speculatable }
 attributes #2 = { convergent nounwind }
 attributes #3 = { nounwind noinline }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll b/llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
index ca2fca69dcf21..2d253c9484309 100644
--- a/llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
+++ b/llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -mattr=+dynamic-vgpr < %s | FileCheck -check-prefix=CHECK %s
+; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -mattr=+real-true16 -mattr=+dynamic-vgpr < %s | FileCheck -check-prefixes=CHECK,CHECK-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -mattr=-real-true16 -mattr=+dynamic-vgpr < %s | FileCheck -check-prefixes=CHECK,CHECK-FAKE16 %s
 
 ; Make sure we use a stack pointer and allocate 112 * 4 bytes at the beginning of the stack.
 
@@ -28,16 +29,27 @@ define amdgpu_kernel void @kernel() #0 {
 }
 
 define amdgpu_cs void @with_local() #0 {
-; CHECK-LABEL: with_local:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
-; CHECK-NEXT:    v_mov_b32_e32 v0, 13
-; CHECK-NEXT:    s_cmp_lg_u32 0, s33
-; CHECK-NEXT:    s_cmovk_i32 s33, 0x1c0
-; CHECK-NEXT:    scratch_store_b8 off, v0, s33 scope:SCOPE_SYS
-; CHECK-NEXT:    s_wait_storecnt 0x0
-; CHECK-NEXT:    s_alloc_vgpr 0
-; CHECK-NEXT:    s_endpgm
+; CHECK-TRUE16-LABEL: with_local:
+; CHECK-TRUE16:       ; %bb.0:
+; CHECK-TRUE16-NEXT:    s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
+; CHECK-TRUE16-NEXT:    v_mov_b16_e32 v0.l, 13
+; CHECK-TRUE16-NEXT:    s_cmp_lg_u32 0, s33
+; CHECK-TRUE16-NEXT:    s_cmovk_i32 s33, 0x1c0
+; CHECK-TRUE16-NEXT:    scratch_store_b8 off, v0, s33 scope:SCOPE_SYS
+; CHECK-TRUE16-NEXT:    s_wait_storecnt 0x0
+; CHECK-TRUE16-NEXT:    s_alloc_vgpr 0
+; CHECK-TRUE16-NEXT:    s_endpgm
+;
+; CHECK-FAKE16-LABEL: with_local:
+; CHECK-FAKE16:       ; %bb.0:
+; CHECK-FAKE16-NEXT:    s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
+; CHECK-FAKE16-NEXT:    v_mov_b32_e32 v0, 13
+; CHECK-FAKE16-NEXT:    s_cmp_lg_u32 0, s33
+; CHECK-FAKE16-NEXT:    s_cmovk_i32 s33, 0x1c0
+; CHECK-FAKE16-NEXT:    scratch_store_b8 off, v0, s33 scope:SCOPE_SYS
+; CHECK-FAKE16-NEXT:    s_wait_storecnt 0x0
+; CHECK-FAKE16-NEXT:    s_alloc_vgpr 0
+; CHECK-FAKE16-NEXT:    s_endpgm
   %local = alloca i32, addrspace(5)
   store volatile i8 13, ptr addrspace(5) %local
   ret void
@@ -46,21 +58,37 @@ define amdgpu_cs void @with_local() #0 {
 ; Check that we generate s_cselect for SP if we can fit
 ; the offset in an inline constant.
 define amdgpu_cs void @with_calls_inline_const() #0 {
-; CHECK-LABEL: with_calls_inline_const:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
-; CHECK-NEXT:    v_mov_b32_e32 v0, 15
-; CHECK-NEXT:    s_cmp_lg_u32 0, s33
-; CHECK-NEXT:    s_mov_b32 s1, callee@abs32@hi
-; CHECK-NEXT:    s_cmovk_i32 s33, 0x1c0
-; CHECK-NEXT:    s_mov_b32 s0, callee@abs32@lo
-; CHECK-NEXT:    scratch_store_b8 off, v0, s33 scope:SCOPE_SYS
-; CHECK-NEXT:    s_wait_storecnt 0x0
-; CHECK-NEXT:    v_mov_b32_e32 v0, 0x47
-; CHECK-NEXT:    s_cselect_b32 s32, 0x1d0, 16
-; CHECK-NEXT:    s_swappc_b64 s[30:31], s[0:1]
-; CHECK-NEXT:    s_alloc_vgpr 0
-; CHECK-NEXT:    s_endpgm
+; CHECK-TRUE16-LABEL: with_calls_inline_const:
+; CHECK-TRUE16:       ; %bb.0:
+; CHECK-TRUE16-NEXT:    s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
+; CHECK-TRUE16-NEXT:    v_mov_b16_e32 v0.l, 15
+; CHECK-TRUE16-NEXT:    s_cmp_lg_u32 0, s33
+; CHECK-TRUE16-NEXT:    s_mov_b32 s1, callee@abs32@hi
+; CHECK-TRUE16-NEXT:    s_cmovk_i32 s33, 0x1c0
+; CHECK-TRUE16-NEXT:    s_mov_b32 s0, callee@abs32@lo
+; CHECK-TRUE16-NEXT:    scratch_store_b8 off, v0, s33 scope:SCOPE_SYS
+; CHECK-TRUE16-NEXT:    s_wait_storecnt 0x0
+; CHECK-TRUE16-NEXT:    v_mov_b32_e32 v0, 0x47
+; CHECK-TRUE16-NEXT:    s_cselect_b32 s32, 0x1d0, 16
+; CHECK-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; CHECK-TRUE16-NEXT:    s_alloc_vgpr 0
+; CHECK-TRUE16-NEXT:    s_endpgm
+;
+; CHECK-FAKE16-LABEL: with_calls_inline_const:
+; CHECK-FAKE16:       ; %bb.0:
+; CHECK-FAKE16-NEXT:    s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
+; CHECK-FAKE16-NEXT:    v_mov_b32_e32 v0, 15
+; CHECK-FAKE16-NEXT:    s_cmp_lg_u32 0, s33
+; CHECK-FAKE16-NEXT:    s_mov_b32 s1, callee@abs32@hi
+; CHECK-FAKE16-NEXT:    s_cmovk_i32 s33, 0x1c0
+; CHECK-FAKE16-NEXT:    s_mov_b32 s0, callee@abs32@lo
+; CHECK-FAKE16-NEXT:    scratch_store_b8 off, v0, s33 scope:SCOPE_SYS
+; CHECK-FAKE16-NEXT:    s_wait_storecnt 0x0
+; CHECK-FAKE16-NEXT:    v_mov_b32_e32 v0, 0x47
+; CHECK-FAKE16-NEXT:    s_cselect_b32 s32, 0x1d0, 16
+; CHECK-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; CHECK-FAKE16-NEXT:    s_alloc_vgpr 0
+; CHECK-FAKE16-NEXT:    s_endpgm
   %local = alloca i32, addrspace(5)
   store volatile i8 15, ptr addrspace(5) %local
   call amdgpu_gfx void @callee(i32 71)
@@ -70,22 +98,39 @@ define amdgpu_cs void @with_calls_inline_const() #0 {
 ; Check that we generate s_mov + s_cmovk if we can't
 ; fit the offset for SP in an inline constant.
 define amdgpu_cs void @with_calls_no_inline_const() #0 {
-; CHECK-LABEL: with_calls_no_inline_const:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
-; CHECK-NEXT:    v_mov_b32_e32 v0, 15
-; CHECK-NEXT:    s_cmp_lg_u32 0, s33
-; CHECK-NEXT:    s_mov_b32 s1, callee@abs32@hi
-; CHECK-NEXT:    s_cmovk_i32 s33, 0x1c0
-; CHECK-NEXT:    s_mov_b32 s0, callee@abs32@lo
-; CHECK-NEXT:    scratch_store_b8 off, v0, s33 scope:SCOPE_SYS
-; CHECK-NEXT:    s_wait_storecnt 0x0
-; CHECK-NEXT:    v_mov_b32_e32 v0, 0x47
-; CHECK-NEXT:    s_movk_i32 s32, 0x100
-; CHECK-NEXT:    s_cmovk_i32 s32, 0x2c0
-; CHECK-NEXT:    s_swappc_b64 s[30:31], s[0:1]
-; CHECK-NEXT:    s_alloc_vgpr 0
-; CHECK-NEXT:    s_endpgm
+; CHECK-TRUE16-LABEL: with_calls_no_inline_const:
+; CHECK-TRUE16:       ; %bb.0:
+; CHECK-TRUE16-NEXT:    s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
+; CHECK-TRUE16-NEXT:    v_mov_b16_e32 v0.l, 15
+; CHECK-TRUE16-NEXT:    s_cmp_lg_u32 0, s33
+; CHECK-TRUE16-NEXT:    s_mov_b32 s1, callee@abs32@hi
+; CHECK-TRUE16-NEXT:    s_cmovk_i32 s33, 0x1c0
+; CHECK-TRUE16-NEXT:    s_mov_b32 s0, callee@abs32@lo
+; CHECK-TRUE16-NEXT:    scratch_store_b8 off, v0, s33 scope:SCOPE_SYS
+; CHECK-TRUE16-NEXT:    s_wait_storecnt 0x0
+; CHECK-TRUE16-NEXT:    v_mov_b32_e32 v0, 0x47
+; CHECK-TRUE16-NEXT:    s_movk_i32 s32, 0x100
+; CHECK-TRUE16-NEXT:    s_cmovk_i32 s32, 0x2c0
+; CHECK-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; CHECK-TRUE16-NEXT:    s_alloc_vgpr 0
+; CHECK-TRUE16-NEXT:    s_endpgm
+;
+; CHECK-FAKE16-LABEL: with_calls_no_inline_const:
+; CHECK-FAKE16:       ; %bb.0:
+; CHECK-FAKE16-NEXT:    s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
+; CHECK-FAKE16-NEXT:    v_mov_b32_e32 v0, 15
+; CHECK-FAKE16-NEXT:    s_cmp_lg_u32 0, s33
+; CHECK-FAKE16-NEXT:    s_mov_b32 s1, callee@abs32@hi
+; CHECK-FAKE16-NEXT:    s_cmovk_i32 s33, 0x1c0
+; CHECK-FAKE16-NEXT:    s_mov_b32 s0, callee@abs32@lo
+; CHECK-FAKE16-NEXT:    scratch_store_b8 off, v0, s33 scope:SCOPE_SYS
+; CHECK-FAKE16-NEXT:    s_wait_storecnt 0x0
+; CHECK-FAKE16-NEXT:    v_mov_b32_e32 v0, 0x47
+; CHECK-FAKE16-NEXT:    s_movk_i32 s32, 0x100
+; CHECK-FAKE16-NEXT:    s_cmovk_i32 s32, 0x2c0
+; CHECK-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; CHECK-FAKE16-NEXT:    s_alloc_vgpr 0
+; CHECK-FAKE16-NEXT:    s_endpgm
   %local = alloca i32, i32 61, addrspace(5)
   store volatile i8 15, ptr addrspace(5) %local
   call amdgpu_gfx void @callee(i32 71)
@@ -135,32 +180,54 @@ define amdgpu_cs void @realign_stack(<32 x i32> %x) #0 {
 }
 
 define amdgpu_cs void @frame_pointer_none() #1 {
-; CHECK-LABEL: frame_pointer_none:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
-; CHECK-NEXT:    v_mov_b32_e32 v0, 13
-; CHECK-NEXT:    s_cmp_lg_u32 0, s33
-; CHECK-NEXT:    s_cmovk_i32 s33, 0x1c0
-; CHECK-NEXT:    scratch_store_b8 off, v0, s33 scope:SCOPE_SYS
-; CHECK-NEXT:    s_wait_storecnt 0x0
-; CHECK-NEXT:    s_alloc_vgpr 0
-; CHECK-NEXT:    s_endpgm
+; CHECK-TRUE16-LABEL: frame_pointer_none:
+; CHECK-TRUE16:       ; %bb.0:
+; CHECK-TRUE16-NEXT:    s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
+; CHECK-TRUE16-NEXT:    v_mov_b16_e32 v0.l, 13
+; CHECK-TRUE16-NEXT:    s_cmp_lg_u32 0, s33
+; CHECK-TRUE16-NEXT:    s_cmovk_i32 s33, 0x1c0
+; CHECK-TRUE16-NEXT:    scratch_store_b8 off, v0, s33 scope:SCOPE_SYS
+; CHECK-TRUE16-NEXT:    s_wait_storecnt 0x0
+; CHECK-TRUE16-NEXT:    s_alloc_vgpr 0
+; CHECK-TRUE16-NEXT:    s_endpgm
+;
+; CHECK-FAKE16-LABEL: frame_pointer_none:
+; CHECK-FAKE16:       ; %bb.0:
+; CHECK-FAKE16-NEXT:    s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
+; CHECK-FAKE16-NEXT:    v_mov_b32_e32 v0, 13
+; CHECK-FAKE16-NEXT:    s_cmp_lg_u32 0, s33
+; CHECK-FAKE16-NEXT:    s_cmovk_i32 s33, 0x1c0
+; CHECK-FAKE16-NEXT:    scratch_store_b8 off, v0, s33 scope:SCOPE_SYS
+; CHECK-FAKE16-NEXT:    s_wait_storecnt 0x0
+; CHECK-FAKE16-NEXT:    s_alloc_vgpr 0
+; CHECK-FAKE16-NEXT:    s_endpgm
   %local = alloca i32, addrspace(5)
   store volatile i8 13, ptr addrspace(5) %local
   ret void
 }
 
 define amdgpu_cs void @frame_pointer_all() #2 {
-; CHECK-LABEL: frame_pointer_all:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
-; CHECK-NEXT:    v_mov_b32_e32 v0, 13
-; CHECK-NEXT:    s_cmp_lg_u32 0, s33
-; CHECK-NEXT:    s_cmovk_i32 s33, 0x1c0
-; CHECK-NEXT:    scratch_store_b8 off, v0, s33 scope:SCOPE_SYS
-; CHECK-NEXT:    s_wait_storecnt 0x0
-; CHECK-NEXT:    s_alloc_vgpr 0
-; CHECK-NEXT:    s_endpgm
+; CHECK-TRUE16-LABEL: frame_pointer_all:
+; CHECK-TRUE16:       ; %bb.0:
+; CHECK-TRUE16-NEXT:    s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
+; CHECK-TRUE16-NEXT:    v_mov_b16_e32 v0.l, 13
+; CHECK-TRUE16-NEXT:    s_cmp_lg_u32 0, s33
+; CHECK-TRUE16-NEXT:    s_cmovk_i32 s33, 0x1c0
+; CHECK-TRUE16-NEXT:    scratch_store_b8 off, v0, s33 scope:SCOPE_SYS
+; CHECK-TRUE16-NEXT:    s_wait_storecnt 0x0
+; CHECK-TRUE16-NEXT:    s_alloc_vgpr 0
+; CHECK-TRUE16-NEXT:    s_endpgm
+;
+; CHECK-FAKE16-LABEL: frame_pointer_all:
+; CHECK-FAKE16:       ; %bb.0:
+; CHECK-FAKE16-NEXT:    s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
+; CHECK-FAKE16-NEXT:    v_mov_b32_e32 v0, 13
+; CHECK-FAKE16-NEXT:    s_cmp_lg_u32 0, s33
+; CHECK-FAKE16-NEXT:    s_cmovk_i32 s33, 0x1c0
+; CHECK-FAKE16-NEXT:    scratch_store_b8 off, v0, s33 scope:SCOPE_SYS
+; CHECK-FAKE16-NEXT:    s_wait_storecnt 0x0
+; CHECK-FAKE16-NEXT:    s_alloc_vgpr 0
+; CHECK-FAKE16-NEXT:    s_endpgm
   %local = alloca i32, addrspace(5)
   store volatile i8 13, ptr addrspace(5) %local
   ret void
@@ -168,18 +235,31 @@ define amdgpu_cs void @frame_pointer_all() #2 {
 
 ; Non-entry functions and graphics shaders don't need to worry about CWSR.
 define amdgpu_gs void @amdgpu_gs() #0 {
-; CHECK-LABEL: amdgpu_gs:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    v_mov_b32_e32 v0, 15
-; CHECK-NEXT:    s_mov_b32 s1, callee@abs32@hi
-; CHECK-NEXT:    s_mov_b32 s0, callee@abs32@lo
-; CHECK-NEXT:    s_mov_b32 s32, 16
-; CHECK-NEXT:    scratch_store_b8 off, v0, off scope:SCOPE_SYS
-; CHECK-NEXT:    s_wait_storecnt 0x0
-; CHECK-NEXT:    v_mov_b32_e32 v0, 0x47
-; CHECK-NEXT:    s_swappc_b64 s[30:31], s[0:1]
-; CHECK-NEXT:    s_alloc_vgpr 0
-; CHECK-NEXT:    s_endpgm
+; CHECK-TRUE16-LABEL: amdgpu_gs:
+; CHECK-TRUE16:       ; %bb.0:
+; CHECK-TRUE16-NEXT:    v_mov_b16_e32 v0.l, 15
+; CHECK-TRUE16-NEXT:    s_mov_b32 s1, callee@abs32@hi
+; CHECK-TRUE16-NEXT:    s_mov_b32 s0, callee@abs32@lo
+; CHECK-TRUE16-NEXT:    s_mov_b32 s32, 16
+; CHECK-TRUE16-NEXT:    scratch_store_b8 off, v0, off scope:SCOPE_SYS
+; CHECK-TRUE16-NEXT:    s_wait_storecnt 0x0
+; CHECK-TRUE16-NEXT:    v_mov_b32_e32 v0, 0x47
+; CHECK-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; CHECK-TRUE16-NEXT:    s_alloc_vgpr 0
+; CHECK-TRUE16-NEXT:    s_endpgm
+;
+; CHECK-FAKE16-LABEL: amdgpu_gs:
+; CHECK-FAKE16:       ; %bb.0:
+; CHECK-FAKE16-NEXT:    v_mov_b32_e32 v0, 15
+; CHECK-FAKE16-NEXT:    s_mov_b32 s1, callee@abs32@hi
+; CHECK-FAKE16-NEXT:    s_mov_b32 s0, callee@abs32@lo
+; CHECK-FAKE16-NEXT:    s_mov_b32 s32, 16
+; CHECK-FAKE16-NEXT:    scratch_store_b8 off, v0, off scope:SCOPE_SYS
+; CHECK-FAKE16-NEXT:    s_wait_storecnt 0x0
+; CHECK-FAKE16-NEXT:    v_mov_b32_e32 v0, 0x47
+; CHECK-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; CHECK-FAKE16-NEXT:    s_alloc_vgpr 0
+; CHECK-FAKE16-NEXT:    s_endpgm
   %local = alloca i32, addrspace(5)
   store volatile i8 15, ptr addrspace(5) %local
   call amdgpu_gfx void @callee(i32 71)
@@ -187,45 +267,85 @@ define amdgpu_gs void @amdgpu_gs() #0 {
 }
 
 define amdgpu_gfx void @amdgpu_gfx() #0 {
-; CHECK-LABEL: amdgpu_gfx:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_wait_loadcnt_dscnt 0x0
-; CHECK-NEXT:    s_wait_expcnt 0x0
-; CHECK-NEXT:    s_wait_samplecnt 0x0
-; CHECK-NEXT:    s_wait_bvhcnt 0x0
-; CHECK-NEXT:    s_wait_kmcnt 0x0
-; CHECK-NEXT:    s_mov_b32 s0, s33
-; CHECK-NEXT:    s_mov_b32 s33, s32
-; CHECK-NEXT:    s_or_saveexec_b32 s1, -1
-; CHECK-NEXT:    scratch_store_b32 off, v40, s33 offset:4 ; 4-byte Folded Spill
-; CHECK-NEXT:    s_wait_alu 0xfffe
-; CHECK-NEXT:    s_mov_b32 exec_lo, s1
-; CHECK-NEXT:    v_writelane_b32 v40, s0, 2
-; CHECK-NEXT:    v_mov_b32_e32 v0, 15
-; CHECK-NEXT:    s_mov_b32 s1, callee@abs32@hi
-; CHECK-NEXT:    s_mov_b32 s0, callee@abs32@lo
-; CHECK-NEXT:    s_add_co_i32 s32, s32, 16
-; CHECK-NEXT:    v_writelane_b32 v40, s30, 0
-; CHECK-NEXT:    s_wait_storecnt 0x0
-; CHECK-NEXT:    scratch_store_b8 off, v0, s33 scope:SCOPE_SYS
-; CHECK-NEXT:    s_wait_storecnt 0x0
-; CHECK-NEXT:    v_mov_b32_e32 v0, 0x47
-; CHECK-NEXT:    v_writelane_b32 v40, s31, 1
-; CHECK-NEXT:    s_wait_alu 0xfffe
-; CHECK-NEXT:    s_swappc_b64 s[30:31], s[0:1]
-; CHECK-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; CHECK-NEXT:    v_readlane_b32 s31, v40, 1
-; CHECK-NEXT:    v_readlane_b32 s30, v40, 0
-; CHECK-NEXT:    s_mov_b32 s32, s33
-; CHECK-NEXT:    v_readlane_b32 s0, v40, 2
-; CHECK-NEXT:    s_or_saveexec_b32 s1, -1
-; CHECK-NEXT:    scratch_load_b32 v40, off, s33 offset:4 ; 4-byte Folded Reload
-; CHECK-NEXT:    s_wait_alu 0xfffe
-; CHECK-NEXT:    s_mov_b32 exec_lo, s1
-; CHECK-NEXT:    s_mov_b32 s33, s0
-; CHECK-NEXT:    s_wait_loadcnt 0x0
-; CHECK-NEXT:    s_wait_alu 0xfffe
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
+; CHECK-TRUE16-LABEL: amdgpu_gfx:
+; CHECK-TRUE16:       ; %bb.0:
+; CHECK-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; CHECK-TRUE16-NEXT:    s_wait_expcnt 0x0
+; CHECK-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; CHECK-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; CHECK-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; CHECK-TRUE16-NEXT:    s_mov_b32 s0, s33
+; CHECK-TRUE16-NEXT:    s_mov_b32 s33, s32
+; CHECK-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; CHECK-TRUE16-NEXT:    scratch_store_b32 off, v40, s33 offset:4 ; 4-byte Folded Spill
+; CHECK-TRUE16-NEXT:    s_wait_alu 0xfffe
+; CHECK-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; CHECK-TRUE16-NEXT:    v_writelane_b32 v40, s0, 2
+; CHECK-TRUE16-NEXT:    v_mov_b16_e32 v0.l, 15
+; CHECK-TRUE16-NEXT:    s_mov_b32 s1, callee@abs32@hi
+; CHECK-TRUE16-NEXT:    s_mov_b32 s0, callee@abs32@lo
+; CHECK-TRUE16-NEXT:    s_add_co_i32 s32, s32, 16
+; CHECK-TRUE16-NEXT:    v_writelane_b32 v40, s30, 0
+; CHECK-TRUE16-NEXT:    s_wait_storecnt 0x0
+; CHECK-TRUE16-NEXT:    scratch_store_b8 off, v0, s33 scope:SCOPE_SYS
+; CHECK-TRUE16-NEXT:    s_wait_storecnt 0x0
+; CHECK-TRUE16-NEXT:    v_mov_b32_e32 v0, 0x47
+; CHECK-TRUE16-NEXT:    v_writelane_b32 v40, s31, 1
+; CHECK-TRUE16-NEXT:    s_wait_alu 0xfffe
+; CHECK-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; CHECK-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; CHECK-TRUE16-NEXT:    v_readlane_b32 s31, v40, 1
+; CHECK-TRUE16-NEXT:    v_readlane_b32 s30, v40, 0
+; CHECK-TRUE16-NEXT:    s_mov_b32 s32, s33
+; CHECK-TRUE16-NEXT:    v_readlane_b32 s0, v40, 2
+; CHECK-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; CHECK-TRUE16-NEXT:    scratch_load_b32 v40, off, s33 offset:4 ; 4-byte Folded Reload
+; CHECK-TRUE16-NEXT:    s_wait_alu 0xfffe
+; CHECK-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; CHECK-TRUE16-NEXT:    s_mov_b32 s33, s0
+; CHECK-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; CHECK-TRUE16-NEXT:    s_wait_alu 0xfffe
+; CHECK-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; CHECK-FAKE16-LABEL: amdgpu_gfx:
+; CHECK-FAKE16:       ; %bb.0:
+; CHECK-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; CHECK-FAKE16-NEXT:    s_wait_expcnt 0x0
+; CHECK-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; CHECK-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; CHECK-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; CHECK-FAKE16-NEXT:    s_mov_b32 s0, s33
+; CHECK-FAKE16-NEXT:    s_mov_b32 s33, s32
+; CHECK-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; CHECK-FAKE16-NEXT:    scratch_store_b32 off, v40, s33 offset:4 ; 4-byte Folded Spill
+; CHECK-FAKE16-NEXT:    s_wait_alu 0xfffe
+; CHECK-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; CHECK-FAKE16-NEXT:    v_writelane_b32 v40, s0, 2
+; CHECK-FAKE16-NEXT:    v_mov_b32_e32 v0, 15
+; CHECK-FAKE16-NEXT:    s_mov_b32 s1, callee@abs32@hi
+; CHECK-FAKE16-NEXT:    s_mov_b32 s0, callee@abs32@lo
+; CHECK-FAKE16-NEXT:    s_add_co_i32 s32, s32, 16
+; CHECK-FAKE16-NEXT:    v_writelane_b32 v40, s30, 0
+; CHECK-FAKE16-NEXT:    s_wait_storecnt 0x0
+; CHECK-FAKE16-NEXT:    scratch_store_b8 off, v0, s33 scope:SCOPE_SYS
+; CHECK-FAKE16-NEXT:    s_wait_storecnt 0x0
+; CHECK-FAKE16-NEXT:    v_mov_b32_e32 v0, 0x47
+; CHECK-FAKE16-NEXT:    v_writelane_b32 v40, s31, 1
+; CHECK-FAKE16-NEXT:    s_wait_alu 0xfffe
+; CHECK-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; CHECK-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; CHECK-FAKE16-NEXT:    v_readlane_b32 s31, v40, 1
+; CHECK-FAKE16-NEXT:    v_readlane_b32 s30, v40, 0
+; CHECK-FAKE16-NEXT:    s_mov_b32 s32, s33
+; CHECK-FAKE16-NEXT:    v_readlane_b32 s0, v40, 2
+; CHECK-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; CHECK-FAKE16-NEXT:    scratch_load_b32 v40, off, s33 offset:4 ; 4-byte Folded Reload
+; CHECK-FAKE16-NEXT:    s_wait_alu 0xfffe
+; CHECK-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; CHECK-FAKE16-NEXT:    s_mov_b32 s33, s0
+; CHECK-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; CHECK-FAKE16-NEXT:    s_wait_alu 0xfffe
+; CHECK-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %local = alloca i32, addrspace(5)
   store volatile i8 15, ptr addrspace(5) %local
   call amdgpu_gfx void @callee(i32 71)
diff --git a/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll b/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
index af7028173f6c7..dbbe43152e0df 100644
--- a/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
@@ -1,7 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgcn-- -verify-machineinstrs -o - %s | FileCheck -check-prefix=SI %s
 ; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX11 %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs -o - %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs -o - %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define <4 x i16> @vec_8xi16_extract_4xi16(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i32 inreg %cond.arg) {
 ; SI-LABEL: vec_8xi16_extract_4xi16:
@@ -116,38 +117,66 @@ define <4 x i16> @vec_8xi16_extract_4xi16(ptr addrspace(1) %p0, ptr addrspace(1)
 ; GFX9-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5
 ; GFX9-NEXT:    s_branch .LBB0_2
 ;
-; GFX11-LABEL: vec_8xi16_extract_4xi16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_cmp_lg_u32 s0, 0
-; GFX11-NEXT:    s_mov_b32 s0, 0
-; GFX11-NEXT:    s_cbranch_scc0 .LBB0_4
-; GFX11-NEXT:  ; %bb.1: ; %F
-; GFX11-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_vccnz .LBB0_3
-; GFX11-NEXT:  .LBB0_2: ; %T
-; GFX11-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:  .LBB0_3: ; %exit
-; GFX11-NEXT:    v_pk_ashrrev_i16 v0, 15, v2 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_ashrrev_i16 v1, 15, v3 op_sel_hi:[0,0]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, 0xffff8000, v1
-; GFX11-NEXT:    v_or_b32_e32 v0, 0xffff8000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v2, 0xffff8000, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, 0xffff8000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v1, v3, v1, 0x5040100
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB0_4:
-; GFX11-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5
-; GFX11-NEXT:    s_branch .LBB0_2
+; GFX11-TRUE16-LABEL: vec_8xi16_extract_4xi16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s0, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, 0
+; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB0_4
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %F
+; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB0_3
+; GFX11-TRUE16-NEXT:  .LBB0_2: ; %T
+; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:  .LBB0_3: ; %exit
+; GFX11-TRUE16-NEXT:    v_pk_ashrrev_i16 v1, 15, v3 op_sel_hi:[0,0]
+; GFX11-TRUE16-NEXT:    v_pk_ashrrev_i16 v0, 15, v2 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, 0x8000, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, 0x8000, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, 0x8000, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, 0x8000, v1.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB0_4:
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5
+; GFX11-TRUE16-NEXT:    s_branch .LBB0_2
+;
+; GFX11-FAKE16-LABEL: vec_8xi16_extract_4xi16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s0, 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, 0
+; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB0_4
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %F
+; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB0_3
+; GFX11-FAKE16-NEXT:  .LBB0_2: ; %T
+; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:  .LBB0_3: ; %exit
+; GFX11-FAKE16-NEXT:    v_pk_ashrrev_i16 v0, 15, v2 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_ashrrev_i16 v1, 15, v3 op_sel_hi:[0,0]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, 0xffff8000, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, 0xffff8000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, 0xffff8000, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, 0xffff8000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB0_4:
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5
+; GFX11-FAKE16-NEXT:    s_branch .LBB0_2
   %cond = icmp eq i32 %cond.arg, 0
   br i1 %cond, label %T, label %F
 
@@ -282,38 +311,66 @@ define <4 x i16> @vec_8xi16_extract_4xi16_2(ptr addrspace(1) %p0, ptr addrspace(
 ; GFX9-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5
 ; GFX9-NEXT:    s_branch .LBB1_2
 ;
-; GFX11-LABEL: vec_8xi16_extract_4xi16_2:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_cmp_lg_u32 s0, 0
-; GFX11-NEXT:    s_mov_b32 s0, 0
-; GFX11-NEXT:    s_cbranch_scc0 .LBB1_4
-; GFX11-NEXT:  ; %bb.1: ; %F
-; GFX11-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_vccnz .LBB1_3
-; GFX11-NEXT:  .LBB1_2: ; %T
-; GFX11-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:  .LBB1_3: ; %exit
-; GFX11-NEXT:    v_pk_ashrrev_i16 v0, 15, v4 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_ashrrev_i16 v1, 15, v5 op_sel_hi:[0,1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, 0xffff8000, v1
-; GFX11-NEXT:    v_or_b32_e32 v0, 0xffff8000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v2, 0xffff8000, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, 0xffff8000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v1, v3, v1, 0x5040100
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB1_4:
-; GFX11-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5
-; GFX11-NEXT:    s_branch .LBB1_2
+; GFX11-TRUE16-LABEL: vec_8xi16_extract_4xi16_2:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s0, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, 0
+; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB1_4
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %F
+; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB1_3
+; GFX11-TRUE16-NEXT:  .LBB1_2: ; %T
+; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:  .LBB1_3: ; %exit
+; GFX11-TRUE16-NEXT:    v_pk_ashrrev_i16 v1, 15, v5 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_ashrrev_i16 v0, 15, v4 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, 0x8000, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, 0x8000, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, 0x8000, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, 0x8000, v1.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB1_4:
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5
+; GFX11-TRUE16-NEXT:    s_branch .LBB1_2
+;
+; GFX11-FAKE16-LABEL: vec_8xi16_extract_4xi16_2:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s0, 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, 0
+; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB1_4
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %F
+; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB1_3
+; GFX11-FAKE16-NEXT:  .LBB1_2: ; %T
+; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:  .LBB1_3: ; %exit
+; GFX11-FAKE16-NEXT:    v_pk_ashrrev_i16 v0, 15, v4 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_ashrrev_i16 v1, 15, v5 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, 0xffff8000, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, 0xffff8000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, 0xffff8000, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, 0xffff8000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB1_4:
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5
+; GFX11-FAKE16-NEXT:    s_branch .LBB1_2
   %cond = icmp eq i32 %cond.arg, 0
   br i1 %cond, label %T, label %F
 
@@ -451,39 +508,73 @@ define <4 x half> @vec_8xf16_extract_4xf16(ptr addrspace(1) %p0, ptr addrspace(1
 ; GFX9-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5
 ; GFX9-NEXT:    s_branch .LBB2_2
 ;
-; GFX11-LABEL: vec_8xf16_extract_4xf16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_cmp_lg_u32 s0, 0
-; GFX11-NEXT:    s_mov_b32 s0, 0
-; GFX11-NEXT:    s_cbranch_scc0 .LBB2_4
-; GFX11-NEXT:  ; %bb.1: ; %F
-; GFX11-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_vccnz .LBB2_3
-; GFX11-NEXT:  .LBB2_2: ; %T
-; GFX11-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:  .LBB2_3: ; %exit
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0x3d00
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, 0x3900, v0, vcc_lo
-; GFX11-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v1
-; GFX11-NEXT:    v_dual_mov_b32 v4, 0x3900 :: v_dual_cndmask_b32 v1, 0x3900, v0
-; GFX11-NEXT:    v_cmp_nge_f16_e32 vcc_lo, 0.5, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v4, 0x3d00, v4, vcc_lo
-; GFX11-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, 0x3900, v0, vcc_lo
-; GFX11-NEXT:    v_pack_b32_f16 v0, v2, v1
-; GFX11-NEXT:    v_pack_b32_f16 v1, v3, v4
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB2_4:
-; GFX11-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5
-; GFX11-NEXT:    s_branch .LBB2_2
+; GFX11-TRUE16-LABEL: vec_8xf16_extract_4xf16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s0, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, 0
+; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB2_4
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %F
+; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB2_3
+; GFX11-TRUE16-NEXT:  .LBB2_2: ; %T
+; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:  .LBB2_3: ; %exit
+; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, 0x3d00
+; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e64 s0, 0.5, v2.h
+; GFX11-TRUE16-NEXT:    v_cmp_nge_f16_e64 s1, 0.5, v3.l
+; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e64 s2, 0.5, v3.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0x3900, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0x3900, v0.l, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v0.l, 0x3900, s1
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, 0x3900, v0.l, s2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v1.l
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v1, v2.l, v1.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB2_4:
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5
+; GFX11-TRUE16-NEXT:    s_branch .LBB2_2
+;
+; GFX11-FAKE16-LABEL: vec_8xf16_extract_4xf16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s0, 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, 0
+; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB2_4
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %F
+; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB2_3
+; GFX11-FAKE16-NEXT:  .LBB2_2: ; %T
+; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:  .LBB2_3: ; %exit
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0x3d00
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x3900, v0, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v1
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v4, 0x3900 :: v_dual_cndmask_b32 v1, 0x3900, v0
+; GFX11-FAKE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, 0.5, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, 0x3d00, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v3
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, 0x3900, v0, vcc_lo
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v2, v1
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v1, v3, v4
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB2_4:
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5
+; GFX11-FAKE16-NEXT:    s_branch .LBB2_2
   %cond = icmp eq i32 %cond.arg, 0
   br i1 %cond, label %T, label %F
 
@@ -656,42 +747,74 @@ define <4 x i16> @vec_16xi16_extract_4xi16(ptr addrspace(1) %p0, ptr addrspace(1
 ; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11
 ; GFX9-NEXT:    s_branch .LBB3_2
 ;
-; GFX11-LABEL: vec_16xi16_extract_4xi16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_cmp_lg_u32 s0, 0
-; GFX11-NEXT:    s_mov_b32 s0, 0
-; GFX11-NEXT:    s_cbranch_scc0 .LBB3_4
-; GFX11-NEXT:  ; %bb.1: ; %F
-; GFX11-NEXT:    global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_vccnz .LBB3_3
-; GFX11-NEXT:  .LBB3_2: ; %T
-; GFX11-NEXT:    global_load_b128 v[2:5], v[0:1], off offset:16 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:  .LBB3_3: ; %exit
-; GFX11-NEXT:    v_pk_ashrrev_i16 v0, 15, v2 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_ashrrev_i16 v1, 15, v3 op_sel_hi:[0,0]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, 0xffff8000, v1
-; GFX11-NEXT:    v_or_b32_e32 v0, 0xffff8000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v2, 0xffff8000, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, 0xffff8000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v1, v3, v1, 0x5040100
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB3_4:
-; GFX11-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
-; GFX11-NEXT:    s_branch .LBB3_2
+; GFX11-TRUE16-LABEL: vec_16xi16_extract_4xi16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s0, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, 0
+; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB3_4
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %F
+; GFX11-TRUE16-NEXT:    global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB3_3
+; GFX11-TRUE16-NEXT:  .LBB3_2: ; %T
+; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[0:1], off offset:16 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:  .LBB3_3: ; %exit
+; GFX11-TRUE16-NEXT:    v_pk_ashrrev_i16 v1, 15, v3 op_sel_hi:[0,0]
+; GFX11-TRUE16-NEXT:    v_pk_ashrrev_i16 v0, 15, v2 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, 0x8000, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, 0x8000, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, 0x8000, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, 0x8000, v1.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB3_4:
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
+; GFX11-TRUE16-NEXT:    s_branch .LBB3_2
+;
+; GFX11-FAKE16-LABEL: vec_16xi16_extract_4xi16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s0, 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, 0
+; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB3_4
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %F
+; GFX11-FAKE16-NEXT:    global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB3_3
+; GFX11-FAKE16-NEXT:  .LBB3_2: ; %T
+; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[0:1], off offset:16 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:  .LBB3_3: ; %exit
+; GFX11-FAKE16-NEXT:    v_pk_ashrrev_i16 v0, 15, v2 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_ashrrev_i16 v1, 15, v3 op_sel_hi:[0,0]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, 0xffff8000, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, 0xffff8000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, 0xffff8000, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, 0xffff8000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB3_4:
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
+; GFX11-FAKE16-NEXT:    s_branch .LBB3_2
   %cond = icmp eq i32 %cond.arg, 0
   br i1 %cond, label %T, label %F
 
@@ -866,42 +989,74 @@ define <4 x i16> @vec_16xi16_extract_4xi16_2(ptr addrspace(1) %p0, ptr addrspace
 ; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11
 ; GFX9-NEXT:    s_branch .LBB4_2
 ;
-; GFX11-LABEL: vec_16xi16_extract_4xi16_2:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_cmp_lg_u32 s0, 0
-; GFX11-NEXT:    s_mov_b32 s0, 0
-; GFX11-NEXT:    s_cbranch_scc0 .LBB4_4
-; GFX11-NEXT:  ; %bb.1: ; %F
-; GFX11-NEXT:    global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_vccnz .LBB4_3
-; GFX11-NEXT:  .LBB4_2: ; %T
-; GFX11-NEXT:    global_load_b128 v[2:5], v[0:1], off offset:16 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:  .LBB4_3: ; %exit
-; GFX11-NEXT:    v_pk_ashrrev_i16 v0, 15, v4 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_ashrrev_i16 v1, 15, v5 op_sel_hi:[0,1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, 0xffff8000, v1
-; GFX11-NEXT:    v_or_b32_e32 v0, 0xffff8000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v2, 0xffff8000, v2
-; GFX11-NEXT:    v_or_b32_e32 v3, 0xffff8000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v1, v3, v1, 0x5040100
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB4_4:
-; GFX11-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
-; GFX11-NEXT:    s_branch .LBB4_2
+; GFX11-TRUE16-LABEL: vec_16xi16_extract_4xi16_2:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s0, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, 0
+; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB4_4
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %F
+; GFX11-TRUE16-NEXT:    global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB4_3
+; GFX11-TRUE16-NEXT:  .LBB4_2: ; %T
+; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[0:1], off offset:16 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:  .LBB4_3: ; %exit
+; GFX11-TRUE16-NEXT:    v_pk_ashrrev_i16 v1, 15, v5 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_ashrrev_i16 v0, 15, v4 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, 0x8000, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, 0x8000, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, 0x8000, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, 0x8000, v1.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB4_4:
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
+; GFX11-TRUE16-NEXT:    s_branch .LBB4_2
+;
+; GFX11-FAKE16-LABEL: vec_16xi16_extract_4xi16_2:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s0, 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, 0
+; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB4_4
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %F
+; GFX11-FAKE16-NEXT:    global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB4_3
+; GFX11-FAKE16-NEXT:  .LBB4_2: ; %T
+; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[0:1], off offset:16 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:  .LBB4_3: ; %exit
+; GFX11-FAKE16-NEXT:    v_pk_ashrrev_i16 v0, 15, v4 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_ashrrev_i16 v1, 15, v5 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, 0xffff8000, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, 0xffff8000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, 0xffff8000, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, 0xffff8000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB4_4:
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
+; GFX11-FAKE16-NEXT:    s_branch .LBB4_2
   %cond = icmp eq i32 %cond.arg, 0
   br i1 %cond, label %T, label %F
 
@@ -1079,43 +1234,81 @@ define <4 x half> @vec_16xf16_extract_4xf16(ptr addrspace(1) %p0, ptr addrspace(
 ; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11
 ; GFX9-NEXT:    s_branch .LBB5_2
 ;
-; GFX11-LABEL: vec_16xf16_extract_4xf16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_cmp_lg_u32 s0, 0
-; GFX11-NEXT:    s_mov_b32 s0, 0
-; GFX11-NEXT:    s_cbranch_scc0 .LBB5_4
-; GFX11-NEXT:  ; %bb.1: ; %F
-; GFX11-NEXT:    global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_vccnz .LBB5_3
-; GFX11-NEXT:  .LBB5_2: ; %T
-; GFX11-NEXT:    global_load_b128 v[2:5], v[0:1], off offset:16 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:  .LBB5_3: ; %exit
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0x3d00
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, 0x3900, v0, vcc_lo
-; GFX11-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v1
-; GFX11-NEXT:    v_dual_mov_b32 v4, 0x3900 :: v_dual_cndmask_b32 v1, 0x3900, v0
-; GFX11-NEXT:    v_cmp_nge_f16_e32 vcc_lo, 0.5, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v4, 0x3d00, v4, vcc_lo
-; GFX11-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, 0x3900, v0, vcc_lo
-; GFX11-NEXT:    v_pack_b32_f16 v0, v2, v1
-; GFX11-NEXT:    v_pack_b32_f16 v1, v3, v4
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-; GFX11-NEXT:  .LBB5_4:
-; GFX11-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
-; GFX11-NEXT:    s_branch .LBB5_2
+; GFX11-TRUE16-LABEL: vec_16xf16_extract_4xf16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s0, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, 0
+; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB5_4
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %F
+; GFX11-TRUE16-NEXT:    global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB5_3
+; GFX11-TRUE16-NEXT:  .LBB5_2: ; %T
+; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[0:1], off offset:16 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:  .LBB5_3: ; %exit
+; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, 0x3d00
+; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e64 s0, 0.5, v2.h
+; GFX11-TRUE16-NEXT:    v_cmp_nge_f16_e64 s1, 0.5, v3.l
+; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e64 s2, 0.5, v3.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0x3900, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0x3900, v0.l, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v0.l, 0x3900, s1
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, 0x3900, v0.l, s2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v1.l
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v1, v2.l, v1.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT:  .LBB5_4:
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
+; GFX11-TRUE16-NEXT:    s_branch .LBB5_2
+;
+; GFX11-FAKE16-LABEL: vec_16xf16_extract_4xf16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s0, 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, 0
+; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB5_4
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %F
+; GFX11-FAKE16-NEXT:    global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB5_3
+; GFX11-FAKE16-NEXT:  .LBB5_2: ; %T
+; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[0:1], off offset:16 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:  .LBB5_3: ; %exit
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0x3d00
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x3900, v0, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v1
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v4, 0x3900 :: v_dual_cndmask_b32 v1, 0x3900, v0
+; GFX11-FAKE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, 0.5, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, 0x3d00, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v3
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, 0x3900, v0, vcc_lo
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v2, v1
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v1, v3, v4
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-NEXT:  .LBB5_4:
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
+; GFX11-FAKE16-NEXT:    s_branch .LBB5_2
   %cond = icmp eq i32 %cond.arg, 0
   br i1 %cond, label %T, label %F
 
@@ -1426,62 +1619,108 @@ define amdgpu_gfx <8 x i16> @vec_16xi16_extract_8xi16_0(i1 inreg %cond, ptr addr
 ; GFX9-NEXT:    v_perm_b32 v3, v7, v3, s34
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: vec_16xi16_extract_8xi16_0:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    scratch_load_u8 v4, off, s32
-; GFX11-NEXT:    s_mov_b32 s0, 0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v4, 1, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v4
-; GFX11-NEXT:    s_and_b32 s1, vcc_lo, exec_lo
-; GFX11-NEXT:    s_cbranch_scc0 .LBB7_2
-; GFX11-NEXT:  ; %bb.1: ; %F
-; GFX11-NEXT:    global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_vccz .LBB7_3
-; GFX11-NEXT:    s_branch .LBB7_4
-; GFX11-NEXT:  .LBB7_2:
-; GFX11-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
-; GFX11-NEXT:  .LBB7_3: ; %T
-; GFX11-NEXT:    global_load_b128 v[2:5], v[0:1], off offset:16 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:  .LBB7_4: ; %exit
-; GFX11-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 0x3801, v5
-; GFX11-NEXT:    v_mov_b32_e32 v9, 0x3900
-; GFX11-NEXT:    v_mov_b32_e32 v1, 0x3d00
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v8, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v5, 0x3900, v1, vcc_lo
-; GFX11-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 0x3801, v4
-; GFX11-NEXT:    v_cndmask_b32_e32 v4, 0x3900, v1, vcc_lo
-; GFX11-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 0x3801, v7
-; GFX11-NEXT:    v_cndmask_b32_e32 v7, 0x3900, v1, vcc_lo
-; GFX11-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 0x3801, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, 0x3900, v1, vcc_lo
-; GFX11-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 0x3801, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, 0x3900, v1, vcc_lo
-; GFX11-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 0x3801, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x3900, v1, vcc_lo
-; GFX11-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 0x3801, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_perm_b32 v0, v0, v2, 0x5040100
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0x3900, v1, vcc_lo
-; GFX11-NEXT:    v_cmp_lt_u16_e32 vcc_lo, 0x3800, v8
-; GFX11-NEXT:    v_perm_b32 v2, v7, v4, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v1, v1, v3, 0x5040100
-; GFX11-NEXT:    v_cndmask_b32_e32 v6, 0x3d00, v9, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v3, v6, v5, 0x5040100
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: vec_16xi16_extract_8xi16_0:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    scratch_load_u8 v4, off, s32
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 1, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v4
+; GFX11-TRUE16-NEXT:    s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB7_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %F
+; GFX11-TRUE16-NEXT:    global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b128 v[4:7], v[2:3], off glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_vccz .LBB7_3
+; GFX11-TRUE16-NEXT:    s_branch .LBB7_4
+; GFX11-TRUE16-NEXT:  .LBB7_2:
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11
+; GFX11-TRUE16-NEXT:  .LBB7_3: ; %T
+; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[0:1], off offset:16 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b128 v[4:7], v[0:1], off glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:  .LBB7_4: ; %exit
+; GFX11-TRUE16-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 0x3801, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, 0x3900
+; GFX11-TRUE16-NEXT:    v_cmp_gt_u16_e64 s0, 0x3801, v6.l
+; GFX11-TRUE16-NEXT:    v_cmp_lt_u16_e64 s1, 0x3800, v7.h
+; GFX11-TRUE16-NEXT:    v_cmp_gt_u16_e64 s2, 0x3801, v4.h
+; GFX11-TRUE16-NEXT:    v_cmp_gt_u16_e64 s3, 0x3801, v5.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.l, v3.h, 0x3d00, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v3.h, 0x3d00, s0
+; GFX11-TRUE16-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 0x3801, v5.l
+; GFX11-TRUE16-NEXT:    v_cmp_gt_u16_e64 s0, 0x3801, v4.l
+; GFX11-TRUE16-NEXT:    v_cmp_gt_u16_e64 s34, 0x3801, v6.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v3.h, 0x3d00, s2
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v3.h, 0x3d00, s3
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.h, 0x3d00, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v3.h, 0x3d00, s0
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.h, v3.h, 0x3d00, s34
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.h, 0x3d00, v3.h, s1
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: vec_16xi16_extract_8xi16_0:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    scratch_load_u8 v4, off, s32
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 1, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v4
+; GFX11-FAKE16-NEXT:    s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB7_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %F
+; GFX11-FAKE16-NEXT:    global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_vccz .LBB7_3
+; GFX11-FAKE16-NEXT:    s_branch .LBB7_4
+; GFX11-FAKE16-NEXT:  .LBB7_2:
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
+; GFX11-FAKE16-NEXT:  .LBB7_3: ; %T
+; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[0:1], off offset:16 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:  .LBB7_4: ; %exit
+; GFX11-FAKE16-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 0x3801, v5
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, 0x3900
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, 0x3d00
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v3
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, 0x3900, v1, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 0x3801, v4
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, 0x3900, v1, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 0x3801, v7
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, 0x3900, v1, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 0x3801, v3
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, 0x3900, v1, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 0x3801, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x3900, v1, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 0x3801, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x3900, v1, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 0x3801, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x3900, v1, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_lt_u16_e32 vcc_lo, 0x3800, v8
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v7, v4, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, 0x3d00, v9, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v6, v5, 0x5040100
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   br i1 %cond, label %T, label %F
 
 T:
@@ -1717,62 +1956,114 @@ define amdgpu_gfx <8 x half> @vec_16xf16_extract_8xf16_0(i1 inreg %cond, ptr add
 ; GFX9-NEXT:    v_pack_b32_f16 v3, v3, v7
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: vec_16xf16_extract_8xf16_0:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    scratch_load_u8 v4, off, s32
-; GFX11-NEXT:    s_mov_b32 s0, 0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v4, 1, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v4
-; GFX11-NEXT:    s_and_b32 s1, vcc_lo, exec_lo
-; GFX11-NEXT:    s_cbranch_scc0 .LBB8_2
-; GFX11-NEXT:  ; %bb.1: ; %F
-; GFX11-NEXT:    global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_vccz .LBB8_3
-; GFX11-NEXT:    s_branch .LBB8_4
-; GFX11-NEXT:  .LBB8_2:
-; GFX11-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
-; GFX11-NEXT:  .LBB8_3: ; %T
-; GFX11-NEXT:    global_load_b128 v[2:5], v[0:1], off offset:16 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:  .LBB8_4: ; %exit
-; GFX11-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v5
-; GFX11-NEXT:    v_mov_b32_e32 v9, 0x3900
-; GFX11-NEXT:    v_mov_b32_e32 v1, 0x3d00
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 16, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v8, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v5, 0x3900, v1, vcc_lo
-; GFX11-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v4
-; GFX11-NEXT:    v_cndmask_b32_e32 v4, 0x3900, v1, vcc_lo
-; GFX11-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v7
-; GFX11-NEXT:    v_cndmask_b32_e32 v7, 0x3900, v1, vcc_lo
-; GFX11-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, 0x3900, v1, vcc_lo
-; GFX11-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, 0x3900, v1, vcc_lo
-; GFX11-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x3900, v1, vcc_lo
-; GFX11-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_pack_b32_f16 v0, v2, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0x3900, v1, vcc_lo
-; GFX11-NEXT:    v_cmp_nge_f16_e32 vcc_lo, 0.5, v8
-; GFX11-NEXT:    v_pack_b32_f16 v2, v4, v7
-; GFX11-NEXT:    v_pack_b32_f16 v1, v3, v1
-; GFX11-NEXT:    v_cndmask_b32_e32 v6, 0x3d00, v9, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_pack_b32_f16 v3, v5, v6
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: vec_16xf16_extract_8xf16_0:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    scratch_load_u8 v4, off, s32
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 1, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v4
+; GFX11-TRUE16-NEXT:    s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB8_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %F
+; GFX11-TRUE16-NEXT:    global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_vccz .LBB8_3
+; GFX11-TRUE16-NEXT:    s_branch .LBB8_4
+; GFX11-TRUE16-NEXT:  .LBB8_2:
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
+; GFX11-TRUE16-NEXT:  .LBB8_3: ; %T
+; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[0:1], off offset:16 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:  .LBB8_4: ; %exit
+; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v5.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, 0x3d00
+; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e64 s0, 0.5, v4.l
+; GFX11-TRUE16-NEXT:    v_cmp_nge_f16_e64 s1, 0.5, v5.h
+; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e64 s2, 0.5, v2.h
+; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e64 s3, 0.5, v3.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.l, 0x3900, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v5.l, 0x3900, v0.l, s0
+; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v3.l
+; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e64 s0, 0.5, v2.l
+; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e64 s34, 0.5, v4.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, 0x3900, v0.l, s2
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, 0x3900, v0.l, s3
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0x3900, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0x3900, v0.l, s0
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.h, 0x3900, v0.l, s34
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.l, v0.l, 0x3900, s1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v1.h
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.l, v2.l
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v2, v5.l, v2.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v3, v4.l, v3.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: vec_16xf16_extract_8xf16_0:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    scratch_load_u8 v4, off, s32
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 1, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v4
+; GFX11-FAKE16-NEXT:    s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB8_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %F
+; GFX11-FAKE16-NEXT:    global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_vccz .LBB8_3
+; GFX11-FAKE16-NEXT:    s_branch .LBB8_4
+; GFX11-FAKE16-NEXT:  .LBB8_2:
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
+; GFX11-FAKE16-NEXT:  .LBB8_3: ; %T
+; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[0:1], off offset:16 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:  .LBB8_4: ; %exit
+; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v5
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, 0x3900
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, 0x3d00
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v3
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, 0x3900, v1, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v4
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, 0x3900, v1, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v7
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, 0x3900, v1, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v3
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, 0x3900, v1, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x3900, v1, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x3900, v1, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v2, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x3900, v1, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, 0.5, v8
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v2, v4, v7
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v1, v3, v1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, 0x3d00, v9, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v3, v5, v6
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   br i1 %cond, label %T, label %F
 
 T:
diff --git a/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll b/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
index 9919497acea73..bc541043f1fab 100644
--- a/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
@@ -2,8 +2,10 @@
 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX678,GFX6 %s
 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX678,GFX8 %s
 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
 
 declare float @llvm.fabs.f32(float) #0
 declare float @llvm.canonicalize.f32(float) #0
@@ -2401,31 +2403,57 @@ define amdgpu_kernel void @test_canonicalize_value_f16_flush(ptr addrspace(1) %a
 ; GFX9-NEXT:    global_store_short v0, v1, s[2:3]
 ; GFX9-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: test_canonicalize_value_f16_flush:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u16 v1, v0, s[0:1]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX11-NEXT:    global_store_b16 v0, v1, s[2:3]
-; GFX11-NEXT:    s_endpgm
-;
-; GFX12-LABEL: test_canonicalize_value_f16_flush:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u16 v1, v0, s[0:1]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_max_num_f16_e32 v1, v1, v1
-; GFX12-NEXT:    global_store_b16 v0, v1, s[2:3]
-; GFX12-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: test_canonicalize_value_f16_flush:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[0:1]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[2:3]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: test_canonicalize_value_f16_flush:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[0:1]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[2:3]
+; GFX11-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-TRUE16-LABEL: test_canonicalize_value_f16_flush:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[0:1]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-TRUE16-NEXT:    global_store_b16 v1, v0, s[2:3]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: test_canonicalize_value_f16_flush:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u16 v1, v0, s[0:1]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v1, v1, v1
+; GFX12-FAKE16-NEXT:    global_store_b16 v0, v1, s[2:3]
+; GFX12-FAKE16-NEXT:    s_endpgm
   %id = tail call i32 @llvm.amdgcn.workitem.id.x()
   %gep = getelementptr inbounds half, ptr addrspace(1) %arg, i32 %id
   %v = load half, ptr addrspace(1) %gep, align 2
@@ -2757,31 +2785,57 @@ define amdgpu_kernel void @test_canonicalize_value_f16_denorm(ptr addrspace(1) %
 ; GFX9-NEXT:    global_store_short v0, v1, s[2:3]
 ; GFX9-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: test_canonicalize_value_f16_denorm:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u16 v1, v0, s[0:1]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX11-NEXT:    global_store_b16 v0, v1, s[2:3]
-; GFX11-NEXT:    s_endpgm
-;
-; GFX12-LABEL: test_canonicalize_value_f16_denorm:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u16 v1, v0, s[0:1]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_max_num_f16_e32 v1, v1, v1
-; GFX12-NEXT:    global_store_b16 v0, v1, s[2:3]
-; GFX12-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: test_canonicalize_value_f16_denorm:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[0:1]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[2:3]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: test_canonicalize_value_f16_denorm:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[0:1]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[2:3]
+; GFX11-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-TRUE16-LABEL: test_canonicalize_value_f16_denorm:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[0:1]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-TRUE16-NEXT:    global_store_b16 v1, v0, s[2:3]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: test_canonicalize_value_f16_denorm:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u16 v1, v0, s[0:1]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v1, v1, v1
+; GFX12-FAKE16-NEXT:    global_store_b16 v0, v1, s[2:3]
+; GFX12-FAKE16-NEXT:    s_endpgm
   %id = tail call i32 @llvm.amdgcn.workitem.id.x()
   %gep = getelementptr inbounds half, ptr addrspace(1) %arg, i32 %id
   %v = load half, ptr addrspace(1) %gep, align 2
diff --git a/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll b/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
index 3156a1280afea..1d83d33a4f832 100644
--- a/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
@@ -3,7 +3,8 @@
 ; RUN:  llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=VI %s
 ; RUN:  llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global,+real-true16 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=GFX11-TRUE16 %s
 ; RUN:  llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global,-real-true16 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=GFX11-FAKE16 %s
-; RUN:  llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1200 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=GFX12 %s
+; RUN:  llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN:  llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=GFX12,GFX12-FAKE16 %s
 
 define amdgpu_kernel void @fcmp_f16_lt(
 ; SI-LABEL: fcmp_f16_lt:
@@ -106,30 +107,55 @@ define amdgpu_kernel void @fcmp_f16_lt(
 ; GFX11-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_f16_lt:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b32 v0, off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_f16_lt:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_f16_lt:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -245,33 +271,61 @@ define amdgpu_kernel void @fcmp_f16_lt_abs(
 ; GFX11-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_f16_lt_abs:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
-; GFX12-NEXT:    v_and_b32_e32 v1, 0x7fff, v1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b32 v0, off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_f16_lt_abs:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v1, 0x7fff, v1
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_f16_lt_abs:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0x7fff, v1
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -387,30 +441,55 @@ define amdgpu_kernel void @fcmp_f16_eq(
 ; GFX11-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_f16_eq:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    v_cmp_eq_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b32 v0, off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_f16_eq:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    v_cmp_eq_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_f16_eq:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    v_cmp_eq_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -524,30 +603,55 @@ define amdgpu_kernel void @fcmp_f16_le(
 ; GFX11-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_f16_le:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    v_cmp_le_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b32 v0, off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_f16_le:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_f16_le:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -661,30 +765,55 @@ define amdgpu_kernel void @fcmp_f16_gt(
 ; GFX11-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_f16_gt:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b32 v0, off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_f16_gt:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_f16_gt:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -798,30 +927,55 @@ define amdgpu_kernel void @fcmp_f16_lg(
 ; GFX11-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_f16_lg:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    v_cmp_lg_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b32 v0, off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_f16_lg:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_f16_lg:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -935,30 +1089,55 @@ define amdgpu_kernel void @fcmp_f16_ge(
 ; GFX11-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_f16_ge:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b32 v0, off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_f16_ge:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_f16_ge:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -1072,30 +1251,55 @@ define amdgpu_kernel void @fcmp_f16_o(
 ; GFX11-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_f16_o:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b32 v0, off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_f16_o:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_f16_o:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -1209,30 +1413,55 @@ define amdgpu_kernel void @fcmp_f16_u(
 ; GFX11-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_f16_u:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    v_cmp_u_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b32 v0, off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_f16_u:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    v_cmp_u_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_f16_u:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    v_cmp_u_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -1346,30 +1575,55 @@ define amdgpu_kernel void @fcmp_f16_nge(
 ; GFX11-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_f16_nge:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b32 v0, off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_f16_nge:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_f16_nge:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -1483,30 +1737,55 @@ define amdgpu_kernel void @fcmp_f16_nlg(
 ; GFX11-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_f16_nlg:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    v_cmp_nlg_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b32 v0, off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_f16_nlg:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    v_cmp_nlg_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_f16_nlg:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    v_cmp_nlg_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -1620,30 +1899,55 @@ define amdgpu_kernel void @fcmp_f16_ngt(
 ; GFX11-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_f16_ngt:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b32 v0, off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_f16_ngt:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_f16_ngt:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -1757,30 +2061,55 @@ define amdgpu_kernel void @fcmp_f16_nle(
 ; GFX11-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_f16_nle:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b32 v0, off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_f16_nle:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_f16_nle:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -1894,30 +2223,55 @@ define amdgpu_kernel void @fcmp_f16_neq(
 ; GFX11-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_f16_neq:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    v_cmp_neq_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b32 v0, off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_f16_neq:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    v_cmp_neq_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_f16_neq:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    v_cmp_neq_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -2031,30 +2385,55 @@ define amdgpu_kernel void @fcmp_f16_nlt(
 ; GFX11-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_f16_nlt:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b32 v0, off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_f16_nlt:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_f16_nlt:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b32 v0, off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -2188,36 +2567,67 @@ define amdgpu_kernel void @fcmp_v2f16_lt(
 ; GFX11-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_v2f16_lt:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_b32 v0, off, s[4:7], null
-; GFX12-NEXT:    buffer_load_b32 v1, off, s[12:15], null
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    s_wait_loadcnt 0x1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v1, v0
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX12-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v3, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_v2f16_lt:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-TRUE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v1.l, v0.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-TRUE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v3.l, v2.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_v2f16_lt:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-FAKE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v1, v0
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_cmp_lt_f16_e32 vcc_lo, v3, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -2352,36 +2762,67 @@ define amdgpu_kernel void @fcmp_v2f16_eq(
 ; GFX11-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_v2f16_eq:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_b32 v0, off, s[4:7], null
-; GFX12-NEXT:    buffer_load_b32 v1, off, s[12:15], null
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    s_wait_loadcnt 0x1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-NEXT:    v_cmp_eq_f16_e32 vcc_lo, v1, v0
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX12-NEXT:    v_cmp_eq_f16_e32 vcc_lo, v3, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_v2f16_eq:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-TRUE16-NEXT:    v_cmp_eq_f16_e32 vcc_lo, v1.l, v0.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-TRUE16-NEXT:    v_cmp_eq_f16_e32 vcc_lo, v3.l, v2.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_v2f16_eq:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-FAKE16-NEXT:    v_cmp_eq_f16_e32 vcc_lo, v1, v0
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_cmp_eq_f16_e32 vcc_lo, v3, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -2515,36 +2956,67 @@ define amdgpu_kernel void @fcmp_v2f16_le(
 ; GFX11-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_v2f16_le:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_b32 v0, off, s[4:7], null
-; GFX12-NEXT:    buffer_load_b32 v1, off, s[12:15], null
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    s_wait_loadcnt 0x1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-NEXT:    v_cmp_le_f16_e32 vcc_lo, v1, v0
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX12-NEXT:    v_cmp_le_f16_e32 vcc_lo, v3, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_v2f16_le:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-TRUE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v1.l, v0.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-TRUE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v3.l, v2.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_v2f16_le:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-FAKE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v1, v0
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_cmp_le_f16_e32 vcc_lo, v3, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -2678,36 +3150,67 @@ define amdgpu_kernel void @fcmp_v2f16_gt(
 ; GFX11-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_v2f16_gt:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_b32 v0, off, s[4:7], null
-; GFX12-NEXT:    buffer_load_b32 v1, off, s[12:15], null
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    s_wait_loadcnt 0x1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v1, v0
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX12-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v3, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_v2f16_gt:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-TRUE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v1.l, v0.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-TRUE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v3.l, v2.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_v2f16_gt:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-FAKE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v1, v0
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_cmp_gt_f16_e32 vcc_lo, v3, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -2842,36 +3345,67 @@ define amdgpu_kernel void @fcmp_v2f16_lg(
 ; GFX11-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_v2f16_lg:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_b32 v0, off, s[4:7], null
-; GFX12-NEXT:    buffer_load_b32 v1, off, s[12:15], null
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    s_wait_loadcnt 0x1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-NEXT:    v_cmp_lg_f16_e32 vcc_lo, v1, v0
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX12-NEXT:    v_cmp_lg_f16_e32 vcc_lo, v3, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_v2f16_lg:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, v1.l, v0.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, v3.l, v2.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_v2f16_lg:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, v1, v0
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, v3, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -3006,36 +3540,67 @@ define amdgpu_kernel void @fcmp_v2f16_ge(
 ; GFX11-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_v2f16_ge:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_b32 v0, off, s[4:7], null
-; GFX12-NEXT:    buffer_load_b32 v1, off, s[12:15], null
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    s_wait_loadcnt 0x1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v1, v0
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX12-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v3, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_v2f16_ge:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-TRUE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v1.l, v0.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-TRUE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v3.l, v2.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_v2f16_ge:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v1, v0
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, v3, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -3170,36 +3735,67 @@ define amdgpu_kernel void @fcmp_v2f16_o(
 ; GFX11-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_v2f16_o:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_b32 v0, off, s[4:7], null
-; GFX12-NEXT:    buffer_load_b32 v1, off, s[12:15], null
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    s_wait_loadcnt 0x1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-NEXT:    v_cmp_o_f16_e32 vcc_lo, v1, v0
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX12-NEXT:    v_cmp_o_f16_e32 vcc_lo, v3, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_v2f16_o:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v1.l, v0.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v3.l, v2.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_v2f16_o:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v1, v0
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v3, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -3334,36 +3930,67 @@ define amdgpu_kernel void @fcmp_v2f16_u(
 ; GFX11-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_v2f16_u:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_b32 v0, off, s[4:7], null
-; GFX12-NEXT:    buffer_load_b32 v1, off, s[12:15], null
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    s_wait_loadcnt 0x1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-NEXT:    v_cmp_u_f16_e32 vcc_lo, v1, v0
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX12-NEXT:    v_cmp_u_f16_e32 vcc_lo, v3, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_v2f16_u:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-TRUE16-NEXT:    v_cmp_u_f16_e32 vcc_lo, v1.l, v0.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-TRUE16-NEXT:    v_cmp_u_f16_e32 vcc_lo, v3.l, v2.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_v2f16_u:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-FAKE16-NEXT:    v_cmp_u_f16_e32 vcc_lo, v1, v0
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_cmp_u_f16_e32 vcc_lo, v3, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -3497,36 +4124,67 @@ define amdgpu_kernel void @fcmp_v2f16_nge(
 ; GFX11-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_v2f16_nge:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_b32 v0, off, s[4:7], null
-; GFX12-NEXT:    buffer_load_b32 v1, off, s[12:15], null
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    s_wait_loadcnt 0x1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v1, v0
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX12-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v3, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_v2f16_nge:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-TRUE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v1.l, v0.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-TRUE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v3.l, v2.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_v2f16_nge:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-FAKE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v1, v0
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, v3, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -3660,36 +4318,67 @@ define amdgpu_kernel void @fcmp_v2f16_nlg(
 ; GFX11-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_v2f16_nlg:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_b32 v0, off, s[4:7], null
-; GFX12-NEXT:    buffer_load_b32 v1, off, s[12:15], null
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    s_wait_loadcnt 0x1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-NEXT:    v_cmp_nlg_f16_e32 vcc_lo, v1, v0
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX12-NEXT:    v_cmp_nlg_f16_e32 vcc_lo, v3, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_v2f16_nlg:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-TRUE16-NEXT:    v_cmp_nlg_f16_e32 vcc_lo, v1.l, v0.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-TRUE16-NEXT:    v_cmp_nlg_f16_e32 vcc_lo, v3.l, v2.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_v2f16_nlg:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-FAKE16-NEXT:    v_cmp_nlg_f16_e32 vcc_lo, v1, v0
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_cmp_nlg_f16_e32 vcc_lo, v3, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -3824,36 +4513,67 @@ define amdgpu_kernel void @fcmp_v2f16_ngt(
 ; GFX11-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_v2f16_ngt:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_b32 v0, off, s[4:7], null
-; GFX12-NEXT:    buffer_load_b32 v1, off, s[12:15], null
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    s_wait_loadcnt 0x1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v1, v0
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX12-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v3, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_v2f16_ngt:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v1.l, v0.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v3.l, v2.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_v2f16_ngt:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v1, v0
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v3, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -3987,36 +4707,67 @@ define amdgpu_kernel void @fcmp_v2f16_nle(
 ; GFX11-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_v2f16_nle:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_b32 v0, off, s[4:7], null
-; GFX12-NEXT:    buffer_load_b32 v1, off, s[12:15], null
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    s_wait_loadcnt 0x1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v1, v0
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX12-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v3, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_v2f16_nle:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-TRUE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v1.l, v0.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-TRUE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v3.l, v2.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_v2f16_nle:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-FAKE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v1, v0
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v3, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -4150,36 +4901,67 @@ define amdgpu_kernel void @fcmp_v2f16_neq(
 ; GFX11-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_v2f16_neq:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_b32 v0, off, s[4:7], null
-; GFX12-NEXT:    buffer_load_b32 v1, off, s[12:15], null
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    s_wait_loadcnt 0x1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-NEXT:    v_cmp_neq_f16_e32 vcc_lo, v1, v0
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX12-NEXT:    v_cmp_neq_f16_e32 vcc_lo, v3, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_v2f16_neq:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-TRUE16-NEXT:    v_cmp_neq_f16_e32 vcc_lo, v1.l, v0.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-TRUE16-NEXT:    v_cmp_neq_f16_e32 vcc_lo, v3.l, v2.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_v2f16_neq:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-FAKE16-NEXT:    v_cmp_neq_f16_e32 vcc_lo, v1, v0
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_cmp_neq_f16_e32 vcc_lo, v3, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -4313,36 +5095,67 @@ define amdgpu_kernel void @fcmp_v2f16_nlt(
 ; GFX11-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], 0
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: fcmp_v2f16_nlt:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_clause 0x1
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s6, s10
-; GFX12-NEXT:    s_mov_b32 s7, s11
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    buffer_load_b32 v0, off, s[4:7], null
-; GFX12-NEXT:    buffer_load_b32 v1, off, s[12:15], null
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    s_wait_loadcnt 0x1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v1, v0
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX12-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v3, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX12-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: fcmp_v2f16_nlt:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_clause 0x1
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-TRUE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v1.l, v0.l
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v3.l, v2.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-TRUE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: fcmp_v2f16_nlt:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_clause 0x1
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s6, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s7, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v0, off, s[4:7], null
+; GFX12-FAKE16-NEXT:    buffer_load_b32 v1, off, s[12:15], null
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v1, v0
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v3, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX12-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -4359,3 +5172,5 @@ declare half @llvm.fabs.f16(half) #1
 
 attributes #0 = { nounwind }
 attributes #1 = { nounwind readnone }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX12: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll b/llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
index c3694f3b92fb4..37cbd2d926413 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
@@ -278,5 +278,3 @@ define amdgpu_kernel void @kernel_no_calls_no_stack() {
 
 attributes #0 = { nounwind }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/fmax3.ll b/llvm/test/CodeGen/AMDGPU/fmax3.ll
index fbcdbed338e60..86ebf3fc3e9de 100644
--- a/llvm/test/CodeGen/AMDGPU/fmax3.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmax3.ll
@@ -2,8 +2,10 @@
 ; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=SI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-FAKE16 %s
 
 define amdgpu_kernel void @test_fmax3_olt_0_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) #0 {
 ; SI-LABEL: test_fmax3_olt_0_f32:
@@ -423,65 +425,125 @@ define amdgpu_kernel void @test_fmax3_olt_0_f16(ptr addrspace(1) %out, ptr addrs
 ; GFX9-NEXT:    buffer_store_short v0, off, s[0:3], 0
 ; GFX9-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: test_fmax3_olt_0_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
-; GFX11-NEXT:    s_mov_b32 s10, -1
-; GFX11-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s14, s10
-; GFX11-NEXT:    s_mov_b32 s15, s11
-; GFX11-NEXT:    s_mov_b32 s18, s10
-; GFX11-NEXT:    s_mov_b32 s19, s11
-; GFX11-NEXT:    s_mov_b32 s22, s10
-; GFX11-NEXT:    s_mov_b32 s23, s11
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s12, s2
-; GFX11-NEXT:    s_mov_b32 s13, s3
-; GFX11-NEXT:    s_mov_b32 s16, s4
-; GFX11-NEXT:    s_mov_b32 s17, s5
-; GFX11-NEXT:    s_mov_b32 s20, s6
-; GFX11-NEXT:    s_mov_b32 s21, s7
-; GFX11-NEXT:    buffer_load_u16 v0, off, s[12:15], 0 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    buffer_load_u16 v1, off, s[16:19], 0 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    buffer_load_u16 v2, off, s[20:23], 0 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s8, s0
-; GFX11-NEXT:    s_mov_b32 s9, s1
-; GFX11-NEXT:    v_max3_f16 v0, v0, v1, v2
-; GFX11-NEXT:    buffer_store_b16 v0, off, s[8:11], 0
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: test_fmax3_olt_0_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX11-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX11-TRUE16-NEXT:    s_mov_b32 s18, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s19, s11
+; GFX11-TRUE16-NEXT:    s_mov_b32 s22, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s23, s11
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s16, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s17, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s20, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s21, s7
+; GFX11-TRUE16-NEXT:    buffer_load_u16 v0, off, s[12:15], 0 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    buffer_load_u16 v1, off, s[16:19], 0 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    buffer_load_u16 v2, off, s[20:23], 0 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX11-TRUE16-NEXT:    v_max3_f16 v0.l, v0.l, v1.l, v2.l
+; GFX11-TRUE16-NEXT:    buffer_store_b16 v0, off, s[8:11], 0
+; GFX11-TRUE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: test_fmax3_olt_0_f16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_mov_b32 s18, s10
-; GFX12-NEXT:    s_mov_b32 s19, s11
-; GFX12-NEXT:    s_mov_b32 s22, s10
-; GFX12-NEXT:    s_mov_b32 s23, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    s_mov_b32 s16, s4
-; GFX12-NEXT:    s_mov_b32 s17, s5
-; GFX12-NEXT:    s_mov_b32 s20, s6
-; GFX12-NEXT:    s_mov_b32 s21, s7
-; GFX12-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    buffer_load_u16 v1, off, s[16:19], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    buffer_load_u16 v2, off, s[20:23], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    v_max3_num_f16 v0, v0, v1, v2
-; GFX12-NEXT:    buffer_store_b16 v0, off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX11-FAKE16-LABEL: test_fmax3_olt_0_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX11-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX11-FAKE16-NEXT:    s_mov_b32 s18, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s19, s11
+; GFX11-FAKE16-NEXT:    s_mov_b32 s22, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s23, s11
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s16, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s17, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s20, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s21, s7
+; GFX11-FAKE16-NEXT:    buffer_load_u16 v0, off, s[12:15], 0 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    buffer_load_u16 v1, off, s[16:19], 0 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    buffer_load_u16 v2, off, s[20:23], 0 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX11-FAKE16-NEXT:    v_max3_f16 v0, v0, v1, v2
+; GFX11-FAKE16-NEXT:    buffer_store_b16 v0, off, s[8:11], 0
+; GFX11-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-TRUE16-LABEL: test_fmax3_olt_0_f16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s18, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s19, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s22, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s23, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s16, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s17, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s20, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s21, s7
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v1, off, s[16:19], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v2, off, s[20:23], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    v_max3_num_f16 v0.l, v0.l, v1.l, v2.l
+; GFX12-TRUE16-NEXT:    buffer_store_b16 v0, off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: test_fmax3_olt_0_f16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s18, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s19, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s22, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s23, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s16, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s17, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s20, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s21, s7
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v1, off, s[16:19], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v2, off, s[20:23], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    v_max3_num_f16 v0, v0, v1, v2
+; GFX12-FAKE16-NEXT:    buffer_store_b16 v0, off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
   %a = load volatile half, ptr addrspace(1) %aptr, align 2
   %b = load volatile half, ptr addrspace(1) %bptr, align 2
   %c = load volatile half, ptr addrspace(1) %cptr, align 2
@@ -591,65 +653,125 @@ define amdgpu_kernel void @test_fmax3_olt_1_f16(ptr addrspace(1) %out, ptr addrs
 ; GFX9-NEXT:    buffer_store_short v0, off, s[0:3], 0
 ; GFX9-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: test_fmax3_olt_1_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
-; GFX11-NEXT:    s_mov_b32 s10, -1
-; GFX11-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s14, s10
-; GFX11-NEXT:    s_mov_b32 s15, s11
-; GFX11-NEXT:    s_mov_b32 s18, s10
-; GFX11-NEXT:    s_mov_b32 s19, s11
-; GFX11-NEXT:    s_mov_b32 s22, s10
-; GFX11-NEXT:    s_mov_b32 s23, s11
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s12, s2
-; GFX11-NEXT:    s_mov_b32 s13, s3
-; GFX11-NEXT:    s_mov_b32 s16, s4
-; GFX11-NEXT:    s_mov_b32 s17, s5
-; GFX11-NEXT:    s_mov_b32 s20, s6
-; GFX11-NEXT:    s_mov_b32 s21, s7
-; GFX11-NEXT:    buffer_load_u16 v0, off, s[12:15], 0 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    buffer_load_u16 v1, off, s[16:19], 0 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    buffer_load_u16 v2, off, s[20:23], 0 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s8, s0
-; GFX11-NEXT:    s_mov_b32 s9, s1
-; GFX11-NEXT:    v_max3_f16 v0, v2, v0, v1
-; GFX11-NEXT:    buffer_store_b16 v0, off, s[8:11], 0
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: test_fmax3_olt_1_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX11-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX11-TRUE16-NEXT:    s_mov_b32 s18, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s19, s11
+; GFX11-TRUE16-NEXT:    s_mov_b32 s22, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s23, s11
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s16, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s17, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s20, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s21, s7
+; GFX11-TRUE16-NEXT:    buffer_load_u16 v1, off, s[12:15], 0 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    buffer_load_u16 v2, off, s[16:19], 0 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    buffer_load_u16 v0, off, s[20:23], 0 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX11-TRUE16-NEXT:    v_max3_f16 v0.l, v0.l, v1.l, v2.l
+; GFX11-TRUE16-NEXT:    buffer_store_b16 v0, off, s[8:11], 0
+; GFX11-TRUE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: test_fmax3_olt_1_f16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_mov_b32 s18, s10
-; GFX12-NEXT:    s_mov_b32 s19, s11
-; GFX12-NEXT:    s_mov_b32 s22, s10
-; GFX12-NEXT:    s_mov_b32 s23, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    s_mov_b32 s16, s4
-; GFX12-NEXT:    s_mov_b32 s17, s5
-; GFX12-NEXT:    s_mov_b32 s20, s6
-; GFX12-NEXT:    s_mov_b32 s21, s7
-; GFX12-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    buffer_load_u16 v1, off, s[16:19], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    buffer_load_u16 v2, off, s[20:23], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    v_max3_num_f16 v0, v2, v0, v1
-; GFX12-NEXT:    buffer_store_b16 v0, off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX11-FAKE16-LABEL: test_fmax3_olt_1_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX11-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX11-FAKE16-NEXT:    s_mov_b32 s18, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s19, s11
+; GFX11-FAKE16-NEXT:    s_mov_b32 s22, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s23, s11
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s16, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s17, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s20, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s21, s7
+; GFX11-FAKE16-NEXT:    buffer_load_u16 v0, off, s[12:15], 0 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    buffer_load_u16 v1, off, s[16:19], 0 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    buffer_load_u16 v2, off, s[20:23], 0 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX11-FAKE16-NEXT:    v_max3_f16 v0, v2, v0, v1
+; GFX11-FAKE16-NEXT:    buffer_store_b16 v0, off, s[8:11], 0
+; GFX11-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-TRUE16-LABEL: test_fmax3_olt_1_f16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s18, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s19, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s22, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s23, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s16, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s17, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s20, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s21, s7
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v1, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v2, off, s[16:19], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v0, off, s[20:23], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    v_max3_num_f16 v0.l, v0.l, v1.l, v2.l
+; GFX12-TRUE16-NEXT:    buffer_store_b16 v0, off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: test_fmax3_olt_1_f16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s18, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s19, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s22, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s23, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s16, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s17, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s20, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s21, s7
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v1, off, s[16:19], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v2, off, s[20:23], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    v_max3_num_f16 v0, v2, v0, v1
+; GFX12-FAKE16-NEXT:    buffer_store_b16 v0, off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
   %a = load volatile half, ptr addrspace(1) %aptr, align 2
   %b = load volatile half, ptr addrspace(1) %bptr, align 2
   %c = load volatile half, ptr addrspace(1) %cptr, align 2
diff --git a/llvm/test/CodeGen/AMDGPU/fmaximum.ll b/llvm/test/CodeGen/AMDGPU/fmaximum.ll
index fe8150b3c21c4..0adbecd952ae3 100644
--- a/llvm/test/CodeGen/AMDGPU/fmaximum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmaximum.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX12-SDAG %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX12-GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
 
 define amdgpu_ps float @test_fmaximum_f32_vv(float %a, float %b) {
 ; GCN-LABEL: test_fmaximum_f32_vv:
@@ -110,10 +112,25 @@ define amdgpu_ps <16 x float> @test_fmaximum_v16f32(<16 x float> %a, <16 x float
 }
 
 define amdgpu_ps half @test_fmaximum_f16_vv(half %a, half %b) {
-; GCN-LABEL: test_fmaximum_f16_vv:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    v_maximum_f16 v0, v0, v1
-; GCN-NEXT:    ; return to shader part epilog
+; GFX12-SDAG-TRUE16-LABEL: test_fmaximum_f16_vv:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    v_maximum_f16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-SDAG-FAKE16-LABEL: test_fmaximum_f16_vv:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    v_maximum_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-TRUE16-LABEL: test_fmaximum_f16_vv:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    v_maximum_f16 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-FAKE16-LABEL: test_fmaximum_f16_vv:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    v_maximum_f16 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    ; return to shader part epilog
   %val = call half @llvm.maximum.f16(half %a, half %b)
   ret half %val
 }
@@ -154,11 +171,17 @@ define amdgpu_ps <3 x half> @test_fmaximum_v3f16_vv(<3 x half> %a, <3 x half> %b
 ; GFX12-SDAG-NEXT:    v_pk_maximum_f16 v1, v1, v3
 ; GFX12-SDAG-NEXT:    ; return to shader part epilog
 ;
-; GFX12-GISEL-LABEL: test_fmaximum_v3f16_vv:
-; GFX12-GISEL:       ; %bb.0:
-; GFX12-GISEL-NEXT:    v_pk_maximum_f16 v0, v0, v2
-; GFX12-GISEL-NEXT:    v_maximum_f16 v1, v1, v3
-; GFX12-GISEL-NEXT:    ; return to shader part epilog
+; GFX12-GISEL-TRUE16-LABEL: test_fmaximum_v3f16_vv:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    v_maximum_f16 v1.l, v1.l, v3.l
+; GFX12-GISEL-TRUE16-NEXT:    v_pk_maximum_f16 v0, v0, v2
+; GFX12-GISEL-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-FAKE16-LABEL: test_fmaximum_v3f16_vv:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    v_pk_maximum_f16 v0, v0, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_maximum_f16 v1, v1, v3
+; GFX12-GISEL-FAKE16-NEXT:    ; return to shader part epilog
   %val = call <3 x half> @llvm.maximum.v3f16(<3 x half> %a, <3 x half> %b)
   ret <3 x half> %val
 }
@@ -282,20 +305,65 @@ define amdgpu_kernel void @fmaximumi_f32_move_to_valu(ptr addrspace(1) %out, ptr
 }
 
 define amdgpu_kernel void @fmaximum_f16_move_to_valu(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {
-; GCN-LABEL: fmaximum_f16_move_to_valu:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_clause 0x1
-; GCN-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GCN-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GCN-NEXT:    v_mov_b32_e32 v0, 0
-; GCN-NEXT:    s_wait_kmcnt 0x0
-; GCN-NEXT:    global_load_u16 v1, v0, s[2:3] scope:SCOPE_SYS
-; GCN-NEXT:    s_wait_loadcnt 0x0
-; GCN-NEXT:    global_load_u16 v2, v0, s[4:5] scope:SCOPE_SYS
-; GCN-NEXT:    s_wait_loadcnt 0x0
-; GCN-NEXT:    v_maximum_f16 v1, v1, v2
-; GCN-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GCN-NEXT:    s_endpgm
+; GFX12-SDAG-TRUE16-LABEL: fmaximum_f16_move_to_valu:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_clause 0x1
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3] scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_hi_b16 v0, v1, s[4:5] scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_maximum_f16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: fmaximum_f16_move_to_valu:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_clause 0x1
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3] scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u16 v2, v0, s[4:5] scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_maximum_f16 v1, v1, v2
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-GISEL-TRUE16-LABEL: fmaximum_f16_move_to_valu:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    s_clause 0x1
+; GFX12-GISEL-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-GISEL-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3] scope:SCOPE_SYS
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    global_load_d16_hi_b16 v0, v1, s[4:5] scope:SCOPE_SYS
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_maximum_f16 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX12-GISEL-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-GISEL-FAKE16-LABEL: fmaximum_f16_move_to_valu:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    s_clause 0x1
+; GFX12-GISEL-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-GISEL-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3] scope:SCOPE_SYS
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    global_load_u16 v2, v0, s[4:5] scope:SCOPE_SYS
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_maximum_f16 v1, v1, v2
+; GFX12-GISEL-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX12-GISEL-FAKE16-NEXT:    s_endpgm
   %a = load volatile half, ptr addrspace(1) %aptr, align 4
   %b = load volatile half, ptr addrspace(1) %bptr, align 4
   %v = call half @llvm.maximum.f16(half %a, half %b)
diff --git a/llvm/test/CodeGen/AMDGPU/fmaximum3.ll b/llvm/test/CodeGen/AMDGPU/fmaximum3.ll
index 2a372dffce650..1b8a79ee982d1 100644
--- a/llvm/test/CodeGen/AMDGPU/fmaximum3.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmaximum3.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX942 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX9,GFX950 %s
 
@@ -1242,15 +1243,25 @@ define <3 x float> @v_fmaximum3_v3f32__inlineimm2(<3 x float> %a, <3 x float> %b
 
 
 define half @v_fmaximum3_f16(half %a, half %b, half %c) {
-; GFX12-LABEL: v_fmaximum3_f16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_maximum3_f16 v0, v0, v1, v2
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fmaximum3_f16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_maximum3_f16 v0.l, v0.l, v1.l, v2.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fmaximum3_f16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_maximum3_f16 v0, v0, v1, v2
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fmaximum3_f16:
 ; GFX942:       ; %bb.0:
@@ -1277,15 +1288,25 @@ define half @v_fmaximum3_f16(half %a, half %b, half %c) {
 }
 
 define half @v_fmaximum3_f16_commute(half %a, half %b, half %c) {
-; GFX12-LABEL: v_fmaximum3_f16_commute:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_maximum3_f16 v0, v2, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fmaximum3_f16_commute:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_maximum3_f16 v0.l, v2.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fmaximum3_f16_commute:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_maximum3_f16 v0, v2, v0, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fmaximum3_f16_commute:
 ; GFX942:       ; %bb.0:
@@ -1312,16 +1333,27 @@ define half @v_fmaximum3_f16_commute(half %a, half %b, half %c) {
 }
 
 define amdgpu_ps i32 @s_fmaximum3_f16(half inreg %a, half inreg %b, half inreg %c) {
-; GFX12-LABEL: s_fmaximum3_f16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    v_mov_b32_e32 v0, s2
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_maximum3_f16 v0, s0, s1, v0
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX12-NEXT:    s_wait_alu 0xf1ff
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX12-TRUE16-LABEL: s_fmaximum3_f16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.l, s2
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_maximum3_f16 v0.l, s0, s1, v0.l
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: s_fmaximum3_f16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v0, s2
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_maximum3_f16 v0, s0, s1, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 ;
 ; GFX942-LABEL: s_fmaximum3_f16:
 ; GFX942:       ; %bb.0:
@@ -1359,15 +1391,25 @@ define amdgpu_ps i32 @s_fmaximum3_f16(half inreg %a, half inreg %b, half inreg %
 }
 
 define half @v_fmaximum3_f16_fabs0(half %a, half %b, half %c) {
-; GFX12-LABEL: v_fmaximum3_f16_fabs0:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_maximum3_f16 v0, |v0|, v1, v2
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fmaximum3_f16_fabs0:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_maximum3_f16 v0.l, |v0.l|, v1.l, v2.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fmaximum3_f16_fabs0:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_maximum3_f16 v0, |v0|, v1, v2
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fmaximum3_f16_fabs0:
 ; GFX942:       ; %bb.0:
@@ -1396,15 +1438,25 @@ define half @v_fmaximum3_f16_fabs0(half %a, half %b, half %c) {
 }
 
 define half @v_fmaximum3_f16_fabs1(half %a, half %b, half %c) {
-; GFX12-LABEL: v_fmaximum3_f16_fabs1:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_maximum3_f16 v0, v0, |v1|, v2
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fmaximum3_f16_fabs1:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_maximum3_f16 v0.l, v0.l, |v1.l|, v2.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fmaximum3_f16_fabs1:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_maximum3_f16 v0, v0, |v1|, v2
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fmaximum3_f16_fabs1:
 ; GFX942:       ; %bb.0:
@@ -1433,15 +1485,25 @@ define half @v_fmaximum3_f16_fabs1(half %a, half %b, half %c) {
 }
 
 define half @v_fmaximum3_f16_fabs2(half %a, half %b, half %c) {
-; GFX12-LABEL: v_fmaximum3_f16_fabs2:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_maximum3_f16 v0, v0, v1, |v2|
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fmaximum3_f16_fabs2:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_maximum3_f16 v0.l, v0.l, v1.l, |v2.l|
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fmaximum3_f16_fabs2:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_maximum3_f16 v0, v0, v1, |v2|
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fmaximum3_f16_fabs2:
 ; GFX942:       ; %bb.0:
@@ -1470,15 +1532,25 @@ define half @v_fmaximum3_f16_fabs2(half %a, half %b, half %c) {
 }
 
 define half @v_fmaximum3_f16_fabs_all(half %a, half %b, half %c) {
-; GFX12-LABEL: v_fmaximum3_f16_fabs_all:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_maximum3_f16 v0, |v0|, |v1|, |v2|
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fmaximum3_f16_fabs_all:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_maximum3_f16 v0.l, |v0.l|, |v1.l|, |v2.l|
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fmaximum3_f16_fabs_all:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_maximum3_f16 v0, |v0|, |v1|, |v2|
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fmaximum3_f16_fabs_all:
 ; GFX942:       ; %bb.0:
@@ -1511,15 +1583,25 @@ define half @v_fmaximum3_f16_fabs_all(half %a, half %b, half %c) {
 }
 
 define half @v_fmaximum3_f16_fneg_all(half %a, half %b, half %c) {
-; GFX12-LABEL: v_fmaximum3_f16_fneg_all:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_maximum3_f16 v0, -v0, -v1, -v2
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fmaximum3_f16_fneg_all:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_maximum3_f16 v0.l, -v0.l, -v1.l, -v2.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fmaximum3_f16_fneg_all:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_maximum3_f16 v0, -v0, -v1, -v2
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fmaximum3_f16_fneg_all:
 ; GFX942:       ; %bb.0:
@@ -1552,15 +1634,25 @@ define half @v_fmaximum3_f16_fneg_all(half %a, half %b, half %c) {
 }
 
 define half @v_fmaximum3_f16_fneg_fabs_all(half %a, half %b, half %c) {
-; GFX12-LABEL: v_fmaximum3_f16_fneg_fabs_all:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_maximum3_f16 v0, -|v0|, -|v1|, -|v2|
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fmaximum3_f16_fneg_fabs_all:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_maximum3_f16 v0.l, -|v0.l|, -|v1.l|, -|v2.l|
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fmaximum3_f16_fneg_fabs_all:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_maximum3_f16 v0, -|v0|, -|v1|, -|v2|
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fmaximum3_f16_fneg_fabs_all:
 ; GFX942:       ; %bb.0:
@@ -1596,15 +1688,25 @@ define half @v_fmaximum3_f16_fneg_fabs_all(half %a, half %b, half %c) {
 }
 
 define half @v_fmaximum3_f16_fneg0(half %a, half %b, half %c) {
-; GFX12-LABEL: v_fmaximum3_f16_fneg0:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_maximum3_f16 v0, -v0, v1, v2
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fmaximum3_f16_fneg0:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_maximum3_f16 v0.l, -v0.l, v1.l, v2.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fmaximum3_f16_fneg0:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_maximum3_f16 v0, -v0, v1, v2
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fmaximum3_f16_fneg0:
 ; GFX942:       ; %bb.0:
@@ -1633,15 +1735,25 @@ define half @v_fmaximum3_f16_fneg0(half %a, half %b, half %c) {
 }
 
 define half @v_fmaximum3_f16_fneg1(half %a, half %b, half %c) {
-; GFX12-LABEL: v_fmaximum3_f16_fneg1:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_maximum3_f16 v0, v0, -v1, v2
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fmaximum3_f16_fneg1:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_maximum3_f16 v0.l, v0.l, -v1.l, v2.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fmaximum3_f16_fneg1:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_maximum3_f16 v0, v0, -v1, v2
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fmaximum3_f16_fneg1:
 ; GFX942:       ; %bb.0:
@@ -1670,15 +1782,25 @@ define half @v_fmaximum3_f16_fneg1(half %a, half %b, half %c) {
 }
 
 define half @v_fmaximum3_f16_fneg2(half %a, half %b, half %c) {
-; GFX12-LABEL: v_fmaximum3_f16_fneg2:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_maximum3_f16 v0, v0, v1, -v2
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fmaximum3_f16_fneg2:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_maximum3_f16 v0.l, v0.l, v1.l, -v2.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fmaximum3_f16_fneg2:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_maximum3_f16 v0, v0, v1, -v2
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fmaximum3_f16_fneg2:
 ; GFX942:       ; %bb.0:
@@ -1707,15 +1829,25 @@ define half @v_fmaximum3_f16_fneg2(half %a, half %b, half %c) {
 }
 
 define half @v_fmaximum3_f16_const0(half %b, half %c) {
-; GFX12-LABEL: v_fmaximum3_f16_const0:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_maximum3_f16 v0, v0, 0x4800, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fmaximum3_f16_const0:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_maximum3_f16 v0.l, v0.l, 0x4800, v1.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fmaximum3_f16_const0:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_maximum3_f16 v0, v0, 0x4800, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fmaximum3_f16_const0:
 ; GFX942:       ; %bb.0:
@@ -1743,15 +1875,25 @@ define half @v_fmaximum3_f16_const0(half %b, half %c) {
 }
 
 define half @v_fmaximum3_f16__const2(half %a, half %b) {
-; GFX12-LABEL: v_fmaximum3_f16__const2:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_maximum3_f16 v0, v0, v1, 0x4800
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fmaximum3_f16__const2:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_maximum3_f16 v0.l, v0.l, v1.l, 0x4800
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fmaximum3_f16__const2:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_maximum3_f16 v0, v0, v1, 0x4800
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fmaximum3_f16__const2:
 ; GFX942:       ; %bb.0:
@@ -1779,15 +1921,25 @@ define half @v_fmaximum3_f16__const2(half %a, half %b) {
 }
 
 define half @v_fmaximum3_f16_inlineimm0(half %b, half %c) {
-; GFX12-LABEL: v_fmaximum3_f16_inlineimm0:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_maximum3_f16 v0, v0, 4.0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fmaximum3_f16_inlineimm0:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_maximum3_f16 v0.l, v0.l, 4.0, v1.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fmaximum3_f16_inlineimm0:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_maximum3_f16 v0, v0, 4.0, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fmaximum3_f16_inlineimm0:
 ; GFX942:       ; %bb.0:
@@ -1814,15 +1966,25 @@ define half @v_fmaximum3_f16_inlineimm0(half %b, half %c) {
 }
 
 define half @v_fmaximum3_f16__inlineimm(half %a, half %b) {
-; GFX12-LABEL: v_fmaximum3_f16__inlineimm:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_maximum3_f16 v0, v0, v1, 4.0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fmaximum3_f16__inlineimm:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_maximum3_f16 v0.l, v0.l, v1.l, 4.0
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fmaximum3_f16__inlineimm:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_maximum3_f16 v0, v0, v1, 4.0
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fmaximum3_f16__inlineimm:
 ; GFX942:       ; %bb.0:
@@ -1849,17 +2011,29 @@ define half @v_fmaximum3_f16__inlineimm(half %a, half %b) {
 }
 
 define half @v_fmaximum3_f16_const1_const2(half %a) {
-; GFX12-LABEL: v_fmaximum3_f16_const1_const2:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_movk_i32 s0, 0x4800
-; GFX12-NEXT:    s_wait_alu 0xfffe
-; GFX12-NEXT:    v_maximum3_f16 v0, v0, s0, 0x4c00
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fmaximum3_f16_const1_const2:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, 0x4c00
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_maximum3_f16 v0.l, v0.l, 0x4800, v0.h
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fmaximum3_f16_const1_const2:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_movk_i32 s0, 0x4800
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT:    v_maximum3_f16 v0, v0, s0, 0x4c00
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fmaximum3_f16_const1_const2:
 ; GFX942:       ; %bb.0:
@@ -3700,18 +3874,31 @@ define amdgpu_ps <2 x i32> @s_no_fmaximum3_f32__multi_use(float inreg %a, float
 }
 
 define <2 x half> @v_no_fmaximum3_f16__multi_use(half %a, half %b, half %c) {
-; GFX12-LABEL: v_no_fmaximum3_f16__multi_use:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_maximum_f16 v0, v0, v1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_maximum_f16 v1, v0, v2
-; GFX12-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_no_fmaximum3_f16__multi_use:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_maximum_f16 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_maximum_f16 v0.h, v0.l, v2.l
+; GFX12-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_no_fmaximum3_f16__multi_use:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_maximum_f16 v0, v0, v1
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_maximum_f16 v1, v0, v2
+; GFX12-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_no_fmaximum3_f16__multi_use:
 ; GFX942:       ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/fmin3.ll b/llvm/test/CodeGen/AMDGPU/fmin3.ll
index 269fd52df5c49..d554707027bb1 100644
--- a/llvm/test/CodeGen/AMDGPU/fmin3.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmin3.ll
@@ -2,8 +2,10 @@
 ; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=SI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-FAKE16 %s
 
 define amdgpu_kernel void @test_fmin3_olt_0_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) #0 {
 ; SI-LABEL: test_fmin3_olt_0_f32:
@@ -423,65 +425,125 @@ define amdgpu_kernel void @test_fmin3_olt_0_f16(ptr addrspace(1) %out, ptr addrs
 ; GFX9-NEXT:    buffer_store_short v0, off, s[0:3], 0
 ; GFX9-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: test_fmin3_olt_0_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
-; GFX11-NEXT:    s_mov_b32 s10, -1
-; GFX11-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s14, s10
-; GFX11-NEXT:    s_mov_b32 s15, s11
-; GFX11-NEXT:    s_mov_b32 s18, s10
-; GFX11-NEXT:    s_mov_b32 s19, s11
-; GFX11-NEXT:    s_mov_b32 s22, s10
-; GFX11-NEXT:    s_mov_b32 s23, s11
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s12, s2
-; GFX11-NEXT:    s_mov_b32 s13, s3
-; GFX11-NEXT:    s_mov_b32 s16, s4
-; GFX11-NEXT:    s_mov_b32 s17, s5
-; GFX11-NEXT:    s_mov_b32 s20, s6
-; GFX11-NEXT:    s_mov_b32 s21, s7
-; GFX11-NEXT:    buffer_load_u16 v0, off, s[12:15], 0 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    buffer_load_u16 v1, off, s[16:19], 0 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    buffer_load_u16 v2, off, s[20:23], 0 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s8, s0
-; GFX11-NEXT:    s_mov_b32 s9, s1
-; GFX11-NEXT:    v_min3_f16 v0, v0, v1, v2
-; GFX11-NEXT:    buffer_store_b16 v0, off, s[8:11], 0
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: test_fmin3_olt_0_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX11-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX11-TRUE16-NEXT:    s_mov_b32 s18, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s19, s11
+; GFX11-TRUE16-NEXT:    s_mov_b32 s22, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s23, s11
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s16, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s17, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s20, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s21, s7
+; GFX11-TRUE16-NEXT:    buffer_load_u16 v0, off, s[12:15], 0 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    buffer_load_u16 v1, off, s[16:19], 0 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    buffer_load_u16 v2, off, s[20:23], 0 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX11-TRUE16-NEXT:    v_min3_f16 v0.l, v0.l, v1.l, v2.l
+; GFX11-TRUE16-NEXT:    buffer_store_b16 v0, off, s[8:11], 0
+; GFX11-TRUE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: test_fmin3_olt_0_f16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_mov_b32 s18, s10
-; GFX12-NEXT:    s_mov_b32 s19, s11
-; GFX12-NEXT:    s_mov_b32 s22, s10
-; GFX12-NEXT:    s_mov_b32 s23, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    s_mov_b32 s16, s4
-; GFX12-NEXT:    s_mov_b32 s17, s5
-; GFX12-NEXT:    s_mov_b32 s20, s6
-; GFX12-NEXT:    s_mov_b32 s21, s7
-; GFX12-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    buffer_load_u16 v1, off, s[16:19], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    buffer_load_u16 v2, off, s[20:23], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    v_min3_num_f16 v0, v0, v1, v2
-; GFX12-NEXT:    buffer_store_b16 v0, off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX11-FAKE16-LABEL: test_fmin3_olt_0_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX11-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX11-FAKE16-NEXT:    s_mov_b32 s18, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s19, s11
+; GFX11-FAKE16-NEXT:    s_mov_b32 s22, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s23, s11
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s16, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s17, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s20, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s21, s7
+; GFX11-FAKE16-NEXT:    buffer_load_u16 v0, off, s[12:15], 0 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    buffer_load_u16 v1, off, s[16:19], 0 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    buffer_load_u16 v2, off, s[20:23], 0 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX11-FAKE16-NEXT:    v_min3_f16 v0, v0, v1, v2
+; GFX11-FAKE16-NEXT:    buffer_store_b16 v0, off, s[8:11], 0
+; GFX11-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-TRUE16-LABEL: test_fmin3_olt_0_f16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s18, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s19, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s22, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s23, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s16, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s17, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s20, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s21, s7
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v1, off, s[16:19], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v2, off, s[20:23], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    v_min3_num_f16 v0.l, v0.l, v1.l, v2.l
+; GFX12-TRUE16-NEXT:    buffer_store_b16 v0, off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: test_fmin3_olt_0_f16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s18, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s19, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s22, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s23, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s16, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s17, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s20, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s21, s7
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v1, off, s[16:19], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v2, off, s[20:23], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    v_min3_num_f16 v0, v0, v1, v2
+; GFX12-FAKE16-NEXT:    buffer_store_b16 v0, off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
   %a = load volatile half, ptr addrspace(1) %aptr, align 2
   %b = load volatile half, ptr addrspace(1) %bptr, align 2
   %c = load volatile half, ptr addrspace(1) %cptr, align 2
@@ -591,65 +653,125 @@ define amdgpu_kernel void @test_fmin3_olt_1_f16(ptr addrspace(1) %out, ptr addrs
 ; GFX9-NEXT:    buffer_store_short v0, off, s[0:3], 0
 ; GFX9-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: test_fmin3_olt_1_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
-; GFX11-NEXT:    s_mov_b32 s10, -1
-; GFX11-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s14, s10
-; GFX11-NEXT:    s_mov_b32 s15, s11
-; GFX11-NEXT:    s_mov_b32 s18, s10
-; GFX11-NEXT:    s_mov_b32 s19, s11
-; GFX11-NEXT:    s_mov_b32 s22, s10
-; GFX11-NEXT:    s_mov_b32 s23, s11
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s12, s2
-; GFX11-NEXT:    s_mov_b32 s13, s3
-; GFX11-NEXT:    s_mov_b32 s16, s4
-; GFX11-NEXT:    s_mov_b32 s17, s5
-; GFX11-NEXT:    s_mov_b32 s20, s6
-; GFX11-NEXT:    s_mov_b32 s21, s7
-; GFX11-NEXT:    buffer_load_u16 v0, off, s[12:15], 0 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    buffer_load_u16 v1, off, s[16:19], 0 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    buffer_load_u16 v2, off, s[20:23], 0 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s8, s0
-; GFX11-NEXT:    s_mov_b32 s9, s1
-; GFX11-NEXT:    v_min3_f16 v0, v2, v0, v1
-; GFX11-NEXT:    buffer_store_b16 v0, off, s[8:11], 0
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: test_fmin3_olt_1_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX11-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX11-TRUE16-NEXT:    s_mov_b32 s18, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s19, s11
+; GFX11-TRUE16-NEXT:    s_mov_b32 s22, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s23, s11
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s16, s4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s17, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s20, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s21, s7
+; GFX11-TRUE16-NEXT:    buffer_load_u16 v1, off, s[12:15], 0 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    buffer_load_u16 v2, off, s[16:19], 0 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    buffer_load_u16 v0, off, s[20:23], 0 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX11-TRUE16-NEXT:    v_min3_f16 v0.l, v0.l, v1.l, v2.l
+; GFX11-TRUE16-NEXT:    buffer_store_b16 v0, off, s[8:11], 0
+; GFX11-TRUE16-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: test_fmin3_olt_1_f16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
-; GFX12-NEXT:    s_mov_b32 s10, -1
-; GFX12-NEXT:    s_mov_b32 s11, 0x31016000
-; GFX12-NEXT:    s_mov_b32 s14, s10
-; GFX12-NEXT:    s_mov_b32 s15, s11
-; GFX12-NEXT:    s_mov_b32 s18, s10
-; GFX12-NEXT:    s_mov_b32 s19, s11
-; GFX12-NEXT:    s_mov_b32 s22, s10
-; GFX12-NEXT:    s_mov_b32 s23, s11
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s12, s2
-; GFX12-NEXT:    s_mov_b32 s13, s3
-; GFX12-NEXT:    s_mov_b32 s16, s4
-; GFX12-NEXT:    s_mov_b32 s17, s5
-; GFX12-NEXT:    s_mov_b32 s20, s6
-; GFX12-NEXT:    s_mov_b32 s21, s7
-; GFX12-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    buffer_load_u16 v1, off, s[16:19], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    buffer_load_u16 v2, off, s[20:23], null scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s8, s0
-; GFX12-NEXT:    s_mov_b32 s9, s1
-; GFX12-NEXT:    v_min3_num_f16 v0, v2, v0, v1
-; GFX12-NEXT:    buffer_store_b16 v0, off, s[8:11], null
-; GFX12-NEXT:    s_endpgm
+; GFX11-FAKE16-LABEL: test_fmin3_olt_1_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX11-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX11-FAKE16-NEXT:    s_mov_b32 s18, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s19, s11
+; GFX11-FAKE16-NEXT:    s_mov_b32 s22, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s23, s11
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s16, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s17, s5
+; GFX11-FAKE16-NEXT:    s_mov_b32 s20, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s21, s7
+; GFX11-FAKE16-NEXT:    buffer_load_u16 v0, off, s[12:15], 0 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    buffer_load_u16 v1, off, s[16:19], 0 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    buffer_load_u16 v2, off, s[20:23], 0 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX11-FAKE16-NEXT:    v_min3_f16 v0, v2, v0, v1
+; GFX11-FAKE16-NEXT:    buffer_store_b16 v0, off, s[8:11], 0
+; GFX11-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-TRUE16-LABEL: test_fmin3_olt_1_f16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-TRUE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s18, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s19, s11
+; GFX12-TRUE16-NEXT:    s_mov_b32 s22, s10
+; GFX12-TRUE16-NEXT:    s_mov_b32 s23, s11
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-TRUE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-TRUE16-NEXT:    s_mov_b32 s16, s4
+; GFX12-TRUE16-NEXT:    s_mov_b32 s17, s5
+; GFX12-TRUE16-NEXT:    s_mov_b32 s20, s6
+; GFX12-TRUE16-NEXT:    s_mov_b32 s21, s7
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v1, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v2, off, s[16:19], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    buffer_load_u16 v0, off, s[20:23], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-TRUE16-NEXT:    v_min3_num_f16 v0.l, v0.l, v1.l, v2.l
+; GFX12-TRUE16-NEXT:    buffer_store_b16 v0, off, s[8:11], null
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: test_fmin3_olt_1_f16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_mov_b32 s10, -1
+; GFX12-FAKE16-NEXT:    s_mov_b32 s11, 0x31016000
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s15, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s18, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s19, s11
+; GFX12-FAKE16-NEXT:    s_mov_b32 s22, s10
+; GFX12-FAKE16-NEXT:    s_mov_b32 s23, s11
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, s2
+; GFX12-FAKE16-NEXT:    s_mov_b32 s13, s3
+; GFX12-FAKE16-NEXT:    s_mov_b32 s16, s4
+; GFX12-FAKE16-NEXT:    s_mov_b32 s17, s5
+; GFX12-FAKE16-NEXT:    s_mov_b32 s20, s6
+; GFX12-FAKE16-NEXT:    s_mov_b32 s21, s7
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v1, off, s[16:19], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    buffer_load_u16 v2, off, s[20:23], null scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s8, s0
+; GFX12-FAKE16-NEXT:    s_mov_b32 s9, s1
+; GFX12-FAKE16-NEXT:    v_min3_num_f16 v0, v2, v0, v1
+; GFX12-FAKE16-NEXT:    buffer_store_b16 v0, off, s[8:11], null
+; GFX12-FAKE16-NEXT:    s_endpgm
   %a = load volatile half, ptr addrspace(1) %aptr, align 2
   %b = load volatile half, ptr addrspace(1) %bptr, align 2
   %c = load volatile half, ptr addrspace(1) %cptr, align 2
diff --git a/llvm/test/CodeGen/AMDGPU/fminimum.ll b/llvm/test/CodeGen/AMDGPU/fminimum.ll
index ba536aade8c49..e1d35b52defee 100644
--- a/llvm/test/CodeGen/AMDGPU/fminimum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fminimum.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX12-SDAG %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX12-GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
 
 define amdgpu_ps float @test_fminimum_f32_vv(float %a, float %b) {
 ; GCN-LABEL: test_fminimum_f32_vv:
@@ -110,10 +112,25 @@ define amdgpu_ps <16 x float> @test_fminimum_v16f32(<16 x float> %a, <16 x float
 }
 
 define amdgpu_ps half @test_fminimum_f16_vv(half %a, half %b) {
-; GCN-LABEL: test_fminimum_f16_vv:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    v_minimum_f16 v0, v0, v1
-; GCN-NEXT:    ; return to shader part epilog
+; GFX12-SDAG-TRUE16-LABEL: test_fminimum_f16_vv:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    v_minimum_f16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-SDAG-FAKE16-LABEL: test_fminimum_f16_vv:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    v_minimum_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-TRUE16-LABEL: test_fminimum_f16_vv:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-FAKE16-LABEL: test_fminimum_f16_vv:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    ; return to shader part epilog
   %val = call half @llvm.minimum.f16(half %a, half %b)
   ret half %val
 }
@@ -154,11 +171,17 @@ define amdgpu_ps <3 x half> @test_fminimum_v3f16_vv(<3 x half> %a, <3 x half> %b
 ; GFX12-SDAG-NEXT:    v_pk_minimum_f16 v1, v1, v3
 ; GFX12-SDAG-NEXT:    ; return to shader part epilog
 ;
-; GFX12-GISEL-LABEL: test_fminimum_v3f16_vv:
-; GFX12-GISEL:       ; %bb.0:
-; GFX12-GISEL-NEXT:    v_pk_minimum_f16 v0, v0, v2
-; GFX12-GISEL-NEXT:    v_minimum_f16 v1, v1, v3
-; GFX12-GISEL-NEXT:    ; return to shader part epilog
+; GFX12-GISEL-TRUE16-LABEL: test_fminimum_v3f16_vv:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v1.l, v1.l, v3.l
+; GFX12-GISEL-TRUE16-NEXT:    v_pk_minimum_f16 v0, v0, v2
+; GFX12-GISEL-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-FAKE16-LABEL: test_fminimum_v3f16_vv:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    v_pk_minimum_f16 v0, v0, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v1, v1, v3
+; GFX12-GISEL-FAKE16-NEXT:    ; return to shader part epilog
   %val = call <3 x half> @llvm.minimum.v3f16(<3 x half> %a, <3 x half> %b)
   ret <3 x half> %val
 }
@@ -282,20 +305,65 @@ define amdgpu_kernel void @fminimumi_f32_move_to_valu(ptr addrspace(1) %out, ptr
 }
 
 define amdgpu_kernel void @fminimum_f16_move_to_valu(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {
-; GCN-LABEL: fminimum_f16_move_to_valu:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_clause 0x1
-; GCN-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GCN-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GCN-NEXT:    v_mov_b32_e32 v0, 0
-; GCN-NEXT:    s_wait_kmcnt 0x0
-; GCN-NEXT:    global_load_u16 v1, v0, s[2:3] scope:SCOPE_SYS
-; GCN-NEXT:    s_wait_loadcnt 0x0
-; GCN-NEXT:    global_load_u16 v2, v0, s[4:5] scope:SCOPE_SYS
-; GCN-NEXT:    s_wait_loadcnt 0x0
-; GCN-NEXT:    v_minimum_f16 v1, v1, v2
-; GCN-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GCN-NEXT:    s_endpgm
+; GFX12-SDAG-TRUE16-LABEL: fminimum_f16_move_to_valu:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_clause 0x1
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3] scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_hi_b16 v0, v1, s[4:5] scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_minimum_f16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: fminimum_f16_move_to_valu:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_clause 0x1
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3] scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u16 v2, v0, s[4:5] scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_minimum_f16 v1, v1, v2
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-GISEL-TRUE16-LABEL: fminimum_f16_move_to_valu:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    s_clause 0x1
+; GFX12-GISEL-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-GISEL-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3] scope:SCOPE_SYS
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    global_load_d16_hi_b16 v0, v1, s[4:5] scope:SCOPE_SYS
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX12-GISEL-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-GISEL-FAKE16-LABEL: fminimum_f16_move_to_valu:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    s_clause 0x1
+; GFX12-GISEL-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-GISEL-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX12-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3] scope:SCOPE_SYS
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    global_load_u16 v2, v0, s[4:5] scope:SCOPE_SYS
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v1, v1, v2
+; GFX12-GISEL-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX12-GISEL-FAKE16-NEXT:    s_endpgm
   %a = load volatile half, ptr addrspace(1) %aptr, align 4
   %b = load volatile half, ptr addrspace(1) %bptr, align 4
   %v = call half @llvm.minimum.f16(half %a, half %b)
diff --git a/llvm/test/CodeGen/AMDGPU/fminimum3.ll b/llvm/test/CodeGen/AMDGPU/fminimum3.ll
index 34d7e5acb7896..96e9aa375f5ee 100644
--- a/llvm/test/CodeGen/AMDGPU/fminimum3.ll
+++ b/llvm/test/CodeGen/AMDGPU/fminimum3.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX942 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX9,GFX950 %s
 
@@ -1242,15 +1243,25 @@ define <3 x float> @v_fminimum3_v3f32__inlineimm2(<3 x float> %a, <3 x float> %b
 
 
 define half @v_fminimum3_f16(half %a, half %b, half %c) {
-; GFX12-LABEL: v_fminimum3_f16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_minimum3_f16 v0, v0, v1, v2
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fminimum3_f16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_minimum3_f16 v0.l, v0.l, v1.l, v2.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fminimum3_f16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_minimum3_f16 v0, v0, v1, v2
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fminimum3_f16:
 ; GFX942:       ; %bb.0:
@@ -1277,15 +1288,25 @@ define half @v_fminimum3_f16(half %a, half %b, half %c) {
 }
 
 define half @v_fminimum3_f16_commute(half %a, half %b, half %c) {
-; GFX12-LABEL: v_fminimum3_f16_commute:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_minimum3_f16 v0, v2, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fminimum3_f16_commute:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_minimum3_f16 v0.l, v2.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fminimum3_f16_commute:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_minimum3_f16 v0, v2, v0, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fminimum3_f16_commute:
 ; GFX942:       ; %bb.0:
@@ -1312,16 +1333,27 @@ define half @v_fminimum3_f16_commute(half %a, half %b, half %c) {
 }
 
 define amdgpu_ps i32 @s_fminimum3_f16(half inreg %a, half inreg %b, half inreg %c) {
-; GFX12-LABEL: s_fminimum3_f16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    v_mov_b32_e32 v0, s2
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_minimum3_f16 v0, s0, s1, v0
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX12-NEXT:    s_wait_alu 0xf1ff
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX12-TRUE16-LABEL: s_fminimum3_f16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.l, s2
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_minimum3_f16 v0.l, s0, s1, v0.l
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: s_fminimum3_f16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v0, s2
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_minimum3_f16 v0, s0, s1, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 ;
 ; GFX942-LABEL: s_fminimum3_f16:
 ; GFX942:       ; %bb.0:
@@ -1359,15 +1391,25 @@ define amdgpu_ps i32 @s_fminimum3_f16(half inreg %a, half inreg %b, half inreg %
 }
 
 define half @v_fminimum3_f16_fabs0(half %a, half %b, half %c) {
-; GFX12-LABEL: v_fminimum3_f16_fabs0:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_minimum3_f16 v0, |v0|, v1, v2
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fminimum3_f16_fabs0:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_minimum3_f16 v0.l, |v0.l|, v1.l, v2.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fminimum3_f16_fabs0:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_minimum3_f16 v0, |v0|, v1, v2
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fminimum3_f16_fabs0:
 ; GFX942:       ; %bb.0:
@@ -1396,15 +1438,25 @@ define half @v_fminimum3_f16_fabs0(half %a, half %b, half %c) {
 }
 
 define half @v_fminimum3_f16_fabs1(half %a, half %b, half %c) {
-; GFX12-LABEL: v_fminimum3_f16_fabs1:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_minimum3_f16 v0, v0, |v1|, v2
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fminimum3_f16_fabs1:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_minimum3_f16 v0.l, v0.l, |v1.l|, v2.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fminimum3_f16_fabs1:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_minimum3_f16 v0, v0, |v1|, v2
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fminimum3_f16_fabs1:
 ; GFX942:       ; %bb.0:
@@ -1433,15 +1485,25 @@ define half @v_fminimum3_f16_fabs1(half %a, half %b, half %c) {
 }
 
 define half @v_fminimum3_f16_fabs2(half %a, half %b, half %c) {
-; GFX12-LABEL: v_fminimum3_f16_fabs2:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_minimum3_f16 v0, v0, v1, |v2|
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fminimum3_f16_fabs2:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_minimum3_f16 v0.l, v0.l, v1.l, |v2.l|
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fminimum3_f16_fabs2:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_minimum3_f16 v0, v0, v1, |v2|
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fminimum3_f16_fabs2:
 ; GFX942:       ; %bb.0:
@@ -1470,15 +1532,25 @@ define half @v_fminimum3_f16_fabs2(half %a, half %b, half %c) {
 }
 
 define half @v_fminimum3_f16_fabs_all(half %a, half %b, half %c) {
-; GFX12-LABEL: v_fminimum3_f16_fabs_all:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_minimum3_f16 v0, |v0|, |v1|, |v2|
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fminimum3_f16_fabs_all:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_minimum3_f16 v0.l, |v0.l|, |v1.l|, |v2.l|
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fminimum3_f16_fabs_all:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_minimum3_f16 v0, |v0|, |v1|, |v2|
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fminimum3_f16_fabs_all:
 ; GFX942:       ; %bb.0:
@@ -1511,15 +1583,25 @@ define half @v_fminimum3_f16_fabs_all(half %a, half %b, half %c) {
 }
 
 define half @v_fminimum3_f16_fneg_all(half %a, half %b, half %c) {
-; GFX12-LABEL: v_fminimum3_f16_fneg_all:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_minimum3_f16 v0, -v0, -v1, -v2
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fminimum3_f16_fneg_all:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_minimum3_f16 v0.l, -v0.l, -v1.l, -v2.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fminimum3_f16_fneg_all:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_minimum3_f16 v0, -v0, -v1, -v2
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fminimum3_f16_fneg_all:
 ; GFX942:       ; %bb.0:
@@ -1552,15 +1634,25 @@ define half @v_fminimum3_f16_fneg_all(half %a, half %b, half %c) {
 }
 
 define half @v_fminimum3_f16_fneg_fabs_all(half %a, half %b, half %c) {
-; GFX12-LABEL: v_fminimum3_f16_fneg_fabs_all:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_minimum3_f16 v0, -|v0|, -|v1|, -|v2|
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fminimum3_f16_fneg_fabs_all:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_minimum3_f16 v0.l, -|v0.l|, -|v1.l|, -|v2.l|
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fminimum3_f16_fneg_fabs_all:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_minimum3_f16 v0, -|v0|, -|v1|, -|v2|
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fminimum3_f16_fneg_fabs_all:
 ; GFX942:       ; %bb.0:
@@ -1596,15 +1688,25 @@ define half @v_fminimum3_f16_fneg_fabs_all(half %a, half %b, half %c) {
 }
 
 define half @v_fminimum3_f16_fneg0(half %a, half %b, half %c) {
-; GFX12-LABEL: v_fminimum3_f16_fneg0:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_minimum3_f16 v0, -v0, v1, v2
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fminimum3_f16_fneg0:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_minimum3_f16 v0.l, -v0.l, v1.l, v2.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fminimum3_f16_fneg0:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_minimum3_f16 v0, -v0, v1, v2
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fminimum3_f16_fneg0:
 ; GFX942:       ; %bb.0:
@@ -1633,15 +1735,25 @@ define half @v_fminimum3_f16_fneg0(half %a, half %b, half %c) {
 }
 
 define half @v_fminimum3_f16_fneg1(half %a, half %b, half %c) {
-; GFX12-LABEL: v_fminimum3_f16_fneg1:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_minimum3_f16 v0, v0, -v1, v2
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fminimum3_f16_fneg1:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_minimum3_f16 v0.l, v0.l, -v1.l, v2.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fminimum3_f16_fneg1:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_minimum3_f16 v0, v0, -v1, v2
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fminimum3_f16_fneg1:
 ; GFX942:       ; %bb.0:
@@ -1670,15 +1782,25 @@ define half @v_fminimum3_f16_fneg1(half %a, half %b, half %c) {
 }
 
 define half @v_fminimum3_f16_fneg2(half %a, half %b, half %c) {
-; GFX12-LABEL: v_fminimum3_f16_fneg2:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_minimum3_f16 v0, v0, v1, -v2
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fminimum3_f16_fneg2:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_minimum3_f16 v0.l, v0.l, v1.l, -v2.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fminimum3_f16_fneg2:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_minimum3_f16 v0, v0, v1, -v2
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fminimum3_f16_fneg2:
 ; GFX942:       ; %bb.0:
@@ -1707,15 +1829,25 @@ define half @v_fminimum3_f16_fneg2(half %a, half %b, half %c) {
 }
 
 define half @v_fminimum3_f16_const0(half %b, half %c) {
-; GFX12-LABEL: v_fminimum3_f16_const0:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_minimum3_f16 v0, v0, 0x4800, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fminimum3_f16_const0:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_minimum3_f16 v0.l, v0.l, 0x4800, v1.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fminimum3_f16_const0:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_minimum3_f16 v0, v0, 0x4800, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fminimum3_f16_const0:
 ; GFX942:       ; %bb.0:
@@ -1743,15 +1875,25 @@ define half @v_fminimum3_f16_const0(half %b, half %c) {
 }
 
 define half @v_fminimum3_f16__const2(half %a, half %b) {
-; GFX12-LABEL: v_fminimum3_f16__const2:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_minimum3_f16 v0, v0, v1, 0x4800
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fminimum3_f16__const2:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_minimum3_f16 v0.l, v0.l, v1.l, 0x4800
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fminimum3_f16__const2:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_minimum3_f16 v0, v0, v1, 0x4800
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fminimum3_f16__const2:
 ; GFX942:       ; %bb.0:
@@ -1779,15 +1921,25 @@ define half @v_fminimum3_f16__const2(half %a, half %b) {
 }
 
 define half @v_fminimum3_f16_inlineimm0(half %b, half %c) {
-; GFX12-LABEL: v_fminimum3_f16_inlineimm0:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_minimum3_f16 v0, v0, 4.0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fminimum3_f16_inlineimm0:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_minimum3_f16 v0.l, v0.l, 4.0, v1.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fminimum3_f16_inlineimm0:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_minimum3_f16 v0, v0, 4.0, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fminimum3_f16_inlineimm0:
 ; GFX942:       ; %bb.0:
@@ -1814,15 +1966,25 @@ define half @v_fminimum3_f16_inlineimm0(half %b, half %c) {
 }
 
 define half @v_fminimum3_f16__inlineimm(half %a, half %b) {
-; GFX12-LABEL: v_fminimum3_f16__inlineimm:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_minimum3_f16 v0, v0, v1, 4.0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fminimum3_f16__inlineimm:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_minimum3_f16 v0.l, v0.l, v1.l, 4.0
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fminimum3_f16__inlineimm:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_minimum3_f16 v0, v0, v1, 4.0
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fminimum3_f16__inlineimm:
 ; GFX942:       ; %bb.0:
@@ -1849,17 +2011,29 @@ define half @v_fminimum3_f16__inlineimm(half %a, half %b) {
 }
 
 define half @v_fminimum3_f16_const1_const2(half %a) {
-; GFX12-LABEL: v_fminimum3_f16_const1_const2:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_movk_i32 s0, 0x4800
-; GFX12-NEXT:    s_wait_alu 0xfffe
-; GFX12-NEXT:    v_minimum3_f16 v0, v0, s0, 0x4c00
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_fminimum3_f16_const1_const2:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, 0x4c00
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_minimum3_f16 v0.l, v0.l, 0x4800, v0.h
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_fminimum3_f16_const1_const2:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_movk_i32 s0, 0x4800
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT:    v_minimum3_f16 v0, v0, s0, 0x4c00
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_fminimum3_f16_const1_const2:
 ; GFX942:       ; %bb.0:
@@ -3700,18 +3874,31 @@ define amdgpu_ps <2 x i32> @s_no_fminimum3_f32__multi_use(float inreg %a, float
 }
 
 define <2 x half> @v_no_fminimum3_f16__multi_use(half %a, half %b, half %c) {
-; GFX12-LABEL: v_no_fminimum3_f16__multi_use:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_minimum_f16 v0, v0, v1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_minimum_f16 v1, v0, v2
-; GFX12-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_no_fminimum3_f16__multi_use:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_minimum_f16 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_minimum_f16 v0.h, v0.l, v2.l
+; GFX12-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_no_fminimum3_f16__multi_use:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_minimum_f16 v0, v0, v1
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_minimum_f16 v1, v0, v2
+; GFX12-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX942-LABEL: v_no_fminimum3_f16__multi_use:
 ; GFX942:       ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll b/llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
index fb2448fb80744..7c0d3692242a4 100644
--- a/llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
@@ -3,8 +3,10 @@
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -denormal-fp-math=preserve-sign -denormal-fp-math-f32=preserve-sign  -verify-machineinstrs < %s | FileCheck -check-prefixes=VI,VI-FLUSH %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -denormal-fp-math-f32=preserve-sign  -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10,GFX10-DENORM %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -denormal-fp-math=preserve-sign -denormal-fp-math-f32=preserve-sign  -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10,GFX10-FLUSH %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -denormal-fp-math-f32=preserve-sign  -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-DENORM %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -denormal-fp-math=preserve-sign -denormal-fp-math-f32=preserve-sign  -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-FLUSH %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 -denormal-fp-math-f32=preserve-sign  -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16,GFX11-DENORM,GFX11-DENORM-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 -denormal-fp-math-f32=preserve-sign  -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16,GFX11-DENORM,GFX11-DENORM-FAKE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 -denormal-fp-math=preserve-sign -denormal-fp-math-f32=preserve-sign  -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16,GFX11-FLUSH,GFX11-FLUSH-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 -denormal-fp-math=preserve-sign -denormal-fp-math-f32=preserve-sign  -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16,GFX11-FLUSH,GFX11-FLUSH-FAKE16 %s
 
 ; Make sure (fmul (fadd x, x), c) -> (fmul x, (fmul 2.0, c)) doesn't
 ; make add an instruction if the fadd has more than one use.
@@ -443,47 +445,90 @@ define amdgpu_kernel void @multiple_fadd_use_test_f16(ptr addrspace(1) %out, i16
 ; GFX10-FLUSH-NEXT:    global_store_short v1, v0, s[0:1]
 ; GFX10-FLUSH-NEXT:    s_endpgm
 ;
-; GFX11-DENORM-LABEL: multiple_fadd_use_test_f16:
-; GFX11-DENORM:       ; %bb.0:
-; GFX11-DENORM-NEXT:    s_load_b32 s0, s[4:5], 0x8
-; GFX11-DENORM-NEXT:    v_mov_b32_e32 v2, 0
-; GFX11-DENORM-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-DENORM-NEXT:    s_lshr_b32 s1, s0, 16
-; GFX11-DENORM-NEXT:    v_add_f16_e64 v0, s0, -1.0
-; GFX11-DENORM-NEXT:    v_add_f16_e64 v1, s1, -1.0
-; GFX11-DENORM-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-DENORM-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-DENORM-NEXT:    v_cmp_gt_f16_e64 vcc_lo, |v1|, |v0|
-; GFX11-DENORM-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX11-DENORM-NEXT:    v_add_f16_e64 v0, |v0|, |v0|
-; GFX11-DENORM-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-DENORM-NEXT:    v_mul_f16_e32 v1, v0, v0
-; GFX11-DENORM-NEXT:    v_fma_f16 v0, -v1, v0, 1.0
-; GFX11-DENORM-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-DENORM-NEXT:    global_store_b16 v2, v0, s[0:1]
-; GFX11-DENORM-NEXT:    s_endpgm
-;
-; GFX11-FLUSH-LABEL: multiple_fadd_use_test_f16:
-; GFX11-FLUSH:       ; %bb.0:
-; GFX11-FLUSH-NEXT:    s_load_b32 s0, s[4:5], 0x8
-; GFX11-FLUSH-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-FLUSH-NEXT:    s_lshr_b32 s1, s0, 16
-; GFX11-FLUSH-NEXT:    v_add_f16_e64 v0, s0, -1.0
-; GFX11-FLUSH-NEXT:    v_add_f16_e64 v1, s1, -1.0
-; GFX11-FLUSH-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FLUSH-NEXT:    v_cmp_gt_f16_e64 vcc_lo, |v1|, |v0|
-; GFX11-FLUSH-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX11-FLUSH-NEXT:    v_add_f16_e64 v0, |v0|, |v0|
-; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FLUSH-NEXT:    v_mul_f16_e32 v1, v0, v0
-; GFX11-FLUSH-NEXT:    v_mul_f16_e32 v0, v1, v0
-; GFX11-FLUSH-NEXT:    v_mov_b32_e32 v1, 0
-; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FLUSH-NEXT:    v_sub_f16_e32 v0, 1.0, v0
-; GFX11-FLUSH-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-FLUSH-NEXT:    global_store_b16 v1, v0, s[0:1]
-; GFX11-FLUSH-NEXT:    s_endpgm
+; GFX11-DENORM-TRUE16-LABEL: multiple_fadd_use_test_f16:
+; GFX11-DENORM-TRUE16:       ; %bb.0:
+; GFX11-DENORM-TRUE16-NEXT:    s_load_b32 s0, s[4:5], 0x8
+; GFX11-DENORM-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-DENORM-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-DENORM-TRUE16-NEXT:    s_lshr_b32 s1, s0, 16
+; GFX11-DENORM-TRUE16-NEXT:    v_add_f16_e64 v0.h, s0, -1.0
+; GFX11-DENORM-TRUE16-NEXT:    v_add_f16_e64 v0.l, s1, -1.0
+; GFX11-DENORM-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-DENORM-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-DENORM-TRUE16-NEXT:    v_cmp_gt_f16_e64 s2, |v0.l|, |v0.h|
+; GFX11-DENORM-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.h, v0.l, s2
+; GFX11-DENORM-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-DENORM-TRUE16-NEXT:    v_add_f16_e64 v0.l, |v0.l|, |v0.l|
+; GFX11-DENORM-TRUE16-NEXT:    v_mul_f16_e32 v0.h, v0.l, v0.l
+; GFX11-DENORM-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-DENORM-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.h, v0.l, 1.0
+; GFX11-DENORM-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-DENORM-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX11-DENORM-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-DENORM-FAKE16-LABEL: multiple_fadd_use_test_f16:
+; GFX11-DENORM-FAKE16:       ; %bb.0:
+; GFX11-DENORM-FAKE16-NEXT:    s_load_b32 s0, s[4:5], 0x8
+; GFX11-DENORM-FAKE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-DENORM-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-DENORM-FAKE16-NEXT:    s_lshr_b32 s1, s0, 16
+; GFX11-DENORM-FAKE16-NEXT:    v_add_f16_e64 v0, s0, -1.0
+; GFX11-DENORM-FAKE16-NEXT:    v_add_f16_e64 v1, s1, -1.0
+; GFX11-DENORM-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-DENORM-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-DENORM-FAKE16-NEXT:    v_cmp_gt_f16_e64 vcc_lo, |v1|, |v0|
+; GFX11-DENORM-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11-DENORM-FAKE16-NEXT:    v_add_f16_e64 v0, |v0|, |v0|
+; GFX11-DENORM-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-DENORM-FAKE16-NEXT:    v_mul_f16_e32 v1, v0, v0
+; GFX11-DENORM-FAKE16-NEXT:    v_fma_f16 v0, -v1, v0, 1.0
+; GFX11-DENORM-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-DENORM-FAKE16-NEXT:    global_store_b16 v2, v0, s[0:1]
+; GFX11-DENORM-FAKE16-NEXT:    s_endpgm
+;
+; GFX11-FLUSH-TRUE16-LABEL: multiple_fadd_use_test_f16:
+; GFX11-FLUSH-TRUE16:       ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT:    s_load_b32 s0, s[4:5], 0x8
+; GFX11-FLUSH-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-FLUSH-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT:    s_lshr_b32 s1, s0, 16
+; GFX11-FLUSH-TRUE16-NEXT:    v_add_f16_e64 v0.h, s0, -1.0
+; GFX11-FLUSH-TRUE16-NEXT:    v_add_f16_e64 v0.l, s1, -1.0
+; GFX11-FLUSH-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FLUSH-TRUE16-NEXT:    v_cmp_gt_f16_e64 s0, |v0.l|, |v0.h|
+; GFX11-FLUSH-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.h, v0.l, s0
+; GFX11-FLUSH-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-FLUSH-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FLUSH-TRUE16-NEXT:    v_add_f16_e64 v0.l, |v0.l|, |v0.l|
+; GFX11-FLUSH-TRUE16-NEXT:    v_mul_f16_e32 v0.h, v0.l, v0.l
+; GFX11-FLUSH-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FLUSH-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.h, v0.l
+; GFX11-FLUSH-TRUE16-NEXT:    v_sub_f16_e32 v0.l, 1.0, v0.l
+; GFX11-FLUSH-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX11-FLUSH-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FLUSH-FAKE16-LABEL: multiple_fadd_use_test_f16:
+; GFX11-FLUSH-FAKE16:       ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT:    s_load_b32 s0, s[4:5], 0x8
+; GFX11-FLUSH-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT:    s_lshr_b32 s1, s0, 16
+; GFX11-FLUSH-FAKE16-NEXT:    v_add_f16_e64 v0, s0, -1.0
+; GFX11-FLUSH-FAKE16-NEXT:    v_add_f16_e64 v1, s1, -1.0
+; GFX11-FLUSH-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-FLUSH-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FLUSH-FAKE16-NEXT:    v_cmp_gt_f16_e64 vcc_lo, |v1|, |v0|
+; GFX11-FLUSH-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11-FLUSH-FAKE16-NEXT:    v_add_f16_e64 v0, |v0|, |v0|
+; GFX11-FLUSH-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FLUSH-FAKE16-NEXT:    v_mul_f16_e32 v1, v0, v0
+; GFX11-FLUSH-FAKE16-NEXT:    v_mul_f16_e32 v0, v1, v0
+; GFX11-FLUSH-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-FLUSH-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FLUSH-FAKE16-NEXT:    v_sub_f16_e32 v0, 1.0, v0
+; GFX11-FLUSH-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX11-FLUSH-FAKE16-NEXT:    s_endpgm
   %x = bitcast i16 %x.arg to half
   %y = bitcast i16 %y.arg to half
   %z = bitcast i16 %z.arg to half
@@ -582,38 +627,71 @@ define amdgpu_kernel void @multiple_use_fadd_fmac_f16(ptr addrspace(1) %out, i16
 ; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-FLUSH-NEXT:    s_endpgm
 ;
-; GFX11-DENORM-LABEL: multiple_use_fadd_fmac_f16:
-; GFX11-DENORM:       ; %bb.0:
-; GFX11-DENORM-NEXT:    s_clause 0x1
-; GFX11-DENORM-NEXT:    s_load_b32 s2, s[4:5], 0x8
-; GFX11-DENORM-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-DENORM-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-DENORM-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-DENORM-NEXT:    s_lshr_b32 s3, s2, 16
-; GFX11-DENORM-NEXT:    v_add_f16_e64 v1, s2, s2
-; GFX11-DENORM-NEXT:    v_fma_f16 v2, s2, 2.0, s3
-; GFX11-DENORM-NEXT:    global_store_b16 v0, v1, s[0:1] dlc
-; GFX11-DENORM-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-DENORM-NEXT:    global_store_b16 v0, v2, s[0:1] offset:2 dlc
-; GFX11-DENORM-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-DENORM-NEXT:    s_endpgm
-;
-; GFX11-FLUSH-LABEL: multiple_use_fadd_fmac_f16:
-; GFX11-FLUSH:       ; %bb.0:
-; GFX11-FLUSH-NEXT:    s_clause 0x1
-; GFX11-FLUSH-NEXT:    s_load_b32 s2, s[4:5], 0x8
-; GFX11-FLUSH-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-FLUSH-NEXT:    v_mov_b32_e32 v1, 0
-; GFX11-FLUSH-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-FLUSH-NEXT:    v_add_f16_e64 v0, s2, s2
-; GFX11-FLUSH-NEXT:    s_lshr_b32 s2, s2, 16
-; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-FLUSH-NEXT:    v_add_f16_e32 v2, s2, v0
-; GFX11-FLUSH-NEXT:    global_store_b16 v1, v0, s[0:1] dlc
-; GFX11-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-FLUSH-NEXT:    global_store_b16 v1, v2, s[0:1] offset:2 dlc
-; GFX11-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-FLUSH-NEXT:    s_endpgm
+; GFX11-DENORM-TRUE16-LABEL: multiple_use_fadd_fmac_f16:
+; GFX11-DENORM-TRUE16:       ; %bb.0:
+; GFX11-DENORM-TRUE16-NEXT:    s_clause 0x1
+; GFX11-DENORM-TRUE16-NEXT:    s_load_b32 s2, s[4:5], 0x8
+; GFX11-DENORM-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-DENORM-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-DENORM-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-DENORM-TRUE16-NEXT:    s_lshr_b32 s3, s2, 16
+; GFX11-DENORM-TRUE16-NEXT:    v_add_f16_e64 v0.l, s2, s2
+; GFX11-DENORM-TRUE16-NEXT:    v_fma_f16 v0.h, s2, 2.0, s3
+; GFX11-DENORM-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1] dlc
+; GFX11-DENORM-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-DENORM-TRUE16-NEXT:    global_store_d16_hi_b16 v1, v0, s[0:1] offset:2 dlc
+; GFX11-DENORM-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-DENORM-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-DENORM-FAKE16-LABEL: multiple_use_fadd_fmac_f16:
+; GFX11-DENORM-FAKE16:       ; %bb.0:
+; GFX11-DENORM-FAKE16-NEXT:    s_clause 0x1
+; GFX11-DENORM-FAKE16-NEXT:    s_load_b32 s2, s[4:5], 0x8
+; GFX11-DENORM-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-DENORM-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-DENORM-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-DENORM-FAKE16-NEXT:    s_lshr_b32 s3, s2, 16
+; GFX11-DENORM-FAKE16-NEXT:    v_add_f16_e64 v1, s2, s2
+; GFX11-DENORM-FAKE16-NEXT:    v_fma_f16 v2, s2, 2.0, s3
+; GFX11-DENORM-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1] dlc
+; GFX11-DENORM-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-DENORM-FAKE16-NEXT:    global_store_b16 v0, v2, s[0:1] offset:2 dlc
+; GFX11-DENORM-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-DENORM-FAKE16-NEXT:    s_endpgm
+;
+; GFX11-FLUSH-TRUE16-LABEL: multiple_use_fadd_fmac_f16:
+; GFX11-FLUSH-TRUE16:       ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT:    s_clause 0x1
+; GFX11-FLUSH-TRUE16-NEXT:    s_load_b32 s2, s[4:5], 0x8
+; GFX11-FLUSH-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-FLUSH-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-FLUSH-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT:    v_add_f16_e64 v0.l, s2, s2
+; GFX11-FLUSH-TRUE16-NEXT:    s_lshr_b32 s2, s2, 16
+; GFX11-FLUSH-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FLUSH-TRUE16-NEXT:    v_add_f16_e32 v0.h, s2, v0.l
+; GFX11-FLUSH-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1] dlc
+; GFX11-FLUSH-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FLUSH-TRUE16-NEXT:    global_store_d16_hi_b16 v1, v0, s[0:1] offset:2 dlc
+; GFX11-FLUSH-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FLUSH-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FLUSH-FAKE16-LABEL: multiple_use_fadd_fmac_f16:
+; GFX11-FLUSH-FAKE16:       ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FLUSH-FAKE16-NEXT:    s_load_b32 s2, s[4:5], 0x8
+; GFX11-FLUSH-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-FLUSH-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-FLUSH-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT:    v_add_f16_e64 v0, s2, s2
+; GFX11-FLUSH-FAKE16-NEXT:    s_lshr_b32 s2, s2, 16
+; GFX11-FLUSH-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FLUSH-FAKE16-NEXT:    v_add_f16_e32 v2, s2, v0
+; GFX11-FLUSH-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1] dlc
+; GFX11-FLUSH-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FLUSH-FAKE16-NEXT:    global_store_b16 v1, v2, s[0:1] offset:2 dlc
+; GFX11-FLUSH-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FLUSH-FAKE16-NEXT:    s_endpgm
   %x = bitcast i16 %x.arg to half
   %y = bitcast i16 %y.arg to half
   %out.gep.1 = getelementptr half, ptr addrspace(1) %out, i32 1
@@ -705,38 +783,71 @@ define amdgpu_kernel void @multiple_use_fadd_fmad_f16(ptr addrspace(1) %out, i16
 ; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-FLUSH-NEXT:    s_endpgm
 ;
-; GFX11-DENORM-LABEL: multiple_use_fadd_fmad_f16:
-; GFX11-DENORM:       ; %bb.0:
-; GFX11-DENORM-NEXT:    s_clause 0x1
-; GFX11-DENORM-NEXT:    s_load_b32 s2, s[4:5], 0x8
-; GFX11-DENORM-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-DENORM-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-DENORM-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-DENORM-NEXT:    s_lshr_b32 s3, s2, 16
-; GFX11-DENORM-NEXT:    v_add_f16_e64 v1, |s2|, |s2|
-; GFX11-DENORM-NEXT:    v_fma_f16 v2, |s2|, 2.0, s3
-; GFX11-DENORM-NEXT:    global_store_b16 v0, v1, s[0:1] dlc
-; GFX11-DENORM-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-DENORM-NEXT:    global_store_b16 v0, v2, s[0:1] offset:2 dlc
-; GFX11-DENORM-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-DENORM-NEXT:    s_endpgm
-;
-; GFX11-FLUSH-LABEL: multiple_use_fadd_fmad_f16:
-; GFX11-FLUSH:       ; %bb.0:
-; GFX11-FLUSH-NEXT:    s_clause 0x1
-; GFX11-FLUSH-NEXT:    s_load_b32 s2, s[4:5], 0x8
-; GFX11-FLUSH-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-FLUSH-NEXT:    v_mov_b32_e32 v1, 0
-; GFX11-FLUSH-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-FLUSH-NEXT:    v_add_f16_e64 v0, |s2|, |s2|
-; GFX11-FLUSH-NEXT:    s_lshr_b32 s2, s2, 16
-; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-FLUSH-NEXT:    v_add_f16_e32 v2, s2, v0
-; GFX11-FLUSH-NEXT:    global_store_b16 v1, v0, s[0:1] dlc
-; GFX11-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-FLUSH-NEXT:    global_store_b16 v1, v2, s[0:1] offset:2 dlc
-; GFX11-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-FLUSH-NEXT:    s_endpgm
+; GFX11-DENORM-TRUE16-LABEL: multiple_use_fadd_fmad_f16:
+; GFX11-DENORM-TRUE16:       ; %bb.0:
+; GFX11-DENORM-TRUE16-NEXT:    s_clause 0x1
+; GFX11-DENORM-TRUE16-NEXT:    s_load_b32 s2, s[4:5], 0x8
+; GFX11-DENORM-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-DENORM-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-DENORM-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-DENORM-TRUE16-NEXT:    s_lshr_b32 s3, s2, 16
+; GFX11-DENORM-TRUE16-NEXT:    v_add_f16_e64 v0.l, |s2|, |s2|
+; GFX11-DENORM-TRUE16-NEXT:    v_fma_f16 v0.h, |s2|, 2.0, s3
+; GFX11-DENORM-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1] dlc
+; GFX11-DENORM-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-DENORM-TRUE16-NEXT:    global_store_d16_hi_b16 v1, v0, s[0:1] offset:2 dlc
+; GFX11-DENORM-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-DENORM-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-DENORM-FAKE16-LABEL: multiple_use_fadd_fmad_f16:
+; GFX11-DENORM-FAKE16:       ; %bb.0:
+; GFX11-DENORM-FAKE16-NEXT:    s_clause 0x1
+; GFX11-DENORM-FAKE16-NEXT:    s_load_b32 s2, s[4:5], 0x8
+; GFX11-DENORM-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-DENORM-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-DENORM-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-DENORM-FAKE16-NEXT:    s_lshr_b32 s3, s2, 16
+; GFX11-DENORM-FAKE16-NEXT:    v_add_f16_e64 v1, |s2|, |s2|
+; GFX11-DENORM-FAKE16-NEXT:    v_fma_f16 v2, |s2|, 2.0, s3
+; GFX11-DENORM-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1] dlc
+; GFX11-DENORM-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-DENORM-FAKE16-NEXT:    global_store_b16 v0, v2, s[0:1] offset:2 dlc
+; GFX11-DENORM-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-DENORM-FAKE16-NEXT:    s_endpgm
+;
+; GFX11-FLUSH-TRUE16-LABEL: multiple_use_fadd_fmad_f16:
+; GFX11-FLUSH-TRUE16:       ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT:    s_clause 0x1
+; GFX11-FLUSH-TRUE16-NEXT:    s_load_b32 s2, s[4:5], 0x8
+; GFX11-FLUSH-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-FLUSH-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-FLUSH-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT:    v_add_f16_e64 v0.l, |s2|, |s2|
+; GFX11-FLUSH-TRUE16-NEXT:    s_lshr_b32 s2, s2, 16
+; GFX11-FLUSH-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FLUSH-TRUE16-NEXT:    v_add_f16_e32 v0.h, s2, v0.l
+; GFX11-FLUSH-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1] dlc
+; GFX11-FLUSH-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FLUSH-TRUE16-NEXT:    global_store_d16_hi_b16 v1, v0, s[0:1] offset:2 dlc
+; GFX11-FLUSH-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FLUSH-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FLUSH-FAKE16-LABEL: multiple_use_fadd_fmad_f16:
+; GFX11-FLUSH-FAKE16:       ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FLUSH-FAKE16-NEXT:    s_load_b32 s2, s[4:5], 0x8
+; GFX11-FLUSH-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-FLUSH-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-FLUSH-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT:    v_add_f16_e64 v0, |s2|, |s2|
+; GFX11-FLUSH-FAKE16-NEXT:    s_lshr_b32 s2, s2, 16
+; GFX11-FLUSH-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FLUSH-FAKE16-NEXT:    v_add_f16_e32 v2, s2, v0
+; GFX11-FLUSH-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1] dlc
+; GFX11-FLUSH-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FLUSH-FAKE16-NEXT:    global_store_b16 v1, v2, s[0:1] offset:2 dlc
+; GFX11-FLUSH-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FLUSH-FAKE16-NEXT:    s_endpgm
   %x = bitcast i16 %x.arg to half
   %y = bitcast i16 %y.arg to half
   %out.gep.1 = getelementptr half, ptr addrspace(1) %out, i32 1
@@ -836,41 +947,77 @@ define amdgpu_kernel void @multiple_use_fadd_multi_fmad_f16(ptr addrspace(1) %ou
 ; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-FLUSH-NEXT:    s_endpgm
 ;
-; GFX11-DENORM-LABEL: multiple_use_fadd_multi_fmad_f16:
-; GFX11-DENORM:       ; %bb.0:
-; GFX11-DENORM-NEXT:    s_clause 0x2
-; GFX11-DENORM-NEXT:    s_load_b64 s[0:1], s[4:5], 0x8
-; GFX11-DENORM-NEXT:    s_load_b32 s6, s[4:5], 0x8
-; GFX11-DENORM-NEXT:    s_load_b64 s[2:3], s[4:5], 0x0
-; GFX11-DENORM-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-DENORM-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-DENORM-NEXT:    s_lshr_b32 s0, s0, 16
-; GFX11-DENORM-NEXT:    v_fma_f16 v2, |s6|, 2.0, s1
-; GFX11-DENORM-NEXT:    v_fma_f16 v1, |s6|, 2.0, s0
-; GFX11-DENORM-NEXT:    global_store_b16 v0, v1, s[2:3] dlc
-; GFX11-DENORM-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-DENORM-NEXT:    global_store_b16 v0, v2, s[2:3] offset:2 dlc
-; GFX11-DENORM-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-DENORM-NEXT:    s_endpgm
-;
-; GFX11-FLUSH-LABEL: multiple_use_fadd_multi_fmad_f16:
-; GFX11-FLUSH:       ; %bb.0:
-; GFX11-FLUSH-NEXT:    s_clause 0x2
-; GFX11-FLUSH-NEXT:    s_load_b32 s6, s[4:5], 0x8
-; GFX11-FLUSH-NEXT:    s_load_b64 s[0:1], s[4:5], 0x8
-; GFX11-FLUSH-NEXT:    s_load_b64 s[2:3], s[4:5], 0x0
-; GFX11-FLUSH-NEXT:    v_mov_b32_e32 v1, 0
-; GFX11-FLUSH-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-FLUSH-NEXT:    v_add_f16_e64 v0, |s6|, |s6|
-; GFX11-FLUSH-NEXT:    s_lshr_b32 s0, s0, 16
-; GFX11-FLUSH-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-FLUSH-NEXT:    v_add_f16_e32 v2, s0, v0
-; GFX11-FLUSH-NEXT:    v_add_f16_e32 v0, s1, v0
-; GFX11-FLUSH-NEXT:    global_store_b16 v1, v2, s[2:3] dlc
-; GFX11-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-FLUSH-NEXT:    global_store_b16 v1, v0, s[2:3] offset:2 dlc
-; GFX11-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-FLUSH-NEXT:    s_endpgm
+; GFX11-DENORM-TRUE16-LABEL: multiple_use_fadd_multi_fmad_f16:
+; GFX11-DENORM-TRUE16:       ; %bb.0:
+; GFX11-DENORM-TRUE16-NEXT:    s_clause 0x2
+; GFX11-DENORM-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x8
+; GFX11-DENORM-TRUE16-NEXT:    s_load_b32 s6, s[4:5], 0x8
+; GFX11-DENORM-TRUE16-NEXT:    s_load_b64 s[2:3], s[4:5], 0x0
+; GFX11-DENORM-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-DENORM-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-DENORM-TRUE16-NEXT:    s_lshr_b32 s0, s0, 16
+; GFX11-DENORM-TRUE16-NEXT:    v_fma_f16 v0.h, |s6|, 2.0, s1
+; GFX11-DENORM-TRUE16-NEXT:    v_fma_f16 v0.l, |s6|, 2.0, s0
+; GFX11-DENORM-TRUE16-NEXT:    global_store_b16 v1, v0, s[2:3] dlc
+; GFX11-DENORM-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-DENORM-TRUE16-NEXT:    global_store_d16_hi_b16 v1, v0, s[2:3] offset:2 dlc
+; GFX11-DENORM-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-DENORM-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-DENORM-FAKE16-LABEL: multiple_use_fadd_multi_fmad_f16:
+; GFX11-DENORM-FAKE16:       ; %bb.0:
+; GFX11-DENORM-FAKE16-NEXT:    s_clause 0x2
+; GFX11-DENORM-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x8
+; GFX11-DENORM-FAKE16-NEXT:    s_load_b32 s6, s[4:5], 0x8
+; GFX11-DENORM-FAKE16-NEXT:    s_load_b64 s[2:3], s[4:5], 0x0
+; GFX11-DENORM-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-DENORM-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-DENORM-FAKE16-NEXT:    s_lshr_b32 s0, s0, 16
+; GFX11-DENORM-FAKE16-NEXT:    v_fma_f16 v2, |s6|, 2.0, s1
+; GFX11-DENORM-FAKE16-NEXT:    v_fma_f16 v1, |s6|, 2.0, s0
+; GFX11-DENORM-FAKE16-NEXT:    global_store_b16 v0, v1, s[2:3] dlc
+; GFX11-DENORM-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-DENORM-FAKE16-NEXT:    global_store_b16 v0, v2, s[2:3] offset:2 dlc
+; GFX11-DENORM-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-DENORM-FAKE16-NEXT:    s_endpgm
+;
+; GFX11-FLUSH-TRUE16-LABEL: multiple_use_fadd_multi_fmad_f16:
+; GFX11-FLUSH-TRUE16:       ; %bb.0:
+; GFX11-FLUSH-TRUE16-NEXT:    s_clause 0x2
+; GFX11-FLUSH-TRUE16-NEXT:    s_load_b32 s6, s[4:5], 0x8
+; GFX11-FLUSH-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x8
+; GFX11-FLUSH-TRUE16-NEXT:    s_load_b64 s[2:3], s[4:5], 0x0
+; GFX11-FLUSH-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-FLUSH-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FLUSH-TRUE16-NEXT:    v_add_f16_e64 v0.l, |s6|, |s6|
+; GFX11-FLUSH-TRUE16-NEXT:    s_lshr_b32 s0, s0, 16
+; GFX11-FLUSH-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FLUSH-TRUE16-NEXT:    v_add_f16_e32 v0.h, s0, v0.l
+; GFX11-FLUSH-TRUE16-NEXT:    v_add_f16_e32 v0.l, s1, v0.l
+; GFX11-FLUSH-TRUE16-NEXT:    global_store_d16_hi_b16 v1, v0, s[2:3] dlc
+; GFX11-FLUSH-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FLUSH-TRUE16-NEXT:    global_store_b16 v1, v0, s[2:3] offset:2 dlc
+; GFX11-FLUSH-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FLUSH-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FLUSH-FAKE16-LABEL: multiple_use_fadd_multi_fmad_f16:
+; GFX11-FLUSH-FAKE16:       ; %bb.0:
+; GFX11-FLUSH-FAKE16-NEXT:    s_clause 0x2
+; GFX11-FLUSH-FAKE16-NEXT:    s_load_b32 s6, s[4:5], 0x8
+; GFX11-FLUSH-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x8
+; GFX11-FLUSH-FAKE16-NEXT:    s_load_b64 s[2:3], s[4:5], 0x0
+; GFX11-FLUSH-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-FLUSH-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FLUSH-FAKE16-NEXT:    v_add_f16_e64 v0, |s6|, |s6|
+; GFX11-FLUSH-FAKE16-NEXT:    s_lshr_b32 s0, s0, 16
+; GFX11-FLUSH-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FLUSH-FAKE16-NEXT:    v_add_f16_e32 v2, s0, v0
+; GFX11-FLUSH-FAKE16-NEXT:    v_add_f16_e32 v0, s1, v0
+; GFX11-FLUSH-FAKE16-NEXT:    global_store_b16 v1, v2, s[2:3] dlc
+; GFX11-FLUSH-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FLUSH-FAKE16-NEXT:    global_store_b16 v1, v0, s[2:3] offset:2 dlc
+; GFX11-FLUSH-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FLUSH-FAKE16-NEXT:    s_endpgm
   %x = bitcast i16 %x.arg to half
   %y = bitcast i16 %y.arg to half
   %z = bitcast i16 %z.arg to half
@@ -914,19 +1061,33 @@ define amdgpu_kernel void @fmul_x2_xn2_f16(ptr addrspace(1) %out, i16 zeroext %x
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: fmul_x2_xn2_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    s_load_b32 s2, s[4:5], 0x8
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-NEXT:    v_mov_b32_e32 v1, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_mul_f16_e64 v0, s2, -4.0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f16_e32 v0, s2, v0
-; GFX11-NEXT:    global_store_b16 v1, v0, s[0:1] dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: fmul_x2_xn2_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    s_load_b32 s2, s[4:5], 0x8
+; GFX11-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mul_f16_e64 v0.l, s2, -4.0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v0.l, s2, v0.l
+; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1] dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: fmul_x2_xn2_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    s_load_b32 s2, s[4:5], 0x8
+; GFX11-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mul_f16_e64 v0, s2, -4.0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v0, s2, v0
+; GFX11-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1] dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_endpgm
   %x = bitcast i16 %x.arg to half
   %y = bitcast i16 %y.arg to half
   %out.gep.1 = getelementptr half, ptr addrspace(1) %out, i32 1
@@ -968,19 +1129,33 @@ define amdgpu_kernel void @fmul_x2_xn3_f16(ptr addrspace(1) %out, i16 zeroext %x
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: fmul_x2_xn3_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    s_load_b32 s2, s[4:5], 0x8
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-NEXT:    v_mov_b32_e32 v1, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_mul_f16_e64 v0, 0xc600, s2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f16_e32 v0, s2, v0
-; GFX11-NEXT:    global_store_b16 v1, v0, s[0:1] dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: fmul_x2_xn3_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    s_load_b32 s2, s[4:5], 0x8
+; GFX11-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mul_f16_e64 v0.l, 0xc600, s2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v0.l, s2, v0.l
+; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1] dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: fmul_x2_xn3_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    s_load_b32 s2, s[4:5], 0x8
+; GFX11-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mul_f16_e64 v0, 0xc600, s2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v0, s2, v0
+; GFX11-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1] dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_endpgm
   %x = bitcast i16 %x.arg to half
   %y = bitcast i16 %y.arg to half
   %out.gep.1 = getelementptr half, ptr addrspace(1) %out, i32 1
@@ -993,3 +1168,6 @@ define amdgpu_kernel void @fmul_x2_xn3_f16(ptr addrspace(1) %out, i16 zeroext %x
 
 attributes #0 = { nounwind "unsafe-fp-math"="true" }
 attributes #1 = { nounwind readnone }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11-DENORM: {{.*}}
+; GFX11-FLUSH: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll b/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
index 8c91acd5ae024..12daf10594df5 100644
--- a/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
@@ -3,8 +3,10 @@
 ; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX10,GFX10-SDAG %s
 ; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX10,GFX10-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX11,GFX11-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX11,GFX11-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
 
 ; Test fmul by power of 2 which is better emitted as ldexp
 
@@ -53,11 +55,41 @@ define double @v_mul_42_f64(double %x) {
 }
 
 define half @v_mul_42_f16(half %x) {
-; GCN-LABEL: v_mul_42_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, 0x5140, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_42_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, 0x5140, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_42_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, 0x5140, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_42_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x5140, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_42_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x5140, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_42_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x5140, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_42_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x5140, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, 42.0
   ret half %mul
 }
@@ -2644,174 +2676,684 @@ define amdgpu_ps <2 x i32> @s_mul_32_f64(double inreg %x, double inreg %y) {
 
 ; 0x1p-23
 define half @v_mul_0x1pn23_f16(half %x) {
-; GCN-LABEL: v_mul_0x1pn23_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, 2, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_0x1pn23_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, 2, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_0x1pn23_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, 2, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_0x1pn23_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 2, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_0x1pn23_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 2, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_0x1pn23_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 2, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_0x1pn23_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 2, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, 0xH0002
   ret half %mul
 }
 
 ; 0x1p-17
 define half @v_mul_0x1pn17_f16(half %x) {
-; GCN-LABEL: v_mul_0x1pn17_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, 0x80, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_0x1pn17_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, 0x80, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_0x1pn17_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, 0x80, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_0x1pn17_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x80, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_0x1pn17_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x80, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_0x1pn17_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x80, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_0x1pn17_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x80, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, 0.00000762939453125
   ret half %mul
 }
 
 ; 0x1p-16
 define half @v_mul_0x1pn16_f16(half %x) {
-; GCN-LABEL: v_mul_0x1pn16_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, 0x100, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_0x1pn16_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, 0x100, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_0x1pn16_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, 0x100, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_0x1pn16_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x100, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_0x1pn16_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x100, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_0x1pn16_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x100, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_0x1pn16_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x100, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, 0.0000152587890625
   ret half %mul
 }
 
 ; 0x1p-15
 define half @v_mul_0x1pn15_f16(half %x) {
-; GCN-LABEL: v_mul_0x1pn15_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, 0x200, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_0x1pn15_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, 0x200, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_0x1pn15_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, 0x200, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_0x1pn15_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x200, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_0x1pn15_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x200, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_0x1pn15_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x200, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_0x1pn15_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x200, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, 0.000030517578125
   ret half %mul
 }
 
 define half @v_mul_neg256_f16(half %x) {
-; GCN-LABEL: v_mul_neg256_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, 0xdc00, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_neg256_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, 0xdc00, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_neg256_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, 0xdc00, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_neg256_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0xdc00, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_neg256_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0xdc00, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_neg256_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0xdc00, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_neg256_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0xdc00, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, -256.0
   ret half %mul
 }
 
 define half @v_mul_neg128_f16(half %x) {
-; GCN-LABEL: v_mul_neg128_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, 0xd800, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_neg128_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, 0xd800, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_neg128_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, 0xd800, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_neg128_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0xd800, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_neg128_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0xd800, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_neg128_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0xd800, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_neg128_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0xd800, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, -128.0
   ret half %mul
 }
 
 define half @v_mul_neg64_f16(half %x) {
-; GCN-LABEL: v_mul_neg64_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, 0xd400, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_neg64_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, 0xd400, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_neg64_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, 0xd400, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_neg64_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0xd400, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_neg64_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0xd400, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_neg64_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0xd400, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_neg64_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0xd400, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, -64.0
   ret half %mul
 }
 
 define half @v_mul_neg32_f16(half %x) {
-; GCN-LABEL: v_mul_neg32_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, 0xd000, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_neg32_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, 0xd000, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_neg32_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, 0xd000, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_neg32_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0xd000, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_neg32_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0xd000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_neg32_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0xd000, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_neg32_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0xd000, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, -32.0
   ret half %mul
 }
 
 define half @v_mul_neg16_f16(half %x) {
-; GCN-LABEL: v_mul_neg16_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, 0xcc00, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_neg16_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, 0xcc00, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_neg16_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, 0xcc00, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_neg16_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0xcc00, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_neg16_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0xcc00, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_neg16_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0xcc00, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_neg16_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0xcc00, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, -16.0
   ret half %mul
 }
 
 define half @v_mul_neg8_f16(half %x) {
-; GCN-LABEL: v_mul_neg8_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, 0xc800, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_neg8_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, 0xc800, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_neg8_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, 0xc800, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_neg8_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0xc800, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_neg8_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0xc800, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_neg8_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0xc800, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_neg8_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0xc800, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, -8.0
   ret half %mul
 }
 
 define half @v_mul_neg4_f16(half %x) {
-; GCN-LABEL: v_mul_neg4_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, -4.0, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_neg4_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, -4.0, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_neg4_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, -4.0, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_neg4_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, -4.0, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_neg4_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, -4.0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_neg4_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, -4.0, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_neg4_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, -4.0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, -4.0
   ret half %mul
 }
 
 define half @v_mul_neg2_f16(half %x) {
-; GCN-LABEL: v_mul_neg2_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, -2.0, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_neg2_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, -2.0, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_neg2_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, -2.0, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_neg2_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, -2.0, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_neg2_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, -2.0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_neg2_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, -2.0, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_neg2_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, -2.0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, -2.0
   ret half %mul
 }
 
 define half @v_mul_neg1_f16(half %x) {
-; GCN-LABEL: v_mul_neg1_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_neg1_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_neg1_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_neg1_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_neg1_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_neg1_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_neg1_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, -1.0
   ret half %mul
 }
 
 define half @v_mul_neg_half_f16(half %x) {
-; GCN-LABEL: v_mul_neg_half_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, -0.5, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_neg_half_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, -0.5, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_neg_half_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, -0.5, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_neg_half_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, -0.5, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_neg_half_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, -0.5, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_neg_half_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, -0.5, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_neg_half_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, -0.5, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, -0.5
   ret half %mul
 }
 
 define half @v_mul_neg_quarter_f16(half %x) {
-; GCN-LABEL: v_mul_neg_quarter_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, 0xb400, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_neg_quarter_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, 0xb400, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_neg_quarter_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, 0xb400, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_neg_quarter_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0xb400, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_neg_quarter_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0xb400, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_neg_quarter_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0xb400, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_neg_quarter_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0xb400, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, -0.25
   ret half %mul
 }
 
 define half @v_mul_quarter_f16(half %x) {
-; GCN-LABEL: v_mul_quarter_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, 0x3400, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_quarter_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, 0x3400, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_quarter_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, 0x3400, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_quarter_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x3400, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_quarter_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x3400, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_quarter_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x3400, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_quarter_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x3400, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, 0.25
   ret half %mul
 }
 
 define half @v_mul_half_f16(half %x) {
-; GCN-LABEL: v_mul_half_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, 0.5, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_half_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, 0.5, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_half_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, 0.5, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_half_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0.5, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_half_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0.5, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_half_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0.5, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_half_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0.5, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, 0.5
   ret half %mul
 }
@@ -2850,109 +3392,391 @@ define half @v_mul_2_f16(half %x) {
 ; GFX10-GISEL-NEXT:    v_mul_f16_e32 v0, 2.0, v0
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: v_mul_2_f16:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_f16_e32 v0, v0, v0
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_mul_2_f16:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_mul_f16_e32 v0, 2.0, v0
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: v_mul_2_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_2_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_2_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 2.0, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_2_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 2.0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, 2.0
   ret half %mul
 }
 
 define half @v_mul_4_f16(half %x) {
-; GCN-LABEL: v_mul_4_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, 4.0, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_4_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, 4.0, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_4_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, 4.0, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_4_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 4.0, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_4_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 4.0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_4_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 4.0, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_4_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 4.0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, 4.0
   ret half %mul
 }
 
 define half @v_mul_8_f16(half %x) {
-; GCN-LABEL: v_mul_8_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, 0x4800, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_8_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, 0x4800, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_8_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, 0x4800, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_8_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x4800, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_8_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x4800, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_8_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x4800, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_8_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x4800, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, 8.0
   ret half %mul
 }
 
 define half @v_mul_16_f16(half %x) {
-; GCN-LABEL: v_mul_16_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, 0x4c00, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_16_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, 0x4c00, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_16_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, 0x4c00, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_16_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x4c00, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_16_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x4c00, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_16_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x4c00, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_16_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x4c00, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, 16.0
   ret half %mul
 }
 
 define half @v_mul_32_f16(half %x) {
-; GCN-LABEL: v_mul_32_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, 0x5000, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_32_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, 0x5000, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_32_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, 0x5000, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_32_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x5000, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_32_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x5000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_32_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x5000, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_32_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x5000, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, 32.0
   ret half %mul
 }
 
 define half @v_mul_64_f16(half %x) {
-; GCN-LABEL: v_mul_64_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, 0x5400, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
-  %mul = fmul half %x, 64.0
-  ret half %mul
-}
-
+; GFX9-LABEL: v_mul_64_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, 0x5400, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_64_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, 0x5400, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_64_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x5400, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_64_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x5400, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_64_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x5400, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_64_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x5400, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+  %mul = fmul half %x, 64.0
+  ret half %mul
+}
+
 define half @v_mul_128_f16(half %x) {
-; GCN-LABEL: v_mul_128_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, 0x5800, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_128_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, 0x5800, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_128_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, 0x5800, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_128_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x5800, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_128_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x5800, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_128_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x5800, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_128_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x5800, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, 128.0
   ret half %mul
 }
 
 define half @v_mul_256_f16(half %x) {
-; GCN-LABEL: v_mul_256_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, 0x5c00, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_256_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, 0x5c00, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_256_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, 0x5c00, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_256_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x5c00, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_256_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x5c00, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_256_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x5c00, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_256_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x5c00, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, 256.0
   ret half %mul
 }
 
 ; 0x1p+15
 define half @v_mul_0x1p15_f16(half %x) {
-; GCN-LABEL: v_mul_0x1p15_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, 0x7800, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_0x1p15_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, 0x7800, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_0x1p15_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, 0x7800, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_0x1p15_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x7800, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_0x1p15_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x7800, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_0x1p15_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x7800, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_0x1p15_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x7800, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, 32768.0
   ret half %mul
 }
 
 ; 0x1p+14
 define half @v_mul_0x1p14_f16(half %x) {
-; GCN-LABEL: v_mul_0x1p14_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, 0x7400, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mul_0x1p14_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, 0x7400, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_0x1p14_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, 0x7400, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_0x1p14_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x7400, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_0x1p14_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x7400, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_0x1p14_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x7400, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_0x1p14_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x7400, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul half %x, 16384.0
   ret half %mul
 }
@@ -2973,11 +3797,36 @@ define half @v_fma_mul_add_32_f16(half %x, half %y) {
 ; GFX9-GISEL-NEXT:    v_fma_f16 v0, v0, v2, v1
 ; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1011-LABEL: v_fma_mul_add_32_f16:
-; GFX1011:       ; %bb.0:
-; GFX1011-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1011-NEXT:    v_fmamk_f16 v0, v0, 0x5000, v1
-; GFX1011-NEXT:    s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_fma_mul_add_32_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_fmamk_f16 v0, v0, 0x5000, v1
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_fma_mul_add_32_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_fmamk_f16 v0.l, v0.l, 0x5000, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_fma_mul_add_32_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_fmamk_f16 v0, v0, 0x5000, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_fma_mul_add_32_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_fmac_f16_e32 v1.l, 0x5000, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v0, v1
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_fma_mul_add_32_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_fmamk_f16 v0, v0, 0x5000, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul contract half %x, 32.0
   %fma = fadd contract half %mul, %y
   ret half %fma
@@ -2998,11 +3847,35 @@ define half @v_fma_mul_sub_32_f16(half %x, half %y) {
 ; GFX9-GISEL-NEXT:    v_fma_f16 v0, v0, v2, -v1
 ; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1011-LABEL: v_fma_mul_sub_32_f16:
-; GFX1011:       ; %bb.0:
-; GFX1011-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1011-NEXT:    v_fma_f16 v0, v0, 0x5000, -v1
-; GFX1011-NEXT:    s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_fma_mul_sub_32_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_fma_f16 v0, v0, 0x5000, -v1
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_fma_mul_sub_32_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_fma_f16 v0.l, v0.l, 0x5000, -v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_fma_mul_sub_32_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_fma_f16 v0, v0, 0x5000, -v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_fma_mul_sub_32_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_fma_f16 v0.l, v0.l, 0x5000, -v1.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_fma_mul_sub_32_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_fma_f16 v0, v0, 0x5000, -v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul contract half %x, 32.0
   %fma = fsub contract half %mul, %y
   ret half %fma
@@ -3023,11 +3896,36 @@ define half @v_fma_mul_add_neg32_f16(half %x, half %y) {
 ; GFX9-GISEL-NEXT:    v_fma_f16 v0, v0, v2, v1
 ; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1011-LABEL: v_fma_mul_add_neg32_f16:
-; GFX1011:       ; %bb.0:
-; GFX1011-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1011-NEXT:    v_fmamk_f16 v0, v0, 0xd000, v1
-; GFX1011-NEXT:    s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_fma_mul_add_neg32_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_fmamk_f16 v0, v0, 0xd000, v1
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_fma_mul_add_neg32_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_fmamk_f16 v0.l, v0.l, 0xd000, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_fma_mul_add_neg32_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_fmamk_f16 v0, v0, 0xd000, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_fma_mul_add_neg32_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_fmac_f16_e32 v1.l, 0xd000, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v0, v1
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_fma_mul_add_neg32_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_fmamk_f16 v0, v0, 0xd000, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %mul = fmul contract half %x, -32.0
   %fma = fadd contract half %mul, %y
   ret half %fma
@@ -3048,11 +3946,35 @@ define half @v_mul_fabs_32_f16(half %x) {
 ; GFX9-GISEL-NEXT:    v_mul_f16_e64 v0, |v0|, v1
 ; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1011-LABEL: v_mul_fabs_32_f16:
-; GFX1011:       ; %bb.0:
-; GFX1011-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1011-NEXT:    v_mul_f16_e64 v0, 0x5000, |v0|
-; GFX1011-NEXT:    s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_mul_fabs_32_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e64 v0, 0x5000, |v0|
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_fabs_32_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e64 v0.l, 0x5000, |v0.l|
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_fabs_32_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e64 v0, 0x5000, |v0|
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_fabs_32_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e64 v0.l, 0x5000, |v0.l|
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_fabs_32_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e64 v0, 0x5000, |v0|
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %x.fabs = call half @llvm.fabs.f16(half %x)
   %mul = fmul half %x.fabs, 32.0
   ret half %mul
@@ -3073,11 +3995,35 @@ define half @v_mul_add_fma_fabs_32_f16(half %x, half %y) {
 ; GFX9-GISEL-NEXT:    v_fma_f16 v0, |v0|, v2, v1
 ; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1011-LABEL: v_mul_add_fma_fabs_32_f16:
-; GFX1011:       ; %bb.0:
-; GFX1011-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1011-NEXT:    v_fma_f16 v0, |v0|, 0x5000, v1
-; GFX1011-NEXT:    s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_mul_add_fma_fabs_32_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_fma_f16 v0, |v0|, 0x5000, v1
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_add_fma_fabs_32_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_fma_f16 v0.l, |v0.l|, 0x5000, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_add_fma_fabs_32_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_fma_f16 v0, |v0|, 0x5000, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_add_fma_fabs_32_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_fma_f16 v0.l, |v0.l|, 0x5000, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_add_fma_fabs_32_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_fma_f16 v0, |v0|, 0x5000, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %x.fabs = call half @llvm.fabs.f16(half %x)
   %mul = fmul contract half %x.fabs, 32.0
   %fma = fadd contract half %mul, %y
@@ -3268,12 +4214,40 @@ define amdgpu_ps i32 @s_mul_32_f16(half inreg %x, half inreg %y) {
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX1011-LABEL: s_mul_32_f16:
-; GFX1011:       ; %bb.0:
-; GFX1011-NEXT:    v_mul_f16_e64 v0, 0x5000, s0
-; GFX1011-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX1011-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX1011-NEXT:    ; return to shader part epilog
+; GFX10-LABEL: s_mul_32_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_mul_f16_e64 v0, 0x5000, s0
+; GFX10-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10-NEXT:    ; return to shader part epilog
+;
+; GFX11-SDAG-TRUE16-LABEL: s_mul_32_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e64 v0.l, 0x5000, s0
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX11-SDAG-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-SDAG-FAKE16-LABEL: s_mul_32_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e64 v0, 0x5000, s0
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX11-SDAG-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-GISEL-TRUE16-LABEL: s_mul_32_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e64 v0.l, 0x5000, s0
+; GFX11-GISEL-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX11-GISEL-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-GISEL-FAKE16-LABEL: s_mul_32_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e64 v0, 0x5000, s0
+; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX11-GISEL-FAKE16-NEXT:    ; return to shader part epilog
   %mul = fmul contract half %x, 32.0
   %cast = bitcast half %mul to i16
   %zext = zext i16 %cast to i32
@@ -4678,13 +5652,45 @@ define half @v_mul_f16_select_64_1(i32 %arg, half %x) {
 ; GFX9-NEXT:    v_ldexp_f16_e32 v0, v1, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1011-LABEL: v_mul_f16_select_64_1:
-; GFX1011:       ; %bb.0:
-; GFX1011-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1011-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX1011-NEXT:    v_cndmask_b32_e64 v0, 0, 6, vcc_lo
-; GFX1011-NEXT:    v_ldexp_f16_e32 v0, v1, v0
-; GFX1011-NEXT:    s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_mul_f16_select_64_1:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 6, vcc_lo
+; GFX10-NEXT:    v_ldexp_f16_e32 v0, v1, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_f16_select_64_1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 6, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_f16_select_64_1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 6, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v1, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_f16_select_64_1:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 6, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v1.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_f16_select_64_1:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 6, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v1, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq i32 %arg, 0
   %select.pow2 = select i1 %cond, half 64.0, half 1.0
   %mul = fmul half %x, %select.pow2
@@ -4700,13 +5706,45 @@ define half @v_mul_f16_select_1_64(i32 %arg, half %x) {
 ; GFX9-NEXT:    v_ldexp_f16_e32 v0, v1, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1011-LABEL: v_mul_f16_select_1_64:
-; GFX1011:       ; %bb.0:
-; GFX1011-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1011-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX1011-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
-; GFX1011-NEXT:    v_ldexp_f16_e32 v0, v1, v0
-; GFX1011-NEXT:    s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_mul_f16_select_1_64:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX10-NEXT:    v_ldexp_f16_e32 v0, v1, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_f16_select_1_64:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_f16_select_1_64:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v1, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_f16_select_1_64:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v1.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_f16_select_1_64:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v1, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq i32 %arg, 0
   %select.pow2 = select i1 %cond, half 1.0, half 64.0
   %mul = fmul half %x, %select.pow2
@@ -4722,13 +5760,45 @@ define half @v_mul_f16_select_n1_n64(i32 %arg, half %x) {
 ; GFX9-NEXT:    v_ldexp_f16_e64 v0, -v1, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1011-LABEL: v_mul_f16_select_n1_n64:
-; GFX1011:       ; %bb.0:
-; GFX1011-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1011-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX1011-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
-; GFX1011-NEXT:    v_ldexp_f16_e64 v0, -v1, v0
-; GFX1011-NEXT:    s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_mul_f16_select_n1_n64:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX10-NEXT:    v_ldexp_f16_e64 v0, -v1, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_f16_select_n1_n64:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_ldexp_f16_e64 v0.l, -v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_f16_select_n1_n64:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_ldexp_f16_e64 v0, -v1, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_f16_select_n1_n64:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e64 v0.l, -v1.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_f16_select_n1_n64:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e64 v0, -v1, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq i32 %arg, 0
   %select.pow2 = select i1 %cond, half -1.0, half -64.0
   %mul = fmul half %x, %select.pow2
@@ -4775,24 +5845,43 @@ define half @v_mul_f16_select_128_64(i32 %arg, half %x) {
 ; GFX10-GISEL-NEXT:    v_ldexp_f16_e32 v0, v1, v0
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: v_mul_f16_select_128_64:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e64 v0, 6, 7, vcc_lo
-; GFX11-SDAG-NEXT:    v_ldexp_f16_e32 v0, v1, v0
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_mul_f16_select_128_64:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7fff
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-GISEL-NEXT:    v_add_nc_u32_e32 v0, 6, v0
-; GFX11-GISEL-NEXT:    v_med3_i32 v0, 0xffff8000, v0, v2
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v1, v0
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: v_mul_f16_select_128_64:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 6, 7, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_f16_select_128_64:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 6, 7, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v1, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_f16_select_128_64:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v2, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_add_nc_u32_e32 v0, 6, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_med3_i32 v0, 0xffff8000, v0, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v1.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_f16_select_128_64:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v2, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_add_nc_u32_e32 v0, 6, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_med3_i32 v0, 0xffff8000, v0, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v1, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq i32 %arg, 0
   %select.pow2 = select i1 %cond, half 128.0, half 64.0
   %mul = fmul half %x, %select.pow2
@@ -4839,24 +5928,43 @@ define half @v_mul_f16_select_n128_n64(i32 %arg, half %x) {
 ; GFX10-GISEL-NEXT:    v_ldexp_f16_e64 v0, -v1, v0
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: v_mul_f16_select_n128_n64:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e64 v0, 6, 7, vcc_lo
-; GFX11-SDAG-NEXT:    v_ldexp_f16_e64 v0, -v1, v0
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_mul_f16_select_n128_n64:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7fff
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-GISEL-NEXT:    v_add_nc_u32_e32 v0, 6, v0
-; GFX11-GISEL-NEXT:    v_med3_i32 v0, 0xffff8000, v0, v2
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e64 v0, -v1, v0
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: v_mul_f16_select_n128_n64:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 6, 7, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_ldexp_f16_e64 v0.l, -v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_f16_select_n128_n64:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 6, 7, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_ldexp_f16_e64 v0, -v1, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_f16_select_n128_n64:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v2, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_add_nc_u32_e32 v0, 6, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_med3_i32 v0, 0xffff8000, v0, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e64 v0.l, -v1.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_f16_select_n128_n64:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v2, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_add_nc_u32_e32 v0, 6, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_med3_i32 v0, 0xffff8000, v0, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e64 v0, -v1, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq i32 %arg, 0
   %select.pow2 = select i1 %cond, half -128.0, half -64.0
   %mul = fmul half %x, %select.pow2
@@ -4872,13 +5980,45 @@ define half @v_mul_f16_select_n128_n16(i32 %arg, half %x) {
 ; GFX9-NEXT:    v_ldexp_f16_e64 v0, -v1, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1011-LABEL: v_mul_f16_select_n128_n16:
-; GFX1011:       ; %bb.0:
-; GFX1011-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1011-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX1011-NEXT:    v_cndmask_b32_e64 v0, 4, 7, vcc_lo
-; GFX1011-NEXT:    v_ldexp_f16_e64 v0, -v1, v0
-; GFX1011-NEXT:    s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_mul_f16_select_n128_n16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-NEXT:    v_cndmask_b32_e64 v0, 4, 7, vcc_lo
+; GFX10-NEXT:    v_ldexp_f16_e64 v0, -v1, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_mul_f16_select_n128_n16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 4, 7, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_ldexp_f16_e64 v0.l, -v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_f16_select_n128_n16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 4, 7, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_ldexp_f16_e64 v0, -v1, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_f16_select_n128_n16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 4, 7, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e64 v0.l, -v1.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_f16_select_n128_n16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 4, 7, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e64 v0, -v1, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq i32 %arg, 0
   %select.pow2 = select i1 %cond, half -128.0, half -16.0
   %mul = fmul half %x, %select.pow2
@@ -4923,23 +6063,41 @@ define half @v_contract_mul_add_f16_select_64_1(i32 %arg, half %x, half %y) {
 ; GFX10-GISEL-NEXT:    v_add_f16_e32 v0, v0, v2
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: v_contract_mul_add_f16_select_64_1:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v3, 0x5400
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0x3c00, v3, vcc_lo
-; GFX11-SDAG-NEXT:    v_fma_f16 v0, v1, v0, v2
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_contract_mul_add_f16_select_64_1:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 6, vcc_lo
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v1, v0
-; GFX11-GISEL-NEXT:    v_add_f16_e32 v0, v0, v2
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: v_contract_mul_add_f16_select_64_1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0x5400
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x3c00, v3.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_fma_f16 v0.l, v1.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_contract_mul_add_f16_select_64_1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v3, 0x5400
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x3c00, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_fma_f16 v0, v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_contract_mul_add_f16_select_64_1:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 6, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v1.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_f16_select_64_1:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 6, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v1, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq i32 %arg, 0
   %select.pow2 = select contract i1 %cond, half 64.0, half 1.0
   %mul = fmul contract half %x, %select.pow2
@@ -4985,23 +6143,41 @@ define half @v_contract_mul_add_f16_select_1_64(i32 %arg, half %x, half %y) {
 ; GFX10-GISEL-NEXT:    v_add_f16_e32 v0, v0, v2
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: v_contract_mul_add_f16_select_1_64:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v3, 0x3c00
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0x5400, v3, vcc_lo
-; GFX11-SDAG-NEXT:    v_fma_f16 v0, v1, v0, v2
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_contract_mul_add_f16_select_1_64:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v1, v0
-; GFX11-GISEL-NEXT:    v_add_f16_e32 v0, v0, v2
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: v_contract_mul_add_f16_select_1_64:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0x3c00
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x5400, v3.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_fma_f16 v0.l, v1.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_contract_mul_add_f16_select_1_64:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v3, 0x3c00
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x5400, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_fma_f16 v0, v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_contract_mul_add_f16_select_1_64:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v1.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_f16_select_1_64:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v1, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq i32 %arg, 0
   %select.pow2 = select contract i1 %cond, half 1.0, half 64.0
   %mul = fmul contract half %x, %select.pow2
@@ -5047,23 +6223,41 @@ define half @v_contract_mul_add_f16_select_n64_n1(i32 %arg, half %x, half %y) {
 ; GFX10-GISEL-NEXT:    v_add_f16_e32 v0, v0, v2
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: v_contract_mul_add_f16_select_n64_n1:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v3, 0xd400
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0xbc00, v3, vcc_lo
-; GFX11-SDAG-NEXT:    v_fma_f16 v0, v1, v0, v2
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_contract_mul_add_f16_select_n64_n1:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 6, vcc_lo
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e64 v0, -v1, v0
-; GFX11-GISEL-NEXT:    v_add_f16_e32 v0, v0, v2
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: v_contract_mul_add_f16_select_n64_n1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0xd400
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0xbc00, v3.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_fma_f16 v0.l, v1.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_contract_mul_add_f16_select_n64_n1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v3, 0xd400
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0xbc00, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_fma_f16 v0, v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_contract_mul_add_f16_select_n64_n1:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 6, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e64 v0.l, -v1.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_f16_select_n64_n1:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 6, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e64 v0, -v1, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq i32 %arg, 0
   %select.pow2 = select contract i1 %cond, half -64.0, half -1.0
   %mul = fmul contract half %x, %select.pow2
@@ -5109,23 +6303,41 @@ define half @v_contract_mul_add_f16_select_n1_n64(i32 %arg, half %x, half %y) {
 ; GFX10-GISEL-NEXT:    v_add_f16_e32 v0, v0, v2
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: v_contract_mul_add_f16_select_n1_n64:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v3, 0xbc00
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0xd400, v3, vcc_lo
-; GFX11-SDAG-NEXT:    v_fma_f16 v0, v1, v0, v2
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_contract_mul_add_f16_select_n1_n64:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e64 v0, -v1, v0
-; GFX11-GISEL-NEXT:    v_add_f16_e32 v0, v0, v2
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: v_contract_mul_add_f16_select_n1_n64:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0xbc00
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0xd400, v3.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_fma_f16 v0.l, v1.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_contract_mul_add_f16_select_n1_n64:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v3, 0xbc00
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0xd400, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_fma_f16 v0, v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_contract_mul_add_f16_select_n1_n64:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e64 v0.l, -v1.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_f16_select_n1_n64:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e64 v0, -v1, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq i32 %arg, 0
   %select.pow2 = select contract i1 %cond, half -1.0, half -64.0
   %mul = fmul contract half %x, %select.pow2
@@ -5178,26 +6390,47 @@ define half @v_contract_mul_add_f16_select_128_64(i32 %arg, half %x, half %y) {
 ; GFX10-GISEL-NEXT:    v_add_f16_e32 v0, v0, v2
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: v_contract_mul_add_f16_select_128_64:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v3, 0x5800
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0x5400, v3, vcc_lo
-; GFX11-SDAG-NEXT:    v_fma_f16 v0, v1, v0, v2
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_contract_mul_add_f16_select_128_64:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT:    v_mov_b32_e32 v3, 0x7fff
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-GISEL-NEXT:    v_add_nc_u32_e32 v0, 6, v0
-; GFX11-GISEL-NEXT:    v_med3_i32 v0, 0xffff8000, v0, v3
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v1, v0
-; GFX11-GISEL-NEXT:    v_add_f16_e32 v0, v0, v2
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: v_contract_mul_add_f16_select_128_64:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0x5800
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x5400, v3.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_fma_f16 v0.l, v1.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_contract_mul_add_f16_select_128_64:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v3, 0x5800
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x5400, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_fma_f16 v0, v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_contract_mul_add_f16_select_128_64:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v3, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_add_nc_u32_e32 v0, 6, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v1.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_f16_select_128_64:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v3, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_add_nc_u32_e32 v0, 6, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v1, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq i32 %arg, 0
   %select.pow2 = select i1 %cond, half 128.0, half 64.0
   %mul = fmul contract half %x, %select.pow2
@@ -5243,23 +6476,41 @@ define half @v_contract_mul_add_f16_select_128_4(i32 %arg, half %x, half %y) {
 ; GFX10-GISEL-NEXT:    v_add_f16_e32 v0, v0, v2
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: v_contract_mul_add_f16_select_128_4:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v3, 0x5800
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0x4400, v3, vcc_lo
-; GFX11-SDAG-NEXT:    v_fma_f16 v0, v1, v0, v2
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_contract_mul_add_f16_select_128_4:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v0, 2, 7, vcc_lo
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v1, v0
-; GFX11-GISEL-NEXT:    v_add_f16_e32 v0, v0, v2
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: v_contract_mul_add_f16_select_128_4:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0x5800
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x4400, v3.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_fma_f16 v0.l, v1.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_contract_mul_add_f16_select_128_4:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v3, 0x5800
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x4400, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_fma_f16 v0, v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_contract_mul_add_f16_select_128_4:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 2, 7, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v1.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_f16_select_128_4:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 2, 7, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v1, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq i32 %arg, 0
   %select.pow2 = select i1 %cond, half 128.0, half 4.0
   %mul = fmul contract half %x, %select.pow2
@@ -5312,26 +6563,47 @@ define half @v_contract_mul_add_f16_select_2_4(i32 %arg, half %x, half %y) {
 ; GFX10-GISEL-NEXT:    v_add_f16_e32 v0, v0, v2
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: v_contract_mul_add_f16_select_2_4:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v3, 0x4000
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0x4400, v3, vcc_lo
-; GFX11-SDAG-NEXT:    v_fma_f16 v0, v1, v0, v2
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_contract_mul_add_f16_select_2_4:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT:    v_mov_b32_e32 v3, 0x7fff
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX11-GISEL-NEXT:    v_add_nc_u32_e32 v0, 2, v0
-; GFX11-GISEL-NEXT:    v_med3_i32 v0, 0xffff8000, v0, v3
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v1, v0
-; GFX11-GISEL-NEXT:    v_add_f16_e32 v0, v0, v2
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: v_contract_mul_add_f16_select_2_4:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0x4000
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x4400, v3.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_fma_f16 v0.l, v1.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_contract_mul_add_f16_select_2_4:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v3, 0x4000
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x4400, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_fma_f16 v0, v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_contract_mul_add_f16_select_2_4:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v3, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_add_nc_u32_e32 v0, 2, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v1.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_f16_select_2_4:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v3, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_add_nc_u32_e32 v0, 2, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v1, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq i32 %arg, 0
   %select.pow2 = select i1 %cond, half 2.0, half 4.0
   %mul = fmul contract half %x, %select.pow2
@@ -5377,23 +6649,41 @@ define half @v_contract_mul_add_f16_select_4_128(i32 %arg, half %x, half %y) {
 ; GFX10-GISEL-NEXT:    v_add_f16_e32 v0, v0, v2
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: v_contract_mul_add_f16_select_4_128:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v3, 0x4400
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0x5800, v3, vcc_lo
-; GFX11-SDAG-NEXT:    v_fma_f16 v0, v1, v0, v2
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_contract_mul_add_f16_select_4_128:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v0, 7, 2, vcc_lo
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v1, v0
-; GFX11-GISEL-NEXT:    v_add_f16_e32 v0, v0, v2
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: v_contract_mul_add_f16_select_4_128:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0x4400
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x5800, v3.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_fma_f16 v0.l, v1.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_contract_mul_add_f16_select_4_128:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v3, 0x4400
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x5800, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_fma_f16 v0, v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_contract_mul_add_f16_select_4_128:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 7, 2, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v1.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_f16_select_4_128:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 7, 2, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v1, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq i32 %arg, 0
   %select.pow2 = select i1 %cond, half 4.0, half 128.0
   %mul = fmul contract half %x, %select.pow2
@@ -5452,31 +6742,54 @@ define <2 x half> @v_mul_v2f16_select_64_1(<2 x i32> %arg, <2 x half> %x) {
 ; GFX10-GISEL-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: v_mul_v2f16_select_64_1:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v3, 0x5400
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0x3c00, v3, vcc_lo
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0x3c00, v3, vcc_lo
-; GFX11-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_pk_mul_f16 v0, v2, v0
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_mul_v2f16_select_64_1:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 6, vcc_lo
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v2, v0
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, 6, vcc_lo
-; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v1, v3, v1
-; GFX11-GISEL-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: v_mul_v2f16_select_64_1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0x5400
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e64 s0, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x3c00, v3.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0x3c00, v3.l, s0
+; GFX11-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_mul_f16 v0, v2, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_v2f16_select_64_1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v3, 0x5400
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x3c00, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x3c00, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_mul_f16 v0, v2, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_v2f16_select_64_1:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 6, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v2.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, 6, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.h, v2.h, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_v2f16_select_64_1:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 6, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v2, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 6, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v1, v3, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq <2 x i32> %arg, zeroinitializer
   %select.pow2 = select <2 x i1> %cond, <2 x half> <half 64.0, half 64.0>, <2 x half> <half 1.0, half 1.0>
   %mul = fmul <2 x half> %x, %select.pow2
@@ -5534,31 +6847,54 @@ define <2 x half> @v_mul_v2f16_select_1_64(<2 x i32> %arg, <2 x half> %x) {
 ; GFX10-GISEL-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: v_mul_v2f16_select_1_64:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v3, 0x3c00
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0x5400, v3, vcc_lo
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0x5400, v3, vcc_lo
-; GFX11-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_pk_mul_f16 v0, v2, v0
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_mul_v2f16_select_1_64:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v2, v0
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v1, 6, 0, vcc_lo
-; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v1, v3, v1
-; GFX11-GISEL-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: v_mul_v2f16_select_1_64:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0x3c00
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e64 s0, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x5400, v3.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0x5400, v3.l, s0
+; GFX11-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_mul_f16 v0, v2, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_v2f16_select_1_64:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v3, 0x3c00
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x5400, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x5400, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_mul_f16 v0, v2, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_v2f16_select_1_64:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v2.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 6, 0, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.h, v2.h, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_v2f16_select_1_64:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v2, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 6, 0, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v1, v3, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq <2 x i32> %arg, zeroinitializer
   %select.pow2 = select <2 x i1> %cond, <2 x half> <half 1.0, half 1.0>, <2 x half> <half 64.0, half 64.0>
   %mul = fmul <2 x half> %x, %select.pow2
@@ -5618,32 +6954,56 @@ define <2 x half> @v_mul_v2f16_select_n1_n64(<2 x i32> %arg, <2 x half> %x) {
 ; GFX10-GISEL-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: v_mul_v2f16_select_n1_n64:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v3, 0xbc00
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0xd400, v3, vcc_lo
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0xd400, v3, vcc_lo
-; GFX11-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_pk_mul_f16 v0, v2, v0
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_mul_v2f16_select_n1_n64:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT:    v_xor_b32_e32 v2, 0x80008000, v2
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v2, v0
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v1, 6, 0, vcc_lo
-; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v1, v3, v1
-; GFX11-GISEL-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: v_mul_v2f16_select_n1_n64:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0xbc00
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e64 s0, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0xd400, v3.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0xd400, v3.l, s0
+; GFX11-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_mul_f16 v0, v2, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_v2f16_select_n1_n64:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v3, 0xbc00
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0xd400, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0xd400, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_mul_f16 v0, v2, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_v2f16_select_n1_n64:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_xor_b32_e32 v2, 0x80008000, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v2.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 6, 0, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.h, v2.h, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_v2f16_select_n1_n64:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_xor_b32_e32 v2, 0x80008000, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v2, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 6, 0, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v1, v3, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq <2 x i32> %arg, zeroinitializer
   %select.pow2 = select <2 x i1> %cond, <2 x half> <half -1.0, half -1.0>, <2 x half> <half -64.0, half -64.0>
   %mul = fmul <2 x half> %x, %select.pow2
@@ -5712,36 +7072,63 @@ define <2 x half> @v_mul_v2f16_select_128_64(<2 x i32> %arg, <2 x half> %x) {
 ; GFX10-GISEL-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: v_mul_v2f16_select_128_64:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v3, 0x5800
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0x5400, v3, vcc_lo
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0x5400, v3, vcc_lo
-; GFX11-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_pk_mul_f16 v0, v2, v0
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_mul_v2f16_select_128_64:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-GISEL-NEXT:    v_mov_b32_e32 v3, 0x7fff
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-NEXT:    v_add_nc_u32_e32 v0, 6, v0
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-GISEL-NEXT:    v_med3_i32 v0, 0xffff8000, v0, v3
-; GFX11-GISEL-NEXT:    v_add_nc_u32_e32 v1, 6, v1
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v2, v0
-; GFX11-GISEL-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v3
-; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v1, v4, v1
-; GFX11-GISEL-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: v_mul_v2f16_select_128_64:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0x5800
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e64 s0, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x5400, v3.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0x5400, v3.l, s0
+; GFX11-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_mul_f16 v0, v2, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_v2f16_select_128_64:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v3, 0x5800
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x5400, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x5400, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_mul_f16 v0, v2, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_v2f16_select_128_64:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_dual_mov_b32 v3, 0x7fff :: v_dual_add_nc_u32 v0, 6, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX11-GISEL-TRUE16-NEXT:    v_add_nc_u32_e32 v1, 6, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v2.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v3
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.h, v2.h, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_v2f16_select_128_64:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v3, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_add_nc_u32_e32 v0, 6, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_add_nc_u32_e32 v1, 6, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v2, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v1, v4, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq <2 x i32> %arg, zeroinitializer
   %select.pow2 = select <2 x i1> %cond, <2 x half> <half 128.0, half 128.0>, <2 x half> <half 64.0, half 64.0>
   %mul = fmul <2 x half> %x, %select.pow2
@@ -5812,37 +7199,65 @@ define <2 x half> @v_mul_v2f16_select_n128_n64(<2 x i32> %arg, <2 x half> %x) {
 ; GFX10-GISEL-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: v_mul_v2f16_select_n128_n64:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v3, 0xd800
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0xd400, v3, vcc_lo
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0xd400, v3, vcc_lo
-; GFX11-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_pk_mul_f16 v0, v2, v0
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_mul_v2f16_select_n128_n64:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT:    v_xor_b32_e32 v2, 0x80008000, v2
-; GFX11-GISEL-NEXT:    v_mov_b32_e32 v3, 0x7fff
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-GISEL-NEXT:    v_add_nc_u32_e32 v0, 6, v0
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-GISEL-NEXT:    v_med3_i32 v0, 0xffff8000, v0, v3
-; GFX11-GISEL-NEXT:    v_add_nc_u32_e32 v1, 6, v1
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v2, v0
-; GFX11-GISEL-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v3
-; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v1, v4, v1
-; GFX11-GISEL-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: v_mul_v2f16_select_n128_n64:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0xd800
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e64 s0, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0xd400, v3.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0xd400, v3.l, s0
+; GFX11-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_mul_f16 v0, v2, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_v2f16_select_n128_n64:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v3, 0xd800
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0xd400, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0xd400, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_mul_f16 v0, v2, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_v2f16_select_n128_n64:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_xor_b32_e32 v2, 0x80008000, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_dual_mov_b32 v3, 0x7fff :: v_dual_add_nc_u32 v0, 6, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX11-GISEL-TRUE16-NEXT:    v_add_nc_u32_e32 v1, 6, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v2.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v3
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.h, v2.h, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_v2f16_select_n128_n64:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_xor_b32_e32 v2, 0x80008000, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v3, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_add_nc_u32_e32 v0, 6, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_add_nc_u32_e32 v1, 6, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v2, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v1, v4, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq <2 x i32> %arg, zeroinitializer
   %select.pow2 = select <2 x i1> %cond, <2 x half> <half -128.0, half -128.0>, <2 x half> <half -64.0, half -64.0>
   %mul = fmul <2 x half> %x, %select.pow2
@@ -5902,32 +7317,56 @@ define <2 x half> @v_mul_v2f16_select_n128_n16(<2 x i32> %arg, <2 x half> %x) {
 ; GFX10-GISEL-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: v_mul_v2f16_select_n128_n16:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v3, 0xd800
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0xcc00, v3, vcc_lo
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0xcc00, v3, vcc_lo
-; GFX11-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_pk_mul_f16 v0, v2, v0
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_mul_v2f16_select_n128_n16:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT:    v_xor_b32_e32 v2, 0x80008000, v2
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v0, 4, 7, vcc_lo
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v2, v0
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v1, 4, 7, vcc_lo
-; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v1, v3, v1
-; GFX11-GISEL-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: v_mul_v2f16_select_n128_n16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0xd800
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e64 s0, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0xcc00, v3.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0xcc00, v3.l, s0
+; GFX11-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_mul_f16 v0, v2, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_mul_v2f16_select_n128_n16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v3, 0xd800
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0xcc00, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0xcc00, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_mul_f16 v0, v2, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_mul_v2f16_select_n128_n16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_xor_b32_e32 v2, 0x80008000, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 4, 7, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v2.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 4, 7, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.h, v2.h, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_mul_v2f16_select_n128_n16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_xor_b32_e32 v2, 0x80008000, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 4, 7, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v2, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 4, 7, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v1, v3, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq <2 x i32> %arg, zeroinitializer
   %select.pow2 = select <2 x i1> %cond, <2 x half> <half -128.0, half -128.0>, <2 x half> <half -16.0, half -16.0>
   %mul = fmul <2 x half> %x, %select.pow2
@@ -5987,32 +7426,56 @@ define <2 x half> @v_contract_mul_add_v2f16_select_64_1(<2 x i32> %arg, <2 x hal
 ; GFX10-GISEL-NEXT:    v_pk_add_f16 v0, v0, v3
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: v_contract_mul_add_v2f16_select_64_1:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v4, 0x5400
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0x3c00, v4, vcc_lo
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0x3c00, v4, vcc_lo
-; GFX11-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_pk_fma_f16 v0, v2, v0, v3
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_contract_mul_add_v2f16_select_64_1:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 6, vcc_lo
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v2, v0
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, 6, vcc_lo
-; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v1, v4, v1
-; GFX11-GISEL-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-GISEL-NEXT:    v_pk_add_f16 v0, v0, v3
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: v_contract_mul_add_v2f16_select_64_1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v4.l, 0x5400
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e64 s0, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x3c00, v4.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0x3c00, v4.l, s0
+; GFX11-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_fma_f16 v0, v2, v0, v3
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_contract_mul_add_v2f16_select_64_1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v4, 0x5400
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x3c00, v4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x3c00, v4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_fma_f16 v0, v2, v0, v3
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_contract_mul_add_v2f16_select_64_1:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 6, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v2.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, 6, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.h, v2.h, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_pk_add_f16 v0, v0, v3
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_v2f16_select_64_1:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 6, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v2, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 6, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v1, v4, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_pk_add_f16 v0, v0, v3
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq <2 x i32> %arg, zeroinitializer
   %select.pow2 = select <2 x i1> %cond, <2 x half> <half 64.0, half 64.0>, <2 x half> <half 1.0, half 1.0>
   %mul = fmul contract <2 x half> %x, %select.pow2
@@ -6073,32 +7536,56 @@ define <2 x half> @v_contract_mul_add_v2f16_select_1_64(<2 x i32> %arg, <2 x hal
 ; GFX10-GISEL-NEXT:    v_pk_add_f16 v0, v0, v3
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: v_contract_mul_add_v2f16_select_1_64:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v4, 0x3c00
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0x5400, v4, vcc_lo
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0x5400, v4, vcc_lo
-; GFX11-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_pk_fma_f16 v0, v2, v0, v3
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_contract_mul_add_v2f16_select_1_64:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v2, v0
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v1, 6, 0, vcc_lo
-; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v1, v4, v1
-; GFX11-GISEL-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-GISEL-NEXT:    v_pk_add_f16 v0, v0, v3
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: v_contract_mul_add_v2f16_select_1_64:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v4.l, 0x3c00
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e64 s0, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x5400, v4.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0x5400, v4.l, s0
+; GFX11-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_fma_f16 v0, v2, v0, v3
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_contract_mul_add_v2f16_select_1_64:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v4, 0x3c00
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x5400, v4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x5400, v4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_fma_f16 v0, v2, v0, v3
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_contract_mul_add_v2f16_select_1_64:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v2.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 6, 0, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.h, v2.h, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_pk_add_f16 v0, v0, v3
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_v2f16_select_1_64:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v2, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 6, 0, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v1, v4, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_pk_add_f16 v0, v0, v3
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq <2 x i32> %arg, zeroinitializer
   %select.pow2 = select <2 x i1> %cond, <2 x half> <half 1.0, half 1.0>, <2 x half> <half 64.0, half 64.0>
   %mul = fmul contract <2 x half> %x, %select.pow2
@@ -6161,33 +7648,58 @@ define <2 x half> @v_contract_mul_add_v2f16_select_n64_n1(<2 x i32> %arg, <2 x h
 ; GFX10-GISEL-NEXT:    v_pk_add_f16 v0, v0, v3
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: v_contract_mul_add_v2f16_select_n64_n1:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v4, 0xd400
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0xbc00, v4, vcc_lo
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0xbc00, v4, vcc_lo
-; GFX11-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_pk_fma_f16 v0, v2, v0, v3
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_contract_mul_add_v2f16_select_n64_n1:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT:    v_xor_b32_e32 v2, 0x80008000, v2
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 6, vcc_lo
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v2, v0
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, 6, vcc_lo
-; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v1, v4, v1
-; GFX11-GISEL-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-GISEL-NEXT:    v_pk_add_f16 v0, v0, v3
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: v_contract_mul_add_v2f16_select_n64_n1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v4.l, 0xd400
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e64 s0, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0xbc00, v4.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0xbc00, v4.l, s0
+; GFX11-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_fma_f16 v0, v2, v0, v3
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_contract_mul_add_v2f16_select_n64_n1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v4, 0xd400
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0xbc00, v4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0xbc00, v4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_fma_f16 v0, v2, v0, v3
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_contract_mul_add_v2f16_select_n64_n1:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_xor_b32_e32 v2, 0x80008000, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 6, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v2.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, 6, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.h, v2.h, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_pk_add_f16 v0, v0, v3
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_v2f16_select_n64_n1:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_xor_b32_e32 v2, 0x80008000, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 6, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v2, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 6, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v1, v4, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_pk_add_f16 v0, v0, v3
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq <2 x i32> %arg, zeroinitializer
   %select.pow2 = select <2 x i1> %cond, <2 x half> <half -64.0, half -64.0>, <2 x half> <half -1.0, half -1.0>
   %mul = fmul contract <2 x half> %x, %select.pow2
@@ -6250,33 +7762,58 @@ define <2 x half> @v_contract_mul_add_v2f16_select_n1_n64(<2 x i32> %arg, <2 x h
 ; GFX10-GISEL-NEXT:    v_pk_add_f16 v0, v0, v3
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: v_contract_mul_add_v2f16_select_n1_n64:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v4, 0xbc00
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0xd400, v4, vcc_lo
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0xd400, v4, vcc_lo
-; GFX11-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_pk_fma_f16 v0, v2, v0, v3
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_contract_mul_add_v2f16_select_n1_n64:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT:    v_xor_b32_e32 v2, 0x80008000, v2
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v2, v0
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v1, 6, 0, vcc_lo
-; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v1, v4, v1
-; GFX11-GISEL-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-GISEL-NEXT:    v_pk_add_f16 v0, v0, v3
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: v_contract_mul_add_v2f16_select_n1_n64:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v4.l, 0xbc00
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e64 s0, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0xd400, v4.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0xd400, v4.l, s0
+; GFX11-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_fma_f16 v0, v2, v0, v3
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_contract_mul_add_v2f16_select_n1_n64:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v4, 0xbc00
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0xd400, v4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0xd400, v4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_fma_f16 v0, v2, v0, v3
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_contract_mul_add_v2f16_select_n1_n64:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_xor_b32_e32 v2, 0x80008000, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v2.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 6, 0, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.h, v2.h, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_pk_add_f16 v0, v0, v3
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_v2f16_select_n1_n64:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_xor_b32_e32 v2, 0x80008000, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 6, 0, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v2, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 6, 0, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v1, v4, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_pk_add_f16 v0, v0, v3
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq <2 x i32> %arg, zeroinitializer
   %select.pow2 = select <2 x i1> %cond, <2 x half> <half -1.0, half -1.0>, <2 x half> <half -64.0, half -64.0>
   %mul = fmul contract <2 x half> %x, %select.pow2
@@ -6348,36 +7885,64 @@ define <2 x half> @v_contract_mul_add_v2f16_select_128_64(<2 x i32> %arg, <2 x h
 ; GFX10-GISEL-NEXT:    v_pk_add_f16 v0, v0, v3
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: v_contract_mul_add_v2f16_select_128_64:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v4, 0x5800
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0x5400, v4, vcc_lo
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0x5400, v4, vcc_lo
-; GFX11-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_pk_fma_f16 v0, v2, v0, v3
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_contract_mul_add_v2f16_select_128_64:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-NEXT:    v_add_nc_u32_e32 v0, 6, v0
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-GISEL-NEXT:    v_dual_mov_b32 v4, 0x7fff :: v_dual_add_nc_u32 v1, 6, v1
-; GFX11-GISEL-NEXT:    v_med3_i32 v0, 0xffff8000, v0, v4
-; GFX11-GISEL-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v4
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v2, v0
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v1, v5, v1
-; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-GISEL-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-GISEL-NEXT:    v_pk_add_f16 v0, v0, v3
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: v_contract_mul_add_v2f16_select_128_64:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v4.l, 0x5800
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e64 s0, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x5400, v4.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0x5400, v4.l, s0
+; GFX11-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_fma_f16 v0, v2, v0, v3
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_contract_mul_add_v2f16_select_128_64:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v4, 0x5800
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x5400, v4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x5400, v4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_fma_f16 v0, v2, v0, v3
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_contract_mul_add_v2f16_select_128_64:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_add_nc_u32_e32 v0, 6, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_dual_mov_b32 v4, 0x7fff :: v_dual_add_nc_u32 v1, 6, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_med3_i32 v0, 0xffff8000, v0, v4
+; GFX11-GISEL-TRUE16-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v4
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v2.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.h, v2.h, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_pk_add_f16 v0, v0, v3
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_v2f16_select_128_64:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_add_nc_u32_e32 v0, 6, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v4, 0x7fff :: v_dual_add_nc_u32 v1, 6, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_med3_i32 v0, 0xffff8000, v0, v4
+; GFX11-GISEL-FAKE16-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v4
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v2, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v1, v5, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_pk_add_f16 v0, v0, v3
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq <2 x i32> %arg, zeroinitializer
   %select.pow2 = select <2 x i1> %cond, <2 x half> <half 128.0, half 128.0>, <2 x half> <half 64.0, half 64.0>
   %mul = fmul contract <2 x half> %x, %select.pow2
@@ -6438,32 +8003,56 @@ define <2 x half> @v_contract_mul_add_v2f16_select_128_4(<2 x i32> %arg, <2 x ha
 ; GFX10-GISEL-NEXT:    v_pk_add_f16 v0, v0, v3
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: v_contract_mul_add_v2f16_select_128_4:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v4, 0x5800
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0x4400, v4, vcc_lo
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0x4400, v4, vcc_lo
-; GFX11-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_pk_fma_f16 v0, v2, v0, v3
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_contract_mul_add_v2f16_select_128_4:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v0, 2, 7, vcc_lo
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v2, v0
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v1, 2, 7, vcc_lo
-; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v1, v4, v1
-; GFX11-GISEL-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-GISEL-NEXT:    v_pk_add_f16 v0, v0, v3
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: v_contract_mul_add_v2f16_select_128_4:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v4.l, 0x5800
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e64 s0, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x4400, v4.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0x4400, v4.l, s0
+; GFX11-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_fma_f16 v0, v2, v0, v3
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_contract_mul_add_v2f16_select_128_4:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v4, 0x5800
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x4400, v4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x4400, v4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_fma_f16 v0, v2, v0, v3
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_contract_mul_add_v2f16_select_128_4:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 2, 7, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v2.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 2, 7, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.h, v2.h, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_pk_add_f16 v0, v0, v3
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_v2f16_select_128_4:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 2, 7, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v2, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 2, 7, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v1, v4, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_pk_add_f16 v0, v0, v3
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq <2 x i32> %arg, zeroinitializer
   %select.pow2 = select <2 x i1> %cond, <2 x half> <half 128.0, half 128.0>, <2 x half> <half 4.0, half 4.0>
   %mul = fmul contract <2 x half> %x, %select.pow2
@@ -6535,36 +8124,64 @@ define <2 x half> @v_contract_mul_add_v2f16_select_2_4(<2 x i32> %arg, <2 x half
 ; GFX10-GISEL-NEXT:    v_pk_add_f16 v0, v0, v3
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: v_contract_mul_add_v2f16_select_2_4:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v4, 0x4000
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0x4400, v4, vcc_lo
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0x4400, v4, vcc_lo
-; GFX11-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_pk_fma_f16 v0, v2, v0, v3
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_contract_mul_add_v2f16_select_2_4:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-NEXT:    v_add_nc_u32_e32 v0, 2, v0
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX11-GISEL-NEXT:    v_dual_mov_b32 v4, 0x7fff :: v_dual_add_nc_u32 v1, 2, v1
-; GFX11-GISEL-NEXT:    v_med3_i32 v0, 0xffff8000, v0, v4
-; GFX11-GISEL-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v4
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v2, v0
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v1, v5, v1
-; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-GISEL-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-GISEL-NEXT:    v_pk_add_f16 v0, v0, v3
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: v_contract_mul_add_v2f16_select_2_4:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v4.l, 0x4000
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e64 s0, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x4400, v4.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0x4400, v4.l, s0
+; GFX11-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_fma_f16 v0, v2, v0, v3
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_contract_mul_add_v2f16_select_2_4:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v4, 0x4000
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x4400, v4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x4400, v4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_fma_f16 v0, v2, v0, v3
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_contract_mul_add_v2f16_select_2_4:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_add_nc_u32_e32 v0, 2, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_dual_mov_b32 v4, 0x7fff :: v_dual_add_nc_u32 v1, 2, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_med3_i32 v0, 0xffff8000, v0, v4
+; GFX11-GISEL-TRUE16-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v4
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v2.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.h, v2.h, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_pk_add_f16 v0, v0, v3
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_v2f16_select_2_4:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_add_nc_u32_e32 v0, 2, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v4, 0x7fff :: v_dual_add_nc_u32 v1, 2, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_med3_i32 v0, 0xffff8000, v0, v4
+; GFX11-GISEL-FAKE16-NEXT:    v_med3_i32 v1, 0xffff8000, v1, v4
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v2, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v1, v5, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_pk_add_f16 v0, v0, v3
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq <2 x i32> %arg, zeroinitializer
   %select.pow2 = select <2 x i1> %cond, <2 x half> <half 2.0, half 2.0>, <2 x half> <half 4.0, half 4.0>
   %mul = fmul contract <2 x half> %x, %select.pow2
@@ -6625,32 +8242,56 @@ define <2 x half> @v_contract_mul_add_v2f16_select_4_128(<2 x i32> %arg, <2 x ha
 ; GFX10-GISEL-NEXT:    v_pk_add_f16 v0, v0, v3
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: v_contract_mul_add_v2f16_select_4_128:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v4, 0x4400
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0x5800, v4, vcc_lo
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0x5800, v4, vcc_lo
-; GFX11-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_pk_fma_f16 v0, v2, v0, v3
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: v_contract_mul_add_v2f16_select_4_128:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v0, 7, 2, vcc_lo
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v0, v2, v0
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v1, 7, 2, vcc_lo
-; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-GISEL-NEXT:    v_ldexp_f16_e32 v1, v4, v1
-; GFX11-GISEL-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-GISEL-NEXT:    v_pk_add_f16 v0, v0, v3
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: v_contract_mul_add_v2f16_select_4_128:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v4.l, 0x4400
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e64 s0, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x5800, v4.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.h, 0x5800, v4.l, s0
+; GFX11-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_fma_f16 v0, v2, v0, v3
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_contract_mul_add_v2f16_select_4_128:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v4, 0x4400
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x5800, v4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x5800, v4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_fma_f16 v0, v2, v0, v3
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_contract_mul_add_v2f16_select_4_128:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 7, 2, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, v2.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 7, 2, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT:    v_ldexp_f16_e32 v0.h, v2.h, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_pk_add_f16 v0, v0, v3
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_v2f16_select_4_128:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 7, 2, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v0, v2, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 7, 2, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_ldexp_f16_e32 v1, v4, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_pk_add_f16 v0, v0, v3
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cond = icmp eq <2 x i32> %arg, zeroinitializer
   %select.pow2 = select <2 x i1> %cond, <2 x half> <half 4.0, half 4.0>, <2 x half> <half 128.0, half 128.0>
   %mul = fmul contract <2 x half> %x, %select.pow2
@@ -6757,11 +8398,41 @@ define double @v_constrained_fmul_0x1p64_f64(double %x, double %y) #0 {
 }
 
 define half @v_constrained_fmul_32_f16(half %x, half %y) #0 {
-; GCN-LABEL: v_constrained_fmul_32_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mul_f16_e32 v0, 0x5000, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_constrained_fmul_32_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mul_f16_e32 v0, 0x5000, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_constrained_fmul_32_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_mul_f16_e32 v0, 0x5000, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: v_constrained_fmul_32_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x5000, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: v_constrained_fmul_32_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x5000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: v_constrained_fmul_32_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x5000, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: v_constrained_fmul_32_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x5000, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val = call half @llvm.experimental.constrained.fmul.f16(half %x, half 32.0, metadata !"round.dynamic", metadata !"fpexcept.strict")
   ret half %val
 }
diff --git a/llvm/test/CodeGen/AMDGPU/fnearbyint.ll b/llvm/test/CodeGen/AMDGPU/fnearbyint.ll
index fe5601594dca8..e9fd6119d0c36 100644
--- a/llvm/test/CodeGen/AMDGPU/fnearbyint.ll
+++ b/llvm/test/CodeGen/AMDGPU/fnearbyint.ll
@@ -2,7 +2,8 @@
 ; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=SICI,SI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=SICI,CI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=VI %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 declare half @llvm.nearbyint.f16(half) #0
 declare float @llvm.nearbyint.f32(float) #0
@@ -51,16 +52,27 @@ define amdgpu_kernel void @fnearbyint_f16(ptr addrspace(1) %out, half %in) #1 {
 ; VI-NEXT:    flat_store_short v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: fnearbyint_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_rndne_f16_e32 v1, s2
-; GFX11-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: fnearbyint_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    s_load_b32 s2, s[4:5], 0x2c
+; GFX11-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_rndne_f16_e32 v0.l, s2
+; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: fnearbyint_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    s_load_b32 s2, s[4:5], 0x2c
+; GFX11-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_rndne_f16_e32 v1, s2
+; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %1 = call half @llvm.nearbyint.f16(half %in)
   store half %1, ptr addrspace(1) %out
   ret void
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-fabs-r600.ll b/llvm/test/CodeGen/AMDGPU/fneg-fabs-r600.ll
index 4f5271ed23252..caf7a845759fc 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-fabs-r600.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-fabs-r600.ll
@@ -176,5 +176,3 @@ declare float @llvm.fabs.f32(float) readnone
 declare <2 x float> @llvm.fabs.v2f32(<2 x float>) readnone
 declare <4 x float> @llvm.fabs.v4f32(<4 x float>) readnone
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-fabs.ll b/llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
index 17e509acfb6e6..1fa9bfa3cfa3f 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
@@ -276,7 +276,5 @@ declare float @llvm.fabs.f32(float) readnone
 declare <2 x float> @llvm.fabs.v2f32(<2 x float>) readnone
 declare <4 x float> @llvm.fabs.v4f32(<4 x float>) readnone
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; FUNC: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll b/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
index 058c273a65d99..ff894d184e6c4 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
@@ -1,7 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,GFX7 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define i32 @fneg_xor_select_i32(i1 %cond, i32 %arg0, i32 %arg1) {
 ; GCN-LABEL: fneg_xor_select_i32:
@@ -158,15 +159,25 @@ define i16 @fneg_xor_select_i16(i1 %cond, i16 %arg0, i16 %arg1) {
 ; GCN-NEXT:    v_xor_b32_e32 v0, 0xffff8000, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fneg_xor_select_i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc_lo
-; GFX11-NEXT:    v_xor_b32_e32 v0, 0xffff8000, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fneg_xor_select_i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fneg_xor_select_i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc_lo
+; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v0, 0xffff8000, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %select = select i1 %cond, i16 %arg0, i16 %arg1
   %fneg = xor i16 %select, -32768
   ret i16 %fneg
@@ -206,22 +217,36 @@ define <2 x i16> @fneg_xor_select_v2i16(<2 x i1> %cond, <2 x i16> %arg0, <2 x i1
 ; GFX9-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fneg_xor_select_v2i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 16, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11-NEXT:    v_dual_cndmask_b32 v0, v3, v2 :: v_dual_and_b32 v1, 1, v1
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v5, v4, vcc_lo
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fneg_xor_select_v2i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 1, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u32_e64 s0, 1, v1
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v3.l, v2.l, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v3.h, v2.h, s0
+; GFX11-TRUE16-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fneg_xor_select_v2i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v3, v2 :: v_dual_and_b32 v1, 1, v1
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v5, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %select = select <2 x i1> %cond, <2 x i16> %arg0, <2 x i16> %arg1
   %fneg = xor <2 x i16> %select, <i16 -32768, i16 -32768>
   ret <2 x i16> %fneg
@@ -250,16 +275,27 @@ define i16 @fneg_xor_select_i16_multi_use(i1 %cond, i16 %arg0, i16 %arg1, ptr ad
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fneg_xor_select_i16_multi_use:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
-; GFX11-NEXT:    v_xor_b32_e32 v0, 0xffff8000, v1
-; GFX11-NEXT:    global_store_b16 v[3:4], v1, off
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fneg_xor_select_i16_multi_use:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v2.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.h
+; GFX11-TRUE16-NEXT:    global_store_d16_hi_b16 v[3:4], v0, off
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fneg_xor_select_i16_multi_use:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v0, 0xffff8000, v1
+; GFX11-FAKE16-NEXT:    global_store_b16 v[3:4], v1, off
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %select = select i1 %cond, i16 %arg0, i16 %arg1
   store i16 %select, ptr addrspace(1) %ptr
   %fneg = xor i16 %select, -32768
@@ -578,21 +614,37 @@ define half @select_fneg_select_f16(i1 %cond0, i1 %cond1, half %arg0, half %arg1
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: select_fneg_select_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX11-NEXT:    v_xor_b32_e32 v2, 0x8000, v2
-; GFX11-NEXT:    v_and_b32_e32 v1, 1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX11-NEXT:    v_xor_b32_e32 v2, 0x8000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: select_fneg_select_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 1, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v2.l
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-TRUE16-NEXT:    v_xor_b16 v0.h, 0x8000, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: select_fneg_select_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v2, 0x8000, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v2, 0x8000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %fneg0 = fneg half %arg0
   %select0 = select i1 %cond0, half %arg1, half %fneg0
   %fneg1 = fneg half %select0
@@ -614,21 +666,37 @@ define i16 @select_fneg_xor_select_i16(i1 %cond0, i1 %cond1, i16 %arg0, i16 %arg
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: select_fneg_xor_select_i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX11-NEXT:    v_xor_b32_e32 v2, 0xffff8000, v2
-; GFX11-NEXT:    v_and_b32_e32 v1, 1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX11-NEXT:    v_xor_b32_e32 v2, 0xffff8000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: select_fneg_xor_select_i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 1, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v2.l
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-TRUE16-NEXT:    v_xor_b16 v0.h, 0x8000, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: select_fneg_xor_select_i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v2, 0xffff8000, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v2, 0xffff8000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %fneg0 = xor i16 %arg0, -32768
   %select0 = select i1 %cond0, i16 %arg1, i16 %fneg0
   %fneg1 = xor i16 %select0, -32768
@@ -699,33 +767,56 @@ define <2 x half> @select_fneg_select_v2f16(<2 x i1> %cond0, <2 x i1> %cond1, <2
 ; GFX9-NEXT:    v_perm_b32 v0, v1, v0, s4
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: select_fneg_select_v2f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_xor_b32_e32 v4, 0x80008000, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v3, 1, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc_lo
-; GFX11-NEXT:    v_and_b32_e32 v1, 1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v7, v6, vcc_lo
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v3
-; GFX11-NEXT:    v_perm_b32 v4, v1, v0, 0x5040100
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_xor_b32_e32 v4, 0x80008000, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 16, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_cndmask_b32 v1, v1, v5 :: v_dual_and_b32 v2, 1, v2
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: select_fneg_select_v2f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 1, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX11-TRUE16-NEXT:    v_xor_b32_e32 v4, 0x80008000, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 1, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u32_e64 s0, 1, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 1, v3
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v4.h, v5.h, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v4.l, v5.l, s0
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u32_e64 s0, 1, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_xor_b32_e32 v0, 0x80008000, v1
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: select_fneg_select_v2f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v4, 0x80008000, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 1, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc_lo
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v7, v6, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v3
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v4, 0x80008000, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v1, v5 :: v_dual_and_b32 v2, 1, v2
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %fneg0 = fneg <2 x half> %arg0
   %select0 = select <2 x i1> %cond0, <2 x half> %arg1, <2 x half> %fneg0
   %fneg1 = fneg <2 x half> %select0
@@ -784,33 +875,56 @@ define <2 x i16> @select_fneg_xor_select_v2i16(<2 x i1> %cond0, <2 x i1> %cond1,
 ; GFX9-NEXT:    v_perm_b32 v0, v1, v0, s4
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: select_fneg_xor_select_v2i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_xor_b32_e32 v4, 0x80008000, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v3, 1, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v0, 1, v0
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc_lo
-; GFX11-NEXT:    v_and_b32_e32 v1, 1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v7, v6, vcc_lo
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v3
-; GFX11-NEXT:    v_perm_b32 v4, v1, v0, 0x5040100
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_xor_b32_e32 v4, 0x80008000, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 16, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_cndmask_b32 v1, v1, v5 :: v_dual_and_b32 v2, 1, v2
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: select_fneg_xor_select_v2i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 1, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX11-TRUE16-NEXT:    v_xor_b32_e32 v4, 0x80008000, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 1, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u32_e64 s0, 1, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 1, v3
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v4.h, v5.h, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v4.l, v5.l, s0
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u32_e64 s0, 1, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_xor_b32_e32 v0, 0x80008000, v1
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: select_fneg_xor_select_v2i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v4, 0x80008000, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 1, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc_lo
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v7, v6, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v3
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v4, 0x80008000, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v1, v5 :: v_dual_and_b32 v2, 1, v2
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %fneg0 = xor <2 x i16> %arg0, <i16 -32768, i16 -32768>
   %select0 = select <2 x i1> %cond0, <2 x i16> %arg1, <2 x i16> %fneg0
   %fneg1 = xor <2 x i16> %select0, <i16 -32768, i16 -32768>
@@ -931,20 +1045,33 @@ define float @cospiD_pattern0_half(i16 %arg, float %arg1, float %arg2) {
 ; GFX9-NEXT:    v_perm_b32 v0, v0, v1, s4
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: cospiD_pattern0_half:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v3, 1, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc_lo
-; GFX11-NEXT:    v_cmp_lt_i16_e32 vcc_lo, 1, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 0xffff8000, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_xor_b32_e32 v0, v2, v0
-; GFX11-NEXT:    v_perm_b32 v0, v0, v1, 0x5040100
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: cospiD_pattern0_half:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, v0.l, 1
+; GFX11-TRUE16-NEXT:    v_cmp_lt_i16_e32 vcc_lo, 1, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0, v0.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, v1, v2, s0
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0, 0x8000, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_xor_b16 v0.h, v0.h, v1.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: cospiD_pattern0_half:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 1, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v3
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_lt_i16_e32 vcc_lo, 1, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 0xffff8000, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %i = and i16 %arg, 1
   %i3 = icmp eq i16 %i, 0
   %i4 = select i1 %i3, float %arg2, float %arg1
@@ -980,16 +1107,27 @@ define float @cospiD_pattern1_half(i16 %arg, float %arg1, float %arg2) {
 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, v1, -v1, vcc
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: cospiD_pattern1_half:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v3, 1, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc_lo
-; GFX11-NEXT:    v_cmp_lt_i16_e32 vcc_lo, 1, v0
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, v1, -v1, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: cospiD_pattern1_half:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, v0.l, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v0.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_lt_i16_e32 vcc_lo, 1, v0.l
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, v1, -v1, vcc_lo
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: cospiD_pattern1_half:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 1, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v3
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_lt_i16_e32 vcc_lo, 1, v0
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, v1, -v1, vcc_lo
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %i = and i16 %arg, 1
   %i3 = icmp eq i16 %i, 0
   %i4 = select i1 %i3, float %arg2, float %arg1
@@ -1170,14 +1308,23 @@ define double @fneg_f64_bitcast_build_vector_v4i16_to_f64(i16 %elt0, i16 %elt1,
 ; GFX9-NEXT:    v_xor_b32_e32 v1, 0x80000000, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fneg_f64_bitcast_build_vector_v4i16_to_f64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_xor_b32_e32 v1, 0x80000000, v2
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fneg_f64_bitcast_build_vector_v4i16_to_f64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_xor_b32_e32 v1, 0x80000000, v2
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fneg_f64_bitcast_build_vector_v4i16_to_f64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v1, 0x80000000, v2
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %insert.0 = insertelement <4 x i16> poison, i16 %elt0, i32 0
   %insert.1 = insertelement <4 x i16> %insert.0, i16 %elt1, i32 1
   %insert.2 = insertelement <4 x i16> %insert.1, i16 %elt2, i32 2
@@ -1211,14 +1358,23 @@ define double @fneg_f64_bitcast_build_vector_v4f16_to_f64(half %elt0, half %elt1
 ; GFX9-NEXT:    v_xor_b32_e32 v1, 0x80000000, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fneg_f64_bitcast_build_vector_v4f16_to_f64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_xor_b32_e32 v1, 0x80000000, v2
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fneg_f64_bitcast_build_vector_v4f16_to_f64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_xor_b32_e32 v1, 0x80000000, v2
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fneg_f64_bitcast_build_vector_v4f16_to_f64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v1, 0x80000000, v2
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %insert.0 = insertelement <4 x half> poison, half %elt0, i32 0
   %insert.1 = insertelement <4 x half> %insert.0, half %elt1, i32 1
   %insert.2 = insertelement <4 x half> %insert.1, half %elt2, i32 2
@@ -1252,14 +1408,23 @@ define double @fneg_f64_bitcast_build_vector_v4bf16_to_f64(bfloat %elt0, bfloat
 ; GFX9-NEXT:    v_xor_b32_e32 v1, 0x80000000, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fneg_f64_bitcast_build_vector_v4bf16_to_f64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_xor_b32_e32 v1, 0x80000000, v2
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fneg_f64_bitcast_build_vector_v4bf16_to_f64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_xor_b32_e32 v1, 0x80000000, v2
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fneg_f64_bitcast_build_vector_v4bf16_to_f64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v1, 0x80000000, v2
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %insert.0 = insertelement <4 x bfloat> poison, bfloat %elt0, i32 0
   %insert.1 = insertelement <4 x bfloat> %insert.0, bfloat %elt1, i32 1
   %insert.2 = insertelement <4 x bfloat> %insert.1, bfloat %elt2, i32 2
diff --git a/llvm/test/CodeGen/AMDGPU/fneg.ll b/llvm/test/CodeGen/AMDGPU/fneg.ll
index 87f1303ab8f5d..07a7d8d20c439 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg.ll
@@ -1,7 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX11,GFX11-FAKE16 %s
 ; RUN: not llc -mtriple=r600 -mcpu=redwood < %s
 
 define amdgpu_kernel void @s_fneg_f32(ptr addrspace(1) %out, float %in) {
@@ -516,11 +517,29 @@ define double @v_fneg_i64_fp_use(i64 %in) {
 }
 
 define i16 @v_fneg_i16(i16 %in) {
-; GCN-LABEL: v_fneg_i16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_xor_b32_e32 v0, 0xffff8000, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; SI-LABEL: v_fneg_i16:
+; SI:       ; %bb.0:
+; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT:    v_xor_b32_e32 v0, 0xffff8000, v0
+; SI-NEXT:    s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_fneg_i16:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_xor_b32_e32 v0, 0xffff8000, v0
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: v_fneg_i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_fneg_i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v0, 0xffff8000, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %fneg = xor i16 %in, -32768
   ret i16 %fneg
 }
@@ -551,16 +570,27 @@ define amdgpu_kernel void @s_fneg_i16_fp_use(ptr addrspace(1) %out, i16 %in) {
 ; VI-NEXT:    flat_store_short v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: s_fneg_i16_fp_use:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_sub_f16_e64 v1, 2.0, s2
-; GFX11-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: s_fneg_i16_fp_use:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    s_load_b32 s2, s[4:5], 0x2c
+; GFX11-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_sub_f16_e64 v0.l, 2.0, s2
+; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: s_fneg_i16_fp_use:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    s_load_b32 s2, s[4:5], 0x2c
+; GFX11-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_sub_f16_e64 v1, 2.0, s2
+; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %fneg = xor i16 %in, -32768
   %bitcast = bitcast i16 %fneg to half
   %fadd = fadd half %bitcast, 2.0
@@ -582,11 +612,17 @@ define half @v_fneg_i16_fp_use(i16 %in) {
 ; VI-NEXT:    v_sub_f16_e32 v0, 2.0, v0
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_fneg_i16_fp_use:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_sub_f16_e32 v0, 2.0, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_fneg_i16_fp_use:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_sub_f16_e32 v0.l, 2.0, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_fneg_i16_fp_use:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_sub_f16_e32 v0, 2.0, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %fneg = xor i16 %in, -32768
   %bitcast = bitcast i16 %fneg to half
   %fadd = fadd half %bitcast, 2.0
diff --git a/llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll b/llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
index 2af12d150154a..63ba18a5433aa 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
@@ -1,7 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN:  llc -amdgpu-scalarize-global-loads=false  -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=VI %s
 ; RUN:  llc -amdgpu-scalarize-global-loads=false  -mtriple=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s
-; RUN:  llc -amdgpu-scalarize-global-loads=false  -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN:  llc -amdgpu-scalarize-global-loads=false  -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN:  llc -amdgpu-scalarize-global-loads=false  -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 declare i16 @llvm.umax.i16(i16, i16)
 declare i64 @llvm.umin.i64(i64, i64)
@@ -208,39 +209,70 @@ define <8 x half> @fmul_pow2_8xhalf(<8 x i16> %i) {
 ; GFX10-NEXT:    v_pk_mul_f16 v3, 0x7000, v3 op_sel_hi:[0,1]
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fmul_pow2_8xhalf:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_pk_lshlrev_b16 v3, v3, 1 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_lshlrev_b16 v2, v2, 1 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_lshlrev_b16 v0, v0, 1 op_sel_hi:[1,0]
-; GFX11-NEXT:    v_pk_lshlrev_b16 v1, v1, 1 op_sel_hi:[1,0]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_cvt_f16_u16_e32 v4, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_cvt_f16_u16_e32 v5, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-NEXT:    v_cvt_f16_u16_e32 v1, v1
-; GFX11-NEXT:    v_cvt_f16_u16_e32 v0, v0
-; GFX11-NEXT:    v_cvt_f16_u16_e32 v6, v6
-; GFX11-NEXT:    v_cvt_f16_u16_e32 v7, v7
-; GFX11-NEXT:    v_cvt_f16_u16_e32 v2, v2
-; GFX11-NEXT:    v_cvt_f16_u16_e32 v3, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v6
-; GFX11-NEXT:    v_pack_b32_f16 v1, v1, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_pack_b32_f16 v2, v5, v2
-; GFX11-NEXT:    v_pack_b32_f16 v3, v4, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_pk_mul_f16 v0, 0x7000, v0 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_mul_f16 v1, 0x7000, v1 op_sel_hi:[0,1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_pk_mul_f16 v2, 0x7000, v2 op_sel_hi:[0,1]
-; GFX11-NEXT:    v_pk_mul_f16 v3, 0x7000, v3 op_sel_hi:[0,1]
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fmul_pow2_8xhalf:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_pk_lshlrev_b16 v3, v3, 1 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_lshlrev_b16 v4, v2, 1 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_lshlrev_b16 v2, v1, 1 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    v_pk_lshlrev_b16 v5, v0, 1 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_u16_e32 v0.l, v3.l
+; GFX11-TRUE16-NEXT:    v_cvt_f16_u16_e32 v0.h, v4.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_u16_e32 v1.l, v2.l
+; GFX11-TRUE16-NEXT:    v_cvt_f16_u16_e32 v1.h, v5.l
+; GFX11-TRUE16-NEXT:    v_cvt_f16_u16_e32 v2.l, v5.h
+; GFX11-TRUE16-NEXT:    v_cvt_f16_u16_e32 v2.h, v2.h
+; GFX11-TRUE16-NEXT:    v_cvt_f16_u16_e32 v3.l, v4.h
+; GFX11-TRUE16-NEXT:    v_cvt_f16_u16_e32 v3.h, v3.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v4, v1.h, v2.l
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.l, v2.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v2, v0.h, v3.l
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v3, v0.l, v3.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_pk_mul_f16 v0, 0x7000, v4 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_mul_f16 v1, 0x7000, v1 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_pk_mul_f16 v2, 0x7000, v2 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    v_pk_mul_f16 v3, 0x7000, v3 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fmul_pow2_8xhalf:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_pk_lshlrev_b16 v3, v3, 1 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_lshlrev_b16 v2, v2, 1 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_lshlrev_b16 v0, v0, 1 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    v_pk_lshlrev_b16 v1, v1, 1 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_u16_e32 v4, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_cvt_f16_u16_e32 v5, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f16_u16_e32 v1, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f16_u16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f16_u16_e32 v6, v6
+; GFX11-FAKE16-NEXT:    v_cvt_f16_u16_e32 v7, v7
+; GFX11-FAKE16-NEXT:    v_cvt_f16_u16_e32 v2, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f16_u16_e32 v3, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v6
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v2, v5, v2
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v3, v4, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_pk_mul_f16 v0, 0x7000, v0 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_mul_f16 v1, 0x7000, v1 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_pk_mul_f16 v2, 0x7000, v2 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    v_pk_mul_f16 v3, 0x7000, v3 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %p2 = shl <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, %i
   %p2_f = uitofp <8 x i16> %p2 to <8 x half>
   %r = fmul <8 x half> <half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000>, %p2_f
@@ -284,28 +316,47 @@ define <8 x half> @fmul_pow2_ldexp_8xhalf(<8 x i16> %i) {
 ; GFX10-NEXT:    v_pack_b32_f16 v3, v5, v3
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fmul_pow2_ldexp_8xhalf:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_ldexp_f16_e32 v4, 0x7000, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_ldexp_f16_e32 v5, 0x7000, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-NEXT:    v_ldexp_f16_e32 v1, 0x7000, v1
-; GFX11-NEXT:    v_ldexp_f16_e32 v0, 0x7000, v0
-; GFX11-NEXT:    v_ldexp_f16_e32 v6, 0x7000, v6
-; GFX11-NEXT:    v_ldexp_f16_e32 v7, 0x7000, v7
-; GFX11-NEXT:    v_ldexp_f16_e32 v2, 0x7000, v2
-; GFX11-NEXT:    v_ldexp_f16_e32 v3, 0x7000, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v6
-; GFX11-NEXT:    v_pack_b32_f16 v1, v1, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_pack_b32_f16 v2, v5, v2
-; GFX11-NEXT:    v_pack_b32_f16 v3, v4, v3
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fmul_pow2_ldexp_8xhalf:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_ldexp_f16_e32 v3.l, 0x7000, v3.l
+; GFX11-TRUE16-NEXT:    v_ldexp_f16_e32 v2.l, 0x7000, v2.l
+; GFX11-TRUE16-NEXT:    v_ldexp_f16_e32 v1.l, 0x7000, v1.l
+; GFX11-TRUE16-NEXT:    v_ldexp_f16_e32 v0.l, 0x7000, v0.l
+; GFX11-TRUE16-NEXT:    v_ldexp_f16_e32 v0.h, 0x7000, v0.h
+; GFX11-TRUE16-NEXT:    v_ldexp_f16_e32 v1.h, 0x7000, v1.h
+; GFX11-TRUE16-NEXT:    v_ldexp_f16_e32 v2.h, 0x7000, v2.h
+; GFX11-TRUE16-NEXT:    v_ldexp_f16_e32 v3.h, 0x7000, v3.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.l, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v2, v2.l, v2.h
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v3, v3.l, v3.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fmul_pow2_ldexp_8xhalf:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_ldexp_f16_e32 v4, 0x7000, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_ldexp_f16_e32 v5, 0x7000, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT:    v_ldexp_f16_e32 v1, 0x7000, v1
+; GFX11-FAKE16-NEXT:    v_ldexp_f16_e32 v0, 0x7000, v0
+; GFX11-FAKE16-NEXT:    v_ldexp_f16_e32 v6, 0x7000, v6
+; GFX11-FAKE16-NEXT:    v_ldexp_f16_e32 v7, 0x7000, v7
+; GFX11-FAKE16-NEXT:    v_ldexp_f16_e32 v2, 0x7000, v2
+; GFX11-FAKE16-NEXT:    v_ldexp_f16_e32 v3, 0x7000, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v6
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v2, v5, v2
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v3, v4, v3
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %r = call <8 x half> @llvm.ldexp.v8f16.v8i16(<8 x half> <half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000, half 0xH7000>, <8 x i16> %i)
   ret <8 x half> %r
 }
@@ -590,16 +641,27 @@ define double @fmul_pow_mul_max_pow2(i16 %cnt) nounwind {
 ; GFX10-NEXT:    v_mul_f64 v[0:1], 0x40080000, v[0:1]
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fmul_pow_mul_max_pow2:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b16 v0, v0, 2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_cvt_f64_u32_e32 v[0:1], v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f64 v[0:1], 0x40080000, v[0:1]
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fmul_pow_mul_max_pow2:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.l, v0.l, 2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_cvt_f64_u32_e32 v[0:1], v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mul_f64 v[0:1], 0x40080000, v[0:1]
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fmul_pow_mul_max_pow2:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v0, v0, 2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f64_u32_e32 v[0:1], v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mul_f64 v[0:1], 0x40080000, v[0:1]
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %shl2 = shl nuw i16 2, %cnt
   %shl1 = shl nuw i16 1, %cnt
   %shl = call i16 @llvm.umax.i16(i16 %shl1, i16 %shl2)
@@ -1029,18 +1091,30 @@ define <2 x half> @fmul_pow_shl_cnt_vec_fail_to_large(<2 x i16> %cnt) nounwind {
 ; GFX10-NEXT:    v_pk_mul_f16 v0, 0x4b80, v0 op_sel_hi:[0,1]
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fmul_pow_shl_cnt_vec_fail_to_large:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_pk_lshlrev_b16 v0, v0, 2 op_sel_hi:[1,0]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_cvt_f16_u16_e32 v0, v0
-; GFX11-NEXT:    v_cvt_f16_u16_e32 v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT:    v_pk_mul_f16 v0, 0x4b80, v0 op_sel_hi:[0,1]
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fmul_pow_shl_cnt_vec_fail_to_large:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_pk_lshlrev_b16 v0, v0, 2 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_u16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT:    v_cvt_f16_u16_e32 v0.h, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_pk_mul_f16 v0, 0x4b80, v0 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fmul_pow_shl_cnt_vec_fail_to_large:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_pk_lshlrev_b16 v0, v0, 2 op_sel_hi:[1,0]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f16_u16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f16_u16_e32 v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_pk_mul_f16 v0, 0x4b80, v0 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %shl = shl nsw nuw <2 x i16> <i16 2, i16 2>, %cnt
   %conv = uitofp <2 x i16> %shl to <2 x half>
   %mul = fmul <2 x half> <half 15.000000e+00, half 15.000000e+00>, %conv
@@ -1117,18 +1191,31 @@ define double @fmul_pow_shl_cnt_safe(i16 %cnt) nounwind {
 ; GFX10-NEXT:    v_mul_f64 v[0:1], v[0:1], s[4:5]
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fmul_pow_shl_cnt_safe:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b16 v0, v0, 1
-; GFX11-NEXT:    s_mov_b32 s0, 0xff5f3992
-; GFX11-NEXT:    s_mov_b32 s1, 0x7befffff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_cvt_f64_u32_e32 v[0:1], v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f64 v[0:1], v[0:1], s[0:1]
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fmul_pow_shl_cnt_safe:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.l, v0.l, 1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, 0xff5f3992
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, 0x7befffff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_cvt_f64_u32_e32 v[0:1], v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mul_f64 v[0:1], v[0:1], s[0:1]
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fmul_pow_shl_cnt_safe:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v0, v0, 1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, 0xff5f3992
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, 0x7befffff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f64_u32_e32 v[0:1], v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mul_f64 v[0:1], v[0:1], s[0:1]
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %shl = shl nuw i16 1, %cnt
   %conv = uitofp i16 %shl to double
   %mul = fmul double 9.745314e+288, %conv
@@ -1479,32 +1566,60 @@ define half @fdiv_pow_shl_cnt_fail_out_of_bounds(i32 %cnt) nounwind {
 ; GFX10-NEXT:    v_div_fixup_f16 v0, v1, v0, 0x7000
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fdiv_pow_shl_cnt_fail_out_of_bounds:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b32_e64 v0, v0, 1
-; GFX11-NEXT:    s_mov_b32 s0, 0x46000000
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cvt_f32_u32_e32 v0, v0
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v1, v0
-; GFX11-NEXT:    v_rcp_f32_e32 v1, v1
-; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_mul_f32_e32 v2, 0x46000000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fma_mix_f32 v3, -v0, v2, s0 op_sel_hi:[1,0,0]
-; GFX11-NEXT:    v_fmac_f32_e32 v2, v3, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fma_mix_f32 v3, -v0, v2, s0 op_sel_hi:[1,0,0]
-; GFX11-NEXT:    v_mul_f32_e32 v1, v3, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
-; GFX11-NEXT:    v_add_f32_e32 v1, v1, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX11-NEXT:    v_div_fixup_f16 v0, v1, v0, 0x7000
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fdiv_pow_shl_cnt_fail_out_of_bounds:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e64 v0, v0, 1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, 0x46000000
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_u32_e32 v0, v0
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v0.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l
+; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v1, v1
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v2, 0x46000000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v4, -v3, v2, s0 op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v2, v4, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v3, -v3, v2, s0 op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v1, v3, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v1
+; GFX11-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.h, v0.l, 0x7000
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fdiv_pow_shl_cnt_fail_out_of_bounds:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e64 v0, v0, 1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, 0x46000000
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_u32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v1, v0
+; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v2, 0x46000000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v3, -v0, v2, s0 op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v2, v3, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v3, -v0, v2, s0 op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT:    v_div_fixup_f16 v0, v1, v0, 0x7000
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %shl = shl nuw i32 1, %cnt
   %conv = uitofp i32 %shl to half
   %mul = fdiv half 0xH7000, %conv
@@ -1526,13 +1641,21 @@ define half @fdiv_pow_shl_cnt_in_bounds(i16 %cnt) nounwind {
 ; GFX10-NEXT:    v_sub_nc_u16 v0, 0x7000, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fdiv_pow_shl_cnt_in_bounds:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b16 v0, 10, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_sub_nc_u16 v0, 0x7000, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fdiv_pow_shl_cnt_in_bounds:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.l, 10, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_sub_nc_u16 v0.l, 0x7000, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fdiv_pow_shl_cnt_in_bounds:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v0, 10, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_sub_nc_u16 v0, 0x7000, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %shl = shl nuw i16 1, %cnt
   %conv = uitofp i16 %shl to half
   %mul = fdiv half 0xH7000, %conv
@@ -1554,13 +1677,21 @@ define half @fdiv_pow_shl_cnt_in_bounds2(i16 %cnt) nounwind {
 ; GFX10-NEXT:    v_sub_nc_u16 v0, 0x4800, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fdiv_pow_shl_cnt_in_bounds2:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b16 v0, 10, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_sub_nc_u16 v0, 0x4800, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fdiv_pow_shl_cnt_in_bounds2:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.l, 10, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_sub_nc_u16 v0.l, 0x4800, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fdiv_pow_shl_cnt_in_bounds2:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v0, 10, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_sub_nc_u16 v0, 0x4800, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %shl = shl nuw i16 1, %cnt
   %conv = uitofp i16 %shl to half
   %mul = fdiv half 0xH4800, %conv
@@ -1604,31 +1735,58 @@ define half @fdiv_pow_shl_cnt_fail_out_of_bound2(i16 %cnt) nounwind {
 ; GFX10-NEXT:    v_div_fixup_f16 v0, v1, v0, 2.0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: fdiv_pow_shl_cnt_fail_out_of_bound2:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b16 v0, v0, 1
-; GFX11-NEXT:    s_mov_b32 s0, 2.0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cvt_f16_u16_e32 v0, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v1, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_rcp_f32_e32 v1, v1
-; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_add_f32_e32 v2, v1, v1
-; GFX11-NEXT:    v_fma_mix_f32 v3, -v0, v2, s0 op_sel_hi:[1,0,0]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fmac_f32_e32 v2, v3, v1
-; GFX11-NEXT:    v_fma_mix_f32 v3, -v0, v2, s0 op_sel_hi:[1,0,0]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f32_e32 v1, v3, v1
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v1, v1, v2
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_div_fixup_f16 v0, v1, v0, 2.0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fdiv_pow_shl_cnt_fail_out_of_bound2:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.l, v0.l, 1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, 2.0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_u16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v0.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v1, v1
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, v1, v1
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v4, -v3, v2, s0 op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v2, v4, v1
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v3, -v3, v2, s0 op_sel_hi:[1,0,0]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v1, v3, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.h, v0.l, 2.0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fdiv_pow_shl_cnt_fail_out_of_bound2:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v0, v0, 1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, 2.0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_u16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v1, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v2, v1, v1
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v3, -v0, v2, s0 op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v2, v3, v1
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v3, -v0, v2, s0 op_sel_hi:[1,0,0]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_div_fixup_f16 v0, v1, v0, 2.0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %shl = shl nuw i16 1, %cnt
   %conv = uitofp i16 %shl to half
   %mul = fdiv half 0xH4000, %conv
diff --git a/llvm/test/CodeGen/AMDGPU/fpext-free.ll b/llvm/test/CodeGen/AMDGPU/fpext-free.ll
index 3752100b7dc0f..d2343740855d6 100644
--- a/llvm/test/CodeGen/AMDGPU/fpext-free.ll
+++ b/llvm/test/CodeGen/AMDGPU/fpext-free.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -denormal-fp-math-f32=preserve-sign -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-F32FLUSH %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -denormal-fp-math-f32=ieee -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-F32DENORM %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -denormal-fp-math-f32=preserve-sign -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16,GFX11-F32FLUSH,GFX11-F32FLUSH-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -denormal-fp-math-f32=preserve-sign -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16,GFX11-F32FLUSH,GFX11-F32FLUSH-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -denormal-fp-math-f32=ieee -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16,GFX11-F32DENORM,GFX11-F32DENORM-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -denormal-fp-math-f32=ieee -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16,GFX11-F32DENORM,GFX11-F32DENORM-FAKE16 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math-f32=preserve-sign -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX89,GFX9-F32FLUSH %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math-f32=ieee -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX89,GFX9-F32DENORM %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx803 -denormal-fp-math-f32=preserve-sign -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX89 %s
@@ -8,14 +10,23 @@
 
 ;  fold (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z)
 define float @fadd_fpext_fmul_f16_to_f32(half %x, half %y, float %z) #0 {
-; GFX11-LABEL: fadd_fpext_fmul_f16_to_f32:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-NEXT:    v_add_f32_e32 v0, v0, v2
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fadd_fpext_fmul_f16_to_f32:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fadd_fpext_fmul_f16_to_f32:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-F32FLUSH-LABEL: fadd_fpext_fmul_f16_to_f32:
 ; GFX9-F32FLUSH:       ; %bb.0: ; %entry
@@ -39,16 +50,27 @@ entry:
 
 ; f16->f64 is not free.
 define double @fadd_fpext_fmul_f16_to_f64(half %x, half %y, double %z) #0 {
-; GFX11-LABEL: fadd_fpext_fmul_f16_to_f64:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f64 v[0:1], v[0:1], v[2:3]
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fadd_fpext_fmul_f16_to_f64:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f64 v[0:1], v[0:1], v[2:3]
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fadd_fpext_fmul_f16_to_f64:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f64 v[0:1], v[0:1], v[2:3]
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX89-LABEL: fadd_fpext_fmul_f16_to_f64:
 ; GFX89:       ; %bb.0: ; %entry
@@ -92,14 +114,23 @@ entry:
 
 ; fold (fadd x, (fpext (fmul y, z))) -> (fma (fpext y), (fpext z), x)
 define float @fadd_fpext_fmul_f16_to_f32_commute(half %x, half %y, float %z) #0 {
-; GFX11-LABEL: fadd_fpext_fmul_f16_to_f32_commute:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-NEXT:    v_add_f32_e32 v0, v2, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fadd_fpext_fmul_f16_to_f32_commute:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, v2, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fadd_fpext_fmul_f16_to_f32_commute:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-F32FLUSH-LABEL: fadd_fpext_fmul_f16_to_f32_commute:
 ; GFX9-F32FLUSH:       ; %bb.0: ; %entry
@@ -124,14 +155,23 @@ entry:
 ; fold (fadd (fma x, y, (fpext (fmul u, v))), z)
 ;   -> (fma x, y, (fma (fpext u), (fpext v), z))
 define float @fadd_muladd_fpext_fmul_f16_to_f32(float %x, float %y, half %u, half %v, float %z) #0 {
-; GFX11-LABEL: fadd_muladd_fpext_fmul_f16_to_f32:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mul_f16_e32 v2, v2, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[0,0,1]
-; GFX11-NEXT:    v_add_f32_e32 v0, v0, v4
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fadd_muladd_fpext_fmul_f16_to_f32:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v2.l, v2.l, v3.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[0,0,1]
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, v0, v4
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fadd_muladd_fpext_fmul_f16_to_f32:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[0,0,1]
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, v0, v4
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-F32FLUSH-LABEL: fadd_muladd_fpext_fmul_f16_to_f32:
 ; GFX9-F32FLUSH:       ; %bb.0: ; %entry
@@ -160,14 +200,23 @@ entry:
 ; fold (fadd x, (fma y, z, (fpext (fmul u, v)))
 ;   -> (fma y, z, (fma (fpext u), (fpext v), x))
 define float @fadd_muladd_fpext_fmul_f16_to_f32_commute(float %x, float %y, half %u, half %v, float %z) #0 {
-; GFX11-LABEL: fadd_muladd_fpext_fmul_f16_to_f32_commute:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mul_f16_e32 v2, v2, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[0,0,1]
-; GFX11-NEXT:    v_add_f32_e32 v0, v4, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fadd_muladd_fpext_fmul_f16_to_f32_commute:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v2.l, v2.l, v3.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[0,0,1]
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, v4, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fadd_muladd_fpext_fmul_f16_to_f32_commute:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[0,0,1]
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-F32FLUSH-LABEL: fadd_muladd_fpext_fmul_f16_to_f32_commute:
 ; GFX9-F32FLUSH:       ; %bb.0: ; %entry
@@ -194,14 +243,23 @@ entry:
 }
 
 define float @fadd_fmad_fpext_fmul_f16_to_f32(float %x, float %y, half %u, half %v, float %z) #0 {
-; GFX11-LABEL: fadd_fmad_fpext_fmul_f16_to_f32:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mul_f16_e32 v2, v2, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[0,0,1]
-; GFX11-NEXT:    v_add_f32_e32 v0, v0, v4
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fadd_fmad_fpext_fmul_f16_to_f32:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v2.l, v2.l, v3.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[0,0,1]
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, v0, v4
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fadd_fmad_fpext_fmul_f16_to_f32:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[0,0,1]
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, v0, v4
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-F32FLUSH-LABEL: fadd_fmad_fpext_fmul_f16_to_f32:
 ; GFX9-F32FLUSH:       ; %bb.0: ; %entry
@@ -231,14 +289,23 @@ entry:
 ; fold (fadd (fma x, y, (fpext (fmul u, v))), z)
 ;   -> (fma x, y, (fma (fpext u), (fpext v), z))
 define float @fadd_fma_fpext_fmul_f16_to_f32(float %x, float %y, half %u, half %v, float %z) #0 {
-; GFX11-LABEL: fadd_fma_fpext_fmul_f16_to_f32:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mul_f16_e32 v2, v2, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[0,0,1]
-; GFX11-NEXT:    v_add_f32_e32 v0, v0, v4
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fadd_fma_fpext_fmul_f16_to_f32:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v2.l, v2.l, v3.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[0,0,1]
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, v0, v4
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fadd_fma_fpext_fmul_f16_to_f32:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[0,0,1]
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, v0, v4
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-F32FLUSH-LABEL: fadd_fma_fpext_fmul_f16_to_f32:
 ; GFX9-F32FLUSH:       ; %bb.0: ; %entry
@@ -265,14 +332,23 @@ entry:
 }
 
 define float @fadd_fma_fpext_fmul_f16_to_f32_commute(float %x, float %y, half %u, half %v, float %z) #0 {
-; GFX11-LABEL: fadd_fma_fpext_fmul_f16_to_f32_commute:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mul_f16_e32 v2, v2, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[0,0,1]
-; GFX11-NEXT:    v_add_f32_e32 v0, v4, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fadd_fma_fpext_fmul_f16_to_f32_commute:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v2.l, v2.l, v3.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[0,0,1]
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, v4, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fadd_fma_fpext_fmul_f16_to_f32_commute:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[0,0,1]
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-F32FLUSH-LABEL: fadd_fma_fpext_fmul_f16_to_f32_commute:
 ; GFX9-F32FLUSH:       ; %bb.0: ; %entry
@@ -301,16 +377,27 @@ entry:
 ; fold (fadd x, (fpext (fma y, z, (fmul u, v)))
 ;   -> (fma (fpext y), (fpext z), (fma (fpext u), (fpext v), x))
 define float @fadd_fpext_fmuladd_f16_to_f32(float %x, half %y, half %z, half %u, half %v) #0 {
-; GFX11-LABEL: fadd_fpext_fmuladd_f16_to_f32:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mul_f16_e32 v3, v3, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fmac_f16_e32 v3, v1, v2
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v1, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fadd_fpext_fmuladd_f16_to_f32:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v1.h, v3.l, v4.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fmac_f16_e32 v1.h, v1.l, v2.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fadd_fpext_fmuladd_f16_to_f32:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fmac_f16_e32 v3, v1, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v1, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-F32FLUSH-LABEL: fadd_fpext_fmuladd_f16_to_f32:
 ; GFX9-F32FLUSH:       ; %bb.0: ; %entry
@@ -336,16 +423,27 @@ entry:
 }
 
 define float @fadd_fpext_fma_f16_to_f32(float %x, half %y, half %z, half %u, half %v) #0 {
-; GFX11-LABEL: fadd_fpext_fma_f16_to_f32:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mul_f16_e32 v3, v3, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fmac_f16_e32 v3, v1, v2
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v1, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fadd_fpext_fma_f16_to_f32:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v1.h, v3.l, v4.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fmac_f16_e32 v1.h, v1.l, v2.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fadd_fpext_fma_f16_to_f32:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fmac_f16_e32 v3, v1, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v1, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-F32FLUSH-LABEL: fadd_fpext_fma_f16_to_f32:
 ; GFX9-F32FLUSH:       ; %bb.0: ; %entry
@@ -371,16 +469,27 @@ entry:
 }
 
 define float @fadd_fpext_fma_f16_to_f32_commute(float %x, half %y, half %z, half %u, half %v) #0 {
-; GFX11-LABEL: fadd_fpext_fma_f16_to_f32_commute:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mul_f16_e32 v3, v3, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fmac_f16_e32 v3, v1, v2
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v1, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v0, v1, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fadd_fpext_fma_f16_to_f32_commute:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v1.h, v3.l, v4.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fmac_f16_e32 v1.h, v1.l, v2.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, v1, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fadd_fpext_fma_f16_to_f32_commute:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fmac_f16_e32 v3, v1, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v1, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-F32FLUSH-LABEL: fadd_fpext_fma_f16_to_f32_commute:
 ; GFX9-F32FLUSH:       ; %bb.0: ; %entry
@@ -408,14 +517,23 @@ entry:
 ; fold (fsub (fpext (fmul x, y)), z)
 ;   -> (fma (fpext x), (fpext y), (fneg z))
 define float @fsub_fpext_fmul_f16_to_f32(half %x, half %y, float %z) #0 {
-; GFX11-LABEL: fsub_fpext_fmul_f16_to_f32:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-NEXT:    v_sub_f32_e32 v0, v0, v2
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fsub_fpext_fmul_f16_to_f32:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT:    v_sub_f32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fsub_fpext_fmul_f16_to_f32:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_sub_f32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-F32FLUSH-LABEL: fsub_fpext_fmul_f16_to_f32:
 ; GFX9-F32FLUSH:       ; %bb.0: ; %entry
@@ -446,14 +564,23 @@ define float @fsub_fpext_fmul_f16_to_f32_commute(float %x, half %y, half %z) #0
 ; GFX11-F32FLUSH-NEXT:    v_fma_mix_f32 v0, -v1, v2, v0 op_sel_hi:[1,1,0]
 ; GFX11-F32FLUSH-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-F32DENORM-LABEL: fsub_fpext_fmul_f16_to_f32_commute:
-; GFX11-F32DENORM:       ; %bb.0: ; %entry
-; GFX11-F32DENORM-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-F32DENORM-NEXT:    v_mul_f16_e32 v1, v1, v2
-; GFX11-F32DENORM-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-F32DENORM-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; GFX11-F32DENORM-NEXT:    v_sub_f32_e32 v0, v0, v1
-; GFX11-F32DENORM-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-F32DENORM-TRUE16-LABEL: fsub_fpext_fmul_f16_to_f32_commute:
+; GFX11-F32DENORM-TRUE16:       ; %bb.0: ; %entry
+; GFX11-F32DENORM-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-F32DENORM-TRUE16-NEXT:    v_mul_f16_e32 v1.l, v1.l, v2.l
+; GFX11-F32DENORM-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-F32DENORM-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v1.l
+; GFX11-F32DENORM-TRUE16-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GFX11-F32DENORM-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-F32DENORM-FAKE16-LABEL: fsub_fpext_fmul_f16_to_f32_commute:
+; GFX11-F32DENORM-FAKE16:       ; %bb.0: ; %entry
+; GFX11-F32DENORM-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-F32DENORM-FAKE16-NEXT:    v_mul_f16_e32 v1, v1, v2
+; GFX11-F32DENORM-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-F32DENORM-FAKE16-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; GFX11-F32DENORM-FAKE16-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GFX11-F32DENORM-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-F32FLUSH-LABEL: fsub_fpext_fmul_f16_to_f32_commute:
 ; GFX9-F32FLUSH:       ; %bb.0: ; %entry
@@ -478,14 +605,23 @@ entry:
 ; fold (fsub (fpext (fneg (fmul, x, y))), z)
 ;   -> (fneg (fma (fpext x), (fpext y), z))
 define float @fsub_fpext_fneg_fmul_f16_to_f32(half %x, half %y, float %z) #0 {
-; GFX11-LABEL: fsub_fpext_fneg_fmul_f16_to_f32:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mul_f16_e64 v0, v0, -v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-NEXT:    v_sub_f32_e32 v0, v0, v2
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fsub_fpext_fneg_fmul_f16_to_f32:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mul_f16_e64 v0.l, v0.l, -v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT:    v_sub_f32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fsub_fpext_fneg_fmul_f16_to_f32:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mul_f16_e64 v0, v0, -v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_sub_f32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-F32FLUSH-LABEL: fsub_fpext_fneg_fmul_f16_to_f32:
 ; GFX9-F32FLUSH:       ; %bb.0: ; %entry
@@ -511,14 +647,23 @@ entry:
 ; fold (fsub (fneg (fpext (fmul, x, y))), z)
 ;   -> (fneg (fma (fpext x)), (fpext y), z)
 define float @fsub_fneg_fpext_fmul_f16_to_f32(half %x, half %y, float %z) #0 {
-; GFX11-LABEL: fsub_fneg_fpext_fmul_f16_to_f32:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mul_f16_e64 v0, v0, -v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-NEXT:    v_sub_f32_e32 v0, v0, v2
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fsub_fneg_fpext_fmul_f16_to_f32:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mul_f16_e64 v0.l, v0.l, -v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT:    v_sub_f32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fsub_fneg_fpext_fmul_f16_to_f32:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mul_f16_e64 v0, v0, -v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_sub_f32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-F32FLUSH-LABEL: fsub_fneg_fpext_fmul_f16_to_f32:
 ; GFX9-F32FLUSH:       ; %bb.0: ; %entry
@@ -544,14 +689,23 @@ entry:
 ; fold (fsub (fmad x, y, (fpext (fmul u, v))), z)
 ;    -> (fmad x, y (fmad (fpext u), (fpext v), (fneg z)))
 define float @fsub_muladd_fpext_mul_f16_to_f32(float %x, float %y, float %z, half %u, half %v) #0 {
-; GFX11-LABEL: fsub_muladd_fpext_mul_f16_to_f32:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mul_f16_e32 v3, v3, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fma_mix_f32 v0, v0, v1, v3 op_sel_hi:[0,0,1]
-; GFX11-NEXT:    v_sub_f32_e32 v0, v0, v2
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fsub_muladd_fpext_mul_f16_to_f32:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v3.l, v3.l, v4.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v0, v0, v1, v3 op_sel_hi:[0,0,1]
+; GFX11-TRUE16-NEXT:    v_sub_f32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fsub_muladd_fpext_mul_f16_to_f32:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v0, v0, v1, v3 op_sel_hi:[0,0,1]
+; GFX11-FAKE16-NEXT:    v_sub_f32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-F32FLUSH-LABEL: fsub_muladd_fpext_mul_f16_to_f32:
 ; GFX9-F32FLUSH:       ; %bb.0: ; %entry
@@ -581,16 +735,27 @@ entry:
 ;    -> (fmad (fpext x), (fpext y),
 ;            (fmad (fpext u), (fpext v), (fneg z)))
 define float @fsub_fpext_muladd_mul_f16_to_f32(half %x, half %y, float %z, half %u, half %v) #0 {
-; GFX11-LABEL: fsub_fpext_muladd_mul_f16_to_f32:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mul_f16_e32 v3, v3, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fmac_f16_e32 v3, v0, v1
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_sub_f32_e32 v0, v0, v2
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fsub_fpext_muladd_mul_f16_to_f32:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v0.h, v3.l, v4.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fmac_f16_e32 v0.h, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_sub_f32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fsub_fpext_muladd_mul_f16_to_f32:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fmac_f16_e32 v3, v0, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_sub_f32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX89-LABEL: fsub_fpext_muladd_mul_f16_to_f32:
 ; GFX89:       ; %bb.0: ; %entry
@@ -611,14 +776,23 @@ entry:
 ; fold (fsub x, (fmad y, z, (fpext (fmul u, v))))
 ;   -> (fmad (fneg y), z, (fmad (fneg (fpext u)), (fpext v), x))
 define float @fsub_muladd_fpext_mul_f16_to_f32_commute(float %x, float %y, float %z, half %u, half %v) #0 {
-; GFX11-LABEL: fsub_muladd_fpext_mul_f16_to_f32_commute:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mul_f16_e32 v3, v3, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fma_mix_f32 v1, v1, v2, v3 op_sel_hi:[0,0,1]
-; GFX11-NEXT:    v_sub_f32_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fsub_muladd_fpext_mul_f16_to_f32_commute:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v3.l, v3.l, v4.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v1, v1, v2, v3 op_sel_hi:[0,0,1]
+; GFX11-TRUE16-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fsub_muladd_fpext_mul_f16_to_f32_commute:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v1, v1, v2, v3 op_sel_hi:[0,0,1]
+; GFX11-FAKE16-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-F32FLUSH-LABEL: fsub_muladd_fpext_mul_f16_to_f32_commute:
 ; GFX9-F32FLUSH:       ; %bb.0: ; %entry
@@ -647,16 +821,27 @@ entry:
 ;    -> (fma (fneg (fpext y)), (fpext z),
 ;            (fma (fneg (fpext u)), (fpext v), x))
 define float @fsub_fpext_muladd_mul_f16_to_f32_commute(float %x, half %y, half %z, half %u, half %v) #0 {
-; GFX11-LABEL: fsub_fpext_muladd_mul_f16_to_f32_commute:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mul_f16_e32 v3, v3, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fmac_f16_e32 v3, v1, v2
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v1, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_sub_f32_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: fsub_fpext_muladd_mul_f16_to_f32_commute:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v1.h, v3.l, v4.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fmac_f16_e32 v1.h, v1.l, v2.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: fsub_fpext_muladd_mul_f16_to_f32_commute:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fmac_f16_e32 v3, v1, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v1, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_sub_f32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX89-LABEL: fsub_fpext_muladd_mul_f16_to_f32_commute:
 ; GFX89:       ; %bb.0: ; %entry
@@ -680,3 +865,7 @@ declare half @llvm.fmuladd.f16(half, half, half) #0
 declare half @llvm.fma.f16(half, half, half) #0
 
 attributes #0 = { nounwind readnone speculatable }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11-F32DENORM: {{.*}}
+; GFX11-F32FLUSH-FAKE16: {{.*}}
+; GFX11-F32FLUSH-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/fpow.ll b/llvm/test/CodeGen/AMDGPU/fpow.ll
index d855707fbe4de..6d383951be9c1 100644
--- a/llvm/test/CodeGen/AMDGPU/fpow.ll
+++ b/llvm/test/CodeGen/AMDGPU/fpow.ll
@@ -4,7 +4,8 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck -check-prefix=GFX90A %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define float @v_pow_f32(float %x, float %y) {
 ; GFX6-LABEL: v_pow_f32:
@@ -188,19 +189,33 @@ define half @v_pow_f16(half %x, half %y) {
 ; GFX10-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_pow_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_log_f32_e32 v0, v0
-; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-NEXT:    v_exp_f32_e32 v0, v0
-; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_pow_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_mul_dx9_zero_f32_e32 v0, v1, v0
+; GFX11-TRUE16-NEXT:    v_exp_f32_e32 v0, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_pow_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_mul_dx9_zero_f32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT:    v_exp_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %pow = call half @llvm.pow.f16(half %x, half %y)
   ret half %pow
 }
@@ -297,31 +312,54 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
 ; GFX10-NEXT:    v_pack_b32_f16 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_pow_v2f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v2, v2
-; GFX11-NEXT:    v_log_f32_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v3, v3
-; GFX11-NEXT:    v_log_f32_e32 v2, v2
-; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-NEXT:    v_mul_dx9_zero_f32_e32 v2, v3, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_exp_f32_e32 v0, v0
-; GFX11-NEXT:    v_exp_f32_e32 v1, v2
-; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_pow_v2f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v2, v0.h
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v3, v1.h
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_log_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_mul_dx9_zero_f32_e32 v2, v3, v2
+; GFX11-TRUE16-NEXT:    v_mul_dx9_zero_f32_e32 v0, v1, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_exp_f32_e32 v1, v2
+; GFX11-TRUE16-NEXT:    v_exp_f32_e32 v2, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v1
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_pow_v2f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v2, v2
+; GFX11-FAKE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v3, v3
+; GFX11-FAKE16-NEXT:    v_log_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_mul_dx9_zero_f32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT:    v_mul_dx9_zero_f32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_exp_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_exp_f32_e32 v1, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x, <2 x half> %y)
   ret <2 x half> %pow
 }
@@ -422,31 +460,54 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
 ; GFX10-NEXT:    v_pack_b32_f16 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_pow_v2f16_fneg_lhs:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e64 v0, -v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cvt_f32_f16_e64 v2, -v2
-; GFX11-NEXT:    v_log_f32_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v3, v3
-; GFX11-NEXT:    v_log_f32_e32 v2, v2
-; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-NEXT:    v_mul_dx9_zero_f32_e32 v2, v3, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_exp_f32_e32 v0, v0
-; GFX11-NEXT:    v_exp_f32_e32 v1, v2
-; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_pow_v2f16_fneg_lhs:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v2, -v0.h
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v0, -v0.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v3, v1.h
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_log_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_mul_dx9_zero_f32_e32 v2, v3, v2
+; GFX11-TRUE16-NEXT:    v_mul_dx9_zero_f32_e32 v0, v1, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_exp_f32_e32 v1, v2
+; GFX11-TRUE16-NEXT:    v_exp_f32_e32 v2, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v1
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_pow_v2f16_fneg_lhs:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v0, -v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v2, -v2
+; GFX11-FAKE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v3, v3
+; GFX11-FAKE16-NEXT:    v_log_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_mul_dx9_zero_f32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT:    v_mul_dx9_zero_f32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_exp_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_exp_f32_e32 v1, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %x.fneg = fneg <2 x half> %x
   %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x.fneg, <2 x half> %y)
   ret <2 x half> %pow
@@ -548,31 +609,54 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
 ; GFX10-NEXT:    v_pack_b32_f16 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_pow_v2f16_fneg_rhs:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-NEXT:    v_cvt_f32_f16_e64 v1, -v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v2, v2
-; GFX11-NEXT:    v_log_f32_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cvt_f32_f16_e64 v3, -v3
-; GFX11-NEXT:    v_log_f32_e32 v2, v2
-; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-NEXT:    v_mul_dx9_zero_f32_e32 v2, v3, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_exp_f32_e32 v0, v0
-; GFX11-NEXT:    v_exp_f32_e32 v1, v2
-; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_pow_v2f16_fneg_rhs:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v2, v0.h
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v3, -v1.h
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v1, -v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_log_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_mul_dx9_zero_f32_e32 v2, v3, v2
+; GFX11-TRUE16-NEXT:    v_mul_dx9_zero_f32_e32 v0, v1, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_exp_f32_e32 v1, v2
+; GFX11-TRUE16-NEXT:    v_exp_f32_e32 v2, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v1
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_pow_v2f16_fneg_rhs:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v1, -v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v2, v2
+; GFX11-FAKE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v3, -v3
+; GFX11-FAKE16-NEXT:    v_log_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_mul_dx9_zero_f32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT:    v_mul_dx9_zero_f32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_exp_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_exp_f32_e32 v1, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %y.fneg = fneg <2 x half> %y
   %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x, <2 x half> %y.fneg)
   ret <2 x half> %pow
@@ -678,31 +762,54 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
 ; GFX10-NEXT:    v_pack_b32_f16 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_pow_v2f16_fneg_lhs_rhs:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e64 v0, -v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-NEXT:    v_cvt_f32_f16_e64 v1, -v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cvt_f32_f16_e64 v2, -v2
-; GFX11-NEXT:    v_log_f32_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cvt_f32_f16_e64 v3, -v3
-; GFX11-NEXT:    v_log_f32_e32 v2, v2
-; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-NEXT:    v_mul_dx9_zero_f32_e32 v2, v3, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_exp_f32_e32 v0, v0
-; GFX11-NEXT:    v_exp_f32_e32 v1, v2
-; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_pow_v2f16_fneg_lhs_rhs:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v2, -v0.h
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v0, -v0.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v3, -v1.h
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v1, -v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_log_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_mul_dx9_zero_f32_e32 v2, v3, v2
+; GFX11-TRUE16-NEXT:    v_mul_dx9_zero_f32_e32 v0, v1, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_exp_f32_e32 v1, v2
+; GFX11-TRUE16-NEXT:    v_exp_f32_e32 v2, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v1
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_pow_v2f16_fneg_lhs_rhs:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v0, -v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v1, -v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v2, -v2
+; GFX11-FAKE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v3, -v3
+; GFX11-FAKE16-NEXT:    v_log_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_mul_dx9_zero_f32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT:    v_mul_dx9_zero_f32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_exp_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_exp_f32_e32 v1, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %x.fneg = fneg <2 x half> %x
   %y.fneg = fneg <2 x half> %y
   %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x.fneg, <2 x half> %y.fneg)
diff --git a/llvm/test/CodeGen/AMDGPU/fract-match.ll b/llvm/test/CodeGen/AMDGPU/fract-match.ll
index 0935438f1b951..d957ba93e4fb3 100644
--- a/llvm/test/CodeGen/AMDGPU/fract-match.ll
+++ b/llvm/test/CodeGen/AMDGPU/fract-match.ll
@@ -13,8 +13,10 @@
 ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=kaveri < %s | FileCheck -check-prefixes=GCN,GFX7 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX8 %s
-; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11 %s
-; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-FAKE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
 
 ; Test patterns to match v_fract_* instructions.
 
@@ -1486,21 +1488,37 @@ define half @basic_fract_f16_nonan(half nofpclass(nan) %x) {
 ; GFX8-NEXT:    v_fract_f16_e32 v0, v0
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: basic_fract_f16_nonan:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_fract_f16_e32 v0, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: basic_fract_f16_nonan:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_fract_f16_e32 v0, v0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: basic_fract_f16_nonan:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_fract_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: basic_fract_f16_nonan:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_fract_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: basic_fract_f16_nonan:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_fract_f16_e32 v0.l, v0.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: basic_fract_f16_nonan:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_fract_f16_e32 v0, v0
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %floor = tail call half @llvm.floor.f16(half %x)
   %sub = fsub half %x, %floor
@@ -1574,29 +1592,51 @@ define <2 x half> @basic_fract_v2f16_nonan(<2 x half> nofpclass(nan) %x) {
 ; GFX8-NEXT:    v_pack_b32_f16 v0, v1, v0
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: basic_fract_v2f16_nonan:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_fract_f16_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fract_f16_e32 v1, v1
-; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: basic_fract_v2f16_nonan:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-NEXT:    v_fract_f16_e32 v0, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_fract_f16_e32 v1, v1
-; GFX12-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: basic_fract_v2f16_nonan:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_fract_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT:    v_fract_f16_e32 v0.h, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: basic_fract_v2f16_nonan:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_fract_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fract_f16_e32 v1, v1
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: basic_fract_v2f16_nonan:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_fract_f16_e32 v0.l, v0.l
+; GFX12-TRUE16-NEXT:    v_fract_f16_e32 v0.h, v0.h
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: basic_fract_v2f16_nonan:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-FAKE16-NEXT:    v_fract_f16_e32 v0, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_fract_f16_e32 v1, v1
+; GFX12-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %floor = tail call <2 x half> @llvm.floor.v2f16(<2 x half> %x)
   %sub = fsub <2 x half> %x, %floor
@@ -1748,25 +1788,45 @@ define half @safe_math_fract_f16_noinf_check(half %x, ptr addrspace(1) writeonly
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: safe_math_fract_f16_noinf_check:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_floor_f16_e32 v3, v0
-; GFX11-NEXT:    v_fract_f16_e32 v0, v0
-; GFX11-NEXT:    global_store_b16 v[1:2], v3, off
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: safe_math_fract_f16_noinf_check:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_floor_f16_e32 v3, v0
-; GFX12-NEXT:    v_fract_f16_e32 v0, v0
-; GFX12-NEXT:    global_store_b16 v[1:2], v3, off
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: safe_math_fract_f16_noinf_check:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_floor_f16_e32 v0.h, v0.l
+; GFX11-TRUE16-NEXT:    v_fract_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT:    global_store_d16_hi_b16 v[1:2], v0, off
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: safe_math_fract_f16_noinf_check:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_floor_f16_e32 v3, v0
+; GFX11-FAKE16-NEXT:    v_fract_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    global_store_b16 v[1:2], v3, off
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: safe_math_fract_f16_noinf_check:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_floor_f16_e32 v0.h, v0.l
+; GFX12-TRUE16-NEXT:    v_fract_f16_e32 v0.l, v0.l
+; GFX12-TRUE16-NEXT:    global_store_d16_hi_b16 v[1:2], v0, off
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: safe_math_fract_f16_noinf_check:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_floor_f16_e32 v3, v0
+; GFX12-FAKE16-NEXT:    v_fract_f16_e32 v0, v0
+; GFX12-FAKE16-NEXT:    global_store_b16 v[1:2], v3, off
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %floor = tail call half @llvm.floor.f16(half %x)
   %sub = fsub half %x, %floor
@@ -2365,31 +2425,57 @@ define half @safe_math_fract_f16(half %x, ptr addrspace(1) writeonly captures(no
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: safe_math_fract_f16:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_fract_f16_e32 v3, v0
-; GFX11-NEXT:    v_cmp_neq_f16_e64 vcc_lo, 0x7c00, |v0|
-; GFX11-NEXT:    v_floor_f16_e32 v4, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc_lo
-; GFX11-NEXT:    global_store_b16 v[1:2], v4, off
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: safe_math_fract_f16:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_fract_f16_e32 v3, v0
-; GFX12-NEXT:    v_cmp_neq_f16_e64 vcc_lo, 0x7c00, |v0|
-; GFX12-NEXT:    v_floor_f16_e32 v4, v0
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc_lo
-; GFX12-NEXT:    global_store_b16 v[1:2], v4, off
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: safe_math_fract_f16:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_fract_f16_e32 v0.h, v0.l
+; GFX11-TRUE16-NEXT:    v_cmp_neq_f16_e64 s0, 0x7c00, |v0.l|
+; GFX11-TRUE16-NEXT:    v_floor_f16_e32 v3.l, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0, v0.h, s0
+; GFX11-TRUE16-NEXT:    global_store_b16 v[1:2], v3, off
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: safe_math_fract_f16:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_fract_f16_e32 v3, v0
+; GFX11-FAKE16-NEXT:    v_cmp_neq_f16_e64 vcc_lo, 0x7c00, |v0|
+; GFX11-FAKE16-NEXT:    v_floor_f16_e32 v4, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc_lo
+; GFX11-FAKE16-NEXT:    global_store_b16 v[1:2], v4, off
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: safe_math_fract_f16:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_fract_f16_e32 v0.h, v0.l
+; GFX12-TRUE16-NEXT:    v_cmp_neq_f16_e64 s0, 0x7c00, |v0.l|
+; GFX12-TRUE16-NEXT:    v_floor_f16_e32 v3.l, v0.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0, v0.h, s0
+; GFX12-TRUE16-NEXT:    global_store_b16 v[1:2], v3, off
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: safe_math_fract_f16:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_fract_f16_e32 v3, v0
+; GFX12-FAKE16-NEXT:    v_cmp_neq_f16_e64 vcc_lo, 0x7c00, |v0|
+; GFX12-FAKE16-NEXT:    v_floor_f16_e32 v4, v0
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc_lo
+; GFX12-FAKE16-NEXT:    global_store_b16 v[1:2], v4, off
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %floor = tail call half @llvm.floor.f16(half %x)
   %sub = fsub half %x, %floor
@@ -2538,49 +2624,89 @@ define <2 x half> @safe_math_fract_v2f16(<2 x half> %x, ptr addrspace(1) writeon
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: safe_math_fract_v2f16:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-NEXT:    v_fract_f16_e32 v6, v0
-; GFX11-NEXT:    v_floor_f16_e32 v5, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_fract_f16_e32 v4, v3
-; GFX11-NEXT:    v_cmp_class_f16_e64 s0, v3, 0x204
-; GFX11-NEXT:    v_floor_f16_e32 v7, v3
-; GFX11-NEXT:    v_cndmask_b32_e64 v3, v4, 0, s0
-; GFX11-NEXT:    v_cmp_class_f16_e64 s0, v0, 0x204
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_pack_b32_f16 v4, v5, v7
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, v6, 0, s0
-; GFX11-NEXT:    global_store_b32 v[1:2], v4, off
-; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v3
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: safe_math_fract_v2f16:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX12-NEXT:    v_fract_f16_e32 v6, v0
-; GFX12-NEXT:    v_floor_f16_e32 v5, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX12-NEXT:    v_fract_f16_e32 v4, v3
-; GFX12-NEXT:    v_cmp_class_f16_e64 s0, v3, 0x204
-; GFX12-NEXT:    v_floor_f16_e32 v7, v3
-; GFX12-NEXT:    s_wait_alu 0xf1ff
-; GFX12-NEXT:    v_cndmask_b32_e64 v3, v4, 0, s0
-; GFX12-NEXT:    v_cmp_class_f16_e64 s0, v0, 0x204
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX12-NEXT:    v_pack_b32_f16 v4, v5, v7
-; GFX12-NEXT:    s_wait_alu 0xf1ff
-; GFX12-NEXT:    v_cndmask_b32_e64 v0, v6, 0, s0
-; GFX12-NEXT:    global_store_b32 v[1:2], v4, off
-; GFX12-NEXT:    v_pack_b32_f16 v0, v0, v3
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: safe_math_fract_v2f16:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_fract_f16_e32 v3.l, v0.l
+; GFX11-TRUE16-NEXT:    v_fract_f16_e32 v3.h, v0.h
+; GFX11-TRUE16-NEXT:    v_cmp_class_f16_e64 s0, v0.h, 0x204
+; GFX11-TRUE16-NEXT:    v_cmp_class_f16_e64 s1, v0.l, 0x204
+; GFX11-TRUE16-NEXT:    v_floor_f16_e32 v0.h, v0.h
+; GFX11-TRUE16-NEXT:    v_floor_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.h, v3.h, 0, s0
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.l, v3.l, 0, s1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v4, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v3.l, v3.h
+; GFX11-TRUE16-NEXT:    global_store_b32 v[1:2], v4, off
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: safe_math_fract_v2f16:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-FAKE16-NEXT:    v_fract_f16_e32 v6, v0
+; GFX11-FAKE16-NEXT:    v_floor_f16_e32 v5, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_fract_f16_e32 v4, v3
+; GFX11-FAKE16-NEXT:    v_cmp_class_f16_e64 s0, v3, 0x204
+; GFX11-FAKE16-NEXT:    v_floor_f16_e32 v7, v3
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v3, v4, 0, s0
+; GFX11-FAKE16-NEXT:    v_cmp_class_f16_e64 s0, v0, 0x204
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v4, v5, v7
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, v6, 0, s0
+; GFX11-FAKE16-NEXT:    global_store_b32 v[1:2], v4, off
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v3
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: safe_math_fract_v2f16:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_fract_f16_e32 v3.l, v0.l
+; GFX12-TRUE16-NEXT:    v_fract_f16_e32 v3.h, v0.h
+; GFX12-TRUE16-NEXT:    v_cmp_class_f16_e64 s0, v0.h, 0x204
+; GFX12-TRUE16-NEXT:    v_cmp_class_f16_e64 s1, v0.l, 0x204
+; GFX12-TRUE16-NEXT:    v_floor_f16_e32 v0.h, v0.h
+; GFX12-TRUE16-NEXT:    v_floor_f16_e32 v0.l, v0.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v3.h, v3.h, 0, s0
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v3.l, v3.l, 0, s1
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_pack_b32_f16 v4, v0.l, v0.h
+; GFX12-TRUE16-NEXT:    v_pack_b32_f16 v0, v3.l, v3.h
+; GFX12-TRUE16-NEXT:    global_store_b32 v[1:2], v4, off
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: safe_math_fract_v2f16:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX12-FAKE16-NEXT:    v_fract_f16_e32 v6, v0
+; GFX12-FAKE16-NEXT:    v_floor_f16_e32 v5, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_fract_f16_e32 v4, v3
+; GFX12-FAKE16-NEXT:    v_cmp_class_f16_e64 s0, v3, 0x204
+; GFX12-FAKE16-NEXT:    v_floor_f16_e32 v7, v3
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v3, v4, 0, s0
+; GFX12-FAKE16-NEXT:    v_cmp_class_f16_e64 s0, v0, 0x204
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_pack_b32_f16 v4, v5, v7
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, v6, 0, s0
+; GFX12-FAKE16-NEXT:    global_store_b32 v[1:2], v4, off
+; GFX12-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v3
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %floor = tail call <2 x half> @llvm.floor.v2f16(<2 x half> %x)
   %sub = fsub <2 x half> %x, %floor
diff --git a/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll b/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
index 25fe57c16c661..ee62359cffc63 100644
--- a/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
+++ b/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
@@ -1,7 +1,8 @@
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,MUBUF %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX9-MUBUF,MUBUF %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-promote-alloca,+enable-flat-scratch -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX9-FLATSCR %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck --check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck --check-prefixes=GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck --check-prefixes=GFX11-FAKE16 %s
 
 ; Test that non-entry function frame indices are expanded properly to
 ; give an index relative to the scratch wave offset register
@@ -303,13 +304,20 @@ ret:
 %type.i16 = type { i16 }
 @_ZZN0 = external hidden addrspace(3) global %struct0, align 8
 
-; GFX11-LABEL: tied_operand_test:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11:     scratch_load_u16 [[LDRESULT:v[0-9]+]], off, off
-; GFX11:     v_dual_mov_b32 [[C:v[0-9]+]], 0x7b :: v_dual_mov_b32 v{{[0-9]+}}, s{{[0-9]+}}
-; GFX11-DAG:     ds_store_b16 v{{[0-9]+}}, [[LDRESULT]]  offset:10
-; GFX11-DAG:     ds_store_b16 v{{[0-9]+}}, [[C]]  offset:8
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: tied_operand_test:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16:     scratch_load_d16_b16 [[LDRESULT:v[0-9]+]], off, off
+; GFX11-TRUE16:     v_mov_b16_e32 [[C:v[0-9]]].{{(l|h)}}, 0x7b
+; GFX11-TRUE16-DAG:     ds_store_b16 v{{[0-9]+}}, [[LDRESULT]]  offset:10
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: tied_operand_test:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16:     scratch_load_u16 [[LDRESULT:v[0-9]+]], off, off
+; GFX11-FAKE16:     v_dual_mov_b32 [[C:v[0-9]+]], 0x7b :: v_dual_mov_b32 v{{[0-9]+}}, s{{[0-9]+}}
+; GFX11-FAKE16-DAG:     ds_store_b16 v{{[0-9]+}}, [[LDRESULT]]  offset:10
+; GFX11-FAKE16-DAG:     ds_store_b16 v{{[0-9]+}}, [[C]]  offset:8
+; GFX11-FAKE16-NEXT:    s_endpgm
 define protected amdgpu_kernel void @tied_operand_test(i1 %c1, i1 %c2, i32 %val) {
 entry:
   %scratch0 = alloca i16, align 4, addrspace(5)
diff --git a/llvm/test/CodeGen/AMDGPU/freeze.ll b/llvm/test/CodeGen/AMDGPU/freeze.ll
index b1732b905e4c1..ff9b0641e43d8 100644
--- a/llvm/test/CodeGen/AMDGPU/freeze.ll
+++ b/llvm/test/CodeGen/AMDGPU/freeze.ll
@@ -14,8 +14,11 @@
 ; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG  %s
 ; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
 
-; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
+; FIXME-TRUE16 enable gisel
+; XUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
 
 define void @freeze_v2i32(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
 ; GFX6-SDAG-LABEL: freeze_v2i32:
@@ -5560,13 +5563,29 @@ define void @freeze_i16(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
 ; GFX10-NEXT:    global_store_short v[2:3], v0, off
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: freeze_i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_u16 v0, v[0:1], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b16 v[2:3], v0, off
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: freeze_i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_b16 v0, v[0:1], off
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b16 v[2:3], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: freeze_i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u16 v0, v[0:1], off
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b16 v[2:3], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: freeze_i16:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    global_load_u16 v0, v[0:1], off
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    global_store_b16 v[2:3], v0, off
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
   %a = load i16, ptr addrspace(1) %ptra
   %freeze = freeze i16 %a
   store i16 %freeze, ptr addrspace(1) %ptrb
@@ -6203,13 +6222,29 @@ define void @freeze_f16(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
 ; GFX10-NEXT:    global_store_short v[2:3], v0, off
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: freeze_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_u16 v0, v[0:1], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b16 v[2:3], v0, off
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: freeze_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_b16 v0, v[0:1], off
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b16 v[2:3], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: freeze_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u16 v0, v[0:1], off
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b16 v[2:3], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: freeze_f16:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    global_load_u16 v0, v[0:1], off
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    global_store_b16 v[2:3], v0, off
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
   %a = load half, ptr addrspace(1) %ptra
   %freeze = freeze half %a
   store half %freeze, ptr addrspace(1) %ptrb
@@ -6852,13 +6887,29 @@ define void @freeze_bf16(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
 ; GFX10-NEXT:    global_store_short v[2:3], v0, off
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: freeze_bf16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_u16 v0, v[0:1], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b16 v[2:3], v0, off
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: freeze_bf16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_b16 v0, v[0:1], off
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b16 v[2:3], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: freeze_bf16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u16 v0, v[0:1], off
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b16 v[2:3], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: freeze_bf16:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    global_load_u16 v0, v[0:1], off
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    global_store_b16 v[2:3], v0, off
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
   %a = load bfloat, ptr addrspace(1) %ptra
   %freeze = freeze bfloat %a
   store bfloat %freeze, ptr addrspace(1) %ptrb
@@ -12115,13 +12166,29 @@ define void @freeze_i8(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
 ; GFX10-NEXT:    global_store_byte v[2:3], v0, off
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: freeze_i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_u8 v0, v[0:1], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b8 v[2:3], v0, off
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: freeze_i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[2:3], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: freeze_i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[2:3], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: freeze_i8:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v[0:1], off
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    global_store_b8 v[2:3], v0, off
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
   %a = load i8, ptr addrspace(1) %ptra
   %freeze = freeze i8 %a
   store i8 %freeze, ptr addrspace(1) %ptrb
@@ -12235,13 +12302,21 @@ define void @freeze_v2i8(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
 ; GFX10-GISEL-NEXT:    global_store_short v[2:3], v0, off
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: freeze_v2i8:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    global_load_u16 v0, v[0:1], off
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    global_store_b16 v[2:3], v0, off
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: freeze_v2i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_b16 v0, v[0:1], off
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b16 v[2:3], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: freeze_v2i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u16 v0, v[0:1], off
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b16 v[2:3], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: freeze_v2i8:
 ; GFX11-GISEL:       ; %bb.0:
@@ -12423,20 +12498,36 @@ define void @freeze_v3i8(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
 ; GFX10-GISEL-NEXT:    global_store_byte_d16_hi v[2:3], v0, off offset:2
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: freeze_v3i8:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    global_load_b32 v0, v[0:1], off
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    v_lshrrev_b16 v1, 8, v0
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v4, 0xff, v0
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v1, v4, v1
-; GFX11-SDAG-NEXT:    s_clause 0x1
-; GFX11-SDAG-NEXT:    global_store_b8 v[2:3], v0, off offset:2
-; GFX11-SDAG-NEXT:    global_store_b16 v[2:3], v1, off
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: freeze_v3i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_b32 v1, v[0:1], off
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v4.h, 0
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b16 v0.l, 8, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v0.l, 8, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_clause 0x1
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[2:3], v4, off offset:2
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b16 v[2:3], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: freeze_v3i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b16 v1, 8, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v1, v4, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_clause 0x1
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[2:3], v0, off offset:2
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b16 v[2:3], v1, off
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: freeze_v3i8:
 ; GFX11-GISEL:       ; %bb.0:
@@ -13407,14 +13498,23 @@ define void @freeze_v2i1(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
 ; GFX10-GISEL-NEXT:    global_store_byte v[2:3], v0, off
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: freeze_v2i1:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    global_load_u8 v0, v[0:1], off
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 3, v0
-; GFX11-SDAG-NEXT:    global_store_b8 v[2:3], v0, off
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: freeze_v2i1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 3
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[2:3], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: freeze_v2i1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 3, v0
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[2:3], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: freeze_v2i1:
 ; GFX11-GISEL:       ; %bb.0:
@@ -13573,14 +13673,23 @@ define void @freeze_v3i1(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
 ; GFX10-GISEL-NEXT:    global_store_byte v[2:3], v0, off
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: freeze_v3i1:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    global_load_u8 v0, v[0:1], off
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 7, v0
-; GFX11-SDAG-NEXT:    global_store_b8 v[2:3], v0, off
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: freeze_v3i1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 7
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[2:3], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: freeze_v3i1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 7, v0
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[2:3], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: freeze_v3i1:
 ; GFX11-GISEL:       ; %bb.0:
@@ -13863,20 +13972,35 @@ define void @freeze_v2i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
 ; GFX10-GISEL-NEXT:    global_store_byte v[2:3], v0, off
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: freeze_v2i1_vcc:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    global_load_b64 v[0:1], v[0:1], off
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    v_lshlrev_b16 v1, 1, v1
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 3, v0
-; GFX11-SDAG-NEXT:    global_store_b8 v[2:3], v0, off
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: freeze_v2i1_vcc:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_b64 v[4:5], v[0:1], off
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v5
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v4
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v0.l, 1, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 3
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[2:3], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: freeze_v2i1_vcc:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_b64 v[0:1], v[0:1], off
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 1, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 3, v0
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[2:3], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: freeze_v2i1_vcc:
 ; GFX11-GISEL:       ; %bb.0:
@@ -14089,24 +14213,43 @@ define void @freeze_v3i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
 ; GFX10-GISEL-NEXT:    global_store_byte v[2:3], v0, off
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: freeze_v3i1_vcc:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    global_load_b96 v[4:6], v[0:1], off
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v5
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v4
-; GFX11-SDAG-NEXT:    v_lshlrev_b16 v0, 1, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v6
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v1, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX11-SDAG-NEXT:    v_lshlrev_b16 v1, 2, v4
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 7, v0
-; GFX11-SDAG-NEXT:    global_store_b8 v[2:3], v0, off
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: freeze_v3i1_vcc:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_b96 v[4:6], v[0:1], off
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v5
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v4
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v0.l, 1, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v6
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 2, v4.l
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 7
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[2:3], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: freeze_v3i1_vcc:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_b96 v[4:6], v[0:1], off
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v0, 1, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v1, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 2, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 7, v0
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[2:3], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: freeze_v3i1_vcc:
 ; GFX11-GISEL:       ; %bb.0:
@@ -14361,28 +14504,52 @@ define void @freeze_v4i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) {
 ; GFX10-GISEL-NEXT:    global_store_byte v[2:3], v0, off
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: freeze_v4i1_vcc:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    global_load_b128 v[4:7], v[0:1], off
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v5
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v4
-; GFX11-SDAG-NEXT:    v_lshlrev_b16 v0, 1, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v6
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v1, v0
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX11-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v7
-; GFX11-SDAG-NEXT:    v_lshlrev_b16 v4, 2, v4
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v4
-; GFX11-SDAG-NEXT:    v_lshlrev_b16 v1, 3, v1
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 15, v0
-; GFX11-SDAG-NEXT:    global_store_b8 v[2:3], v0, off
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: freeze_v4i1_vcc:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_b128 v[4:7], v[0:1], off
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v5
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v4
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v0.l, 1, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v6
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 2, v4.l
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v5.l
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 3, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 15
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[2:3], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: freeze_v4i1_vcc:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_b128 v[4:7], v[0:1], off
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v0, 1, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v1, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v4, 2, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 3, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 15, v0
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[2:3], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: freeze_v4i1_vcc:
 ; GFX11-GISEL:       ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/frem.ll b/llvm/test/CodeGen/AMDGPU/frem.ll
index 5febd5256e794..fbe253e95d210 100644
--- a/llvm/test/CodeGen/AMDGPU/frem.ll
+++ b/llvm/test/CodeGen/AMDGPU/frem.ll
@@ -4,7 +4,8 @@
 ; RUN:  llc -amdgpu-scalarize-global-loads=false -enable-misched=0 -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=VI %s
 ; RUN:  llc -amdgpu-scalarize-global-loads=false -enable-misched=0 -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX9 %s
 ; RUN:  llc -amdgpu-scalarize-global-loads=false -enable-misched=0 -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s
-; RUN:  llc -amdgpu-scalarize-global-loads=false -enable-misched=0 -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX11 %s
+; RUN:  llc -amdgpu-scalarize-global-loads=false -enable-misched=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN:  llc -amdgpu-scalarize-global-loads=false -enable-misched=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11,GFX11-FAKE16 %s
 ; RUN:  llc -amdgpu-scalarize-global-loads=false -enable-misched=0 -mtriple=amdgcn -mcpu=gfx1150 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX1150 %s
 
 define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1,
@@ -180,41 +181,79 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; GFX10-NEXT:    global_store_short v0, v1, s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: frem_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_load_u16 v1, v0, s[2:3]
-; GFX11-NEXT:    global_load_u16 v2, v0, s[4:5] offset:8
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v3, v1
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v4, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_rcp_f32_e32 v4, v4
-; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_mul_f32_e32 v3, v3, v4
-; GFX11-NEXT:    v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fmac_f32_e32 v3, v5, v4
-; GFX11-NEXT:    v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f32_e32 v4, v5, v4
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff800000, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v3, v4, v3
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v3, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_div_fixup_f16 v3, v3, v2, v1
-; GFX11-NEXT:    v_trunc_f16_e32 v3, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_fma_f16 v1, -v3, v2, v1
-; GFX11-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: frem_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v2, s[2:3]
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v1, v2, s[4:5] offset:8
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v3, v0.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v4, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v7, -v5, v3, v6 op_sel_hi:[1,0,1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v3, v7, v4
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v5, -v5, v3, v6 op_sel_hi:[1,0,1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v4, v5, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xff800000, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_div_fixup_f16 v0.h, v0.h, v1.l, v0.l
+; GFX11-TRUE16-NEXT:    v_trunc_f16_e32 v0.h, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.h, v1.l, v0.l
+; GFX11-TRUE16-NEXT:    global_store_b16 v2, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: frem_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3]
+; GFX11-FAKE16-NEXT:    global_load_u16 v2, v0, s[4:5] offset:8
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v3, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v4, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v4, v4
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v3, v5, v4
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v4, v5, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff800000, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_div_fixup_f16 v3, v3, v2, v1
+; GFX11-FAKE16-NEXT:    v_trunc_f16_e32 v3, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_f16 v1, -v3, v2, v1
+; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX1150-LABEL: frem_f16:
 ; GFX1150:       ; %bb.0:
@@ -377,25 +416,45 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
 ; GFX10-NEXT:    global_store_short v0, v1, s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: fast_frem_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_load_u16 v1, v0, s[2:3]
-; GFX11-NEXT:    global_load_u16 v2, v0, s[4:5] offset:8
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_rcp_f16_e32 v3, v2
-; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_mul_f16_e32 v3, v1, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_trunc_f16_e32 v3, v3
-; GFX11-NEXT:    v_fma_f16 v1, -v3, v2, v1
-; GFX11-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: fast_frem_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v2, s[2:3]
+; GFX11-TRUE16-NEXT:    global_load_d16_hi_b16 v0, v2, s[4:5] offset:8
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_rcp_f16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v1.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_trunc_f16_e32 v1.l, v1.l
+; GFX11-TRUE16-NEXT:    v_fma_f16 v0.l, -v1.l, v0.h, v0.l
+; GFX11-TRUE16-NEXT:    global_store_b16 v2, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: fast_frem_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3]
+; GFX11-FAKE16-NEXT:    global_load_u16 v2, v0, s[4:5] offset:8
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_rcp_f16_e32 v3, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v3, v1, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_trunc_f16_e32 v3, v3
+; GFX11-FAKE16-NEXT:    v_fma_f16 v1, -v3, v2, v1
+; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX1150-LABEL: fast_frem_f16:
 ; GFX1150:       ; %bb.0:
@@ -542,25 +601,45 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(
 ; GFX10-NEXT:    global_store_short v0, v1, s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: unsafe_frem_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_load_u16 v1, v0, s[2:3]
-; GFX11-NEXT:    global_load_u16 v2, v0, s[4:5] offset:8
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_rcp_f16_e32 v3, v2
-; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_mul_f16_e32 v3, v1, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_trunc_f16_e32 v3, v3
-; GFX11-NEXT:    v_fma_f16 v1, -v3, v2, v1
-; GFX11-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: unsafe_frem_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v2, s[2:3]
+; GFX11-TRUE16-NEXT:    global_load_d16_hi_b16 v0, v2, s[4:5] offset:8
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_rcp_f16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v1.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_trunc_f16_e32 v1.l, v1.l
+; GFX11-TRUE16-NEXT:    v_fma_f16 v0.l, -v1.l, v0.h, v0.l
+; GFX11-TRUE16-NEXT:    global_store_b16 v2, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: unsafe_frem_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3]
+; GFX11-FAKE16-NEXT:    global_load_u16 v2, v0, s[4:5] offset:8
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_rcp_f16_e32 v3, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v3, v1, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_trunc_f16_e32 v3, v3
+; GFX11-FAKE16-NEXT:    v_fma_f16 v1, -v3, v2, v1
+; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX1150-LABEL: unsafe_frem_f16:
 ; GFX1150:       ; %bb.0:
@@ -2109,65 +2188,128 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: frem_v2f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_load_b32 v1, v0, s[2:3]
-; GFX11-NEXT:    global_load_b32 v2, v0, s[4:5] offset:16
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v3, v1
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v4, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_rcp_f32_e32 v4, v4
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v7, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_rcp_f32_e32 v7, v7
-; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_mul_f32_e32 v3, v3, v4
-; GFX11-NEXT:    v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fmac_f32_e32 v3, v5, v4
-; GFX11-NEXT:    v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f32_e32 v4, v5, v4
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff800000, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add_f32_e32 v3, v4, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v3, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v5, v4
-; GFX11-NEXT:    v_div_fixup_f16 v3, v3, v2, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_mul_f32_e32 v5, v5, v7
-; GFX11-NEXT:    v_trunc_f16_e32 v3, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_fma_mix_f32 v8, -v2, v5, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX11-NEXT:    v_fma_f16 v3, -v3, v2, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fmac_f32_e32 v5, v8, v7
-; GFX11-NEXT:    v_fma_mix_f32 v1, -v2, v5, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f32_e32 v1, v1, v7
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v1, v1, v5
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_div_fixup_f16 v1, v1, v6, v4
-; GFX11-NEXT:    v_trunc_f16_e32 v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fma_f16 v1, -v1, v6, v4
-; GFX11-NEXT:    v_pack_b32_f16 v1, v3, v1
-; GFX11-NEXT:    global_store_b32 v0, v1, s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: frem_v2f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    global_load_b32 v2, v1, s[2:3]
+; GFX11-TRUE16-NEXT:    global_load_b32 v3, v1, s[4:5] offset:16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v2.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v4, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v2.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v4
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v7, -v5, v0, v6 op_sel_hi:[1,0,1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v0, v7, v4
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v5, -v5, v0, v6 op_sel_hi:[1,0,1]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v7, v6.l
+; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v7, v7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v4, v5, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xff800000, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, v4, v0
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v5, v4.l
+; GFX11-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v5, v5, v7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v8, -v3, v5, v2 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.l, v3.l, v2.l
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v5, v8, v7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v2, -v3, v5, v2 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v2, v2, v7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xff800000, v2
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v2
+; GFX11-TRUE16-NEXT:    v_div_fixup_f16 v0.h, v0.h, v6.l, v4.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_trunc_f16_e32 v0.h, v0.h
+; GFX11-TRUE16-NEXT:    v_fma_f16 v0.h, -v0.h, v6.l, v4.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    global_store_b32 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: frem_v2f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v0, s[2:3]
+; GFX11-FAKE16-NEXT:    global_load_b32 v2, v0, s[4:5] offset:16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v3, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v4, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v4, v4
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v7, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v7, v7
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v3, v5, v4
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v4, v5, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff800000, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v5, v4
+; GFX11-FAKE16-NEXT:    v_div_fixup_f16 v3, v3, v2, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v5, v5, v7
+; GFX11-FAKE16-NEXT:    v_trunc_f16_e32 v3, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v8, -v2, v5, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX11-FAKE16-NEXT:    v_fma_f16 v3, -v3, v2, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v5, v8, v7
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v1, -v2, v5, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v1, v1, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, v1, v5
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_div_fixup_f16 v1, v1, v6, v4
+; GFX11-FAKE16-NEXT:    v_trunc_f16_e32 v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_f16 v1, -v1, v6, v4
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v1, v3, v1
+; GFX11-FAKE16-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX1150-LABEL: frem_v2f16:
 ; GFX1150:       ; %bb.0:
@@ -2683,110 +2825,217 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; GFX10-NEXT:    global_store_dwordx2 v4, v[0:1], s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: frem_v4f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-NEXT:    v_mov_b32_e32 v4, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_load_b64 v[0:1], v4, s[2:3]
-; GFX11-NEXT:    global_load_b64 v[2:3], v4, s[4:5] offset:32
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v5, v1
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v6, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v8, 16, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_rcp_f32_e32 v6, v6
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v9, v8
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_rcp_f32_e32 v9, v9
-; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_mul_f32_e32 v5, v5, v6
-; GFX11-NEXT:    v_fma_mix_f32 v7, -v3, v5, v1 op_sel_hi:[1,0,1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fmac_f32_e32 v5, v7, v6
-; GFX11-NEXT:    v_fma_mix_f32 v7, -v3, v5, v1 op_sel_hi:[1,0,1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f32_e32 v6, v7, v6
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff800000, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add_f32_e32 v5, v6, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v5, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v7, v6
-; GFX11-NEXT:    v_div_fixup_f16 v5, v5, v3, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_mul_f32_e32 v7, v7, v9
-; GFX11-NEXT:    v_trunc_f16_e32 v5, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_fma_mix_f32 v10, -v3, v7, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX11-NEXT:    v_fma_f16 v5, -v5, v3, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fmac_f32_e32 v7, v10, v9
-; GFX11-NEXT:    v_fma_mix_f32 v1, -v3, v7, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v3, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f32_e32 v1, v1, v9
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add_f32_e32 v1, v1, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_div_fixup_f16 v1, v1, v8, v6
-; GFX11-NEXT:    v_trunc_f16_e32 v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_fma_f16 v1, -v1, v8, v6
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v8, v7
-; GFX11-NEXT:    v_pack_b32_f16 v1, v5, v1
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v5, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_rcp_f32_e32 v8, v8
-; GFX11-NEXT:    v_rcp_f32_e32 v5, v5
-; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_mul_f32_e32 v3, v3, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fma_mix_f32 v6, -v2, v3, v0 op_sel_hi:[1,0,1]
-; GFX11-NEXT:    v_fmac_f32_e32 v3, v6, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fma_mix_f32 v6, -v2, v3, v0 op_sel_hi:[1,0,1]
-; GFX11-NEXT:    v_mul_f32_e32 v5, v6, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xff800000, v5
-; GFX11-NEXT:    v_add_f32_e32 v3, v5, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v3, v3
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v6, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_div_fixup_f16 v3, v3, v2, v0
-; GFX11-NEXT:    v_mul_f32_e32 v6, v6, v8
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_trunc_f16_e32 v3, v3
-; GFX11-NEXT:    v_fma_mix_f32 v9, -v2, v6, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_fma_f16 v3, -v3, v2, v0
-; GFX11-NEXT:    v_fmac_f32_e32 v6, v9, v8
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fma_mix_f32 v0, -v2, v6, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX11-NEXT:    v_mul_f32_e32 v0, v0, v8
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff800000, v0
-; GFX11-NEXT:    v_add_f32_e32 v0, v0, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    v_div_fixup_f16 v0, v0, v7, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_trunc_f16_e32 v0, v0
-; GFX11-NEXT:    v_fma_f16 v0, -v0, v7, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_pack_b32_f16 v0, v3, v0
-; GFX11-NEXT:    global_store_b64 v4, v[0:1], s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: frem_v4f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v5, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    global_load_b64 v[1:2], v5, s[2:3]
+; GFX11-TRUE16-NEXT:    global_load_b64 v[3:4], v5, s[4:5] offset:32
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v2.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v6, v4.l
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v6, v6
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v9, v8.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v9, v9
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v6
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v7, -v4, v0, v2 op_sel_hi:[1,0,1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v0, v7, v6
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v7, -v4, v0, v2 op_sel_hi:[1,0,1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v6, v7, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xff800000, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, v6, v0
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v7, v6.l
+; GFX11-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.l, v4.l, v2.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v7, v7, v9
+; GFX11-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v10, -v4, v7, v2 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX11-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.l, v4.l, v2.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v7, v10, v9
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v2, -v4, v7, v2 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v4, v3.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v2, v2, v9
+; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xff800000, v2
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, v2, v7
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v2
+; GFX11-TRUE16-NEXT:    v_div_fixup_f16 v0.h, v0.h, v8.l, v6.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_trunc_f16_e32 v0.h, v0.h
+; GFX11-TRUE16-NEXT:    v_fma_f16 v0.h, -v0.h, v8.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v3.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v2, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v1.l
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v8, -v6, v0, v7 op_sel_hi:[1,0,1]
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v0, v8, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v6, -v6, v0, v7 op_sel_hi:[1,0,1]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v3
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v4, v6, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v8, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xff800000, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v8, v8
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, v4, v0
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v6, v4.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.l, v3.l, v1.l
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v6, v6, v8
+; GFX11-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v9, -v3, v6, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.l, v3.l, v1.l
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v6, v9, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v1, -v3, v6, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v1, v1, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, v1, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v1
+; GFX11-TRUE16-NEXT:    v_div_fixup_f16 v0.h, v0.h, v7.l, v4.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_trunc_f16_e32 v0.h, v0.h
+; GFX11-TRUE16-NEXT:    v_fma_f16 v0.h, -v0.h, v7.l, v4.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v1, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    global_store_b64 v5, v[1:2], s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: frem_v4f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    global_load_b64 v[0:1], v4, s[2:3]
+; GFX11-FAKE16-NEXT:    global_load_b64 v[2:3], v4, s[4:5] offset:32
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v5, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v6, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v6, v6
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v9, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v9, v9
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v5, v5, v6
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v7, -v3, v5, v1 op_sel_hi:[1,0,1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v5, v7, v6
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v7, -v3, v5, v1 op_sel_hi:[1,0,1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v6, v7, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff800000, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v5, v6, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v5, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v7, v6
+; GFX11-FAKE16-NEXT:    v_div_fixup_f16 v5, v5, v3, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v7, v7, v9
+; GFX11-FAKE16-NEXT:    v_trunc_f16_e32 v5, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v10, -v3, v7, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX11-FAKE16-NEXT:    v_fma_f16 v5, -v5, v3, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v7, v10, v9
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v1, -v3, v7, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v3, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v1, v1, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, v1, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_div_fixup_f16 v1, v1, v8, v6
+; GFX11-FAKE16-NEXT:    v_trunc_f16_e32 v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_fma_f16 v1, -v1, v8, v6
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v8, v7
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v1, v5, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v5, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v8, v8
+; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v5, v5
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v3, v3, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v6, -v2, v3, v0 op_sel_hi:[1,0,1]
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v3, v6, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v6, -v2, v3, v0 op_sel_hi:[1,0,1]
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v5, v6, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff800000, v5
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, v5, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v6, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_div_fixup_f16 v3, v3, v2, v0
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v6, v6, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_trunc_f16_e32 v3, v3
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v9, -v2, v6, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_fma_f16 v3, -v3, v2, v0
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v6, v9, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v0, -v2, v6, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v0, v0, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff800000, v0
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, v0, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_div_fixup_f16 v0, v0, v7, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_trunc_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_fma_f16 v0, -v0, v7, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v3, v0
+; GFX11-FAKE16-NEXT:    global_store_b64 v4, v[0:1], s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX1150-LABEL: frem_v4f16:
 ; GFX1150:       ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll b/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
index 7061685729804..0db2a1679197e 100644
--- a/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
@@ -1,6 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -enable-var-scope -check-prefix=GFX11 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define void @void_func_i1_inreg(i1 inreg %arg0) #0 {
 ; GFX9-LABEL: void_func_i1_inreg:
@@ -33,12 +34,19 @@ define void @void_func_i8_inreg(i8 inreg %arg0) #0 {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: void_func_i8_inreg:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mov_b32_e32 v0, s0
-; GFX11-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: void_func_i8_inreg:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, s0
+; GFX11-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: void_func_i8_inreg:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, s0
+; GFX11-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   store i8 %arg0, ptr addrspace(1) poison
   ret void
 }
@@ -52,12 +60,19 @@ define void @void_func_i16_inreg(i16 inreg %arg0) #0 {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: void_func_i16_inreg:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mov_b32_e32 v0, s0
-; GFX11-NEXT:    global_store_b16 v[0:1], v0, off
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: void_func_i16_inreg:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, s0
+; GFX11-TRUE16-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: void_func_i16_inreg:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, s0
+; GFX11-FAKE16-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   store i16 %arg0, ptr addrspace(1) poison
   ret void
 }
@@ -110,12 +125,19 @@ define void @void_func_f16_inreg(half inreg %arg0) #0 {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: void_func_f16_inreg:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mov_b32_e32 v0, s0
-; GFX11-NEXT:    global_store_b16 v[0:1], v0, off
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: void_func_f16_inreg:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, s0
+; GFX11-TRUE16-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: void_func_f16_inreg:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, s0
+; GFX11-FAKE16-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   store half %arg0, ptr addrspace(1) poison
   ret void
 }
@@ -1292,45 +1314,85 @@ define void @void_func_v32i32_i1_i8_i16_f32_inreg(<32 x i32> inreg %arg0, i1 inr
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: void_func_v32i32_i1_i8_i16_f32_inreg:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v21, v1 :: v_dual_mov_b32 v20, v0
-; GFX11-NEXT:    v_dual_mov_b32 v18, s28 :: v_dual_mov_b32 v19, s29
-; GFX11-NEXT:    global_store_b128 v[0:1], v[10:13], off dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    global_store_b128 v[0:1], v[6:9], off dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    global_store_b128 v[0:1], v[2:5], off dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    global_store_b128 v[0:1], v[18:21], off dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    v_dual_mov_b32 v0, s24 :: v_dual_mov_b32 v1, s25
-; GFX11-NEXT:    v_dual_mov_b32 v2, s26 :: v_dual_mov_b32 v3, s27
-; GFX11-NEXT:    v_dual_mov_b32 v4, s20 :: v_dual_mov_b32 v5, s21
-; GFX11-NEXT:    v_dual_mov_b32 v6, s22 :: v_dual_mov_b32 v7, s23
-; GFX11-NEXT:    v_dual_mov_b32 v8, s16 :: v_dual_mov_b32 v9, s17
-; GFX11-NEXT:    v_dual_mov_b32 v10, s18 :: v_dual_mov_b32 v11, s19
-; GFX11-NEXT:    v_dual_mov_b32 v18, s0 :: v_dual_mov_b32 v19, s1
-; GFX11-NEXT:    v_dual_mov_b32 v20, s2 :: v_dual_mov_b32 v21, s3
-; GFX11-NEXT:    v_and_b32_e32 v12, 1, v14
-; GFX11-NEXT:    global_store_b128 v[0:1], v[0:3], off dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    global_store_b128 v[0:1], v[4:7], off dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    global_store_b128 v[0:1], v[8:11], off dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    global_store_b128 v[0:1], v[18:21], off dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    global_store_b8 v[0:1], v12, off dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    global_store_b8 v[0:1], v15, off dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    global_store_b16 v[0:1], v16, off dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    global_store_b16 v[0:1], v17, off dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: void_func_v32i32_i1_i8_i16_f32_inreg:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v21, v1 :: v_dual_mov_b32 v20, v0
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v18, s28 :: v_dual_mov_b32 v19, s29
+; GFX11-TRUE16-NEXT:    global_store_b128 v[0:1], v[10:13], off dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    global_store_b128 v[0:1], v[6:9], off dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v6, s24 :: v_dual_mov_b32 v7, s25
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v8, s26 :: v_dual_mov_b32 v9, s27
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v10, s20 :: v_dual_mov_b32 v11, s21
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v12, s22 :: v_dual_mov_b32 v13, s23
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v22, s16 :: v_dual_mov_b32 v23, s17
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v24, s18 :: v_dual_mov_b32 v25, s19
+; GFX11-TRUE16-NEXT:    global_store_b128 v[0:1], v[2:5], off dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    global_store_b128 v[0:1], v[18:21], off dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    global_store_b128 v[0:1], v[6:9], off dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    global_store_b128 v[0:1], v[10:13], off dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    global_store_b128 v[0:1], v[22:25], off dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 1, v14
+; GFX11-TRUE16-NEXT:    global_store_b128 v[0:1], v[0:3], off dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    global_store_b8 v[0:1], v4, off dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    global_store_b8 v[0:1], v15, off dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    global_store_b16 v[0:1], v16, off dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    global_store_b16 v[0:1], v17, off dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: void_func_v32i32_i1_i8_i16_f32_inreg:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v21, v1 :: v_dual_mov_b32 v20, v0
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v18, s28 :: v_dual_mov_b32 v19, s29
+; GFX11-FAKE16-NEXT:    global_store_b128 v[0:1], v[10:13], off dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    global_store_b128 v[0:1], v[6:9], off dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    global_store_b128 v[0:1], v[2:5], off dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    global_store_b128 v[0:1], v[18:21], off dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v0, s24 :: v_dual_mov_b32 v1, s25
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v2, s26 :: v_dual_mov_b32 v3, s27
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v4, s20 :: v_dual_mov_b32 v5, s21
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v6, s22 :: v_dual_mov_b32 v7, s23
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v8, s16 :: v_dual_mov_b32 v9, s17
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v10, s18 :: v_dual_mov_b32 v11, s19
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v18, s0 :: v_dual_mov_b32 v19, s1
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v20, s2 :: v_dual_mov_b32 v21, s3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 1, v14
+; GFX11-FAKE16-NEXT:    global_store_b128 v[0:1], v[0:3], off dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    global_store_b128 v[0:1], v[4:7], off dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    global_store_b128 v[0:1], v[8:11], off dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    global_store_b128 v[0:1], v[18:21], off dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    global_store_b8 v[0:1], v12, off dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    global_store_b8 v[0:1], v15, off dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    global_store_b16 v[0:1], v16, off dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    global_store_b16 v[0:1], v17, off dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   store volatile <32 x i32> %arg0, ptr addrspace(1) poison
   store volatile i1 %arg1, ptr addrspace(1) poison
   store volatile i8 %arg2, ptr addrspace(1) poison
@@ -1758,12 +1820,19 @@ define void @void_func_bf16_inreg(bfloat inreg %arg0) #0 {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: void_func_bf16_inreg:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mov_b32_e32 v0, s0
-; GFX11-NEXT:    global_store_b16 v[0:1], v0, off
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: void_func_bf16_inreg:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, s0
+; GFX11-TRUE16-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: void_func_bf16_inreg:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, s0
+; GFX11-FAKE16-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   store bfloat %arg0, ptr addrspace(1) poison
   ret void
 }
diff --git a/llvm/test/CodeGen/AMDGPU/function-args.ll b/llvm/test/CodeGen/AMDGPU/function-args.ll
index d0a3811314029..81b8b36180746 100644
--- a/llvm/test/CodeGen/AMDGPU/function-args.ll
+++ b/llvm/test/CodeGen/AMDGPU/function-args.ll
@@ -2,7 +2,8 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CIGFX89,CI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CIGFX89,GFX89,VI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CIGFX89,GFX89,GFX9 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define void @void_func_i1(i1 %arg0) #0 {
 ; CIGFX89-LABEL: void_func_i1:
@@ -943,18 +944,31 @@ define void @void_func_v2i8(<2 x i8> %arg0) #0 {
 ; GFX89-NEXT:    s_waitcnt vmcnt(0)
 ; GFX89-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: void_func_v2i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    s_mov_b64 s[0:1], 0
-; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: void_func_v2i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    s_mov_b64 s[0:1], 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: void_func_v2i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    s_mov_b64 s[0:1], 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   store <2 x i8> %arg0, ptr addrspace(1) null
   ret void
 }
@@ -1022,20 +1036,35 @@ define void @void_func_v3i8(<3 x i8> %arg0) #0 {
 ; GFX89-NEXT:    s_waitcnt vmcnt(0)
 ; GFX89-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: void_func_v3i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    s_mov_b64 s[0:1], 2
-; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    buffer_store_b8 v2, off, s[0:3], 0
-; GFX11-NEXT:    s_mov_b64 s[0:1], 0
-; GFX11-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: void_func_v3i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    s_mov_b64 s[0:1], 2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    buffer_store_b8 v2, off, s[0:3], 0
+; GFX11-TRUE16-NEXT:    s_mov_b64 s[0:1], 0
+; GFX11-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: void_func_v3i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    s_mov_b64 s[0:1], 2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    buffer_store_b8 v2, off, s[0:3], 0
+; GFX11-FAKE16-NEXT:    s_mov_b64 s[0:1], 0
+; GFX11-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   store <3 x i8> %arg0, ptr addrspace(1) null
   ret void
 }
@@ -1075,25 +1104,45 @@ define void @void_func_v4i8(<4 x i8> %arg0) #0 {
 ; GFX89-NEXT:    s_waitcnt vmcnt(0)
 ; GFX89-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: void_func_v4i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_lshlrev_b16 v3, 8, v3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    s_mov_b64 s[0:1], 0
-; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    buffer_store_b32 v0, off, s[0:3], 0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: void_func_v4i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    s_mov_b64 s[0:1], 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT:    buffer_store_b32 v0, off, s[0:3], 0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: void_func_v4i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b64 s[0:1], 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    buffer_store_b32 v0, off, s[0:3], 0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   store <4 x i8> %arg0, ptr addrspace(1) null
   ret void
 }
@@ -1137,26 +1186,47 @@ define void @void_func_v5i8(<5 x i8> %arg0) #0 {
 ; GFX89-NEXT:    s_waitcnt vmcnt(0)
 ; GFX89-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: void_func_v5i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_lshlrev_b16 v3, 8, v3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    s_mov_b64 s[0:1], 4
-; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    buffer_store_b8 v4, off, s[0:3], 0
-; GFX11-NEXT:    s_mov_b64 s[0:1], 0
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    buffer_store_b32 v0, off, s[0:3], 0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: void_func_v5i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    s_mov_b64 s[0:1], 4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT:    buffer_store_b8 v4, off, s[0:3], 0
+; GFX11-TRUE16-NEXT:    s_mov_b64 s[0:1], 0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT:    buffer_store_b32 v0, off, s[0:3], 0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: void_func_v5i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    s_mov_b64 s[0:1], 4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    buffer_store_b8 v4, off, s[0:3], 0
+; GFX11-FAKE16-NEXT:    s_mov_b64 s[0:1], 0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    buffer_store_b32 v0, off, s[0:3], 0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   store <5 x i8> %arg0, ptr addrspace(1) null
   ret void
 }
@@ -1210,33 +1280,61 @@ define void @void_func_v8i8(<8 x i8> %arg0) #0 {
 ; GFX89-NEXT:    s_waitcnt vmcnt(0)
 ; GFX89-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: void_func_v8i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b16 v5, 8, v5
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_lshlrev_b16 v7, 8, v7
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_lshlrev_b16 v3, 8, v3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v5, v6, v7
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    s_mov_b64 s[0:1], 0
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 16, v1
-; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v4
-; GFX11-NEXT:    buffer_store_b64 v[0:1], off, s[0:3], 0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: void_func_v8i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v4.l, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v0.h, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    s_mov_b64 s[0:1], 0
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v2.l, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v4
+; GFX11-TRUE16-NEXT:    buffer_store_b64 v[0:1], off, s[0:3], 0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: void_func_v8i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_mov_b64 s[0:1], 0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v4
+; GFX11-FAKE16-NEXT:    buffer_store_b64 v[0:1], off, s[0:3], 0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   store <8 x i8> %arg0, ptr addrspace(1) null
   ret void
 }
@@ -1318,50 +1416,95 @@ define void @void_func_v16i8(<16 x i8> %arg0) #0 {
 ; GFX89-NEXT:    s_waitcnt vmcnt(0)
 ; GFX89-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: void_func_v16i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v13
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v15
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_lshlrev_b16 v9, 8, v9
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v11
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_lshlrev_b16 v5, 8, v5
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_lshlrev_b16 v7, 8, v7
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_lshlrev_b16 v3, 8, v3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v13, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v9
-; GFX11-NEXT:    v_or_b32_e32 v10, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v5, v6, v7
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v1
-; GFX11-NEXT:    v_or_b32_e32 v3, v9, v12
-; GFX11-NEXT:    v_or_b32_e32 v2, v8, v2
-; GFX11-NEXT:    v_or_b32_e32 v1, v4, v5
-; GFX11-NEXT:    s_mov_b64 s[0:1], 0
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v6
-; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    buffer_store_b128 v[0:3], off, s[0:3], 0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: void_func_v16i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.l, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.l, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.l, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.l, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v13.l, v8.h, v13.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v12.l, v9.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v8.l, v9.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v5.h, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v0.h, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v2.l, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v13
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v9, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v8, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v4, v5
+; GFX11-TRUE16-NEXT:    s_mov_b64 s[0:1], 0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT:    buffer_store_b128 v[0:3], off, s[0:3], 0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: void_func_v16i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, 8, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v9, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v8, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v4, v5
+; GFX11-FAKE16-NEXT:    s_mov_b64 s[0:1], 0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT:    buffer_store_b128 v[0:3], off, s[0:3], 0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   store <16 x i8> %arg0, ptr addrspace(1) null
   ret void
 }
@@ -1507,92 +1650,180 @@ define void @void_func_v32i8(<32 x i8> %arg0) #0 {
 ; GFX89-NEXT:    s_waitcnt vmcnt(0)
 ; GFX89-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: void_func_v32i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    scratch_load_u8 v31, off, s32
-; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_lshlrev_b16 v3, 8, v3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_lshlrev_b16 v9, 8, v9
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v11
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_lshlrev_b16 v17, 8, v17
-; GFX11-NEXT:    v_and_b32_e32 v16, 0xff, v16
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v13
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_lshlrev_b16 v15, 8, v15
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_lshlrev_b16 v5, 8, v5
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_lshlrev_b16 v7, 8, v7
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_lshlrev_b16 v29, 8, v29
-; GFX11-NEXT:    v_and_b32_e32 v28, 0xff, v28
-; GFX11-NEXT:    v_and_b32_e32 v30, 0xff, v30
-; GFX11-NEXT:    v_lshlrev_b16 v25, 8, v25
-; GFX11-NEXT:    v_and_b32_e32 v24, 0xff, v24
-; GFX11-NEXT:    v_lshlrev_b16 v27, 8, v27
-; GFX11-NEXT:    v_and_b32_e32 v26, 0xff, v26
-; GFX11-NEXT:    v_lshlrev_b16 v21, 8, v21
-; GFX11-NEXT:    v_and_b32_e32 v20, 0xff, v20
-; GFX11-NEXT:    v_lshlrev_b16 v23, 8, v23
-; GFX11-NEXT:    v_and_b32_e32 v22, 0xff, v22
-; GFX11-NEXT:    v_lshlrev_b16 v19, 8, v19
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xff, v18
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v9
-; GFX11-NEXT:    v_or_b32_e32 v9, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v11, v16, v17
-; GFX11-NEXT:    v_lshlrev_b32_e32 v17, 16, v1
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v13, v14, v15
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v5, v6, v7
-; GFX11-NEXT:    v_or_b32_e32 v2, v28, v29
-; GFX11-NEXT:    v_or_b32_e32 v3, v24, v25
-; GFX11-NEXT:    v_or_b32_e32 v6, v26, v27
-; GFX11-NEXT:    v_or_b32_e32 v7, v20, v21
-; GFX11-NEXT:    v_or_b32_e32 v10, v22, v23
-; GFX11-NEXT:    v_or_b32_e32 v14, v18, v19
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v16, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v18, 0xffff, v2
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v7
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_or_b32_e32 v6, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v5, v7, v10
-; GFX11-NEXT:    v_or_b32_e32 v4, v11, v14
-; GFX11-NEXT:    v_or_b32_e32 v3, v12, v13
-; GFX11-NEXT:    v_or_b32_e32 v2, v8, v9
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v17
-; GFX11-NEXT:    s_mov_b64 s[0:1], 16
-; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v31
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_or_b32_e32 v1, v30, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_or_b32_e32 v7, v18, v1
-; GFX11-NEXT:    v_or_b32_e32 v1, v15, v16
-; GFX11-NEXT:    buffer_store_b128 v[4:7], off, s[0:3], 0
-; GFX11-NEXT:    s_mov_b64 s[0:1], 0
-; GFX11-NEXT:    buffer_store_b128 v[0:3], off, s[0:3], 0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: void_func_v32i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    scratch_load_d16_u8 v31, off, s32
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.l, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v11.h, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v12.l, 0xff, v20.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v8.l, 8, v29.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v8.h, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v9.l, 0xff, v30.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v9.h, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v10.h, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v11.l, 0xff, v26.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v12.h, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v13.l, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v13.h, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v14.l, 0xff, v16.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v14.h, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v15.l, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v6.l, v7.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v12.l, v11.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v16.l, v1.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v17.l, v3.h, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v18.l, v5.h, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v19.l, v7.h, v6.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v2.l, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v8.h, v8.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v10.l, v9.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v6.l, v11.l, v10.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v13.l, v12.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v10.l, v14.l, v13.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v11.l, v15.l, v14.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v13, 0xffff, v16
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v17
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff, v18
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v19
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v2
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v6
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v13, v14
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v4, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v15, v16
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v7, v8
+; GFX11-TRUE16-NEXT:    s_mov_b64 s[0:1], 16
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.l, 8, v31.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v9.l, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff, v10
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v11
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v9, v10
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v1, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v17, v18
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v12, v19
+; GFX11-TRUE16-NEXT:    buffer_store_b128 v[4:7], off, s[0:3], 0
+; GFX11-TRUE16-NEXT:    s_mov_b64 s[0:1], 0
+; GFX11-TRUE16-NEXT:    buffer_store_b128 v[0:3], off, s[0:3], 0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: void_func_v32i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    scratch_load_u8 v31, off, s32
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, 8, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v17, 8, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v15, 8, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v29, 8, v29
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v30, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v25, 8, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v27, 8, v27
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v21, 8, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v23, 8, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v19, 8, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v16, v17
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v14, v15
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v28, v29
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v24, v25
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v26, v27
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v20, v21
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v22, v23
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, v18, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v18, 0xffff, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v6
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v7, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v11, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v12, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v8, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v17
+; GFX11-FAKE16-NEXT:    s_mov_b64 s[0:1], 16
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v31
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v30, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v18, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v15, v16
+; GFX11-FAKE16-NEXT:    buffer_store_b128 v[4:7], off, s[0:3], 0
+; GFX11-FAKE16-NEXT:    s_mov_b64 s[0:1], 0
+; GFX11-FAKE16-NEXT:    buffer_store_b128 v[0:3], off, s[0:3], 0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   store <32 x i8> %arg0, ptr addrspace(1) null
   ret void
 }
@@ -1847,18 +2078,32 @@ define void @void_func_v2i24(<2 x i24> %arg0) #0 {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: void_func_v2i24:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_nc_u32_e32 v0, v0, v1
-; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    buffer_store_b8 v1, off, s[0:3], 0
-; GFX11-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: void_func_v2i24:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX11-TRUE16-NEXT:    buffer_store_b8 v1, off, s[0:3], 0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: void_func_v2i24:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    buffer_store_b8 v1, off, s[0:3], 0
+; GFX11-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %elt0 = extractelement <2 x i24> %arg0, i32 0
   %elt1 = extractelement <2 x i24> %arg0, i32 1
   %add = add i24 %elt0, %elt1
@@ -2436,19 +2681,33 @@ define void @void_func_byval_struct_i8_i32(ptr addrspace(5) byval({ i8, i32 }) %
 ; CIGFX89-NEXT:    s_waitcnt vmcnt(0)
 ; CIGFX89-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: void_func_byval_struct_i8_i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_b32 v0, off, s32 offset:4
-; GFX11-NEXT:    scratch_load_u8 v1, off, s32
-; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    buffer_store_b32 v0, off, s[0:3], 0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    buffer_store_b8 v1, off, s[0:3], 0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: void_func_byval_struct_i8_i32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_d16_u8 v0, off, s32
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v1, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    buffer_store_b32 v1, off, s[0:3], 0
+; GFX11-TRUE16-NEXT:    buffer_store_b8 v0, off, s[0:3], 0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: void_func_byval_struct_i8_i32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v0, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    scratch_load_u8 v1, off, s32
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    buffer_store_b32 v0, off, s[0:3], 0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    buffer_store_b8 v1, off, s[0:3], 0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %arg0.load = load { i8, i32 }, ptr addrspace(5) %arg0
   store { i8, i32 } %arg0.load, ptr addrspace(1) poison
   ret void
@@ -2532,30 +2791,55 @@ define void @void_func_byval_struct_i8_i32_x2(ptr addrspace(5) byval({ i8, i32 }
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: void_func_byval_struct_i8_i32_x2:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    scratch_load_u8 v1, off, s32 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    scratch_load_b32 v2, off, s32 offset:4 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    scratch_load_u8 v3, off, s32 offset:8 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    scratch_load_b32 v4, off, s32 offset:12 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    buffer_store_b32 v2, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    buffer_store_b8 v1, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    buffer_store_b32 v4, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    buffer_store_b8 v3, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    ds_store_b32 v0, v0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: void_func_byval_struct_i8_i32_x2:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    scratch_load_d16_u8 v1, off, s32 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v3, off, s32 offset:4 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    scratch_load_d16_u8 v2, off, s32 offset:8 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v4, off, s32 offset:12 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT:    buffer_store_b32 v3, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    buffer_store_b8 v1, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    buffer_store_b32 v4, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    buffer_store_b8 v2, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    ds_store_b32 v0, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: void_func_byval_struct_i8_i32_x2:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    scratch_load_u8 v1, off, s32 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v2, off, s32 offset:4 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    scratch_load_u8 v3, off, s32 offset:8 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v4, off, s32 offset:12 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT:    buffer_store_b32 v2, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    buffer_store_b8 v1, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    buffer_store_b32 v4, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    buffer_store_b8 v3, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    ds_store_b32 v0, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %arg0.load = load volatile { i8, i32 }, ptr addrspace(5) %arg0
   %arg1.load = load volatile { i8, i32 }, ptr addrspace(5) %arg1
   store volatile { i8, i32 } %arg0.load, ptr addrspace(1) poison
@@ -2760,52 +3044,99 @@ define void @void_func_v32i32_i1_i8_i16_bf16(<32 x i32> %arg0, i1 %arg1, i8 %arg
 ; GFX89-NEXT:    s_waitcnt vmcnt(0)
 ; GFX89-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: void_func_v32i32_i1_i8_i16_bf16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x5
-; GFX11-NEXT:    scratch_load_b32 v31, off, s32
-; GFX11-NEXT:    scratch_load_u8 v32, off, s32 offset:4
-; GFX11-NEXT:    scratch_load_u16 v33, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_u16 v34, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_u16 v35, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_u16 v36, off, s32 offset:20
-; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    s_waitcnt vmcnt(5)
-; GFX11-NEXT:    buffer_store_b128 v[28:31], off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    buffer_store_b128 v[24:27], off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    buffer_store_b128 v[20:23], off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    buffer_store_b128 v[16:19], off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_waitcnt vmcnt(4)
-; GFX11-NEXT:    v_and_b32_e32 v16, 1, v32
-; GFX11-NEXT:    buffer_store_b128 v[12:15], off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    buffer_store_b128 v[8:11], off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    buffer_store_b128 v[4:7], off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    buffer_store_b128 v[0:3], off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    buffer_store_b8 v16, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_waitcnt vmcnt(3)
-; GFX11-NEXT:    buffer_store_b8 v33, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_waitcnt vmcnt(2)
-; GFX11-NEXT:    buffer_store_b16 v34, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    buffer_store_b16 v35, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    buffer_store_b16 v36, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: void_func_v32i32_i1_i8_i16_bf16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x5
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-TRUE16-NEXT:    scratch_load_u8 v36, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v32, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v33, off, s32 offset:12
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v34, off, s32 offset:16
+; GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v35, off, s32 offset:20
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(5)
+; GFX11-TRUE16-NEXT:    buffer_store_b128 v[28:31], off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    buffer_store_b128 v[24:27], off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    buffer_store_b128 v[20:23], off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    buffer_store_b128 v[16:19], off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    buffer_store_b128 v[12:15], off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    buffer_store_b128 v[8:11], off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    buffer_store_b128 v[4:7], off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    buffer_store_b128 v[0:3], off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(4)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 1, v36
+; GFX11-TRUE16-NEXT:    buffer_store_b8 v0, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(3)
+; GFX11-TRUE16-NEXT:    buffer_store_b8 v32, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-TRUE16-NEXT:    buffer_store_b16 v33, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    buffer_store_b16 v34, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    buffer_store_b16 v35, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: void_func_v32i32_i1_i8_i16_bf16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x5
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-FAKE16-NEXT:    scratch_load_u8 v32, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v33, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v34, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v35, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_u16 v36, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(5)
+; GFX11-FAKE16-NEXT:    buffer_store_b128 v[28:31], off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    buffer_store_b128 v[24:27], off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    buffer_store_b128 v[20:23], off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    buffer_store_b128 v[16:19], off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(4)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 1, v32
+; GFX11-FAKE16-NEXT:    buffer_store_b128 v[12:15], off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    buffer_store_b128 v[8:11], off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    buffer_store_b128 v[4:7], off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    buffer_store_b128 v[0:3], off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    buffer_store_b8 v16, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(3)
+; GFX11-FAKE16-NEXT:    buffer_store_b8 v33, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-FAKE16-NEXT:    buffer_store_b16 v34, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    buffer_store_b16 v35, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    buffer_store_b16 v36, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   store volatile <32 x i32> %arg0, ptr addrspace(1) poison
   store volatile i1 %arg1, ptr addrspace(1) poison
   store volatile i8 %arg2, ptr addrspace(1) poison
@@ -4143,95 +4474,185 @@ define void @void_func_v32i32_v16i8(<32 x i32> %arg0, <16 x i8> %arg1) #0 {
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: void_func_v32i32_v16i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x10
-; GFX11-NEXT:    scratch_load_b32 v31, off, s32
-; GFX11-NEXT:    scratch_load_u8 v32, off, s32 offset:64
-; GFX11-NEXT:    scratch_load_u8 v33, off, s32 offset:60
-; GFX11-NEXT:    scratch_load_u8 v34, off, s32 offset:56
-; GFX11-NEXT:    scratch_load_u8 v35, off, s32 offset:52
-; GFX11-NEXT:    scratch_load_u8 v36, off, s32 offset:48
-; GFX11-NEXT:    scratch_load_u8 v37, off, s32 offset:44
-; GFX11-NEXT:    scratch_load_u8 v38, off, s32 offset:40
-; GFX11-NEXT:    scratch_load_u8 v39, off, s32 offset:36
-; GFX11-NEXT:    scratch_load_u8 v48, off, s32 offset:32
-; GFX11-NEXT:    scratch_load_u8 v49, off, s32 offset:28
-; GFX11-NEXT:    scratch_load_u8 v50, off, s32 offset:24
-; GFX11-NEXT:    scratch_load_u8 v51, off, s32 offset:20
-; GFX11-NEXT:    scratch_load_u8 v52, off, s32 offset:16
-; GFX11-NEXT:    scratch_load_u8 v53, off, s32 offset:12
-; GFX11-NEXT:    scratch_load_u8 v54, off, s32 offset:8
-; GFX11-NEXT:    scratch_load_u8 v55, off, s32 offset:4
-; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    s_waitcnt vmcnt(16)
-; GFX11-NEXT:    buffer_store_b128 v[28:31], off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    buffer_store_b128 v[24:27], off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    buffer_store_b128 v[20:23], off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    buffer_store_b128 v[16:19], off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    buffer_store_b128 v[12:15], off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    buffer_store_b128 v[8:11], off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    buffer_store_b128 v[4:7], off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    buffer_store_b128 v[0:3], off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_waitcnt vmcnt(15)
-; GFX11-NEXT:    buffer_store_b8 v32, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_waitcnt vmcnt(14)
-; GFX11-NEXT:    buffer_store_b8 v33, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_waitcnt vmcnt(13)
-; GFX11-NEXT:    buffer_store_b8 v34, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_waitcnt vmcnt(12)
-; GFX11-NEXT:    buffer_store_b8 v35, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_waitcnt vmcnt(11)
-; GFX11-NEXT:    buffer_store_b8 v36, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_waitcnt vmcnt(10)
-; GFX11-NEXT:    buffer_store_b8 v37, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_waitcnt vmcnt(9)
-; GFX11-NEXT:    buffer_store_b8 v38, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_waitcnt vmcnt(8)
-; GFX11-NEXT:    buffer_store_b8 v39, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_waitcnt vmcnt(7)
-; GFX11-NEXT:    buffer_store_b8 v48, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_waitcnt vmcnt(6)
-; GFX11-NEXT:    buffer_store_b8 v49, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_waitcnt vmcnt(5)
-; GFX11-NEXT:    buffer_store_b8 v50, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_waitcnt vmcnt(4)
-; GFX11-NEXT:    buffer_store_b8 v51, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_waitcnt vmcnt(3)
-; GFX11-NEXT:    buffer_store_b8 v52, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_waitcnt vmcnt(2)
-; GFX11-NEXT:    buffer_store_b8 v53, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    buffer_store_b8 v54, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    buffer_store_b8 v55, off, s[0:3], 0 dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: void_func_v32i32_v16i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x10
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_u8 v32, off, s32 offset:64
+; GFX11-TRUE16-NEXT:    scratch_load_d16_u8 v33, off, s32 offset:60
+; GFX11-TRUE16-NEXT:    scratch_load_d16_u8 v34, off, s32 offset:56
+; GFX11-TRUE16-NEXT:    scratch_load_d16_u8 v35, off, s32 offset:52
+; GFX11-TRUE16-NEXT:    scratch_load_d16_u8 v36, off, s32 offset:48
+; GFX11-TRUE16-NEXT:    scratch_load_d16_u8 v37, off, s32 offset:44
+; GFX11-TRUE16-NEXT:    scratch_load_d16_u8 v38, off, s32 offset:40
+; GFX11-TRUE16-NEXT:    scratch_load_d16_u8 v39, off, s32 offset:36
+; GFX11-TRUE16-NEXT:    scratch_load_d16_u8 v48, off, s32 offset:32
+; GFX11-TRUE16-NEXT:    scratch_load_d16_u8 v49, off, s32 offset:28
+; GFX11-TRUE16-NEXT:    scratch_load_d16_u8 v50, off, s32 offset:24
+; GFX11-TRUE16-NEXT:    scratch_load_d16_u8 v51, off, s32 offset:20
+; GFX11-TRUE16-NEXT:    scratch_load_d16_u8 v52, off, s32 offset:16
+; GFX11-TRUE16-NEXT:    scratch_load_d16_u8 v53, off, s32 offset:12
+; GFX11-TRUE16-NEXT:    scratch_load_d16_u8 v54, off, s32 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_d16_u8 v55, off, s32 offset:4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(16)
+; GFX11-TRUE16-NEXT:    buffer_store_b128 v[28:31], off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    buffer_store_b128 v[24:27], off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    buffer_store_b128 v[20:23], off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    buffer_store_b128 v[16:19], off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    buffer_store_b128 v[12:15], off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    buffer_store_b128 v[8:11], off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    buffer_store_b128 v[4:7], off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    buffer_store_b128 v[0:3], off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(15)
+; GFX11-TRUE16-NEXT:    buffer_store_b8 v32, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(14)
+; GFX11-TRUE16-NEXT:    buffer_store_b8 v33, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(13)
+; GFX11-TRUE16-NEXT:    buffer_store_b8 v34, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(12)
+; GFX11-TRUE16-NEXT:    buffer_store_b8 v35, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(11)
+; GFX11-TRUE16-NEXT:    buffer_store_b8 v36, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(10)
+; GFX11-TRUE16-NEXT:    buffer_store_b8 v37, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(9)
+; GFX11-TRUE16-NEXT:    buffer_store_b8 v38, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(8)
+; GFX11-TRUE16-NEXT:    buffer_store_b8 v39, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT:    buffer_store_b8 v48, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(6)
+; GFX11-TRUE16-NEXT:    buffer_store_b8 v49, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(5)
+; GFX11-TRUE16-NEXT:    buffer_store_b8 v50, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(4)
+; GFX11-TRUE16-NEXT:    buffer_store_b8 v51, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(3)
+; GFX11-TRUE16-NEXT:    buffer_store_b8 v52, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-TRUE16-NEXT:    buffer_store_b8 v53, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    buffer_store_b8 v54, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    buffer_store_b8 v55, off, s[0:3], 0 dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: void_func_v32i32_v16i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x10
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v31, off, s32
+; GFX11-FAKE16-NEXT:    scratch_load_u8 v32, off, s32 offset:64
+; GFX11-FAKE16-NEXT:    scratch_load_u8 v33, off, s32 offset:60
+; GFX11-FAKE16-NEXT:    scratch_load_u8 v34, off, s32 offset:56
+; GFX11-FAKE16-NEXT:    scratch_load_u8 v35, off, s32 offset:52
+; GFX11-FAKE16-NEXT:    scratch_load_u8 v36, off, s32 offset:48
+; GFX11-FAKE16-NEXT:    scratch_load_u8 v37, off, s32 offset:44
+; GFX11-FAKE16-NEXT:    scratch_load_u8 v38, off, s32 offset:40
+; GFX11-FAKE16-NEXT:    scratch_load_u8 v39, off, s32 offset:36
+; GFX11-FAKE16-NEXT:    scratch_load_u8 v48, off, s32 offset:32
+; GFX11-FAKE16-NEXT:    scratch_load_u8 v49, off, s32 offset:28
+; GFX11-FAKE16-NEXT:    scratch_load_u8 v50, off, s32 offset:24
+; GFX11-FAKE16-NEXT:    scratch_load_u8 v51, off, s32 offset:20
+; GFX11-FAKE16-NEXT:    scratch_load_u8 v52, off, s32 offset:16
+; GFX11-FAKE16-NEXT:    scratch_load_u8 v53, off, s32 offset:12
+; GFX11-FAKE16-NEXT:    scratch_load_u8 v54, off, s32 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_u8 v55, off, s32 offset:4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(16)
+; GFX11-FAKE16-NEXT:    buffer_store_b128 v[28:31], off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    buffer_store_b128 v[24:27], off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    buffer_store_b128 v[20:23], off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    buffer_store_b128 v[16:19], off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    buffer_store_b128 v[12:15], off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    buffer_store_b128 v[8:11], off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    buffer_store_b128 v[4:7], off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    buffer_store_b128 v[0:3], off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(15)
+; GFX11-FAKE16-NEXT:    buffer_store_b8 v32, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(14)
+; GFX11-FAKE16-NEXT:    buffer_store_b8 v33, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(13)
+; GFX11-FAKE16-NEXT:    buffer_store_b8 v34, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(12)
+; GFX11-FAKE16-NEXT:    buffer_store_b8 v35, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(11)
+; GFX11-FAKE16-NEXT:    buffer_store_b8 v36, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(10)
+; GFX11-FAKE16-NEXT:    buffer_store_b8 v37, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(9)
+; GFX11-FAKE16-NEXT:    buffer_store_b8 v38, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(8)
+; GFX11-FAKE16-NEXT:    buffer_store_b8 v39, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(7)
+; GFX11-FAKE16-NEXT:    buffer_store_b8 v48, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(6)
+; GFX11-FAKE16-NEXT:    buffer_store_b8 v49, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(5)
+; GFX11-FAKE16-NEXT:    buffer_store_b8 v50, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(4)
+; GFX11-FAKE16-NEXT:    buffer_store_b8 v51, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(3)
+; GFX11-FAKE16-NEXT:    buffer_store_b8 v52, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-FAKE16-NEXT:    buffer_store_b8 v53, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    buffer_store_b8 v54, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    buffer_store_b8 v55, off, s[0:3], 0 dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   store volatile <32 x i32> %arg0, ptr addrspace(1) poison
   store volatile <16 x i8> %arg1, ptr addrspace(1) poison
   ret void
diff --git a/llvm/test/CodeGen/AMDGPU/function-returns.ll b/llvm/test/CodeGen/AMDGPU/function-returns.ll
index 70c23f7b9ea33..08515fcc08e5e 100644
--- a/llvm/test/CodeGen/AMDGPU/function-returns.ll
+++ b/llvm/test/CodeGen/AMDGPU/function-returns.ll
@@ -2,7 +2,8 @@
 ; RUN: llc -mtriple=amdgcn-- -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX789,CI %s
 ; RUN: llc -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX789,GFX89,GFX8 %s
 ; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX789,GFX89,GFX9 %s
-; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-real-true16 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define i1 @i1_func_void() #0 {
 ; GFX789-LABEL: i1_func_void:
@@ -1176,32 +1177,59 @@ define <16 x i8> @v16i8_func_void() #0 {
 ; GFX789-NEXT:    v_mov_b32_e32 v3, v18
 ; GFX789-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v16i8_func_void:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x0
-; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    buffer_load_b128 v[0:3], off, s[0:3], 0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v16, 8, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 24, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v11, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v3
-; GFX11-NEXT:    v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v1, v16
-; GFX11-NEXT:    v_mov_b32_e32 v8, v2
-; GFX11-NEXT:    v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v3, v18
-; GFX11-NEXT:    v_mov_b32_e32 v2, v17
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v16i8_func_void:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_load_b64 s[0:1], s[0:1], 0x0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    buffer_load_b128 v[16:19], off, s[0:3], 0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v11, 24, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v17.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v19.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v16i8_func_void:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_load_b64 s[0:1], s[0:1], 0x0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    buffer_load_b128 v[0:3], off, s[0:3], 0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 24, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v11, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v3
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v1, v16
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v2
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v3, v18
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, v17
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %ptr = load volatile ptr addrspace(1), ptr addrspace(4) poison
   %val = load <16 x i8>, ptr addrspace(1) %ptr
   ret <16 x i8> %val
@@ -2310,17 +2338,30 @@ define void @void_func_sret_max_known_zero_bits(ptr addrspace(5) sret(i8) %arg0)
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: void_func_sret_max_known_zero_bits:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v0, 17, v0
-; GFX11-NEXT:    v_mov_b32_e32 v2, 0
-; GFX11-NEXT:    ds_store_b32 v0, v1
-; GFX11-NEXT:    ds_store_b32 v0, v0
-; GFX11-NEXT:    ds_store_b32 v0, v2
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: void_func_sret_max_known_zero_bits:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, 0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, 17, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-TRUE16-NEXT:    ds_store_b32 v0, v1
+; GFX11-TRUE16-NEXT:    ds_store_b32 v0, v0
+; GFX11-TRUE16-NEXT:    ds_store_b32 v0, v2
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: void_func_sret_max_known_zero_bits:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 17, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-FAKE16-NEXT:    ds_store_b32 v0, v1
+; GFX11-FAKE16-NEXT:    ds_store_b32 v0, v0
+; GFX11-FAKE16-NEXT:    ds_store_b32 v0, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %arg0.int = ptrtoint ptr addrspace(5) %arg0 to i32
 
   %lshr0 = lshr i32 %arg0.int, 16
diff --git a/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll b/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
index a780c739dce7d..ca9cb456fa19f 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
+++ b/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
@@ -1,7 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX9 %s
 ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s
-; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX11 %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11,GFX11-FAKE16 %s
 ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1010 -mattr=+enable-flat-scratch -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10-SCRATCH %s
 
 declare hidden amdgpu_gfx void @external_void_func_i1(i1) #0
@@ -677,34 +678,63 @@ define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_call_external_void_func_i8_signext:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, s33
-; GFX11-NEXT:    s_mov_b32 s33, s32
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    global_load_i8 v0, v[0:1], off glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_writelane_b32 v40, s0, 2
-; GFX11-NEXT:    s_mov_b32 s1, external_void_func_i8_signext@abs32@hi
-; GFX11-NEXT:    s_mov_b32 s0, external_void_func_i8_signext@abs32@lo
-; GFX11-NEXT:    s_add_i32 s32, s32, 16
-; GFX11-NEXT:    v_writelane_b32 v40, s30, 0
-; GFX11-NEXT:    v_writelane_b32 v40, s31, 1
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_readlane_b32 s31, v40, 1
-; GFX11-NEXT:    v_readlane_b32 s30, v40, 0
-; GFX11-NEXT:    s_mov_b32 s32, s33
-; GFX11-NEXT:    v_readlane_b32 s0, v40, 2
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_mov_b32 s33, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test_call_external_void_func_i8_signext:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    global_load_d16_i8 v0, v[0:1], off glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s0, 2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, external_void_func_i8_signext@abs32@hi
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, external_void_func_i8_signext@abs32@lo
+; GFX11-TRUE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s30, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s31, v40, 1
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s0, v40, 2
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_call_external_void_func_i8_signext:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    global_load_i8 v0, v[0:1], off glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s0, 2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, external_void_func_i8_signext@abs32@hi
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, external_void_func_i8_signext@abs32@lo
+; GFX11-FAKE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s30, 0
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s31, v40, 1
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s0, v40, 2
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-SCRATCH-LABEL: test_call_external_void_func_i8_signext:
 ; GFX10-SCRATCH:       ; %bb.0:
@@ -799,34 +829,63 @@ define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_call_external_void_func_i8_zeroext:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, s33
-; GFX11-NEXT:    s_mov_b32 s33, s32
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    global_load_u8 v0, v[0:1], off glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_writelane_b32 v40, s0, 2
-; GFX11-NEXT:    s_mov_b32 s1, external_void_func_i8_zeroext@abs32@hi
-; GFX11-NEXT:    s_mov_b32 s0, external_void_func_i8_zeroext@abs32@lo
-; GFX11-NEXT:    s_add_i32 s32, s32, 16
-; GFX11-NEXT:    v_writelane_b32 v40, s30, 0
-; GFX11-NEXT:    v_writelane_b32 v40, s31, 1
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_readlane_b32 s31, v40, 1
-; GFX11-NEXT:    v_readlane_b32 s30, v40, 0
-; GFX11-NEXT:    s_mov_b32 s32, s33
-; GFX11-NEXT:    v_readlane_b32 s0, v40, 2
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_mov_b32 s33, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test_call_external_void_func_i8_zeroext:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s0, 2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, external_void_func_i8_zeroext@abs32@hi
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, external_void_func_i8_zeroext@abs32@lo
+; GFX11-TRUE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s30, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s31, v40, 1
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s0, v40, 2
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_call_external_void_func_i8_zeroext:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s0, 2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, external_void_func_i8_zeroext@abs32@hi
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, external_void_func_i8_zeroext@abs32@lo
+; GFX11-FAKE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s30, 0
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s31, v40, 1
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s0, v40, 2
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-SCRATCH-LABEL: test_call_external_void_func_i8_zeroext:
 ; GFX10-SCRATCH:       ; %bb.0:
@@ -1038,34 +1097,63 @@ define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_call_external_void_func_i16_signext:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, s33
-; GFX11-NEXT:    s_mov_b32 s33, s32
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    global_load_u16 v0, v[0:1], off glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_writelane_b32 v40, s0, 2
-; GFX11-NEXT:    s_mov_b32 s1, external_void_func_i16_signext@abs32@hi
-; GFX11-NEXT:    s_mov_b32 s0, external_void_func_i16_signext@abs32@lo
-; GFX11-NEXT:    s_add_i32 s32, s32, 16
-; GFX11-NEXT:    v_writelane_b32 v40, s30, 0
-; GFX11-NEXT:    v_writelane_b32 v40, s31, 1
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_readlane_b32 s31, v40, 1
-; GFX11-NEXT:    v_readlane_b32 s30, v40, 0
-; GFX11-NEXT:    s_mov_b32 s32, s33
-; GFX11-NEXT:    v_readlane_b32 s0, v40, 2
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_mov_b32 s33, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test_call_external_void_func_i16_signext:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v[0:1], off glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s0, 2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, external_void_func_i16_signext@abs32@hi
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, external_void_func_i16_signext@abs32@lo
+; GFX11-TRUE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s30, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s31, v40, 1
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s0, v40, 2
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_call_external_void_func_i16_signext:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    global_load_u16 v0, v[0:1], off glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s0, 2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, external_void_func_i16_signext@abs32@hi
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, external_void_func_i16_signext@abs32@lo
+; GFX11-FAKE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s30, 0
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s31, v40, 1
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s0, v40, 2
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-SCRATCH-LABEL: test_call_external_void_func_i16_signext:
 ; GFX10-SCRATCH:       ; %bb.0:
@@ -1160,34 +1248,63 @@ define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_call_external_void_func_i16_zeroext:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, s33
-; GFX11-NEXT:    s_mov_b32 s33, s32
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    global_load_u16 v0, v[0:1], off glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_writelane_b32 v40, s0, 2
-; GFX11-NEXT:    s_mov_b32 s1, external_void_func_i16_zeroext@abs32@hi
-; GFX11-NEXT:    s_mov_b32 s0, external_void_func_i16_zeroext@abs32@lo
-; GFX11-NEXT:    s_add_i32 s32, s32, 16
-; GFX11-NEXT:    v_writelane_b32 v40, s30, 0
-; GFX11-NEXT:    v_writelane_b32 v40, s31, 1
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_readlane_b32 s31, v40, 1
-; GFX11-NEXT:    v_readlane_b32 s30, v40, 0
-; GFX11-NEXT:    s_mov_b32 s32, s33
-; GFX11-NEXT:    v_readlane_b32 s0, v40, 2
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_mov_b32 s33, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test_call_external_void_func_i16_zeroext:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v[0:1], off glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s0, 2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, external_void_func_i16_zeroext@abs32@hi
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, external_void_func_i16_zeroext@abs32@lo
+; GFX11-TRUE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s30, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s31, v40, 1
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s0, v40, 2
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_call_external_void_func_i16_zeroext:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    global_load_u16 v0, v[0:1], off glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s0, 2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, external_void_func_i16_zeroext@abs32@hi
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, external_void_func_i16_zeroext@abs32@lo
+; GFX11-FAKE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s30, 0
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s31, v40, 1
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s0, v40, 2
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-SCRATCH-LABEL: test_call_external_void_func_i16_zeroext:
 ; GFX10-SCRATCH:       ; %bb.0:
@@ -3044,38 +3161,71 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8() #0 {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_call_external_void_func_v2i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, s33
-; GFX11-NEXT:    s_mov_b32 s33, s32
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    v_mov_b32_e32 v1, 0
-; GFX11-NEXT:    v_writelane_b32 v40, s0, 2
-; GFX11-NEXT:    s_mov_b32 s1, external_void_func_v2i8@abs32@hi
-; GFX11-NEXT:    s_mov_b32 s0, external_void_func_v2i8@abs32@lo
-; GFX11-NEXT:    s_add_i32 s32, s32, 16
-; GFX11-NEXT:    global_load_u16 v0, v[0:1], off
-; GFX11-NEXT:    v_writelane_b32 v40, s30, 0
-; GFX11-NEXT:    v_writelane_b32 v40, s31, 1
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT:    v_readlane_b32 s31, v40, 1
-; GFX11-NEXT:    v_readlane_b32 s30, v40, 0
-; GFX11-NEXT:    s_mov_b32 s32, s33
-; GFX11-NEXT:    v_readlane_b32 s0, v40, 2
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_mov_b32 s33, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test_call_external_void_func_v2i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s0, 2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, external_void_func_v2i8@abs32@hi
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, external_void_func_v2i8@abs32@lo
+; GFX11-TRUE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s30, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s31, v40, 1
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s0, v40, 2
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_call_external_void_func_v2i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s0, 2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, external_void_func_v2i8@abs32@hi
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, external_void_func_v2i8@abs32@lo
+; GFX11-FAKE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-FAKE16-NEXT:    global_load_u16 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s30, 0
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s31, v40, 1
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s0, v40, 2
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-SCRATCH-LABEL: test_call_external_void_func_v2i8:
 ; GFX10-SCRATCH:       ; %bb.0:
@@ -3466,40 +3616,76 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8() #0 {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_call_external_void_func_v5i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, s33
-; GFX11-NEXT:    s_mov_b32 s33, s32
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    v_mov_b32_e32 v1, 0
-; GFX11-NEXT:    v_writelane_b32 v40, s0, 2
-; GFX11-NEXT:    s_mov_b32 s1, external_void_func_v5i8@abs32@hi
-; GFX11-NEXT:    s_mov_b32 s0, external_void_func_v5i8@abs32@lo
-; GFX11-NEXT:    s_add_i32 s32, s32, 16
-; GFX11-NEXT:    global_load_b64 v[5:6], v[0:1], off
-; GFX11-NEXT:    v_writelane_b32 v40, s30, 0
-; GFX11-NEXT:    v_writelane_b32 v40, s31, 1
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_mov_b32_e32 v0, v5
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v5
-; GFX11-NEXT:    v_mov_b32_e32 v4, v6
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT:    v_readlane_b32 s31, v40, 1
-; GFX11-NEXT:    v_readlane_b32 s30, v40, 0
-; GFX11-NEXT:    s_mov_b32 s32, s33
-; GFX11-NEXT:    v_readlane_b32 s0, v40, 2
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_mov_b32 s33, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test_call_external_void_func_v5i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s0, 2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, external_void_func_v5i8@abs32@hi
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, external_void_func_v5i8@abs32@lo
+; GFX11-TRUE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-TRUE16-NEXT:    global_load_b64 v[3:4], v[0:1], off
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s30, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[5:6], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v3.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v5.l
+; GFX11-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s31, v40, 1
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s0, v40, 2
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_call_external_void_func_v5i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s0, 2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, external_void_func_v5i8@abs32@hi
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, external_void_func_v5i8@abs32@lo
+; GFX11-FAKE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-FAKE16-NEXT:    global_load_b64 v[5:6], v[0:1], off
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s30, 0
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v5
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v6
+; GFX11-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s31, v40, 1
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s0, v40, 2
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-SCRATCH-LABEL: test_call_external_void_func_v5i8:
 ; GFX10-SCRATCH:       ; %bb.0:
@@ -3621,42 +3807,80 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8() #0 {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_call_external_void_func_v8i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, s33
-; GFX11-NEXT:    s_mov_b32 s33, s32
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    v_mov_b32_e32 v1, 0
-; GFX11-NEXT:    v_writelane_b32 v40, s0, 2
-; GFX11-NEXT:    s_mov_b32 s1, external_void_func_v8i8@abs32@hi
-; GFX11-NEXT:    s_mov_b32 s0, external_void_func_v8i8@abs32@lo
-; GFX11-NEXT:    s_add_i32 s32, s32, 16
-; GFX11-NEXT:    global_load_b64 v[0:1], v[0:1], off
-; GFX11-NEXT:    v_writelane_b32 v40, s30, 0
-; GFX11-NEXT:    v_writelane_b32 v40, s31, 1
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v8, 8, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
-; GFX11-NEXT:    v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v1, v8
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT:    v_readlane_b32 s31, v40, 1
-; GFX11-NEXT:    v_readlane_b32 s30, v40, 0
-; GFX11-NEXT:    s_mov_b32 s32, s33
-; GFX11-NEXT:    v_readlane_b32 s0, v40, 2
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_mov_b32 s33, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test_call_external_void_func_v8i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s0, 2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, external_void_func_v8i8@abs32@hi
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, external_void_func_v8i8@abs32@lo
+; GFX11-TRUE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-TRUE16-NEXT:    global_load_b64 v[8:9], v[0:1], off
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s30, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v9.l
+; GFX11-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s31, v40, 1
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s0, v40, 2
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_call_external_void_func_v8i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s0, 2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, external_void_func_v8i8@abs32@hi
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, external_void_func_v8i8@abs32@lo
+; GFX11-FAKE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-FAKE16-NEXT:    global_load_b64 v[0:1], v[0:1], off
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s30, 0
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 8, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v1, v8
+; GFX11-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s31, v40, 1
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s0, v40, 2
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-SCRATCH-LABEL: test_call_external_void_func_v8i8:
 ; GFX10-SCRATCH:       ; %bb.0:
@@ -3846,70 +4070,136 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8() #0 {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_call_external_void_func_v32i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, s33
-; GFX11-NEXT:    s_mov_b32 s33, s32
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 16
-; GFX11-NEXT:    v_mov_b32_e32 v5, 0
-; GFX11-NEXT:    v_writelane_b32 v40, s0, 2
-; GFX11-NEXT:    s_mov_b32 s1, external_void_func_v32i8@abs32@hi
-; GFX11-NEXT:    global_load_b128 v[0:3], v[0:1], off
-; GFX11-NEXT:    s_mov_b32 s0, external_void_func_v32i8@abs32@lo
-; GFX11-NEXT:    global_load_b128 v[16:19], v[4:5], off
-; GFX11-NEXT:    v_writelane_b32 v40, s30, 0
-; GFX11-NEXT:    s_add_i32 s32, s32, 16
-; GFX11-NEXT:    v_writelane_b32 v40, s31, 1
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 8, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 24, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v11, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 16, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 24, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 16, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 24, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v19
-; GFX11-NEXT:    v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v1, v35
-; GFX11-NEXT:    v_mov_b32_e32 v8, v2
-; GFX11-NEXT:    v_mov_b32_e32 v12, v3
-; GFX11-NEXT:    v_mov_b32_e32 v20, v17
-; GFX11-NEXT:    v_mov_b32_e32 v24, v18
-; GFX11-NEXT:    v_dual_mov_b32 v28, v19 :: v_dual_mov_b32 v19, v34
-; GFX11-NEXT:    v_dual_mov_b32 v2, v36 :: v_dual_mov_b32 v3, v37
-; GFX11-NEXT:    v_dual_mov_b32 v17, v32 :: v_dual_mov_b32 v18, v33
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT:    v_readlane_b32 s31, v40, 1
-; GFX11-NEXT:    v_readlane_b32 s30, v40, 0
-; GFX11-NEXT:    s_mov_b32 s32, s33
-; GFX11-NEXT:    v_readlane_b32 s0, v40, 2
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_mov_b32 s33, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test_call_external_void_func_v32i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s0, 2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, external_void_func_v32i8@abs32@hi
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, external_void_func_v32i8@abs32@lo
+; GFX11-TRUE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-TRUE16-NEXT:    global_load_b128 v[32:35], v[0:1], off
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, 16
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s30, 0
+; GFX11-TRUE16-NEXT:    global_load_b128 v[36:39], v[0:1], off
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v34
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v34
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v11, 24, v34
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v35
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v35
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v35
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v36
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v36
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v19, 24, v36
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v37
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v22, 16, v37
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v37
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v38
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 16, v38
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 24, v38
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v39
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v39
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v39
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v32.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v33.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v34.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v35.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v36.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.l, v37.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v24.l, v38.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.l, v39.l
+; GFX11-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s31, v40, 1
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s0, v40, 2
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_call_external_void_func_v32i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 16
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, 0
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s0, 2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, external_void_func_v32i8@abs32@hi
+; GFX11-FAKE16-NEXT:    global_load_b128 v[0:3], v[0:1], off
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, external_void_func_v32i8@abs32@lo
+; GFX11-FAKE16-NEXT:    global_load_b128 v[16:19], v[4:5], off
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s30, 0
+; GFX11-FAKE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 8, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v11, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 24, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v19
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v1, v35
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v2
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v12, v3
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v20, v17
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v24, v18
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v28, v19 :: v_dual_mov_b32 v19, v34
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v2, v36 :: v_dual_mov_b32 v3, v37
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v17, v32 :: v_dual_mov_b32 v18, v33
+; GFX11-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s31, v40, 1
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s0, v40, 2
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-SCRATCH-LABEL: test_call_external_void_func_v32i8:
 ; GFX10-SCRATCH:       ; %bb.0:
@@ -4062,41 +4352,77 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_call_external_void_func_i8_ret:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, s33
-; GFX11-NEXT:    s_mov_b32 s33, s32
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_store_b32 off, v40, s33 offset:4
-; GFX11-NEXT:    scratch_store_b32 off, v41, s33
-; GFX11-NEXT:    v_mov_b32_e32 v40, 0
-; GFX11-NEXT:    v_mov_b32_e32 v41, 0
-; GFX11-NEXT:    v_writelane_b32 v42, s0, 2
-; GFX11-NEXT:    s_mov_b32 s1, external_void_func_i8_ret@abs32@hi
-; GFX11-NEXT:    s_mov_b32 s0, external_void_func_i8_ret@abs32@lo
-; GFX11-NEXT:    s_add_i32 s32, s32, 16
-; GFX11-NEXT:    global_load_u8 v0, v[40:41], off
-; GFX11-NEXT:    v_writelane_b32 v42, s30, 0
-; GFX11-NEXT:    v_writelane_b32 v42, s31, 1
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT:    global_store_b8 v[40:41], v0, off
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_b32 v41, off, s33
-; GFX11-NEXT:    scratch_load_b32 v40, off, s33 offset:4
-; GFX11-NEXT:    v_readlane_b32 s31, v42, 1
-; GFX11-NEXT:    v_readlane_b32 s30, v42, 0
-; GFX11-NEXT:    s_mov_b32 s32, s33
-; GFX11-NEXT:    v_readlane_b32 s0, v42, 2
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_mov_b32 s33, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test_call_external_void_func_i8_ret:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v40, s33 offset:4
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v41, s33
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v40, 0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v41, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v42, s0, 2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, external_void_func_i8_ret@abs32@hi
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, external_void_func_i8_ret@abs32@lo
+; GFX11-TRUE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-TRUE16-NEXT:    global_load_d16_u8 v0, v[40:41], off
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v42, s30, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v42, s31, 1
+; GFX11-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-TRUE16-NEXT:    global_store_b8 v[40:41], v0, off
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v41, off, s33
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v40, off, s33 offset:4
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s31, v42, 1
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s30, v42, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s0, v42, 2
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_call_external_void_func_i8_ret:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s33 offset:4
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v41, s33
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v40, 0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v41, 0
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v42, s0, 2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, external_void_func_i8_ret@abs32@hi
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, external_void_func_i8_ret@abs32@lo
+; GFX11-FAKE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-FAKE16-NEXT:    global_load_u8 v0, v[40:41], off
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v42, s30, 0
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v42, s31, 1
+; GFX11-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-FAKE16-NEXT:    global_store_b8 v[40:41], v0, off
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v41, off, s33
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s33 offset:4
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s31, v42, 1
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s30, v42, 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s0, v42, 2
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-SCRATCH-LABEL: test_call_external_void_func_i8_ret:
 ; GFX10-SCRATCH:       ; %bb.0:
@@ -4224,48 +4550,92 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_call_external_void_func_v2i8_ret:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, s33
-; GFX11-NEXT:    s_mov_b32 s33, s32
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_store_b32 off, v40, s33 offset:4
-; GFX11-NEXT:    scratch_store_b32 off, v41, s33
-; GFX11-NEXT:    v_mov_b32_e32 v40, 0
-; GFX11-NEXT:    v_mov_b32_e32 v41, 0
-; GFX11-NEXT:    v_writelane_b32 v42, s0, 2
-; GFX11-NEXT:    s_mov_b32 s1, external_void_func_v2i8_ret@abs32@hi
-; GFX11-NEXT:    s_mov_b32 s0, external_void_func_v2i8_ret@abs32@lo
-; GFX11-NEXT:    s_add_i32 s32, s32, 16
-; GFX11-NEXT:    global_load_u16 v0, v[40:41], off
-; GFX11-NEXT:    v_writelane_b32 v42, s30, 0
-; GFX11-NEXT:    v_writelane_b32 v42, s31, 1
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_readlane_b32 s31, v42, 1
-; GFX11-NEXT:    v_readlane_b32 s30, v42, 0
-; GFX11-NEXT:    s_mov_b32 s32, s33
-; GFX11-NEXT:    v_readlane_b32 s0, v42, 2
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    global_store_b16 v[40:41], v0, off
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_b32 v41, off, s33
-; GFX11-NEXT:    scratch_load_b32 v40, off, s33 offset:4
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_mov_b32 s33, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test_call_external_void_func_v2i8_ret:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v40, s33 offset:4
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v41, s33
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v40, 0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v41, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v42, s0, 2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, external_void_func_v2i8_ret@abs32@hi
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, external_void_func_v2i8_ret@abs32@lo
+; GFX11-TRUE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v[40:41], off
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v42, s30, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v42, s31, 1
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s31, v42, 1
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s30, v42, 0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s0, v42, 2
+; GFX11-TRUE16-NEXT:    global_store_b16 v[40:41], v0, off
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v41, off, s33
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v40, off, s33 offset:4
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_call_external_void_func_v2i8_ret:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s33 offset:4
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v41, s33
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v40, 0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v41, 0
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v42, s0, 2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, external_void_func_v2i8_ret@abs32@hi
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, external_void_func_v2i8_ret@abs32@lo
+; GFX11-FAKE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-FAKE16-NEXT:    global_load_u16 v0, v[40:41], off
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v42, s30, 0
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v42, s31, 1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s31, v42, 1
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s30, v42, 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s0, v42, 2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    global_store_b16 v[40:41], v0, off
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v41, off, s33
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s33 offset:4
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-SCRATCH-LABEL: test_call_external_void_func_v2i8_ret:
 ; GFX10-SCRATCH:       ; %bb.0:
@@ -4389,67 +4759,114 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
 ; GFX10-NEXT:    v_readlane_b32 s31, v42, 1
 ; GFX10-NEXT:    v_readlane_b32 s30, v42, 0
 ; GFX10-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-NEXT:    s_mov_b32 s32, s33
-; GFX10-NEXT:    v_readlane_b32 s34, v42, 2
-; GFX10-NEXT:    global_store_byte v[3:4], v2, off
-; GFX10-NEXT:    global_store_short v[40:41], v0, off
-; GFX10-NEXT:    s_clause 0x1
-; GFX10-NEXT:    buffer_load_dword v41, off, s[0:3], s33
-; GFX10-NEXT:    buffer_load_dword v40, off, s[0:3], s33 offset:4
-; GFX10-NEXT:    s_or_saveexec_b32 s35, -1
-; GFX10-NEXT:    buffer_load_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
-; GFX10-NEXT:    s_waitcnt_depctr 0xffe3
-; GFX10-NEXT:    s_mov_b32 exec_lo, s35
-; GFX10-NEXT:    s_mov_b32 s33, s34
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: test_call_external_void_func_v3i8_ret:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, s33
-; GFX11-NEXT:    s_mov_b32 s33, s32
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_store_b32 off, v40, s33 offset:4
-; GFX11-NEXT:    scratch_store_b32 off, v41, s33
-; GFX11-NEXT:    v_mov_b32_e32 v40, 0
-; GFX11-NEXT:    v_mov_b32_e32 v41, 0
-; GFX11-NEXT:    v_writelane_b32 v42, s0, 2
-; GFX11-NEXT:    s_mov_b32 s1, external_void_func_v3i8_ret@abs32@hi
-; GFX11-NEXT:    s_mov_b32 s0, external_void_func_v3i8_ret@abs32@lo
-; GFX11-NEXT:    s_add_i32 s32, s32, 16
-; GFX11-NEXT:    global_load_b32 v0, v[40:41], off
-; GFX11-NEXT:    v_writelane_b32 v42, s30, 0
-; GFX11-NEXT:    v_writelane_b32 v42, s31, 1
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_lshlrev_b16 v3, 8, v1
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v0
-; GFX11-NEXT:    v_mov_b32_e32 v0, 2
-; GFX11-NEXT:    v_mov_b32_e32 v1, 0
-; GFX11-NEXT:    v_readlane_b32 s31, v42, 1
-; GFX11-NEXT:    v_readlane_b32 s30, v42, 0
-; GFX11-NEXT:    v_or_b32_e32 v3, v4, v3
-; GFX11-NEXT:    s_mov_b32 s32, s33
-; GFX11-NEXT:    v_readlane_b32 s0, v42, 2
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_store_b8 v[0:1], v2, off
-; GFX11-NEXT:    global_store_b16 v[40:41], v3, off
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_b32 v41, off, s33
-; GFX11-NEXT:    scratch_load_b32 v40, off, s33 offset:4
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_mov_b32 s33, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_mov_b32 s32, s33
+; GFX10-NEXT:    v_readlane_b32 s34, v42, 2
+; GFX10-NEXT:    global_store_byte v[3:4], v2, off
+; GFX10-NEXT:    global_store_short v[40:41], v0, off
+; GFX10-NEXT:    s_clause 0x1
+; GFX10-NEXT:    buffer_load_dword v41, off, s[0:3], s33
+; GFX10-NEXT:    buffer_load_dword v40, off, s[0:3], s33 offset:4
+; GFX10-NEXT:    s_or_saveexec_b32 s35, -1
+; GFX10-NEXT:    buffer_load_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
+; GFX10-NEXT:    s_waitcnt_depctr 0xffe3
+; GFX10-NEXT:    s_mov_b32 exec_lo, s35
+; GFX10-NEXT:    s_mov_b32 s33, s34
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: test_call_external_void_func_v3i8_ret:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v40, s33 offset:4
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v41, s33
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v40, 0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v41, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v42, s0, 2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, external_void_func_v3i8_ret@abs32@hi
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, external_void_func_v3i8_ret@abs32@lo
+; GFX11-TRUE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[40:41], off
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v42, s30, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v42, s31, 1
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v3, 2
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v4, 0
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s31, v42, 1
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    global_store_b8 v[3:4], v2, off
+; GFX11-TRUE16-NEXT:    global_store_b16 v[40:41], v0, off
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v41, off, s33
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v40, off, s33 offset:4
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s30, v42, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s0, v42, 2
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_call_external_void_func_v3i8_ret:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s33 offset:4
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v41, s33
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v40, 0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v41, 0
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v42, s0, 2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, external_void_func_v3i8_ret@abs32@hi
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, external_void_func_v3i8_ret@abs32@lo
+; GFX11-FAKE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[40:41], off
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v42, s30, 0
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v42, s31, 1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 2
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s31, v42, 1
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s30, v42, 0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v4, v3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s0, v42, 2
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    global_store_b8 v[0:1], v2, off
+; GFX11-FAKE16-NEXT:    global_store_b16 v[40:41], v3, off
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v41, off, s33
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s33 offset:4
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-SCRATCH-LABEL: test_call_external_void_func_v3i8_ret:
 ; GFX10-SCRATCH:       ; %bb.0:
@@ -4593,57 +5010,109 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_call_external_void_func_v4i8_ret:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, s33
-; GFX11-NEXT:    s_mov_b32 s33, s32
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_store_b32 off, v40, s33 offset:4
-; GFX11-NEXT:    scratch_store_b32 off, v41, s33
-; GFX11-NEXT:    v_mov_b32_e32 v40, 0
-; GFX11-NEXT:    v_mov_b32_e32 v41, 0
-; GFX11-NEXT:    v_writelane_b32 v42, s0, 2
-; GFX11-NEXT:    s_mov_b32 s1, external_void_func_v4i8_ret@abs32@hi
-; GFX11-NEXT:    s_mov_b32 s0, external_void_func_v4i8_ret@abs32@lo
-; GFX11-NEXT:    s_add_i32 s32, s32, 16
-; GFX11-NEXT:    global_load_b32 v0, v[40:41], off
-; GFX11-NEXT:    v_writelane_b32 v42, s30, 0
-; GFX11-NEXT:    v_writelane_b32 v42, s31, 1
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_lshlrev_b16 v3, 8, v3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_readlane_b32 s31, v42, 1
-; GFX11-NEXT:    v_readlane_b32 s30, v42, 0
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    s_mov_b32 s32, s33
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_readlane_b32 s0, v42, 2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    global_store_b32 v[40:41], v0, off
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_b32 v41, off, s33
-; GFX11-NEXT:    scratch_load_b32 v40, off, s33 offset:4
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_mov_b32 s33, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test_call_external_void_func_v4i8_ret:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v40, s33 offset:4
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v41, s33
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v40, 0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v41, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v42, s0, 2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, external_void_func_v4i8_ret@abs32@hi
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, external_void_func_v4i8_ret@abs32@lo
+; GFX11-TRUE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[40:41], off
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v42, s30, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v42, s31, 1
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
+; GFX11-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s31, v42, 1
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s30, v42, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s0, v42, 2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT:    global_store_b32 v[40:41], v0, off
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v41, off, s33
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v40, off, s33 offset:4
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_call_external_void_func_v4i8_ret:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s33 offset:4
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v41, s33
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v40, 0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v41, 0
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v42, s0, 2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, external_void_func_v4i8_ret@abs32@hi
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, external_void_func_v4i8_ret@abs32@lo
+; GFX11-FAKE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[40:41], off
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v42, s30, 0
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v42, s31, 1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
+; GFX11-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s31, v42, 1
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s30, v42, 0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s0, v42, 2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    global_store_b32 v[40:41], v0, off
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v41, off, s33
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s33 offset:4
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-SCRATCH-LABEL: test_call_external_void_func_v4i8_ret:
 ; GFX10-SCRATCH:       ; %bb.0:
@@ -4798,62 +5267,120 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_call_external_void_func_v5i8_ret:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, s33
-; GFX11-NEXT:    s_mov_b32 s33, s32
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_store_b32 off, v40, s33 offset:4
-; GFX11-NEXT:    scratch_store_b32 off, v41, s33
-; GFX11-NEXT:    v_mov_b32_e32 v40, 0
-; GFX11-NEXT:    v_mov_b32_e32 v41, 0
-; GFX11-NEXT:    v_writelane_b32 v42, s0, 2
-; GFX11-NEXT:    s_mov_b32 s1, external_void_func_v5i8_ret@abs32@hi
-; GFX11-NEXT:    s_mov_b32 s0, external_void_func_v5i8_ret@abs32@lo
-; GFX11-NEXT:    s_add_i32 s32, s32, 16
-; GFX11-NEXT:    global_load_b64 v[5:6], v[40:41], off
-; GFX11-NEXT:    v_writelane_b32 v42, s30, 0
-; GFX11-NEXT:    v_writelane_b32 v42, s31, 1
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_mov_b32_e32 v0, v5
-; GFX11-NEXT:    v_lshrrev_b64 v[3:4], 24, v[5:6]
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v5
-; GFX11-NEXT:    v_mov_b32_e32 v4, v6
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_lshlrev_b16 v3, 8, v3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_readlane_b32 s31, v42, 1
-; GFX11-NEXT:    v_readlane_b32 s30, v42, 0
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    s_mov_b32 s32, s33
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_readlane_b32 s0, v42, 2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v0
-; GFX11-NEXT:    v_dual_mov_b32 v0, 4 :: v_dual_lshlrev_b32 v3, 16, v1
-; GFX11-NEXT:    v_mov_b32_e32 v1, 0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v3
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_store_b8 v[0:1], v4, off
-; GFX11-NEXT:    global_store_b32 v[40:41], v2, off
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_b32 v41, off, s33
-; GFX11-NEXT:    scratch_load_b32 v40, off, s33 offset:4
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_mov_b32 s33, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test_call_external_void_func_v5i8_ret:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v40, s33 offset:4
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v41, s33
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v40, 0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v41, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v42, s0, 2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, external_void_func_v5i8_ret@abs32@hi
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, external_void_func_v5i8_ret@abs32@lo
+; GFX11-TRUE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-TRUE16-NEXT:    global_load_b64 v[3:4], v[40:41], off
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v42, s30, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v42, s31, 1
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b64 v[5:6], 24, v[3:4]
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v3.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v5.l
+; GFX11-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v0, 4 :: v_dual_lshlrev_b32 v3, 16, v1
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s31, v42, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v2, v3
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    global_store_b8 v[0:1], v4, off
+; GFX11-TRUE16-NEXT:    global_store_b32 v[40:41], v2, off
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v41, off, s33
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v40, off, s33 offset:4
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s30, v42, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s0, v42, 2
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_call_external_void_func_v5i8_ret:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s33 offset:4
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v41, s33
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v40, 0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v41, 0
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v42, s0, 2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, external_void_func_v5i8_ret@abs32@hi
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, external_void_func_v5i8_ret@abs32@lo
+; GFX11-FAKE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-FAKE16-NEXT:    global_load_b64 v[5:6], v[40:41], off
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v42, s30, 0
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v42, s31, 1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b64 v[3:4], 24, v[5:6]
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v5
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v6
+; GFX11-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s31, v42, 1
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s30, v42, 0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s0, v42, 2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v0, 4 :: v_dual_lshlrev_b32 v3, 16, v1
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    global_store_b8 v[0:1], v4, off
+; GFX11-FAKE16-NEXT:    global_store_b32 v[40:41], v2, off
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v41, off, s33
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s33 offset:4
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-SCRATCH-LABEL: test_call_external_void_func_v5i8_ret:
 ; GFX10-SCRATCH:       ; %bb.0:
@@ -5023,69 +5550,137 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_call_external_void_func_v8i8_ret:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, s33
-; GFX11-NEXT:    s_mov_b32 s33, s32
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_store_b32 off, v40, s33 offset:4
-; GFX11-NEXT:    scratch_store_b32 off, v41, s33
-; GFX11-NEXT:    v_mov_b32_e32 v40, 0
-; GFX11-NEXT:    v_mov_b32_e32 v41, 0
-; GFX11-NEXT:    v_writelane_b32 v42, s0, 2
-; GFX11-NEXT:    s_mov_b32 s1, external_void_func_v8i8_ret@abs32@hi
-; GFX11-NEXT:    s_mov_b32 s0, external_void_func_v8i8_ret@abs32@lo
-; GFX11-NEXT:    s_add_i32 s32, s32, 16
-; GFX11-NEXT:    global_load_b64 v[0:1], v[40:41], off
-; GFX11-NEXT:    v_writelane_b32 v42, s30, 0
-; GFX11-NEXT:    v_writelane_b32 v42, s31, 1
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_mov_b32_e32 v4, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v8, 8, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
-; GFX11-NEXT:    v_mov_b32_e32 v1, v8
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT:    v_lshlrev_b16 v5, 8, v5
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_lshlrev_b16 v7, 8, v7
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_lshlrev_b16 v3, 8, v3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v5, v6, v7
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_readlane_b32 s31, v42, 1
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_readlane_b32 s30, v42, 0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 16, v1
-; GFX11-NEXT:    s_mov_b32 s32, s33
-; GFX11-NEXT:    v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT:    v_readlane_b32 s0, v42, 2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v4
-; GFX11-NEXT:    global_store_b64 v[40:41], v[0:1], off
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_b32 v41, off, s33
-; GFX11-NEXT:    scratch_load_b32 v40, off, s33 offset:4
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_mov_b32 s33, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test_call_external_void_func_v8i8_ret:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v40, s33 offset:4
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v41, s33
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v40, 0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v41, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v42, s0, 2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, external_void_func_v8i8_ret@abs32@hi
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, external_void_func_v8i8_ret@abs32@lo
+; GFX11-TRUE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-TRUE16-NEXT:    global_load_b64 v[8:9], v[40:41], off
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v42, s30, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v42, s31, 1
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v8
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v9.l
+; GFX11-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v5.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v1.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v3.h, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v2.l, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v5
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v4
+; GFX11-TRUE16-NEXT:    global_store_b64 v[40:41], v[0:1], off
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v41, off, s33
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v40, off, s33 offset:4
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s31, v42, 1
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s30, v42, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s0, v42, 2
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_call_external_void_func_v8i8_ret:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s33 offset:4
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v41, s33
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v40, 0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v41, 0
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v42, s0, 2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, external_void_func_v8i8_ret@abs32@hi
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, external_void_func_v8i8_ret@abs32@lo
+; GFX11-FAKE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-FAKE16-NEXT:    global_load_b64 v[0:1], v[40:41], off
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v42, s30, 0
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v42, s31, 1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 8, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v8
+; GFX11-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s31, v42, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s30, v42, 0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s0, v42, 2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v4
+; GFX11-FAKE16-NEXT:    global_store_b64 v[40:41], v[0:1], off
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v41, off, s33
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s33 offset:4
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-SCRATCH-LABEL: test_call_external_void_func_v8i8_ret:
 ; GFX10-SCRATCH:       ; %bb.0:
@@ -5395,155 +5990,307 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_call_external_void_func_v32i8_ret:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, s33
-; GFX11-NEXT:    s_mov_b32 s33, s32
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_store_b32 off, v44, s33 offset:16 ; 4-byte Folded Spill
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_clause 0x3
-; GFX11-NEXT:    scratch_store_b32 off, v40, s33 offset:12
-; GFX11-NEXT:    scratch_store_b32 off, v41, s33 offset:8
-; GFX11-NEXT:    scratch_store_b32 off, v42, s33 offset:4
-; GFX11-NEXT:    scratch_store_b32 off, v43, s33
-; GFX11-NEXT:    v_mov_b32_e32 v40, 0
-; GFX11-NEXT:    v_dual_mov_b32 v41, 0 :: v_dual_mov_b32 v42, 16
-; GFX11-NEXT:    v_mov_b32_e32 v43, 0
-; GFX11-NEXT:    v_writelane_b32 v44, s0, 2
-; GFX11-NEXT:    s_mov_b32 s1, external_void_func_v3i8_ret@abs32@hi
-; GFX11-NEXT:    global_load_b128 v[0:3], v[40:41], off
-; GFX11-NEXT:    s_mov_b32 s0, external_void_func_v3i8_ret@abs32@lo
-; GFX11-NEXT:    global_load_b128 v[16:19], v[42:43], off
-; GFX11-NEXT:    v_writelane_b32 v44, s30, 0
-; GFX11-NEXT:    s_add_i32 s32, s32, 32
-; GFX11-NEXT:    v_writelane_b32 v44, s31, 1
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v35, 8, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v36, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v37, 24, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v32, 8, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v33, 16, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v34, 24, v16
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v11, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v21, 8, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v22, 16, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 24, v17
-; GFX11-NEXT:    v_lshrrev_b32_e32 v25, 8, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v26, 16, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v27, 24, v18
-; GFX11-NEXT:    v_lshrrev_b32_e32 v29, 8, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v30, 16, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v31, 24, v19
-; GFX11-NEXT:    v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v1, v35
-; GFX11-NEXT:    v_mov_b32_e32 v8, v2
-; GFX11-NEXT:    v_mov_b32_e32 v12, v3
-; GFX11-NEXT:    v_mov_b32_e32 v20, v17
-; GFX11-NEXT:    v_mov_b32_e32 v24, v18
-; GFX11-NEXT:    v_dual_mov_b32 v28, v19 :: v_dual_mov_b32 v19, v34
-; GFX11-NEXT:    v_dual_mov_b32 v2, v36 :: v_dual_mov_b32 v3, v37
-; GFX11-NEXT:    v_dual_mov_b32 v17, v32 :: v_dual_mov_b32 v18, v33
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT:    v_lshlrev_b16 v9, 8, v9
-; GFX11-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-NEXT:    v_lshlrev_b16 v11, 8, v11
-; GFX11-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-NEXT:    v_lshlrev_b16 v5, 8, v5
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-NEXT:    v_lshlrev_b16 v7, 8, v7
-; GFX11-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v13
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-NEXT:    v_or_b32_e32 v8, v8, v9
-; GFX11-NEXT:    v_or_b32_e32 v9, v10, v11
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v5
-; GFX11-NEXT:    v_or_b32_e32 v5, v6, v7
-; GFX11-NEXT:    v_or_b32_e32 v12, v12, v13
-; GFX11-NEXT:    v_lshlrev_b16 v13, 8, v15
-; GFX11-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v9
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v9, 16, v5
-; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT:    v_or_b32_e32 v13, v14, v13
-; GFX11-NEXT:    v_or_b32_e32 v5, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v4, v4, v9
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xff, v28
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshlrev_b16 v1, 8, v29
-; GFX11-NEXT:    v_lshlrev_b16 v8, 8, v31
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v30
-; GFX11-NEXT:    v_lshlrev_b16 v10, 8, v25
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v24
-; GFX11-NEXT:    v_and_b32_e32 v12, 0xffff, v12
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 16, v13
-; GFX11-NEXT:    v_lshlrev_b16 v3, 8, v3
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_or_b32_e32 v1, v7, v1
-; GFX11-NEXT:    v_or_b32_e32 v7, v9, v8
-; GFX11-NEXT:    v_or_b32_e32 v8, v11, v10
-; GFX11-NEXT:    v_or_b32_e32 v6, v12, v6
-; GFX11-NEXT:    v_or_b32_e32 v2, v2, v3
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xff, v26
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v7
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff, v8
-; GFX11-NEXT:    v_lshlrev_b16 v8, 8, v27
-; GFX11-NEXT:    v_lshlrev_b16 v10, 8, v21
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xff, v20
-; GFX11-NEXT:    v_lshlrev_b16 v12, 8, v23
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xff, v22
-; GFX11-NEXT:    v_lshlrev_b16 v14, 8, v17
-; GFX11-NEXT:    v_and_b32_e32 v15, 0xff, v16
-; GFX11-NEXT:    v_lshlrev_b16 v16, 8, v19
-; GFX11-NEXT:    v_and_b32_e32 v17, 0xff, v18
-; GFX11-NEXT:    v_or_b32_e32 v8, v9, v8
-; GFX11-NEXT:    v_or_b32_e32 v9, v11, v10
-; GFX11-NEXT:    v_or_b32_e32 v10, v13, v12
-; GFX11-NEXT:    v_or_b32_e32 v11, v15, v14
-; GFX11-NEXT:    v_or_b32_e32 v12, v17, v16
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT:    v_and_b32_e32 v13, 0xffff, v9
-; GFX11-NEXT:    v_lshlrev_b32_e32 v14, 16, v10
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff, v11
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT:    v_or_b32_e32 v10, v1, v3
-; GFX11-NEXT:    v_or_b32_e32 v9, v7, v8
-; GFX11-NEXT:    v_or_b32_e32 v8, v13, v14
-; GFX11-NEXT:    v_or_b32_e32 v7, v11, v12
-; GFX11-NEXT:    v_or_b32_e32 v3, v0, v2
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_store_b128 v[42:43], v[7:10], off
-; GFX11-NEXT:    global_store_b128 v[40:41], v[3:6], off
-; GFX11-NEXT:    s_clause 0x3
-; GFX11-NEXT:    scratch_load_b32 v43, off, s33
-; GFX11-NEXT:    scratch_load_b32 v42, off, s33 offset:4
-; GFX11-NEXT:    scratch_load_b32 v41, off, s33 offset:8
-; GFX11-NEXT:    scratch_load_b32 v40, off, s33 offset:12
-; GFX11-NEXT:    v_readlane_b32 s31, v44, 1
-; GFX11-NEXT:    v_readlane_b32 s30, v44, 0
-; GFX11-NEXT:    s_mov_b32 s32, s33
-; GFX11-NEXT:    v_readlane_b32 s0, v44, 2
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_load_b32 v44, off, s33 offset:16 ; 4-byte Folded Reload
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_mov_b32 s33, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test_call_external_void_func_v32i8_ret:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v44, s33 offset:16 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_clause 0x3
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v40, s33 offset:12
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v41, s33 offset:8
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v42, s33 offset:4
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v43, s33
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v40, 0
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v41, 0 :: v_dual_mov_b32 v42, 16
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v43, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v44, s0, 2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, external_void_func_v3i8_ret@abs32@hi
+; GFX11-TRUE16-NEXT:    global_load_b128 v[32:35], v[40:41], off
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, external_void_func_v3i8_ret@abs32@lo
+; GFX11-TRUE16-NEXT:    global_load_b128 v[36:39], v[42:43], off
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v44, s30, 0
+; GFX11-TRUE16-NEXT:    s_add_i32 s32, s32, 32
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v44, s31, 1
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v32
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v33
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v34
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v34
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v11, 24, v34
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v35
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v35
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v35
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v17, 8, v36
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v36
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v19, 24, v36
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v37
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v22, 16, v37
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v37
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v38
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v26, 16, v38
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v27, 24, v38
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v39
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v39
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v39
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v32.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v33.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v34.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v35.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v36.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.l, v37.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v24.l, v38.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.l, v39.l
+; GFX11-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v13.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v12.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.h, 8, v9.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v8.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v4.h, 8, v11.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v10.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v12.l, v1.h, v0.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v15.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v14.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v5.l, 8, v5.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v6.h, 8, v7.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v1.h, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v3.h, v2.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v9.l, v5.h, v4.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v4.l, v4.l, v5.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v5.l, v6.l, v6.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v7
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v1.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v5
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, v7, v8
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v28.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v29.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.h, 8, v25.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v24.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v3.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v4, v9
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v31.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v30.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v0.h
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.l, v3.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v2.l, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v6, v12, v6
+; GFX11-TRUE16-NEXT:    v_or_b16 v8.l, v2.h, v1.h
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff, v9
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v0.l
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.l, 8, v27.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v26.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v21.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v20.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v23.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v22.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v3.l, 8, v17.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v16.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v7.l, 8, v19.l
+; GFX11-TRUE16-NEXT:    v_and_b16 v7.h, 0xff, v18.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v2.l, v2.h, v2.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v3.l, v3.h, v3.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v7.l, v7.h, v7.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v9
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v10, v10, v8
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v9, v12, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, v1, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v7, v3, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v11, v13
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    global_store_b128 v[42:43], v[7:10], off
+; GFX11-TRUE16-NEXT:    global_store_b128 v[40:41], v[3:6], off
+; GFX11-TRUE16-NEXT:    s_clause 0x3
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v43, off, s33
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v42, off, s33 offset:4
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v41, off, s33 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v40, off, s33 offset:12
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s31, v44, 1
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s30, v44, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s0, v44, 2
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v44, off, s33 offset:16 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_call_external_void_func_v32i8_ret:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v44, s33 offset:16 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_clause 0x3
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s33 offset:12
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v41, s33 offset:8
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v42, s33 offset:4
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v43, s33
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v40, 0
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v41, 0 :: v_dual_mov_b32 v42, 16
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v43, 0
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v44, s0, 2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, external_void_func_v3i8_ret@abs32@hi
+; GFX11-FAKE16-NEXT:    global_load_b128 v[0:3], v[40:41], off
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, external_void_func_v3i8_ret@abs32@lo
+; GFX11-FAKE16-NEXT:    global_load_b128 v[16:19], v[42:43], off
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v44, s30, 0
+; GFX11-FAKE16-NEXT:    s_add_i32 s32, s32, 32
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v44, s31, 1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 8, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v37, 24, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v32, 8, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 24, v16
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v11, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 8, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 16, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 24, v17
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 8, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 16, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 24, v18
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v29, 8, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v30, 16, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v31, 24, v19
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v1, v35
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v2
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v12, v3
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v20, v17
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v24, v18
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v28, v19 :: v_dual_mov_b32 v19, v34
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v2, v36 :: v_dual_mov_b32 v3, v37
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v17, v32 :: v_dual_mov_b32 v18, v33
+; GFX11-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v9, 8, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v11, 8, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v13
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v8, v9
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v10, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v5
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v6, v7
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v12, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v13, 8, v15
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v13, v14, v13
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v9
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v28
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v29
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v31
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v30
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v10, 8, v25
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v13
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v7, v1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v9, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v11, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v6, v12, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v26
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v7
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff, v8
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v27
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v10, 8, v21
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v20
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v12, 8, v23
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v22
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v14, 8, v17
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v16
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v16, 8, v19
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v17, 0xff, v18
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v9, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v11, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v13, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v11, v15, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, v17, v16
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff, v9
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, v1, v3
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v9, v7, v8
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, v13, v14
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v7, v11, v12
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v0, v2
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    global_store_b128 v[42:43], v[7:10], off
+; GFX11-FAKE16-NEXT:    global_store_b128 v[40:41], v[3:6], off
+; GFX11-FAKE16-NEXT:    s_clause 0x3
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v43, off, s33
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v42, off, s33 offset:4
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v41, off, s33 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s33 offset:12
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s31, v44, 1
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s30, v44, 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s0, v44, 2
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v44, off, s33 offset:16 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-SCRATCH-LABEL: test_call_external_void_func_v32i8_ret:
 ; GFX10-SCRATCH:       ; %bb.0:
@@ -8474,38 +9221,71 @@ define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_call_external_void_func_struct_i8_i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, s33
-; GFX11-NEXT:    s_mov_b32 s33, s32
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    v_writelane_b32 v40, s0, 2
-; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x0
-; GFX11-NEXT:    v_mov_b32_e32 v1, 0
-; GFX11-NEXT:    s_add_i32 s32, s32, 16
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_load_u8 v0, v1, s[0:1]
-; GFX11-NEXT:    global_load_b32 v1, v1, s[0:1] offset:4
-; GFX11-NEXT:    v_writelane_b32 v40, s30, 0
-; GFX11-NEXT:    s_mov_b32 s1, external_void_func_struct_i8_i32@abs32@hi
-; GFX11-NEXT:    s_mov_b32 s0, external_void_func_struct_i8_i32@abs32@lo
-; GFX11-NEXT:    v_writelane_b32 v40, s31, 1
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_readlane_b32 s31, v40, 1
-; GFX11-NEXT:    v_readlane_b32 s30, v40, 0
-; GFX11-NEXT:    s_mov_b32 s32, s33
-; GFX11-NEXT:    v_readlane_b32 s0, v40, 2
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_mov_b32 s33, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test_call_external_void_func_struct_i8_i32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s0, 2
+; GFX11-TRUE16-NEXT:    s_load_b64 s[0:1], s[0:1], 0x0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s30, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    global_load_d16_u8 v0, v1, s[0:1]
+; GFX11-TRUE16-NEXT:    global_load_b32 v1, v1, s[0:1] offset:4
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, external_void_func_struct_i8_i32@abs32@hi
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, external_void_func_struct_i8_i32@abs32@lo
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s31, v40, 1
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s0, v40, 2
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_call_external_void_func_struct_i8_i32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s0, 2
+; GFX11-FAKE16-NEXT:    s_load_b64 s[0:1], s[0:1], 0x0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-FAKE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    global_load_u8 v0, v1, s[0:1]
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v1, s[0:1] offset:4
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s30, 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, external_void_func_struct_i8_i32@abs32@hi
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, external_void_func_struct_i8_i32@abs32@lo
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s31, v40, 1
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s0, v40, 2
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-SCRATCH-LABEL: test_call_external_void_func_struct_i8_i32:
 ; GFX10-SCRATCH:       ; %bb.0:
@@ -8611,37 +9391,70 @@ define amdgpu_gfx void @test_call_external_void_func_byval_struct_i8_i32() #0 {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_call_external_void_func_byval_struct_i8_i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, s33
-; GFX11-NEXT:    s_mov_b32 s33, s32
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_store_b32 off, v40, s33 offset:8 ; 4-byte Folded Spill
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    v_writelane_b32 v40, s0, 2
-; GFX11-NEXT:    v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 8
-; GFX11-NEXT:    s_mov_b32 s1, external_void_func_byval_struct_i8_i32@abs32@hi
-; GFX11-NEXT:    s_mov_b32 s0, external_void_func_byval_struct_i8_i32@abs32@lo
-; GFX11-NEXT:    v_writelane_b32 v40, s30, 0
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_store_b8 off, v0, s33
-; GFX11-NEXT:    scratch_store_b32 off, v1, s33 offset:4
-; GFX11-NEXT:    v_mov_b32_e32 v0, s33
-; GFX11-NEXT:    s_add_i32 s32, s32, 16
-; GFX11-NEXT:    v_writelane_b32 v40, s31, 1
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_readlane_b32 s31, v40, 1
-; GFX11-NEXT:    v_readlane_b32 s30, v40, 0
-; GFX11-NEXT:    s_mov_b32 s32, s33
-; GFX11-NEXT:    v_readlane_b32 s0, v40, 2
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_load_b32 v40, off, s33 offset:8 ; 4-byte Folded Reload
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_mov_b32 s33, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test_call_external_void_func_byval_struct_i8_i32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v40, s33 offset:8 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s0, 2
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, 3
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, external_void_func_byval_struct_i8_i32@abs32@hi
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, external_void_func_byval_struct_i8_i32@abs32@lo
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s30, 0
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_store_b8 off, v0, s33
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v1, s33 offset:4
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, s33
+; GFX11-TRUE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s31, v40, 1
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s0, v40, 2
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v40, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_call_external_void_func_byval_struct_i8_i32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s33 offset:8 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s0, 2
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 8
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, external_void_func_byval_struct_i8_i32@abs32@hi
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, external_void_func_byval_struct_i8_i32@abs32@lo
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s30, 0
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_store_b8 off, v0, s33
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v1, s33 offset:4
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, s33
+; GFX11-FAKE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s31, v40, 1
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s0, v40, 2
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s33 offset:8 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-SCRATCH-LABEL: test_call_external_void_func_byval_struct_i8_i32:
 ; GFX10-SCRATCH:       ; %bb.0:
@@ -8768,45 +9581,86 @@ define amdgpu_gfx void @test_call_external_void_func_sret_struct_i8_i32_byval_st
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, s33
-; GFX11-NEXT:    s_mov_b32 s33, s32
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_store_b32 off, v40, s33 offset:16 ; 4-byte Folded Spill
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    v_writelane_b32 v40, s0, 2
-; GFX11-NEXT:    v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 8
-; GFX11-NEXT:    s_add_i32 s32, s32, 32
-; GFX11-NEXT:    s_add_i32 s2, s33, 8
-; GFX11-NEXT:    v_writelane_b32 v40, s30, 0
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_store_b8 off, v0, s33
-; GFX11-NEXT:    scratch_store_b32 off, v1, s33 offset:4
-; GFX11-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s33
-; GFX11-NEXT:    s_mov_b32 s1, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@abs32@hi
-; GFX11-NEXT:    s_mov_b32 s0, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@abs32@lo
-; GFX11-NEXT:    v_writelane_b32 v40, s31, 1
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    scratch_load_u8 v0, off, s33 offset:8
-; GFX11-NEXT:    scratch_load_b32 v1, off, s33 offset:12
-; GFX11-NEXT:    v_readlane_b32 s31, v40, 1
-; GFX11-NEXT:    v_readlane_b32 s30, v40, 0
-; GFX11-NEXT:    s_mov_b32 s32, s33
-; GFX11-NEXT:    v_readlane_b32 s0, v40, 2
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b8 v[0:1], v0, off dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    global_store_b32 v[0:1], v1, off dlc
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_load_b32 v40, off, s33 offset:16 ; 4-byte Folded Reload
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_mov_b32 s33, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v40, s33 offset:16 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s0, 2
+; GFX11-TRUE16-NEXT:    s_add_i32 s32, s32, 32
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, 3
+; GFX11-TRUE16-NEXT:    s_add_i32 s2, s33, 8
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 8
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s30, 0
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_store_b8 off, v0, s33
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v1, s33 offset:4
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s33
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@abs32@hi
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@abs32@lo
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    scratch_load_d16_u8 v0, off, s33 offset:8
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v1, off, s33 offset:12
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s31, v40, 1
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s0, v40, 2
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    global_store_b32 v[0:1], v1, off dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v40, off, s33 offset:16 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s33 offset:16 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s0, 2
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 8
+; GFX11-FAKE16-NEXT:    s_add_i32 s32, s32, 32
+; GFX11-FAKE16-NEXT:    s_add_i32 s2, s33, 8
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s30, 0
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_store_b8 off, v0, s33
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v1, s33 offset:4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s33
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@abs32@hi
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@abs32@lo
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    scratch_load_u8 v0, off, s33 offset:8
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v1, off, s33 offset:12
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s31, v40, 1
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s0, v40, 2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    global_store_b32 v[0:1], v1, off dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s33 offset:16 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-SCRATCH-LABEL: test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32:
 ; GFX10-SCRATCH:       ; %bb.0:
@@ -8969,52 +9823,99 @@ define amdgpu_gfx void @test_call_external_void_func_v16i8() #0 {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_call_external_void_func_v16i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, s33
-; GFX11-NEXT:    s_mov_b32 s33, s32
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    v_writelane_b32 v40, s0, 2
-; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x0
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_add_i32 s32, s32, 16
-; GFX11-NEXT:    v_writelane_b32 v40, s30, 0
-; GFX11-NEXT:    v_writelane_b32 v40, s31, 1
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_b128 v[0:3], v0, s[0:1]
-; GFX11-NEXT:    s_mov_b32 s1, external_void_func_v16i8@abs32@hi
-; GFX11-NEXT:    s_mov_b32 s0, external_void_func_v16i8@abs32@lo
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v16, 8, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v17, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v18, 24, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v10, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v11, 24, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 8, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v14, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v15, 24, v3
-; GFX11-NEXT:    v_mov_b32_e32 v4, v1
-; GFX11-NEXT:    v_mov_b32_e32 v8, v2
-; GFX11-NEXT:    v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v3, v18
-; GFX11-NEXT:    v_dual_mov_b32 v1, v16 :: v_dual_mov_b32 v2, v17
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT:    v_readlane_b32 s31, v40, 1
-; GFX11-NEXT:    v_readlane_b32 s30, v40, 0
-; GFX11-NEXT:    s_mov_b32 s32, s33
-; GFX11-NEXT:    v_readlane_b32 s0, v40, 2
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_mov_b32 s33, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test_call_external_void_func_v16i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s0, 2
+; GFX11-TRUE16-NEXT:    s_load_b64 s[0:1], s[0:1], 0x0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-TRUE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s30, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b128 v[16:19], v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, external_void_func_v16i8@abs32@hi
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, external_void_func_v16i8@abs32@lo
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v16
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v17
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v11, 24, v18
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v19
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v16.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v17.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v18.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v19.l
+; GFX11-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s31, v40, 1
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s0, v40, 2
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_call_external_void_func_v16i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s0, 2
+; GFX11-FAKE16-NEXT:    s_load_b64 s[0:1], s[0:1], 0x0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-FAKE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s30, 0
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b128 v[0:3], v0, s[0:1]
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, external_void_func_v16i8@abs32@hi
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, external_void_func_v16i8@abs32@lo
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 8, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 24, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v11, 24, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 8, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 24, v3
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v1
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v2
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v3, v18
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v1, v16 :: v_dual_mov_b32 v2, v17
+; GFX11-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s31, v40, 1
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s0, v40, 2
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-SCRATCH-LABEL: test_call_external_void_func_v16i8:
 ; GFX10-SCRATCH:       ; %bb.0:
@@ -17319,32 +18220,61 @@ define amdgpu_gfx void @test_call_external_void_func_bf16_inreg(i16 inreg %arg)
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_call_external_void_func_bf16_inreg:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s0, s33
-; GFX11-NEXT:    s_mov_b32 s33, s32
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    v_writelane_b32 v40, s0, 2
-; GFX11-NEXT:    s_mov_b32 s1, external_void_func_bf16@abs32@hi
-; GFX11-NEXT:    s_mov_b32 s0, external_void_func_bf16@abs32@lo
-; GFX11-NEXT:    s_add_i32 s32, s32, 16
-; GFX11-NEXT:    v_writelane_b32 v40, s30, 0
-; GFX11-NEXT:    v_writelane_b32 v40, s31, 1
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_readlane_b32 s31, v40, 1
-; GFX11-NEXT:    v_readlane_b32 s30, v40, 0
-; GFX11-NEXT:    s_mov_b32 s32, s33
-; GFX11-NEXT:    v_readlane_b32 s0, v40, 2
-; GFX11-NEXT:    s_or_saveexec_b32 s1, -1
-; GFX11-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_mov_b32 s33, s0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test_call_external_void_func_bf16_inreg:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s0, 3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, external_void_func_bf16@abs32@hi
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, external_void_func_bf16@abs32@lo
+; GFX11-TRUE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s4, 0
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s30, 1
+; GFX11-TRUE16-NEXT:    v_writelane_b32 v40, s31, 2
+; GFX11-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s31, v40, 2
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s30, v40, 1
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s4, v40, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-TRUE16-NEXT:    v_readlane_b32 s0, v40, 3
+; GFX11-TRUE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-TRUE16-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_call_external_void_func_bf16_inreg:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s33
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s32
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s0, 2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, external_void_func_bf16@abs32@hi
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, external_void_func_bf16@abs32@lo
+; GFX11-FAKE16-NEXT:    s_add_i32 s32, s32, 16
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s30, 0
+; GFX11-FAKE16-NEXT:    v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s31, v40, 1
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s32, s33
+; GFX11-FAKE16-NEXT:    v_readlane_b32 s0, v40, 2
+; GFX11-FAKE16-NEXT:    s_or_saveexec_b32 s1, -1
+; GFX11-FAKE16-NEXT:    scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s33, s0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-SCRATCH-LABEL: test_call_external_void_func_bf16_inreg:
 ; GFX10-SCRATCH:       ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll b/llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
index 3685ac18ab4d4..63376def3d7e1 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
+++ b/llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
@@ -1,9 +1,13 @@
-; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,WORKAROUND %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,WORKAROUND %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,WORKAROUND,WORKAROUND-TRUE16-SDAG %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,WORKAROUND,WORKAROUND-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,WORKAROUND %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,WORKAROUND,WORKAROUND-FAKE16 %s
 
 ; Does not apply to wave64
-; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+wavefrontsize64 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,NOWORKAROUND %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+wavefrontsize64 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,NOWORKAROUND %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 -mattr=+wavefrontsize64 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,NOWORKAROUND %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 -mattr=+wavefrontsize64 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,NOWORKAROUND %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 -mattr=+wavefrontsize64 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,NOWORKAROUND %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 -mattr=+wavefrontsize64 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,NOWORKAROUND %s
 
 ; Does not apply to gfx1101
 ; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1101 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,NOWORKAROUND %s
@@ -83,7 +87,8 @@ define amdgpu_kernel void @minimal_kernel_inputs_with_stack() #0 {
 }
 
 ; GCN-LABEL: {{^}}queue_ptr:
-; GCN: global_load_u8 v{{[0-9]+}},
+; WORKAROUND-TRUE16-SDAG: global_load_d16_u8
+; WORKAROUND-FAKE16: global_load_u8 v{{[0-9]+}},
 
 ; WORKAROUND: v_mov_b32_e32 [[V:v[0-9]+]], s15
 ; NOWORKAROUND: v_mov_b32_e32 [[V:v[0-9]+]], s4
@@ -124,9 +129,13 @@ define amdgpu_kernel void @queue_ptr() #1 {
 ; NOWORKAROUND: v_mov_b32_e32 [[V_Y:v[0-9]+]], s9
 ; NOWORKAROUND: v_mov_b32_e32 [[V_Z:v[0-9]+]], s10
 
-; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[0:1]
-; GCN: global_load_u8 v{{[0-9]+}},
-; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[4:5]
+; WORKAROUND-TRUE16-SDAG: global_load_d16_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[0:1]
+; WORKAROUND-TRUE16-SDAG: global_load_d16_u8 v{{[0-9]+}},
+; WORKAROUND-TRUE16-SDAG: global_load_d16_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[4:5]
+
+; WORKAROUND-FAKE16: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[0:1]
+; WORKAROUND-FAKE16: global_load_u8 v{{[0-9]+}},
+; WORKAROUND-FAKE16: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[4:5]
 
 ; GCN-DAG: v_mov_b32_e32 v[[DISPATCH_LO:[0-9]+]], s6
 ; GCN-DAG: v_mov_b32_e32 v[[DISPATCH_HI:[0-9]+]], s7
@@ -196,5 +205,3 @@ attributes #1 = { "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-ld
 attributes #2 = { "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }
 attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll b/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
index a33aeac255372..28245c538a04c 100644
--- a/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
@@ -1,9 +1,12 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GCN,GFX10 %s
-; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11 %s
-; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
+; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=+real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=-real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -mattr=+real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -mattr=-real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -mattr=+real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -mattr=-real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
 
 ; Test using saddr addressing mode of global_*load_* flat instructions.
 
@@ -2284,17 +2287,35 @@ define amdgpu_ps half @global_load_saddr_i16(ptr addrspace(1) inreg %sbase, i32
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: global_load_saddr_i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    global_load_u16 v0, v0, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: global_load_saddr_i16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    global_load_u16 v0, v0, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: global_load_saddr_i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v0, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: global_load_saddr_i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    global_load_u16 v0, v0, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-SDAG-TRUE16-LABEL: global_load_saddr_i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_b16 v0, v0, s[2:3]
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-SDAG-FAKE16-LABEL: global_load_saddr_i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u16 v0, v0, s[2:3]
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-LABEL: global_load_saddr_i16:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    global_load_u16 v0, v0, s[2:3]
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    ; return to shader part epilog
   %zext.offset = zext i32 %voffset to i64
   %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset
   %load = load i16, ptr addrspace(1) %gep0
@@ -2309,17 +2330,35 @@ define amdgpu_ps half @global_load_saddr_i16_immneg128(ptr addrspace(1) inreg %s
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: global_load_saddr_i16_immneg128:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    global_load_u16 v0, v0, s[2:3] offset:-128
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: global_load_saddr_i16_immneg128:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    global_load_u16 v0, v0, s[2:3] offset:-128
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: global_load_saddr_i16_immneg128:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v0, s[2:3] offset:-128
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: global_load_saddr_i16_immneg128:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    global_load_u16 v0, v0, s[2:3] offset:-128
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-SDAG-TRUE16-LABEL: global_load_saddr_i16_immneg128:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_b16 v0, v0, s[2:3] offset:-128
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-SDAG-FAKE16-LABEL: global_load_saddr_i16_immneg128:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u16 v0, v0, s[2:3] offset:-128
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-LABEL: global_load_saddr_i16_immneg128:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    global_load_u16 v0, v0, s[2:3] offset:-128
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    ; return to shader part epilog
   %zext.offset = zext i32 %voffset to i64
   %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset
   %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128
@@ -2335,17 +2374,35 @@ define amdgpu_ps half @global_load_saddr_f16(ptr addrspace(1) inreg %sbase, i32
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: global_load_saddr_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    global_load_u16 v0, v0, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: global_load_saddr_f16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    global_load_u16 v0, v0, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: global_load_saddr_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v0, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: global_load_saddr_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    global_load_u16 v0, v0, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-SDAG-TRUE16-LABEL: global_load_saddr_f16:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_b16 v0, v0, s[2:3]
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-SDAG-FAKE16-LABEL: global_load_saddr_f16:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u16 v0, v0, s[2:3]
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-LABEL: global_load_saddr_f16:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    global_load_u16 v0, v0, s[2:3]
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    ; return to shader part epilog
   %zext.offset = zext i32 %voffset to i64
   %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset
   %load = load half, ptr addrspace(1) %gep0
@@ -2359,17 +2416,35 @@ define amdgpu_ps half @global_load_saddr_f16_immneg128(ptr addrspace(1) inreg %s
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: global_load_saddr_f16_immneg128:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    global_load_u16 v0, v0, s[2:3] offset:-128
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: global_load_saddr_f16_immneg128:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    global_load_u16 v0, v0, s[2:3] offset:-128
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: global_load_saddr_f16_immneg128:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v0, s[2:3] offset:-128
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: global_load_saddr_f16_immneg128:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    global_load_u16 v0, v0, s[2:3] offset:-128
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-SDAG-TRUE16-LABEL: global_load_saddr_f16_immneg128:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_b16 v0, v0, s[2:3] offset:-128
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-SDAG-FAKE16-LABEL: global_load_saddr_f16_immneg128:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u16 v0, v0, s[2:3] offset:-128
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-LABEL: global_load_saddr_f16_immneg128:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    global_load_u16 v0, v0, s[2:3] offset:-128
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    ; return to shader part epilog
   %zext.offset = zext i32 %voffset to i64
   %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset
   %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128
@@ -3841,11 +3916,17 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_undef_hi(ptr addrspace(
 ; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
 ; GFX12-SDAG-NEXT:    ; return to shader part epilog
 ;
-; GFX12-GISEL-LABEL: global_load_saddr_i16_d16lo_undef_hi:
-; GFX12-GISEL:       ; %bb.0:
-; GFX12-GISEL-NEXT:    global_load_u16 v0, v0, s[2:3]
-; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT:    ; return to shader part epilog
+; GFX12-GISEL-TRUE16-LABEL: global_load_saddr_i16_d16lo_undef_hi:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    global_load_d16_b16 v0, v0, s[2:3]
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-FAKE16-LABEL: global_load_saddr_i16_d16lo_undef_hi:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    global_load_u16 v0, v0, s[2:3]
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    ; return to shader part epilog
   %zext.offset = zext i32 %voffset to i64
   %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset
   %load = load i16, ptr addrspace(1) %gep0
@@ -3873,11 +3954,17 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_undef_hi_immneg128(ptr
 ; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
 ; GFX12-SDAG-NEXT:    ; return to shader part epilog
 ;
-; GFX12-GISEL-LABEL: global_load_saddr_i16_d16lo_undef_hi_immneg128:
-; GFX12-GISEL:       ; %bb.0:
-; GFX12-GISEL-NEXT:    global_load_u16 v0, v0, s[2:3] offset:-128
-; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT:    ; return to shader part epilog
+; GFX12-GISEL-TRUE16-LABEL: global_load_saddr_i16_d16lo_undef_hi_immneg128:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    global_load_d16_b16 v0, v0, s[2:3] offset:-128
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-FAKE16-LABEL: global_load_saddr_i16_d16lo_undef_hi_immneg128:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    global_load_u16 v0, v0, s[2:3] offset:-128
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    ; return to shader part epilog
   %zext.offset = zext i32 %voffset to i64
   %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset
   %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128
@@ -3912,12 +3999,19 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_zero_hi(ptr addrspace(1
 ; GFX12-SDAG-NEXT:    v_mov_b32_e32 v0, v1
 ; GFX12-SDAG-NEXT:    ; return to shader part epilog
 ;
-; GFX12-GISEL-LABEL: global_load_saddr_i16_d16lo_zero_hi:
-; GFX12-GISEL:       ; %bb.0:
-; GFX12-GISEL-NEXT:    global_load_u16 v0, v0, s[2:3]
-; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-GISEL-NEXT:    ; return to shader part epilog
+; GFX12-GISEL-TRUE16-LABEL: global_load_saddr_i16_d16lo_zero_hi:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    global_load_d16_b16 v0, v0, s[2:3]
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-GISEL-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-FAKE16-LABEL: global_load_saddr_i16_d16lo_zero_hi:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    global_load_u16 v0, v0, s[2:3]
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-GISEL-FAKE16-NEXT:    ; return to shader part epilog
   %zext.offset = zext i32 %voffset to i64
   %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset
   %load = load i16, ptr addrspace(1) %gep0
@@ -3951,12 +4045,19 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_zero_hi_immneg128(ptr a
 ; GFX12-SDAG-NEXT:    v_mov_b32_e32 v0, v1
 ; GFX12-SDAG-NEXT:    ; return to shader part epilog
 ;
-; GFX12-GISEL-LABEL: global_load_saddr_i16_d16lo_zero_hi_immneg128:
-; GFX12-GISEL:       ; %bb.0:
-; GFX12-GISEL-NEXT:    global_load_u16 v0, v0, s[2:3] offset:-128
-; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-GISEL-NEXT:    ; return to shader part epilog
+; GFX12-GISEL-TRUE16-LABEL: global_load_saddr_i16_d16lo_zero_hi_immneg128:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    global_load_d16_b16 v0, v0, s[2:3] offset:-128
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-GISEL-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-FAKE16-LABEL: global_load_saddr_i16_d16lo_zero_hi_immneg128:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    global_load_u16 v0, v0, s[2:3] offset:-128
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-GISEL-FAKE16-NEXT:    ; return to shader part epilog
   %zext.offset = zext i32 %voffset to i64
   %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset
   %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128
@@ -4216,12 +4317,19 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_undef_hi(ptr addrspace(
 ; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
 ; GFX12-SDAG-NEXT:    ; return to shader part epilog
 ;
-; GFX12-GISEL-LABEL: global_load_saddr_i16_d16hi_undef_hi:
-; GFX12-GISEL:       ; %bb.0:
-; GFX12-GISEL-NEXT:    global_load_u16 v0, v0, s[2:3]
-; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
-; GFX12-GISEL-NEXT:    ; return to shader part epilog
+; GFX12-GISEL-TRUE16-LABEL: global_load_saddr_i16_d16hi_undef_hi:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    global_load_d16_b16 v0, v0, s[2:3]
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-GISEL-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-FAKE16-LABEL: global_load_saddr_i16_d16hi_undef_hi:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    global_load_u16 v0, v0, s[2:3]
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-GISEL-FAKE16-NEXT:    ; return to shader part epilog
   %zext.offset = zext i32 %voffset to i64
   %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset
   %load = load i16, ptr addrspace(1) %gep0
@@ -4249,12 +4357,19 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_undef_hi_immneg128(ptr
 ; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
 ; GFX12-SDAG-NEXT:    ; return to shader part epilog
 ;
-; GFX12-GISEL-LABEL: global_load_saddr_i16_d16hi_undef_hi_immneg128:
-; GFX12-GISEL:       ; %bb.0:
-; GFX12-GISEL-NEXT:    global_load_u16 v0, v0, s[2:3] offset:-128
-; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
-; GFX12-GISEL-NEXT:    ; return to shader part epilog
+; GFX12-GISEL-TRUE16-LABEL: global_load_saddr_i16_d16hi_undef_hi_immneg128:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    global_load_d16_b16 v0, v0, s[2:3] offset:-128
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-GISEL-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-FAKE16-LABEL: global_load_saddr_i16_d16hi_undef_hi_immneg128:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    global_load_u16 v0, v0, s[2:3] offset:-128
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-GISEL-FAKE16-NEXT:    ; return to shader part epilog
   %zext.offset = zext i32 %voffset to i64
   %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset
   %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128
@@ -4289,12 +4404,19 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_zero_hi(ptr addrspace(1
 ; GFX12-SDAG-NEXT:    v_mov_b32_e32 v0, v1
 ; GFX12-SDAG-NEXT:    ; return to shader part epilog
 ;
-; GFX12-GISEL-LABEL: global_load_saddr_i16_d16hi_zero_hi:
-; GFX12-GISEL:       ; %bb.0:
-; GFX12-GISEL-NEXT:    global_load_u16 v0, v0, s[2:3]
-; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
-; GFX12-GISEL-NEXT:    ; return to shader part epilog
+; GFX12-GISEL-TRUE16-LABEL: global_load_saddr_i16_d16hi_zero_hi:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    global_load_d16_b16 v0, v0, s[2:3]
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-GISEL-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-FAKE16-LABEL: global_load_saddr_i16_d16hi_zero_hi:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    global_load_u16 v0, v0, s[2:3]
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-GISEL-FAKE16-NEXT:    ; return to shader part epilog
   %zext.offset = zext i32 %voffset to i64
   %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset
   %load = load i16, ptr addrspace(1) %gep0
@@ -4328,12 +4450,19 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_zero_hi_immneg128(ptr a
 ; GFX12-SDAG-NEXT:    v_mov_b32_e32 v0, v1
 ; GFX12-SDAG-NEXT:    ; return to shader part epilog
 ;
-; GFX12-GISEL-LABEL: global_load_saddr_i16_d16hi_zero_hi_immneg128:
-; GFX12-GISEL:       ; %bb.0:
-; GFX12-GISEL-NEXT:    global_load_u16 v0, v0, s[2:3] offset:-128
-; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
-; GFX12-GISEL-NEXT:    ; return to shader part epilog
+; GFX12-GISEL-TRUE16-LABEL: global_load_saddr_i16_d16hi_zero_hi_immneg128:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    global_load_d16_b16 v0, v0, s[2:3] offset:-128
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-GISEL-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-FAKE16-LABEL: global_load_saddr_i16_d16hi_zero_hi_immneg128:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    global_load_u16 v0, v0, s[2:3] offset:-128
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-GISEL-FAKE16-NEXT:    ; return to shader part epilog
   %zext.offset = zext i32 %voffset to i64
   %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset
   %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
index 9d5b324b271cb..82c58394c03bb 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
@@ -14728,6 +14728,4 @@ attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign"  }
 attributes #1 = { strictfp "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
 attributes #2 = { strictfp }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
 !1 = !{}
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
index aad38411d12e6..f8f911b693e09 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
@@ -9465,7 +9465,5 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_uni_value_system_scope
 
 attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
 !1 = !{}
 
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
index 478daf363820f..1f76a476107a3 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
@@ -9465,6 +9465,4 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_uni_value_system_scope
 
 attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
 !1 = !{}
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
index 66f8c2de30530..9db3c37045ccf 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
@@ -14362,5 +14362,3 @@ attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
 attributes #1 = { strictfp "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
 attributes #2 = { strictfp }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/half.ll b/llvm/test/CodeGen/AMDGPU/half.ll
index 10573aad38a51..f767511370eee 100644
--- a/llvm/test/CodeGen/AMDGPU/half.ll
+++ b/llvm/test/CodeGen/AMDGPU/half.ll
@@ -1,7 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=CIVI,CI %s
 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=CIVI,VI %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=GFX11 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 ; half args should be promoted to float for CI and lower.
 
@@ -961,15 +962,25 @@ define amdgpu_kernel void @global_load_store_f16(ptr addrspace(1) %out, ptr addr
 ; CIVI-NEXT:    flat_store_short v[0:1], v2
 ; CIVI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_load_store_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u16 v1, v0, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: global_load_store_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: global_load_store_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %val = load half, ptr addrspace(1) %in
   store half %val, ptr addrspace(1) %out
   ret void
@@ -1086,16 +1097,27 @@ define amdgpu_kernel void @global_extload_f16_to_f32(ptr addrspace(1) %out, ptr
 ; CIVI-NEXT:    flat_store_dword v[0:1], v2
 ; CIVI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_extload_f16_to_f32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u16 v1, v0, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; GFX11-NEXT:    global_store_b32 v0, v1, s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: global_extload_f16_to_f32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT:    global_store_b32 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: global_extload_f16_to_f32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; GFX11-FAKE16-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %val = load half, ptr addrspace(1) %in
   %cvt = fpext half %val to float
   store float %cvt, ptr addrspace(1) %out
@@ -1140,19 +1162,33 @@ define amdgpu_kernel void @global_extload_v2f16_to_v2f32(ptr addrspace(1) %out,
 ; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_extload_v2f16_to_v2f32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT:    v_mov_b32_e32 v2, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v2, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; GFX11-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: global_extload_v2f16_to_v2f32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v2, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v1.l
+; GFX11-TRUE16-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: global_extload_v2f16_to_v2f32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v2, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; GFX11-FAKE16-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %val = load <2 x half>, ptr addrspace(1) %in
   %cvt = fpext <2 x half> %val to <2 x float>
   store <2 x float> %cvt, ptr addrspace(1) %out
@@ -1199,20 +1235,35 @@ define amdgpu_kernel void @global_extload_v3f16_to_v3f32(ptr addrspace(1) %out,
 ; VI-NEXT:    flat_store_dwordx3 v[3:4], v[0:2]
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_extload_v3f16_to_v3f32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT:    v_mov_b32_e32 v3, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[0:1], v3, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v2, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v1, v4
-; GFX11-NEXT:    global_store_b96 v3, v[0:2], s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: global_extload_v3f16_to_v3f32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v3, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b64 v[0:1], v3, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v2, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v4.l
+; GFX11-TRUE16-NEXT:    global_store_b96 v3, v[0:2], s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: global_extload_v3f16_to_v3f32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v3, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[0:1], v3, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v2, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v1, v4
+; GFX11-FAKE16-NEXT:    global_store_b96 v3, v[0:2], s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %val = load <3 x half>, ptr addrspace(1) %in
   %cvt = fpext <3 x half> %val to <3 x float>
   store <3 x float> %cvt, ptr addrspace(1) %out
@@ -1262,22 +1313,39 @@ define amdgpu_kernel void @global_extload_v4f16_to_v4f32(ptr addrspace(1) %out,
 ; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_extload_v4f16_to_v4f32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT:    v_mov_b32_e32 v4, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[0:1], v4, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v2, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v3, v3
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v1, v5
-; GFX11-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: global_extload_v4f16_to_v4f32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v4, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b64 v[0:1], v4, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v2, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v3, v3.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v5.l
+; GFX11-TRUE16-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: global_extload_v4f16_to_v4f32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[0:1], v4, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v2, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v3, v3
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v1, v5
+; GFX11-FAKE16-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %val = load <4 x half>, ptr addrspace(1) %in
   %cvt = fpext <4 x half> %val to <4 x float>
   store <4 x float> %cvt, ptr addrspace(1) %out
@@ -1347,29 +1415,53 @@ define amdgpu_kernel void @global_extload_v8f16_to_v8f32(ptr addrspace(1) %out,
 ; VI-NEXT:    flat_store_dwordx4 v[12:13], v[4:7]
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_extload_v8f16_to_v8f32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT:    v_mov_b32_e32 v12, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_b128 v[0:3], v12, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 16, v2
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v6, v1
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v4, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v10, v3
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v8, v2
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v11, v5
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v9, v9
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v7, v1
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v5, v0
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_store_b128 v12, v[8:11], s[0:1] offset:16
-; GFX11-NEXT:    global_store_b128 v12, v[4:7], s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: global_extload_v8f16_to_v8f32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v12, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b128 v[0:3], v12, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v2
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v6, v1.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v4, v0.l
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v10, v3.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v8, v2.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v11, v5.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v9, v9.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v7, v1.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v5, v0.l
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    global_store_b128 v12, v[8:11], s[0:1] offset:16
+; GFX11-TRUE16-NEXT:    global_store_b128 v12, v[4:7], s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: global_extload_v8f16_to_v8f32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v12, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b128 v[0:3], v12, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v6, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v4, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v10, v3
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v8, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v11, v5
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v9, v9
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v7, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v5, v0
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    global_store_b128 v12, v[8:11], s[0:1] offset:16
+; GFX11-FAKE16-NEXT:    global_store_b128 v12, v[4:7], s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %val = load <8 x half>, ptr addrspace(1) %in
   %cvt = fpext <8 x half> %val to <8 x float>
   store <8 x float> %cvt, ptr addrspace(1) %out
@@ -1491,46 +1583,87 @@ define amdgpu_kernel void @global_extload_v16f16_to_v16f32(ptr addrspace(1) %out
 ; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_extload_v16f16_to_v16f32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT:    v_mov_b32_e32 v20, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_load_b128 v[0:3], v20, s[2:3]
-; GFX11-NEXT:    global_load_b128 v[4:7], v20, s[2:3] offset:16
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v10, v1
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v18, v7
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v16, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v8, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 16, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v14, v3
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v12, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v13, 16, v2
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v2, v5
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v4
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v19, v7
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v17, v6
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v11, v1
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v15, v3
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v3, v5
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v1, v4
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v13, v13
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v9, v9
-; GFX11-NEXT:    s_clause 0x3
-; GFX11-NEXT:    global_store_b128 v20, v[16:19], s[0:1] offset:48
-; GFX11-NEXT:    global_store_b128 v20, v[0:3], s[0:1] offset:32
-; GFX11-NEXT:    global_store_b128 v20, v[12:15], s[0:1] offset:16
-; GFX11-NEXT:    global_store_b128 v20, v[8:11], s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: global_extload_v16f16_to_v16f32:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v20, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    global_load_b128 v[0:3], v20, s[2:3]
+; GFX11-TRUE16-NEXT:    global_load_b128 v[4:7], v20, s[2:3] offset:16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v10, v1.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v18, v7.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v16, v6.l
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v8, v0.l
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v0
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v14, v3.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v12, v2.l
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v13, 16, v2
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v2, v5.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v4.l
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v19, v7.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v17, v6.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v11, v1.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v15, v3.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v3, v5.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v4.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v13, v13.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v9, v9.l
+; GFX11-TRUE16-NEXT:    s_clause 0x3
+; GFX11-TRUE16-NEXT:    global_store_b128 v20, v[16:19], s[0:1] offset:48
+; GFX11-TRUE16-NEXT:    global_store_b128 v20, v[0:3], s[0:1] offset:32
+; GFX11-TRUE16-NEXT:    global_store_b128 v20, v[12:15], s[0:1] offset:16
+; GFX11-TRUE16-NEXT:    global_store_b128 v20, v[8:11], s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: global_extload_v16f16_to_v16f32:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v20, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    global_load_b128 v[0:3], v20, s[2:3]
+; GFX11-FAKE16-NEXT:    global_load_b128 v[4:7], v20, s[2:3] offset:16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v10, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v18, v7
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v16, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v8, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v14, v3
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v12, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 16, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v2, v5
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v4
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v19, v7
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v17, v6
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v11, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v15, v3
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v3, v5
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v1, v4
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v13, v13
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v9, v9
+; GFX11-FAKE16-NEXT:    s_clause 0x3
+; GFX11-FAKE16-NEXT:    global_store_b128 v20, v[16:19], s[0:1] offset:48
+; GFX11-FAKE16-NEXT:    global_store_b128 v20, v[0:3], s[0:1] offset:32
+; GFX11-FAKE16-NEXT:    global_store_b128 v20, v[12:15], s[0:1] offset:16
+; GFX11-FAKE16-NEXT:    global_store_b128 v20, v[8:11], s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %val = load <16 x half>, ptr addrspace(1) %in
   %cvt = fpext <16 x half> %val to <16 x float>
   store <16 x float> %cvt, ptr addrspace(1) %out
@@ -1556,18 +1689,31 @@ define amdgpu_kernel void @global_extload_f16_to_f64(ptr addrspace(1) %out, ptr
 ; CIVI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
 ; CIVI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_extload_f16_to_f64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT:    v_mov_b32_e32 v2, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u16 v0, v2, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
-; GFX11-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: global_extload_f16_to_f64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v2, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
+; GFX11-TRUE16-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: global_extload_f16_to_f64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_u16 v0, v2, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
+; GFX11-FAKE16-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %val = load half, ptr addrspace(1) %in
   %cvt = fpext half %val to double
   store double %cvt, ptr addrspace(1) %out
@@ -1616,22 +1762,39 @@ define amdgpu_kernel void @global_extload_v2f16_to_v2f64(ptr addrspace(1) %out,
 ; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_extload_v2f16_to_v2f64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT:    v_mov_b32_e32 v4, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v4, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v2, v1
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[2:3], v2
-; GFX11-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: global_extload_v2f16_to_v2f64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v4, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v4, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v2, v1.l
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[2:3], v2
+; GFX11-TRUE16-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: global_extload_v2f16_to_v2f64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v4, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v2, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[2:3], v2
+; GFX11-FAKE16-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %val = load <2 x half>, ptr addrspace(1) %in
   %cvt = fpext <2 x half> %val to <2 x double>
   store <2 x double> %cvt, ptr addrspace(1) %out
@@ -1694,26 +1857,47 @@ define amdgpu_kernel void @global_extload_v3f16_to_v3f64(ptr addrspace(1) %out,
 ; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_extload_v3f16_to_v3f64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT:    v_mov_b32_e32 v6, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[0:1], v6, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v3, v1
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v2, v2
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[4:5], v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[2:3], v2
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_store_b64 v6, v[4:5], s[0:1] offset:16
-; GFX11-NEXT:    global_store_b128 v6, v[0:3], s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: global_extload_v3f16_to_v3f64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v6, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b64 v[0:1], v6, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v3, v1.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v2, v2.l
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[4:5], v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[2:3], v2
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    global_store_b64 v6, v[4:5], s[0:1] offset:16
+; GFX11-TRUE16-NEXT:    global_store_b128 v6, v[0:3], s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: global_extload_v3f16_to_v3f64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v6, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[0:1], v6, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v3, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v2, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[4:5], v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[2:3], v2
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    global_store_b64 v6, v[4:5], s[0:1] offset:16
+; GFX11-FAKE16-NEXT:    global_store_b128 v6, v[0:3], s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %val = load <3 x half>, ptr addrspace(1) %in
   %cvt = fpext <3 x half> %val to <3 x double>
   store <3 x double> %cvt, ptr addrspace(1) %out
@@ -1781,30 +1965,55 @@ define amdgpu_kernel void @global_extload_v4f16_to_v4f64(ptr addrspace(1) %out,
 ; VI-NEXT:    flat_store_dwordx4 v[8:9], v[0:3]
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_extload_v4f16_to_v4f64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT:    v_mov_b32_e32 v8, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[0:1], v8, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v4, v1
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v2, v2
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v3, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[4:5], v4
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[6:7], v2
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[2:3], v3
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_store_b128 v8, v[4:7], s[0:1] offset:16
-; GFX11-NEXT:    global_store_b128 v8, v[0:3], s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: global_extload_v4f16_to_v4f64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v8, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b64 v[0:1], v8, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v4, v1.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v2, v2.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v3, v3.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[4:5], v4
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[6:7], v2
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[2:3], v3
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    global_store_b128 v8, v[4:7], s[0:1] offset:16
+; GFX11-TRUE16-NEXT:    global_store_b128 v8, v[0:3], s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: global_extload_v4f16_to_v4f64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[0:1], v8, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v4, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v2, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v3, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[4:5], v4
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[6:7], v2
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[2:3], v3
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    global_store_b128 v8, v[4:7], s[0:1] offset:16
+; GFX11-FAKE16-NEXT:    global_store_b128 v8, v[0:3], s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %val = load <4 x half>, ptr addrspace(1) %in
   %cvt = fpext <4 x half> %val to <4 x double>
   store <4 x double> %cvt, ptr addrspace(1) %out
@@ -1910,39 +2119,73 @@ define amdgpu_kernel void @global_extload_v8f16_to_v8f64(ptr addrspace(1) %out,
 ; VI-NEXT:    flat_store_dwordx4 v[12:13], v[0:3]
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_extload_v8f16_to_v8f64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT:    v_mov_b32_e32 v16, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_b128 v[0:3], v16, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v4, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v6, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 16, v3
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v8, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v3, v3
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[0:1], v4
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v17, v5
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[4:5], v6
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v6, v9
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v2, v2
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v7, v7
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[12:13], v3
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[8:9], v8
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[14:15], v6
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[10:11], v2
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[6:7], v7
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[2:3], v17
-; GFX11-NEXT:    s_clause 0x3
-; GFX11-NEXT:    global_store_b128 v16, v[12:15], s[0:1] offset:48
-; GFX11-NEXT:    global_store_b128 v16, v[8:11], s[0:1] offset:32
-; GFX11-NEXT:    global_store_b128 v16, v[4:7], s[0:1] offset:16
-; GFX11-NEXT:    global_store_b128 v16, v[0:3], s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: global_extload_v8f16_to_v8f64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v16, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b128 v[0:3], v16, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v4, v0.l
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v6, v1.l
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v3
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v8, v2.l
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v1
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v3, v3.l
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v4
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v17, v5.l
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[4:5], v6
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v6, v9.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v2, v2.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v7, v7.l
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[12:13], v3
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[8:9], v8
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[14:15], v6
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[10:11], v2
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[6:7], v7
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[2:3], v17
+; GFX11-TRUE16-NEXT:    s_clause 0x3
+; GFX11-TRUE16-NEXT:    global_store_b128 v16, v[12:15], s[0:1] offset:48
+; GFX11-TRUE16-NEXT:    global_store_b128 v16, v[8:11], s[0:1] offset:32
+; GFX11-TRUE16-NEXT:    global_store_b128 v16, v[4:7], s[0:1] offset:16
+; GFX11-TRUE16-NEXT:    global_store_b128 v16, v[0:3], s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: global_extload_v8f16_to_v8f64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v16, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b128 v[0:3], v16, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v4, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v6, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v3
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v8, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v3, v3
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v4
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v17, v5
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[4:5], v6
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v6, v9
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v2, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v7, v7
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[12:13], v3
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[8:9], v8
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[14:15], v6
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[10:11], v2
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[6:7], v7
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[2:3], v17
+; GFX11-FAKE16-NEXT:    s_clause 0x3
+; GFX11-FAKE16-NEXT:    global_store_b128 v16, v[12:15], s[0:1] offset:48
+; GFX11-FAKE16-NEXT:    global_store_b128 v16, v[8:11], s[0:1] offset:32
+; GFX11-FAKE16-NEXT:    global_store_b128 v16, v[4:7], s[0:1] offset:16
+; GFX11-FAKE16-NEXT:    global_store_b128 v16, v[0:3], s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %val = load <8 x half>, ptr addrspace(1) %in
   %cvt = fpext <8 x half> %val to <8 x double>
   store <8 x double> %cvt, ptr addrspace(1) %out
@@ -2137,66 +2380,127 @@ define amdgpu_kernel void @global_extload_v16f16_to_v16f64(ptr addrspace(1) %out
 ; VI-NEXT:    flat_store_dwordx4 v[13:14], v[5:8]
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_extload_v16f16_to_v16f64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT:    v_mov_b32_e32 v32, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_load_b128 v[0:3], v32, s[2:3]
-; GFX11-NEXT:    global_load_b128 v[4:7], v32, s[2:3] offset:16
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v10, v1
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v23, 16, v5
-; GFX11-NEXT:    v_lshrrev_b32_e32 v11, 16, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v19, 16, v4
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v15, v7
-; GFX11-NEXT:    v_lshrrev_b32_e32 v7, 16, v7
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v14, v6
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v13, v3
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v12, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v18, v4
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v22, v5
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[4:5], v10
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v10, v23
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v34, v11
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v11, v19
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 16, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v7, v7
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v6, v6
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v8, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v3, v3
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v2, v2
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[28:29], v22
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[30:31], v10
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[24:25], v18
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[26:27], v11
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v33, v9
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[20:21], v15
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[22:23], v7
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[16:17], v14
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[18:19], v6
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[0:1], v8
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[8:9], v12
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[12:13], v13
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[14:15], v3
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[10:11], v2
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[6:7], v34
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[2:3], v33
-; GFX11-NEXT:    s_clause 0x7
-; GFX11-NEXT:    global_store_b128 v32, v[28:31], s[0:1] offset:80
-; GFX11-NEXT:    global_store_b128 v32, v[24:27], s[0:1] offset:64
-; GFX11-NEXT:    global_store_b128 v32, v[20:23], s[0:1] offset:112
-; GFX11-NEXT:    global_store_b128 v32, v[16:19], s[0:1] offset:96
-; GFX11-NEXT:    global_store_b128 v32, v[12:15], s[0:1] offset:48
-; GFX11-NEXT:    global_store_b128 v32, v[8:11], s[0:1] offset:32
-; GFX11-NEXT:    global_store_b128 v32, v[4:7], s[0:1] offset:16
-; GFX11-NEXT:    global_store_b128 v32, v[0:3], s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: global_extload_v16f16_to_v16f64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v32, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    global_load_b128 v[0:3], v32, s[2:3]
+; GFX11-TRUE16-NEXT:    global_load_b128 v[4:7], v32, s[2:3] offset:16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v10, v1.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v23, 16, v5
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v19, 16, v4
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v15, v7.l
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v14, v6.l
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v13, v3.l
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v12, v2.l
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v18, v4.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v22, v5.l
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[4:5], v10
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v10, v23.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v34, v11.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v11, v19.l
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v0
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v7, v7.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v6, v6.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v8, v0.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v3, v3.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v2, v2.l
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[28:29], v22
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[30:31], v10
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[24:25], v18
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[26:27], v11
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v33, v9.l
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[20:21], v15
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[22:23], v7
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[16:17], v14
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[18:19], v6
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v8
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[8:9], v12
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[12:13], v13
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[14:15], v3
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[10:11], v2
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[6:7], v34
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[2:3], v33
+; GFX11-TRUE16-NEXT:    s_clause 0x7
+; GFX11-TRUE16-NEXT:    global_store_b128 v32, v[28:31], s[0:1] offset:80
+; GFX11-TRUE16-NEXT:    global_store_b128 v32, v[24:27], s[0:1] offset:64
+; GFX11-TRUE16-NEXT:    global_store_b128 v32, v[20:23], s[0:1] offset:112
+; GFX11-TRUE16-NEXT:    global_store_b128 v32, v[16:19], s[0:1] offset:96
+; GFX11-TRUE16-NEXT:    global_store_b128 v32, v[12:15], s[0:1] offset:48
+; GFX11-TRUE16-NEXT:    global_store_b128 v32, v[8:11], s[0:1] offset:32
+; GFX11-TRUE16-NEXT:    global_store_b128 v32, v[4:7], s[0:1] offset:16
+; GFX11-TRUE16-NEXT:    global_store_b128 v32, v[0:3], s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: global_extload_v16f16_to_v16f64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v32, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    global_load_b128 v[0:3], v32, s[2:3]
+; GFX11-FAKE16-NEXT:    global_load_b128 v[4:7], v32, s[2:3] offset:16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v10, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v23, 16, v5
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v11, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v19, 16, v4
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v15, v7
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v14, v6
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v13, v3
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v12, v2
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v18, v4
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v22, v5
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[4:5], v10
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v10, v23
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v34, v11
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v11, v19
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v7, v7
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v6, v6
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v8, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v3, v3
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v2, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[28:29], v22
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[30:31], v10
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[24:25], v18
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[26:27], v11
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v33, v9
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[20:21], v15
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[22:23], v7
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[16:17], v14
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[18:19], v6
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v8
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[8:9], v12
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[12:13], v13
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[14:15], v3
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[10:11], v2
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[6:7], v34
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[2:3], v33
+; GFX11-FAKE16-NEXT:    s_clause 0x7
+; GFX11-FAKE16-NEXT:    global_store_b128 v32, v[28:31], s[0:1] offset:80
+; GFX11-FAKE16-NEXT:    global_store_b128 v32, v[24:27], s[0:1] offset:64
+; GFX11-FAKE16-NEXT:    global_store_b128 v32, v[20:23], s[0:1] offset:112
+; GFX11-FAKE16-NEXT:    global_store_b128 v32, v[16:19], s[0:1] offset:96
+; GFX11-FAKE16-NEXT:    global_store_b128 v32, v[12:15], s[0:1] offset:48
+; GFX11-FAKE16-NEXT:    global_store_b128 v32, v[8:11], s[0:1] offset:32
+; GFX11-FAKE16-NEXT:    global_store_b128 v32, v[4:7], s[0:1] offset:16
+; GFX11-FAKE16-NEXT:    global_store_b128 v32, v[0:3], s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %val = load <16 x half>, ptr addrspace(1) %in
   %cvt = fpext <16 x half> %val to <16 x double>
   store <16 x double> %cvt, ptr addrspace(1) %out
@@ -2221,16 +2525,27 @@ define amdgpu_kernel void @global_truncstore_f32_to_f16(ptr addrspace(1) %out, p
 ; CIVI-NEXT:    flat_store_short v[0:1], v2
 ; CIVI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_truncstore_f32_to_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v1, v0, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX11-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: global_truncstore_f32_to_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v1, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: global_truncstore_f32_to_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v0, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %val = load float, ptr addrspace(1) %in
   %cvt = fptrunc float %val to half
   store half %cvt, ptr addrspace(1) %out
@@ -2277,19 +2592,33 @@ define amdgpu_kernel void @global_truncstore_v2f32_to_v2f16(ptr addrspace(1) %ou
 ; VI-NEXT:    flat_store_dword v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_truncstore_v2f32_to_v2f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT:    v_mov_b32_e32 v2, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[0:1], v2, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT:    global_store_b32 v2, v0, s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: global_truncstore_v2f32_to_v2f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v3, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b64 v[1:2], v3, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v2
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v0.l
+; GFX11-TRUE16-NEXT:    global_store_b32 v3, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: global_truncstore_v2f32_to_v2f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[0:1], v2, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-FAKE16-NEXT:    global_store_b32 v2, v0, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %val = load <2 x float>, ptr addrspace(1) %in
   %cvt = fptrunc <2 x float> %val to <2 x half>
   store <2 x half> %cvt, ptr addrspace(1) %out
@@ -2348,22 +2677,39 @@ define amdgpu_kernel void @global_truncstore_v3f32_to_v3f16(ptr addrspace(1) %ou
 ; VI-NEXT:    flat_store_dword v[0:1], v3
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_truncstore_v3f32_to_v3f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT:    v_mov_b32_e32 v3, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_b96 v[0:2], v3, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_store_b16 v3, v2, s[0:1] offset:4
-; GFX11-NEXT:    global_store_b32 v3, v0, s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: global_truncstore_v3f32_to_v3f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v3, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b96 v[0:2], v3, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v1.l, v1
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v1, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    global_store_d16_hi_b16 v3, v0, s[0:1] offset:4
+; GFX11-TRUE16-NEXT:    global_store_b32 v3, v1, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: global_truncstore_v3f32_to_v3f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v3, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b96 v[0:2], v3, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    global_store_b16 v3, v2, s[0:1] offset:4
+; GFX11-FAKE16-NEXT:    global_store_b32 v3, v0, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %val = load <3 x float>, ptr addrspace(1) %in
   %cvt = fptrunc <3 x float> %val to <3 x half>
   store <3 x half> %cvt, ptr addrspace(1) %out
@@ -2417,22 +2763,39 @@ define amdgpu_kernel void @global_truncstore_v4f32_to_v4f16(ptr addrspace(1) %ou
 ; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_truncstore_v4f32_to_v4f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT:    v_mov_b32_e32 v4, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_b128 v[0:3], v4, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v3, v3
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v5, v1
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_pack_b32_f16 v1, v2, v3
-; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v5
-; GFX11-NEXT:    global_store_b64 v4, v[0:1], s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: global_truncstore_v4f32_to_v4f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v4, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b128 v[0:3], v4, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v3.l, v3
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v2.l, v2
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v1.l, v1
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v2, v2.l, v3.l
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v1, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    global_store_b64 v4, v[1:2], s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: global_truncstore_v4f32_to_v4f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b128 v[0:3], v4, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v5, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v1, v2, v3
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v5
+; GFX11-FAKE16-NEXT:    global_store_b64 v4, v[0:1], s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %val = load <4 x float>, ptr addrspace(1) %in
   %cvt = fptrunc <4 x float> %val to <4 x half>
   store <4 x half> %cvt, ptr addrspace(1) %out
@@ -2512,31 +2875,57 @@ define amdgpu_kernel void @global_truncstore_v8f32_to_v8f16(ptr addrspace(1) %ou
 ; VI-NEXT:    flat_store_dwordx4 v[8:9], v[0:3]
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_truncstore_v8f32_to_v8f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT:    v_mov_b32_e32 v8, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_load_b128 v[0:3], v8, s[2:3] offset:16
-; GFX11-NEXT:    global_load_b128 v[4:7], v8, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v3, v3
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v7, v7
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v6, v6
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v5, v5
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v4, v4
-; GFX11-NEXT:    v_pack_b32_f16 v3, v2, v3
-; GFX11-NEXT:    v_pack_b32_f16 v2, v0, v1
-; GFX11-NEXT:    v_pack_b32_f16 v1, v6, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_pack_b32_f16 v0, v4, v5
-; GFX11-NEXT:    global_store_b128 v8, v[0:3], s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: global_truncstore_v8f32_to_v8f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v8, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    global_load_b128 v[0:3], v8, s[2:3] offset:16
+; GFX11-TRUE16-NEXT:    global_load_b128 v[4:7], v8, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v3.l, v3
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v2.l, v2
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v1.l, v1
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v7
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v1.h, v6
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v5.l, v5
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v4.l, v4
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v3, v2.l, v3.l
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v2, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.h, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v4.l, v5.l
+; GFX11-TRUE16-NEXT:    global_store_b128 v8, v[0:3], s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: global_truncstore_v8f32_to_v8f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    global_load_b128 v[0:3], v8, s[2:3] offset:16
+; GFX11-FAKE16-NEXT:    global_load_b128 v[4:7], v8, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v7, v7
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v6, v6
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v5, v5
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v4, v4
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v3, v2, v3
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v2, v0, v1
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v1, v6, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v4, v5
+; GFX11-FAKE16-NEXT:    global_store_b128 v8, v[0:3], s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %val = load <8 x float>, ptr addrspace(1) %in
   %cvt = fptrunc <8 x float> %val to <8 x half>
   store <8 x half> %cvt, ptr addrspace(1) %out
@@ -2678,48 +3067,91 @@ define amdgpu_kernel void @global_truncstore_v16f32_to_v16f16(ptr addrspace(1) %
 ; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_truncstore_v16f32_to_v16f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT:    v_mov_b32_e32 v16, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x3
-; GFX11-NEXT:    global_load_b128 v[0:3], v16, s[2:3] offset:16
-; GFX11-NEXT:    global_load_b128 v[4:7], v16, s[2:3]
-; GFX11-NEXT:    global_load_b128 v[8:11], v16, s[2:3] offset:48
-; GFX11-NEXT:    global_load_b128 v[12:15], v16, s[2:3] offset:32
-; GFX11-NEXT:    s_waitcnt vmcnt(3)
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v3, v3
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    s_waitcnt vmcnt(2)
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v7, v7
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v6, v6
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v17, v5
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v18, v4
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v4, v11
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v5, v10
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v9, v9
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v8, v8
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v10, v15
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v11, v14
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v13, v13
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v12, v12
-; GFX11-NEXT:    v_pack_b32_f16 v3, v2, v3
-; GFX11-NEXT:    v_pack_b32_f16 v2, v0, v1
-; GFX11-NEXT:    v_pack_b32_f16 v1, v6, v7
-; GFX11-NEXT:    v_pack_b32_f16 v7, v5, v4
-; GFX11-NEXT:    v_pack_b32_f16 v6, v8, v9
-; GFX11-NEXT:    v_pack_b32_f16 v5, v11, v10
-; GFX11-NEXT:    v_pack_b32_f16 v4, v12, v13
-; GFX11-NEXT:    v_pack_b32_f16 v0, v18, v17
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_store_b128 v16, v[4:7], s[0:1] offset:16
-; GFX11-NEXT:    global_store_b128 v16, v[0:3], s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: global_truncstore_v16f32_to_v16f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v17, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x3
+; GFX11-TRUE16-NEXT:    global_load_b128 v[0:3], v17, s[2:3] offset:16
+; GFX11-TRUE16-NEXT:    global_load_b128 v[4:7], v17, s[2:3]
+; GFX11-TRUE16-NEXT:    global_load_b128 v[8:11], v17, s[2:3] offset:48
+; GFX11-TRUE16-NEXT:    global_load_b128 v[12:15], v17, s[2:3] offset:32
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(3)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v3.l, v3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v16.l, v5
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v16.h, v4
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v4.l, v11
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v4.h, v10
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v5.l, v9
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v5.h, v8
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v8.l, v15
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v8.h, v14
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v9.l, v13
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v9.h, v12
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v2.l, v2
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v1.l, v1
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v7
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v1.h, v6
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v7, v4.h, v4.l
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v6, v5.h, v5.l
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v5, v8.h, v8.l
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v4, v9.h, v9.l
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v3, v2.l, v3.l
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v2, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.h, v0.h
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v16.h, v16.l
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    global_store_b128 v17, v[4:7], s[0:1] offset:16
+; GFX11-TRUE16-NEXT:    global_store_b128 v17, v[0:3], s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: global_truncstore_v16f32_to_v16f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v16, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x3
+; GFX11-FAKE16-NEXT:    global_load_b128 v[0:3], v16, s[2:3] offset:16
+; GFX11-FAKE16-NEXT:    global_load_b128 v[4:7], v16, s[2:3]
+; GFX11-FAKE16-NEXT:    global_load_b128 v[8:11], v16, s[2:3] offset:48
+; GFX11-FAKE16-NEXT:    global_load_b128 v[12:15], v16, s[2:3] offset:32
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(3)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v7, v7
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v6, v6
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v17, v5
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v18, v4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v4, v11
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v5, v10
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v9, v9
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v8, v8
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v10, v15
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v11, v14
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v13, v13
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v12, v12
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v3, v2, v3
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v2, v0, v1
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v1, v6, v7
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v7, v5, v4
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v6, v8, v9
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v5, v11, v10
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v4, v12, v13
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v18, v17
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    global_store_b128 v16, v[4:7], s[0:1] offset:16
+; GFX11-FAKE16-NEXT:    global_store_b128 v16, v[0:3], s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %val = load <16 x float>, ptr addrspace(1) %in
   %cvt = fptrunc <16 x float> %val to <16 x half>
   store <16 x half> %cvt, ptr addrspace(1) %out
@@ -2763,18 +3195,31 @@ define amdgpu_kernel void @fadd_f16(ptr addrspace(1) %out, half %a, half %b) #0
 ; VI-NEXT:    flat_store_short v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: fadd_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    s_load_b32 s2, s[4:5], 0x8
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_lshr_b32 s3, s2, 16
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    v_add_f16_e64 v1, s2, s3
-; GFX11-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: fadd_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    s_load_b32 s2, s[4:5], 0x8
+; GFX11-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_lshr_b32 s3, s2, 16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    v_add_f16_e64 v0.l, s2, s3
+; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: fadd_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    s_load_b32 s2, s[4:5], 0x8
+; GFX11-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_lshr_b32 s3, s2, 16
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    v_add_f16_e64 v1, s2, s3
+; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
    %add = fadd half %a, %b
    store half %add, ptr addrspace(1) %out, align 4
    ret void
@@ -3062,15 +3507,25 @@ define amdgpu_kernel void @test_bitcast_from_half(ptr addrspace(1) %in, ptr addr
 ; CIVI-NEXT:    flat_store_short v[0:1], v2
 ; CIVI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: test_bitcast_from_half:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u16 v1, v0, s[0:1]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b16 v0, v1, s[2:3]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: test_bitcast_from_half:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[0:1]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[2:3]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: test_bitcast_from_half:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[0:1]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[2:3]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %val = load half, ptr addrspace(1) %in
   %val_int = bitcast half %val to i16
   store i16 %val_int, ptr addrspace(1) %out
@@ -3094,15 +3549,25 @@ define amdgpu_kernel void @test_bitcast_to_half(ptr addrspace(1) %out, ptr addrs
 ; CIVI-NEXT:    flat_store_short v[0:1], v2
 ; CIVI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: test_bitcast_to_half:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u16 v1, v0, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: test_bitcast_to_half:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: test_bitcast_to_half:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %val = load i16, ptr addrspace(1) %in
   %val_fp = bitcast i16 %val to half
   store half %val_fp, ptr addrspace(1) %out
diff --git a/llvm/test/CodeGen/AMDGPU/idot4s.ll b/llvm/test/CodeGen/AMDGPU/idot4s.ll
index 6c472123ee766..d28f0a190e117 100644
--- a/llvm/test/CodeGen/AMDGPU/idot4s.ll
+++ b/llvm/test/CodeGen/AMDGPU/idot4s.ll
@@ -5,7 +5,8 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefixes=GFX9-DL %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1011 < %s | FileCheck -check-prefixes=GFX10-DL %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1012 < %s | FileCheck -check-prefixes=GFX10-DL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11-DL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-DL,GFX11-DL-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-DL,GFX11-DL-FAKE16 %s
 
 define amdgpu_kernel void @idot4_acc32(ptr addrspace(1) %src1,
 ; GFX7-LABEL: idot4_acc32:
@@ -1155,52 +1156,96 @@ define amdgpu_kernel void @idot4_acc16_vecMul(ptr addrspace(1) %src1,
 ; GFX10-DL-NEXT:    global_store_short v0, v1, s[6:7]
 ; GFX10-DL-NEXT:    s_endpgm
 ;
-; GFX11-DL-LABEL: idot4_acc16_vecMul:
-; GFX11-DL:       ; %bb.0: ; %entry
-; GFX11-DL-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-DL-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-DL-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-DL-NEXT:    v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-DL-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT:    s_clause 0x1
-; GFX11-DL-NEXT:    global_load_b32 v1, v0, s[0:1]
-; GFX11-DL-NEXT:    global_load_b32 v0, v0, s[2:3]
-; GFX11-DL-NEXT:    global_load_u16 v3, v2, s[4:5]
-; GFX11-DL-NEXT:    s_waitcnt vmcnt(2)
-; GFX11-DL-NEXT:    v_ashrrev_i16 v4, 8, v1
-; GFX11-DL-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT:    v_ashrrev_i16 v5, 8, v0
-; GFX11-DL-NEXT:    v_bfe_i32 v6, v0, 0, 8
-; GFX11-DL-NEXT:    v_bfe_i32 v7, v1, 0, 8
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-DL-NEXT:    v_perm_b32 v5, v5, v6, 0x5040100
-; GFX11-DL-NEXT:    v_perm_b32 v4, v4, v7, 0x5040100
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-DL-NEXT:    v_ashrrev_i16 v6, 8, v1
-; GFX11-DL-NEXT:    v_ashrrev_i16 v7, 8, v0
-; GFX11-DL-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX11-DL-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX11-DL-NEXT:    v_pk_mul_lo_u16 v4, v4, v5
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-DL-NEXT:    v_perm_b32 v0, v7, v0, 0x5040100
-; GFX11-DL-NEXT:    v_perm_b32 v1, v6, v1, 0x5040100
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v5, 16, v4
-; GFX11-DL-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT:    v_add_nc_u16 v3, v4, v3
-; GFX11-DL-NEXT:    v_pk_mul_lo_u16 v0, v1, v0
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-DL-NEXT:    v_add_nc_u16 v1, v3, v5
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-DL-NEXT:    v_add_nc_u16 v0, v1, v0
-; GFX11-DL-NEXT:    v_add_nc_u16 v0, v0, v3
-; GFX11-DL-NEXT:    global_store_b16 v2, v0, s[4:5]
-; GFX11-DL-NEXT:    s_endpgm
+; GFX11-DL-TRUE16-LABEL: idot4_acc16_vecMul:
+; GFX11-DL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-DL-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-DL-TRUE16-NEXT:    v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX11-DL-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-DL-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-DL-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-DL-TRUE16-NEXT:    s_clause 0x1
+; GFX11-DL-TRUE16-NEXT:    global_load_b32 v1, v0, s[2:3]
+; GFX11-DL-TRUE16-NEXT:    global_load_b32 v2, v0, s[0:1]
+; GFX11-DL-TRUE16-NEXT:    global_load_d16_b16 v0, v3, s[4:5]
+; GFX11-DL-TRUE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v1.l
+; GFX11-DL-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v2.l
+; GFX11-DL-TRUE16-NEXT:    v_ashrrev_i16 v6.h, 8, v2.l
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v2.h
+; GFX11-DL-TRUE16-NEXT:    v_ashrrev_i16 v8.h, 8, v1.l
+; GFX11-DL-TRUE16-NEXT:    v_bfe_i32 v4, v4, 0, 8
+; GFX11-DL-TRUE16-NEXT:    v_bfe_i32 v5, v5, 0, 8
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v1.h
+; GFX11-DL-TRUE16-NEXT:    v_ashrrev_i16 v2.h, 8, v2.h
+; GFX11-DL-TRUE16-NEXT:    v_ashrrev_i16 v1.h, 8, v1.h
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v4.l
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v5.l
+; GFX11-DL-TRUE16-NEXT:    v_bfe_i32 v4, v9, 0, 8
+; GFX11-DL-TRUE16-NEXT:    v_bfe_i32 v5, v7, 0, 8
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-DL-TRUE16-NEXT:    v_pk_mul_lo_u16 v6, v6, v8
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v4.l
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v5.l
+; GFX11-DL-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-DL-TRUE16-NEXT:    v_add_nc_u16 v0.l, v6.l, v0.l
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-DL-TRUE16-NEXT:    v_pk_mul_lo_u16 v1, v2, v1
+; GFX11-DL-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v6.h
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-DL-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX11-DL-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v1.h
+; GFX11-DL-TRUE16-NEXT:    global_store_b16 v3, v0, s[4:5]
+; GFX11-DL-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-DL-FAKE16-LABEL: idot4_acc16_vecMul:
+; GFX11-DL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-DL-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-DL-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-DL-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-DL-FAKE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-DL-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-DL-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-DL-FAKE16-NEXT:    s_clause 0x1
+; GFX11-DL-FAKE16-NEXT:    global_load_b32 v1, v0, s[0:1]
+; GFX11-DL-FAKE16-NEXT:    global_load_b32 v0, v0, s[2:3]
+; GFX11-DL-FAKE16-NEXT:    global_load_u16 v3, v2, s[4:5]
+; GFX11-DL-FAKE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-DL-FAKE16-NEXT:    v_ashrrev_i16 v4, 8, v1
+; GFX11-DL-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-DL-FAKE16-NEXT:    v_ashrrev_i16 v5, 8, v0
+; GFX11-DL-FAKE16-NEXT:    v_bfe_i32 v6, v0, 0, 8
+; GFX11-DL-FAKE16-NEXT:    v_bfe_i32 v7, v1, 0, 8
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-DL-FAKE16-NEXT:    v_perm_b32 v5, v5, v6, 0x5040100
+; GFX11-DL-FAKE16-NEXT:    v_perm_b32 v4, v4, v7, 0x5040100
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-DL-FAKE16-NEXT:    v_ashrrev_i16 v6, 8, v1
+; GFX11-DL-FAKE16-NEXT:    v_ashrrev_i16 v7, 8, v0
+; GFX11-DL-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX11-DL-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX11-DL-FAKE16-NEXT:    v_pk_mul_lo_u16 v4, v4, v5
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-DL-FAKE16-NEXT:    v_perm_b32 v0, v7, v0, 0x5040100
+; GFX11-DL-FAKE16-NEXT:    v_perm_b32 v1, v6, v1, 0x5040100
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v4
+; GFX11-DL-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-DL-FAKE16-NEXT:    v_add_nc_u16 v3, v4, v3
+; GFX11-DL-FAKE16-NEXT:    v_pk_mul_lo_u16 v0, v1, v0
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-DL-FAKE16-NEXT:    v_add_nc_u16 v1, v3, v5
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-DL-FAKE16-NEXT:    v_add_nc_u16 v0, v1, v0
+; GFX11-DL-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v3
+; GFX11-DL-FAKE16-NEXT:    global_store_b16 v2, v0, s[4:5]
+; GFX11-DL-FAKE16-NEXT:    s_endpgm
                                               ptr addrspace(1) %src2,
                                               ptr addrspace(1) nocapture %dst) {
 entry:
@@ -3378,42 +3423,87 @@ define amdgpu_kernel void @idot4_nonstandard_signed(ptr addrspace(1) %src1,
 ; GFX10-DL-NEXT:    global_store_dword v1, v0, s[6:7]
 ; GFX10-DL-NEXT:    s_endpgm
 ;
-; GFX11-DL-LABEL: idot4_nonstandard_signed:
-; GFX11-DL:       ; %bb.0: ; %entry
-; GFX11-DL-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-DL-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-DL-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-DL-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT:    s_clause 0x1
-; GFX11-DL-NEXT:    global_load_b32 v1, v0, s[0:1]
-; GFX11-DL-NEXT:    global_load_b32 v0, v0, s[2:3]
-; GFX11-DL-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT:    v_bfe_i32 v2, v1, 0, 8
-; GFX11-DL-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT:    v_and_b32_e32 v3, 0xff, v0
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v5, 8, v0
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v7, 16, v0
-; GFX11-DL-NEXT:    v_mul_lo_u16 v2, v2, v3
-; GFX11-DL-NEXT:    v_bfe_i32 v3, v4, 0, 8
-; GFX11-DL-NEXT:    v_and_b32_e32 v4, 0xff, v5
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v1, 24, v1
-; GFX11-DL-NEXT:    v_bfe_i32 v5, v6, 0, 8
-; GFX11-DL-NEXT:    v_and_b32_e32 v6, 0xff, v7
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v0, 24, v0
-; GFX11-DL-NEXT:    v_mad_u16 v2, v4, v3, v2
-; GFX11-DL-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-DL-NEXT:    v_mad_u16 v2, v6, v5, v2
-; GFX11-DL-NEXT:    v_mad_u16 v0, v1, v0, v2
-; GFX11-DL-NEXT:    v_mov_b32_e32 v1, 0
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-DL-NEXT:    v_bfe_i32 v0, v0, 0, 16
-; GFX11-DL-NEXT:    global_store_b32 v1, v0, s[4:5]
-; GFX11-DL-NEXT:    s_endpgm
+; GFX11-DL-TRUE16-LABEL: idot4_nonstandard_signed:
+; GFX11-DL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-DL-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-DL-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-DL-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-DL-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-DL-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-DL-TRUE16-NEXT:    s_clause 0x1
+; GFX11-DL-TRUE16-NEXT:    global_load_b32 v2, v0, s[0:1]
+; GFX11-DL-TRUE16-NEXT:    global_load_b32 v3, v0, s[2:3]
+; GFX11-DL-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v2.l
+; GFX11-DL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-DL-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-DL-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 8, v3
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v2.h
+; GFX11-DL-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 24, v2
+; GFX11-DL-TRUE16-NEXT:    v_bfe_i32 v4, v0, 0, 8
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v1.l
+; GFX11-DL-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v3.l
+; GFX11-DL-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v6.l
+; GFX11-DL-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v3.h
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v4.l
+; GFX11-DL-TRUE16-NEXT:    v_bfe_i32 v4, v5, 0, 8
+; GFX11-DL-TRUE16-NEXT:    v_bfe_i32 v5, v7, 0, 8
+; GFX11-DL-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v3
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-DL-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v1.l, v0.l
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v4.l
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v2.l
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v5.l
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-DL-TRUE16-NEXT:    v_mad_u16 v0.l, v0.h, v1.l, v0.l
+; GFX11-DL-TRUE16-NEXT:    v_bfe_i32 v4, v4, 0, 8
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-DL-TRUE16-NEXT:    v_mad_u16 v0.l, v1.h, v2.l, v0.l
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v4.l
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-DL-TRUE16-NEXT:    v_mad_u16 v0.l, v1.l, v3.l, v0.l
+; GFX11-DL-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-DL-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX11-DL-TRUE16-NEXT:    global_store_b32 v1, v0, s[4:5]
+; GFX11-DL-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-DL-FAKE16-LABEL: idot4_nonstandard_signed:
+; GFX11-DL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-DL-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-DL-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-DL-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-DL-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-DL-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-DL-FAKE16-NEXT:    s_clause 0x1
+; GFX11-DL-FAKE16-NEXT:    global_load_b32 v1, v0, s[0:1]
+; GFX11-DL-FAKE16-NEXT:    global_load_b32 v0, v0, s[2:3]
+; GFX11-DL-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-DL-FAKE16-NEXT:    v_bfe_i32 v2, v1, 0, 8
+; GFX11-DL-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-DL-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v0
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v0
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v0
+; GFX11-DL-FAKE16-NEXT:    v_mul_lo_u16 v2, v2, v3
+; GFX11-DL-FAKE16-NEXT:    v_bfe_i32 v3, v4, 0, 8
+; GFX11-DL-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v5
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 24, v1
+; GFX11-DL-FAKE16-NEXT:    v_bfe_i32 v5, v6, 0, 8
+; GFX11-DL-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v7
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 24, v0
+; GFX11-DL-FAKE16-NEXT:    v_mad_u16 v2, v4, v3, v2
+; GFX11-DL-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-DL-FAKE16-NEXT:    v_mad_u16 v2, v6, v5, v2
+; GFX11-DL-FAKE16-NEXT:    v_mad_u16 v0, v1, v0, v2
+; GFX11-DL-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-DL-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX11-DL-FAKE16-NEXT:    global_store_b32 v1, v0, s[4:5]
+; GFX11-DL-FAKE16-NEXT:    s_endpgm
                                        ptr addrspace(1) %src2,
                                        ptr addrspace(1) nocapture %dst) {
 entry:
diff --git a/llvm/test/CodeGen/AMDGPU/idot4u.ll b/llvm/test/CodeGen/AMDGPU/idot4u.ll
index 75e72a72bebb1..82d62910bcb00 100644
--- a/llvm/test/CodeGen/AMDGPU/idot4u.ll
+++ b/llvm/test/CodeGen/AMDGPU/idot4u.ll
@@ -5,7 +5,8 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefixes=GFX9-DL %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1011 < %s | FileCheck -check-prefixes=GFX10-DL %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1012 < %s | FileCheck -check-prefixes=GFX10-DL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11-DL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-DL,GFX11-DL-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-DL,GFX11-DL-FAKE16 %s
 
 define amdgpu_kernel void @udot4_acc32(ptr addrspace(1) %src1,
 ; GFX7-LABEL: udot4_acc32:
@@ -1665,38 +1666,77 @@ define amdgpu_kernel void @notdot4_mixedtypes(ptr addrspace(1) %src1,
 ; GFX10-DL-NEXT:    global_store_short v0, v1, s[6:7]
 ; GFX10-DL-NEXT:    s_endpgm
 ;
-; GFX11-DL-LABEL: notdot4_mixedtypes:
-; GFX11-DL:       ; %bb.0: ; %entry
-; GFX11-DL-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-DL-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-DL-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-DL-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT:    s_clause 0x1
-; GFX11-DL-NEXT:    global_load_b32 v1, v0, s[0:1]
-; GFX11-DL-NEXT:    global_load_b32 v0, v0, s[2:3]
-; GFX11-DL-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
-; GFX11-DL-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v5, 8, v0
-; GFX11-DL-NEXT:    v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT:    v_bfe_i32 v6, v1, 0, 8
-; GFX11-DL-NEXT:    v_bfe_i32 v7, v0, 0, 8
-; GFX11-DL-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-DL-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-DL-NEXT:    global_load_u16 v3, v2, s[4:5]
-; GFX11-DL-NEXT:    v_perm_b32 v0, v0, v0, 0xc0c0302
-; GFX11-DL-NEXT:    v_perm_b32 v1, v1, v1, 0xc0c0302
-; GFX11-DL-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT:    v_mad_u16 v3, v4, v5, v3
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-DL-NEXT:    v_mad_u16 v3, v6, v7, v3
-; GFX11-DL-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-DL-NEXT:    v_dot4_u32_u8 v0, v1, v0, v3
-; GFX11-DL-NEXT:    global_store_b16 v2, v0, s[4:5]
-; GFX11-DL-NEXT:    s_endpgm
+; GFX11-DL-TRUE16-LABEL: notdot4_mixedtypes:
+; GFX11-DL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-DL-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-DL-TRUE16-NEXT:    v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX11-DL-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-DL-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-DL-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-DL-TRUE16-NEXT:    s_clause 0x1
+; GFX11-DL-TRUE16-NEXT:    global_load_b32 v3, v0, s[0:1]
+; GFX11-DL-TRUE16-NEXT:    global_load_b32 v4, v0, s[2:3]
+; GFX11-DL-TRUE16-NEXT:    global_load_d16_b16 v0, v5, s[4:5]
+; GFX11-DL-TRUE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-DL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-DL-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-DL-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 8, v4
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v3.l
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v4.l
+; GFX11-DL-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v1.l
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-DL-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v2.l
+; GFX11-DL-TRUE16-NEXT:    v_bfe_i32 v2, v6, 0, 8
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-DL-TRUE16-NEXT:    v_bfe_i32 v6, v7, 0, 8
+; GFX11-DL-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-DL-TRUE16-NEXT:    v_mad_u16 v0.l, v0.h, v1.l, v0.l
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.l
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v6.l
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-DL-TRUE16-NEXT:    v_mad_u16 v0.l, v1.l, v2.l, v0.l
+; GFX11-DL-TRUE16-NEXT:    v_perm_b32 v1, v4, v4, 0xc0c0302
+; GFX11-DL-TRUE16-NEXT:    v_perm_b32 v2, v3, v3, 0xc0c0302
+; GFX11-DL-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-DL-TRUE16-NEXT:    v_dot4_u32_u8 v0, v2, v1, v0
+; GFX11-DL-TRUE16-NEXT:    global_store_b16 v5, v0, s[4:5]
+; GFX11-DL-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-DL-FAKE16-LABEL: notdot4_mixedtypes:
+; GFX11-DL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-DL-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-DL-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-DL-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-DL-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-DL-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-DL-FAKE16-NEXT:    s_clause 0x1
+; GFX11-DL-FAKE16-NEXT:    global_load_b32 v1, v0, s[0:1]
+; GFX11-DL-FAKE16-NEXT:    global_load_b32 v0, v0, s[2:3]
+; GFX11-DL-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
+; GFX11-DL-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v0
+; GFX11-DL-FAKE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-DL-FAKE16-NEXT:    v_bfe_i32 v6, v1, 0, 8
+; GFX11-DL-FAKE16-NEXT:    v_bfe_i32 v7, v0, 0, 8
+; GFX11-DL-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-DL-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-DL-FAKE16-NEXT:    global_load_u16 v3, v2, s[4:5]
+; GFX11-DL-FAKE16-NEXT:    v_perm_b32 v0, v0, v0, 0xc0c0302
+; GFX11-DL-FAKE16-NEXT:    v_perm_b32 v1, v1, v1, 0xc0c0302
+; GFX11-DL-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-DL-FAKE16-NEXT:    v_mad_u16 v3, v4, v5, v3
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-DL-FAKE16-NEXT:    v_mad_u16 v3, v6, v7, v3
+; GFX11-DL-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-DL-FAKE16-NEXT:    v_dot4_u32_u8 v0, v1, v0, v3
+; GFX11-DL-FAKE16-NEXT:    global_store_b16 v2, v0, s[4:5]
+; GFX11-DL-FAKE16-NEXT:    s_endpgm
                                               ptr addrspace(1) %src2,
                                               ptr addrspace(1) nocapture %dst) {
 entry:
@@ -1921,43 +1961,86 @@ define amdgpu_kernel void @notdot4_mixedtypes2(ptr addrspace(1) %src1,
 ; GFX10-DL-NEXT:    global_store_short v0, v1, s[6:7]
 ; GFX10-DL-NEXT:    s_endpgm
 ;
-; GFX11-DL-LABEL: notdot4_mixedtypes2:
-; GFX11-DL:       ; %bb.0: ; %entry
-; GFX11-DL-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-DL-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-DL-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-DL-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT:    s_clause 0x1
-; GFX11-DL-NEXT:    global_load_b32 v1, v0, s[0:1]
-; GFX11-DL-NEXT:    global_load_b32 v0, v0, s[2:3]
-; GFX11-DL-NEXT:    v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
-; GFX11-DL-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT:    v_and_b32_e32 v9, 0xff, v0
-; GFX11-DL-NEXT:    global_load_u16 v3, v2, s[4:5]
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v5, 8, v0
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-DL-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v7, 16, v0
-; GFX11-DL-NEXT:    v_bfe_i32 v8, v1, 0, 8
-; GFX11-DL-NEXT:    v_bfe_i32 v5, v5, 0, 8
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v0, 24, v0
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v1, 24, v1
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-DL-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX11-DL-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT:    v_mad_u16 v3, v4, v5, v3
-; GFX11-DL-NEXT:    v_bfe_i32 v4, v6, 0, 8
-; GFX11-DL-NEXT:    v_and_b32_e32 v5, 0xff, v7
-; GFX11-DL-NEXT:    v_mad_u16 v3, v8, v9, v3
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-DL-NEXT:    v_mad_u16 v3, v4, v5, v3
-; GFX11-DL-NEXT:    v_mad_u16 v0, v1, v0, v3
-; GFX11-DL-NEXT:    global_store_b16 v2, v0, s[4:5]
-; GFX11-DL-NEXT:    s_endpgm
+; GFX11-DL-TRUE16-LABEL: notdot4_mixedtypes2:
+; GFX11-DL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-DL-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-DL-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-DL-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-DL-TRUE16-NEXT:    v_mov_b32_e32 v4, 0
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-DL-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-DL-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-DL-TRUE16-NEXT:    s_clause 0x1
+; GFX11-DL-TRUE16-NEXT:    global_load_b32 v2, v0, s[2:3]
+; GFX11-DL-TRUE16-NEXT:    global_load_b32 v3, v0, s[0:1]
+; GFX11-DL-TRUE16-NEXT:    global_load_d16_b16 v0, v4, s[4:5]
+; GFX11-DL-TRUE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-DL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-DL-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v3.l
+; GFX11-DL-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 8, v3
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v3.h
+; GFX11-DL-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v3
+; GFX11-DL-TRUE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX11-DL-TRUE16-NEXT:    v_bfe_i32 v5, v5, 0, 8
+; GFX11-DL-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v6.l
+; GFX11-DL-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 24, v2
+; GFX11-DL-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v2.l
+; GFX11-DL-TRUE16-NEXT:    v_bfe_i32 v7, v7, 0, 8
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v5.l
+; GFX11-DL-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-DL-TRUE16-NEXT:    v_mad_u16 v0.l, v0.h, v1.l, v0.l
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v6.l
+; GFX11-DL-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v2.h
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v7.l
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-DL-TRUE16-NEXT:    v_mad_u16 v0.l, v2.l, v1.h, v0.l
+; GFX11-DL-TRUE16-NEXT:    v_bfe_i32 v2, v5, 0, 8
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-DL-TRUE16-NEXT:    v_mad_u16 v0.l, v1.l, v0.h, v0.l
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.l
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-DL-TRUE16-NEXT:    v_mad_u16 v0.l, v3.l, v1.l, v0.l
+; GFX11-DL-TRUE16-NEXT:    global_store_b16 v4, v0, s[4:5]
+; GFX11-DL-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-DL-FAKE16-LABEL: notdot4_mixedtypes2:
+; GFX11-DL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-DL-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-DL-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-DL-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-DL-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-DL-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-DL-FAKE16-NEXT:    s_clause 0x1
+; GFX11-DL-FAKE16-NEXT:    global_load_b32 v1, v0, s[0:1]
+; GFX11-DL-FAKE16-NEXT:    global_load_b32 v0, v0, s[2:3]
+; GFX11-DL-FAKE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-DL-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
+; GFX11-DL-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-DL-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v0
+; GFX11-DL-FAKE16-NEXT:    global_load_u16 v3, v2, s[4:5]
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v0
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-DL-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v0
+; GFX11-DL-FAKE16-NEXT:    v_bfe_i32 v8, v1, 0, 8
+; GFX11-DL-FAKE16-NEXT:    v_bfe_i32 v5, v5, 0, 8
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 24, v0
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 24, v1
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-DL-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX11-DL-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-DL-FAKE16-NEXT:    v_mad_u16 v3, v4, v5, v3
+; GFX11-DL-FAKE16-NEXT:    v_bfe_i32 v4, v6, 0, 8
+; GFX11-DL-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v7
+; GFX11-DL-FAKE16-NEXT:    v_mad_u16 v3, v8, v9, v3
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-DL-FAKE16-NEXT:    v_mad_u16 v3, v4, v5, v3
+; GFX11-DL-FAKE16-NEXT:    v_mad_u16 v0, v1, v0, v3
+; GFX11-DL-FAKE16-NEXT:    global_store_b16 v2, v0, s[4:5]
+; GFX11-DL-FAKE16-NEXT:    s_endpgm
                                               ptr addrspace(1) %src2,
                                               ptr addrspace(1) nocapture %dst) {
 entry:
@@ -2358,50 +2441,87 @@ define amdgpu_kernel void @udot4_acc16_vecMul(ptr addrspace(1) %src1,
 ; GFX10-DL-NEXT:    global_store_short v0, v1, s[6:7]
 ; GFX10-DL-NEXT:    s_endpgm
 ;
-; GFX11-DL-LABEL: udot4_acc16_vecMul:
-; GFX11-DL:       ; %bb.0: ; %entry
-; GFX11-DL-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-DL-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-DL-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-DL-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT:    s_clause 0x1
-; GFX11-DL-NEXT:    global_load_b32 v1, v0, s[0:1]
-; GFX11-DL-NEXT:    global_load_b32 v0, v0, s[2:3]
-; GFX11-DL-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v7, 0xff, v1
-; GFX11-DL-NEXT:    global_load_u16 v3, v2, s[4:5]
-; GFX11-DL-NEXT:    v_lshrrev_b16 v4, 8, v1
-; GFX11-DL-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT:    v_lshrrev_b16 v5, 8, v0
-; GFX11-DL-NEXT:    v_and_b32_e32 v6, 0xff, v0
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v8, 16, v1
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v9, 16, v0
-; GFX11-DL-NEXT:    v_perm_b32 v4, v4, v7, 0x5040100
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v1, 24, v1
-; GFX11-DL-NEXT:    v_perm_b32 v5, v5, v6, 0x5040100
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v0, 24, v0
-; GFX11-DL-NEXT:    v_and_b32_e32 v6, 0xff, v9
-; GFX11-DL-NEXT:    v_and_b32_e32 v7, 0xff, v8
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-DL-NEXT:    v_pk_mul_lo_u16 v4, v4, v5
-; GFX11-DL-NEXT:    v_perm_b32 v0, v0, v6, 0x5040100
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-DL-NEXT:    v_perm_b32 v1, v1, v7, 0x5040100
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v5, 16, v4
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-DL-NEXT:    v_pk_mul_lo_u16 v0, v1, v0
-; GFX11-DL-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT:    v_add_nc_u16 v3, v4, v3
-; GFX11-DL-NEXT:    v_add_nc_u16 v1, v3, v5
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-DL-NEXT:    v_add_nc_u16 v0, v1, v0
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-DL-NEXT:    v_add_nc_u16 v0, v0, v3
-; GFX11-DL-NEXT:    global_store_b16 v2, v0, s[4:5]
-; GFX11-DL-NEXT:    s_endpgm
+; GFX11-DL-TRUE16-LABEL: udot4_acc16_vecMul:
+; GFX11-DL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-DL-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-DL-TRUE16-NEXT:    v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX11-DL-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-DL-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-DL-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-DL-TRUE16-NEXT:    s_clause 0x1
+; GFX11-DL-TRUE16-NEXT:    global_load_b32 v1, v0, s[0:1]
+; GFX11-DL-TRUE16-NEXT:    global_load_b32 v2, v0, s[2:3]
+; GFX11-DL-TRUE16-NEXT:    global_load_d16_b16 v0, v3, s[4:5]
+; GFX11-DL-TRUE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-DL-TRUE16-NEXT:    v_lshrrev_b16 v4.h, 8, v1.l
+; GFX11-DL-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-DL-TRUE16-NEXT:    v_lshrrev_b16 v5.h, 8, v2.l
+; GFX11-DL-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v1.l
+; GFX11-DL-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v2.l
+; GFX11-DL-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 24, v2
+; GFX11-DL-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
+; GFX11-DL-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.h
+; GFX11-DL-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.h
+; GFX11-DL-TRUE16-NEXT:    v_pk_mul_lo_u16 v4, v4, v5
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v6.l
+; GFX11-DL-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v7.l
+; GFX11-DL-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-DL-TRUE16-NEXT:    v_add_nc_u16 v0.l, v4.l, v0.l
+; GFX11-DL-TRUE16-NEXT:    v_pk_mul_lo_u16 v1, v1, v2
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-DL-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v4.h
+; GFX11-DL-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-DL-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v1.h
+; GFX11-DL-TRUE16-NEXT:    global_store_b16 v3, v0, s[4:5]
+; GFX11-DL-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-DL-FAKE16-LABEL: udot4_acc16_vecMul:
+; GFX11-DL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-DL-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-DL-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-DL-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-DL-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-DL-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-DL-FAKE16-NEXT:    s_clause 0x1
+; GFX11-DL-FAKE16-NEXT:    global_load_b32 v1, v0, s[0:1]
+; GFX11-DL-FAKE16-NEXT:    global_load_b32 v0, v0, s[2:3]
+; GFX11-DL-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-DL-FAKE16-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v7, 0xff, v1
+; GFX11-DL-FAKE16-NEXT:    global_load_u16 v3, v2, s[4:5]
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b16 v4, 8, v1
+; GFX11-DL-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b16 v5, 8, v0
+; GFX11-DL-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v0
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v1
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v0
+; GFX11-DL-FAKE16-NEXT:    v_perm_b32 v4, v4, v7, 0x5040100
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 24, v1
+; GFX11-DL-FAKE16-NEXT:    v_perm_b32 v5, v5, v6, 0x5040100
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 24, v0
+; GFX11-DL-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v9
+; GFX11-DL-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v8
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-DL-FAKE16-NEXT:    v_pk_mul_lo_u16 v4, v4, v5
+; GFX11-DL-FAKE16-NEXT:    v_perm_b32 v0, v0, v6, 0x5040100
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-DL-FAKE16-NEXT:    v_perm_b32 v1, v1, v7, 0x5040100
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v4
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-DL-FAKE16-NEXT:    v_pk_mul_lo_u16 v0, v1, v0
+; GFX11-DL-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-DL-FAKE16-NEXT:    v_add_nc_u16 v3, v4, v3
+; GFX11-DL-FAKE16-NEXT:    v_add_nc_u16 v1, v3, v5
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-DL-FAKE16-NEXT:    v_add_nc_u16 v0, v1, v0
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-DL-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v3
+; GFX11-DL-FAKE16-NEXT:    global_store_b16 v2, v0, s[4:5]
+; GFX11-DL-FAKE16-NEXT:    s_endpgm
                                               ptr addrspace(1) %src2,
                                               ptr addrspace(1) nocapture %dst) {
 entry:
@@ -2596,52 +2716,95 @@ define amdgpu_kernel void @udot4_acc8_vecMul(ptr addrspace(1) %src1,
 ; GFX10-DL-NEXT:    global_store_byte v0, v1, s[6:7]
 ; GFX10-DL-NEXT:    s_endpgm
 ;
-; GFX11-DL-LABEL: udot4_acc8_vecMul:
-; GFX11-DL:       ; %bb.0: ; %entry
-; GFX11-DL-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-DL-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-DL-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-DL-NEXT:    v_mov_b32_e32 v2, 0
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-DL-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-DL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-DL-NEXT:    s_clause 0x1
-; GFX11-DL-NEXT:    global_load_b32 v1, v0, s[0:1]
-; GFX11-DL-NEXT:    global_load_b32 v0, v0, s[2:3]
-; GFX11-DL-NEXT:    global_load_u8 v3, v2, s[4:5]
-; GFX11-DL-NEXT:    s_waitcnt vmcnt(2)
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v5, 24, v1
-; GFX11-DL-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v6, 24, v0
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v7, 16, v0
-; GFX11-DL-NEXT:    v_lshrrev_b16 v8, 8, v1
-; GFX11-DL-NEXT:    v_lshrrev_b16 v9, 8, v0
-; GFX11-DL-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-DL-NEXT:    v_mad_u16 v0, v1, v0, v3
-; GFX11-DL-NEXT:    v_mul_lo_u16 v5, v5, v6
-; GFX11-DL-NEXT:    v_mul_lo_u16 v6, v4, v7
-; GFX11-DL-NEXT:    v_mul_lo_u16 v8, v8, v9
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-DL-NEXT:    v_lshlrev_b16 v5, 8, v5
-; GFX11-DL-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-DL-NEXT:    v_lshlrev_b16 v8, 8, v8
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v1, 8, v5
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-DL-NEXT:    v_or_b32_e32 v6, v6, v5
-; GFX11-DL-NEXT:    v_and_b32_e32 v8, 0xffff, v8
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-DL-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-DL-NEXT:    v_or_b32_e32 v6, v8, v6
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-DL-NEXT:    v_lshrrev_b32_e32 v6, 8, v6
-; GFX11-DL-NEXT:    v_add_nc_u16 v0, v0, v6
-; GFX11-DL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-DL-NEXT:    v_mad_u16 v0, v4, v7, v0
-; GFX11-DL-NEXT:    v_add_nc_u16 v0, v0, v1
-; GFX11-DL-NEXT:    global_store_b8 v2, v0, s[4:5]
-; GFX11-DL-NEXT:    s_endpgm
+; GFX11-DL-TRUE16-LABEL: udot4_acc8_vecMul:
+; GFX11-DL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-DL-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-DL-TRUE16-NEXT:    v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX11-DL-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-DL-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-DL-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-DL-TRUE16-NEXT:    s_clause 0x1
+; GFX11-DL-TRUE16-NEXT:    global_load_b32 v3, v0, s[0:1]
+; GFX11-DL-TRUE16-NEXT:    global_load_b32 v4, v0, s[2:3]
+; GFX11-DL-TRUE16-NEXT:    global_load_d16_u8 v0, v5, s[4:5]
+; GFX11-DL-TRUE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-DL-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 24, v3
+; GFX11-DL-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-DL-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 24, v4
+; GFX11-DL-TRUE16-NEXT:    v_lshrrev_b16 v0.h, 8, v3.l
+; GFX11-DL-TRUE16-NEXT:    v_mul_lo_u16 v1.l, v3.h, v4.h
+; GFX11-DL-TRUE16-NEXT:    v_lshrrev_b16 v1.h, 8, v4.l
+; GFX11-DL-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-DL-TRUE16-NEXT:    v_mad_u16 v0.l, v3.l, v4.l, v0.l
+; GFX11-DL-TRUE16-NEXT:    v_mul_lo_u16 v2.l, v2.l, v6.l
+; GFX11-DL-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-DL-TRUE16-NEXT:    v_mul_lo_u16 v0.h, v0.h, v1.h
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-DL-TRUE16-NEXT:    v_lshlrev_b16 v6.l, 8, v2.l
+; GFX11-DL-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v0.h
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-DL-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v6.l
+; GFX11-DL-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-DL-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-DL-TRUE16-NEXT:    v_or_b32_e32 v1, v2, v1
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-DL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-DL-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX11-DL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v6
+; GFX11-DL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-DL-TRUE16-NEXT:    v_mad_u16 v0.l, v3.h, v4.h, v0.l
+; GFX11-DL-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX11-DL-TRUE16-NEXT:    global_store_b8 v5, v0, s[4:5]
+; GFX11-DL-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-DL-FAKE16-LABEL: udot4_acc8_vecMul:
+; GFX11-DL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-DL-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-DL-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-DL-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-DL-FAKE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-DL-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-DL-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-DL-FAKE16-NEXT:    s_clause 0x1
+; GFX11-DL-FAKE16-NEXT:    global_load_b32 v1, v0, s[0:1]
+; GFX11-DL-FAKE16-NEXT:    global_load_b32 v0, v0, s[2:3]
+; GFX11-DL-FAKE16-NEXT:    global_load_u8 v3, v2, s[4:5]
+; GFX11-DL-FAKE16-NEXT:    s_waitcnt vmcnt(2)
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 24, v1
+; GFX11-DL-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 24, v0
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v0
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b16 v8, 8, v1
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b16 v9, 8, v0
+; GFX11-DL-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-DL-FAKE16-NEXT:    v_mad_u16 v0, v1, v0, v3
+; GFX11-DL-FAKE16-NEXT:    v_mul_lo_u16 v5, v5, v6
+; GFX11-DL-FAKE16-NEXT:    v_mul_lo_u16 v6, v4, v7
+; GFX11-DL-FAKE16-NEXT:    v_mul_lo_u16 v8, v8, v9
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-DL-FAKE16-NEXT:    v_lshlrev_b16 v5, 8, v5
+; GFX11-DL-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-DL-FAKE16-NEXT:    v_lshlrev_b16 v8, 8, v8
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v5
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-DL-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v5
+; GFX11-DL-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff, v8
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-DL-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-DL-FAKE16-NEXT:    v_or_b32_e32 v6, v8, v6
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-DL-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 8, v6
+; GFX11-DL-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v6
+; GFX11-DL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-DL-FAKE16-NEXT:    v_mad_u16 v0, v4, v7, v0
+; GFX11-DL-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v1
+; GFX11-DL-FAKE16-NEXT:    global_store_b8 v2, v0, s[4:5]
+; GFX11-DL-FAKE16-NEXT:    s_endpgm
                                              ptr addrspace(1) %src2,
                                              ptr addrspace(1) nocapture %dst) {
 entry:
diff --git a/llvm/test/CodeGen/AMDGPU/implicit-kernel-argument-alignment.ll b/llvm/test/CodeGen/AMDGPU/implicit-kernel-argument-alignment.ll
index 3762ed5a3bfec..06c902a3cac47 100644
--- a/llvm/test/CodeGen/AMDGPU/implicit-kernel-argument-alignment.ll
+++ b/llvm/test/CodeGen/AMDGPU/implicit-kernel-argument-alignment.ll
@@ -57,5 +57,3 @@ define amdgpu_kernel void @test_aligned_to_eight(i64 %eight)  {
 
 declare ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll b/llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
index c664c5ccab431..3964207792163 100644
--- a/llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
+++ b/llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
@@ -110,5 +110,3 @@ entry:
   ret void
 }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll b/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
index 44b1bb25bc057..8196ffae2ca27 100644
--- a/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=GFX11
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GFX11,GFX11-TRUE16
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GFX11,GFX11-FAKE16
 
 declare i32 @llvm.amdgcn.workitem.id.x()
 
@@ -50,160 +51,313 @@ bb:
 
 ; FIXME: This generates "instid1(/* invalid instid value */)".
 define amdgpu_kernel void @f2(i32 %arg, i32 %arg1, i32 %arg2, i1 %arg3, i32 %arg4, i1 %arg5, ptr %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10, i1 %arg11) {
-; GFX11-LABEL: f2:
-; GFX11:       ; %bb.0: ; %bb
-; GFX11-NEXT:    s_mov_b64 s[16:17], s[4:5]
-; GFX11-NEXT:    v_mov_b32_e32 v31, v0
-; GFX11-NEXT:    s_load_b32 s19, s[16:17], 0x24
-; GFX11-NEXT:    s_mov_b32 s12, s13
-; GFX11-NEXT:    s_mov_b64 s[10:11], s[6:7]
-; GFX11-NEXT:    s_mov_b64 s[6:7], s[2:3]
-; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v31
-; GFX11-NEXT:    s_mov_b64 s[4:5], s[0:1]
-; GFX11-NEXT:    s_mov_b32 s20, 0
-; GFX11-NEXT:    s_mov_b32 s0, -1
-; GFX11-NEXT:    s_mov_b32 s3, exec_lo
-; GFX11-NEXT:    s_mov_b32 s32, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_mul_lo_u32 v0, s19, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_cmpx_eq_u32_e32 0, v0
-; GFX11-NEXT:    s_cbranch_execz .LBB2_13
-; GFX11-NEXT:  ; %bb.1: ; %bb14
-; GFX11-NEXT:    s_load_b128 s[20:23], s[16:17], 0x2c
-; GFX11-NEXT:    s_mov_b32 s18, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_bitcmp1_b32 s21, 0
-; GFX11-NEXT:    s_cselect_b32 s24, -1, 0
-; GFX11-NEXT:    s_bitcmp0_b32 s21, 0
-; GFX11-NEXT:    s_cbranch_scc0 .LBB2_3
-; GFX11-NEXT:  ; %bb.2: ; %bb15
-; GFX11-NEXT:    s_add_u32 s8, s16, 0x58
-; GFX11-NEXT:    s_addc_u32 s9, s17, 0
-; GFX11-NEXT:    s_getpc_b64 s[0:1]
-; GFX11-NEXT:    s_add_u32 s0, s0, f0@gotpcrel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s1, s1, f0@gotpcrel32@hi+12
-; GFX11-NEXT:    s_mov_b32 s13, s14
-; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x0
-; GFX11-NEXT:    s_mov_b32 s21, s14
-; GFX11-NEXT:    s_mov_b32 s14, s15
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT:    s_mov_b32 s14, s21
-; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    s_cbranch_execz .LBB2_4
-; GFX11-NEXT:    s_branch .LBB2_12
-; GFX11-NEXT:  .LBB2_3:
-; GFX11-NEXT:    s_mov_b32 s2, 0
-; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_vccnz .LBB2_12
-; GFX11-NEXT:  .LBB2_4: ; %bb16
-; GFX11-NEXT:    s_load_b32 s0, s[16:17], 0x54
-; GFX11-NEXT:    s_bitcmp1_b32 s23, 0
-; GFX11-NEXT:    s_cselect_b32 s9, -1, 0
-; GFX11-NEXT:    s_and_b32 s1, s23, 1
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_bitcmp1_b32 s0, 0
-; GFX11-NEXT:    s_mov_b32 s0, -1
-; GFX11-NEXT:    s_cselect_b32 s8, -1, 0
-; GFX11-NEXT:    s_cmp_eq_u32 s1, 0
-; GFX11-NEXT:    s_cbranch_scc0 .LBB2_8
-; GFX11-NEXT:  ; %bb.5: ; %bb18.preheader
-; GFX11-NEXT:    s_load_b128 s[28:31], s[16:17], 0x44
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_mul_hi_u32 s0, s29, s28
-; GFX11-NEXT:    s_mul_i32 s1, s29, s28
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_alignbit_b32 v0, s0, s1, 1
-; GFX11-NEXT:    s_mov_b32 s1, 0
-; GFX11-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_or_b32 s0, s0, 1
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT:    s_lshr_b32 s0, s0, s30
-; GFX11-NEXT:    s_mul_i32 s0, s0, s22
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT:    s_mul_i32 s0, s0, s20
-; GFX11-NEXT:    s_or_b32 s0, s19, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_lshl_b64 s[20:21], s[0:1], 1
-; GFX11-NEXT:    s_mov_b32 s0, s1
-; GFX11-NEXT:    global_load_u16 v1, v0, s[20:21]
-; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s24
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-NEXT:    s_mov_b32 vcc_lo, 0
-; GFX11-NEXT:    .p2align 6
-; GFX11-NEXT:  .LBB2_6: ; %bb18
-; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX11-NEXT:    s_and_b32 s1, 0xffff, s1
-; GFX11-NEXT:    v_readfirstlane_b32 s13, v0
-; GFX11-NEXT:    s_cmp_lg_u32 s1, 0
-; GFX11-NEXT:    s_cselect_b32 s1, -1, 0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s1
-; GFX11-NEXT:    s_and_b32 s1, s8, s1
-; GFX11-NEXT:    s_and_b32 s1, s1, exec_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_readfirstlane_b32 s19, v2
-; GFX11-NEXT:    s_cselect_b32 s1, s19, s13
-; GFX11-NEXT:    s_and_b32 s13, 0xffff, s0
-; GFX11-NEXT:    s_and_b32 s1, s1, 1
-; GFX11-NEXT:    s_cmp_lg_u32 s13, 0
-; GFX11-NEXT:    s_cselect_b32 s13, -1, 0
-; GFX11-NEXT:    s_and_b32 s20, s9, exec_lo
-; GFX11-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s13
-; GFX11-NEXT:    v_readfirstlane_b32 s13, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT:    v_readfirstlane_b32 s19, v2
-; GFX11-NEXT:    s_cselect_b32 s13, s19, s13
-; GFX11-NEXT:    s_bitcmp1_b32 s13, 0
-; GFX11-NEXT:    s_cselect_b32 s13, 0x100, 0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_or_b32 s0, s13, s0
-; GFX11-NEXT:    s_cbranch_vccz .LBB2_6
-; GFX11-NEXT:  ; %bb.7: ; %Flow
-; GFX11-NEXT:    s_mov_b32 s0, 0
-; GFX11-NEXT:  .LBB2_8: ; %Flow12
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_b32 vcc_lo, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_vccz .LBB2_12
-; GFX11-NEXT:  ; %bb.9:
-; GFX11-NEXT:    s_xor_b32 s0, s8, -1
-; GFX11-NEXT:  .LBB2_10: ; %bb17
-; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_b32 vcc_lo, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_vccz .LBB2_10
-; GFX11-NEXT:  ; %bb.11: ; %Flow6
-; GFX11-NEXT:    s_mov_b32 s18, -1
-; GFX11-NEXT:  .LBB2_12: ; %Flow11
-; GFX11-NEXT:    s_and_b32 s20, s2, exec_lo
-; GFX11-NEXT:    s_or_not1_b32 s0, s18, exec_lo
-; GFX11-NEXT:  .LBB2_13: ; %Flow9
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s3
-; GFX11-NEXT:    s_and_saveexec_b32 s3, s0
-; GFX11-NEXT:    s_cbranch_execz .LBB2_15
-; GFX11-NEXT:  ; %bb.14: ; %bb43
-; GFX11-NEXT:    s_add_u32 s8, s16, 0x58
-; GFX11-NEXT:    s_addc_u32 s9, s17, 0
-; GFX11-NEXT:    s_getpc_b64 s[0:1]
-; GFX11-NEXT:    s_add_u32 s0, s0, f0@gotpcrel32@lo+4
-; GFX11-NEXT:    s_addc_u32 s1, s1, f0@gotpcrel32@hi+12
-; GFX11-NEXT:    s_mov_b32 s13, s14
-; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x0
-; GFX11-NEXT:    s_mov_b32 s14, s15
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT:    s_or_b32 s20, s20, exec_lo
-; GFX11-NEXT:  .LBB2_15: ; %Flow14
-; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s3
-; GFX11-NEXT:    s_and_saveexec_b32 s0, s20
-; GFX11-NEXT:  ; %bb.16: ; %UnifiedUnreachableBlock
-; GFX11-NEXT:    ; divergent unreachable
-; GFX11-NEXT:  ; %bb.17: ; %UnifiedReturnBlock
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: f2:
+; GFX11-TRUE16:       ; %bb.0: ; %bb
+; GFX11-TRUE16-NEXT:    s_mov_b64 s[16:17], s[4:5]
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v31, v0
+; GFX11-TRUE16-NEXT:    s_load_b32 s19, s[16:17], 0x24
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, s13
+; GFX11-TRUE16-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX11-TRUE16-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v31
+; GFX11-TRUE16-NEXT:    s_mov_b64 s[4:5], s[0:1]
+; GFX11-TRUE16-NEXT:    s_mov_b32 s20, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, -1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, exec_lo
+; GFX11-TRUE16-NEXT:    s_mov_b32 s32, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mul_lo_u32 v0, s19, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cmpx_eq_u32_e32 0, v0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB2_13
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %bb14
+; GFX11-TRUE16-NEXT:    s_load_b128 s[20:23], s[16:17], 0x2c
+; GFX11-TRUE16-NEXT:    s_mov_b32 s18, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_bitcmp1_b32 s21, 0
+; GFX11-TRUE16-NEXT:    s_cselect_b32 s24, -1, 0
+; GFX11-TRUE16-NEXT:    s_bitcmp0_b32 s21, 0
+; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB2_3
+; GFX11-TRUE16-NEXT:  ; %bb.2: ; %bb15
+; GFX11-TRUE16-NEXT:    s_add_u32 s8, s16, 0x58
+; GFX11-TRUE16-NEXT:    s_addc_u32 s9, s17, 0
+; GFX11-TRUE16-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-TRUE16-NEXT:    s_add_u32 s0, s0, f0@gotpcrel32@lo+4
+; GFX11-TRUE16-NEXT:    s_addc_u32 s1, s1, f0@gotpcrel32@hi+12
+; GFX11-TRUE16-NEXT:    s_mov_b32 s13, s14
+; GFX11-TRUE16-NEXT:    s_load_b64 s[0:1], s[0:1], 0x0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s21, s14
+; GFX11-TRUE16-NEXT:    s_mov_b32 s14, s15
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-TRUE16-NEXT:    s_mov_b32 s14, s21
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, -1
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB2_4
+; GFX11-TRUE16-NEXT:    s_branch .LBB2_12
+; GFX11-TRUE16-NEXT:  .LBB2_3:
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, 0
+; GFX11-TRUE16-NEXT:  .LBB2_4: ; %bb16
+; GFX11-TRUE16-NEXT:    s_load_b32 s1, s[16:17], 0x54
+; GFX11-TRUE16-NEXT:    s_bitcmp1_b32 s23, 0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s8, -1
+; GFX11-TRUE16-NEXT:    s_cselect_b32 s2, -1, 0
+; GFX11-TRUE16-NEXT:    s_and_b32 s9, s23, 1
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_bitcmp1_b32 s1, 0
+; GFX11-TRUE16-NEXT:    s_cselect_b32 s1, -1, 0
+; GFX11-TRUE16-NEXT:    s_cmp_eq_u32 s9, 0
+; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB2_8
+; GFX11-TRUE16-NEXT:  ; %bb.5: ; %bb18.preheader
+; GFX11-TRUE16-NEXT:    s_load_b128 s[28:31], s[16:17], 0x44
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mul_hi_u32 s8, s29, s28
+; GFX11-TRUE16-NEXT:    s_mul_i32 s9, s29, s28
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_alignbit_b32 v0, s8, s9, 1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s9, 0
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s8, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-TRUE16-NEXT:    s_or_b32 s8, s8, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_lshr_b32 s8, s8, s30
+; GFX11-TRUE16-NEXT:    s_mul_i32 s8, s8, s22
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_mul_i32 s8, s8, s20
+; GFX11-TRUE16-NEXT:    s_or_b32 s8, s19, s8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_lshl_b64 s[20:21], s[8:9], 1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s8, s9
+; GFX11-TRUE16-NEXT:    global_load_u16 v1, v0, s[20:21]
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s24
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT:    s_mov_b32 vcc_lo, 0
+; GFX11-TRUE16-NEXT:    .p2align 6
+; GFX11-TRUE16-NEXT:  .LBB2_6: ; %bb18
+; GFX11-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-TRUE16-NEXT:    s_and_b32 s8, 0xffff, s8
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s13, v0
+; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s8, 0
+; GFX11-TRUE16-NEXT:    s_cselect_b32 s8, -1, 0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s8
+; GFX11-TRUE16-NEXT:    s_and_b32 s8, s1, s8
+; GFX11-TRUE16-NEXT:    s_and_b32 s8, s8, exec_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s19, v2
+; GFX11-TRUE16-NEXT:    s_cselect_b32 s8, s19, s13
+; GFX11-TRUE16-NEXT:    s_and_b32 s13, 0xffff, s9
+; GFX11-TRUE16-NEXT:    s_and_b32 s8, s8, 1
+; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s13, 0
+; GFX11-TRUE16-NEXT:    s_cselect_b32 s13, -1, 0
+; GFX11-TRUE16-NEXT:    s_and_b32 s20, s2, exec_lo
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s13
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s13, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s19, v2
+; GFX11-TRUE16-NEXT:    s_cselect_b32 s13, s19, s13
+; GFX11-TRUE16-NEXT:    s_bitcmp1_b32 s13, 0
+; GFX11-TRUE16-NEXT:    s_cselect_b32 s13, 0x100, 0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_or_b32 s9, s13, s9
+; GFX11-TRUE16-NEXT:    s_cbranch_vccz .LBB2_6
+; GFX11-TRUE16-NEXT:  ; %bb.7: ; %Flow
+; GFX11-TRUE16-NEXT:    s_mov_b32 s8, 0
+; GFX11-TRUE16-NEXT:  .LBB2_8: ; %Flow12
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_b32 vcc_lo, exec_lo, s8
+; GFX11-TRUE16-NEXT:    s_cbranch_vccz .LBB2_12
+; GFX11-TRUE16-NEXT:  ; %bb.9:
+; GFX11-TRUE16-NEXT:    s_xor_b32 s1, s1, -1
+; GFX11-TRUE16-NEXT:  .LBB2_10: ; %bb17
+; GFX11-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_b32 vcc_lo, exec_lo, s1
+; GFX11-TRUE16-NEXT:    s_cbranch_vccz .LBB2_10
+; GFX11-TRUE16-NEXT:  ; %bb.11: ; %Flow6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s18, -1
+; GFX11-TRUE16-NEXT:  .LBB2_12: ; %Flow11
+; GFX11-TRUE16-NEXT:    s_and_b32 s20, s0, exec_lo
+; GFX11-TRUE16-NEXT:    s_or_not1_b32 s0, s18, exec_lo
+; GFX11-TRUE16-NEXT:  .LBB2_13: ; %Flow9
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s3
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s3, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB2_15
+; GFX11-TRUE16-NEXT:  ; %bb.14: ; %bb43
+; GFX11-TRUE16-NEXT:    s_add_u32 s8, s16, 0x58
+; GFX11-TRUE16-NEXT:    s_addc_u32 s9, s17, 0
+; GFX11-TRUE16-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-TRUE16-NEXT:    s_add_u32 s0, s0, f0@gotpcrel32@lo+4
+; GFX11-TRUE16-NEXT:    s_addc_u32 s1, s1, f0@gotpcrel32@hi+12
+; GFX11-TRUE16-NEXT:    s_mov_b32 s13, s14
+; GFX11-TRUE16-NEXT:    s_load_b64 s[0:1], s[0:1], 0x0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s14, s15
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-TRUE16-NEXT:    s_or_b32 s20, s20, exec_lo
+; GFX11-TRUE16-NEXT:  .LBB2_15: ; %Flow14
+; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s3
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, s20
+; GFX11-TRUE16-NEXT:  ; %bb.16: ; %UnifiedUnreachableBlock
+; GFX11-TRUE16-NEXT:    ; divergent unreachable
+; GFX11-TRUE16-NEXT:  ; %bb.17: ; %UnifiedReturnBlock
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: f2:
+; GFX11-FAKE16:       ; %bb.0: ; %bb
+; GFX11-FAKE16-NEXT:    s_mov_b64 s[16:17], s[4:5]
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v31, v0
+; GFX11-FAKE16-NEXT:    s_load_b32 s19, s[16:17], 0x24
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, s13
+; GFX11-FAKE16-NEXT:    s_mov_b64 s[10:11], s[6:7]
+; GFX11-FAKE16-NEXT:    s_mov_b64 s[6:7], s[2:3]
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v31
+; GFX11-FAKE16-NEXT:    s_mov_b64 s[4:5], s[0:1]
+; GFX11-FAKE16-NEXT:    s_mov_b32 s20, 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, -1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, exec_lo
+; GFX11-FAKE16-NEXT:    s_mov_b32 s32, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_mul_lo_u32 v0, s19, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cmpx_eq_u32_e32 0, v0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB2_13
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %bb14
+; GFX11-FAKE16-NEXT:    s_load_b128 s[20:23], s[16:17], 0x2c
+; GFX11-FAKE16-NEXT:    s_mov_b32 s18, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_bitcmp1_b32 s21, 0
+; GFX11-FAKE16-NEXT:    s_cselect_b32 s24, -1, 0
+; GFX11-FAKE16-NEXT:    s_bitcmp0_b32 s21, 0
+; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB2_3
+; GFX11-FAKE16-NEXT:  ; %bb.2: ; %bb15
+; GFX11-FAKE16-NEXT:    s_add_u32 s8, s16, 0x58
+; GFX11-FAKE16-NEXT:    s_addc_u32 s9, s17, 0
+; GFX11-FAKE16-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-FAKE16-NEXT:    s_add_u32 s0, s0, f0@gotpcrel32@lo+4
+; GFX11-FAKE16-NEXT:    s_addc_u32 s1, s1, f0@gotpcrel32@hi+12
+; GFX11-FAKE16-NEXT:    s_mov_b32 s13, s14
+; GFX11-FAKE16-NEXT:    s_load_b64 s[0:1], s[0:1], 0x0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s21, s14
+; GFX11-FAKE16-NEXT:    s_mov_b32 s14, s15
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-FAKE16-NEXT:    s_mov_b32 s14, s21
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB2_4
+; GFX11-FAKE16-NEXT:    s_branch .LBB2_12
+; GFX11-FAKE16-NEXT:  .LBB2_3:
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, 0
+; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB2_12
+; GFX11-FAKE16-NEXT:  .LBB2_4: ; %bb16
+; GFX11-FAKE16-NEXT:    s_load_b32 s0, s[16:17], 0x54
+; GFX11-FAKE16-NEXT:    s_bitcmp1_b32 s23, 0
+; GFX11-FAKE16-NEXT:    s_cselect_b32 s9, -1, 0
+; GFX11-FAKE16-NEXT:    s_and_b32 s1, s23, 1
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_bitcmp1_b32 s0, 0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, -1
+; GFX11-FAKE16-NEXT:    s_cselect_b32 s8, -1, 0
+; GFX11-FAKE16-NEXT:    s_cmp_eq_u32 s1, 0
+; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB2_8
+; GFX11-FAKE16-NEXT:  ; %bb.5: ; %bb18.preheader
+; GFX11-FAKE16-NEXT:    s_load_b128 s[28:31], s[16:17], 0x44
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mul_hi_u32 s0, s29, s28
+; GFX11-FAKE16-NEXT:    s_mul_i32 s1, s29, s28
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v0, s0, s1, 1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, 0
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-FAKE16-NEXT:    s_or_b32 s0, s0, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_lshr_b32 s0, s0, s30
+; GFX11-FAKE16-NEXT:    s_mul_i32 s0, s0, s22
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_mul_i32 s0, s0, s20
+; GFX11-FAKE16-NEXT:    s_or_b32 s0, s19, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_lshl_b64 s[20:21], s[0:1], 1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, s1
+; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[20:21]
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s24
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT:    s_mov_b32 vcc_lo, 0
+; GFX11-FAKE16-NEXT:    .p2align 6
+; GFX11-FAKE16-NEXT:  .LBB2_6: ; %bb18
+; GFX11-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-FAKE16-NEXT:    s_and_b32 s1, 0xffff, s1
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s13, v0
+; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s1, 0
+; GFX11-FAKE16-NEXT:    s_cselect_b32 s1, -1, 0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s1
+; GFX11-FAKE16-NEXT:    s_and_b32 s1, s8, s1
+; GFX11-FAKE16-NEXT:    s_and_b32 s1, s1, exec_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s19, v2
+; GFX11-FAKE16-NEXT:    s_cselect_b32 s1, s19, s13
+; GFX11-FAKE16-NEXT:    s_and_b32 s13, 0xffff, s0
+; GFX11-FAKE16-NEXT:    s_and_b32 s1, s1, 1
+; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s13, 0
+; GFX11-FAKE16-NEXT:    s_cselect_b32 s13, -1, 0
+; GFX11-FAKE16-NEXT:    s_and_b32 s20, s9, exec_lo
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s13
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s13, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s19, v2
+; GFX11-FAKE16-NEXT:    s_cselect_b32 s13, s19, s13
+; GFX11-FAKE16-NEXT:    s_bitcmp1_b32 s13, 0
+; GFX11-FAKE16-NEXT:    s_cselect_b32 s13, 0x100, 0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_or_b32 s0, s13, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_vccz .LBB2_6
+; GFX11-FAKE16-NEXT:  ; %bb.7: ; %Flow
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, 0
+; GFX11-FAKE16-NEXT:  .LBB2_8: ; %Flow12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_b32 vcc_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_vccz .LBB2_12
+; GFX11-FAKE16-NEXT:  ; %bb.9:
+; GFX11-FAKE16-NEXT:    s_xor_b32 s0, s8, -1
+; GFX11-FAKE16-NEXT:  .LBB2_10: ; %bb17
+; GFX11-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_b32 vcc_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_vccz .LBB2_10
+; GFX11-FAKE16-NEXT:  ; %bb.11: ; %Flow6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s18, -1
+; GFX11-FAKE16-NEXT:  .LBB2_12: ; %Flow11
+; GFX11-FAKE16-NEXT:    s_and_b32 s20, s2, exec_lo
+; GFX11-FAKE16-NEXT:    s_or_not1_b32 s0, s18, exec_lo
+; GFX11-FAKE16-NEXT:  .LBB2_13: ; %Flow9
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s3
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s3, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB2_15
+; GFX11-FAKE16-NEXT:  ; %bb.14: ; %bb43
+; GFX11-FAKE16-NEXT:    s_add_u32 s8, s16, 0x58
+; GFX11-FAKE16-NEXT:    s_addc_u32 s9, s17, 0
+; GFX11-FAKE16-NEXT:    s_getpc_b64 s[0:1]
+; GFX11-FAKE16-NEXT:    s_add_u32 s0, s0, f0@gotpcrel32@lo+4
+; GFX11-FAKE16-NEXT:    s_addc_u32 s1, s1, f0@gotpcrel32@hi+12
+; GFX11-FAKE16-NEXT:    s_mov_b32 s13, s14
+; GFX11-FAKE16-NEXT:    s_load_b64 s[0:1], s[0:1], 0x0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s14, s15
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_swappc_b64 s[30:31], s[0:1]
+; GFX11-FAKE16-NEXT:    s_or_b32 s20, s20, exec_lo
+; GFX11-FAKE16-NEXT:  .LBB2_15: ; %Flow14
+; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s3
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, s20
+; GFX11-FAKE16-NEXT:  ; %bb.16: ; %UnifiedUnreachableBlock
+; GFX11-FAKE16-NEXT:    ; divergent unreachable
+; GFX11-FAKE16-NEXT:  ; %bb.17: ; %UnifiedReturnBlock
+; GFX11-FAKE16-NEXT:    s_endpgm
 bb:
   %i = tail call i32 @llvm.amdgcn.workitem.id.x()
   %i12 = mul i32 %arg, %i
@@ -257,5 +411,3 @@ bb43:
 
 attributes #0 = { noinline optnone }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll b/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
index ef91f36d60373..0d3340006f17e 100644
--- a/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
+++ b/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
@@ -1,10 +1,14 @@
 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32 -stop-after=finalize-isel -verify-machineinstrs < %s | FileCheck -check-prefix=GISEL-GFX11 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -stop-after=finalize-isel -verify-machineinstrs < %s | FileCheck -check-prefix=GISEL-GFX11 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=+wavefrontsize32 -stop-after=finalize-isel -verify-machineinstrs < %s | FileCheck -check-prefixes=GISEL-GFX11,GISEL-GFX11-TRUE16 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=+wavefrontsize32 -stop-after=finalize-isel -verify-machineinstrs < %s | FileCheck -check-prefixes=GISEL-GFX11,GISEL-GFX11-FAKE16 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=+wavefrontsize64 -stop-after=finalize-isel -verify-machineinstrs < %s | FileCheck -check-prefixes=GISEL-GFX11,GISEL-GFX11-TRUE16 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=+wavefrontsize64 -stop-after=finalize-isel -verify-machineinstrs < %s | FileCheck -check-prefixes=GISEL-GFX11,GISEL-GFX11-FAKE16 %s
 ; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize32 -stop-after=finalize-isel -verify-machineinstrs < %s | FileCheck -check-prefix=GISEL-GFX10 %s
 ; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize64 -stop-after=finalize-isel -verify-machineinstrs < %s | FileCheck -check-prefix=GISEL-GFX10 %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32 -stop-after=finalize-isel -verify-machineinstrs < %s | FileCheck -check-prefix=DAGISEL-GFX11-WF32 %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -stop-after=finalize-isel -verify-machineinstrs < %s | FileCheck -check-prefix=DAGISEL-GFX11-WF64 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=+wavefrontsize32 -stop-after=finalize-isel -verify-machineinstrs < %s | FileCheck -check-prefixes=DAGISEL-GFX11-WF32,DAGISEL-GFX11-WF32-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=+wavefrontsize32 -stop-after=finalize-isel -verify-machineinstrs < %s | FileCheck -check-prefixes=DAGISEL-GFX11-WF32,DAGISEL-GFX11-WF32-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=+wavefrontsize64 -stop-after=finalize-isel -verify-machineinstrs < %s | FileCheck -check-prefixes=DAGISEL-GFX11-WF64,DAGISEL-GFX11-WF64-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=+wavefrontsize64 -stop-after=finalize-isel -verify-machineinstrs < %s | FileCheck -check-prefixes=DAGISEL-GFX11-WF64,DAGISEL-GFX11-WF64-FAKE16 %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize32 -stop-after=finalize-isel -verify-machineinstrs < %s | FileCheck -check-prefix=DAGISEL-GFX10-WF32 %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize64 -stop-after=finalize-isel -verify-machineinstrs < %s | FileCheck -check-prefix=DAGISEL-GFX10-WF64 %s
 
@@ -794,18 +798,32 @@ define amdgpu_cs_chain_preserve void @amdgpu_cs_chain_preserve_cc_float(float in
 }
 
 define amdgpu_cs_chain_preserve void @amdgpu_cs_chain_preserve_cc_half(half inreg %a, half %b) {
-  ; GISEL-GFX11-LABEL: name: amdgpu_cs_chain_preserve_cc_half
-  ; GISEL-GFX11: bb.1 (%ir-block.0):
-  ; GISEL-GFX11-NEXT:   liveins: $sgpr0, $vgpr8
-  ; GISEL-GFX11-NEXT: {{  $}}
-  ; GISEL-GFX11-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GISEL-GFX11-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
-  ; GISEL-GFX11-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
-  ; GISEL-GFX11-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
-  ; GISEL-GFX11-NEXT:   [[V_ADD_F16_fake16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F16_fake16_e64 0, [[COPY2]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
-  ; GISEL-GFX11-NEXT:   [[COPY3:%[0-9]+]]:vreg_64 = COPY [[DEF]]
-  ; GISEL-GFX11-NEXT:   FLAT_STORE_SHORT [[COPY3]], [[V_ADD_F16_fake16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into `ptr poison`)
-  ; GISEL-GFX11-NEXT:   S_ENDPGM 0
+  ; GISEL-GFX11-TRUE16-LABEL: name: amdgpu_cs_chain_preserve_cc_half
+  ; GISEL-GFX11-TRUE16: bb.1 (%ir-block.0):
+  ; GISEL-GFX11-TRUE16-NEXT:   liveins: $sgpr0, $vgpr8
+  ; GISEL-GFX11-TRUE16-NEXT: {{  $}}
+  ; GISEL-GFX11-TRUE16-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GISEL-GFX11-TRUE16-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
+  ; GISEL-GFX11-TRUE16-NEXT:   [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY1]].lo16
+  ; GISEL-GFX11-TRUE16-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+  ; GISEL-GFX11-TRUE16-NEXT:   [[COPY3:%[0-9]+]]:vgpr_16 = COPY [[COPY]]
+  ; GISEL-GFX11-TRUE16-NEXT:   [[V_ADD_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_ADD_F16_t16_e64 0, [[COPY3]], 0, [[COPY2]], 0, 0, 0, implicit $mode, implicit $exec
+  ; GISEL-GFX11-TRUE16-NEXT:   [[COPY4:%[0-9]+]]:vreg_64 = COPY [[DEF]]
+  ; GISEL-GFX11-TRUE16-NEXT:   FLAT_STORE_SHORT_t16 [[COPY4]], [[V_ADD_F16_t16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into `ptr poison`)
+  ; GISEL-GFX11-TRUE16-NEXT:   S_ENDPGM 0
+  ;
+  ; GISEL-GFX11-FAKE16-LABEL: name: amdgpu_cs_chain_preserve_cc_half
+  ; GISEL-GFX11-FAKE16: bb.1 (%ir-block.0):
+  ; GISEL-GFX11-FAKE16-NEXT:   liveins: $sgpr0, $vgpr8
+  ; GISEL-GFX11-FAKE16-NEXT: {{  $}}
+  ; GISEL-GFX11-FAKE16-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GISEL-GFX11-FAKE16-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
+  ; GISEL-GFX11-FAKE16-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+  ; GISEL-GFX11-FAKE16-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
+  ; GISEL-GFX11-FAKE16-NEXT:   [[V_ADD_F16_fake16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F16_fake16_e64 0, [[COPY2]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
+  ; GISEL-GFX11-FAKE16-NEXT:   [[COPY3:%[0-9]+]]:vreg_64 = COPY [[DEF]]
+  ; GISEL-GFX11-FAKE16-NEXT:   FLAT_STORE_SHORT [[COPY3]], [[V_ADD_F16_fake16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into `ptr poison`)
+  ; GISEL-GFX11-FAKE16-NEXT:   S_ENDPGM 0
   ;
   ; GISEL-GFX10-LABEL: name: amdgpu_cs_chain_preserve_cc_half
   ; GISEL-GFX10: bb.1 (%ir-block.0):
@@ -820,29 +838,55 @@ define amdgpu_cs_chain_preserve void @amdgpu_cs_chain_preserve_cc_half(half inre
   ; GISEL-GFX10-NEXT:   FLAT_STORE_SHORT [[COPY3]], [[V_ADD_F16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into `ptr poison`)
   ; GISEL-GFX10-NEXT:   S_ENDPGM 0
   ;
-  ; DAGISEL-GFX11-WF32-LABEL: name: amdgpu_cs_chain_preserve_cc_half
-  ; DAGISEL-GFX11-WF32: bb.0 (%ir-block.0):
-  ; DAGISEL-GFX11-WF32-NEXT:   liveins: $sgpr0, $vgpr8
-  ; DAGISEL-GFX11-WF32-NEXT: {{  $}}
-  ; DAGISEL-GFX11-WF32-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr8
-  ; DAGISEL-GFX11-WF32-NEXT:   [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
-  ; DAGISEL-GFX11-WF32-NEXT:   [[V_ADD_F16_fake16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F16_fake16_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
-  ; DAGISEL-GFX11-WF32-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
-  ; DAGISEL-GFX11-WF32-NEXT:   [[COPY2:%[0-9]+]]:vreg_64 = COPY [[DEF]]
-  ; DAGISEL-GFX11-WF32-NEXT:   FLAT_STORE_SHORT killed [[COPY2]], killed [[V_ADD_F16_fake16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into `ptr poison`)
-  ; DAGISEL-GFX11-WF32-NEXT:   S_ENDPGM 0
+  ; DAGISEL-GFX11-WF32-TRUE16-LABEL: name: amdgpu_cs_chain_preserve_cc_half
+  ; DAGISEL-GFX11-WF32-TRUE16: bb.0 (%ir-block.0):
+  ; DAGISEL-GFX11-WF32-TRUE16-NEXT:   liveins: $sgpr0, $vgpr8
+  ; DAGISEL-GFX11-WF32-TRUE16-NEXT: {{  $}}
+  ; DAGISEL-GFX11-WF32-TRUE16-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr8
+  ; DAGISEL-GFX11-WF32-TRUE16-NEXT:   [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
+  ; DAGISEL-GFX11-WF32-TRUE16-NEXT:   [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY]]
+  ; DAGISEL-GFX11-WF32-TRUE16-NEXT:   [[V_ADD_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_ADD_F16_t16_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, 0, implicit $mode, implicit $exec
+  ; DAGISEL-GFX11-WF32-TRUE16-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+  ; DAGISEL-GFX11-WF32-TRUE16-NEXT:   [[COPY3:%[0-9]+]]:vreg_64 = COPY [[DEF]]
+  ; DAGISEL-GFX11-WF32-TRUE16-NEXT:   FLAT_STORE_SHORT_t16 killed [[COPY3]], killed [[V_ADD_F16_t16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into `ptr poison`)
+  ; DAGISEL-GFX11-WF32-TRUE16-NEXT:   S_ENDPGM 0
   ;
-  ; DAGISEL-GFX11-WF64-LABEL: name: amdgpu_cs_chain_preserve_cc_half
-  ; DAGISEL-GFX11-WF64: bb.0 (%ir-block.0):
-  ; DAGISEL-GFX11-WF64-NEXT:   liveins: $sgpr0, $vgpr8
-  ; DAGISEL-GFX11-WF64-NEXT: {{  $}}
-  ; DAGISEL-GFX11-WF64-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr8
-  ; DAGISEL-GFX11-WF64-NEXT:   [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
-  ; DAGISEL-GFX11-WF64-NEXT:   [[V_ADD_F16_fake16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F16_fake16_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
-  ; DAGISEL-GFX11-WF64-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
-  ; DAGISEL-GFX11-WF64-NEXT:   [[COPY2:%[0-9]+]]:vreg_64 = COPY [[DEF]]
-  ; DAGISEL-GFX11-WF64-NEXT:   FLAT_STORE_SHORT killed [[COPY2]], killed [[V_ADD_F16_fake16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into `ptr poison`)
-  ; DAGISEL-GFX11-WF64-NEXT:   S_ENDPGM 0
+  ; DAGISEL-GFX11-WF32-FAKE16-LABEL: name: amdgpu_cs_chain_preserve_cc_half
+  ; DAGISEL-GFX11-WF32-FAKE16: bb.0 (%ir-block.0):
+  ; DAGISEL-GFX11-WF32-FAKE16-NEXT:   liveins: $sgpr0, $vgpr8
+  ; DAGISEL-GFX11-WF32-FAKE16-NEXT: {{  $}}
+  ; DAGISEL-GFX11-WF32-FAKE16-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr8
+  ; DAGISEL-GFX11-WF32-FAKE16-NEXT:   [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
+  ; DAGISEL-GFX11-WF32-FAKE16-NEXT:   [[V_ADD_F16_fake16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F16_fake16_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
+  ; DAGISEL-GFX11-WF32-FAKE16-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+  ; DAGISEL-GFX11-WF32-FAKE16-NEXT:   [[COPY2:%[0-9]+]]:vreg_64 = COPY [[DEF]]
+  ; DAGISEL-GFX11-WF32-FAKE16-NEXT:   FLAT_STORE_SHORT killed [[COPY2]], killed [[V_ADD_F16_fake16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into `ptr poison`)
+  ; DAGISEL-GFX11-WF32-FAKE16-NEXT:   S_ENDPGM 0
+  ;
+  ; DAGISEL-GFX11-WF64-TRUE16-LABEL: name: amdgpu_cs_chain_preserve_cc_half
+  ; DAGISEL-GFX11-WF64-TRUE16: bb.0 (%ir-block.0):
+  ; DAGISEL-GFX11-WF64-TRUE16-NEXT:   liveins: $sgpr0, $vgpr8
+  ; DAGISEL-GFX11-WF64-TRUE16-NEXT: {{  $}}
+  ; DAGISEL-GFX11-WF64-TRUE16-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr8
+  ; DAGISEL-GFX11-WF64-TRUE16-NEXT:   [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
+  ; DAGISEL-GFX11-WF64-TRUE16-NEXT:   [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY]]
+  ; DAGISEL-GFX11-WF64-TRUE16-NEXT:   [[V_ADD_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_ADD_F16_t16_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, 0, implicit $mode, implicit $exec
+  ; DAGISEL-GFX11-WF64-TRUE16-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+  ; DAGISEL-GFX11-WF64-TRUE16-NEXT:   [[COPY3:%[0-9]+]]:vreg_64 = COPY [[DEF]]
+  ; DAGISEL-GFX11-WF64-TRUE16-NEXT:   FLAT_STORE_SHORT_t16 killed [[COPY3]], killed [[V_ADD_F16_t16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into `ptr poison`)
+  ; DAGISEL-GFX11-WF64-TRUE16-NEXT:   S_ENDPGM 0
+  ;
+  ; DAGISEL-GFX11-WF64-FAKE16-LABEL: name: amdgpu_cs_chain_preserve_cc_half
+  ; DAGISEL-GFX11-WF64-FAKE16: bb.0 (%ir-block.0):
+  ; DAGISEL-GFX11-WF64-FAKE16-NEXT:   liveins: $sgpr0, $vgpr8
+  ; DAGISEL-GFX11-WF64-FAKE16-NEXT: {{  $}}
+  ; DAGISEL-GFX11-WF64-FAKE16-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr8
+  ; DAGISEL-GFX11-WF64-FAKE16-NEXT:   [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
+  ; DAGISEL-GFX11-WF64-FAKE16-NEXT:   [[V_ADD_F16_fake16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F16_fake16_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
+  ; DAGISEL-GFX11-WF64-FAKE16-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+  ; DAGISEL-GFX11-WF64-FAKE16-NEXT:   [[COPY2:%[0-9]+]]:vreg_64 = COPY [[DEF]]
+  ; DAGISEL-GFX11-WF64-FAKE16-NEXT:   FLAT_STORE_SHORT killed [[COPY2]], killed [[V_ADD_F16_fake16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into `ptr poison`)
+  ; DAGISEL-GFX11-WF64-FAKE16-NEXT:   S_ENDPGM 0
   ;
   ; DAGISEL-GFX10-WF32-LABEL: name: amdgpu_cs_chain_preserve_cc_half
   ; DAGISEL-GFX10-WF32: bb.0 (%ir-block.0):
@@ -962,18 +1006,32 @@ define amdgpu_cs_chain_preserve void @amdgpu_cs_chain_cc_bfloat(bfloat inreg %a,
 }
 
 define amdgpu_cs_chain_preserve void @amdgpu_cs_chain_preserve_cc_i16(i16 inreg %a, i16 %b) {
-  ; GISEL-GFX11-LABEL: name: amdgpu_cs_chain_preserve_cc_i16
-  ; GISEL-GFX11: bb.1 (%ir-block.0):
-  ; GISEL-GFX11-NEXT:   liveins: $sgpr0, $vgpr8
-  ; GISEL-GFX11-NEXT: {{  $}}
-  ; GISEL-GFX11-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GISEL-GFX11-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
-  ; GISEL-GFX11-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
-  ; GISEL-GFX11-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
-  ; GISEL-GFX11-NEXT:   [[V_ADD_NC_U16_fake16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_NC_U16_fake16_e64 0, [[COPY2]], 0, [[COPY1]], 0, 0, implicit $exec
-  ; GISEL-GFX11-NEXT:   [[COPY3:%[0-9]+]]:vreg_64 = COPY [[DEF]]
-  ; GISEL-GFX11-NEXT:   FLAT_STORE_SHORT [[COPY3]], [[V_ADD_NC_U16_fake16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into `ptr poison`)
-  ; GISEL-GFX11-NEXT:   S_ENDPGM 0
+  ; GISEL-GFX11-TRUE16-LABEL: name: amdgpu_cs_chain_preserve_cc_i16
+  ; GISEL-GFX11-TRUE16: bb.1 (%ir-block.0):
+  ; GISEL-GFX11-TRUE16-NEXT:   liveins: $sgpr0, $vgpr8
+  ; GISEL-GFX11-TRUE16-NEXT: {{  $}}
+  ; GISEL-GFX11-TRUE16-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GISEL-GFX11-TRUE16-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
+  ; GISEL-GFX11-TRUE16-NEXT:   [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY1]].lo16
+  ; GISEL-GFX11-TRUE16-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+  ; GISEL-GFX11-TRUE16-NEXT:   [[COPY3:%[0-9]+]]:vgpr_16 = COPY [[COPY]]
+  ; GISEL-GFX11-TRUE16-NEXT:   [[V_ADD_NC_U16_t16_e64_:%[0-9]+]]:vgpr_16 = V_ADD_NC_U16_t16_e64 0, [[COPY3]], 0, [[COPY2]], 0, 0, implicit $exec
+  ; GISEL-GFX11-TRUE16-NEXT:   [[COPY4:%[0-9]+]]:vreg_64 = COPY [[DEF]]
+  ; GISEL-GFX11-TRUE16-NEXT:   FLAT_STORE_SHORT_t16 [[COPY4]], [[V_ADD_NC_U16_t16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into `ptr poison`)
+  ; GISEL-GFX11-TRUE16-NEXT:   S_ENDPGM 0
+  ;
+  ; GISEL-GFX11-FAKE16-LABEL: name: amdgpu_cs_chain_preserve_cc_i16
+  ; GISEL-GFX11-FAKE16: bb.1 (%ir-block.0):
+  ; GISEL-GFX11-FAKE16-NEXT:   liveins: $sgpr0, $vgpr8
+  ; GISEL-GFX11-FAKE16-NEXT: {{  $}}
+  ; GISEL-GFX11-FAKE16-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GISEL-GFX11-FAKE16-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
+  ; GISEL-GFX11-FAKE16-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+  ; GISEL-GFX11-FAKE16-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
+  ; GISEL-GFX11-FAKE16-NEXT:   [[V_ADD_NC_U16_fake16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_NC_U16_fake16_e64 0, [[COPY2]], 0, [[COPY1]], 0, 0, implicit $exec
+  ; GISEL-GFX11-FAKE16-NEXT:   [[COPY3:%[0-9]+]]:vreg_64 = COPY [[DEF]]
+  ; GISEL-GFX11-FAKE16-NEXT:   FLAT_STORE_SHORT [[COPY3]], [[V_ADD_NC_U16_fake16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into `ptr poison`)
+  ; GISEL-GFX11-FAKE16-NEXT:   S_ENDPGM 0
   ;
   ; GISEL-GFX10-LABEL: name: amdgpu_cs_chain_preserve_cc_i16
   ; GISEL-GFX10: bb.1 (%ir-block.0):
@@ -988,29 +1046,55 @@ define amdgpu_cs_chain_preserve void @amdgpu_cs_chain_preserve_cc_i16(i16 inreg
   ; GISEL-GFX10-NEXT:   FLAT_STORE_SHORT [[COPY3]], [[V_ADD_NC_U16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into `ptr poison`)
   ; GISEL-GFX10-NEXT:   S_ENDPGM 0
   ;
-  ; DAGISEL-GFX11-WF32-LABEL: name: amdgpu_cs_chain_preserve_cc_i16
-  ; DAGISEL-GFX11-WF32: bb.0 (%ir-block.0):
-  ; DAGISEL-GFX11-WF32-NEXT:   liveins: $sgpr0, $vgpr8
-  ; DAGISEL-GFX11-WF32-NEXT: {{  $}}
-  ; DAGISEL-GFX11-WF32-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr8
-  ; DAGISEL-GFX11-WF32-NEXT:   [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
-  ; DAGISEL-GFX11-WF32-NEXT:   [[V_ADD_NC_U16_fake16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_NC_U16_fake16_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
-  ; DAGISEL-GFX11-WF32-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
-  ; DAGISEL-GFX11-WF32-NEXT:   [[COPY2:%[0-9]+]]:vreg_64 = COPY [[DEF]]
-  ; DAGISEL-GFX11-WF32-NEXT:   FLAT_STORE_SHORT killed [[COPY2]], killed [[V_ADD_NC_U16_fake16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into `ptr poison`)
-  ; DAGISEL-GFX11-WF32-NEXT:   S_ENDPGM 0
+  ; DAGISEL-GFX11-WF32-TRUE16-LABEL: name: amdgpu_cs_chain_preserve_cc_i16
+  ; DAGISEL-GFX11-WF32-TRUE16: bb.0 (%ir-block.0):
+  ; DAGISEL-GFX11-WF32-TRUE16-NEXT:   liveins: $sgpr0, $vgpr8
+  ; DAGISEL-GFX11-WF32-TRUE16-NEXT: {{  $}}
+  ; DAGISEL-GFX11-WF32-TRUE16-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr8
+  ; DAGISEL-GFX11-WF32-TRUE16-NEXT:   [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
+  ; DAGISEL-GFX11-WF32-TRUE16-NEXT:   [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY]]
+  ; DAGISEL-GFX11-WF32-TRUE16-NEXT:   [[V_ADD_NC_U16_t16_e64_:%[0-9]+]]:vgpr_16 = V_ADD_NC_U16_t16_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
+  ; DAGISEL-GFX11-WF32-TRUE16-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+  ; DAGISEL-GFX11-WF32-TRUE16-NEXT:   [[COPY3:%[0-9]+]]:vreg_64 = COPY [[DEF]]
+  ; DAGISEL-GFX11-WF32-TRUE16-NEXT:   FLAT_STORE_SHORT_t16 killed [[COPY3]], killed [[V_ADD_NC_U16_t16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into `ptr poison`)
+  ; DAGISEL-GFX11-WF32-TRUE16-NEXT:   S_ENDPGM 0
   ;
-  ; DAGISEL-GFX11-WF64-LABEL: name: amdgpu_cs_chain_preserve_cc_i16
-  ; DAGISEL-GFX11-WF64: bb.0 (%ir-block.0):
-  ; DAGISEL-GFX11-WF64-NEXT:   liveins: $sgpr0, $vgpr8
-  ; DAGISEL-GFX11-WF64-NEXT: {{  $}}
-  ; DAGISEL-GFX11-WF64-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr8
-  ; DAGISEL-GFX11-WF64-NEXT:   [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
-  ; DAGISEL-GFX11-WF64-NEXT:   [[V_ADD_NC_U16_fake16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_NC_U16_fake16_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
-  ; DAGISEL-GFX11-WF64-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
-  ; DAGISEL-GFX11-WF64-NEXT:   [[COPY2:%[0-9]+]]:vreg_64 = COPY [[DEF]]
-  ; DAGISEL-GFX11-WF64-NEXT:   FLAT_STORE_SHORT killed [[COPY2]], killed [[V_ADD_NC_U16_fake16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into `ptr poison`)
-  ; DAGISEL-GFX11-WF64-NEXT:   S_ENDPGM 0
+  ; DAGISEL-GFX11-WF32-FAKE16-LABEL: name: amdgpu_cs_chain_preserve_cc_i16
+  ; DAGISEL-GFX11-WF32-FAKE16: bb.0 (%ir-block.0):
+  ; DAGISEL-GFX11-WF32-FAKE16-NEXT:   liveins: $sgpr0, $vgpr8
+  ; DAGISEL-GFX11-WF32-FAKE16-NEXT: {{  $}}
+  ; DAGISEL-GFX11-WF32-FAKE16-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr8
+  ; DAGISEL-GFX11-WF32-FAKE16-NEXT:   [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
+  ; DAGISEL-GFX11-WF32-FAKE16-NEXT:   [[V_ADD_NC_U16_fake16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_NC_U16_fake16_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
+  ; DAGISEL-GFX11-WF32-FAKE16-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+  ; DAGISEL-GFX11-WF32-FAKE16-NEXT:   [[COPY2:%[0-9]+]]:vreg_64 = COPY [[DEF]]
+  ; DAGISEL-GFX11-WF32-FAKE16-NEXT:   FLAT_STORE_SHORT killed [[COPY2]], killed [[V_ADD_NC_U16_fake16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into `ptr poison`)
+  ; DAGISEL-GFX11-WF32-FAKE16-NEXT:   S_ENDPGM 0
+  ;
+  ; DAGISEL-GFX11-WF64-TRUE16-LABEL: name: amdgpu_cs_chain_preserve_cc_i16
+  ; DAGISEL-GFX11-WF64-TRUE16: bb.0 (%ir-block.0):
+  ; DAGISEL-GFX11-WF64-TRUE16-NEXT:   liveins: $sgpr0, $vgpr8
+  ; DAGISEL-GFX11-WF64-TRUE16-NEXT: {{  $}}
+  ; DAGISEL-GFX11-WF64-TRUE16-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr8
+  ; DAGISEL-GFX11-WF64-TRUE16-NEXT:   [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
+  ; DAGISEL-GFX11-WF64-TRUE16-NEXT:   [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY]]
+  ; DAGISEL-GFX11-WF64-TRUE16-NEXT:   [[V_ADD_NC_U16_t16_e64_:%[0-9]+]]:vgpr_16 = V_ADD_NC_U16_t16_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
+  ; DAGISEL-GFX11-WF64-TRUE16-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+  ; DAGISEL-GFX11-WF64-TRUE16-NEXT:   [[COPY3:%[0-9]+]]:vreg_64 = COPY [[DEF]]
+  ; DAGISEL-GFX11-WF64-TRUE16-NEXT:   FLAT_STORE_SHORT_t16 killed [[COPY3]], killed [[V_ADD_NC_U16_t16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into `ptr poison`)
+  ; DAGISEL-GFX11-WF64-TRUE16-NEXT:   S_ENDPGM 0
+  ;
+  ; DAGISEL-GFX11-WF64-FAKE16-LABEL: name: amdgpu_cs_chain_preserve_cc_i16
+  ; DAGISEL-GFX11-WF64-FAKE16: bb.0 (%ir-block.0):
+  ; DAGISEL-GFX11-WF64-FAKE16-NEXT:   liveins: $sgpr0, $vgpr8
+  ; DAGISEL-GFX11-WF64-FAKE16-NEXT: {{  $}}
+  ; DAGISEL-GFX11-WF64-FAKE16-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr8
+  ; DAGISEL-GFX11-WF64-FAKE16-NEXT:   [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
+  ; DAGISEL-GFX11-WF64-FAKE16-NEXT:   [[V_ADD_NC_U16_fake16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_NC_U16_fake16_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
+  ; DAGISEL-GFX11-WF64-FAKE16-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+  ; DAGISEL-GFX11-WF64-FAKE16-NEXT:   [[COPY2:%[0-9]+]]:vreg_64 = COPY [[DEF]]
+  ; DAGISEL-GFX11-WF64-FAKE16-NEXT:   FLAT_STORE_SHORT killed [[COPY2]], killed [[V_ADD_NC_U16_fake16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into `ptr poison`)
+  ; DAGISEL-GFX11-WF64-FAKE16-NEXT:   S_ENDPGM 0
   ;
   ; DAGISEL-GFX10-WF32-LABEL: name: amdgpu_cs_chain_preserve_cc_i16
   ; DAGISEL-GFX10-WF32: bb.0 (%ir-block.0):
diff --git a/llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll b/llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
index 77a76387d1049..0681263b7428e 100644
--- a/llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
+++ b/llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
@@ -92,5 +92,3 @@ declare void @device_func(ptr addrspace(5))
 
 attributes #0 = { nounwind "frame-pointer"="all" }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll b/llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
index 2f694def5396b..04abb75c3f912 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
+++ b/llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
@@ -696,5 +696,3 @@ define amdgpu_kernel void @module_1_kernel_overalign_indirect_extern_overalign(i
 
 attributes #0 = { noinline }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.wave32.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.wave32.ll
index fe69dc4906243..91aba09e942f0 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.wave32.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.wave32.ll
@@ -1,8 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgcn -global-isel=0 -mcpu=gfx1010 < %s | FileCheck %s --check-prefixes=CHECK,DAGISEL
-; RUN: llc -mtriple=amdgcn -global-isel=0 -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck %s --check-prefixes=CHECK,DAGISEL
+; RUN: llc -mtriple=amdgcn -global-isel=0 -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck %s --check-prefixes=CHECK,DAGISEL,DAGISEL-TRUE16
+; RUN: llc -mtriple=amdgcn -global-isel=0 -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck %s --check-prefixes=CHECK,DAGISEL,DAGISEL-FAKE16
 ; RUN: llc -mtriple=amdgcn -global-isel -mcpu=gfx1010 < %s | FileCheck %s --check-prefixes=CHECK,GISEL
-; RUN: llc -mtriple=amdgcn -global-isel -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck %s --check-prefixes=CHECK,GISEL
+; RUN: llc -mtriple=amdgcn -global-isel -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck %s --check-prefixes=CHECK,GISEL,GISEL-TRUE16
+; RUN: llc -mtriple=amdgcn -global-isel -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck %s --check-prefixes=CHECK,GISEL,GISEL-FAKE16
 
 declare i64 @llvm.amdgcn.ballot.i64(i1)
 declare i64 @llvm.ctpop.i64(i64)
@@ -47,13 +49,21 @@ define amdgpu_cs i64 @non_compare(i32 %x) {
 ; DAGISEL-NEXT:    v_cmp_ne_u32_e64 s0, 0, v0
 ; DAGISEL-NEXT:    ; return to shader part epilog
 ;
-; GISEL-LABEL: non_compare:
-; GISEL:       ; %bb.0:
-; GISEL-NEXT:    v_and_b32_e32 v0, 1, v0
-; GISEL-NEXT:    s_mov_b32 s1, 0
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GISEL-NEXT:    s_and_b32 s0, vcc_lo, exec_lo
-; GISEL-NEXT:    ; return to shader part epilog
+; GISEL-TRUE16-LABEL: non_compare:
+; GISEL-TRUE16:       ; %bb.0:
+; GISEL-TRUE16-NEXT:    v_and_b16 v0.l, 1, v0.l
+; GISEL-TRUE16-NEXT:    s_mov_b32 s1, 0
+; GISEL-TRUE16-NEXT:    v_cmp_ne_u16_e32 vcc_lo, 0, v0.l
+; GISEL-TRUE16-NEXT:    s_and_b32 s0, vcc_lo, exec_lo
+; GISEL-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GISEL-FAKE16-LABEL: non_compare:
+; GISEL-FAKE16:       ; %bb.0:
+; GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 1, v0
+; GISEL-FAKE16-NEXT:    s_mov_b32 s1, 0
+; GISEL-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GISEL-FAKE16-NEXT:    s_and_b32 s0, vcc_lo, exec_lo
+; GISEL-FAKE16-NEXT:    ; return to shader part epilog
   %trunc = trunc i32 %x to i1
   %ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %trunc)
   ret i64 %ballot
@@ -182,3 +192,6 @@ true:
 false:
   ret i32 33
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; DAGISEL-FAKE16: {{.*}}
+; DAGISEL-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
index a009854542f21..a6352134bad25 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefix=ASM-DAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefix=ASM-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=ASM-DAG %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=ASM-DAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=ASM-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=ASM-GISEL-FAKE16 %s
 
 ; Test that we can use v0 for temporaries in the if.then block.
 define i32 @dead(i1 %cond, i32 %x, ptr addrspace(1) %ptr1, ptr addrspace(1) %ptr2) #0 {
@@ -27,28 +29,51 @@ define i32 @dead(i1 %cond, i32 %x, ptr addrspace(1) %ptr1, ptr addrspace(1) %ptr
 ; ASM-DAG-NEXT:    s_or_b32 exec_lo, exec_lo, s0
 ; ASM-DAG-NEXT:    s_setpc_b64 s[30:31]
 ;
-; ASM-GISEL-LABEL: dead:
-; ASM-GISEL:       ; %bb.0: ; %entry
-; ASM-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
-; ASM-GISEL-NEXT:    s_wait_expcnt 0x0
-; ASM-GISEL-NEXT:    s_wait_samplecnt 0x0
-; ASM-GISEL-NEXT:    s_wait_bvhcnt 0x0
-; ASM-GISEL-NEXT:    s_wait_kmcnt 0x0
-; ASM-GISEL-NEXT:    v_mov_b32_e32 v4, v0
-; ASM-GISEL-NEXT:    v_mov_b32_e32 v0, v1
-; ASM-GISEL-NEXT:    s_mov_b32 s0, exec_lo
-; ASM-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; ASM-GISEL-NEXT:    v_and_b32_e32 v1, 1, v4
-; ASM-GISEL-NEXT:    v_cmpx_ne_u32_e32 0, v1
-; ASM-GISEL-NEXT:    s_cbranch_execz .LBB0_2
-; ASM-GISEL-NEXT:  ; %bb.1: ; %if.then
-; ASM-GISEL-NEXT:    v_add_nc_u32_e32 v0, 1, v0
-; ASM-GISEL-NEXT:    global_store_b32 v[2:3], v0, off
-; ASM-GISEL-NEXT:    ; implicit-def: $vgpr0
-; ASM-GISEL-NEXT:  .LBB0_2: ; %if.end
-; ASM-GISEL-NEXT:    s_wait_alu 0xfffe
-; ASM-GISEL-NEXT:    s_or_b32 exec_lo, exec_lo, s0
-; ASM-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; ASM-GISEL-TRUE16-LABEL: dead:
+; ASM-GISEL-TRUE16:       ; %bb.0: ; %entry
+; ASM-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; ASM-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; ASM-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; ASM-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; ASM-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; ASM-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v4, v0
+; ASM-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v0, v1
+; ASM-GISEL-TRUE16-NEXT:    s_mov_b32 s0, exec_lo
+; ASM-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; ASM-GISEL-TRUE16-NEXT:    v_and_b16 v1.l, 1, v4.l
+; ASM-GISEL-TRUE16-NEXT:    v_cmpx_ne_u16_e32 0, v1.l
+; ASM-GISEL-TRUE16-NEXT:    s_cbranch_execz .LBB0_2
+; ASM-GISEL-TRUE16-NEXT:  ; %bb.1: ; %if.then
+; ASM-GISEL-TRUE16-NEXT:    v_add_nc_u32_e32 v0, 1, v0
+; ASM-GISEL-TRUE16-NEXT:    global_store_b32 v[2:3], v0, off
+; ASM-GISEL-TRUE16-NEXT:    ; implicit-def: $vgpr0
+; ASM-GISEL-TRUE16-NEXT:  .LBB0_2: ; %if.end
+; ASM-GISEL-TRUE16-NEXT:    s_wait_alu 0xfffe
+; ASM-GISEL-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; ASM-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; ASM-GISEL-FAKE16-LABEL: dead:
+; ASM-GISEL-FAKE16:       ; %bb.0: ; %entry
+; ASM-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; ASM-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; ASM-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; ASM-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; ASM-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; ASM-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v4, v0
+; ASM-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v0, v1
+; ASM-GISEL-FAKE16-NEXT:    s_mov_b32 s0, exec_lo
+; ASM-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; ASM-GISEL-FAKE16-NEXT:    v_and_b32_e32 v1, 1, v4
+; ASM-GISEL-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v1
+; ASM-GISEL-FAKE16-NEXT:    s_cbranch_execz .LBB0_2
+; ASM-GISEL-FAKE16-NEXT:  ; %bb.1: ; %if.then
+; ASM-GISEL-FAKE16-NEXT:    v_add_nc_u32_e32 v0, 1, v0
+; ASM-GISEL-FAKE16-NEXT:    global_store_b32 v[2:3], v0, off
+; ASM-GISEL-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; ASM-GISEL-FAKE16-NEXT:  .LBB0_2: ; %if.end
+; ASM-GISEL-FAKE16-NEXT:    s_wait_alu 0xfffe
+; ASM-GISEL-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s0
+; ASM-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %dead = call i32 @llvm.amdgcn.dead.i32()
   br i1 %cond, label %if.then, label %if.end
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
index dea0cc5fd07b6..addb395eccf11 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
@@ -1,23 +1,38 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GFX11,SDAG-GFX11
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GFX11,SDAG-GFX11,SDAG-GFX11-TRUE16
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GFX11,SDAG-GFX11,SDAG-GFX11-FAKE16
 ; FIXME: GlobalIsel doesn't support BF16 for now.
-; xUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GFX11,GISEL-GFX11
+; xUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-TRUE16
+; xUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-FAKE16
 
 declare bfloat @llvm.amdgcn.fdot2.bf16.bf16(<2 x bfloat> %a, <2 x bfloat> %b, bfloat %c)
 
 define amdgpu_kernel void @test_llvm_amdgcn_fdot2_bf16_bf16(
-; GFX11-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u16 v1, v0, s[6:7]
-; GFX11-NEXT:    s_load_b32 s2, s[2:3], 0x0
-; GFX11-NEXT:    s_load_b32 s3, s[4:5], 0x0
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dot2_bf16_bf16 v1, s2, s3, v1
-; GFX11-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX11-NEXT:    s_endpgm
+; SDAG-GFX11-TRUE16-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16:
+; SDAG-GFX11-TRUE16:       ; %bb.0: ; %entry
+; SDAG-GFX11-TRUE16-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
+; SDAG-GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; SDAG-GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[6:7]
+; SDAG-GFX11-TRUE16-NEXT:    s_load_b32 s2, s[2:3], 0x0
+; SDAG-GFX11-TRUE16-NEXT:    s_load_b32 s3, s[4:5], 0x0
+; SDAG-GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; SDAG-GFX11-TRUE16-NEXT:    v_dot2_bf16_bf16 v0.l, s2, s3, v0.l
+; SDAG-GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; SDAG-GFX11-TRUE16-NEXT:    s_endpgm
+;
+; SDAG-GFX11-FAKE16-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16:
+; SDAG-GFX11-FAKE16:       ; %bb.0: ; %entry
+; SDAG-GFX11-FAKE16-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
+; SDAG-GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; SDAG-GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[6:7]
+; SDAG-GFX11-FAKE16-NEXT:    s_load_b32 s2, s[2:3], 0x0
+; SDAG-GFX11-FAKE16-NEXT:    s_load_b32 s3, s[4:5], 0x0
+; SDAG-GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; SDAG-GFX11-FAKE16-NEXT:    v_dot2_bf16_bf16 v1, s2, s3, v1
+; SDAG-GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; SDAG-GFX11-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b,
@@ -32,17 +47,32 @@ entry:
 }
 
 define amdgpu_kernel void @test_llvm_amdgcn_fdot2_bf16_bf16_dpp(
-; GFX11-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16_dpp:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    scratch_load_b32 v0, off, s2
-; GFX11-NEXT:    scratch_load_u16 v1, off, s3
-; GFX11-NEXT:    scratch_load_b32 v2, off, s1
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_dot2_bf16_bf16_e64_dpp v0, v2, v0, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX11-NEXT:    scratch_store_b16 off, v0, s0
-; GFX11-NEXT:    s_endpgm
+; SDAG-GFX11-TRUE16-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16_dpp:
+; SDAG-GFX11-TRUE16:       ; %bb.0: ; %entry
+; SDAG-GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; SDAG-GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX11-TRUE16-NEXT:    scratch_load_b32 v1, off, s1
+; SDAG-GFX11-TRUE16-NEXT:    scratch_load_b32 v2, off, s2
+; SDAG-GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v0, off, s3
+; SDAG-GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(2)
+; SDAG-GFX11-TRUE16-NEXT:    v_mov_b32_dpp v1, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
+; SDAG-GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; SDAG-GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX11-TRUE16-NEXT:    v_dot2_bf16_bf16 v0.l, v1, v2, v0.l
+; SDAG-GFX11-TRUE16-NEXT:    scratch_store_b16 off, v0, s0
+; SDAG-GFX11-TRUE16-NEXT:    s_endpgm
+;
+; SDAG-GFX11-FAKE16-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16_dpp:
+; SDAG-GFX11-FAKE16:       ; %bb.0: ; %entry
+; SDAG-GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; SDAG-GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX11-FAKE16-NEXT:    scratch_load_b32 v0, off, s2
+; SDAG-GFX11-FAKE16-NEXT:    scratch_load_u16 v1, off, s3
+; SDAG-GFX11-FAKE16-NEXT:    scratch_load_b32 v2, off, s1
+; SDAG-GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; SDAG-GFX11-FAKE16-NEXT:    v_dot2_bf16_bf16_e64_dpp v0, v2, v0, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
+; SDAG-GFX11-FAKE16-NEXT:    scratch_store_b16 off, v0, s0
+; SDAG-GFX11-FAKE16-NEXT:    s_endpgm
     ptr addrspace(5) %r,
     ptr addrspace(5) %a,
     ptr addrspace(5) %b,
@@ -62,13 +92,21 @@ entry:
 ; Make sure we do not violate constant bus restriction with 3 scalar inputs and simingly inlinable literal.
 
 define amdgpu_ps void @test_llvm_amdgcn_fdot2_bf16_bf16_sis(
-; GFX11-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16_sis:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    v_mov_b32_e32 v2, s1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_dot2_bf16_bf16 v2, s0, 0x3f803f80, v2
-; GFX11-NEXT:    global_store_b16 v[0:1], v2, off
-; GFX11-NEXT:    s_endpgm
+; SDAG-GFX11-TRUE16-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16_sis:
+; SDAG-GFX11-TRUE16:       ; %bb.0: ; %entry
+; SDAG-GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, s1
+; SDAG-GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX11-TRUE16-NEXT:    v_dot2_bf16_bf16 v2.l, s0, 0x3f803f80, v2.l
+; SDAG-GFX11-TRUE16-NEXT:    global_store_b16 v[0:1], v2, off
+; SDAG-GFX11-TRUE16-NEXT:    s_endpgm
+;
+; SDAG-GFX11-FAKE16-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16_sis:
+; SDAG-GFX11-FAKE16:       ; %bb.0: ; %entry
+; SDAG-GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, s1
+; SDAG-GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX11-FAKE16-NEXT:    v_dot2_bf16_bf16 v2, s0, 0x3f803f80, v2
+; SDAG-GFX11-FAKE16-NEXT:    global_store_b16 v[0:1], v2, off
+; SDAG-GFX11-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     <2 x bfloat> inreg %a,
     bfloat inreg %c) {
@@ -80,4 +118,5 @@ entry:
 
 declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1)
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11: {{.*}}
 ; SDAG-GFX11: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
index 066edea969883..19e03486d122d 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
@@ -1,22 +1,63 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GFX11,SDAG-GFX11
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GFX11,GISEL-GFX11
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GFX11,SDAG-GFX11,SDAG-GFX11-TRUE16
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GFX11,SDAG-GFX11,SDAG-GFX11-FAKE16
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-TRUE16
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-FAKE16
 
 declare half @llvm.amdgcn.fdot2.f16.f16(<2 x half> %a, <2 x half> %b, half %c)
 
 define amdgpu_kernel void @test_llvm_amdgcn_fdot2_f16_f16(
-; GFX11-LABEL: test_llvm_amdgcn_fdot2_f16_f16:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u16 v1, v0, s[6:7]
-; GFX11-NEXT:    s_load_b32 s2, s[2:3], 0x0
-; GFX11-NEXT:    s_load_b32 s3, s[4:5], 0x0
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_dot2_f16_f16 v1, s2, s3, v1
-; GFX11-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX11-NEXT:    s_endpgm
+; SDAG-GFX11-TRUE16-LABEL: test_llvm_amdgcn_fdot2_f16_f16:
+; SDAG-GFX11-TRUE16:       ; %bb.0: ; %entry
+; SDAG-GFX11-TRUE16-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
+; SDAG-GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; SDAG-GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[6:7]
+; SDAG-GFX11-TRUE16-NEXT:    s_load_b32 s2, s[2:3], 0x0
+; SDAG-GFX11-TRUE16-NEXT:    s_load_b32 s3, s[4:5], 0x0
+; SDAG-GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; SDAG-GFX11-TRUE16-NEXT:    v_dot2_f16_f16 v0.l, s2, s3, v0.l
+; SDAG-GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; SDAG-GFX11-TRUE16-NEXT:    s_endpgm
+;
+; SDAG-GFX11-FAKE16-LABEL: test_llvm_amdgcn_fdot2_f16_f16:
+; SDAG-GFX11-FAKE16:       ; %bb.0: ; %entry
+; SDAG-GFX11-FAKE16-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
+; SDAG-GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; SDAG-GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[6:7]
+; SDAG-GFX11-FAKE16-NEXT:    s_load_b32 s2, s[2:3], 0x0
+; SDAG-GFX11-FAKE16-NEXT:    s_load_b32 s3, s[4:5], 0x0
+; SDAG-GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; SDAG-GFX11-FAKE16-NEXT:    v_dot2_f16_f16 v1, s2, s3, v1
+; SDAG-GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; SDAG-GFX11-FAKE16-NEXT:    s_endpgm
+;
+; GISEL-GFX11-TRUE16-LABEL: test_llvm_amdgcn_fdot2_f16_f16:
+; GISEL-GFX11-TRUE16:       ; %bb.0: ; %entry
+; GISEL-GFX11-TRUE16-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
+; GISEL-GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GISEL-GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[6:7]
+; GISEL-GFX11-TRUE16-NEXT:    s_load_b32 s2, s[2:3], 0x0
+; GISEL-GFX11-TRUE16-NEXT:    s_load_b32 s3, s[4:5], 0x0
+; GISEL-GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GISEL-GFX11-TRUE16-NEXT:    v_dot2_f16_f16 v0.l, s2, s3, v0.l
+; GISEL-GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GISEL-GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GISEL-GFX11-FAKE16-LABEL: test_llvm_amdgcn_fdot2_f16_f16:
+; GISEL-GFX11-FAKE16:       ; %bb.0: ; %entry
+; GISEL-GFX11-FAKE16-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
+; GISEL-GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GISEL-GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[6:7]
+; GISEL-GFX11-FAKE16-NEXT:    s_load_b32 s2, s[2:3], 0x0
+; GISEL-GFX11-FAKE16-NEXT:    s_load_b32 s3, s[4:5], 0x0
+; GISEL-GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GISEL-GFX11-FAKE16-NEXT:    v_dot2_f16_f16 v1, s2, s3, v1
+; GISEL-GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GISEL-GFX11-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b,
@@ -31,29 +72,59 @@ entry:
 }
 
 define amdgpu_kernel void @test_llvm_amdgcn_fdot2_f16_f16_dpp(
-; SDAG-GFX11-LABEL: test_llvm_amdgcn_fdot2_f16_f16_dpp:
-; SDAG-GFX11:       ; %bb.0: ; %entry
-; SDAG-GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT:    scratch_load_b32 v0, off, s2
-; SDAG-GFX11-NEXT:    scratch_load_u16 v1, off, s3
-; SDAG-GFX11-NEXT:    scratch_load_b32 v2, off, s1
-; SDAG-GFX11-NEXT:    s_waitcnt vmcnt(0)
-; SDAG-GFX11-NEXT:    v_dot2_f16_f16_e64_dpp v0, v2, v0, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
-; SDAG-GFX11-NEXT:    scratch_store_b16 off, v0, s0
-; SDAG-GFX11-NEXT:    s_endpgm
+; SDAG-GFX11-TRUE16-LABEL: test_llvm_amdgcn_fdot2_f16_f16_dpp:
+; SDAG-GFX11-TRUE16:       ; %bb.0: ; %entry
+; SDAG-GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; SDAG-GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX11-TRUE16-NEXT:    scratch_load_b32 v1, off, s1
+; SDAG-GFX11-TRUE16-NEXT:    scratch_load_b32 v2, off, s2
+; SDAG-GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v0, off, s3
+; SDAG-GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(2)
+; SDAG-GFX11-TRUE16-NEXT:    v_mov_b32_dpp v1, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
+; SDAG-GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; SDAG-GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX11-TRUE16-NEXT:    v_dot2_f16_f16 v0.l, v1, v2, v0.l
+; SDAG-GFX11-TRUE16-NEXT:    scratch_store_b16 off, v0, s0
+; SDAG-GFX11-TRUE16-NEXT:    s_endpgm
+;
+; SDAG-GFX11-FAKE16-LABEL: test_llvm_amdgcn_fdot2_f16_f16_dpp:
+; SDAG-GFX11-FAKE16:       ; %bb.0: ; %entry
+; SDAG-GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; SDAG-GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX11-FAKE16-NEXT:    scratch_load_b32 v0, off, s2
+; SDAG-GFX11-FAKE16-NEXT:    scratch_load_u16 v1, off, s3
+; SDAG-GFX11-FAKE16-NEXT:    scratch_load_b32 v2, off, s1
+; SDAG-GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; SDAG-GFX11-FAKE16-NEXT:    v_dot2_f16_f16_e64_dpp v0, v2, v0, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
+; SDAG-GFX11-FAKE16-NEXT:    scratch_store_b16 off, v0, s0
+; SDAG-GFX11-FAKE16-NEXT:    s_endpgm
+;
+; GISEL-GFX11-TRUE16-LABEL: test_llvm_amdgcn_fdot2_f16_f16_dpp:
+; GISEL-GFX11-TRUE16:       ; %bb.0: ; %entry
+; GISEL-GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GISEL-GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX11-TRUE16-NEXT:    scratch_load_b32 v1, off, s1
+; GISEL-GFX11-TRUE16-NEXT:    scratch_load_b32 v2, off, s2
+; GISEL-GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v0, off, s3
+; GISEL-GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(2)
+; GISEL-GFX11-TRUE16-NEXT:    v_mov_b32_dpp v1, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GISEL-GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GISEL-GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX11-TRUE16-NEXT:    v_dot2_f16_f16 v0.l, v1, v2, v0.l
+; GISEL-GFX11-TRUE16-NEXT:    scratch_store_b16 off, v0, s0
+; GISEL-GFX11-TRUE16-NEXT:    s_endpgm
 ;
-; GISEL-GFX11-LABEL: test_llvm_amdgcn_fdot2_f16_f16_dpp:
-; GISEL-GFX11:       ; %bb.0: ; %entry
-; GISEL-GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT:    scratch_load_b32 v0, off, s1
-; GISEL-GFX11-NEXT:    scratch_load_b32 v1, off, s2
-; GISEL-GFX11-NEXT:    scratch_load_u16 v2, off, s3
-; GISEL-GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GISEL-GFX11-NEXT:    v_dot2_f16_f16_e64_dpp v0, v0, v1, v2 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GISEL-GFX11-NEXT:    scratch_store_b16 off, v0, s0
-; GISEL-GFX11-NEXT:    s_endpgm
+; GISEL-GFX11-FAKE16-LABEL: test_llvm_amdgcn_fdot2_f16_f16_dpp:
+; GISEL-GFX11-FAKE16:       ; %bb.0: ; %entry
+; GISEL-GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GISEL-GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX11-FAKE16-NEXT:    scratch_load_b32 v0, off, s1
+; GISEL-GFX11-FAKE16-NEXT:    scratch_load_b32 v1, off, s2
+; GISEL-GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s3
+; GISEL-GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GISEL-GFX11-FAKE16-NEXT:    v_dot2_f16_f16_e64_dpp v0, v0, v1, v2 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GISEL-GFX11-FAKE16-NEXT:    scratch_store_b16 off, v0, s0
+; GISEL-GFX11-FAKE16-NEXT:    s_endpgm
     ptr addrspace(5) %r,
     ptr addrspace(5) %a,
     ptr addrspace(5) %b,
@@ -71,3 +142,7 @@ entry:
 }
 
 declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11: {{.*}}
+; GISEL-GFX11: {{.*}}
+; SDAG-GFX11: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.AFLCustomIRMutator.opt.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.AFLCustomIRMutator.opt.ll
new file mode 100644
index 0000000000000..a319f1260d870
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.AFLCustomIRMutator.opt.ll
@@ -0,0 +1,43 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -O1 < %s | FileCheck -check-prefix=GCN %s
+
+define amdgpu_kernel void @test_iglp_opt_rev_mfma_gemm(<1 x i64> %L1) {
+; GCN-LABEL: test_iglp_opt_rev_mfma_gemm:
+; GCN:       ; %bb.0: ; %entry
+; GCN-NEXT:    v_mov_b32_e32 v32, 0
+; GCN-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x0
+; GCN-NEXT:    ds_read_b128 v[28:31], v32 offset:112
+; GCN-NEXT:    ds_read_b128 v[24:27], v32 offset:96
+; GCN-NEXT:    ds_read_b128 v[20:23], v32 offset:80
+; GCN-NEXT:    ds_read_b128 v[16:19], v32 offset:64
+; GCN-NEXT:    ds_read_b128 v[0:3], v32
+; GCN-NEXT:    ds_read_b128 v[4:7], v32 offset:16
+; GCN-NEXT:    ds_read_b128 v[8:11], v32 offset:32
+; GCN-NEXT:    ds_read_b128 v[12:15], v32 offset:48
+; GCN-NEXT:    v_mov_b32_e32 v34, 0
+; GCN-NEXT:    v_mov_b32_e32 v35, v34
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    s_cmp_lg_u64 s[0:1], 0
+; GCN-NEXT:    ; iglp_opt mask(0x00000001)
+; GCN-NEXT:    ds_write_b128 v32, v[28:31] offset:112
+; GCN-NEXT:    ds_write_b128 v32, v[24:27] offset:96
+; GCN-NEXT:    ds_write_b128 v32, v[20:23] offset:80
+; GCN-NEXT:    ds_write_b128 v32, v[16:19] offset:64
+; GCN-NEXT:    ds_write_b128 v32, v[12:15] offset:48
+; GCN-NEXT:    ds_write_b128 v32, v[8:11] offset:32
+; GCN-NEXT:    ds_write_b128 v32, v[4:7] offset:16
+; GCN-NEXT:    ds_write_b128 v32, v[0:3]
+; GCN-NEXT:    ds_write_b64 v32, v[34:35]
+; GCN-NEXT:    s_endpgm
+entry:
+  call void @llvm.amdgcn.iglp.opt(i32 1)
+  %load.4 = load <32 x float>, ptr addrspace(3) null, align 128
+  %B = urem <1 x i64> zeroinitializer, %L1
+  store <32 x float> %load.4, ptr addrspace(3) null, align 128
+  store <1 x i64> %B, ptr addrspace(3) null, align 8
+  ret void
+}
+
+declare void @llvm.amdgcn.iglp.opt(i32 immarg) #0
+
+attributes #0 = { convergent nocallback nofree nounwind willreturn }
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
index 40b4b33e74a6f..93f0080deabe7 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
@@ -1,8 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-delay-alu=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
 
 define amdgpu_ps <4 x float> @gather4_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t) {
 ; GFX9-LABEL: gather4_2d:
@@ -16,25 +18,45 @@ define amdgpu_ps <4 x float> @gather4_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: gather4_2d:
-; GFX10:       ; %bb.0: ; %main_body
-; GFX10-NEXT:    s_mov_b32 s12, exec_lo
-; GFX10-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX10-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX10-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX10-NEXT:    image_gather4 v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: gather4_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s12, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT:    image_gather4 v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT:    image_gather4 v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-FAKE16-NEXT:    image_gather4 v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-TRUE16-NEXT:    image_gather4 v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-FAKE16-NEXT:    image_gather4 v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f16(i32 1, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -52,25 +74,47 @@ define amdgpu_ps <4 x float> @gather4_cube(<8 x i32> inreg %rsrc, <4 x i32> inre
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: gather4_cube:
-; GFX10:       ; %bb.0: ; %main_body
-; GFX10-NEXT:    s_mov_b32 s12, exec_lo
-; GFX10-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX10-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX10-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX10-NEXT:    image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: gather4_cube:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s12, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT:    image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_cube:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v1.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT:    image_gather4 v[0:3], v[2:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_cube:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-FAKE16-NEXT:    image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_cube:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-TRUE16-NEXT:    image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_cube:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-FAKE16-NEXT:    image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.cube.v4f32.f16(i32 1, half %s, half %t, half %face, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -88,25 +132,47 @@ define amdgpu_ps <4 x float> @gather4_2darray(<8 x i32> inreg %rsrc, <4 x i32> i
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: gather4_2darray:
-; GFX10:       ; %bb.0: ; %main_body
-; GFX10-NEXT:    s_mov_b32 s12, exec_lo
-; GFX10-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX10-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX10-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX10-NEXT:    image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY a16
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: gather4_2darray:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s12, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT:    image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_2darray:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v1.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT:    image_gather4 v[0:3], v[2:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_2darray:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-FAKE16-NEXT:    image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_2darray:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-TRUE16-NEXT:    image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_2darray:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-FAKE16-NEXT:    image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.2darray.v4f32.f16(i32 1, half %s, half %t, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -124,25 +190,45 @@ define amdgpu_ps <4 x float> @gather4_c_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: gather4_c_2d:
-; GFX10:       ; %bb.0: ; %main_body
-; GFX10-NEXT:    s_mov_b32 s12, exec_lo
-; GFX10-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX10-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX10-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX10-NEXT:    image_gather4_c v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: gather4_c_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s12, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT:    image_gather4_c v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_c_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT:    image_gather4_c v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_c_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-FAKE16-NEXT:    image_gather4_c v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_c_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-TRUE16-NEXT:    image_gather4_c v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_c_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-FAKE16-NEXT:    image_gather4_c v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.c.2d.v4f32.f32(i32 1, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -160,25 +246,47 @@ define amdgpu_ps <4 x float> @gather4_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: gather4_cl_2d:
-; GFX10:       ; %bb.0: ; %main_body
-; GFX10-NEXT:    s_mov_b32 s12, exec_lo
-; GFX10-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX10-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX10-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX10-NEXT:    image_gather4_cl v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: gather4_cl_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s12, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT:    image_gather4_cl v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_cl_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v1.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT:    image_gather4_cl v[0:3], v[2:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_cl_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-FAKE16-NEXT:    image_gather4_cl v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_cl_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-TRUE16-NEXT:    image_gather4_cl v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_cl_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-FAKE16-NEXT:    image_gather4_cl v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.cl.2d.v4f32.f16(i32 1, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -198,25 +306,45 @@ define amdgpu_ps <4 x float> @gather4_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: gather4_c_cl_2d:
-; GFX10:       ; %bb.0: ; %main_body
-; GFX10-NEXT:    s_mov_b32 s12, exec_lo
-; GFX10-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX10-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX10-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX10-NEXT:    image_gather4_c_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: gather4_c_cl_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s12, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT:    image_gather4_c_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_c_cl_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT:    image_gather4_c_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_c_cl_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-FAKE16-NEXT:    image_gather4_c_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_c_cl_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-TRUE16-NEXT:    image_gather4_c_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_c_cl_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-FAKE16-NEXT:    image_gather4_c_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.c.cl.2d.v4f32.f32(i32 1, float %zcompare, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -234,25 +362,45 @@ define amdgpu_ps <4 x float> @gather4_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: gather4_b_2d:
-; GFX10:       ; %bb.0: ; %main_body
-; GFX10-NEXT:    s_mov_b32 s12, exec_lo
-; GFX10-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX10-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX10-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX10-NEXT:    image_gather4_b v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: gather4_b_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s12, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT:    image_gather4_b v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_b_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT:    image_gather4_b v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_b_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-FAKE16-NEXT:    image_gather4_b v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_b_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-TRUE16-NEXT:    image_gather4_b v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_b_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-FAKE16-NEXT:    image_gather4_b v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.b.2d.v4f32.f16.f16(i32 1, half %bias, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -270,25 +418,45 @@ define amdgpu_ps <4 x float> @gather4_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> in
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: gather4_c_b_2d:
-; GFX10:       ; %bb.0: ; %main_body
-; GFX10-NEXT:    s_mov_b32 s12, exec_lo
-; GFX10-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX10-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX10-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX10-NEXT:    image_gather4_c_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: gather4_c_b_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s12, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT:    image_gather4_c_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_c_b_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT:    image_gather4_c_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_c_b_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-FAKE16-NEXT:    image_gather4_c_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_c_b_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-TRUE16-NEXT:    image_gather4_c_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_c_b_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-FAKE16-NEXT:    image_gather4_c_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.2d.v4f32.f16.f16(i32 1, half %bias, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -308,25 +476,48 @@ define amdgpu_ps <4 x float> @gather4_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: gather4_b_cl_2d:
-; GFX10:       ; %bb.0: ; %main_body
-; GFX10-NEXT:    s_mov_b32 s12, exec_lo
-; GFX10-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX10-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX10-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX10-NEXT:    image_gather4_b_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: gather4_b_cl_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s12, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT:    image_gather4_b_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_b_cl_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT:    image_gather4_b_cl v[0:3], v[2:4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_b_cl_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-FAKE16-NEXT:    image_gather4_b_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_b_cl_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-TRUE16-NEXT:    image_gather4_b_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_b_cl_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-FAKE16-NEXT:    image_gather4_b_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.b.cl.2d.v4f32.f16.f16(i32 1, half %bias, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -347,25 +538,45 @@ define amdgpu_ps <4 x float> @gather4_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: gather4_c_b_cl_2d:
-; GFX10:       ; %bb.0: ; %main_body
-; GFX10-NEXT:    s_mov_b32 s12, exec_lo
-; GFX10-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX10-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX10-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX10-NEXT:    image_gather4_c_b_cl v[0:3], [v0, v1, v2, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: gather4_c_b_cl_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s12, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT:    image_gather4_c_b_cl v[0:3], [v0, v1, v2, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_c_b_cl_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT:    image_gather4_c_b_cl v[0:3], [v0, v1, v2, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_c_b_cl_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-FAKE16-NEXT:    image_gather4_c_b_cl v[0:3], [v0, v1, v2, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_c_b_cl_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-TRUE16-NEXT:    image_gather4_c_b_cl v[0:3], [v0, v1, v2, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_c_b_cl_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-FAKE16-NEXT:    image_gather4_c_b_cl v[0:3], [v0, v1, v2, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.2d.v4f32.f16.f16(i32 1, half %bias, float %zcompare, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -380,19 +591,35 @@ define amdgpu_ps <4 x float> @gather4_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: gather4_l_2d:
-; GFX10:       ; %bb.0: ; %main_body
-; GFX10-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX10-NEXT:    image_gather4_l v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: gather4_l_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-NEXT:    image_gather4_l v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_l_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v1.l
+; GFX11-TRUE16-NEXT:    image_gather4_l v[0:3], v[2:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_l_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    image_gather4_l v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_l_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    image_gather4_l v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_l_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    image_gather4_l v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.l.2d.v4f32.f16(i32 1, half %s, half %t, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -409,19 +636,33 @@ define amdgpu_ps <4 x float> @gather4_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> in
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: gather4_c_l_2d:
-; GFX10:       ; %bb.0: ; %main_body
-; GFX10-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX10-NEXT:    image_gather4_c_l v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: gather4_c_l_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-NEXT:    image_gather4_c_l v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_c_l_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    image_gather4_c_l v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_c_l_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    image_gather4_c_l v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_c_l_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    image_gather4_c_l v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_c_l_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-FAKE16-NEXT:    image_gather4_c_l v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.2d.v4f32.f32(i32 1, float %zcompare, half %s, half %t, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -436,19 +677,33 @@ define amdgpu_ps <4 x float> @gather4_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: gather4_lz_2d:
-; GFX10:       ; %bb.0: ; %main_body
-; GFX10-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX10-NEXT:    image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: gather4_lz_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-NEXT:    image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_lz_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_lz_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_lz_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_lz_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f16(i32 1, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -463,19 +718,33 @@ define amdgpu_ps <4 x float> @gather4_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> i
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: gather4_c_lz_2d:
-; GFX10:       ; %bb.0: ; %main_body
-; GFX10-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX10-NEXT:    image_gather4_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: gather4_c_lz_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-NEXT:    image_gather4_c_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: gather4_c_lz_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    image_gather4_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: gather4_c_lz_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    image_gather4_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: gather4_c_lz_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    image_gather4_c_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: gather4_c_lz_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-FAKE16-NEXT:    image_gather4_c_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.gather4.c.lz.2d.v4f32.f32(i32 1, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -503,3 +772,6 @@ declare <4 x float> @llvm.amdgcn.image.gather4.c.lz.2d.v4f32.f32(i32, float, hal
 attributes #0 = { nounwind }
 attributes #1 = { nounwind readonly }
 attributes #2 = { nounwind readnone }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX10: {{.*}}
+; GFX12: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
index e789b964d3cf1..f188d37c904ff 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=GCN,GFX11 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=GCN,GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=GCN,GFX12,GFX12-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=GCN,GFX12,GFX12-FAKE16 %s
 
 define amdgpu_ps <4 x float> @load_2dmsaa(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %fragid) {
 ; GFX11-LABEL: load_2dmsaa:
@@ -281,40 +283,74 @@ main_body:
 }
 
 define amdgpu_ps <4 x float> @load_2dmsaa_a16(<8 x i32> inreg %rsrc, i16 %s, i16 %t, i16 %fragid) {
-; GFX11-LABEL: load_2dmsaa_a16:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100 ; encoding: [0x00,0x00,0x44,0xd6,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX11-NEXT:    image_msaa_load v[0:3], [v0, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16 ; encoding: [0x99,0x01,0x61,0xf0,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00]
-; GFX11-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: load_2dmsaa_a16:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v2.l ; encoding: [0x02,0x39,0x06,0x7e]
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l ; encoding: [0x00,0x39,0x04,0x7e]
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v1.l ; encoding: [0x01,0x39,0x04,0x7f]
+; GFX11-TRUE16-NEXT:    image_msaa_load v[0:3], v[2:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16 ; encoding: [0x98,0x01,0x61,0xf0,0x02,0x00,0x00,0x00]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: load_2dmsaa_a16:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100 ; encoding: [0x00,0x00,0x44,0xd6,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX12-NEXT:    image_msaa_load v[0:3], [v0, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16 ; encoding: [0x46,0x20,0x46,0xe4,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00]
-; GFX12-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-FAKE16-LABEL: load_2dmsaa_a16:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100 ; encoding: [0x00,0x00,0x44,0xd6,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX11-FAKE16-NEXT:    image_msaa_load v[0:3], [v0, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16 ; encoding: [0x99,0x01,0x61,0xf0,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: load_2dmsaa_a16:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l ; encoding: [0x01,0x39,0x00,0x7f]
+; GFX12-TRUE16-NEXT:    image_msaa_load v[0:3], [v0, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16 ; encoding: [0x46,0x20,0x46,0xe4,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00]
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: load_2dmsaa_a16:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100 ; encoding: [0x00,0x00,0x44,0xd6,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX12-FAKE16-NEXT:    image_msaa_load v[0:3], [v0, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16 ; encoding: [0x46,0x20,0x46,0xe4,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00]
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.msaa.load.2dmsaa.v4f32.i16(i32 1, i16 %s, i16 %t, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
   ret <4 x float> %v
 }
 
 define amdgpu_ps <4 x float> @load_2darraymsaa_a16(<8 x i32> inreg %rsrc, i16 %s, i16 %t, i16 %slice, i16 %fragid) {
-; GFX11-LABEL: load_2darraymsaa_a16:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100 ; encoding: [0x02,0x00,0x44,0xd6,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX11-NEXT:    v_perm_b32 v1, v1, v0, 0x5040100 ; encoding: [0x01,0x00,0x44,0xd6,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX11-NEXT:    image_msaa_load v[0:3], v[1:2], s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 ; encoding: [0x9c,0x04,0x61,0xf0,0x01,0x00,0x00,0x00]
-; GFX11-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: load_2darraymsaa_a16:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v2.l ; encoding: [0x02,0x39,0x08,0x7e]
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v3.l ; encoding: [0x03,0x39,0x08,0x7f]
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l ; encoding: [0x00,0x39,0x06,0x7e]
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v1.l ; encoding: [0x01,0x39,0x06,0x7f]
+; GFX11-TRUE16-NEXT:    image_msaa_load v[0:3], v[3:4], s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 ; encoding: [0x9c,0x04,0x61,0xf0,0x03,0x00,0x00,0x00]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: load_2darraymsaa_a16:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100 ; encoding: [0x02,0x00,0x44,0xd6,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100 ; encoding: [0x00,0x00,0x44,0xd6,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX12-NEXT:    image_msaa_load v[0:3], [v0, v2], s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 ; encoding: [0x47,0x20,0x06,0xe5,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00]
-; GFX12-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-FAKE16-LABEL: load_2darraymsaa_a16:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100 ; encoding: [0x02,0x00,0x44,0xd6,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v0, 0x5040100 ; encoding: [0x01,0x00,0x44,0xd6,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX11-FAKE16-NEXT:    image_msaa_load v[0:3], v[1:2], s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 ; encoding: [0x9c,0x04,0x61,0xf0,0x01,0x00,0x00,0x00]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: load_2darraymsaa_a16:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l ; encoding: [0x03,0x39,0x04,0x7f]
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l ; encoding: [0x01,0x39,0x00,0x7f]
+; GFX12-TRUE16-NEXT:    image_msaa_load v[0:3], [v0, v2], s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 ; encoding: [0x47,0x20,0x06,0xe5,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00]
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: load_2darraymsaa_a16:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100 ; encoding: [0x02,0x00,0x44,0xd6,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100 ; encoding: [0x00,0x00,0x44,0xd6,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX12-FAKE16-NEXT:    image_msaa_load v[0:3], [v0, v2], s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 ; encoding: [0x47,0x20,0x06,0xe5,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00]
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.msaa.load.2darraymsaa.v4f32.i16(i32 4, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
   ret <4 x float> %v
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
index 10a85aa7c02c7..4a58091a14617 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
@@ -1,8 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
 
 define amdgpu_ps <4 x float> @sample_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s) {
 ; GFX9-LABEL: sample_1d:
@@ -67,25 +69,45 @@ define amdgpu_ps <4 x float> @sample_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    s_mov_b32 s12, exec_lo
-; GFX11-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX11-NEXT:    image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s12, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT:    image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT:    image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-FAKE16-NEXT:    image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-TRUE16-NEXT:    image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-FAKE16-NEXT:    image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f16(i32 15, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -113,25 +135,47 @@ define amdgpu_ps <4 x float> @sample_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_3d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    s_mov_b32 s12, exec_lo
-; GFX11-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX11-NEXT:    image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_3d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s12, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT:    image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_3d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v1.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT:    image_sample v[0:3], v[2:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_3d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-FAKE16-NEXT:    image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_3d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-TRUE16-NEXT:    image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_3d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-FAKE16-NEXT:    image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f16(i32 15, half %s, half %t, half %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -159,25 +203,47 @@ define amdgpu_ps <4 x float> @sample_cube(<8 x i32> inreg %rsrc, <4 x i32> inreg
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_cube:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    s_mov_b32 s12, exec_lo
-; GFX11-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX11-NEXT:    image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_cube:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s12, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT:    image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_cube:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v1.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT:    image_sample v[0:3], v[2:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_cube:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-FAKE16-NEXT:    image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_cube:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-TRUE16-NEXT:    image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_cube:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-FAKE16-NEXT:    image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.cube.v4f32.f16(i32 15, half %s, half %t, half %face, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -205,25 +271,45 @@ define amdgpu_ps <4 x float> @sample_1darray(<8 x i32> inreg %rsrc, <4 x i32> in
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_1darray:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    s_mov_b32 s12, exec_lo
-; GFX11-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX11-NEXT:    image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_1darray:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s12, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT:    image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_1darray:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT:    image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_1darray:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-FAKE16-NEXT:    image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_1darray:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-TRUE16-NEXT:    image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_1darray:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-FAKE16-NEXT:    image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.1darray.v4f32.f16(i32 15, half %s, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -251,25 +337,47 @@ define amdgpu_ps <4 x float> @sample_2darray(<8 x i32> inreg %rsrc, <4 x i32> in
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_2darray:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    s_mov_b32 s12, exec_lo
-; GFX11-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX11-NEXT:    image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_2darray:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s12, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT:    image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_2darray:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v1.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT:    image_sample v[0:3], v[2:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_2darray:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-FAKE16-NEXT:    image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_2darray:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-TRUE16-NEXT:    image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_2darray:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-FAKE16-NEXT:    image_sample v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.2darray.v4f32.f16(i32 15, half %s, half %t, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -338,25 +446,45 @@ define amdgpu_ps <4 x float> @sample_c_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    s_mov_b32 s12, exec_lo
-; GFX11-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX11-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX11-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX11-NEXT:    image_sample_c v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_c_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s12, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT:    image_sample_c v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT:    image_sample_c v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_c_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-FAKE16-NEXT:    image_sample_c v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-TRUE16-NEXT:    image_sample_c v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-FAKE16-NEXT:    image_sample_c v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.c.2d.v4f32.f16(i32 15, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -384,25 +512,45 @@ define amdgpu_ps <4 x float> @sample_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_cl_1d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    s_mov_b32 s12, exec_lo
-; GFX11-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX11-NEXT:    image_sample_cl v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_cl_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s12, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT:    image_sample_cl v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_cl_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT:    image_sample_cl v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_cl_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-FAKE16-NEXT:    image_sample_cl v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_cl_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-TRUE16-NEXT:    image_sample_cl v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_cl_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-FAKE16-NEXT:    image_sample_cl v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.cl.1d.v4f32.f16(i32 15, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -430,25 +578,47 @@ define amdgpu_ps <4 x float> @sample_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_cl_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    s_mov_b32 s12, exec_lo
-; GFX11-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX11-NEXT:    image_sample_cl v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_cl_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s12, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT:    image_sample_cl v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_cl_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v1.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT:    image_sample_cl v[0:3], v[2:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_cl_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-FAKE16-NEXT:    image_sample_cl v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_cl_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-TRUE16-NEXT:    image_sample_cl v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_cl_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-FAKE16-NEXT:    image_sample_cl v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.cl.2d.v4f32.f16(i32 15, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -476,25 +646,45 @@ define amdgpu_ps <4 x float> @sample_c_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_cl_1d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    s_mov_b32 s12, exec_lo
-; GFX11-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX11-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX11-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX11-NEXT:    image_sample_c_cl v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_c_cl_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s12, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT:    image_sample_c_cl v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_cl_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT:    image_sample_c_cl v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_c_cl_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-FAKE16-NEXT:    image_sample_c_cl v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_cl_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-TRUE16-NEXT:    image_sample_c_cl v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_cl_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-FAKE16-NEXT:    image_sample_c_cl v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.c.cl.1d.v4f32.f16(i32 15, float %zcompare, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -524,25 +714,45 @@ define amdgpu_ps <4 x float> @sample_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_cl_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    s_mov_b32 s12, exec_lo
-; GFX11-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX11-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX11-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX11-NEXT:    image_sample_c_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_c_cl_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s12, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT:    image_sample_c_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_cl_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT:    image_sample_c_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_c_cl_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-FAKE16-NEXT:    image_sample_c_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_cl_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-TRUE16-NEXT:    image_sample_c_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_cl_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-FAKE16-NEXT:    image_sample_c_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.c.cl.2d.v4f32.f16(i32 15, float %zcompare, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -611,25 +821,45 @@ define amdgpu_ps <4 x float> @sample_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_b_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    s_mov_b32 s12, exec_lo
-; GFX11-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX11-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX11-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX11-NEXT:    image_sample_b v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_b_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s12, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT:    image_sample_b v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_b_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT:    image_sample_b v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_b_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-FAKE16-NEXT:    image_sample_b v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_b_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-TRUE16-NEXT:    image_sample_b v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_b_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-FAKE16-NEXT:    image_sample_b v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.b.2d.v4f32.f16.f16(i32 15, half %bias, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -698,25 +928,45 @@ define amdgpu_ps <4 x float> @sample_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_b_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    s_mov_b32 s12, exec_lo
-; GFX11-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX11-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX11-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX11-NEXT:    image_sample_c_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_c_b_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s12, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT:    image_sample_c_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_b_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT:    image_sample_c_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_c_b_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-FAKE16-NEXT:    image_sample_c_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_b_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-TRUE16-NEXT:    image_sample_c_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_b_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-FAKE16-NEXT:    image_sample_c_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.c.b.2d.v4f32.f16.f16(i32 15, half %bias, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -744,25 +994,45 @@ define amdgpu_ps <4 x float> @sample_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_b_cl_1d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    s_mov_b32 s12, exec_lo
-; GFX11-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX11-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX11-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX11-NEXT:    image_sample_b_cl v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_b_cl_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s12, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT:    image_sample_b_cl v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_b_cl_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT:    image_sample_b_cl v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_b_cl_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-FAKE16-NEXT:    image_sample_b_cl v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_b_cl_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-TRUE16-NEXT:    image_sample_b_cl v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_b_cl_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-FAKE16-NEXT:    image_sample_b_cl v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.b.cl.1d.v4f32.f16.f16(i32 15, half %bias, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -792,25 +1062,48 @@ define amdgpu_ps <4 x float> @sample_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_b_cl_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    s_mov_b32 s12, exec_lo
-; GFX11-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX11-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX11-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX11-NEXT:    image_sample_b_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_b_cl_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s12, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT:    image_sample_b_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_b_cl_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT:    image_sample_b_cl v[0:3], v[2:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_b_cl_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-FAKE16-NEXT:    image_sample_b_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_b_cl_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-TRUE16-NEXT:    image_sample_b_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_b_cl_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-FAKE16-NEXT:    image_sample_b_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.b.cl.2d.v4f32.f16.f16(i32 15, half %bias, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -838,25 +1131,45 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_b_cl_1d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    s_mov_b32 s12, exec_lo
-; GFX11-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX11-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX11-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX11-NEXT:    image_sample_c_b_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_c_b_cl_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s12, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT:    image_sample_c_b_cl v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_b_cl_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT:    image_sample_c_b_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_c_b_cl_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-FAKE16-NEXT:    image_sample_c_b_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_b_cl_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-TRUE16-NEXT:    image_sample_c_b_cl v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_b_cl_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-FAKE16-NEXT:    image_sample_c_b_cl v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.1d.v4f32.f16.f16(i32 15, half %bias, float %zcompare, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -887,25 +1200,45 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_b_cl_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    s_mov_b32 s12, exec_lo
-; GFX11-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX11-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX11-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX11-NEXT:    image_sample_c_b_cl v[0:3], [v0, v1, v2, v4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_c_b_cl_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s12, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s12
-; GFX12-NEXT:    image_sample_c_b_cl v[0:3], [v0, v1, v2, v4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_b_cl_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-TRUE16-NEXT:    image_sample_c_b_cl v[0:3], [v0, v1, v2, v4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_c_b_cl_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX11-FAKE16-NEXT:    image_sample_c_b_cl v[0:3], [v0, v1, v2, v4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_b_cl_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-TRUE16-NEXT:    image_sample_c_b_cl v[0:3], [v0, v1, v2, v4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_b_cl_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s12, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s12
+; GFX12-FAKE16-NEXT:    image_sample_c_b_cl v[0:3], [v0, v1, v2, v4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.2d.v4f32.f16.f16(i32 15, half %bias, float %zcompare, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -960,23 +1293,44 @@ define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_d_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v4, v5, v4, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v3, v3, v2, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v2, v1, v0, 0x5040100
-; GFX11-NEXT:    image_sample_d_g16 v[0:3], v[2:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_d_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v4, v5, v4, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_d_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v5.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v0.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v1.l
+; GFX11-TRUE16-NEXT:    image_sample_d_g16 v[0:3], v[4:6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_d_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v5, v4, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    image_sample_d_g16 v[0:3], v[2:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_d_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v5.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_d_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v4, v5, v4, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f16.f16(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -1008,25 +1362,48 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_d_3d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v7, v7, v6, 0x5040100
-; GFX11-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v3, v5, v[7:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_d_3d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_mov_b32_e32 v10, v8
-; GFX12-NEXT:    v_mov_b32_e32 v8, v5
-; GFX12-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v9, v7, v6, 0x5040100
-; GFX12-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v3, v[8:10]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_d_3d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.h, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v3, v5, v[8:9]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_d_3d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v6, 0x5040100
+; GFX11-FAKE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v3, v5, v[7:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_d_3d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v8.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v6.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v8.h, v7.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v5.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v3, v[7:9]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_d_3d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v10, v8
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v8, v5
+; GFX12-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v9, v7, v6, 0x5040100
+; GFX12-FAKE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v3, v[8:10]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f16.f16(i32 15, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, half %s, half %t, half %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -1083,23 +1460,41 @@ define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_d_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v5, v6, v5, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX11-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_c_d_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v5, v6, v5, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_d_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_c_d_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v6, v5, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_d_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v6.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_d_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v5, v6, v5, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-FAKE16-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f32.f16(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -1121,19 +1516,33 @@ define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_d_cl_1d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX11-NEXT:    image_sample_d_cl_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_d_cl_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_d_cl_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    image_sample_d_cl_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_d_cl_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    image_sample_d_cl_g16 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_d_cl_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_d_cl_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12-FAKE16-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f16.f16(i32 15, half %dsdh, half %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -1159,23 +1568,45 @@ define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_d_cl_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v4, v5, v4, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_d_cl_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v4, v5, v4, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_d_cl_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v5.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v0.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v1.l
+; GFX11-TRUE16-NEXT:    image_sample_d_cl_g16 v[0:3], v[4:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_d_cl_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v5, v4, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_d_cl_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v5.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_d_cl_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v4, v5, v4, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f16.f16(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -1197,19 +1628,33 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_d_cl_1d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
-; GFX11-NEXT:    image_sample_c_d_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_c_d_cl_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
-; GFX12-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_d_cl_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l
+; GFX11-TRUE16-NEXT:    image_sample_c_d_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_c_d_cl_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    image_sample_c_d_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_d_cl_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l
+; GFX12-TRUE16-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_d_cl_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
+; GFX12-FAKE16-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f32.f16(i32 15, float %zcompare, half %dsdh, half %dsdv, half %s, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -1237,23 +1682,43 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_d_cl_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v5, v6, v5, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX11-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v5, v7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_c_d_cl_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v6, v6, v5, 0x5040100
-; GFX12-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v[6:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_d_cl_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v5, v7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_c_d_cl_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v6, v5, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v5, v7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_d_cl_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v7.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v5.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v7.h, v6.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v[7:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_d_cl_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v6, v6, v5, 0x5040100
+; GFX12-FAKE16-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v[6:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f32.f16(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -1275,19 +1740,33 @@ define amdgpu_ps <4 x float> @sample_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_l_1d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    image_sample_l v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_l_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-NEXT:    image_sample_l v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_l_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    image_sample_l v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_l_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    image_sample_l v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_l_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    image_sample_l v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_l_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    image_sample_l v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.l.1d.v4f32.f16(i32 15, half %s, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -1309,19 +1788,35 @@ define amdgpu_ps <4 x float> @sample_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_l_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    image_sample_l v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_l_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-NEXT:    image_sample_l v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_l_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v1.l
+; GFX11-TRUE16-NEXT:    image_sample_l v[0:3], v[2:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_l_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    image_sample_l v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_l_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    image_sample_l v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_l_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    image_sample_l v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.l.2d.v4f32.f16(i32 15, half %s, half %t, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -1343,19 +1838,33 @@ define amdgpu_ps <4 x float> @sample_c_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_l_1d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX11-NEXT:    image_sample_c_l v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_c_l_1d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-NEXT:    image_sample_c_l v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_l_1d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    image_sample_c_l v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_c_l_1d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    image_sample_c_l v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_l_1d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    image_sample_c_l v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_l_1d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-FAKE16-NEXT:    image_sample_c_l v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.c.l.1d.v4f32.f16(i32 15, float %zcompare, half %s, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -1379,19 +1888,33 @@ define amdgpu_ps <4 x float> @sample_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_l_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX11-NEXT:    image_sample_c_l v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_c_l_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-NEXT:    image_sample_c_l v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_l_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    image_sample_c_l v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_c_l_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    image_sample_c_l v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_l_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    image_sample_c_l v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_l_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-FAKE16-NEXT:    image_sample_c_l v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.c.l.2d.v4f32.f16(i32 15, float %zcompare, half %s, half %t, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -1442,19 +1965,33 @@ define amdgpu_ps <4 x float> @sample_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_lz_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    image_sample_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_lz_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-NEXT:    image_sample_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_lz_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    image_sample_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_lz_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    image_sample_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_lz_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    image_sample_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_lz_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    image_sample_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f16(i32 15, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -1505,19 +2042,33 @@ define amdgpu_ps <4 x float> @sample_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> in
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_lz_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX11-NEXT:    image_sample_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_c_lz_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-NEXT:    image_sample_c_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_lz_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    image_sample_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_c_lz_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    image_sample_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_lz_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    image_sample_c_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_lz_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-FAKE16-NEXT:    image_sample_c_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.c.lz.2d.v4f32.f16(i32 15, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -1549,23 +2100,46 @@ define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32>
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_d_o_2darray_V1:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v4, v5, v4, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v7, v7, v6, 0x5040100
-; GFX11-NEXT:    image_sample_c_d_o_g16 v0, [v0, v1, v2, v4, v[7:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_c_d_o_2darray_V1:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v7, v7, v6, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v6, v5, v4, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-NEXT:    image_sample_c_d_o_g16 v0, [v0, v1, v2, v[6:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_d_o_2darray_V1:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.h, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v5.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    image_sample_c_d_o_g16 v0, [v0, v1, v2, v4, v[8:9]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_c_d_o_2darray_V1:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v5, v4, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v6, 0x5040100
+; GFX11-FAKE16-NEXT:    image_sample_c_d_o_g16 v0, [v0, v1, v2, v4, v[7:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_d_o_2darray_V1:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v8.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v6.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v8.h, v7.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v4.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v7.h, v5.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    image_sample_c_d_o_g16 v0, [v0, v1, v2, v[7:9]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_d_o_2darray_V1:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v7, v7, v6, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v6, v5, v4, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12-FAKE16-NEXT:    image_sample_c_d_o_g16 v0, [v0, v1, v2, v[6:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f32.f16.f16(i32 4, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret float %v
@@ -1597,23 +2171,46 @@ define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_d_o_2darray_V2:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v4, v5, v4, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v7, v7, v6, 0x5040100
-; GFX11-NEXT:    image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v4, v[7:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: sample_c_d_o_2darray_V2:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v7, v7, v6, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v6, v5, v4, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-NEXT:    image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v[6:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY a16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_d_o_2darray_V2:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v8.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v6.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.h, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v5.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v4, v[8:9]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: sample_c_d_o_2darray_V2:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v5, v4, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v7, v6, 0x5040100
+; GFX11-FAKE16-NEXT:    image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v4, v[7:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_d_o_2darray_V2:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v8.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v6.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v8.h, v7.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v4.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v7.h, v5.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v[7:9]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_d_o_2darray_V2:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v7, v7, v6, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v6, v5, v4, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12-FAKE16-NEXT:    image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v[6:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY a16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f32.f16(i32 6, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <2 x float> %v
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
index 8861ff4c78137..323d0fbe741a4 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
@@ -3,8 +3,10 @@
 ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -check-prefixes=GFX81 %s
 ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefixes=GFX9 %s
 ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-TRUE16 %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-FAKE16 %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
 
 define amdgpu_ps half @image_sample_2d_f16(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {
 ; TONGA-LABEL: image_sample_2d_f16:
@@ -121,33 +123,63 @@ define amdgpu_ps half @image_sample_2d_f16_tfe(<8 x i32> inreg %rsrc, <4 x i32>
 ; GFX10-NEXT:    global_store_dword v4, v1, s[12:13]
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: image_sample_2d_f16_tfe:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    s_mov_b32 s14, exec_lo
-; GFX11-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX11-NEXT:    v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, v1
-; GFX11-NEXT:    v_mov_b32_e32 v2, v0
-; GFX11-NEXT:    v_mov_b32_e32 v5, v4
-; GFX11-NEXT:    v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
-; GFX11-NEXT:    s_and_b32 exec_lo, exec_lo, s14
-; GFX11-NEXT:    image_sample v[0:1], v[2:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe d16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b32 v4, v1, s[12:13]
-; GFX11-NEXT:    ; return to shader part epilog
-;
-; GFX12-LABEL: image_sample_2d_f16_tfe:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s14, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    v_mov_b32_e32 v4, 0
-; GFX12-NEXT:    v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v3, v0
-; GFX12-NEXT:    v_mov_b32_e32 v5, v4
-; GFX12-NEXT:    v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
-; GFX12-NEXT:    s_and_b32 exec_lo, exec_lo, s14
-; GFX12-NEXT:    image_sample v[0:1], [v3, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe d16
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    global_store_b32 v4, v1, s[12:13]
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: image_sample_2d_f16_tfe:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX11-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v3, v2
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v4, v3
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v3, v2
+; GFX11-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX11-TRUE16-NEXT:    image_sample v[3:4], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe d16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v3.l
+; GFX11-TRUE16-NEXT:    global_store_b32 v2, v4, s[12:13]
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: image_sample_2d_f16_tfe:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX11-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, v1
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX11-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX11-FAKE16-NEXT:    image_sample v[0:1], v[2:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe d16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    global_store_b32 v4, v1, s[12:13]
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: image_sample_2d_f16_tfe:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v3, v2
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v4, v3
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v3, v2
+; GFX12-TRUE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX12-TRUE16-NEXT:    image_sample v[3:4], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe d16
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v3.l
+; GFX12-TRUE16-NEXT:    global_store_b32 v2, v4, s[12:13]
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: image_sample_2d_f16_tfe:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s14, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v4, 0
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v3, v0
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v5, v4
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX12-FAKE16-NEXT:    s_and_b32 exec_lo, exec_lo, s14
+; GFX12-FAKE16-NEXT:    image_sample v[0:1], [v3, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe d16
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    global_store_b32 v4, v1, s[12:13]
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %tex = call {half,i32} @llvm.amdgcn.image.sample.2d.f16i32.f32(i32 1, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 1, i32 0)
   %tex.vec = extractvalue {half, i32} %tex, 0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
index aa24ac394730e..e7b048dda1c1f 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
@@ -1,7 +1,9 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX10 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX11 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-vopd=0 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-vopd=0 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-vopd=0 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-vopd=0 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-vopd=0 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
 
 define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) {
 ; GFX10-LABEL: sample_d_1d:
@@ -35,21 +37,37 @@ define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_d_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100 ; encoding: [0x02,0x00,0x44,0xd6,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100 ; encoding: [0x00,0x00,0x44,0xd6,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX11-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x05,0x0f,0xe4,0xf0,0x00,0x00,0x00,0x08,0x02,0x04,0x05,0x00]
-; GFX11-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_d_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l ; encoding: [0x03,0x39,0x04,0x7f]
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l ; encoding: [0x01,0x39,0x00,0x7f]
+; GFX11-TRUE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x05,0x0f,0xe4,0xf0,0x00,0x00,0x00,0x08,0x02,0x04,0x05,0x00]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: sample_d_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100 ; encoding: [0x02,0x00,0x44,0xd6,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100 ; encoding: [0x00,0x00,0x44,0xd6,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX12-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x40,0xce,0xe7,0x00,0x00,0x00,0x04,0x00,0x02,0x04,0x05]
-; GFX12-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-FAKE16-LABEL: sample_d_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100 ; encoding: [0x02,0x00,0x44,0xd6,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100 ; encoding: [0x00,0x00,0x44,0xd6,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX11-FAKE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x05,0x0f,0xe4,0xf0,0x00,0x00,0x00,0x08,0x02,0x04,0x05,0x00]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_d_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l ; encoding: [0x03,0x39,0x04,0x7f]
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l ; encoding: [0x01,0x39,0x00,0x7f]
+; GFX12-TRUE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x40,0xce,0xe7,0x00,0x00,0x00,0x04,0x00,0x02,0x04,0x05]
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_d_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100 ; encoding: [0x02,0x00,0x44,0xd6,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100 ; encoding: [0x00,0x00,0x44,0xd6,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX12-FAKE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x40,0xce,0xe7,0x00,0x00,0x00,0x04,0x00,0x02,0x04,0x05]
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -66,21 +84,37 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_d_3d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100 ; encoding: [0x03,0x00,0x44,0xd6,0x04,0x07,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100 ; encoding: [0x00,0x00,0x44,0xd6,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX11-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v3, v5, v[6:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x09,0x0f,0xe4,0xf0,0x00,0x00,0x00,0x08,0x02,0x03,0x05,0x06]
-; GFX11-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_d_3d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l ; encoding: [0x04,0x39,0x06,0x7f]
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l ; encoding: [0x01,0x39,0x00,0x7f]
+; GFX11-TRUE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v3, v5, v[6:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x09,0x0f,0xe4,0xf0,0x00,0x00,0x00,0x08,0x02,0x03,0x05,0x06]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: sample_d_3d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100 ; encoding: [0x03,0x00,0x44,0xd6,0x04,0x07,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100 ; encoding: [0x00,0x00,0x44,0xd6,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX12-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v3, v[5:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x40,0xce,0xe7,0x00,0x00,0x00,0x04,0x00,0x02,0x03,0x05]
-; GFX12-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-FAKE16-LABEL: sample_d_3d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100 ; encoding: [0x03,0x00,0x44,0xd6,0x04,0x07,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100 ; encoding: [0x00,0x00,0x44,0xd6,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX11-FAKE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v3, v5, v[6:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x09,0x0f,0xe4,0xf0,0x00,0x00,0x00,0x08,0x02,0x03,0x05,0x06]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_d_3d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l ; encoding: [0x04,0x39,0x06,0x7f]
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l ; encoding: [0x01,0x39,0x00,0x7f]
+; GFX12-TRUE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v3, v[5:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x40,0xce,0xe7,0x00,0x00,0x00,0x04,0x00,0x02,0x03,0x05]
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_d_3d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100 ; encoding: [0x03,0x00,0x44,0xd6,0x04,0x07,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100 ; encoding: [0x00,0x00,0x44,0xd6,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX12-FAKE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v3, v[5:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x40,0xce,0xe7,0x00,0x00,0x00,0x04,0x00,0x02,0x03,0x05]
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -118,21 +152,37 @@ define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_d_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100 ; encoding: [0x03,0x00,0x44,0xd6,0x04,0x07,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX11-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100 ; encoding: [0x01,0x00,0x44,0xd6,0x02,0x03,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX11-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x05,0x0f,0xe8,0xf0,0x00,0x00,0x00,0x08,0x01,0x03,0x05,0x06]
-; GFX11-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_d_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l ; encoding: [0x04,0x39,0x06,0x7f]
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l ; encoding: [0x02,0x39,0x02,0x7f]
+; GFX11-TRUE16-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x05,0x0f,0xe8,0xf0,0x00,0x00,0x00,0x08,0x01,0x03,0x05,0x06]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: sample_c_d_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100 ; encoding: [0x03,0x00,0x44,0xd6,0x04,0x07,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX12-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100 ; encoding: [0x01,0x00,0x44,0xd6,0x02,0x03,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX12-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v3, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0xce,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x03,0x05]
-; GFX12-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-FAKE16-LABEL: sample_c_d_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100 ; encoding: [0x03,0x00,0x44,0xd6,0x04,0x07,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100 ; encoding: [0x01,0x00,0x44,0xd6,0x02,0x03,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX11-FAKE16-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x05,0x0f,0xe8,0xf0,0x00,0x00,0x00,0x08,0x01,0x03,0x05,0x06]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_d_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l ; encoding: [0x04,0x39,0x06,0x7f]
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l ; encoding: [0x02,0x39,0x02,0x7f]
+; GFX12-TRUE16-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v3, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0xce,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x03,0x05]
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_d_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100 ; encoding: [0x03,0x00,0x44,0xd6,0x04,0x07,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100 ; encoding: [0x01,0x00,0x44,0xd6,0x02,0x03,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX12-FAKE16-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v3, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0xce,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x03,0x05]
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -170,21 +220,37 @@ define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_d_cl_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100 ; encoding: [0x02,0x00,0x44,0xd6,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100 ; encoding: [0x00,0x00,0x44,0xd6,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX11-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x05,0x0f,0x7c,0xf1,0x00,0x00,0x00,0x08,0x02,0x04,0x05,0x06]
-; GFX11-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_d_cl_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l ; encoding: [0x03,0x39,0x04,0x7f]
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l ; encoding: [0x01,0x39,0x00,0x7f]
+; GFX11-TRUE16-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x05,0x0f,0x7c,0xf1,0x00,0x00,0x00,0x08,0x02,0x04,0x05,0x06]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: sample_d_cl_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100 ; encoding: [0x02,0x00,0x44,0xd6,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100 ; encoding: [0x00,0x00,0x44,0xd6,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX12-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0xd7,0xe7,0x00,0x00,0x00,0x04,0x00,0x02,0x04,0x05]
-; GFX12-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-FAKE16-LABEL: sample_d_cl_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100 ; encoding: [0x02,0x00,0x44,0xd6,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100 ; encoding: [0x00,0x00,0x44,0xd6,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX11-FAKE16-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x05,0x0f,0x7c,0xf1,0x00,0x00,0x00,0x08,0x02,0x04,0x05,0x06]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_d_cl_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l ; encoding: [0x03,0x39,0x04,0x7f]
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l ; encoding: [0x01,0x39,0x00,0x7f]
+; GFX12-TRUE16-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0xd7,0xe7,0x00,0x00,0x00,0x04,0x00,0x02,0x04,0x05]
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_d_cl_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100 ; encoding: [0x02,0x00,0x44,0xd6,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100 ; encoding: [0x00,0x00,0x44,0xd6,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX12-FAKE16-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0xd7,0xe7,0x00,0x00,0x00,0x04,0x00,0x02,0x04,0x05]
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -224,21 +290,37 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_d_cl_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100 ; encoding: [0x03,0x00,0x44,0xd6,0x04,0x07,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX11-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100 ; encoding: [0x01,0x00,0x44,0xd6,0x02,0x03,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX11-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v5, v[6:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x05,0x0f,0x50,0xf1,0x00,0x00,0x00,0x08,0x01,0x03,0x05,0x06]
-; GFX11-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_d_cl_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l ; encoding: [0x04,0x39,0x06,0x7f]
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l ; encoding: [0x02,0x39,0x02,0x7f]
+; GFX11-TRUE16-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v5, v[6:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x05,0x0f,0x50,0xf1,0x00,0x00,0x00,0x08,0x01,0x03,0x05,0x06]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: sample_c_d_cl_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100 ; encoding: [0x03,0x00,0x44,0xd6,0x04,0x07,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX12-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100 ; encoding: [0x01,0x00,0x44,0xd6,0x02,0x03,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX12-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v[5:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0xd5,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x03,0x05]
-; GFX12-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-FAKE16-LABEL: sample_c_d_cl_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100 ; encoding: [0x03,0x00,0x44,0xd6,0x04,0x07,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100 ; encoding: [0x01,0x00,0x44,0xd6,0x02,0x03,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX11-FAKE16-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v5, v[6:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x05,0x0f,0x50,0xf1,0x00,0x00,0x00,0x08,0x01,0x03,0x05,0x06]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_d_cl_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l ; encoding: [0x04,0x39,0x06,0x7f]
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l ; encoding: [0x02,0x39,0x02,0x7f]
+; GFX12-TRUE16-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v[5:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0xd5,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x03,0x05]
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_d_cl_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100 ; encoding: [0x03,0x00,0x44,0xd6,0x04,0x07,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100 ; encoding: [0x01,0x00,0x44,0xd6,0x02,0x03,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX12-FAKE16-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v[5:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0xd5,0xe7,0x00,0x00,0x00,0x04,0x00,0x01,0x03,0x05]
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -257,21 +339,40 @@ define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32>
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_d_o_2darray_V1:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v4, v5, v4, 0x5040100 ; encoding: [0x04,0x00,0x44,0xd6,0x05,0x09,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX11-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100 ; encoding: [0x02,0x00,0x44,0xd6,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX11-NEXT:    image_sample_c_d_o_g16 v0, [v0, v1, v2, v4, v[6:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x15,0x04,0xf0,0xf0,0x00,0x00,0x00,0x08,0x01,0x02,0x04,0x06]
-; GFX11-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_d_o_2darray_V1:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v5.l ; encoding: [0x05,0x39,0x08,0x7f]
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l ; encoding: [0x03,0x39,0x04,0x7f]
+; GFX11-TRUE16-NEXT:    image_sample_c_d_o_g16 v0, [v0, v1, v2, v4, v[6:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x15,0x04,0xf0,0xf0,0x00,0x00,0x00,0x08,0x01,0x02,0x04,0x06]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: sample_c_d_o_2darray_V1:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v5, v5, v4, 0x5040100 ; encoding: [0x05,0x00,0x44,0xd6,0x05,0x09,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX12-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100 ; encoding: [0x02,0x00,0x44,0xd6,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX12-NEXT:    image_sample_c_d_o_g16 v0, [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0x0f,0xe5,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x05]
-; GFX12-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-FAKE16-LABEL: sample_c_d_o_2darray_V1:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v5, v4, 0x5040100 ; encoding: [0x04,0x00,0x44,0xd6,0x05,0x09,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100 ; encoding: [0x02,0x00,0x44,0xd6,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX11-FAKE16-NEXT:    image_sample_c_d_o_g16 v0, [v0, v1, v2, v4, v[6:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x15,0x04,0xf0,0xf0,0x00,0x00,0x00,0x08,0x01,0x02,0x04,0x06]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_d_o_2darray_V1:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v9, v5 ; encoding: [0x05,0x03,0x12,0x7e]
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v4.l ; encoding: [0x04,0x39,0x0a,0x7e]
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l ; encoding: [0x03,0x39,0x04,0x7f]
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) ; encoding: [0x03,0x00,0x87,0xbf]
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v9.l ; encoding: [0x09,0x39,0x0a,0x7f]
+; GFX12-TRUE16-NEXT:    image_sample_c_d_o_g16 v0, [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0x0f,0xe5,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x05]
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_d_o_2darray_V1:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v5, v5, v4, 0x5040100 ; encoding: [0x05,0x00,0x44,0xd6,0x05,0x09,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX12-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100 ; encoding: [0x02,0x00,0x44,0xd6,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX12-FAKE16-NEXT:    image_sample_c_d_o_g16 v0, [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0x0f,0xe5,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x05]
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f16.f32.f32(i32 4, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret float %v
@@ -290,21 +391,40 @@ define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_d_o_2darray_V2:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v4, v5, v4, 0x5040100 ; encoding: [0x04,0x00,0x44,0xd6,0x05,0x09,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX11-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100 ; encoding: [0x02,0x00,0x44,0xd6,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX11-NEXT:    image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v4, v[6:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x15,0x06,0xf0,0xf0,0x00,0x00,0x00,0x08,0x01,0x02,0x04,0x06]
-; GFX11-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_d_o_2darray_V2:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v5.l ; encoding: [0x05,0x39,0x08,0x7f]
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l ; encoding: [0x03,0x39,0x04,0x7f]
+; GFX11-TRUE16-NEXT:    image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v4, v[6:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x15,0x06,0xf0,0xf0,0x00,0x00,0x00,0x08,0x01,0x02,0x04,0x06]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: sample_c_d_o_2darray_V2:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v5, v5, v4, 0x5040100 ; encoding: [0x05,0x00,0x44,0xd6,0x05,0x09,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX12-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100 ; encoding: [0x02,0x00,0x44,0xd6,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
-; GFX12-NEXT:    image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0x8f,0xe5,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x05]
-; GFX12-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-FAKE16-LABEL: sample_c_d_o_2darray_V2:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v5, v4, 0x5040100 ; encoding: [0x04,0x00,0x44,0xd6,0x05,0x09,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100 ; encoding: [0x02,0x00,0x44,0xd6,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX11-FAKE16-NEXT:    image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v4, v[6:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x15,0x06,0xf0,0xf0,0x00,0x00,0x00,0x08,0x01,0x02,0x04,0x06]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf]
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_d_o_2darray_V2:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v9, v5 ; encoding: [0x05,0x03,0x12,0x7e]
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v4.l ; encoding: [0x04,0x39,0x0a,0x7e]
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l ; encoding: [0x03,0x39,0x04,0x7f]
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) ; encoding: [0x03,0x00,0x87,0xbf]
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v9.l ; encoding: [0x09,0x39,0x0a,0x7f]
+; GFX12-TRUE16-NEXT:    image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0x8f,0xe5,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x05]
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_d_o_2darray_V2:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v5, v5, v4, 0x5040100 ; encoding: [0x05,0x00,0x44,0xd6,0x05,0x09,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX12-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100 ; encoding: [0x02,0x00,0x44,0xd6,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
+; GFX12-FAKE16-NEXT:    image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x05,0x00,0x8f,0xe5,0x00,0x00,0x00,0x04,0x00,0x01,0x02,0x05]
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f32(i32 6, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <2 x float> %v
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
index 90dfab501d0a4..4873b42a235e3 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
@@ -1,10 +1,15 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10PLUS-SDAG,GFX10,GFX10-SDAG %s
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10PLUS-GISEL,GFX10,GFX10-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10PLUS-SDAG,GFX11,GFX11-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10PLUS-GISEL,GFX11,GFX11-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10PLUS-SDAG,GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10PLUS-SDAG,GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
+; FIXME-TRUE16. enable gisel
+; XUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10PLUS-GISEL,GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10PLUS-GISEL,GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
+; XUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
 
 define amdgpu_ps void @sample_1d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {
 ; GFX10PLUS-LABEL: sample_1d_nortn:
@@ -476,4 +481,10 @@ attributes #1 = { nounwind readonly }
 ; GFX10-SDAG: {{.*}}
 ; GFX11: {{.*}}
 ; GFX11-GISEL: {{.*}}
+; GFX11-GISEL-FAKE16: {{.*}}
 ; GFX11-SDAG: {{.*}}
+; GFX11-SDAG-FAKE16: {{.*}}
+; GFX11-SDAG-TRUE16: {{.*}}
+; GFX12-GISEL-FAKE16: {{.*}}
+; GFX12-SDAG-FAKE16: {{.*}}
+; GFX12-SDAG-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
index 19da3f4503aa5..4d937dade51f4 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
@@ -1,7 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
 
 define amdgpu_ps void @v_interp_f32(float inreg %i, float inreg %j, i32 inreg %m0) #0 {
 ; GFX11-LABEL: v_interp_f32:
@@ -227,23 +228,41 @@ define amdgpu_ps half @v_interp_f16(float inreg %i, float inreg %j, i32 inreg %m
 ; GFX11-FAKE16-NEXT:    v_add_f16_e32 v0, v3, v0
 ; GFX11-FAKE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: v_interp_f16:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s3, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    s_mov_b32 m0, s2
-; GFX12-NEXT:    ds_param_load v1, attr0.x wait_va_vdst:15 wait_vm_vsrc:1
-; GFX12-NEXT:    s_mov_b32 exec_lo, s3
-; GFX12-NEXT:    v_mov_b32_e32 v0, s0
-; GFX12-NEXT:    v_mov_b32_e32 v2, s1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_interp_p10_f16_f32 v3, v1, v0, v1 wait_exp:0
-; GFX12-NEXT:    v_interp_p10_f16_f32 v0, v1, v0, v1 op_sel:[1,0,1,0] wait_exp:7
-; GFX12-NEXT:    v_interp_p2_f16_f32 v3, v1, v2, v3 wait_exp:7
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_interp_p2_f16_f32 v0, v1, v2, v0 op_sel:[1,0,0,0] wait_exp:7
-; GFX12-NEXT:    v_add_f16_e32 v0, v3, v0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX12-TRUE16-LABEL: v_interp_f16:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    s_mov_b32 m0, s2
+; GFX12-TRUE16-NEXT:    ds_param_load v1, attr0.x wait_va_vdst:15 wait_vm_vsrc:1
+; GFX12-TRUE16-NEXT:    s_mov_b32 exec_lo, s3
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v0, s0
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v2, s1
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_interp_p10_f16_f32 v3, v1.l, v0, v1.l wait_exp:0
+; GFX12-TRUE16-NEXT:    v_interp_p10_f16_f32 v4, v1.h, v0, v1.h wait_exp:7
+; GFX12-TRUE16-NEXT:    v_interp_p2_f16_f32 v0.l, v1.l, v2, v3 wait_exp:7
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_interp_p2_f16_f32 v0.h, v1.h, v2, v4 wait_exp:7
+; GFX12-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: v_interp_f16:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    s_mov_b32 m0, s2
+; GFX12-FAKE16-NEXT:    ds_param_load v1, attr0.x wait_va_vdst:15 wait_vm_vsrc:1
+; GFX12-FAKE16-NEXT:    s_mov_b32 exec_lo, s3
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v0, s0
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v2, s1
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_interp_p10_f16_f32 v3, v1, v0, v1 wait_exp:0
+; GFX12-FAKE16-NEXT:    v_interp_p10_f16_f32 v0, v1, v0, v1 op_sel:[1,0,1,0] wait_exp:7
+; GFX12-FAKE16-NEXT:    v_interp_p2_f16_f32 v3, v1, v2, v3 wait_exp:7
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_interp_p2_f16_f32 v0, v1, v2, v0 op_sel:[1,0,0,0] wait_exp:7
+; GFX12-FAKE16-NEXT:    v_add_f16_e32 v0, v3, v0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %p0 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 0, i32 %m0)
   %l_p0 = call float @llvm.amdgcn.interp.inreg.p10.f16(float %p0, float %i, float %p0, i1 0)
@@ -291,23 +310,41 @@ define amdgpu_ps half @v_interp_rtz_f16(float inreg %i, float inreg %j, i32 inre
 ; GFX11-FAKE16-NEXT:    v_add_f16_e32 v0, v3, v0
 ; GFX11-FAKE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: v_interp_rtz_f16:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    s_mov_b32 s3, exec_lo
-; GFX12-NEXT:    s_wqm_b32 exec_lo, exec_lo
-; GFX12-NEXT:    s_mov_b32 m0, s2
-; GFX12-NEXT:    ds_param_load v1, attr0.x wait_va_vdst:15 wait_vm_vsrc:1
-; GFX12-NEXT:    s_mov_b32 exec_lo, s3
-; GFX12-NEXT:    v_mov_b32_e32 v0, s0
-; GFX12-NEXT:    v_mov_b32_e32 v2, s1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_interp_p10_rtz_f16_f32 v3, v1, v0, v1 wait_exp:0
-; GFX12-NEXT:    v_interp_p10_rtz_f16_f32 v0, v1, v0, v1 op_sel:[1,0,1,0] wait_exp:7
-; GFX12-NEXT:    v_interp_p2_rtz_f16_f32 v3, v1, v2, v3 wait_exp:7
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_interp_p2_rtz_f16_f32 v0, v1, v2, v0 op_sel:[1,0,0,0] wait_exp:7
-; GFX12-NEXT:    v_add_f16_e32 v0, v3, v0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX12-TRUE16-LABEL: v_interp_rtz_f16:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    s_mov_b32 s3, exec_lo
+; GFX12-TRUE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-TRUE16-NEXT:    s_mov_b32 m0, s2
+; GFX12-TRUE16-NEXT:    ds_param_load v1, attr0.x wait_va_vdst:15 wait_vm_vsrc:1
+; GFX12-TRUE16-NEXT:    s_mov_b32 exec_lo, s3
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v0, s0
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v2, s1
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_interp_p10_rtz_f16_f32 v3, v1.l, v0, v1.l wait_exp:0
+; GFX12-TRUE16-NEXT:    v_interp_p10_rtz_f16_f32 v4, v1.h, v0, v1.h wait_exp:7
+; GFX12-TRUE16-NEXT:    v_interp_p2_rtz_f16_f32 v0.l, v1.l, v2, v3 wait_exp:7
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_interp_p2_rtz_f16_f32 v0.h, v1.h, v2, v4 wait_exp:7
+; GFX12-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: v_interp_rtz_f16:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    s_mov_b32 s3, exec_lo
+; GFX12-FAKE16-NEXT:    s_wqm_b32 exec_lo, exec_lo
+; GFX12-FAKE16-NEXT:    s_mov_b32 m0, s2
+; GFX12-FAKE16-NEXT:    ds_param_load v1, attr0.x wait_va_vdst:15 wait_vm_vsrc:1
+; GFX12-FAKE16-NEXT:    s_mov_b32 exec_lo, s3
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v0, s0
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v2, s1
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_interp_p10_rtz_f16_f32 v3, v1, v0, v1 wait_exp:0
+; GFX12-FAKE16-NEXT:    v_interp_p10_rtz_f16_f32 v0, v1, v0, v1 op_sel:[1,0,1,0] wait_exp:7
+; GFX12-FAKE16-NEXT:    v_interp_p2_rtz_f16_f32 v3, v1, v2, v3 wait_exp:7
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_interp_p2_rtz_f16_f32 v0, v1, v2, v0 op_sel:[1,0,0,0] wait_exp:7
+; GFX12-FAKE16-NEXT:    v_add_f16_e32 v0, v3, v0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %p0 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 0, i32 %m0)
   %l_p0 = call float @llvm.amdgcn.interp.p10.rtz.f16(float %p0, float %i, float %p0, i1 0)
@@ -344,17 +381,30 @@ define amdgpu_ps half @v_interp_f16_imm_params(float inreg %i, float inreg %j) #
 ; GFX11-FAKE16-NEXT:    v_add_f16_e32 v0, v1, v0
 ; GFX11-FAKE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: v_interp_f16_imm_params:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
-; GFX12-NEXT:    v_mov_b32_e32 v2, s1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_interp_p10_f16_f32 v1, v0, v1, v0 wait_exp:7
-; GFX12-NEXT:    v_interp_p2_f16_f32 v0, v0, v2, v0 wait_exp:7
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX12-NEXT:    v_add_f16_e32 v0, v1, v0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX12-TRUE16-LABEL: v_interp_f16_imm_params:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.l, 0
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, 0
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v3, s1
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_interp_p10_f16_f32 v1, v0.l, v1, v0.l wait_exp:7
+; GFX12-TRUE16-NEXT:    v_interp_p2_f16_f32 v0.l, v0.l, v3, v2 wait_exp:7
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v1
+; GFX12-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.h, v0.l
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: v_interp_f16_imm_params:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v2, s1
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_interp_p10_f16_f32 v1, v0, v1, v0 wait_exp:7
+; GFX12-FAKE16-NEXT:    v_interp_p2_f16_f32 v0, v0, v2, v0 wait_exp:7
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX12-FAKE16-NEXT:    v_add_f16_e32 v0, v1, v0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %l_p0 = call float @llvm.amdgcn.interp.inreg.p10.f16(float 0.0, float %i, float 0.0, i1 0)
   %l_p1 = call half @llvm.amdgcn.interp.inreg.p2.f16(float 0.0, float %j, float 0.0, i1 0)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
index 4509d954c5e8b..9606c68684957 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
@@ -3,9 +3,12 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1013 -verify-machineinstrs < %s | FileCheck -check-prefixes=PRE-GFX12,GFX10,GFX1013 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefixes=PRE-GFX12,GFX10,GFX1030 %s
 ; RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERR %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=PRE-GFX12,GFX11 %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=PRE-GFX12,GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=PRE-GFX12,GFX11,GFX11-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
 
 ; uint4 llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(uint node_ptr, float ray_extent, float3 ray_origin, float3 ray_dir, float3 ray_inv_dir, uint4 texture_descr)
 ; uint4 llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(uint node_ptr, float ray_extent, float3 ray_origin, half3 ray_dir, half3 ray_inv_dir, uint4 texture_descr)
@@ -69,67 +72,138 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16(i32 inreg %node_ptr, f
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: image_bvh_intersect_ray_a16:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
-; GFX11-NEXT:    s_lshr_b32 s2, s7, 16
-; GFX11-NEXT:    s_lshr_b32 s3, s5, 16
-; GFX11-NEXT:    v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v7, s1
-; GFX11-NEXT:    s_pack_ll_b32_b16 s2, s3, s2
-; GFX11-NEXT:    s_pack_ll_b32_b16 s3, s5, s7
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT:    v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s3
-; GFX11-NEXT:    s_pack_ll_b32_b16 s4, s6, s8
-; GFX11-NEXT:    v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s4
-; GFX11-NEXT:    s_mov_b32 s15, s12
-; GFX11-NEXT:    s_mov_b32 s14, s11
-; GFX11-NEXT:    s_mov_b32 s13, s10
-; GFX11-NEXT:    s_mov_b32 s12, s9
-; GFX11-NEXT:    image_bvh_intersect_ray v[0:3], [v6, v7, v[0:2], v[3:5]], s[12:15] a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: image_bvh_intersect_ray_a16:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX11-TRUE16-NEXT:    s_lshr_b32 s2, s7, 16
+; GFX11-TRUE16-NEXT:    s_lshr_b32 s3, s5, 16
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, s4
+; GFX11-TRUE16-NEXT:    s_pack_ll_b32_b16 s2, s3, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s5
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT:    s_pack_ll_b32_b16 s4, s4, s5
+; GFX11-TRUE16-NEXT:    s_pack_ll_b32_b16 s3, s3, s6
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s2
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v6, s0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v7, s1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s15, s12
+; GFX11-TRUE16-NEXT:    s_mov_b32 s14, s11
+; GFX11-TRUE16-NEXT:    s_mov_b32 s13, s10
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, s9
+; GFX11-TRUE16-NEXT:    image_bvh_intersect_ray v[0:3], [v6, v7, v[0:2], v[3:5]], s[12:15] a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-SDAG-LABEL: image_bvh_intersect_ray_a16:
-; GFX12-SDAG:       ; %bb.0: ; %main_body
-; GFX12-SDAG-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
-; GFX12-SDAG-NEXT:    s_lshr_b32 s2, s7, 16
-; GFX12-SDAG-NEXT:    s_lshr_b32 s3, s5, 16
-; GFX12-SDAG-NEXT:    v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v7, s1
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffe
-; GFX12-SDAG-NEXT:    s_pack_ll_b32_b16 s2, s3, s2
-; GFX12-SDAG-NEXT:    s_pack_ll_b32_b16 s3, s5, s7
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffe
-; GFX12-SDAG-NEXT:    v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s3
-; GFX12-SDAG-NEXT:    s_pack_ll_b32_b16 s4, s6, s8
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffe
-; GFX12-SDAG-NEXT:    v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s4
-; GFX12-SDAG-NEXT:    s_mov_b32 s15, s12
-; GFX12-SDAG-NEXT:    s_mov_b32 s14, s11
-; GFX12-SDAG-NEXT:    s_mov_b32 s13, s10
-; GFX12-SDAG-NEXT:    s_mov_b32 s12, s9
-; GFX12-SDAG-NEXT:    image_bvh_intersect_ray v[0:3], [v6, v7, v[0:2], v[3:5]], s[12:15] a16
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    ; return to shader part epilog
+; GFX11-FAKE16-LABEL: image_bvh_intersect_ray_a16:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX11-FAKE16-NEXT:    s_lshr_b32 s2, s7, 16
+; GFX11-FAKE16-NEXT:    s_lshr_b32 s3, s5, 16
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v7, s1
+; GFX11-FAKE16-NEXT:    s_pack_ll_b32_b16 s2, s3, s2
+; GFX11-FAKE16-NEXT:    s_pack_ll_b32_b16 s3, s5, s7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s3
+; GFX11-FAKE16-NEXT:    s_pack_ll_b32_b16 s4, s6, s8
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s15, s12
+; GFX11-FAKE16-NEXT:    s_mov_b32 s14, s11
+; GFX11-FAKE16-NEXT:    s_mov_b32 s13, s10
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, s9
+; GFX11-FAKE16-NEXT:    image_bvh_intersect_ray v[0:3], [v6, v7, v[0:2], v[3:5]], s[12:15] a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-GISEL-LABEL: image_bvh_intersect_ray_a16:
-; GFX12-GISEL:       ; %bb.0: ; %main_body
-; GFX12-GISEL-NEXT:    s_mov_b32 s20, s2
-; GFX12-GISEL-NEXT:    s_mov_b32 s22, s4
-; GFX12-GISEL-NEXT:    s_pack_ll_b32_b16 s4, s7, s5
-; GFX12-GISEL-NEXT:    s_mov_b32 s21, s3
-; GFX12-GISEL-NEXT:    s_pack_hh_b32_b16 s5, s7, s5
-; GFX12-GISEL-NEXT:    s_pack_ll_b32_b16 s6, s8, s6
-; GFX12-GISEL-NEXT:    v_dual_mov_b32 v0, s20 :: v_dual_mov_b32 v1, s21
-; GFX12-GISEL-NEXT:    v_dual_mov_b32 v2, s22 :: v_dual_mov_b32 v3, s4
-; GFX12-GISEL-NEXT:    v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v7, s1
-; GFX12-GISEL-NEXT:    v_dual_mov_b32 v4, s5 :: v_dual_mov_b32 v5, s6
-; GFX12-GISEL-NEXT:    s_mov_b32 s16, s9
-; GFX12-GISEL-NEXT:    s_mov_b32 s17, s10
-; GFX12-GISEL-NEXT:    s_mov_b32 s18, s11
-; GFX12-GISEL-NEXT:    s_mov_b32 s19, s12
-; GFX12-GISEL-NEXT:    image_bvh_intersect_ray v[0:3], [v6, v7, v[0:2], v[3:5]], s[16:19] a16
-; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT:    ; return to shader part epilog
+; GFX12-SDAG-TRUE16-LABEL: image_bvh_intersect_ray_a16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-SDAG-TRUE16-NEXT:    s_lshr_b32 s2, s7, 16
+; GFX12-SDAG-TRUE16-NEXT:    s_lshr_b32 s3, s5, 16
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v2, s4
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX12-SDAG-TRUE16-NEXT:    s_pack_ll_b32_b16 s2, s3, s2
+; GFX12-SDAG-TRUE16-NEXT:    s_mov_b32 s3, s6
+; GFX12-SDAG-TRUE16-NEXT:    s_mov_b32 s4, s5
+; GFX12-SDAG-TRUE16-NEXT:    s_mov_b32 s5, s7
+; GFX12-SDAG-TRUE16-NEXT:    s_mov_b32 s6, s8
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX12-SDAG-TRUE16-NEXT:    s_pack_ll_b32_b16 s4, s4, s5
+; GFX12-SDAG-TRUE16-NEXT:    s_pack_ll_b32_b16 s3, s3, s6
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX12-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s2
+; GFX12-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v6, s0
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v7, s1
+; GFX12-SDAG-TRUE16-NEXT:    s_mov_b32 s15, s12
+; GFX12-SDAG-TRUE16-NEXT:    s_mov_b32 s14, s11
+; GFX12-SDAG-TRUE16-NEXT:    s_mov_b32 s13, s10
+; GFX12-SDAG-TRUE16-NEXT:    s_mov_b32 s12, s9
+; GFX12-SDAG-TRUE16-NEXT:    image_bvh_intersect_ray v[0:3], [v6, v7, v[0:2], v[3:5]], s[12:15] a16
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-SDAG-FAKE16-LABEL: image_bvh_intersect_ray_a16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12-SDAG-FAKE16-NEXT:    s_lshr_b32 s2, s7, 16
+; GFX12-SDAG-FAKE16-NEXT:    s_lshr_b32 s3, s5, 16
+; GFX12-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v7, s1
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX12-SDAG-FAKE16-NEXT:    s_pack_ll_b32_b16 s2, s3, s2
+; GFX12-SDAG-FAKE16-NEXT:    s_pack_ll_b32_b16 s3, s5, s7
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX12-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s3
+; GFX12-SDAG-FAKE16-NEXT:    s_pack_ll_b32_b16 s4, s6, s8
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX12-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s4
+; GFX12-SDAG-FAKE16-NEXT:    s_mov_b32 s15, s12
+; GFX12-SDAG-FAKE16-NEXT:    s_mov_b32 s14, s11
+; GFX12-SDAG-FAKE16-NEXT:    s_mov_b32 s13, s10
+; GFX12-SDAG-FAKE16-NEXT:    s_mov_b32 s12, s9
+; GFX12-SDAG-FAKE16-NEXT:    image_bvh_intersect_ray v[0:3], [v6, v7, v[0:2], v[3:5]], s[12:15] a16
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-TRUE16-LABEL: image_bvh_intersect_ray_a16:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-GISEL-TRUE16-NEXT:    s_mov_b32 s20, s2
+; GFX12-GISEL-TRUE16-NEXT:    s_mov_b32 s22, s4
+; GFX12-GISEL-TRUE16-NEXT:    s_pack_ll_b32_b16 s4, s7, s5
+; GFX12-GISEL-TRUE16-NEXT:    s_mov_b32 s21, s3
+; GFX12-GISEL-TRUE16-NEXT:    s_pack_ll_b32_b16 s6, s8, s6
+; GFX12-GISEL-TRUE16-NEXT:    s_mov_b32 s5, s4
+; GFX12-GISEL-TRUE16-NEXT:    v_dual_mov_b32 v0, s20 :: v_dual_mov_b32 v1, s21
+; GFX12-GISEL-TRUE16-NEXT:    v_dual_mov_b32 v2, s22 :: v_dual_mov_b32 v3, s4
+; GFX12-GISEL-TRUE16-NEXT:    v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v7, s1
+; GFX12-GISEL-TRUE16-NEXT:    v_dual_mov_b32 v4, s5 :: v_dual_mov_b32 v5, s6
+; GFX12-GISEL-TRUE16-NEXT:    s_mov_b32 s16, s9
+; GFX12-GISEL-TRUE16-NEXT:    s_mov_b32 s17, s10
+; GFX12-GISEL-TRUE16-NEXT:    s_mov_b32 s18, s11
+; GFX12-GISEL-TRUE16-NEXT:    s_mov_b32 s19, s12
+; GFX12-GISEL-TRUE16-NEXT:    image_bvh_intersect_ray v[0:3], [v6, v7, v[0:2], v[3:5]], s[16:19] a16
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-FAKE16-LABEL: image_bvh_intersect_ray_a16:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-GISEL-FAKE16-NEXT:    s_mov_b32 s20, s2
+; GFX12-GISEL-FAKE16-NEXT:    s_mov_b32 s22, s4
+; GFX12-GISEL-FAKE16-NEXT:    s_pack_ll_b32_b16 s4, s7, s5
+; GFX12-GISEL-FAKE16-NEXT:    s_mov_b32 s21, s3
+; GFX12-GISEL-FAKE16-NEXT:    s_pack_hh_b32_b16 s5, s7, s5
+; GFX12-GISEL-FAKE16-NEXT:    s_pack_ll_b32_b16 s6, s8, s6
+; GFX12-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v0, s20 :: v_dual_mov_b32 v1, s21
+; GFX12-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v2, s22 :: v_dual_mov_b32 v3, s4
+; GFX12-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v7, s1
+; GFX12-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v4, s5 :: v_dual_mov_b32 v5, s6
+; GFX12-GISEL-FAKE16-NEXT:    s_mov_b32 s16, s9
+; GFX12-GISEL-FAKE16-NEXT:    s_mov_b32 s17, s10
+; GFX12-GISEL-FAKE16-NEXT:    s_mov_b32 s18, s11
+; GFX12-GISEL-FAKE16-NEXT:    s_mov_b32 s19, s12
+; GFX12-GISEL-FAKE16-NEXT:    image_bvh_intersect_ray v[0:3], [v6, v7, v[0:2], v[3:5]], s[16:19] a16
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
   %r = bitcast <4 x i32> %v to <4 x float>
@@ -189,70 +263,142 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16(i64 inreg %node_ptr,
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: image_bvh64_intersect_ray_a16:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s4
-; GFX11-NEXT:    v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v7, s1
-; GFX11-NEXT:    s_lshr_b32 s3, s6, 16
-; GFX11-NEXT:    s_pack_ll_b32_b16 s1, s6, s8
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT:    v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v3, s1
-; GFX11-NEXT:    s_lshr_b32 s0, s8, 16
-; GFX11-NEXT:    v_mov_b32_e32 v8, s2
-; GFX11-NEXT:    s_pack_ll_b32_b16 s0, s3, s0
-; GFX11-NEXT:    s_pack_ll_b32_b16 s3, s7, s9
-; GFX11-NEXT:    v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v5, s3
-; GFX11-NEXT:    s_mov_b32 s15, s13
-; GFX11-NEXT:    s_mov_b32 s14, s12
-; GFX11-NEXT:    s_mov_b32 s13, s11
-; GFX11-NEXT:    s_mov_b32 s12, s10
-; GFX11-NEXT:    image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[0:2], v[3:5]], s[12:15] a16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: image_bvh64_intersect_ray_a16:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s4
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v6, s0
+; GFX11-TRUE16-NEXT:    s_lshr_b32 s0, s8, 16
+; GFX11-TRUE16-NEXT:    s_lshr_b32 s3, s6, 16
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v7, s1
+; GFX11-TRUE16-NEXT:    s_pack_ll_b32_b16 s0, s3, s0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, s7
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s8
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s9
+; GFX11-TRUE16-NEXT:    s_pack_ll_b32_b16 s3, s3, s4
+; GFX11-TRUE16-NEXT:    s_pack_ll_b32_b16 s1, s1, s5
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v3, s3 :: v_dual_mov_b32 v4, s0
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v5, s1 :: v_dual_mov_b32 v8, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s15, s13
+; GFX11-TRUE16-NEXT:    s_mov_b32 s14, s12
+; GFX11-TRUE16-NEXT:    s_mov_b32 s13, s11
+; GFX11-TRUE16-NEXT:    s_mov_b32 s12, s10
+; GFX11-TRUE16-NEXT:    image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[0:2], v[3:5]], s[12:15] a16
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-SDAG-LABEL: image_bvh64_intersect_ray_a16:
-; GFX12-SDAG:       ; %bb.0: ; %main_body
-; GFX12-SDAG-NEXT:    v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s4
-; GFX12-SDAG-NEXT:    v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v7, s1
-; GFX12-SDAG-NEXT:    s_lshr_b32 s3, s6, 16
-; GFX12-SDAG-NEXT:    s_pack_ll_b32_b16 s1, s6, s8
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffe
-; GFX12-SDAG-NEXT:    v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v3, s1
-; GFX12-SDAG-NEXT:    s_lshr_b32 s0, s8, 16
-; GFX12-SDAG-NEXT:    v_mov_b32_e32 v8, s2
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffe
-; GFX12-SDAG-NEXT:    s_pack_ll_b32_b16 s0, s3, s0
-; GFX12-SDAG-NEXT:    s_pack_ll_b32_b16 s3, s7, s9
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffe
-; GFX12-SDAG-NEXT:    v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v5, s3
-; GFX12-SDAG-NEXT:    s_mov_b32 s15, s13
-; GFX12-SDAG-NEXT:    s_mov_b32 s14, s12
-; GFX12-SDAG-NEXT:    s_mov_b32 s13, s11
-; GFX12-SDAG-NEXT:    s_mov_b32 s12, s10
-; GFX12-SDAG-NEXT:    image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[0:2], v[3:5]], s[12:15] a16
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    ; return to shader part epilog
+; GFX11-FAKE16-LABEL: image_bvh64_intersect_ray_a16:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s4
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v7, s1
+; GFX11-FAKE16-NEXT:    s_lshr_b32 s3, s6, 16
+; GFX11-FAKE16-NEXT:    s_pack_ll_b32_b16 s1, s6, s8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v3, s1
+; GFX11-FAKE16-NEXT:    s_lshr_b32 s0, s8, 16
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, s2
+; GFX11-FAKE16-NEXT:    s_pack_ll_b32_b16 s0, s3, s0
+; GFX11-FAKE16-NEXT:    s_pack_ll_b32_b16 s3, s7, s9
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v5, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s15, s13
+; GFX11-FAKE16-NEXT:    s_mov_b32 s14, s12
+; GFX11-FAKE16-NEXT:    s_mov_b32 s13, s11
+; GFX11-FAKE16-NEXT:    s_mov_b32 s12, s10
+; GFX11-FAKE16-NEXT:    image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[0:2], v[3:5]], s[12:15] a16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-GISEL-LABEL: image_bvh64_intersect_ray_a16:
-; GFX12-GISEL:       ; %bb.0: ; %main_body
-; GFX12-GISEL-NEXT:    s_mov_b32 s20, s3
-; GFX12-GISEL-NEXT:    s_mov_b32 s21, s4
-; GFX12-GISEL-NEXT:    s_pack_ll_b32_b16 s4, s8, s6
-; GFX12-GISEL-NEXT:    s_mov_b32 s22, s5
-; GFX12-GISEL-NEXT:    s_pack_hh_b32_b16 s5, s8, s6
-; GFX12-GISEL-NEXT:    s_pack_ll_b32_b16 s6, s9, s7
-; GFX12-GISEL-NEXT:    v_dual_mov_b32 v0, s20 :: v_dual_mov_b32 v3, s4
-; GFX12-GISEL-NEXT:    v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
-; GFX12-GISEL-NEXT:    v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v1, s21
-; GFX12-GISEL-NEXT:    v_dual_mov_b32 v2, s22 :: v_dual_mov_b32 v5, s6
-; GFX12-GISEL-NEXT:    v_mov_b32_e32 v4, s5
-; GFX12-GISEL-NEXT:    s_mov_b32 s16, s10
-; GFX12-GISEL-NEXT:    s_mov_b32 s17, s11
-; GFX12-GISEL-NEXT:    s_mov_b32 s18, s12
-; GFX12-GISEL-NEXT:    s_mov_b32 s19, s13
-; GFX12-GISEL-NEXT:    image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[0:2], v[3:5]], s[16:19] a16
-; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT:    ; return to shader part epilog
+; GFX12-SDAG-TRUE16-LABEL: image_bvh64_intersect_ray_a16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s4
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v6, s0
+; GFX12-SDAG-TRUE16-NEXT:    s_lshr_b32 s0, s8, 16
+; GFX12-SDAG-TRUE16-NEXT:    s_lshr_b32 s3, s6, 16
+; GFX12-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v7, s1
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX12-SDAG-TRUE16-NEXT:    s_pack_ll_b32_b16 s0, s3, s0
+; GFX12-SDAG-TRUE16-NEXT:    s_mov_b32 s1, s7
+; GFX12-SDAG-TRUE16-NEXT:    s_mov_b32 s3, s6
+; GFX12-SDAG-TRUE16-NEXT:    s_mov_b32 s4, s8
+; GFX12-SDAG-TRUE16-NEXT:    s_mov_b32 s5, s9
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX12-SDAG-TRUE16-NEXT:    s_pack_ll_b32_b16 s3, s3, s4
+; GFX12-SDAG-TRUE16-NEXT:    s_pack_ll_b32_b16 s1, s1, s5
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX12-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v3, s3 :: v_dual_mov_b32 v4, s0
+; GFX12-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v5, s1 :: v_dual_mov_b32 v8, s2
+; GFX12-SDAG-TRUE16-NEXT:    s_mov_b32 s15, s13
+; GFX12-SDAG-TRUE16-NEXT:    s_mov_b32 s14, s12
+; GFX12-SDAG-TRUE16-NEXT:    s_mov_b32 s13, s11
+; GFX12-SDAG-TRUE16-NEXT:    s_mov_b32 s12, s10
+; GFX12-SDAG-TRUE16-NEXT:    image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[0:2], v[3:5]], s[12:15] a16
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-SDAG-FAKE16-LABEL: image_bvh64_intersect_ray_a16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s4
+; GFX12-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v7, s1
+; GFX12-SDAG-FAKE16-NEXT:    s_lshr_b32 s3, s6, 16
+; GFX12-SDAG-FAKE16-NEXT:    s_pack_ll_b32_b16 s1, s6, s8
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX12-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v3, s1
+; GFX12-SDAG-FAKE16-NEXT:    s_lshr_b32 s0, s8, 16
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v8, s2
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX12-SDAG-FAKE16-NEXT:    s_pack_ll_b32_b16 s0, s3, s0
+; GFX12-SDAG-FAKE16-NEXT:    s_pack_ll_b32_b16 s3, s7, s9
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX12-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v5, s3
+; GFX12-SDAG-FAKE16-NEXT:    s_mov_b32 s15, s13
+; GFX12-SDAG-FAKE16-NEXT:    s_mov_b32 s14, s12
+; GFX12-SDAG-FAKE16-NEXT:    s_mov_b32 s13, s11
+; GFX12-SDAG-FAKE16-NEXT:    s_mov_b32 s12, s10
+; GFX12-SDAG-FAKE16-NEXT:    image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[0:2], v[3:5]], s[12:15] a16
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-TRUE16-LABEL: image_bvh64_intersect_ray_a16:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-GISEL-TRUE16-NEXT:    s_mov_b32 s21, s4
+; GFX12-GISEL-TRUE16-NEXT:    s_pack_ll_b32_b16 s4, s8, s6
+; GFX12-GISEL-TRUE16-NEXT:    s_mov_b32 s20, s3
+; GFX12-GISEL-TRUE16-NEXT:    s_mov_b32 s22, s5
+; GFX12-GISEL-TRUE16-NEXT:    s_pack_ll_b32_b16 s6, s9, s7
+; GFX12-GISEL-TRUE16-NEXT:    s_mov_b32 s5, s4
+; GFX12-GISEL-TRUE16-NEXT:    v_dual_mov_b32 v0, s20 :: v_dual_mov_b32 v3, s4
+; GFX12-GISEL-TRUE16-NEXT:    v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
+; GFX12-GISEL-TRUE16-NEXT:    v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v1, s21
+; GFX12-GISEL-TRUE16-NEXT:    v_dual_mov_b32 v2, s22 :: v_dual_mov_b32 v5, s6
+; GFX12-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v4, s5
+; GFX12-GISEL-TRUE16-NEXT:    s_mov_b32 s16, s10
+; GFX12-GISEL-TRUE16-NEXT:    s_mov_b32 s17, s11
+; GFX12-GISEL-TRUE16-NEXT:    s_mov_b32 s18, s12
+; GFX12-GISEL-TRUE16-NEXT:    s_mov_b32 s19, s13
+; GFX12-GISEL-TRUE16-NEXT:    image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[0:2], v[3:5]], s[16:19] a16
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-GISEL-FAKE16-LABEL: image_bvh64_intersect_ray_a16:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-GISEL-FAKE16-NEXT:    s_mov_b32 s20, s3
+; GFX12-GISEL-FAKE16-NEXT:    s_mov_b32 s21, s4
+; GFX12-GISEL-FAKE16-NEXT:    s_pack_ll_b32_b16 s4, s8, s6
+; GFX12-GISEL-FAKE16-NEXT:    s_mov_b32 s22, s5
+; GFX12-GISEL-FAKE16-NEXT:    s_pack_hh_b32_b16 s5, s8, s6
+; GFX12-GISEL-FAKE16-NEXT:    s_pack_ll_b32_b16 s6, s9, s7
+; GFX12-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v0, s20 :: v_dual_mov_b32 v3, s4
+; GFX12-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
+; GFX12-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v1, s21
+; GFX12-GISEL-FAKE16-NEXT:    v_dual_mov_b32 v2, s22 :: v_dual_mov_b32 v5, s6
+; GFX12-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v4, s5
+; GFX12-GISEL-FAKE16-NEXT:    s_mov_b32 s16, s10
+; GFX12-GISEL-FAKE16-NEXT:    s_mov_b32 s17, s11
+; GFX12-GISEL-FAKE16-NEXT:    s_mov_b32 s18, s12
+; GFX12-GISEL-FAKE16-NEXT:    s_mov_b32 s19, s13
+; GFX12-GISEL-FAKE16-NEXT:    image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[0:2], v[3:5]], s[16:19] a16
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
   %r = bitcast <4 x i32> %v to <4 x float>
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
index 4edd0357c6e7a..9e1815b48abfd 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
@@ -240,8 +240,6 @@ bb1:
   ret void
 }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; CI: {{.*}}
 ; GFX10-GISEL: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
index 9d078f7906b4d..c364c391559ea 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
@@ -307,8 +307,6 @@ bb1:
   ret void
 }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; CI: {{.*}}
 ; GFX10-GISEL: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
index 46829b07f265d..30b7b3b472f08 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 | FileCheck %s -check-prefix=CHECK
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 | FileCheck %s -check-prefix=CHECK
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 | FileCheck %s -check-prefixes=CHECK,CHECK-SDAG-TRUE16
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 | FileCheck %s -check-prefixes=CHECK,CHECK-FAKE16
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 | FileCheck %s -check-prefixes=CHECK,CHECK-GISEL-TRUE16
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 | FileCheck %s -check-prefixes=CHECK,CHECK-FAKE16
 
 define amdgpu_kernel void @raw_atomic_buffer_load_i32(<4 x i32> %addr) {
 ; CHECK-LABEL: raw_atomic_buffer_load_i32:
@@ -207,26 +209,66 @@ bb2:
 }
 
 define amdgpu_kernel void @raw_atomic_buffer_load_v4i16(<4 x i32> %addr) {
-; CHECK-LABEL: raw_atomic_buffer_load_v4i16:
-; CHECK:       ; %bb.0: ; %bb
-; CHECK-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; CHECK-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; CHECK-NEXT:    s_mov_b32 s4, 0
-; CHECK-NEXT:  .LBB7_1: ; %bb1
-; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
-; CHECK-NEXT:    buffer_load_b64 v[1:2], off, s[0:3], 0 offset:4 glc
-; CHECK-NEXT:    s_waitcnt vmcnt(0)
-; CHECK-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; CHECK-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; CHECK-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v1, v0
-; CHECK-NEXT:    s_or_b32 s4, vcc_lo, s4
-; CHECK-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; CHECK-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s4
-; CHECK-NEXT:    s_cbranch_execnz .LBB7_1
-; CHECK-NEXT:  ; %bb.2: ; %bb2
-; CHECK-NEXT:    s_endpgm
+; CHECK-SDAG-TRUE16-LABEL: raw_atomic_buffer_load_v4i16:
+; CHECK-SDAG-TRUE16:       ; %bb.0: ; %bb
+; CHECK-SDAG-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; CHECK-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; CHECK-SDAG-TRUE16-NEXT:    s_mov_b32 s4, 0
+; CHECK-SDAG-TRUE16-NEXT:  .LBB7_1: ; %bb1
+; CHECK-SDAG-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CHECK-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-SDAG-TRUE16-NEXT:    buffer_load_b64 v[1:2], off, s[0:3], 0 offset:4 glc
+; CHECK-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; CHECK-SDAG-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; CHECK-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; CHECK-SDAG-TRUE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; CHECK-SDAG-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v1, v0
+; CHECK-SDAG-TRUE16-NEXT:    s_or_b32 s4, vcc_lo, s4
+; CHECK-SDAG-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; CHECK-SDAG-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s4
+; CHECK-SDAG-TRUE16-NEXT:    s_cbranch_execnz .LBB7_1
+; CHECK-SDAG-TRUE16-NEXT:  ; %bb.2: ; %bb2
+; CHECK-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; CHECK-FAKE16-LABEL: raw_atomic_buffer_load_v4i16:
+; CHECK-FAKE16:       ; %bb.0: ; %bb
+; CHECK-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; CHECK-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; CHECK-FAKE16-NEXT:    s_mov_b32 s4, 0
+; CHECK-FAKE16-NEXT:  .LBB7_1: ; %bb1
+; CHECK-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CHECK-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-FAKE16-NEXT:    buffer_load_b64 v[1:2], off, s[0:3], 0 offset:4 glc
+; CHECK-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; CHECK-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; CHECK-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; CHECK-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; CHECK-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v1, v0
+; CHECK-FAKE16-NEXT:    s_or_b32 s4, vcc_lo, s4
+; CHECK-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; CHECK-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s4
+; CHECK-FAKE16-NEXT:    s_cbranch_execnz .LBB7_1
+; CHECK-FAKE16-NEXT:  ; %bb.2: ; %bb2
+; CHECK-FAKE16-NEXT:    s_endpgm
+;
+; CHECK-GISEL-TRUE16-LABEL: raw_atomic_buffer_load_v4i16:
+; CHECK-GISEL-TRUE16:       ; %bb.0: ; %bb
+; CHECK-GISEL-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; CHECK-GISEL-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; CHECK-GISEL-TRUE16-NEXT:    s_mov_b32 s4, 0
+; CHECK-GISEL-TRUE16-NEXT:  .LBB7_1: ; %bb1
+; CHECK-GISEL-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CHECK-GISEL-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-GISEL-TRUE16-NEXT:    buffer_load_b64 v[1:2], off, s[0:3], 0 offset:4 glc
+; CHECK-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; CHECK-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; CHECK-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; CHECK-GISEL-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v1, v0
+; CHECK-GISEL-TRUE16-NEXT:    s_or_b32 s4, vcc_lo, s4
+; CHECK-GISEL-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s4
+; CHECK-GISEL-TRUE16-NEXT:    s_cbranch_execnz .LBB7_1
+; CHECK-GISEL-TRUE16-NEXT:  ; %bb.2: ; %bb2
+; CHECK-GISEL-TRUE16-NEXT:    s_endpgm
 bb:
   %id = tail call i32 @llvm.amdgcn.workitem.id.x()
   br label %bb1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
index 4813a71f5c7b5..643805d6be93e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 | FileCheck %s -check-prefix=CHECK
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 | FileCheck %s -check-prefix=CHECK
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 | FileCheck %s -check-prefixes=CHECK,CHECK-SDAG-TRUE16
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 | FileCheck %s -check-prefixes=CHECK,CHECK-FAKE16
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 | FileCheck %s -check-prefixes=CHECK,CHECK-GISEL-TRUE16
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 | FileCheck %s -check-prefixes=CHECK,CHECK-FAKE16
 
 define amdgpu_kernel void @raw_ptr_atomic_buffer_ptr_load_i32(ptr addrspace(8) %ptr) {
 ; CHECK-LABEL: raw_ptr_atomic_buffer_ptr_load_i32:
@@ -207,26 +209,66 @@ bb2:
 }
 
 define amdgpu_kernel void @raw_ptr_atomic_buffer_load_v4i16(ptr addrspace(8) %ptr) {
-; CHECK-LABEL: raw_ptr_atomic_buffer_load_v4i16:
-; CHECK:       ; %bb.0: ; %bb
-; CHECK-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; CHECK-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; CHECK-NEXT:    s_mov_b32 s4, 0
-; CHECK-NEXT:  .LBB7_1: ; %bb1
-; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
-; CHECK-NEXT:    buffer_load_b64 v[1:2], off, s[0:3], 0 offset:4 glc
-; CHECK-NEXT:    s_waitcnt vmcnt(0)
-; CHECK-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; CHECK-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; CHECK-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v1, v0
-; CHECK-NEXT:    s_or_b32 s4, vcc_lo, s4
-; CHECK-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; CHECK-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s4
-; CHECK-NEXT:    s_cbranch_execnz .LBB7_1
-; CHECK-NEXT:  ; %bb.2: ; %bb2
-; CHECK-NEXT:    s_endpgm
+; CHECK-SDAG-TRUE16-LABEL: raw_ptr_atomic_buffer_load_v4i16:
+; CHECK-SDAG-TRUE16:       ; %bb.0: ; %bb
+; CHECK-SDAG-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; CHECK-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; CHECK-SDAG-TRUE16-NEXT:    s_mov_b32 s4, 0
+; CHECK-SDAG-TRUE16-NEXT:  .LBB7_1: ; %bb1
+; CHECK-SDAG-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CHECK-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-SDAG-TRUE16-NEXT:    buffer_load_b64 v[1:2], off, s[0:3], 0 offset:4 glc
+; CHECK-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; CHECK-SDAG-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; CHECK-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; CHECK-SDAG-TRUE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; CHECK-SDAG-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v1, v0
+; CHECK-SDAG-TRUE16-NEXT:    s_or_b32 s4, vcc_lo, s4
+; CHECK-SDAG-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; CHECK-SDAG-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s4
+; CHECK-SDAG-TRUE16-NEXT:    s_cbranch_execnz .LBB7_1
+; CHECK-SDAG-TRUE16-NEXT:  ; %bb.2: ; %bb2
+; CHECK-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; CHECK-FAKE16-LABEL: raw_ptr_atomic_buffer_load_v4i16:
+; CHECK-FAKE16:       ; %bb.0: ; %bb
+; CHECK-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; CHECK-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; CHECK-FAKE16-NEXT:    s_mov_b32 s4, 0
+; CHECK-FAKE16-NEXT:  .LBB7_1: ; %bb1
+; CHECK-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CHECK-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-FAKE16-NEXT:    buffer_load_b64 v[1:2], off, s[0:3], 0 offset:4 glc
+; CHECK-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; CHECK-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; CHECK-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; CHECK-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; CHECK-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v1, v0
+; CHECK-FAKE16-NEXT:    s_or_b32 s4, vcc_lo, s4
+; CHECK-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; CHECK-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s4
+; CHECK-FAKE16-NEXT:    s_cbranch_execnz .LBB7_1
+; CHECK-FAKE16-NEXT:  ; %bb.2: ; %bb2
+; CHECK-FAKE16-NEXT:    s_endpgm
+;
+; CHECK-GISEL-TRUE16-LABEL: raw_ptr_atomic_buffer_load_v4i16:
+; CHECK-GISEL-TRUE16:       ; %bb.0: ; %bb
+; CHECK-GISEL-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; CHECK-GISEL-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; CHECK-GISEL-TRUE16-NEXT:    s_mov_b32 s4, 0
+; CHECK-GISEL-TRUE16-NEXT:  .LBB7_1: ; %bb1
+; CHECK-GISEL-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CHECK-GISEL-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-GISEL-TRUE16-NEXT:    buffer_load_b64 v[1:2], off, s[0:3], 0 offset:4 glc
+; CHECK-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; CHECK-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; CHECK-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; CHECK-GISEL-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v1, v0
+; CHECK-GISEL-TRUE16-NEXT:    s_or_b32 s4, vcc_lo, s4
+; CHECK-GISEL-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s4
+; CHECK-GISEL-TRUE16-NEXT:    s_cbranch_execnz .LBB7_1
+; CHECK-GISEL-TRUE16-NEXT:  ; %bb.2: ; %bb2
+; CHECK-GISEL-TRUE16-NEXT:    s_endpgm
 bb:
   %id = tail call i32 @llvm.amdgcn.workitem.id.x()
   br label %bb1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.d16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.d16.ll
index cc75531e4953e..3fd100d4a7c89 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.d16.ll
@@ -3,7 +3,8 @@
 ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=PREGFX10-PACKED %s
 ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=PREGFX10-PACKED %s
 ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX10-PACKED %s
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX11-PACKED %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX11-PACKED,GFX11-PACKED-TRUE16 %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX11-PACKED,GFX11-PACKED-FAKE16 %s
 
 define amdgpu_ps half @tbuffer_load_d16_x(ptr addrspace(8) inreg %rsrc) {
 ; PREGFX10-UNPACKED-LABEL: tbuffer_load_d16_x:
@@ -90,12 +91,19 @@ define amdgpu_ps half @tbuffer_load_d16_xyz(ptr addrspace(8) inreg %rsrc) {
 ; GFX10-PACKED-NEXT:    v_mov_b32_e32 v0, v1
 ; GFX10-PACKED-NEXT:    ; return to shader part epilog
 ;
-; GFX11-PACKED-LABEL: tbuffer_load_d16_xyz:
-; GFX11-PACKED:       ; %bb.0: ; %main_body
-; GFX11-PACKED-NEXT:    tbuffer_load_d16_format_xyz v[0:1], off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
-; GFX11-PACKED-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-PACKED-NEXT:    v_mov_b32_e32 v0, v1
-; GFX11-PACKED-NEXT:    ; return to shader part epilog
+; GFX11-PACKED-TRUE16-LABEL: tbuffer_load_d16_xyz:
+; GFX11-PACKED-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-PACKED-TRUE16-NEXT:    tbuffer_load_d16_format_xyz v[0:1], off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
+; GFX11-PACKED-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-PACKED-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v1.l
+; GFX11-PACKED-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-PACKED-FAKE16-LABEL: tbuffer_load_d16_xyz:
+; GFX11-PACKED-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-PACKED-FAKE16-NEXT:    tbuffer_load_d16_format_xyz v[0:1], off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
+; GFX11-PACKED-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-PACKED-FAKE16-NEXT:    v_mov_b32_e32 v0, v1
+; GFX11-PACKED-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %data = call <3 x half> @llvm.amdgcn.raw.ptr.tbuffer.load.v3f16(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 22, i32 0)
   %elt = extractelement <3 x half> %data, i32 2
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
index d976c7992aff5..aad3532172e10 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
@@ -189,7 +189,7 @@ define amdgpu_kernel void @tbuffer_store_d16_xyz(<4 x i32> %rsrc, <4 x half> %da
 ; GFX12-PACKED-GISEL-NEXT:    s_wait_kmcnt 0x0
 ; GFX12-PACKED-GISEL-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX12-PACKED-GISEL-NEXT:    v_mov_b32_e32 v1, s7
-; GFX12-PACKED-GISEL-NEXT:    tbuffer_store_d16_format_xyzw v[0:1], off, s[0:3], null format:[BUF_FMT_10_10_10_2_SNORM]
+; GFX12-PACKED-GISEL-NEXT:    tbuffer_store_d16_format_xyz v[0:1], off, s[0:3], null format:[BUF_FMT_10_10_10_2_SNORM]
 ; GFX12-PACKED-GISEL-NEXT:    s_endpgm
 main_body:
   %data_subvec = shufflevector <4 x half> %data, <4 x half> poison, <3 x i32> <i32 0, i32 1, i32 2>
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
index eb2d95e4db2d5..2d8e9f2ab39e4 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefix=CHECK
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefix=CHECK
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck %s -check-prefixes=CHECK,CHECK-SDAG-TRUE16
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck %s -check-prefixes=CHECK,CHECK-FAKE16
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck %s -check-prefixes=CHECK,CHECK-GISEL-TRUE16
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck %s -check-prefixes=CHECK,CHECK-FAKE16
 
 define amdgpu_kernel void @struct_atomic_buffer_load_i32(<4 x i32> %addr, i32 %index) {
 ; CHECK-LABEL: struct_atomic_buffer_load_i32:
@@ -257,29 +259,75 @@ bb2:
 }
 
 define amdgpu_kernel void @struct_atomic_buffer_load_v4i16(<4 x i32> %addr, i32 %index) {
-; CHECK-LABEL: struct_atomic_buffer_load_v4i16:
-; CHECK:       ; %bb.0: ; %bb
-; CHECK-NEXT:    s_clause 0x1
-; CHECK-NEXT:    s_load_b32 s6, s[4:5], 0x34
-; CHECK-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; CHECK-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; CHECK-NEXT:    s_mov_b32 s4, 0
-; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
-; CHECK-NEXT:    v_mov_b32_e32 v1, s6
-; CHECK-NEXT:  .LBB8_1: ; %bb1
-; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    buffer_load_b64 v[2:3], v1, s[0:3], 0 idxen offset:4 glc
-; CHECK-NEXT:    s_waitcnt vmcnt(0)
-; CHECK-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; CHECK-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; CHECK-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v2, v0
-; CHECK-NEXT:    s_or_b32 s4, vcc_lo, s4
-; CHECK-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; CHECK-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s4
-; CHECK-NEXT:    s_cbranch_execnz .LBB8_1
-; CHECK-NEXT:  ; %bb.2: ; %bb2
-; CHECK-NEXT:    s_endpgm
+; CHECK-SDAG-TRUE16-LABEL: struct_atomic_buffer_load_v4i16:
+; CHECK-SDAG-TRUE16:       ; %bb.0: ; %bb
+; CHECK-SDAG-TRUE16-NEXT:    s_clause 0x1
+; CHECK-SDAG-TRUE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; CHECK-SDAG-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; CHECK-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; CHECK-SDAG-TRUE16-NEXT:    s_mov_b32 s4, 0
+; CHECK-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v1, s6
+; CHECK-SDAG-TRUE16-NEXT:  .LBB8_1: ; %bb1
+; CHECK-SDAG-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CHECK-SDAG-TRUE16-NEXT:    buffer_load_b64 v[2:3], v1, s[0:3], 0 idxen offset:4 glc
+; CHECK-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; CHECK-SDAG-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; CHECK-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; CHECK-SDAG-TRUE16-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
+; CHECK-SDAG-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v2, v0
+; CHECK-SDAG-TRUE16-NEXT:    s_or_b32 s4, vcc_lo, s4
+; CHECK-SDAG-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; CHECK-SDAG-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s4
+; CHECK-SDAG-TRUE16-NEXT:    s_cbranch_execnz .LBB8_1
+; CHECK-SDAG-TRUE16-NEXT:  ; %bb.2: ; %bb2
+; CHECK-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; CHECK-FAKE16-LABEL: struct_atomic_buffer_load_v4i16:
+; CHECK-FAKE16:       ; %bb.0: ; %bb
+; CHECK-FAKE16-NEXT:    s_clause 0x1
+; CHECK-FAKE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; CHECK-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; CHECK-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; CHECK-FAKE16-NEXT:    s_mov_b32 s4, 0
+; CHECK-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-FAKE16-NEXT:    v_mov_b32_e32 v1, s6
+; CHECK-FAKE16-NEXT:  .LBB8_1: ; %bb1
+; CHECK-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CHECK-FAKE16-NEXT:    buffer_load_b64 v[2:3], v1, s[0:3], 0 idxen offset:4 glc
+; CHECK-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; CHECK-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; CHECK-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; CHECK-FAKE16-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
+; CHECK-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v2, v0
+; CHECK-FAKE16-NEXT:    s_or_b32 s4, vcc_lo, s4
+; CHECK-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; CHECK-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s4
+; CHECK-FAKE16-NEXT:    s_cbranch_execnz .LBB8_1
+; CHECK-FAKE16-NEXT:  ; %bb.2: ; %bb2
+; CHECK-FAKE16-NEXT:    s_endpgm
+;
+; CHECK-GISEL-TRUE16-LABEL: struct_atomic_buffer_load_v4i16:
+; CHECK-GISEL-TRUE16:       ; %bb.0: ; %bb
+; CHECK-GISEL-TRUE16-NEXT:    s_clause 0x1
+; CHECK-GISEL-TRUE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; CHECK-GISEL-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; CHECK-GISEL-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; CHECK-GISEL-TRUE16-NEXT:    s_mov_b32 s4, 0
+; CHECK-GISEL-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v1, s6
+; CHECK-GISEL-TRUE16-NEXT:  .LBB8_1: ; %bb1
+; CHECK-GISEL-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CHECK-GISEL-TRUE16-NEXT:    buffer_load_b64 v[2:3], v1, s[0:3], 0 idxen offset:4 glc
+; CHECK-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; CHECK-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; CHECK-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; CHECK-GISEL-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v2, v0
+; CHECK-GISEL-TRUE16-NEXT:    s_or_b32 s4, vcc_lo, s4
+; CHECK-GISEL-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s4
+; CHECK-GISEL-TRUE16-NEXT:    s_cbranch_execnz .LBB8_1
+; CHECK-GISEL-TRUE16-NEXT:  ; %bb.2: ; %bb2
+; CHECK-GISEL-TRUE16-NEXT:    s_endpgm
 bb:
   %id = tail call i32 @llvm.amdgcn.workitem.id.x()
   br label %bb1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
index ffa598d634e43..701b80d59bcc6 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
@@ -2,8 +2,10 @@
 ; RUN: llc -mcpu=gfx1010 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
 ; RUN: llc -mcpu=gfx900 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s
 ; RUN: llc -mcpu=gfx810 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s
-; RUN: llc -mcpu=gfx1100 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11 %s
-; RUN: llc -mcpu=gfx1200 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -mcpu=gfx1100 -mattr=+real-true16 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mcpu=gfx1100 -mattr=-real-true16 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -mcpu=gfx1200 -mattr=+real-true16 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -mcpu=gfx1200 -mattr=-real-true16 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
 
 @esgs_ring = external addrspace(3) global [0 x i32], align 65536
 
@@ -88,58 +90,113 @@ define amdgpu_gs void @main(<4 x i32> %arg, i32 %arg1) {
 ; GFX8-NEXT:    s_mov_b32 m0, -1
 ; GFX8-NEXT:    ds_write2_b32 v2, v0, v1 offset0:7 offset1:8
 ;
-; GFX11-LABEL: main:
-; GFX11:       ; %bb.0: ; %bb
-; GFX11-NEXT:    s_mov_b32 s1, exec_lo
-; GFX11-NEXT:  .LBB0_1: ; =>This Inner Loop Header: Depth=1
-; GFX11-NEXT:    v_readfirstlane_b32 s4, v0
-; GFX11-NEXT:    v_readfirstlane_b32 s5, v1
-; GFX11-NEXT:    v_readfirstlane_b32 s6, v2
-; GFX11-NEXT:    v_readfirstlane_b32 s7, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
-; GFX11-NEXT:    v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
-; GFX11-NEXT:    s_and_b32 s0, vcc_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_saveexec_b32 s0, s0
-; GFX11-NEXT:    buffer_load_d16_format_xyz v[5:6], v4, s[4:7], 0 idxen
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr4
-; GFX11-NEXT:    s_xor_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB0_1
-; GFX11-NEXT:  ; %bb.2:
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v0, 16, v5
-; GFX11-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0xffff, v6
-; GFX11-NEXT:    ds_store_2addr_b32 v2, v0, v1 offset0:7 offset1:8
+; GFX11-TRUE16-LABEL: main:
+; GFX11-TRUE16:       ; %bb.0: ; %bb
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, exec_lo
+; GFX11-TRUE16-NEXT:  .LBB0_1: ; =>This Inner Loop Header: Depth=1
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s4, v0
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s5, v1
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s6, v2
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s7, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
+; GFX11-TRUE16-NEXT:    s_and_b32 s0, vcc_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    buffer_load_d16_format_xyz v[5:6], v4, s[4:7], 0 idxen
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-TRUE16-NEXT:    s_xor_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB0_1
+; GFX11-TRUE16-NEXT:  ; %bb.2:
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v5.h
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0xffff, v6
+; GFX11-TRUE16-NEXT:    ds_store_2addr_b32 v2, v0, v1 offset0:7 offset1:8
 ;
-; GFX12-LABEL: main:
-; GFX12:       ; %bb.0: ; %bb
-; GFX12-NEXT:    s_mov_b32 s1, exec_lo
-; GFX12-NEXT:  .LBB0_1: ; =>This Inner Loop Header: Depth=1
-; GFX12-NEXT:    v_readfirstlane_b32 s4, v0
-; GFX12-NEXT:    v_readfirstlane_b32 s5, v1
-; GFX12-NEXT:    v_readfirstlane_b32 s6, v2
-; GFX12-NEXT:    v_readfirstlane_b32 s7, v3
-; GFX12-NEXT:    s_wait_alu 0xf1ff
-; GFX12-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
-; GFX12-NEXT:    v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
-; GFX12-NEXT:    s_and_b32 s0, vcc_lo, s0
-; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT:    s_and_saveexec_b32 s0, s0
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    buffer_load_d16_format_xyz v[5:6], v4, s[4:7], null idxen
-; GFX12-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
-; GFX12-NEXT:    ; implicit-def: $vgpr4
-; GFX12-NEXT:    s_xor_b32 exec_lo, exec_lo, s0
-; GFX12-NEXT:    s_cbranch_execnz .LBB0_1
-; GFX12-NEXT:  ; %bb.2:
-; GFX12-NEXT:    s_mov_b32 exec_lo, s1
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v0, 16, v5
-; GFX12-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0xffff, v6
-; GFX12-NEXT:    ds_store_2addr_b32 v2, v0, v1 offset0:7 offset1:8
+; GFX11-FAKE16-LABEL: main:
+; GFX11-FAKE16:       ; %bb.0: ; %bb
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, exec_lo
+; GFX11-FAKE16-NEXT:  .LBB0_1: ; =>This Inner Loop Header: Depth=1
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s4, v0
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s5, v1
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s6, v2
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s7, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
+; GFX11-FAKE16-NEXT:    s_and_b32 s0, vcc_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    buffer_load_d16_format_xyz v[5:6], v4, s[4:7], 0 idxen
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT:    s_xor_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB0_1
+; GFX11-FAKE16-NEXT:  ; %bb.2:
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v5
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0xffff, v6
+; GFX11-FAKE16-NEXT:    ds_store_2addr_b32 v2, v0, v1 offset0:7 offset1:8
+;
+; GFX12-TRUE16-LABEL: main:
+; GFX12-TRUE16:       ; %bb.0: ; %bb
+; GFX12-TRUE16-NEXT:    s_mov_b32 s1, exec_lo
+; GFX12-TRUE16-NEXT:  .LBB0_1: ; =>This Inner Loop Header: Depth=1
+; GFX12-TRUE16-NEXT:    v_readfirstlane_b32 s4, v0
+; GFX12-TRUE16-NEXT:    v_readfirstlane_b32 s5, v1
+; GFX12-TRUE16-NEXT:    v_readfirstlane_b32 s6, v2
+; GFX12-TRUE16-NEXT:    v_readfirstlane_b32 s7, v3
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX12-TRUE16-NEXT:    v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
+; GFX12-TRUE16-NEXT:    s_and_b32 s0, vcc_lo, s0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-TRUE16-NEXT:    s_and_saveexec_b32 s0, s0
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    buffer_load_d16_format_xyz v[5:6], v4, s[4:7], null idxen
+; GFX12-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX12-TRUE16-NEXT:    ; implicit-def: $vgpr4
+; GFX12-TRUE16-NEXT:    s_xor_b32 exec_lo, exec_lo, s0
+; GFX12-TRUE16-NEXT:    s_cbranch_execnz .LBB0_1
+; GFX12-TRUE16-NEXT:  ; %bb.2:
+; GFX12-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, 0
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v5.h
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0xffff, v6
+; GFX12-TRUE16-NEXT:    ds_store_2addr_b32 v2, v0, v1 offset0:7 offset1:8
+;
+; GFX12-FAKE16-LABEL: main:
+; GFX12-FAKE16:       ; %bb.0: ; %bb
+; GFX12-FAKE16-NEXT:    s_mov_b32 s1, exec_lo
+; GFX12-FAKE16-NEXT:  .LBB0_1: ; =>This Inner Loop Header: Depth=1
+; GFX12-FAKE16-NEXT:    v_readfirstlane_b32 s4, v0
+; GFX12-FAKE16-NEXT:    v_readfirstlane_b32 s5, v1
+; GFX12-FAKE16-NEXT:    v_readfirstlane_b32 s6, v2
+; GFX12-FAKE16-NEXT:    v_readfirstlane_b32 s7, v3
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX12-FAKE16-NEXT:    v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
+; GFX12-FAKE16-NEXT:    s_and_b32 s0, vcc_lo, s0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-FAKE16-NEXT:    s_and_saveexec_b32 s0, s0
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    buffer_load_d16_format_xyz v[5:6], v4, s[4:7], null idxen
+; GFX12-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX12-FAKE16-NEXT:    ; implicit-def: $vgpr4
+; GFX12-FAKE16-NEXT:    s_xor_b32 exec_lo, exec_lo, s0
+; GFX12-FAKE16-NEXT:    s_cbranch_execnz .LBB0_1
+; GFX12-FAKE16-NEXT:  ; %bb.2:
+; GFX12-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v5
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0xffff, v6
+; GFX12-FAKE16-NEXT:    ds_store_2addr_b32 v2, v0, v1 offset0:7 offset1:8
 bb:
   %i = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 poison)
   %i2 = call nsz arcp <3 x half> @llvm.amdgcn.struct.buffer.load.format.v3f16(<4 x i32> %arg, i32 %arg1, i32 0, i32 0, i32 0)
@@ -163,3 +220,6 @@ declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0
 declare <3 x half> @llvm.amdgcn.struct.buffer.load.format.v3f16(<4 x i32>, i32, i32, i32, i32 immarg) #1
 attributes #0 = { nounwind readnone willreturn }
 attributes #1 = { nounwind readonly willreturn }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11: {{.*}}
+; GFX12: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
index 87b83f68d685d..4319bdd5d9b65 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
@@ -1,7 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc < %s -mtriple=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefixes=GFX68,VERDE %s
 ; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefixes=GFX68,GFX8 %s
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define amdgpu_ps void @buffer_store(<4 x i32> inreg, <4 x float>, <4 x float>, <4 x float>) {
 ; GFX68-LABEL: buffer_store:
@@ -225,11 +226,17 @@ define amdgpu_ps void @struct_buffer_store_f16(<4 x i32> inreg %rsrc, float %v1,
 ; GFX68-NEXT:    buffer_store_short v0, v1, s[0:3], 0 idxen
 ; GFX68-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: struct_buffer_store_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    buffer_store_b16 v0, v1, s[0:3], 0 idxen
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: struct_buffer_store_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT:    buffer_store_b16 v0, v1, s[0:3], 0 idxen
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: struct_buffer_store_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    buffer_store_b16 v0, v1, s[0:3], 0 idxen
+; GFX11-FAKE16-NEXT:    s_endpgm
   %v2 = fptrunc float %v1 to half
   call void @llvm.amdgcn.struct.buffer.store.f16(half %v2, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)
   ret void
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
index bc50b12b59049..ff5b17f7324cb 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefix=CHECK
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefix=CHECK
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck %s -check-prefixes=CHECK,CHECK-SDAG-TRUE16
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck %s -check-prefixes=CHECK,CHECK-FAKE16
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck %s -check-prefixes=CHECK,CHECK-GISEL-TRUE16
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck %s -check-prefixes=CHECK,CHECK-FAKE16
 
 define amdgpu_kernel void @struct_ptr_atomic_buffer_load_i32(ptr addrspace(8) %ptr, i32 %index) {
 ; CHECK-LABEL: struct_ptr_atomic_buffer_load_i32:
@@ -257,29 +259,75 @@ bb2:
 }
 
 define amdgpu_kernel void @struct_ptr_atomic_buffer_load_v4i16(ptr addrspace(8) %ptr, i32 %index) {
-; CHECK-LABEL: struct_ptr_atomic_buffer_load_v4i16:
-; CHECK:       ; %bb.0: ; %bb
-; CHECK-NEXT:    s_clause 0x1
-; CHECK-NEXT:    s_load_b32 s6, s[4:5], 0x34
-; CHECK-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; CHECK-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; CHECK-NEXT:    s_mov_b32 s4, 0
-; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
-; CHECK-NEXT:    v_mov_b32_e32 v1, s6
-; CHECK-NEXT:  .LBB8_1: ; %bb1
-; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    buffer_load_b64 v[2:3], v1, s[0:3], 0 idxen offset:4 glc
-; CHECK-NEXT:    s_waitcnt vmcnt(0)
-; CHECK-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; CHECK-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; CHECK-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v2, v0
-; CHECK-NEXT:    s_or_b32 s4, vcc_lo, s4
-; CHECK-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; CHECK-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s4
-; CHECK-NEXT:    s_cbranch_execnz .LBB8_1
-; CHECK-NEXT:  ; %bb.2: ; %bb2
-; CHECK-NEXT:    s_endpgm
+; CHECK-SDAG-TRUE16-LABEL: struct_ptr_atomic_buffer_load_v4i16:
+; CHECK-SDAG-TRUE16:       ; %bb.0: ; %bb
+; CHECK-SDAG-TRUE16-NEXT:    s_clause 0x1
+; CHECK-SDAG-TRUE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; CHECK-SDAG-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; CHECK-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; CHECK-SDAG-TRUE16-NEXT:    s_mov_b32 s4, 0
+; CHECK-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v1, s6
+; CHECK-SDAG-TRUE16-NEXT:  .LBB8_1: ; %bb1
+; CHECK-SDAG-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CHECK-SDAG-TRUE16-NEXT:    buffer_load_b64 v[2:3], v1, s[0:3], 0 idxen offset:4 glc
+; CHECK-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; CHECK-SDAG-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; CHECK-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; CHECK-SDAG-TRUE16-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
+; CHECK-SDAG-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v2, v0
+; CHECK-SDAG-TRUE16-NEXT:    s_or_b32 s4, vcc_lo, s4
+; CHECK-SDAG-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; CHECK-SDAG-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s4
+; CHECK-SDAG-TRUE16-NEXT:    s_cbranch_execnz .LBB8_1
+; CHECK-SDAG-TRUE16-NEXT:  ; %bb.2: ; %bb2
+; CHECK-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; CHECK-FAKE16-LABEL: struct_ptr_atomic_buffer_load_v4i16:
+; CHECK-FAKE16:       ; %bb.0: ; %bb
+; CHECK-FAKE16-NEXT:    s_clause 0x1
+; CHECK-FAKE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; CHECK-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; CHECK-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; CHECK-FAKE16-NEXT:    s_mov_b32 s4, 0
+; CHECK-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-FAKE16-NEXT:    v_mov_b32_e32 v1, s6
+; CHECK-FAKE16-NEXT:  .LBB8_1: ; %bb1
+; CHECK-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CHECK-FAKE16-NEXT:    buffer_load_b64 v[2:3], v1, s[0:3], 0 idxen offset:4 glc
+; CHECK-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; CHECK-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; CHECK-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; CHECK-FAKE16-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
+; CHECK-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v2, v0
+; CHECK-FAKE16-NEXT:    s_or_b32 s4, vcc_lo, s4
+; CHECK-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; CHECK-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s4
+; CHECK-FAKE16-NEXT:    s_cbranch_execnz .LBB8_1
+; CHECK-FAKE16-NEXT:  ; %bb.2: ; %bb2
+; CHECK-FAKE16-NEXT:    s_endpgm
+;
+; CHECK-GISEL-TRUE16-LABEL: struct_ptr_atomic_buffer_load_v4i16:
+; CHECK-GISEL-TRUE16:       ; %bb.0: ; %bb
+; CHECK-GISEL-TRUE16-NEXT:    s_clause 0x1
+; CHECK-GISEL-TRUE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; CHECK-GISEL-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; CHECK-GISEL-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; CHECK-GISEL-TRUE16-NEXT:    s_mov_b32 s4, 0
+; CHECK-GISEL-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v1, s6
+; CHECK-GISEL-TRUE16-NEXT:  .LBB8_1: ; %bb1
+; CHECK-GISEL-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CHECK-GISEL-TRUE16-NEXT:    buffer_load_b64 v[2:3], v1, s[0:3], 0 idxen offset:4 glc
+; CHECK-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; CHECK-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; CHECK-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; CHECK-GISEL-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v2, v0
+; CHECK-GISEL-TRUE16-NEXT:    s_or_b32 s4, vcc_lo, s4
+; CHECK-GISEL-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s4
+; CHECK-GISEL-TRUE16-NEXT:    s_cbranch_execnz .LBB8_1
+; CHECK-GISEL-TRUE16-NEXT:  ; %bb.2: ; %bb2
+; CHECK-GISEL-TRUE16-NEXT:    s_endpgm
 bb:
   %id = tail call i32 @llvm.amdgcn.workitem.id.x()
   br label %bb1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
index 68a585cce2e23..ff02c2e2f58e0 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
@@ -2,7 +2,8 @@
 ; RUN: llc -mcpu=gfx1010 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
 ; RUN: llc -mcpu=gfx900 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s
 ; RUN: llc -mcpu=gfx810 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s
-; RUN: llc -mcpu=gfx1100 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11 %s
+; RUN: llc -mcpu=gfx1100 -mattr=+real-true16 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mcpu=gfx1100 -mattr=-real-true16 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 @esgs_ring = external addrspace(3) global [0 x i32], align 65536
 
 define amdgpu_gs void @main(ptr addrspace(8) %arg, i32 %arg1) {
@@ -86,31 +87,58 @@ define amdgpu_gs void @main(ptr addrspace(8) %arg, i32 %arg1) {
 ; GFX8-NEXT:    s_mov_b32 m0, -1
 ; GFX8-NEXT:    ds_write2_b32 v2, v0, v1 offset0:7 offset1:8
 ;
-; GFX11-LABEL: main:
-; GFX11:       ; %bb.0: ; %bb
-; GFX11-NEXT:    s_mov_b32 s1, exec_lo
-; GFX11-NEXT:  .LBB0_1: ; =>This Inner Loop Header: Depth=1
-; GFX11-NEXT:    v_readfirstlane_b32 s4, v0
-; GFX11-NEXT:    v_readfirstlane_b32 s5, v1
-; GFX11-NEXT:    v_readfirstlane_b32 s6, v2
-; GFX11-NEXT:    v_readfirstlane_b32 s7, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
-; GFX11-NEXT:    v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
-; GFX11-NEXT:    s_and_b32 s0, vcc_lo, s0
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_saveexec_b32 s0, s0
-; GFX11-NEXT:    buffer_load_d16_format_xyz v[5:6], v4, s[4:7], 0 idxen
-; GFX11-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
-; GFX11-NEXT:    ; implicit-def: $vgpr4
-; GFX11-NEXT:    s_xor_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB0_1
-; GFX11-NEXT:  ; %bb.2:
-; GFX11-NEXT:    s_mov_b32 exec_lo, s1
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v0, 16, v5
-; GFX11-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0xffff, v6
-; GFX11-NEXT:    ds_store_2addr_b32 v2, v0, v1 offset0:7 offset1:8
+; GFX11-TRUE16-LABEL: main:
+; GFX11-TRUE16:       ; %bb.0: ; %bb
+; GFX11-TRUE16-NEXT:    s_mov_b32 s1, exec_lo
+; GFX11-TRUE16-NEXT:  .LBB0_1: ; =>This Inner Loop Header: Depth=1
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s4, v0
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s5, v1
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s6, v2
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s7, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
+; GFX11-TRUE16-NEXT:    s_and_b32 s0, vcc_lo, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT:    buffer_load_d16_format_xyz v[5:6], v4, s[4:7], 0 idxen
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-TRUE16-NEXT:    s_xor_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB0_1
+; GFX11-TRUE16-NEXT:  ; %bb.2:
+; GFX11-TRUE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v5.h
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0xffff, v6
+; GFX11-TRUE16-NEXT:    ds_store_2addr_b32 v2, v0, v1 offset0:7 offset1:8
+;
+; GFX11-FAKE16-LABEL: main:
+; GFX11-FAKE16:       ; %bb.0: ; %bb
+; GFX11-FAKE16-NEXT:    s_mov_b32 s1, exec_lo
+; GFX11-FAKE16-NEXT:  .LBB0_1: ; =>This Inner Loop Header: Depth=1
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s4, v0
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s5, v1
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s6, v2
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s7, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
+; GFX11-FAKE16-NEXT:    s_and_b32 s0, vcc_lo, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, s0
+; GFX11-FAKE16-NEXT:    buffer_load_d16_format_xyz v[5:6], v4, s[4:7], 0 idxen
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT:    s_xor_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB0_1
+; GFX11-FAKE16-NEXT:  ; %bb.2:
+; GFX11-FAKE16-NEXT:    s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v5
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0xffff, v6
+; GFX11-FAKE16-NEXT:    ds_store_2addr_b32 v2, v0, v1 offset0:7 offset1:8
 bb:
   %i = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 poison)
   %i2 = call nsz arcp <3 x half> @llvm.amdgcn.struct.ptr.buffer.load.format.v3f16(ptr addrspace(8) %arg, i32 %arg1, i32 0, i32 0, i32 0)
@@ -134,3 +162,5 @@ declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0
 declare <3 x half> @llvm.amdgcn.struct.ptr.buffer.load.format.v3f16(ptr addrspace(8), i32, i32, i32, i32 immarg) #1
 attributes #0 = { nounwind readnone willreturn }
 attributes #1 = { nounwind readonly willreturn }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
index a9e561da98db6..268ac534cc241 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
@@ -211,7 +211,7 @@ define amdgpu_kernel void @tbuffer_store_d16_xyz(<4 x i32> %rsrc, <4 x half> %da
 ; GFX12-PACKED-GISEL-NEXT:    v_mov_b32_e32 v0, s8
 ; GFX12-PACKED-GISEL-NEXT:    v_mov_b32_e32 v1, s9
 ; GFX12-PACKED-GISEL-NEXT:    v_mov_b32_e32 v2, s10
-; GFX12-PACKED-GISEL-NEXT:    tbuffer_store_d16_format_xyzw v[0:1], v2, s[0:3], null format:[BUF_FMT_10_10_10_2_SNORM] idxen
+; GFX12-PACKED-GISEL-NEXT:    tbuffer_store_d16_format_xyz v[0:1], v2, s[0:3], null format:[BUF_FMT_10_10_10_2_SNORM] idxen
 ; GFX12-PACKED-GISEL-NEXT:    s_endpgm
 main_body:
   %data_subvec = shufflevector <4 x half> %data, <4 x half> poison, <3 x i32> <i32 0, i32 1, i32 2>
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll b/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
index 88ef7a9363930..f44faf4f7edba 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
@@ -2,14 +2,18 @@
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6,GFX6-SDAG %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-SDAG %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-SDAG %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-SDAG %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12,GFX12-SDAG %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
 
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6,GFX6-GISEL %s
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12,GFX12-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
 
 define { half, i32 } @test_frexp_f16_i32(half %a) {
 ; GFX6-SDAG-LABEL: test_frexp_f16_i32:
@@ -43,27 +47,49 @@ define { half, i32 } @test_frexp_f16_i32(half %a) {
 ; GFX9-NEXT:    v_mov_b32_e32 v0, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_frexp_f16_i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_frexp_exp_i16_f16_e32 v1, v0
-; GFX11-NEXT:    v_frexp_mant_f16_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_i32 v1, v1, 0, 16
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: test_frexp_f16_i32:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_frexp_exp_i16_f16_e32 v1, v0
-; GFX12-NEXT:    v_frexp_mant_f16_e32 v0, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT:    v_bfe_i32 v1, v1, 0, 16
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_frexp_f16_i32:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_frexp_f16_i32:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v1, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_frexp_mant_f16_e32 v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_frexp_f16_i32:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v1.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_frexp_f16_i32:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v1, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_frexp_mant_f16_e32 v0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX6-GISEL-LABEL: test_frexp_f16_i32:
 ; GFX6-GISEL:       ; %bb.0:
@@ -77,6 +103,50 @@ define { half, i32 } @test_frexp_f16_i32(half %a) {
 ; GFX6-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX6-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
 ; GFX6-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_frexp_f16_i32:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v1.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_frexp_f16_i32:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v1, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_frexp_mant_f16_e32 v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_frexp_f16_i32:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v1.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_frexp_f16_i32:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v1, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_frexp_mant_f16_e32 v0, v0
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = call { half, i32 } @llvm.frexp.f16.i32(half %a)
   ret { half, i32 } %result
 }
@@ -105,21 +175,37 @@ define half @test_frexp_f16_i32_only_use_fract(half %a) {
 ; GFX9-NEXT:    v_frexp_mant_f16_e32 v0, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_frexp_f16_i32_only_use_fract:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_frexp_mant_f16_e32 v0, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: test_frexp_f16_i32_only_use_fract:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_frexp_mant_f16_e32 v0, v0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_frexp_f16_i32_only_use_fract:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_frexp_f16_i32_only_use_fract:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_frexp_mant_f16_e32 v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_frexp_f16_i32_only_use_fract:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_frexp_f16_i32_only_use_fract:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_frexp_mant_f16_e32 v0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX6-GISEL-LABEL: test_frexp_f16_i32_only_use_fract:
 ; GFX6-GISEL:       ; %bb.0:
@@ -131,6 +217,38 @@ define half @test_frexp_f16_i32_only_use_fract(half %a) {
 ; GFX6-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
 ; GFX6-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX6-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_frexp_f16_i32_only_use_fract:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_frexp_f16_i32_only_use_fract:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_frexp_mant_f16_e32 v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_frexp_f16_i32_only_use_fract:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_frexp_f16_i32_only_use_fract:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_frexp_mant_f16_e32 v0, v0
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = call { half, i32 } @llvm.frexp.f16.i32(half %a)
   %result.0 = extractvalue { half, i32 } %result, 0
   ret half %result.0
@@ -162,25 +280,45 @@ define i32 @test_frexp_f16_i32_only_use_exp(half %a) {
 ; GFX9-NEXT:    v_bfe_i32 v0, v0, 0, 16
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_frexp_f16_i32_only_use_exp:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_bfe_i32 v0, v0, 0, 16
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: test_frexp_f16_i32_only_use_exp:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_bfe_i32 v0, v0, 0, 16
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_frexp_f16_i32_only_use_exp:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v0.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_frexp_f16_i32_only_use_exp:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_frexp_f16_i32_only_use_exp:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v0.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_frexp_f16_i32_only_use_exp:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX6-GISEL-LABEL: test_frexp_f16_i32_only_use_exp:
 ; GFX6-GISEL:       ; %bb.0:
@@ -191,6 +329,46 @@ define i32 @test_frexp_f16_i32_only_use_exp(half %a) {
 ; GFX6-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v1
 ; GFX6-GISEL-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
 ; GFX6-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_frexp_f16_i32_only_use_exp:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_frexp_f16_i32_only_use_exp:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_frexp_f16_i32_only_use_exp:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_frexp_f16_i32_only_use_exp:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = call { half, i32 } @llvm.frexp.f16.i32(half %a)
   %result.0 = extractvalue { half, i32 } %result, 1
   ret i32 %result.0
@@ -243,39 +421,71 @@ define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) {
 ; GFX9-SDAG-NEXT:    v_mov_b32_e32 v0, v3
 ; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_frexp_v2f16_v2i32:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_frexp_mant_f16_e32 v2, v0
-; GFX11-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_frexp_mant_f16_e32 v3, v1
-; GFX11-NEXT:    v_frexp_exp_i16_f16_e32 v4, v1
-; GFX11-NEXT:    v_bfe_i32 v1, v0, 0, 16
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_pack_b32_f16 v0, v2, v3
-; GFX11-NEXT:    v_bfe_i32 v2, v4, 0, 16
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: test_frexp_v2f16_v2i32:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-NEXT:    v_frexp_mant_f16_e32 v2, v0
-; GFX12-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-NEXT:    v_frexp_mant_f16_e32 v3, v1
-; GFX12-NEXT:    v_frexp_exp_i16_f16_e32 v4, v1
-; GFX12-NEXT:    v_bfe_i32 v1, v0, 0, 16
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-NEXT:    v_pack_b32_f16 v0, v2, v3
-; GFX12-NEXT:    v_bfe_i32 v2, v4, 0, 16
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_frexp_v2f16_v2i32:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v2.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.h, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v2, v2, 0, 16
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_frexp_v2f16_v2i32:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_frexp_mant_f16_e32 v2, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT:    v_frexp_mant_f16_e32 v3, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v4, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v0, 0, 16
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v2, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v2, v4, 0, 16
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_frexp_v2f16_v2i32:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v1.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v2.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.h, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v2, v2, 0, 16
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_frexp_v2f16_v2i32:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_frexp_mant_f16_e32 v2, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-SDAG-FAKE16-NEXT:    v_frexp_mant_f16_e32 v3, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v4, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v0, 0, 16
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v2, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v2, v4, 0, 16
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX6-GISEL-LABEL: test_frexp_v2f16_v2i32:
 ; GFX6-GISEL:       ; %bb.0:
@@ -320,6 +530,72 @@ define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) {
 ; GFX9-GISEL-NEXT:    v_bfe_i32 v2, v0, 0, 16
 ; GFX9-GISEL-NEXT:    v_pack_b32_f16 v0, v3, v4
 ; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_frexp_v2f16_v2i32:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v1.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v2.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.h, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-TRUE16-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX11-GISEL-TRUE16-NEXT:    v_bfe_i32 v2, v2, 0, 16
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_frexp_v2f16_v2i32:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_frexp_mant_f16_e32 v2, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-GISEL-FAKE16-NEXT:    v_frexp_mant_f16_e32 v3, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v4, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_bfe_i32 v1, v0, 0, 16
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v2, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_bfe_i32 v2, v4, 0, 16
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_frexp_v2f16_v2i32:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v1.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v2.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.h, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-GISEL-TRUE16-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX12-GISEL-TRUE16-NEXT:    v_bfe_i32 v2, v2, 0, 16
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX12-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_frexp_v2f16_v2i32:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_frexp_mant_f16_e32 v2, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-GISEL-FAKE16-NEXT:    v_frexp_mant_f16_e32 v3, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v4, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_bfe_i32 v1, v0, 0, 16
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v2, v3
+; GFX12-GISEL-FAKE16-NEXT:    v_bfe_i32 v2, v4, 0, 16
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = call { <2 x half>, <2 x i32> } @llvm.frexp.v2f16.v2i32(<2 x half> %a)
   ret { <2 x half>, <2 x i32> } %result
 }
@@ -357,29 +633,51 @@ define <2 x half> @test_frexp_v2f16_v2i32_only_use_fract(<2 x half> %a) {
 ; GFX9-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v1
 ; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_frexp_v2f16_v2i32_only_use_fract:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_frexp_mant_f16_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_frexp_mant_f16_e32 v1, v1
-; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: test_frexp_v2f16_v2i32_only_use_fract:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-NEXT:    v_frexp_mant_f16_e32 v0, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_frexp_mant_f16_e32 v1, v1
-; GFX12-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_frexp_v2f16_v2i32_only_use_fract:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.h, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_frexp_v2f16_v2i32_only_use_fract:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_frexp_mant_f16_e32 v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_frexp_mant_f16_e32 v1, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_frexp_v2f16_v2i32_only_use_fract:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.h, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_frexp_v2f16_v2i32_only_use_fract:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_frexp_mant_f16_e32 v0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_frexp_mant_f16_e32 v1, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX6-GISEL-LABEL: test_frexp_v2f16_v2i32_only_use_fract:
 ; GFX6-GISEL:       ; %bb.0:
@@ -404,6 +702,52 @@ define <2 x half> @test_frexp_v2f16_v2i32_only_use_fract(<2 x half> %a) {
 ; GFX9-GISEL-NEXT:    v_frexp_mant_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
 ; GFX9-GISEL-NEXT:    v_pack_b32_f16 v0, v1, v0
 ; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_frexp_v2f16_v2i32_only_use_fract:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.h, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_frexp_v2f16_v2i32_only_use_fract:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_frexp_mant_f16_e32 v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_frexp_mant_f16_e32 v1, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_frexp_v2f16_v2i32_only_use_fract:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.h, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_frexp_v2f16_v2i32_only_use_fract:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_frexp_mant_f16_e32 v0, v0
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_frexp_mant_f16_e32 v1, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = call { <2 x half>, <2 x i32> } @llvm.frexp.v2f16.v2i32(<2 x half> %a)
   %result.0 = extractvalue { <2 x half>, <2 x i32> } %result, 0
   ret <2 x half> %result.0
@@ -444,33 +788,57 @@ define <2 x i32> @test_frexp_v2f16_v2i32_only_use_exp(<2 x half> %a) {
 ; GFX9-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 16
 ; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_frexp_v2f16_v2i32_only_use_exp:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_frexp_exp_i16_f16_e32 v1, v1
-; GFX11-NEXT:    v_bfe_i32 v0, v0, 0, 16
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_i32 v1, v1, 0, 16
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: test_frexp_v2f16_v2i32_only_use_exp:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_frexp_exp_i16_f16_e32 v1, v1
-; GFX12-NEXT:    v_bfe_i32 v0, v0, 0, 16
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT:    v_bfe_i32 v1, v1, 0, 16
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_frexp_v2f16_v2i32_only_use_exp:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v0.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v1.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_frexp_v2f16_v2i32_only_use_exp:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v1, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_frexp_v2f16_v2i32_only_use_exp:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v0.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v1.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_frexp_v2f16_v2i32_only_use_exp:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v1, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX6-GISEL-LABEL: test_frexp_v2f16_v2i32_only_use_exp:
 ; GFX6-GISEL:       ; %bb.0:
@@ -505,6 +873,58 @@ define <2 x i32> @test_frexp_v2f16_v2i32_only_use_exp(<2 x half> %a) {
 ; GFX9-GISEL-NEXT:    v_bfe_i32 v1, v0, 0, 16
 ; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, v2
 ; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_frexp_v2f16_v2i32_only_use_exp:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v1.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX11-GISEL-TRUE16-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_frexp_v2f16_v2i32_only_use_exp:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v1, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_frexp_v2f16_v2i32_only_use_exp:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v1.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX12-GISEL-TRUE16-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_frexp_v2f16_v2i32_only_use_exp:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v1, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = call { <2 x half>, <2 x i32> } @llvm.frexp.v2f16.v2i32(<2 x half> %a)
   %result.1 = extractvalue { <2 x half>, <2 x i32> } %result, 1
   ret <2 x i32> %result.1
@@ -540,27 +960,49 @@ define { half, i16 } @test_frexp_f16_i16(half %a) {
 ; GFX9-NEXT:    v_mov_b32_e32 v0, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_frexp_f16_i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_frexp_mant_f16_e32 v2, v0
-; GFX11-NEXT:    v_frexp_exp_i16_f16_e32 v1, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_mov_b32_e32 v0, v2
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: test_frexp_f16_i16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_frexp_mant_f16_e32 v2, v0
-; GFX12-NEXT:    v_frexp_exp_i16_f16_e32 v1, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT:    v_mov_b32_e32 v0, v2
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_frexp_f16_i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v1.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_frexp_f16_i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_frexp_mant_f16_e32 v2, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v1, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_frexp_f16_i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v1.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_frexp_f16_i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_frexp_mant_f16_e32 v2, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v1, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX6-GISEL-LABEL: test_frexp_f16_i16:
 ; GFX6-GISEL:       ; %bb.0:
@@ -574,6 +1016,50 @@ define { half, i16 } @test_frexp_f16_i16(half %a) {
 ; GFX6-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX6-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
 ; GFX6-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_frexp_f16_i16:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_frexp_mant_f16_e32 v2.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v1.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_frexp_f16_i16:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_frexp_mant_f16_e32 v2, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v1, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v0, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_frexp_f16_i16:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_frexp_mant_f16_e32 v2.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v1.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_frexp_f16_i16:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_frexp_mant_f16_e32 v2, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v1, v0
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v0, v2
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = call { half, i16 } @llvm.frexp.f16.i16(half %a)
   ret { half, i16 } %result
 }
@@ -602,21 +1088,37 @@ define half @test_frexp_f16_i16_only_use_fract(half %a) {
 ; GFX9-NEXT:    v_frexp_mant_f16_e32 v0, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_frexp_f16_i16_only_use_fract:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_frexp_mant_f16_e32 v0, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: test_frexp_f16_i16_only_use_fract:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_frexp_mant_f16_e32 v0, v0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_frexp_f16_i16_only_use_fract:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_frexp_f16_i16_only_use_fract:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_frexp_mant_f16_e32 v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_frexp_f16_i16_only_use_fract:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_frexp_f16_i16_only_use_fract:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_frexp_mant_f16_e32 v0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX6-GISEL-LABEL: test_frexp_f16_i16_only_use_fract:
 ; GFX6-GISEL:       ; %bb.0:
@@ -628,6 +1130,38 @@ define half @test_frexp_f16_i16_only_use_fract(half %a) {
 ; GFX6-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
 ; GFX6-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX6-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_frexp_f16_i16_only_use_fract:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_frexp_f16_i16_only_use_fract:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_frexp_mant_f16_e32 v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_frexp_f16_i16_only_use_fract:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_frexp_mant_f16_e32 v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_frexp_f16_i16_only_use_fract:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_frexp_mant_f16_e32 v0, v0
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = call { half, i16 } @llvm.frexp.f16.i16(half %a)
   %result.0 = extractvalue { half, i16 } %result, 0
   ret half %result.0
@@ -657,21 +1191,37 @@ define i16 @test_frexp_f16_i16_only_use_exp(half %a) {
 ; GFX9-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_frexp_f16_i16_only_use_exp:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: test_frexp_f16_i16_only_use_exp:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_frexp_f16_i16_only_use_exp:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v0.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_frexp_f16_i16_only_use_exp:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_frexp_f16_i16_only_use_exp:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v0.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_frexp_f16_i16_only_use_exp:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX6-GISEL-LABEL: test_frexp_f16_i16_only_use_exp:
 ; GFX6-GISEL:       ; %bb.0:
@@ -682,6 +1232,38 @@ define i16 @test_frexp_f16_i16_only_use_exp(half %a) {
 ; GFX6-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v1
 ; GFX6-GISEL-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
 ; GFX6-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_frexp_f16_i16_only_use_exp:
+; GFX11-GISEL-TRUE16:       ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_frexp_f16_i16_only_use_exp:
+; GFX11-GISEL-FAKE16:       ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_frexp_f16_i16_only_use_exp:
+; GFX12-GISEL-TRUE16:       ; %bb.0:
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_frexp_exp_i16_f16_e32 v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_frexp_f16_i16_only_use_exp:
+; GFX12-GISEL-FAKE16:       ; %bb.0:
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = call { half, i16 } @llvm.frexp.f16.i16(half %a)
   %result.0 = extractvalue { half, i16 } %result, 1
   ret i16 %result.0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log.ll b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
index ff8b539fd5ebb..1dd6a7926029e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
@@ -5,8 +5,10 @@
 ; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck  -check-prefixes=GFX689,VI,GFX689-GISEL,VI-GISEL %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-SDAG,GFX900-SDAG %s
 ; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-GISEL,GFX900-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-SDAG,GFX1100-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-SDAG,GFX1100-SDAG-FAKE16 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-FAKE16 %s
 
 ; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
 ; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
@@ -6010,39 +6012,73 @@ define float @v_log_f32_from_fpext_f16(i16 %src.i) {
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-SDAG-LABEL: v_log_f32_from_fpext_f16:
-; GFX1100-SDAG:       ; %bb.0:
-; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1100-SDAG-NEXT:    v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX1100-SDAG-NEXT:    v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-SDAG-NEXT:    v_fma_f32 v2, 0x3f317217, v0, -v1
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT:    v_fmamk_f32 v2, v0, 0x3377d1cf, v2
-; GFX1100-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX1100-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1100-GISEL-LABEL: v_log_f32_from_fpext_f16:
-; GFX1100-GISEL:       ; %bb.0:
-; GFX1100-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT:    v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX1100-GISEL-NEXT:    v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-GISEL-NEXT:    v_fma_f32 v2, 0x3f317217, v0, -v1
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_fmac_f32_e32 v2, 0x3377d1cf, v0
-; GFX1100-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX1100-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log_f32_from_fpext_f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-SDAG-TRUE16-NEXT:    v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-SDAG-TRUE16-NEXT:    v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT:    v_fmamk_f32 v2, v0, 0x3377d1cf, v2
+; GFX1100-SDAG-TRUE16-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log_f32_from_fpext_f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-SDAG-FAKE16-NEXT:    v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_fmamk_f32 v2, v0, 0x3377d1cf, v2
+; GFX1100-SDAG-FAKE16-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log_f32_from_fpext_f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-TRUE16-NEXT:    v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-GISEL-TRUE16-NEXT:    v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-TRUE16-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log_f32_from_fpext_f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-GISEL-FAKE16-NEXT:    v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_f32_from_fpext_f16:
 ; R600:       ; %bb.0:
@@ -6179,41 +6215,77 @@ define float @v_log_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-SDAG-LABEL: v_log_f32_from_fpext_math_f16:
-; GFX1100-SDAG:       ; %bb.0:
-; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX1100-SDAG-NEXT:    v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX1100-SDAG-NEXT:    v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT:    v_fma_f32 v2, 0x3f317217, v0, -v1
-; GFX1100-SDAG-NEXT:    v_fmamk_f32 v2, v0, 0x3377d1cf, v2
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
-; GFX1100-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX1100-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1100-GISEL-LABEL: v_log_f32_from_fpext_math_f16:
-; GFX1100-GISEL:       ; %bb.0:
-; GFX1100-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX1100-GISEL-NEXT:    v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX1100-GISEL-NEXT:    v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_fma_f32 v2, 0x3f317217, v0, -v1
-; GFX1100-GISEL-NEXT:    v_fmac_f32_e32 v2, 0x3377d1cf, v0
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
-; GFX1100-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX1100-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log_f32_from_fpext_math_f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-SDAG-TRUE16-NEXT:    v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT:    v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-SDAG-TRUE16-NEXT:    v_fmamk_f32 v2, v0, 0x3377d1cf, v2
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log_f32_from_fpext_math_f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_fmamk_f32 v2, v0, 0x3377d1cf, v2
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log_f32_from_fpext_math_f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-TRUE16-NEXT:    v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-TRUE16-NEXT:    v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log_f32_from_fpext_math_f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-FAKE16-NEXT:    v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_f32_from_fpext_math_f16:
 ; R600:       ; %bb.0:
@@ -6376,13 +6448,37 @@ define half @v_log_f16(half %in) {
 ; GFX900-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
 ; GFX900-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log_f16:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log_f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log_f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log_f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log_f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_f16:
 ; R600:       ; %bb.0:
@@ -6432,13 +6528,37 @@ define half @v_log_fabs_f16(half %in) {
 ; GFX900-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
 ; GFX900-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log_fabs_f16:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_log_f16_e64 v0, |v0|
-; GFX1100-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log_fabs_f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.l, |v0.l|
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log_fabs_f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v0, |v0|
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log_fabs_f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e64 v0.l, |v0.l|
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log_fabs_f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e64 v0, |v0|
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_fabs_f16:
 ; R600:       ; %bb.0:
@@ -6489,13 +6609,37 @@ define half @v_log_fneg_fabs_f16(half %in) {
 ; GFX900-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
 ; GFX900-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log_fneg_fabs_f16:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_log_f16_e64 v0, -|v0|
-; GFX1100-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log_fneg_fabs_f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.l, -|v0.l|
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log_fneg_fabs_f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v0, -|v0|
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log_fneg_fabs_f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e64 v0.l, -|v0.l|
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log_fneg_fabs_f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e64 v0, -|v0|
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_fneg_fabs_f16:
 ; R600:       ; %bb.0:
@@ -6547,13 +6691,37 @@ define half @v_log_fneg_f16(half %in) {
 ; GFX900-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
 ; GFX900-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log_fneg_f16:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_log_f16_e64 v0, -v0
-; GFX1100-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log_fneg_f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.l, -v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log_fneg_f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v0, -v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log_fneg_f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e64 v0.l, -v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log_fneg_f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e64 v0, -v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_fneg_f16:
 ; R600:       ; %bb.0:
@@ -6604,13 +6772,37 @@ define half @v_log_f16_fast(half %in) {
 ; GFX900-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
 ; GFX900-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log_f16_fast:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log_f16_fast:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log_f16_fast:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log_f16_fast:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log_f16_fast:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_f16_fast:
 ; R600:       ; %bb.0:
@@ -6688,18 +6880,55 @@ define <2 x half> @v_log_v2f16(<2 x half> %in) {
 ; GFX900-NEXT:    v_pack_b32_f16 v0, v1, v0
 ; GFX900-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log_v2f16:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX1100-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX1100-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
-; GFX1100-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
-; GFX1100-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log_v2f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x398c, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log_v2f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log_v2f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x398c, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log_v2f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_v2f16:
 ; R600:       ; %bb.0:
@@ -6794,33 +7023,59 @@ define <2 x half> @v_log_fabs_v2f16(<2 x half> %in) {
 ; GFX900-GISEL-NEXT:    v_pack_b32_f16 v0, v1, v0
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-SDAG-LABEL: v_log_fabs_v2f16:
-; GFX1100-SDAG:       ; %bb.0:
-; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX1100-SDAG-NEXT:    v_log_f16_e64 v0, |v0|
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT:    v_log_f16_e64 v1, |v1|
-; GFX1100-SDAG-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
-; GFX1100-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX1100-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1100-GISEL-LABEL: v_log_fabs_v2f16:
-; GFX1100-GISEL:       ; %bb.0:
-; GFX1100-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT:    v_and_b32_e32 v0, 0x7fff7fff, v0
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-GISEL-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX1100-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log_fabs_v2f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.l, |v0.l|
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.h, |v0.h|
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x398c, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log_fabs_v2f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v0, |v0|
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v1, |v1|
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log_fabs_v2f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_and_b32_e32 v0, 0x7fff7fff, v0
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x398c, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log_fabs_v2f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0x7fff7fff, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_fabs_v2f16:
 ; R600:       ; %bb.0:
@@ -6920,33 +7175,59 @@ define <2 x half> @v_log_fneg_fabs_v2f16(<2 x half> %in) {
 ; GFX900-GISEL-NEXT:    v_pack_b32_f16 v0, v1, v0
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-SDAG-LABEL: v_log_fneg_fabs_v2f16:
-; GFX1100-SDAG:       ; %bb.0:
-; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX1100-SDAG-NEXT:    v_log_f16_e64 v0, -|v0|
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT:    v_log_f16_e64 v1, -|v1|
-; GFX1100-SDAG-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
-; GFX1100-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX1100-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1100-GISEL-LABEL: v_log_fneg_fabs_v2f16:
-; GFX1100-GISEL:       ; %bb.0:
-; GFX1100-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT:    v_or_b32_e32 v0, 0x80008000, v0
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-GISEL-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX1100-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log_fneg_fabs_v2f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.l, -|v0.l|
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.h, -|v0.h|
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x398c, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log_fneg_fabs_v2f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v0, -|v0|
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v1, -|v1|
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log_fneg_fabs_v2f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_or_b32_e32 v0, 0x80008000, v0
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x398c, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log_fneg_fabs_v2f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_or_b32_e32 v0, 0x80008000, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_fneg_fabs_v2f16:
 ; R600:       ; %bb.0:
@@ -7047,33 +7328,59 @@ define <2 x half> @v_log_fneg_v2f16(<2 x half> %in) {
 ; GFX900-GISEL-NEXT:    v_pack_b32_f16 v0, v1, v0
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-SDAG-LABEL: v_log_fneg_v2f16:
-; GFX1100-SDAG:       ; %bb.0:
-; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX1100-SDAG-NEXT:    v_log_f16_e64 v0, -v0
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT:    v_log_f16_e64 v1, -v1
-; GFX1100-SDAG-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
-; GFX1100-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX1100-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1100-GISEL-LABEL: v_log_fneg_v2f16:
-; GFX1100-GISEL:       ; %bb.0:
-; GFX1100-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-GISEL-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX1100-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log_fneg_v2f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.l, -v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.h, -v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x398c, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log_fneg_v2f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v0, -v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v1, -v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log_fneg_v2f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x398c, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log_fneg_v2f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_fneg_v2f16:
 ; R600:       ; %bb.0:
@@ -7152,18 +7459,55 @@ define <2 x half> @v_log_v2f16_fast(<2 x half> %in) {
 ; GFX900-NEXT:    v_pack_b32_f16 v0, v1, v0
 ; GFX900-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log_v2f16_fast:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX1100-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX1100-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
-; GFX1100-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
-; GFX1100-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log_v2f16_fast:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x398c, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log_v2f16_fast:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log_v2f16_fast:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x398c, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log_v2f16_fast:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_v2f16_fast:
 ; R600:       ; %bb.0:
@@ -7244,21 +7588,65 @@ define <3 x half> @v_log_v3f16(<3 x half> %in) {
 ; GFX900-NEXT:    v_pack_b32_f16 v0, v2, v0
 ; GFX900-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log_v3f16:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
-; GFX1100-NEXT:    v_log_f16_e32 v2, v2
-; GFX1100-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
-; GFX1100-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
-; GFX1100-NEXT:    v_mul_f16_e32 v2, 0x398c, v2
-; GFX1100-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT:    v_pack_b32_f16 v0, v0, v2
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log_v3f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v1.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x398c, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v1.l, 0x398c, v1.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log_v3f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v2, v2
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v2, 0x398c, v2
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log_v3f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v1.l, v1.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x398c, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v1.l, 0x398c, v1.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log_v3f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v2, v2
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v2, 0x398c, v2
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_v3f16:
 ; R600:       ; %bb.0:
@@ -7339,21 +7727,65 @@ define <3 x half> @v_log_v3f16_fast(<3 x half> %in) {
 ; GFX900-NEXT:    v_pack_b32_f16 v0, v2, v0
 ; GFX900-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log_v3f16_fast:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
-; GFX1100-NEXT:    v_log_f16_e32 v2, v2
-; GFX1100-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
-; GFX1100-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
-; GFX1100-NEXT:    v_mul_f16_e32 v2, 0x398c, v2
-; GFX1100-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT:    v_pack_b32_f16 v0, v0, v2
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log_v3f16_fast:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v1.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x398c, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v1.l, 0x398c, v1.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log_v3f16_fast:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v2, v2
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v2, 0x398c, v2
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log_v3f16_fast:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v1.l, v1.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x398c, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v1.l, 0x398c, v1.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log_v3f16_fast:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v2, v2
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v2, 0x398c, v2
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_v3f16_fast:
 ; R600:       ; %bb.0:
@@ -7481,47 +7913,82 @@ define <4 x half> @v_log_v4f16(<4 x half> %in) {
 ; GFX900-GISEL-NEXT:    v_pack_b32_f16 v1, v3, v1
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-SDAG-LABEL: v_log_v4f16:
-; GFX1100-SDAG:       ; %bb.0:
-; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-SDAG-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX1100-SDAG-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-SDAG-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT:    v_log_f16_e32 v2, v2
-; GFX1100-SDAG-NEXT:    v_log_f16_e32 v3, v3
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
-; GFX1100-SDAG-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v2, 0x398c, v2
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v3, 0x398c, v3
-; GFX1100-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v2
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX1100-SDAG-NEXT:    v_pack_b32_f16 v1, v1, v3
-; GFX1100-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1100-GISEL-LABEL: v_log_v4f16:
-; GFX1100-GISEL:       ; %bb.0:
-; GFX1100-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v2, v2
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v3, v3
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
-; GFX1100-GISEL-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v2, 0x398c, v2
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v3, 0x398c, v3
-; GFX1100-GISEL-NEXT:    v_pack_b32_f16 v0, v0, v2
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX1100-GISEL-NEXT:    v_pack_b32_f16 v1, v1, v3
-; GFX1100-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log_v4f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v1.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v1.h, v1.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v1.l, 0x398c, v1.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x398c, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v1.h, 0x398c, v1.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.l, v1.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log_v4f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v2, v2
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v3, v3
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v2, 0x398c, v2
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v3, 0x398c, v3
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, v3
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log_v4f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v1.l, v1.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v1.h, v1.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x398c, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v1.l, 0x398c, v1.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v1.h, 0x398c, v1.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.l, v1.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log_v4f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v2, v2
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v3, v3
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v2, 0x398c, v2
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v3, 0x398c, v3
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, v3
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_v4f16:
 ; R600:       ; %bb.0:
@@ -7649,47 +8116,82 @@ define <4 x half> @v_log_v4f16_fast(<4 x half> %in) {
 ; GFX900-GISEL-NEXT:    v_pack_b32_f16 v1, v3, v1
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-SDAG-LABEL: v_log_v4f16_fast:
-; GFX1100-SDAG:       ; %bb.0:
-; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-SDAG-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX1100-SDAG-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-SDAG-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT:    v_log_f16_e32 v2, v2
-; GFX1100-SDAG-NEXT:    v_log_f16_e32 v3, v3
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
-; GFX1100-SDAG-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v2, 0x398c, v2
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v3, 0x398c, v3
-; GFX1100-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v2
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX1100-SDAG-NEXT:    v_pack_b32_f16 v1, v1, v3
-; GFX1100-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1100-GISEL-LABEL: v_log_v4f16_fast:
-; GFX1100-GISEL:       ; %bb.0:
-; GFX1100-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v2, v2
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v3, v3
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
-; GFX1100-GISEL-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v2, 0x398c, v2
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v3, 0x398c, v3
-; GFX1100-GISEL-NEXT:    v_pack_b32_f16 v0, v0, v2
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX1100-GISEL-NEXT:    v_pack_b32_f16 v1, v1, v3
-; GFX1100-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log_v4f16_fast:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v1.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v1.h, v1.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v1.l, 0x398c, v1.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x398c, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v1.h, 0x398c, v1.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.l, v1.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log_v4f16_fast:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v2, v2
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v3, v3
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v2, 0x398c, v2
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v3, 0x398c, v3
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, v3
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log_v4f16_fast:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v1.l, v1.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v1.h, v1.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x398c, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v1.l, 0x398c, v1.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v1.h, 0x398c, v1.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.l, v1.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log_v4f16_fast:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v2, v2
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v3, v3
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x398c, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x398c, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v2, 0x398c, v2
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v3, 0x398c, v3
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, v3
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log_v4f16_fast:
 ; R600:       ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
index 4f783589f148f..86a58d26c6ae5 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
@@ -5,8 +5,10 @@
 ; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck  -check-prefixes=GFX689,VI,GFX689-GISEL,VI-GISEL %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-SDAG,GFX900-SDAG %s
 ; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-GISEL,GFX900-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-SDAG,GFX1100-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-SDAG,GFX1100-SDAG-FAKE16 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-FAKE16 %s
 
 ; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
 ; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
@@ -6010,39 +6012,73 @@ define float @v_log10_f32_from_fpext_f16(i16 %src.i) {
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-SDAG-LABEL: v_log10_f32_from_fpext_f16:
-; GFX1100-SDAG:       ; %bb.0:
-; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1100-SDAG-NEXT:    v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX1100-SDAG-NEXT:    v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-SDAG-NEXT:    v_fma_f32 v2, 0x3e9a209a, v0, -v1
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT:    v_fmamk_f32 v2, v0, 0x3284fbcf, v2
-; GFX1100-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX1100-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1100-GISEL-LABEL: v_log10_f32_from_fpext_f16:
-; GFX1100-GISEL:       ; %bb.0:
-; GFX1100-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT:    v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX1100-GISEL-NEXT:    v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-GISEL-NEXT:    v_fma_f32 v2, 0x3e9a209a, v0, -v1
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_fmac_f32_e32 v2, 0x3284fbcf, v0
-; GFX1100-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX1100-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log10_f32_from_fpext_f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-SDAG-TRUE16-NEXT:    v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-SDAG-TRUE16-NEXT:    v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT:    v_fmamk_f32 v2, v0, 0x3284fbcf, v2
+; GFX1100-SDAG-TRUE16-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log10_f32_from_fpext_f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-SDAG-FAKE16-NEXT:    v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_fmamk_f32 v2, v0, 0x3284fbcf, v2
+; GFX1100-SDAG-FAKE16-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log10_f32_from_fpext_f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-TRUE16-NEXT:    v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-GISEL-TRUE16-NEXT:    v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-TRUE16-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log10_f32_from_fpext_f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-GISEL-FAKE16-NEXT:    v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_f32_from_fpext_f16:
 ; R600:       ; %bb.0:
@@ -6179,41 +6215,77 @@ define float @v_log10_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-SDAG-LABEL: v_log10_f32_from_fpext_math_f16:
-; GFX1100-SDAG:       ; %bb.0:
-; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX1100-SDAG-NEXT:    v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX1100-SDAG-NEXT:    v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT:    v_fma_f32 v2, 0x3e9a209a, v0, -v1
-; GFX1100-SDAG-NEXT:    v_fmamk_f32 v2, v0, 0x3284fbcf, v2
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
-; GFX1100-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX1100-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1100-GISEL-LABEL: v_log10_f32_from_fpext_math_f16:
-; GFX1100-GISEL:       ; %bb.0:
-; GFX1100-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX1100-GISEL-NEXT:    v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX1100-GISEL-NEXT:    v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_fma_f32 v2, 0x3e9a209a, v0, -v1
-; GFX1100-GISEL-NEXT:    v_fmac_f32_e32 v2, 0x3284fbcf, v0
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
-; GFX1100-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX1100-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log10_f32_from_fpext_math_f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-SDAG-TRUE16-NEXT:    v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT:    v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-SDAG-TRUE16-NEXT:    v_fmamk_f32 v2, v0, 0x3284fbcf, v2
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log10_f32_from_fpext_math_f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_fmamk_f32 v2, v0, 0x3284fbcf, v2
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log10_f32_from_fpext_math_f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-TRUE16-NEXT:    v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-TRUE16-NEXT:    v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log10_f32_from_fpext_math_f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-FAKE16-NEXT:    v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_f32_from_fpext_math_f16:
 ; R600:       ; %bb.0:
@@ -6376,13 +6448,37 @@ define half @v_log10_f16(half %in) {
 ; GFX900-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
 ; GFX900-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log10_f16:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log10_f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log10_f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log10_f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log10_f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_f16:
 ; R600:       ; %bb.0:
@@ -6432,13 +6528,37 @@ define half @v_log10_fabs_f16(half %in) {
 ; GFX900-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
 ; GFX900-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log10_fabs_f16:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_log_f16_e64 v0, |v0|
-; GFX1100-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log10_fabs_f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.l, |v0.l|
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log10_fabs_f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v0, |v0|
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log10_fabs_f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e64 v0.l, |v0.l|
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log10_fabs_f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e64 v0, |v0|
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_fabs_f16:
 ; R600:       ; %bb.0:
@@ -6489,13 +6609,37 @@ define half @v_log10_fneg_fabs_f16(half %in) {
 ; GFX900-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
 ; GFX900-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log10_fneg_fabs_f16:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_log_f16_e64 v0, -|v0|
-; GFX1100-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log10_fneg_fabs_f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.l, -|v0.l|
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log10_fneg_fabs_f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v0, -|v0|
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log10_fneg_fabs_f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e64 v0.l, -|v0.l|
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log10_fneg_fabs_f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e64 v0, -|v0|
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_fneg_fabs_f16:
 ; R600:       ; %bb.0:
@@ -6547,13 +6691,37 @@ define half @v_log10_fneg_f16(half %in) {
 ; GFX900-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
 ; GFX900-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log10_fneg_f16:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_log_f16_e64 v0, -v0
-; GFX1100-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log10_fneg_f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.l, -v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log10_fneg_f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v0, -v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log10_fneg_f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e64 v0.l, -v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log10_fneg_f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e64 v0, -v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_fneg_f16:
 ; R600:       ; %bb.0:
@@ -6604,13 +6772,37 @@ define half @v_log10_f16_fast(half %in) {
 ; GFX900-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
 ; GFX900-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log10_f16_fast:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log10_f16_fast:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log10_f16_fast:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log10_f16_fast:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log10_f16_fast:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_f16_fast:
 ; R600:       ; %bb.0:
@@ -6688,18 +6880,55 @@ define <2 x half> @v_log10_v2f16(<2 x half> %in) {
 ; GFX900-NEXT:    v_pack_b32_f16 v0, v1, v0
 ; GFX900-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log10_v2f16:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX1100-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX1100-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
-; GFX1100-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
-; GFX1100-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log10_v2f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x34d1, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log10_v2f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log10_v2f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x34d1, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log10_v2f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_v2f16:
 ; R600:       ; %bb.0:
@@ -6794,33 +7023,59 @@ define <2 x half> @v_log10_fabs_v2f16(<2 x half> %in) {
 ; GFX900-GISEL-NEXT:    v_pack_b32_f16 v0, v1, v0
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-SDAG-LABEL: v_log10_fabs_v2f16:
-; GFX1100-SDAG:       ; %bb.0:
-; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX1100-SDAG-NEXT:    v_log_f16_e64 v0, |v0|
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT:    v_log_f16_e64 v1, |v1|
-; GFX1100-SDAG-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
-; GFX1100-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX1100-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1100-GISEL-LABEL: v_log10_fabs_v2f16:
-; GFX1100-GISEL:       ; %bb.0:
-; GFX1100-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT:    v_and_b32_e32 v0, 0x7fff7fff, v0
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-GISEL-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX1100-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log10_fabs_v2f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.l, |v0.l|
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.h, |v0.h|
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x34d1, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log10_fabs_v2f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v0, |v0|
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v1, |v1|
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log10_fabs_v2f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_and_b32_e32 v0, 0x7fff7fff, v0
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x34d1, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log10_fabs_v2f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0x7fff7fff, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_fabs_v2f16:
 ; R600:       ; %bb.0:
@@ -6920,33 +7175,59 @@ define <2 x half> @v_log10_fneg_fabs_v2f16(<2 x half> %in) {
 ; GFX900-GISEL-NEXT:    v_pack_b32_f16 v0, v1, v0
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-SDAG-LABEL: v_log10_fneg_fabs_v2f16:
-; GFX1100-SDAG:       ; %bb.0:
-; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX1100-SDAG-NEXT:    v_log_f16_e64 v0, -|v0|
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT:    v_log_f16_e64 v1, -|v1|
-; GFX1100-SDAG-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
-; GFX1100-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX1100-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1100-GISEL-LABEL: v_log10_fneg_fabs_v2f16:
-; GFX1100-GISEL:       ; %bb.0:
-; GFX1100-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT:    v_or_b32_e32 v0, 0x80008000, v0
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-GISEL-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX1100-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log10_fneg_fabs_v2f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.l, -|v0.l|
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.h, -|v0.h|
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x34d1, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log10_fneg_fabs_v2f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v0, -|v0|
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v1, -|v1|
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log10_fneg_fabs_v2f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_or_b32_e32 v0, 0x80008000, v0
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x34d1, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log10_fneg_fabs_v2f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_or_b32_e32 v0, 0x80008000, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_fneg_fabs_v2f16:
 ; R600:       ; %bb.0:
@@ -7047,33 +7328,59 @@ define <2 x half> @v_log10_fneg_v2f16(<2 x half> %in) {
 ; GFX900-GISEL-NEXT:    v_pack_b32_f16 v0, v1, v0
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-SDAG-LABEL: v_log10_fneg_v2f16:
-; GFX1100-SDAG:       ; %bb.0:
-; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX1100-SDAG-NEXT:    v_log_f16_e64 v0, -v0
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT:    v_log_f16_e64 v1, -v1
-; GFX1100-SDAG-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
-; GFX1100-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX1100-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1100-GISEL-LABEL: v_log10_fneg_v2f16:
-; GFX1100-GISEL:       ; %bb.0:
-; GFX1100-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-GISEL-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX1100-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log10_fneg_v2f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.l, -v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.h, -v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x34d1, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log10_fneg_v2f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v0, -v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v1, -v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log10_fneg_v2f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x34d1, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log10_fneg_v2f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_fneg_v2f16:
 ; R600:       ; %bb.0:
@@ -7152,18 +7459,55 @@ define <2 x half> @v_log10_v2f16_fast(<2 x half> %in) {
 ; GFX900-NEXT:    v_pack_b32_f16 v0, v1, v0
 ; GFX900-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log10_v2f16_fast:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX1100-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX1100-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
-; GFX1100-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
-; GFX1100-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log10_v2f16_fast:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x34d1, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log10_v2f16_fast:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log10_v2f16_fast:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x34d1, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log10_v2f16_fast:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_v2f16_fast:
 ; R600:       ; %bb.0:
@@ -7244,21 +7588,65 @@ define <3 x half> @v_log10_v3f16(<3 x half> %in) {
 ; GFX900-NEXT:    v_pack_b32_f16 v0, v2, v0
 ; GFX900-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log10_v3f16:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
-; GFX1100-NEXT:    v_log_f16_e32 v2, v2
-; GFX1100-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
-; GFX1100-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
-; GFX1100-NEXT:    v_mul_f16_e32 v2, 0x34d1, v2
-; GFX1100-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT:    v_pack_b32_f16 v0, v0, v2
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log10_v3f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v1.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x34d1, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v1.l, 0x34d1, v1.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log10_v3f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v2, v2
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v2, 0x34d1, v2
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log10_v3f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v1.l, v1.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x34d1, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v1.l, 0x34d1, v1.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log10_v3f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v2, v2
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v2, 0x34d1, v2
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_v3f16:
 ; R600:       ; %bb.0:
@@ -7339,21 +7727,65 @@ define <3 x half> @v_log10_v3f16_fast(<3 x half> %in) {
 ; GFX900-NEXT:    v_pack_b32_f16 v0, v2, v0
 ; GFX900-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log10_v3f16_fast:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
-; GFX1100-NEXT:    v_log_f16_e32 v2, v2
-; GFX1100-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
-; GFX1100-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
-; GFX1100-NEXT:    v_mul_f16_e32 v2, 0x34d1, v2
-; GFX1100-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT:    v_pack_b32_f16 v0, v0, v2
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log10_v3f16_fast:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v1.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x34d1, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v1.l, 0x34d1, v1.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log10_v3f16_fast:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v2, v2
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v2, 0x34d1, v2
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log10_v3f16_fast:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v1.l, v1.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x34d1, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v1.l, 0x34d1, v1.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log10_v3f16_fast:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v2, v2
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v2, 0x34d1, v2
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_v3f16_fast:
 ; R600:       ; %bb.0:
@@ -7481,47 +7913,82 @@ define <4 x half> @v_log10_v4f16(<4 x half> %in) {
 ; GFX900-GISEL-NEXT:    v_pack_b32_f16 v1, v3, v1
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-SDAG-LABEL: v_log10_v4f16:
-; GFX1100-SDAG:       ; %bb.0:
-; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-SDAG-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX1100-SDAG-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-SDAG-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT:    v_log_f16_e32 v2, v2
-; GFX1100-SDAG-NEXT:    v_log_f16_e32 v3, v3
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
-; GFX1100-SDAG-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v2, 0x34d1, v2
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v3, 0x34d1, v3
-; GFX1100-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v2
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX1100-SDAG-NEXT:    v_pack_b32_f16 v1, v1, v3
-; GFX1100-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1100-GISEL-LABEL: v_log10_v4f16:
-; GFX1100-GISEL:       ; %bb.0:
-; GFX1100-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v2, v2
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v3, v3
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
-; GFX1100-GISEL-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v2, 0x34d1, v2
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v3, 0x34d1, v3
-; GFX1100-GISEL-NEXT:    v_pack_b32_f16 v0, v0, v2
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX1100-GISEL-NEXT:    v_pack_b32_f16 v1, v1, v3
-; GFX1100-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log10_v4f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v1.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v1.h, v1.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v1.l, 0x34d1, v1.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x34d1, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v1.h, 0x34d1, v1.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.l, v1.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log10_v4f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v2, v2
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v3, v3
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v2, 0x34d1, v2
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v3, 0x34d1, v3
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, v3
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log10_v4f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v1.l, v1.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v1.h, v1.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x34d1, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v1.l, 0x34d1, v1.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v1.h, 0x34d1, v1.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.l, v1.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log10_v4f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v2, v2
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v3, v3
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v2, 0x34d1, v2
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v3, 0x34d1, v3
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, v3
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_v4f16:
 ; R600:       ; %bb.0:
@@ -7649,47 +8116,82 @@ define <4 x half> @v_log10_v4f16_fast(<4 x half> %in) {
 ; GFX900-GISEL-NEXT:    v_pack_b32_f16 v1, v3, v1
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-SDAG-LABEL: v_log10_v4f16_fast:
-; GFX1100-SDAG:       ; %bb.0:
-; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-SDAG-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX1100-SDAG-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-SDAG-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT:    v_log_f16_e32 v2, v2
-; GFX1100-SDAG-NEXT:    v_log_f16_e32 v3, v3
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
-; GFX1100-SDAG-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v2, 0x34d1, v2
-; GFX1100-SDAG-NEXT:    v_mul_f16_e32 v3, 0x34d1, v3
-; GFX1100-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v2
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX1100-SDAG-NEXT:    v_pack_b32_f16 v1, v1, v3
-; GFX1100-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1100-GISEL-LABEL: v_log10_v4f16_fast:
-; GFX1100-GISEL:       ; %bb.0:
-; GFX1100-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v2, v2
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v3, v3
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
-; GFX1100-GISEL-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v2, 0x34d1, v2
-; GFX1100-GISEL-NEXT:    v_mul_f16_e32 v3, 0x34d1, v3
-; GFX1100-GISEL-NEXT:    v_pack_b32_f16 v0, v0, v2
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX1100-GISEL-NEXT:    v_pack_b32_f16 v1, v1, v3
-; GFX1100-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log10_v4f16_fast:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v1.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v1.h, v1.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v1.l, 0x34d1, v1.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x34d1, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v1.h, 0x34d1, v1.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.l, v1.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log10_v4f16_fast:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v2, v2
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v3, v3
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v2, 0x34d1, v2
+; GFX1100-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v3, 0x34d1, v3
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, v3
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log10_v4f16_fast:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v1.l, v1.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v1.h, v1.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.h, 0x34d1, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v1.l, 0x34d1, v1.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v1.h, 0x34d1, v1.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.l, v1.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log10_v4f16_fast:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v2, v2
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v3, v3
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x34d1, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v1, 0x34d1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v2, 0x34d1, v2
+; GFX1100-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v3, 0x34d1, v3
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, v3
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log10_v4f16_fast:
 ; R600:       ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
index a98baa2fdb35c..ea88f77f98735 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
@@ -5,8 +5,10 @@
 ; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GFX689,VI,GFX689-GISEL,VI-GISEL %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-SDAG,GFX900-SDAG %s
 ; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-GISEL,GFX900-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-SDAG,GFX1100-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-SDAG,GFX1100-SDAG-FAKE16 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-FAKE16 %s
 
 ; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
 ; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
@@ -3642,13 +3644,37 @@ define float @v_log2_f32_from_fpext_f16(i16 %src.i) {
 ; GFX689-NEXT:    v_log_f32_e32 v0, v0
 ; GFX689-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log2_f32_from_fpext_f16:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX1100-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT:    v_log_f32_e32 v0, v0
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log2_f32_from_fpext_f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log2_f32_from_fpext_f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log2_f32_from_fpext_f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log2_f32_from_fpext_f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_f32_from_fpext_f16:
 ; R600:       ; %bb.0:
@@ -3709,14 +3735,41 @@ define float @v_log2_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
 ; GFX900-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log2_f32_from_fpext_math_f16:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX1100-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX1100-NEXT:    v_log_f32_e32 v0, v0
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log2_f32_from_fpext_math_f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log2_f32_from_fpext_math_f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log2_f32_from_fpext_math_f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log2_f32_from_fpext_math_f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_f32_from_fpext_math_f16:
 ; R600:       ; %bb.0:
@@ -3837,11 +3890,29 @@ define half @v_log2_f16(half %in) {
 ; GFX900-NEXT:    v_log_f16_e32 v0, v0
 ; GFX900-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log2_f16:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log2_f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log2_f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log2_f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log2_f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_f16:
 ; R600:       ; %bb.0:
@@ -3887,11 +3958,29 @@ define half @v_log2_fabs_f16(half %in) {
 ; GFX900-NEXT:    v_log_f16_e64 v0, |v0|
 ; GFX900-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log2_fabs_f16:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_log_f16_e64 v0, |v0|
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log2_fabs_f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.l, |v0.l|
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log2_fabs_f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v0, |v0|
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log2_fabs_f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e64 v0.l, |v0.l|
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log2_fabs_f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e64 v0, |v0|
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_fabs_f16:
 ; R600:       ; %bb.0:
@@ -3938,11 +4027,29 @@ define half @v_log2_fneg_fabs_f16(half %in) {
 ; GFX900-NEXT:    v_log_f16_e64 v0, -|v0|
 ; GFX900-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log2_fneg_fabs_f16:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_log_f16_e64 v0, -|v0|
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log2_fneg_fabs_f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.l, -|v0.l|
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log2_fneg_fabs_f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v0, -|v0|
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log2_fneg_fabs_f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e64 v0.l, -|v0.l|
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log2_fneg_fabs_f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e64 v0, -|v0|
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_fneg_fabs_f16:
 ; R600:       ; %bb.0:
@@ -3990,11 +4097,29 @@ define half @v_log2_fneg_f16(half %in) {
 ; GFX900-NEXT:    v_log_f16_e64 v0, -v0
 ; GFX900-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log2_fneg_f16:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_log_f16_e64 v0, -v0
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log2_fneg_f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.l, -v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log2_fneg_f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v0, -v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log2_fneg_f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e64 v0.l, -v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log2_fneg_f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e64 v0, -v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_fneg_f16:
 ; R600:       ; %bb.0:
@@ -4041,11 +4166,29 @@ define half @v_log2_f16_fast(half %in) {
 ; GFX900-NEXT:    v_log_f16_e32 v0, v0
 ; GFX900-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log2_f16_fast:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log2_f16_fast:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log2_f16_fast:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log2_f16_fast:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log2_f16_fast:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_f16_fast:
 ; R600:       ; %bb.0:
@@ -4119,16 +4262,45 @@ define <2 x half> @v_log2_v2f16(<2 x half> %in) {
 ; GFX900-GISEL-NEXT:    v_pack_b32_f16 v0, v1, v0
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log2_v2f16:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX1100-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log2_v2f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log2_v2f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log2_v2f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log2_v2f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_v2f16:
 ; R600:       ; %bb.0:
@@ -4209,28 +4381,48 @@ define <2 x half> @v_log2_fabs_v2f16(<2 x half> %in) {
 ; GFX900-GISEL-NEXT:    v_pack_b32_f16 v0, v1, v0
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-SDAG-LABEL: v_log2_fabs_v2f16:
-; GFX1100-SDAG:       ; %bb.0:
-; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX1100-SDAG-NEXT:    v_log_f16_e64 v0, |v0|
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-SDAG-NEXT:    v_log_f16_e64 v1, |v1|
-; GFX1100-SDAG-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX1100-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1100-GISEL-LABEL: v_log2_fabs_v2f16:
-; GFX1100-GISEL:       ; %bb.0:
-; GFX1100-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT:    v_and_b32_e32 v0, 0x7fff7fff, v0
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-GISEL-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-GISEL-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX1100-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log2_fabs_v2f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.h, |v0.h|
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.l, |v0.l|
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log2_fabs_v2f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v0, |v0|
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v1, |v1|
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log2_fabs_v2f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_and_b32_e32 v0, 0x7fff7fff, v0
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log2_fabs_v2f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0x7fff7fff, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_fabs_v2f16:
 ; R600:       ; %bb.0:
@@ -4316,28 +4508,48 @@ define <2 x half> @v_log2_fneg_fabs_v2f16(<2 x half> %in) {
 ; GFX900-GISEL-NEXT:    v_pack_b32_f16 v0, v1, v0
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-SDAG-LABEL: v_log2_fneg_fabs_v2f16:
-; GFX1100-SDAG:       ; %bb.0:
-; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX1100-SDAG-NEXT:    v_log_f16_e64 v0, -|v0|
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-SDAG-NEXT:    v_log_f16_e64 v1, -|v1|
-; GFX1100-SDAG-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX1100-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1100-GISEL-LABEL: v_log2_fneg_fabs_v2f16:
-; GFX1100-GISEL:       ; %bb.0:
-; GFX1100-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT:    v_or_b32_e32 v0, 0x80008000, v0
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-GISEL-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-GISEL-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX1100-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log2_fneg_fabs_v2f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.h, -|v0.h|
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.l, -|v0.l|
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log2_fneg_fabs_v2f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v0, -|v0|
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v1, -|v1|
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log2_fneg_fabs_v2f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_or_b32_e32 v0, 0x80008000, v0
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log2_fneg_fabs_v2f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_or_b32_e32 v0, 0x80008000, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_fneg_fabs_v2f16:
 ; R600:       ; %bb.0:
@@ -4424,28 +4636,48 @@ define <2 x half> @v_log2_fneg_v2f16(<2 x half> %in) {
 ; GFX900-GISEL-NEXT:    v_pack_b32_f16 v0, v1, v0
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-SDAG-LABEL: v_log2_fneg_v2f16:
-; GFX1100-SDAG:       ; %bb.0:
-; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX1100-SDAG-NEXT:    v_log_f16_e64 v0, -v0
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-SDAG-NEXT:    v_log_f16_e64 v1, -v1
-; GFX1100-SDAG-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX1100-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1100-GISEL-LABEL: v_log2_fneg_v2f16:
-; GFX1100-GISEL:       ; %bb.0:
-; GFX1100-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-GISEL-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-GISEL-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX1100-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log2_fneg_v2f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.h, -v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e64 v0.l, -v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log2_fneg_v2f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v0, -v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e64 v1, -v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log2_fneg_v2f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log2_fneg_v2f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_fneg_v2f16:
 ; R600:       ; %bb.0:
@@ -4520,16 +4752,45 @@ define <2 x half> @v_log2_v2f16_fast(<2 x half> %in) {
 ; GFX900-GISEL-NEXT:    v_pack_b32_f16 v0, v1, v0
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log2_v2f16_fast:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX1100-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log2_v2f16_fast:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log2_v2f16_fast:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log2_v2f16_fast:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log2_v2f16_fast:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_v2f16_fast:
 ; R600:       ; %bb.0:
@@ -4615,17 +4876,49 @@ define <3 x half> @v_log2_v3f16(<3 x half> %in) {
 ; GFX900-GISEL-NEXT:    v_pack_b32_f16 v0, v2, v0
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log2_v3f16:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT:    v_log_f16_e32 v2, v2
-; GFX1100-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-NEXT:    v_pack_b32_f16 v0, v0, v2
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log2_v3f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v1.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log2_v3f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v2, v2
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log2_v3f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v1.l, v1.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log2_v3f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v2, v2
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_v3f16:
 ; R600:       ; %bb.0:
@@ -4711,17 +5004,49 @@ define <3 x half> @v_log2_v3f16_fast(<3 x half> %in) {
 ; GFX900-GISEL-NEXT:    v_pack_b32_f16 v0, v2, v0
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-LABEL: v_log2_v3f16_fast:
-; GFX1100:       ; %bb.0:
-; GFX1100-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT:    v_log_f16_e32 v2, v2
-; GFX1100-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-NEXT:    v_pack_b32_f16 v0, v0, v2
-; GFX1100-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log2_v3f16_fast:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v1.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log2_v3f16_fast:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v2, v2
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log2_v3f16_fast:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v1.l, v1.l
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log2_v3f16_fast:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v2, v2
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_v3f16_fast:
 ; R600:       ; %bb.0:
@@ -4823,35 +5148,60 @@ define <4 x half> @v_log2_v4f16(<4 x half> %in) {
 ; GFX900-GISEL-NEXT:    v_pack_b32_f16 v1, v3, v1
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-SDAG-LABEL: v_log2_v4f16:
-; GFX1100-SDAG:       ; %bb.0:
-; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-SDAG-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX1100-SDAG-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-SDAG-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT:    v_log_f16_e32 v2, v2
-; GFX1100-SDAG-NEXT:    v_log_f16_e32 v3, v3
-; GFX1100-SDAG-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v2
-; GFX1100-SDAG-NEXT:    v_pack_b32_f16 v1, v1, v3
-; GFX1100-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1100-GISEL-LABEL: v_log2_v4f16:
-; GFX1100-GISEL:       ; %bb.0:
-; GFX1100-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v2, v2
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v3, v3
-; GFX1100-GISEL-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-GISEL-NEXT:    v_pack_b32_f16 v0, v0, v2
-; GFX1100-GISEL-NEXT:    v_pack_b32_f16 v1, v1, v3
-; GFX1100-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log2_v4f16:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v1.h, v1.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v1.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.l, v1.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log2_v4f16:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v2, v2
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v3, v3
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, v3
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log2_v4f16:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v1.l, v1.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v1.h, v1.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_3)
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.l, v1.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log2_v4f16:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v2, v2
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v3, v3
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, v3
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_v4f16:
 ; R600:       ; %bb.0:
@@ -4953,35 +5303,60 @@ define <4 x half> @v_log2_v4f16_fast(<4 x half> %in) {
 ; GFX900-GISEL-NEXT:    v_pack_b32_f16 v1, v3, v1
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1100-SDAG-LABEL: v_log2_v4f16_fast:
-; GFX1100-SDAG:       ; %bb.0:
-; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-SDAG-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX1100-SDAG-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-SDAG-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT:    v_log_f16_e32 v2, v2
-; GFX1100-SDAG-NEXT:    v_log_f16_e32 v3, v3
-; GFX1100-SDAG-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-SDAG-NEXT:    v_pack_b32_f16 v0, v0, v2
-; GFX1100-SDAG-NEXT:    v_pack_b32_f16 v1, v1, v3
-; GFX1100-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1100-GISEL-LABEL: v_log2_v4f16_fast:
-; GFX1100-GISEL:       ; %bb.0:
-; GFX1100-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v0, v0
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v1, v1
-; GFX1100-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v2, v2
-; GFX1100-GISEL-NEXT:    v_log_f16_e32 v3, v3
-; GFX1100-GISEL-NEXT:    s_waitcnt_depctr 0xfff
-; GFX1100-GISEL-NEXT:    v_pack_b32_f16 v0, v0, v2
-; GFX1100-GISEL-NEXT:    v_pack_b32_f16 v1, v1, v3
-; GFX1100-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX1100-SDAG-TRUE16-LABEL: v_log2_v4f16_fast:
+; GFX1100-SDAG-TRUE16:       ; %bb.0:
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v1.h, v1.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-SDAG-TRUE16-NEXT:    v_log_f16_e32 v1.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.l, v1.h
+; GFX1100-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-FAKE16-LABEL: v_log2_v4f16_fast:
+; GFX1100-SDAG-FAKE16:       ; %bb.0:
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v2, v2
+; GFX1100-SDAG-FAKE16-NEXT:    v_log_f16_e32 v3, v3
+; GFX1100-SDAG-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX1100-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, v3
+; GFX1100-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-TRUE16-LABEL: v_log2_v4f16_fast:
+; GFX1100-GISEL-TRUE16:       ; %bb.0:
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.l, v0.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v0.h, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v1.l, v1.l
+; GFX1100-GISEL-TRUE16-NEXT:    v_log_f16_e32 v1.h, v1.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_3)
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.l, v1.h
+; GFX1100-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-FAKE16-LABEL: v_log2_v4f16_fast:
+; GFX1100-GISEL-FAKE16:       ; %bb.0:
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v0, v0
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v1, v1
+; GFX1100-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v2, v2
+; GFX1100-GISEL-FAKE16-NEXT:    v_log_f16_e32 v3, v3
+; GFX1100-GISEL-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX1100-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, v3
+; GFX1100-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_log2_v4f16_fast:
 ; R600:       ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.powi.ll b/llvm/test/CodeGen/AMDGPU/llvm.powi.ll
index a467e29d0bff6..64cd94134f8f9 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.powi.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.powi.ll
@@ -1,7 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii < %s | FileCheck -check-prefixes=GFX78,GFX7 %s
 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefixes=GFX78,GFX8 %s
-; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define i16 @v_powi_f16(i16 %l, i32 %r) {
 ; GFX78-LABEL: v_powi_f16:
@@ -15,19 +16,33 @@ define i16 @v_powi_f16(i16 %l, i32 %r) {
 ; GFX78-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX78-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_powi_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-NEXT:    v_cvt_f32_i32_e32 v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_log_f32_e32 v0, v0
-; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-NEXT:    v_exp_f32_e32 v0, v0
-; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_powi_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_i32_e32 v1, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_mul_dx9_zero_f32_e32 v0, v1, v0
+; GFX11-TRUE16-NEXT:    v_exp_f32_e32 v0, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_powi_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_i32_e32 v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_log_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_mul_dx9_zero_f32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT:    v_exp_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %l.cast = bitcast i16 %l to half
   %res = call half @llvm.powi.f16.i32(half %l.cast, i32 %r)
   %res.cast = bitcast half %res to i16
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.round.ll b/llvm/test/CodeGen/AMDGPU/llvm.round.ll
index c0a85bba93b73..c29362898f40e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.round.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.round.ll
@@ -2,7 +2,8 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck --check-prefixes=GFX6 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GFX8 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GFX9 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GFX11,GFX11-FAKE16 %s
 ; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck --check-prefixes=R600 %s
 
 define amdgpu_kernel void @round_f32(ptr addrspace(1) %out, float %x) #0 {
@@ -827,25 +828,45 @@ define amdgpu_kernel void @round_f16(ptr addrspace(1) %out, i32 %x.arg) #0 {
 ; GFX9-NEXT:    buffer_store_short v0, off, s[0:3], 0
 ; GFX9-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: round_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_trunc_f16_e32 v0, s2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_sub_f16_e32 v1, s2, v0
-; GFX11-NEXT:    v_cmp_ge_f16_e64 s3, |v1|, 0.5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cndmask_b32_e64 v1, 0, 0x3c00, s3
-; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX11-NEXT:    v_bfi_b32 v1, 0x7fff, v1, s2
-; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX11-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: round_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b32 s2, s[4:5], 0x2c
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, s2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_sub_f16_e32 v0.h, s2, v0.l
+; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e64 s0, |v0.h|, 0.5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0, 0x3c00, s0
+; GFX11-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0x7fff, v1, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: round_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    s_load_b32 s2, s[4:5], 0x2c
+; GFX11-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_trunc_f16_e32 v0, s2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_sub_f16_e32 v1, s2, v0
+; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e64 s3, |v1|, 0.5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v1, 0, 0x3c00, s3
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-FAKE16-NEXT:    v_bfi_b32 v1, 0x7fff, v1, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX11-FAKE16-NEXT:    s_endpgm
 ;
 ; R600-LABEL: round_f16:
 ; R600:       ; %bb.0:
@@ -968,36 +989,67 @@ define amdgpu_kernel void @round_v2f16(ptr addrspace(1) %out, i32 %in.arg) #0 {
 ; GFX9-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX9-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: round_v2f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_lshr_b32 s3, s2, 16
-; GFX11-NEXT:    v_trunc_f16_e32 v1, s2
-; GFX11-NEXT:    v_trunc_f16_e32 v0, s3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_sub_f16_e32 v3, s2, v1
-; GFX11-NEXT:    v_sub_f16_e32 v2, s3, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cmp_ge_f16_e64 s4, |v2|, 0.5
-; GFX11-NEXT:    v_cndmask_b32_e64 v2, 0, 0x3c00, s4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cmp_ge_f16_e64 s4, |v3|, 0.5
-; GFX11-NEXT:    v_bfi_b32 v2, 0x7fff, v2, s3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e64 v3, 0, 0x3c00, s4
-; GFX11-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_bfi_b32 v3, 0x7fff, v3, s2
-; GFX11-NEXT:    s_mov_b32 s2, -1
-; GFX11-NEXT:    v_add_f16_e32 v1, v1, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_pack_b32_f16 v0, v1, v0
-; GFX11-NEXT:    buffer_store_b32 v0, off, s[0:3], 0
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: round_v2f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b32 s2, s[4:5], 0x2c
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_lshr_b32 s3, s2, 16
+; GFX11-TRUE16-NEXT:    v_trunc_f16_e32 v0.h, s2
+; GFX11-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, s3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_sub_f16_e32 v1.h, s2, v0.h
+; GFX11-TRUE16-NEXT:    v_sub_f16_e32 v1.l, s3, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e64 s1, |v1.h|, 0.5
+; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e64 s0, |v1.l|, 0.5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, 0, 0x3c00, s1
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0, 0x3c00, s0
+; GFX11-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, s2
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0x7fff, v1, s3
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_add_f16_e32 v0.h, v0.h, v2.l
+; GFX11-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v0.l
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    buffer_store_b32 v0, off, s[0:3], 0
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: round_v2f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    s_load_b32 s2, s[4:5], 0x2c
+; GFX11-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_lshr_b32 s3, s2, 16
+; GFX11-FAKE16-NEXT:    v_trunc_f16_e32 v1, s2
+; GFX11-FAKE16-NEXT:    v_trunc_f16_e32 v0, s3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_sub_f16_e32 v3, s2, v1
+; GFX11-FAKE16-NEXT:    v_sub_f16_e32 v2, s3, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e64 s4, |v2|, 0.5
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v2, 0, 0x3c00, s4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e64 s4, |v3|, 0.5
+; GFX11-FAKE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, s3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v3, 0, 0x3c00, s4
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_bfi_b32 v3, 0x7fff, v3, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT:    v_add_f16_e32 v1, v1, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v1, v0
+; GFX11-FAKE16-NEXT:    buffer_store_b32 v0, off, s[0:3], 0
+; GFX11-FAKE16-NEXT:    s_endpgm
 ;
 ; R600-LABEL: round_v2f16:
 ; R600:       ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
index 4031be65fab61..3b0f8523e1b52 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
@@ -3,7 +3,8 @@
 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GFX7-HSA %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8-NOHSA %s
 ; RUN: llc -mtriple=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
 
 ; TODO: NOT AND
 define amdgpu_kernel void @constant_load_i8(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
@@ -79,15 +80,25 @@ define amdgpu_kernel void @constant_load_i8(ptr addrspace(1) %out, ptr addrspace
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_load_i8:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v1, v0, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b8 v0, v1, s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_load_i8:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_u8 v0, v1, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    global_store_b8 v1, v0, s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_load_i8:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u8 v1, v0, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    global_store_b8 v0, v1, s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
 entry:
   %ld = load i8, ptr addrspace(4) %in
   store i8 %ld, ptr addrspace(1) %out
@@ -167,15 +178,25 @@ define amdgpu_kernel void @constant_load_v2i8(ptr addrspace(1) %out, ptr addrspa
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_load_v2i8:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u16 v1, v0, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_load_v2i8:
+; GFX12-TRUE16:       ; %bb.0: ; %entry
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_load_v2i8:
+; GFX12-FAKE16:       ; %bb.0: ; %entry
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
 entry:
   %ld = load <2 x i8>, ptr addrspace(4) %in
   store <2 x i8> %ld, ptr addrspace(1) %out
@@ -923,19 +944,33 @@ define amdgpu_kernel void @constant_zextload_v2i8_to_v2i32(ptr addrspace(1) %out
 ; EG-NEXT:     LSHR * T5.X, KC0[2].Y, literal.y,
 ; EG-NEXT:    255(3.573311e-43), 2(2.802597e-45)
 ;
-; GFX12-LABEL: constant_zextload_v2i8_to_v2i32:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v2, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u16 v0, v2, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v0
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX12-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_zextload_v2i8_to_v2i32:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_b16 v0, v2, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v0
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-TRUE16-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_zextload_v2i8_to_v2i32:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u16 v0, v2, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-FAKE16-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
   %load = load <2 x i8>, ptr addrspace(4) %in
   %ext = zext <2 x i8> %load to <2 x i32>
   store <2 x i32> %ext, ptr addrspace(1) %out
@@ -5279,16 +5314,27 @@ define amdgpu_kernel void @constant_zextload_i8_to_i64(ptr addrspace(1) %out, pt
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_zextload_i8_to_i64:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v1, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v1, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT:    global_store_b64 v1, v[0:1], s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_zextload_i8_to_i64:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_u8 v0, v1, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-TRUE16-NEXT:    global_store_b64 v1, v[0:1], s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_zextload_i8_to_i64:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u8 v0, v1, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT:    global_store_b64 v1, v[0:1], s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
   %a = load i8, ptr addrspace(4) %in
   %ext = zext i8 %a to i64
   store i64 %ext, ptr addrspace(1) %out
@@ -5366,18 +5412,31 @@ define amdgpu_kernel void @constant_sextload_i8_to_i64(ptr addrspace(1) %out, pt
 ; EG-NEXT:     ASHR * T0.Y, PV.X, literal.x,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_sextload_i8_to_i64:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v2, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_i8 v0, v2, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_bfe_i32 v0, v0, 0, 16
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
-; GFX12-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_sextload_i8_to_i64:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_i8 v0, v2, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
+; GFX12-TRUE16-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_sextload_i8_to_i64:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_i8 v0, v2, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
+; GFX12-FAKE16-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
   %a = load i8, ptr addrspace(4) %in
   %ext = sext i8 %a to i64
   store i64 %ext, ptr addrspace(1) %out
@@ -5537,18 +5596,31 @@ define amdgpu_kernel void @constant_sextload_v1i8_to_v1i64(ptr addrspace(1) %out
 ; EG-NEXT:     ASHR * T0.Y, PV.X, literal.x,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_sextload_v1i8_to_v1i64:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v2, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_i8 v0, v2, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_bfe_i32 v0, v0, 0, 16
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
-; GFX12-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_sextload_v1i8_to_v1i64:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_i8 v0, v2, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
+; GFX12-TRUE16-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_sextload_v1i8_to_v1i64:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_i8 v0, v2, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
+; GFX12-FAKE16-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
   %load = load <1 x i8>, ptr addrspace(4) %in
   %ext = sext <1 x i8> %load to <1 x i64>
   store <1 x i64> %ext, ptr addrspace(1) %out
@@ -5645,19 +5717,33 @@ define amdgpu_kernel void @constant_zextload_v2i8_to_v2i64(ptr addrspace(1) %out
 ; EG-NEXT:     LSHR * T5.X, KC0[2].Y, literal.y,
 ; EG-NEXT:    255(3.573311e-43), 2(2.802597e-45)
 ;
-; GFX12-LABEL: constant_zextload_v2i8_to_v2i64:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v1, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u16 v0, v1, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v0
-; GFX12-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_and_b32 v0, 0xff, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 8, v2
-; GFX12-NEXT:    global_store_b128 v1, v[0:3], s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_zextload_v2i8_to_v2i64:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v0
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_and_b32 v0, 0xff, v0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 8, v2
+; GFX12-TRUE16-NEXT:    global_store_b128 v1, v[0:3], s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_zextload_v2i8_to_v2i64:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u16 v0, v1, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v0
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_and_b32 v0, 0xff, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 8, v2
+; GFX12-FAKE16-NEXT:    global_store_b128 v1, v[0:3], s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
   %load = load <2 x i8>, ptr addrspace(4) %in
   %ext = zext <2 x i8> %load to <2 x i64>
   store <2 x i64> %ext, ptr addrspace(1) %out
@@ -5757,22 +5843,39 @@ define amdgpu_kernel void @constant_sextload_v2i8_to_v2i64(ptr addrspace(1) %out
 ; EG-NEXT:     ASHR * T4.W, PV.Z, literal.y,
 ; EG-NEXT:    2(2.802597e-45), 31(4.344025e-44)
 ;
-; GFX12-LABEL: constant_sextload_v2i8_to_v2i64:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v4, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u16 v0, v4, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
-; GFX12-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_bfe_i32 v2, v1, 0, 8
-; GFX12-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
-; GFX12-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_sextload_v2i8_to_v2i64:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v4, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_b16 v0, v4, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
+; GFX12-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_bfe_i32 v2, v1, 0, 8
+; GFX12-TRUE16-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
+; GFX12-TRUE16-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_sextload_v2i8_to_v2i64:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v4, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u16 v0, v4, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
+; GFX12-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_bfe_i32 v2, v1, 0, 8
+; GFX12-FAKE16-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
+; GFX12-FAKE16-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
   %load = load <2 x i8>, ptr addrspace(4) %in
   %ext = sext <2 x i8> %load to <2 x i64>
   store <2 x i64> %ext, ptr addrspace(1) %out
@@ -9063,15 +9166,25 @@ define amdgpu_kernel void @constant_zextload_i8_to_i16(ptr addrspace(1) %out, pt
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_zextload_i8_to_i16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v1, v0, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_zextload_i8_to_i16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_u8 v0, v1, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_zextload_i8_to_i16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u8 v1, v0, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
   %a = load i8, ptr addrspace(4) %in
   %ext = zext i8 %a to i16
   store i16 %ext, ptr addrspace(1) %out
@@ -9152,15 +9265,25 @@ define amdgpu_kernel void @constant_sextload_i8_to_i16(ptr addrspace(1) %out, pt
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_sextload_i8_to_i16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_i8 v1, v0, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_sextload_i8_to_i16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_i8 v0, v1, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_sextload_i8_to_i16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_i8 v1, v0, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
   %a = load i8, ptr addrspace(4) %in
   %ext = sext i8 %a to i16
   store i16 %ext, ptr addrspace(1) %out
@@ -9239,15 +9362,25 @@ define amdgpu_kernel void @constant_zextload_v1i8_to_v1i16(ptr addrspace(1) %out
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_zextload_v1i8_to_v1i16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v1, v0, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_zextload_v1i8_to_v1i16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_u8 v0, v1, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_zextload_v1i8_to_v1i16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u8 v1, v0, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
   %load = load <1 x i8>, ptr addrspace(4) %in
   %ext = zext <1 x i8> %load to <1 x i16>
   store <1 x i16> %ext, ptr addrspace(1) %out
@@ -9328,15 +9461,25 @@ define amdgpu_kernel void @constant_sextload_v1i8_to_v1i16(ptr addrspace(1) %out
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_sextload_v1i8_to_v1i16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_i8 v1, v0, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_sextload_v1i8_to_v1i16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_i8 v0, v1, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_sextload_v1i8_to_v1i16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_i8 v1, v0, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
   %load = load <1 x i8>, ptr addrspace(4) %in
   %ext = sext <1 x i8> %load to <1 x i16>
   store <1 x i16> %ext, ptr addrspace(1) %out
@@ -9421,22 +9564,39 @@ define amdgpu_kernel void @constant_zextload_v2i8_to_v2i16(ptr addrspace(1) %out
 ; EG-NEXT:     LSHR * T6.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_zextload_v2i8_to_v2i16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u16 v1, v0, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff, v1
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 8, v2
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-NEXT:    global_store_b32 v0, v1, s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_zextload_v2i8_to_v2i16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_b16 v1, v0, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v1
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 8, v2
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX12-TRUE16-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_zextload_v2i8_to_v2i16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v1
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 8, v2
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX12-FAKE16-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
   %load = load <2 x i8>, ptr addrspace(4) %in
   %ext = zext <2 x i8> %load to <2 x i16>
   store <2 x i16> %ext, ptr addrspace(1) %out
@@ -9538,22 +9698,39 @@ define amdgpu_kernel void @constant_sextload_v2i8_to_v2i16(ptr addrspace(1) %out
 ; EG-NEXT:     LSHR * T6.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_sextload_v2i8_to_v2i16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u16 v1, v0, s[2:3]
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_bfe_i32 v2, v1, 0, 16
-; GFX12-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 8, v2
-; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-NEXT:    global_store_b32 v0, v1, s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_sextload_v2i8_to_v2i16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_b16 v1, v0, s[2:3]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_bfe_i32 v2, v1, 0, 16
+; GFX12-TRUE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 8, v2
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX12-TRUE16-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_sextload_v2i8_to_v2i16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_bfe_i32 v2, v1, 0, 16
+; GFX12-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 8, v2
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
+; GFX12-FAKE16-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
   %load = load <2 x i8>, ptr addrspace(4) %in
   %ext = sext <2 x i8> %load to <2 x i16>
   store <2 x i16> %ext, ptr addrspace(1) %out
@@ -9763,25 +9940,46 @@ define amdgpu_kernel void @constant_sextload_v4i8_to_v4i16(ptr addrspace(1) %out
 ; EG-NEXT:     BFE_INT * T5.Y, PV.W, 0.0, literal.x,
 ; EG-NEXT:    8(1.121039e-44), 0(0.000000e+00)
 ;
-; GFX12-LABEL: constant_sextload_v4i8_to_v4i16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_load_b32 s2, s[2:3], 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_lshr_b32 s3, s2, 16
-; GFX12-NEXT:    s_sext_i32_i16 s5, s2
-; GFX12-NEXT:    s_ashr_i32 s4, s2, 24
-; GFX12-NEXT:    s_bfe_i32 s2, s2, 0x80000
-; GFX12-NEXT:    s_lshr_b32 s5, s5, 8
-; GFX12-NEXT:    s_bfe_i32 s3, s3, 0x80000
-; GFX12-NEXT:    s_pack_ll_b32_b16 s2, s2, s5
-; GFX12-NEXT:    s_pack_ll_b32_b16 s3, s3, s4
-; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
-; GFX12-NEXT:    v_mov_b32_e32 v0, s2
-; GFX12-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_sextload_v4i8_to_v4i16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_load_b32 s2, s[2:3], 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s3, s2, 16
+; GFX12-TRUE16-NEXT:    s_ashr_i32 s4, s2, 24
+; GFX12-TRUE16-NEXT:    s_mov_b32 s5, s2
+; GFX12-TRUE16-NEXT:    s_sext_i32_i16 s2, s2
+; GFX12-TRUE16-NEXT:    s_bfe_i32 s5, s5, 0x80000
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s2, s2, 8
+; GFX12-TRUE16-NEXT:    s_bfe_i32 s3, s3, 0x80000
+; GFX12-TRUE16-NEXT:    s_pack_ll_b32_b16 s2, s5, s2
+; GFX12-TRUE16-NEXT:    s_pack_ll_b32_b16 s3, s3, s4
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v0, s2
+; GFX12-TRUE16-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_sextload_v4i8_to_v4i16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_load_b32 s2, s[2:3], 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s3, s2, 16
+; GFX12-FAKE16-NEXT:    s_sext_i32_i16 s5, s2
+; GFX12-FAKE16-NEXT:    s_ashr_i32 s4, s2, 24
+; GFX12-FAKE16-NEXT:    s_bfe_i32 s2, s2, 0x80000
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s5, s5, 8
+; GFX12-FAKE16-NEXT:    s_bfe_i32 s3, s3, 0x80000
+; GFX12-FAKE16-NEXT:    s_pack_ll_b32_b16 s2, s2, s5
+; GFX12-FAKE16-NEXT:    s_pack_ll_b32_b16 s3, s3, s4
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v0, s2
+; GFX12-FAKE16-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
   %load = load <4 x i8>, ptr addrspace(4) %in
   %ext = sext <4 x i8> %load to <4 x i16>
   store <4 x i16> %ext, ptr addrspace(1) %out
@@ -10072,34 +10270,64 @@ define amdgpu_kernel void @constant_sextload_v8i8_to_v8i16(ptr addrspace(1) %out
 ; EG-NEXT:     BFE_INT * T6.Y, PS, 0.0, literal.y,
 ; EG-NEXT:    2(2.802597e-45), 8(1.121039e-44)
 ;
-; GFX12-LABEL: constant_sextload_v8i8_to_v8i16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_ashr_i64 s[4:5], s[2:3], 56
-; GFX12-NEXT:    s_lshr_b32 s6, s2, 16
-; GFX12-NEXT:    s_lshr_b32 s7, s3, 16
-; GFX12-NEXT:    s_bfe_i32 s5, s3, 0x80000
-; GFX12-NEXT:    s_sext_i32_i16 s3, s3
-; GFX12-NEXT:    s_ashr_i32 s8, s2, 24
-; GFX12-NEXT:    s_bfe_i32 s9, s2, 0x80000
-; GFX12-NEXT:    s_sext_i32_i16 s2, s2
-; GFX12-NEXT:    s_bfe_i32 s7, s7, 0x80000
-; GFX12-NEXT:    s_lshr_b32 s3, s3, 8
-; GFX12-NEXT:    s_bfe_i32 s6, s6, 0x80000
-; GFX12-NEXT:    s_lshr_b32 s2, s2, 8
-; GFX12-NEXT:    s_pack_ll_b32_b16 s4, s7, s4
-; GFX12-NEXT:    s_pack_ll_b32_b16 s3, s5, s3
-; GFX12-NEXT:    s_pack_ll_b32_b16 s2, s9, s2
-; GFX12-NEXT:    s_pack_ll_b32_b16 s5, s6, s8
-; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT:    v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s5
-; GFX12-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v3, s4
-; GFX12-NEXT:    v_mov_b32_e32 v2, s3
-; GFX12-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_sextload_v8i8_to_v8i16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_ashr_i64 s[4:5], s[2:3], 56
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s6, s2, 16
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s7, s3, 16
+; GFX12-TRUE16-NEXT:    s_bfe_i32 s5, s3, 0x80000
+; GFX12-TRUE16-NEXT:    s_sext_i32_i16 s3, s3
+; GFX12-TRUE16-NEXT:    s_ashr_i32 s8, s2, 24
+; GFX12-TRUE16-NEXT:    s_mov_b32 s9, s2
+; GFX12-TRUE16-NEXT:    s_sext_i32_i16 s2, s2
+; GFX12-TRUE16-NEXT:    s_bfe_i32 s7, s7, 0x80000
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s3, s3, 8
+; GFX12-TRUE16-NEXT:    s_bfe_i32 s6, s6, 0x80000
+; GFX12-TRUE16-NEXT:    s_bfe_i32 s9, s9, 0x80000
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s2, s2, 8
+; GFX12-TRUE16-NEXT:    s_pack_ll_b32_b16 s4, s7, s4
+; GFX12-TRUE16-NEXT:    s_pack_ll_b32_b16 s3, s5, s3
+; GFX12-TRUE16-NEXT:    s_pack_ll_b32_b16 s2, s9, s2
+; GFX12-TRUE16-NEXT:    s_pack_ll_b32_b16 s5, s6, s8
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s5
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v3, s4
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v2, s3
+; GFX12-TRUE16-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_sextload_v8i8_to_v8i16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_ashr_i64 s[4:5], s[2:3], 56
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s6, s2, 16
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s7, s3, 16
+; GFX12-FAKE16-NEXT:    s_bfe_i32 s5, s3, 0x80000
+; GFX12-FAKE16-NEXT:    s_sext_i32_i16 s3, s3
+; GFX12-FAKE16-NEXT:    s_ashr_i32 s8, s2, 24
+; GFX12-FAKE16-NEXT:    s_bfe_i32 s9, s2, 0x80000
+; GFX12-FAKE16-NEXT:    s_sext_i32_i16 s2, s2
+; GFX12-FAKE16-NEXT:    s_bfe_i32 s7, s7, 0x80000
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s3, s3, 8
+; GFX12-FAKE16-NEXT:    s_bfe_i32 s6, s6, 0x80000
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s2, s2, 8
+; GFX12-FAKE16-NEXT:    s_pack_ll_b32_b16 s4, s7, s4
+; GFX12-FAKE16-NEXT:    s_pack_ll_b32_b16 s3, s5, s3
+; GFX12-FAKE16-NEXT:    s_pack_ll_b32_b16 s2, s9, s2
+; GFX12-FAKE16-NEXT:    s_pack_ll_b32_b16 s5, s6, s8
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s5
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v3, s4
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v2, s3
+; GFX12-FAKE16-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
   %load = load <8 x i8>, ptr addrspace(4) %in
   %ext = sext <8 x i8> %load to <8 x i16>
   store <8 x i16> %ext, ptr addrspace(1) %out
@@ -11491,94 +11719,183 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i16(ptr addrspace(1) %o
 ; EG-NEXT:     BFE_INT * T18.Y, PV.Z, 0.0, literal.y,
 ; EG-NEXT:    2(2.802597e-45), 8(1.121039e-44)
 ;
-; GFX12-LABEL: constant_sextload_v32i8_to_v32i16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[8:11], s[4:5], 0x24
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_load_b256 s[0:7], s[10:11], 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_lshr_b32 s13, s5, 16
-; GFX12-NEXT:    s_lshr_b32 s16, s0, 16
-; GFX12-NEXT:    s_lshr_b32 s17, s1, 16
-; GFX12-NEXT:    s_ashr_i32 s18, s1, 16
-; GFX12-NEXT:    s_bfe_i32 s19, s1, 0x80000
-; GFX12-NEXT:    s_sext_i32_i16 s20, s1
-; GFX12-NEXT:    s_ashr_i32 s21, s0, 24
-; GFX12-NEXT:    s_bfe_i32 s22, s0, 0x80000
-; GFX12-NEXT:    s_sext_i32_i16 s23, s0
-; GFX12-NEXT:    s_ashr_i64 s[0:1], s[4:5], 56
-; GFX12-NEXT:    s_lshr_b32 s12, s4, 16
-; GFX12-NEXT:    s_bfe_i32 s1, s5, 0x80000
-; GFX12-NEXT:    s_sext_i32_i16 s5, s5
-; GFX12-NEXT:    s_bfe_i32 s13, s13, 0x80000
-; GFX12-NEXT:    s_lshr_b32 s5, s5, 8
-; GFX12-NEXT:    s_pack_ll_b32_b16 s0, s13, s0
-; GFX12-NEXT:    s_ashr_i32 s13, s4, 24
-; GFX12-NEXT:    s_bfe_i32 s12, s12, 0x80000
-; GFX12-NEXT:    s_pack_ll_b32_b16 s1, s1, s5
-; GFX12-NEXT:    s_pack_ll_b32_b16 s5, s12, s13
-; GFX12-NEXT:    s_sext_i32_i16 s12, s4
-; GFX12-NEXT:    s_bfe_i32 s4, s4, 0x80000
-; GFX12-NEXT:    s_lshr_b32 s12, s12, 8
-; GFX12-NEXT:    s_ashr_i32 s13, s7, 16
-; GFX12-NEXT:    s_pack_ll_b32_b16 s4, s4, s12
-; GFX12-NEXT:    s_lshr_b32 s12, s13, 8
-; GFX12-NEXT:    s_sext_i32_i16 s13, s7
-; GFX12-NEXT:    s_lshr_b32 s11, s7, 16
-; GFX12-NEXT:    s_bfe_i32 s7, s7, 0x80000
-; GFX12-NEXT:    s_lshr_b32 s13, s13, 8
-; GFX12-NEXT:    s_lshr_b32 s10, s6, 16
-; GFX12-NEXT:    s_bfe_i32 s11, s11, 0x80000
-; GFX12-NEXT:    s_pack_ll_b32_b16 s7, s7, s13
-; GFX12-NEXT:    s_sext_i32_i16 s13, s6
-; GFX12-NEXT:    s_lshr_b32 s14, s2, 16
-; GFX12-NEXT:    s_lshr_b32 s15, s3, 16
-; GFX12-NEXT:    s_ashr_i32 s24, s3, 16
-; GFX12-NEXT:    s_bfe_i32 s25, s3, 0x80000
-; GFX12-NEXT:    s_sext_i32_i16 s3, s3
-; GFX12-NEXT:    s_ashr_i32 s26, s2, 24
-; GFX12-NEXT:    s_bfe_i32 s27, s2, 0x80000
-; GFX12-NEXT:    s_sext_i32_i16 s2, s2
-; GFX12-NEXT:    s_pack_ll_b32_b16 s11, s11, s12
-; GFX12-NEXT:    s_ashr_i32 s12, s6, 24
-; GFX12-NEXT:    s_bfe_i32 s6, s6, 0x80000
-; GFX12-NEXT:    s_lshr_b32 s13, s13, 8
-; GFX12-NEXT:    s_bfe_i32 s10, s10, 0x80000
-; GFX12-NEXT:    s_lshr_b32 s24, s24, 8
-; GFX12-NEXT:    s_bfe_i32 s15, s15, 0x80000
-; GFX12-NEXT:    s_lshr_b32 s3, s3, 8
-; GFX12-NEXT:    s_bfe_i32 s14, s14, 0x80000
-; GFX12-NEXT:    s_lshr_b32 s2, s2, 8
-; GFX12-NEXT:    s_pack_ll_b32_b16 s6, s6, s13
-; GFX12-NEXT:    s_pack_ll_b32_b16 s10, s10, s12
-; GFX12-NEXT:    s_lshr_b32 s18, s18, 8
-; GFX12-NEXT:    s_bfe_i32 s17, s17, 0x80000
-; GFX12-NEXT:    s_lshr_b32 s20, s20, 8
-; GFX12-NEXT:    s_bfe_i32 s16, s16, 0x80000
-; GFX12-NEXT:    s_lshr_b32 s23, s23, 8
-; GFX12-NEXT:    v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v1, s10
-; GFX12-NEXT:    s_pack_ll_b32_b16 s15, s15, s24
-; GFX12-NEXT:    s_pack_ll_b32_b16 s3, s25, s3
-; GFX12-NEXT:    s_pack_ll_b32_b16 s14, s14, s26
-; GFX12-NEXT:    s_pack_ll_b32_b16 s2, s27, s2
-; GFX12-NEXT:    v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v3, s11
-; GFX12-NEXT:    v_dual_mov_b32 v2, s7 :: v_dual_mov_b32 v5, s5
-; GFX12-NEXT:    s_pack_ll_b32_b16 s17, s17, s18
-; GFX12-NEXT:    s_pack_ll_b32_b16 s18, s19, s20
-; GFX12-NEXT:    s_pack_ll_b32_b16 s16, s16, s21
-; GFX12-NEXT:    s_pack_ll_b32_b16 s19, s22, s23
-; GFX12-NEXT:    v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s0
-; GFX12-NEXT:    v_dual_mov_b32 v6, s1 :: v_dual_mov_b32 v9, s14
-; GFX12-NEXT:    v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v11, s15
-; GFX12-NEXT:    v_dual_mov_b32 v10, s3 :: v_dual_mov_b32 v13, s16
-; GFX12-NEXT:    v_dual_mov_b32 v12, s19 :: v_dual_mov_b32 v15, s17
-; GFX12-NEXT:    v_mov_b32_e32 v14, s18
-; GFX12-NEXT:    s_clause 0x3
-; GFX12-NEXT:    global_store_b128 v16, v[0:3], s[8:9] offset:48
-; GFX12-NEXT:    global_store_b128 v16, v[4:7], s[8:9] offset:32
-; GFX12-NEXT:    global_store_b128 v16, v[8:11], s[8:9] offset:16
-; GFX12-NEXT:    global_store_b128 v16, v[12:15], s[8:9]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: constant_sextload_v32i8_to_v32i16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[8:11], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_load_b256 s[0:7], s[10:11], 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s13, s5, 16
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s16, s0, 16
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s17, s1, 16
+; GFX12-TRUE16-NEXT:    s_ashr_i32 s18, s1, 16
+; GFX12-TRUE16-NEXT:    s_bfe_i32 s19, s1, 0x80000
+; GFX12-TRUE16-NEXT:    s_sext_i32_i16 s20, s1
+; GFX12-TRUE16-NEXT:    s_ashr_i32 s21, s0, 24
+; GFX12-TRUE16-NEXT:    s_bfe_i32 s22, s0, 0x80000
+; GFX12-TRUE16-NEXT:    s_sext_i32_i16 s23, s0
+; GFX12-TRUE16-NEXT:    s_ashr_i64 s[0:1], s[4:5], 56
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s12, s4, 16
+; GFX12-TRUE16-NEXT:    s_sext_i32_i16 s1, s5
+; GFX12-TRUE16-NEXT:    s_bfe_i32 s13, s13, 0x80000
+; GFX12-TRUE16-NEXT:    s_bfe_i32 s5, s5, 0x80000
+; GFX12-TRUE16-NEXT:    s_pack_ll_b32_b16 s0, s13, s0
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s1, s1, 8
+; GFX12-TRUE16-NEXT:    s_ashr_i32 s13, s4, 24
+; GFX12-TRUE16-NEXT:    s_bfe_i32 s12, s12, 0x80000
+; GFX12-TRUE16-NEXT:    s_pack_ll_b32_b16 s1, s5, s1
+; GFX12-TRUE16-NEXT:    s_pack_ll_b32_b16 s5, s12, s13
+; GFX12-TRUE16-NEXT:    s_sext_i32_i16 s12, s4
+; GFX12-TRUE16-NEXT:    s_bfe_i32 s4, s4, 0x80000
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s12, s12, 8
+; GFX12-TRUE16-NEXT:    s_ashr_i32 s13, s7, 16
+; GFX12-TRUE16-NEXT:    s_pack_ll_b32_b16 s4, s4, s12
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s12, s13, 8
+; GFX12-TRUE16-NEXT:    s_sext_i32_i16 s13, s7
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s11, s7, 16
+; GFX12-TRUE16-NEXT:    s_bfe_i32 s7, s7, 0x80000
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s13, s13, 8
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s10, s6, 16
+; GFX12-TRUE16-NEXT:    s_bfe_i32 s11, s11, 0x80000
+; GFX12-TRUE16-NEXT:    s_pack_ll_b32_b16 s7, s7, s13
+; GFX12-TRUE16-NEXT:    s_sext_i32_i16 s13, s6
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s14, s2, 16
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s15, s3, 16
+; GFX12-TRUE16-NEXT:    s_ashr_i32 s24, s3, 16
+; GFX12-TRUE16-NEXT:    s_bfe_i32 s25, s3, 0x80000
+; GFX12-TRUE16-NEXT:    s_sext_i32_i16 s3, s3
+; GFX12-TRUE16-NEXT:    s_ashr_i32 s26, s2, 24
+; GFX12-TRUE16-NEXT:    s_bfe_i32 s27, s2, 0x80000
+; GFX12-TRUE16-NEXT:    s_sext_i32_i16 s2, s2
+; GFX12-TRUE16-NEXT:    s_pack_ll_b32_b16 s11, s11, s12
+; GFX12-TRUE16-NEXT:    s_ashr_i32 s12, s6, 24
+; GFX12-TRUE16-NEXT:    s_bfe_i32 s6, s6, 0x80000
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s13, s13, 8
+; GFX12-TRUE16-NEXT:    s_bfe_i32 s10, s10, 0x80000
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s24, s24, 8
+; GFX12-TRUE16-NEXT:    s_bfe_i32 s15, s15, 0x80000
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s3, s3, 8
+; GFX12-TRUE16-NEXT:    s_bfe_i32 s14, s14, 0x80000
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s2, s2, 8
+; GFX12-TRUE16-NEXT:    s_pack_ll_b32_b16 s6, s6, s13
+; GFX12-TRUE16-NEXT:    s_pack_ll_b32_b16 s10, s10, s12
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s18, s18, 8
+; GFX12-TRUE16-NEXT:    s_bfe_i32 s17, s17, 0x80000
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s20, s20, 8
+; GFX12-TRUE16-NEXT:    s_bfe_i32 s16, s16, 0x80000
+; GFX12-TRUE16-NEXT:    s_lshr_b32 s23, s23, 8
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v1, s10
+; GFX12-TRUE16-NEXT:    s_pack_ll_b32_b16 s15, s15, s24
+; GFX12-TRUE16-NEXT:    s_pack_ll_b32_b16 s3, s25, s3
+; GFX12-TRUE16-NEXT:    s_pack_ll_b32_b16 s14, s14, s26
+; GFX12-TRUE16-NEXT:    s_pack_ll_b32_b16 s2, s27, s2
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v3, s11
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v2, s7 :: v_dual_mov_b32 v5, s5
+; GFX12-TRUE16-NEXT:    s_pack_ll_b32_b16 s17, s17, s18
+; GFX12-TRUE16-NEXT:    s_pack_ll_b32_b16 s18, s19, s20
+; GFX12-TRUE16-NEXT:    s_pack_ll_b32_b16 s16, s16, s21
+; GFX12-TRUE16-NEXT:    s_pack_ll_b32_b16 s19, s22, s23
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s0
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v6, s1 :: v_dual_mov_b32 v9, s14
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v11, s15
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v10, s3 :: v_dual_mov_b32 v13, s16
+; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v12, s19 :: v_dual_mov_b32 v15, s17
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v14, s18
+; GFX12-TRUE16-NEXT:    s_clause 0x3
+; GFX12-TRUE16-NEXT:    global_store_b128 v16, v[0:3], s[8:9] offset:48
+; GFX12-TRUE16-NEXT:    global_store_b128 v16, v[4:7], s[8:9] offset:32
+; GFX12-TRUE16-NEXT:    global_store_b128 v16, v[8:11], s[8:9] offset:16
+; GFX12-TRUE16-NEXT:    global_store_b128 v16, v[12:15], s[8:9]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: constant_sextload_v32i8_to_v32i16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[8:11], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_load_b256 s[0:7], s[10:11], 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s13, s5, 16
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s16, s0, 16
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s17, s1, 16
+; GFX12-FAKE16-NEXT:    s_ashr_i32 s18, s1, 16
+; GFX12-FAKE16-NEXT:    s_bfe_i32 s19, s1, 0x80000
+; GFX12-FAKE16-NEXT:    s_sext_i32_i16 s20, s1
+; GFX12-FAKE16-NEXT:    s_ashr_i32 s21, s0, 24
+; GFX12-FAKE16-NEXT:    s_bfe_i32 s22, s0, 0x80000
+; GFX12-FAKE16-NEXT:    s_sext_i32_i16 s23, s0
+; GFX12-FAKE16-NEXT:    s_ashr_i64 s[0:1], s[4:5], 56
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s12, s4, 16
+; GFX12-FAKE16-NEXT:    s_bfe_i32 s1, s5, 0x80000
+; GFX12-FAKE16-NEXT:    s_sext_i32_i16 s5, s5
+; GFX12-FAKE16-NEXT:    s_bfe_i32 s13, s13, 0x80000
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s5, s5, 8
+; GFX12-FAKE16-NEXT:    s_pack_ll_b32_b16 s0, s13, s0
+; GFX12-FAKE16-NEXT:    s_ashr_i32 s13, s4, 24
+; GFX12-FAKE16-NEXT:    s_bfe_i32 s12, s12, 0x80000
+; GFX12-FAKE16-NEXT:    s_pack_ll_b32_b16 s1, s1, s5
+; GFX12-FAKE16-NEXT:    s_pack_ll_b32_b16 s5, s12, s13
+; GFX12-FAKE16-NEXT:    s_sext_i32_i16 s12, s4
+; GFX12-FAKE16-NEXT:    s_bfe_i32 s4, s4, 0x80000
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s12, s12, 8
+; GFX12-FAKE16-NEXT:    s_ashr_i32 s13, s7, 16
+; GFX12-FAKE16-NEXT:    s_pack_ll_b32_b16 s4, s4, s12
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s12, s13, 8
+; GFX12-FAKE16-NEXT:    s_sext_i32_i16 s13, s7
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s11, s7, 16
+; GFX12-FAKE16-NEXT:    s_bfe_i32 s7, s7, 0x80000
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s13, s13, 8
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s10, s6, 16
+; GFX12-FAKE16-NEXT:    s_bfe_i32 s11, s11, 0x80000
+; GFX12-FAKE16-NEXT:    s_pack_ll_b32_b16 s7, s7, s13
+; GFX12-FAKE16-NEXT:    s_sext_i32_i16 s13, s6
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s14, s2, 16
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s15, s3, 16
+; GFX12-FAKE16-NEXT:    s_ashr_i32 s24, s3, 16
+; GFX12-FAKE16-NEXT:    s_bfe_i32 s25, s3, 0x80000
+; GFX12-FAKE16-NEXT:    s_sext_i32_i16 s3, s3
+; GFX12-FAKE16-NEXT:    s_ashr_i32 s26, s2, 24
+; GFX12-FAKE16-NEXT:    s_bfe_i32 s27, s2, 0x80000
+; GFX12-FAKE16-NEXT:    s_sext_i32_i16 s2, s2
+; GFX12-FAKE16-NEXT:    s_pack_ll_b32_b16 s11, s11, s12
+; GFX12-FAKE16-NEXT:    s_ashr_i32 s12, s6, 24
+; GFX12-FAKE16-NEXT:    s_bfe_i32 s6, s6, 0x80000
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s13, s13, 8
+; GFX12-FAKE16-NEXT:    s_bfe_i32 s10, s10, 0x80000
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s24, s24, 8
+; GFX12-FAKE16-NEXT:    s_bfe_i32 s15, s15, 0x80000
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s3, s3, 8
+; GFX12-FAKE16-NEXT:    s_bfe_i32 s14, s14, 0x80000
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s2, s2, 8
+; GFX12-FAKE16-NEXT:    s_pack_ll_b32_b16 s6, s6, s13
+; GFX12-FAKE16-NEXT:    s_pack_ll_b32_b16 s10, s10, s12
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s18, s18, 8
+; GFX12-FAKE16-NEXT:    s_bfe_i32 s17, s17, 0x80000
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s20, s20, 8
+; GFX12-FAKE16-NEXT:    s_bfe_i32 s16, s16, 0x80000
+; GFX12-FAKE16-NEXT:    s_lshr_b32 s23, s23, 8
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v1, s10
+; GFX12-FAKE16-NEXT:    s_pack_ll_b32_b16 s15, s15, s24
+; GFX12-FAKE16-NEXT:    s_pack_ll_b32_b16 s3, s25, s3
+; GFX12-FAKE16-NEXT:    s_pack_ll_b32_b16 s14, s14, s26
+; GFX12-FAKE16-NEXT:    s_pack_ll_b32_b16 s2, s27, s2
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v3, s11
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v2, s7 :: v_dual_mov_b32 v5, s5
+; GFX12-FAKE16-NEXT:    s_pack_ll_b32_b16 s17, s17, s18
+; GFX12-FAKE16-NEXT:    s_pack_ll_b32_b16 s18, s19, s20
+; GFX12-FAKE16-NEXT:    s_pack_ll_b32_b16 s16, s16, s21
+; GFX12-FAKE16-NEXT:    s_pack_ll_b32_b16 s19, s22, s23
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s0
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v6, s1 :: v_dual_mov_b32 v9, s14
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v11, s15
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v10, s3 :: v_dual_mov_b32 v13, s16
+; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v12, s19 :: v_dual_mov_b32 v15, s17
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v14, s18
+; GFX12-FAKE16-NEXT:    s_clause 0x3
+; GFX12-FAKE16-NEXT:    global_store_b128 v16, v[0:3], s[8:9] offset:48
+; GFX12-FAKE16-NEXT:    global_store_b128 v16, v[4:7], s[8:9] offset:32
+; GFX12-FAKE16-NEXT:    global_store_b128 v16, v[8:11], s[8:9] offset:16
+; GFX12-FAKE16-NEXT:    global_store_b128 v16, v[12:15], s[8:9]
+; GFX12-FAKE16-NEXT:    s_endpgm
   %load = load <32 x i8>, ptr addrspace(4) %in
   %ext = sext <32 x i8> %load to <32 x i16>
   store <32 x i16> %ext, ptr addrspace(1) %out
diff --git a/llvm/test/CodeGen/AMDGPU/lower-kernargs.ll b/llvm/test/CodeGen/AMDGPU/lower-kernargs.ll
index 119beb958f1bd..e970027ca5d40 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-kernargs.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-kernargs.ll
@@ -17,7 +17,7 @@ define amdgpu_kernel void @kern_i8(i8 %arg) #0 {
 ; HSA-LABEL: @kern_i8(
 ; HSA-NEXT:    [[KERN_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I8_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1:![0-9]+]]
+; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0:![0-9]+]]
 ; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
 ; HSA-NEXT:    store i8 [[TMP2]], ptr addrspace(1) poison, align 1
 ; HSA-NEXT:    ret void
@@ -25,7 +25,7 @@ define amdgpu_kernel void @kern_i8(i8 %arg) #0 {
 ; MESA-LABEL: @kern_i8(
 ; MESA-NEXT:    [[KERN_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I8_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1:![0-9]+]]
+; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0:![0-9]+]]
 ; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
 ; MESA-NEXT:    store i8 [[TMP2]], ptr addrspace(1) poison, align 1
 ; MESA-NEXT:    ret void
@@ -38,7 +38,7 @@ define amdgpu_kernel void @kern_i16(i16 %arg) #0 {
 ; HSA-LABEL: @kern_i16(
 ; HSA-NEXT:    [[KERN_I16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I16_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
 ; HSA-NEXT:    store i16 [[TMP2]], ptr addrspace(1) poison, align 1
 ; HSA-NEXT:    ret void
@@ -46,7 +46,7 @@ define amdgpu_kernel void @kern_i16(i16 %arg) #0 {
 ; MESA-LABEL: @kern_i16(
 ; MESA-NEXT:    [[KERN_I16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I16_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
 ; MESA-NEXT:    store i16 [[TMP2]], ptr addrspace(1) poison, align 1
 ; MESA-NEXT:    ret void
@@ -59,7 +59,7 @@ define amdgpu_kernel void @kern_f16(half %arg) #0 {
 ; HSA-LABEL: @kern_f16(
 ; HSA-NEXT:    [[KERN_F16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_F16_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
 ; HSA-NEXT:    [[ARG_LOAD:%.*]] = bitcast i16 [[TMP2]] to half
 ; HSA-NEXT:    store half [[ARG_LOAD]], ptr addrspace(1) poison, align 1
@@ -68,7 +68,7 @@ define amdgpu_kernel void @kern_f16(half %arg) #0 {
 ; MESA-LABEL: @kern_f16(
 ; MESA-NEXT:    [[KERN_F16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_F16_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
 ; MESA-NEXT:    [[ARG_LOAD:%.*]] = bitcast i16 [[TMP2]] to half
 ; MESA-NEXT:    store half [[ARG_LOAD]], ptr addrspace(1) poison, align 1
@@ -82,7 +82,7 @@ define amdgpu_kernel void @kern_zeroext_i8(i8 zeroext %arg) #0 {
 ; HSA-LABEL: @kern_zeroext_i8(
 ; HSA-NEXT:    [[KERN_ZEROEXT_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_ZEROEXT_I8_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
 ; HSA-NEXT:    store i8 [[TMP2]], ptr addrspace(1) poison, align 1
 ; HSA-NEXT:    ret void
@@ -90,7 +90,7 @@ define amdgpu_kernel void @kern_zeroext_i8(i8 zeroext %arg) #0 {
 ; MESA-LABEL: @kern_zeroext_i8(
 ; MESA-NEXT:    [[KERN_ZEROEXT_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_ZEROEXT_I8_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
 ; MESA-NEXT:    store i8 [[TMP2]], ptr addrspace(1) poison, align 1
 ; MESA-NEXT:    ret void
@@ -103,7 +103,7 @@ define amdgpu_kernel void @kern_zeroext_i16(i16 zeroext %arg) #0 {
 ; HSA-LABEL: @kern_zeroext_i16(
 ; HSA-NEXT:    [[KERN_ZEROEXT_I16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_ZEROEXT_I16_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
 ; HSA-NEXT:    store i16 [[TMP2]], ptr addrspace(1) poison, align 1
 ; HSA-NEXT:    ret void
@@ -111,7 +111,7 @@ define amdgpu_kernel void @kern_zeroext_i16(i16 zeroext %arg) #0 {
 ; MESA-LABEL: @kern_zeroext_i16(
 ; MESA-NEXT:    [[KERN_ZEROEXT_I16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_ZEROEXT_I16_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
 ; MESA-NEXT:    store i16 [[TMP2]], ptr addrspace(1) poison, align 1
 ; MESA-NEXT:    ret void
@@ -124,7 +124,7 @@ define amdgpu_kernel void @kern_signext_i8(i8 signext %arg) #0 {
 ; HSA-LABEL: @kern_signext_i8(
 ; HSA-NEXT:    [[KERN_SIGNEXT_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_SIGNEXT_I8_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
 ; HSA-NEXT:    store i8 [[TMP2]], ptr addrspace(1) poison, align 1
 ; HSA-NEXT:    ret void
@@ -132,7 +132,7 @@ define amdgpu_kernel void @kern_signext_i8(i8 signext %arg) #0 {
 ; MESA-LABEL: @kern_signext_i8(
 ; MESA-NEXT:    [[KERN_SIGNEXT_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_SIGNEXT_I8_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
 ; MESA-NEXT:    store i8 [[TMP2]], ptr addrspace(1) poison, align 1
 ; MESA-NEXT:    ret void
@@ -145,7 +145,7 @@ define amdgpu_kernel void @kern_signext_i16(i16 signext %arg) #0 {
 ; HSA-LABEL: @kern_signext_i16(
 ; HSA-NEXT:    [[KERN_SIGNEXT_I16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_SIGNEXT_I16_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
 ; HSA-NEXT:    store i16 [[TMP2]], ptr addrspace(1) poison, align 1
 ; HSA-NEXT:    ret void
@@ -153,7 +153,7 @@ define amdgpu_kernel void @kern_signext_i16(i16 signext %arg) #0 {
 ; MESA-LABEL: @kern_signext_i16(
 ; MESA-NEXT:    [[KERN_SIGNEXT_I16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_SIGNEXT_I16_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
 ; MESA-NEXT:    store i16 [[TMP2]], ptr addrspace(1) poison, align 1
 ; MESA-NEXT:    ret void
@@ -166,10 +166,10 @@ define amdgpu_kernel void @kern_i8_i8(i8 %arg0, i8 %arg1) {
 ; HSA-LABEL: @kern_i8_i8(
 ; HSA-NEXT:    [[KERN_I8_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I8_I8_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
 ; HSA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I8_I8_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
 ; HSA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
 ; HSA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1
@@ -179,10 +179,10 @@ define amdgpu_kernel void @kern_i8_i8(i8 %arg0, i8 %arg1) {
 ; MESA-LABEL: @kern_i8_i8(
 ; MESA-NEXT:    [[KERN_I8_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I8_I8_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
 ; MESA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I8_I8_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
 ; MESA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
 ; MESA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1
@@ -198,7 +198,7 @@ define amdgpu_kernel void @kern_v3i8(<3 x i8> %arg) {
 ; HSA-LABEL: @kern_v3i8(
 ; HSA-NEXT:    [[KERN_V3I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_V3I8_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i24
 ; HSA-NEXT:    [[ARG_LOAD:%.*]] = bitcast i24 [[TMP2]] to <3 x i8>
 ; HSA-NEXT:    store <3 x i8> [[ARG_LOAD]], ptr addrspace(1) poison, align 4
@@ -207,7 +207,7 @@ define amdgpu_kernel void @kern_v3i8(<3 x i8> %arg) {
 ; MESA-LABEL: @kern_v3i8(
 ; MESA-NEXT:    [[KERN_V3I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_V3I8_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i24
 ; MESA-NEXT:    [[ARG_LOAD:%.*]] = bitcast i24 [[TMP2]] to <3 x i8>
 ; MESA-NEXT:    store <3 x i8> [[ARG_LOAD]], ptr addrspace(1) poison, align 4
@@ -221,7 +221,7 @@ define amdgpu_kernel void @kern_i24(i24 %arg0) {
 ; HSA-LABEL: @kern_i24(
 ; HSA-NEXT:    [[KERN_I24_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I24_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i24
 ; HSA-NEXT:    store i24 [[TMP2]], ptr addrspace(1) poison, align 4
 ; HSA-NEXT:    ret void
@@ -229,7 +229,7 @@ define amdgpu_kernel void @kern_i24(i24 %arg0) {
 ; MESA-LABEL: @kern_i24(
 ; MESA-NEXT:    [[KERN_I24_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I24_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i24
 ; MESA-NEXT:    store i24 [[TMP2]], ptr addrspace(1) poison, align 4
 ; MESA-NEXT:    ret void
@@ -242,14 +242,14 @@ define amdgpu_kernel void @kern_i32(i32 %arg0) {
 ; HSA-LABEL: @kern_i32(
 ; HSA-NEXT:    [[KERN_I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I32_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    store i32 [[ARG0_LOAD]], ptr addrspace(1) poison, align 4
 ; HSA-NEXT:    ret void
 ;
 ; MESA-LABEL: @kern_i32(
 ; MESA-NEXT:    [[KERN_I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I32_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    store i32 [[ARG0_LOAD]], ptr addrspace(1) poison, align 4
 ; MESA-NEXT:    ret void
 ;
@@ -261,14 +261,14 @@ define amdgpu_kernel void @kern_range_noundef_i32(i32 noundef range(i32 0, 8) %a
 ; HSA-LABEL: @kern_range_noundef_i32(
 ; HSA-NEXT:    [[KERN_RANGE_NOUNDEF_I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_RANGE_NOUNDEF_I32_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !range [[RNG2:![0-9]+]], !invariant.load [[META1]], !noundef [[META1]]
+; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !range [[RNG1:![0-9]+]], !invariant.load [[META0]], !noundef [[META0]]
 ; HSA-NEXT:    call void (...) @llvm.fake.use(i32 [[ARG0_LOAD]])
 ; HSA-NEXT:    ret void
 ;
 ; MESA-LABEL: @kern_range_noundef_i32(
 ; MESA-NEXT:    [[KERN_RANGE_NOUNDEF_I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_RANGE_NOUNDEF_I32_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !range [[RNG2:![0-9]+]], !invariant.load [[META1]], !noundef [[META1]]
+; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !range [[RNG1:![0-9]+]], !invariant.load [[META0]], !noundef [[META0]]
 ; MESA-NEXT:    call void (...) @llvm.fake.use(i32 [[ARG0_LOAD]])
 ; MESA-NEXT:    ret void
 ;
@@ -280,14 +280,14 @@ define amdgpu_kernel void @kern_f32(float %arg0) {
 ; HSA-LABEL: @kern_f32(
 ; HSA-NEXT:    [[KERN_F32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_F32_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load float, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load float, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    store float [[ARG0_LOAD]], ptr addrspace(1) poison, align 4
 ; HSA-NEXT:    ret void
 ;
 ; MESA-LABEL: @kern_f32(
 ; MESA-NEXT:    [[KERN_F32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_F32_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load float, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load float, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    store float [[ARG0_LOAD]], ptr addrspace(1) poison, align 4
 ; MESA-NEXT:    ret void
 ;
@@ -299,7 +299,7 @@ define amdgpu_kernel void @kern_v3i32(<3 x i32> %arg0) {
 ; HSA-LABEL: @kern_v3i32(
 ; HSA-NEXT:    [[KERN_V3I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_V3I32_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP1:%.*]] = load <4 x i32>, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP1:%.*]] = load <4 x i32>, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[ARG0_LOAD:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>
 ; HSA-NEXT:    store <3 x i32> [[ARG0_LOAD]], ptr addrspace(1) poison, align 4
 ; HSA-NEXT:    ret void
@@ -307,7 +307,7 @@ define amdgpu_kernel void @kern_v3i32(<3 x i32> %arg0) {
 ; MESA-LABEL: @kern_v3i32(
 ; MESA-NEXT:    [[KERN_V3I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_V3I32_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP1:%.*]] = load <4 x i32>, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP1:%.*]] = load <4 x i32>, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[ARG0_LOAD:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>
 ; MESA-NEXT:    store <3 x i32> [[ARG0_LOAD]], ptr addrspace(1) poison, align 4
 ; MESA-NEXT:    ret void
@@ -320,14 +320,14 @@ define amdgpu_kernel void @kern_v8i32(<8 x i32> %arg) #0 {
 ; HSA-LABEL: @kern_v8i32(
 ; HSA-NEXT:    [[KERN_V8I32_KERNARG_SEGMENT:%.*]] = call nonnull align 32 dereferenceable(288) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_V8I32_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[ARG_LOAD:%.*]] = load <8 x i32>, ptr addrspace(4) [[ARG_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[ARG_LOAD:%.*]] = load <8 x i32>, ptr addrspace(4) [[ARG_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    store <8 x i32> [[ARG_LOAD]], ptr addrspace(1) poison, align 32
 ; HSA-NEXT:    ret void
 ;
 ; MESA-LABEL: @kern_v8i32(
 ; MESA-NEXT:    [[KERN_V8I32_KERNARG_SEGMENT:%.*]] = call nonnull align 32 dereferenceable(288) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_V8I32_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[ARG_LOAD:%.*]] = load <8 x i32>, ptr addrspace(4) [[ARG_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[ARG_LOAD:%.*]] = load <8 x i32>, ptr addrspace(4) [[ARG_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    store <8 x i32> [[ARG_LOAD]], ptr addrspace(1) poison, align 32
 ; MESA-NEXT:    ret void
 ;
@@ -339,14 +339,14 @@ define amdgpu_kernel void @kern_v8i64(<8 x i64> %arg) #0 {
 ; HSA-LABEL: @kern_v8i64(
 ; HSA-NEXT:    [[KERN_V8I64_KERNARG_SEGMENT:%.*]] = call nonnull align 64 dereferenceable(320) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_V8I64_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[ARG_LOAD:%.*]] = load <8 x i64>, ptr addrspace(4) [[ARG_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[ARG_LOAD:%.*]] = load <8 x i64>, ptr addrspace(4) [[ARG_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    store <8 x i64> [[ARG_LOAD]], ptr addrspace(1) poison, align 64
 ; HSA-NEXT:    ret void
 ;
 ; MESA-LABEL: @kern_v8i64(
 ; MESA-NEXT:    [[KERN_V8I64_KERNARG_SEGMENT:%.*]] = call nonnull align 64 dereferenceable(320) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_V8I64_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[ARG_LOAD:%.*]] = load <8 x i64>, ptr addrspace(4) [[ARG_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[ARG_LOAD:%.*]] = load <8 x i64>, ptr addrspace(4) [[ARG_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    store <8 x i64> [[ARG_LOAD]], ptr addrspace(1) poison, align 64
 ; MESA-NEXT:    ret void
 ;
@@ -358,14 +358,14 @@ define amdgpu_kernel void @kern_v16i64(<16 x i64> %arg) #0 {
 ; HSA-LABEL: @kern_v16i64(
 ; HSA-NEXT:    [[KERN_V16I64_KERNARG_SEGMENT:%.*]] = call nonnull align 128 dereferenceable(384) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_V16I64_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[ARG_LOAD:%.*]] = load <16 x i64>, ptr addrspace(4) [[ARG_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[ARG_LOAD:%.*]] = load <16 x i64>, ptr addrspace(4) [[ARG_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    store <16 x i64> [[ARG_LOAD]], ptr addrspace(1) poison, align 128
 ; HSA-NEXT:    ret void
 ;
 ; MESA-LABEL: @kern_v16i64(
 ; MESA-NEXT:    [[KERN_V16I64_KERNARG_SEGMENT:%.*]] = call nonnull align 128 dereferenceable(384) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_V16I64_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[ARG_LOAD:%.*]] = load <16 x i64>, ptr addrspace(4) [[ARG_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[ARG_LOAD:%.*]] = load <16 x i64>, ptr addrspace(4) [[ARG_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    store <16 x i64> [[ARG_LOAD]], ptr addrspace(1) poison, align 128
 ; MESA-NEXT:    ret void
 ;
@@ -377,9 +377,9 @@ define amdgpu_kernel void @kern_i32_v3i32(i32 %arg0, <3 x i32> %arg1) {
 ; HSA-LABEL: @kern_i32_v3i32(
 ; HSA-NEXT:    [[KERN_I32_V3I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(288) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I32_V3I32_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[ARG1_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I32_V3I32_KERNARG_SEGMENT]], i64 16
-; HSA-NEXT:    [[TMP1:%.*]] = load <4 x i32>, ptr addrspace(4) [[ARG1_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP1:%.*]] = load <4 x i32>, ptr addrspace(4) [[ARG1_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[ARG1_LOAD:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>
 ; HSA-NEXT:    store i32 [[ARG0_LOAD]], ptr addrspace(1) poison, align 4
 ; HSA-NEXT:    store <3 x i32> [[ARG1_LOAD]], ptr addrspace(1) poison, align 4
@@ -388,9 +388,9 @@ define amdgpu_kernel void @kern_i32_v3i32(i32 %arg0, <3 x i32> %arg1) {
 ; MESA-LABEL: @kern_i32_v3i32(
 ; MESA-NEXT:    [[KERN_I32_V3I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(288) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I32_V3I32_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[ARG1_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I32_V3I32_KERNARG_SEGMENT]], i64 52
-; MESA-NEXT:    [[TMP1:%.*]] = load <4 x i32>, ptr addrspace(4) [[ARG1_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP1:%.*]] = load <4 x i32>, ptr addrspace(4) [[ARG1_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[ARG1_LOAD:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>
 ; MESA-NEXT:    store i32 [[ARG0_LOAD]], ptr addrspace(1) poison, align 4
 ; MESA-NEXT:    store <3 x i32> [[ARG1_LOAD]], ptr addrspace(1) poison, align 4
@@ -408,14 +408,14 @@ define amdgpu_kernel void @kern_struct_a(%struct.a %arg0) {
 ; HSA-LABEL: @kern_struct_a(
 ; HSA-NEXT:    [[KERN_STRUCT_A_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_STRUCT_A_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load [[STRUCT_A:%.*]], ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load [[STRUCT_A:%.*]], ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    store [[STRUCT_A]] [[ARG0_LOAD]], ptr addrspace(1) poison, align 4
 ; HSA-NEXT:    ret void
 ;
 ; MESA-LABEL: @kern_struct_a(
 ; MESA-NEXT:    [[KERN_STRUCT_A_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(268) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_STRUCT_A_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load [[STRUCT_A:%.*]], ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load [[STRUCT_A:%.*]], ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    store [[STRUCT_A]] [[ARG0_LOAD]], ptr addrspace(1) poison, align 4
 ; MESA-NEXT:    ret void
 ;
@@ -427,14 +427,14 @@ define amdgpu_kernel void @kern_struct_b_packed(%struct.b.packed %arg0) #0 {
 ; HSA-LABEL: @kern_struct_b_packed(
 ; HSA-NEXT:    [[KERN_STRUCT_B_PACKED_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(288) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_STRUCT_B_PACKED_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load [[STRUCT_B_PACKED:%.*]], ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load [[STRUCT_B_PACKED:%.*]], ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    store [[STRUCT_B_PACKED]] [[ARG0_LOAD]], ptr addrspace(1) poison, align 16
 ; HSA-NEXT:    ret void
 ;
 ; MESA-LABEL: @kern_struct_b_packed(
 ; MESA-NEXT:    [[KERN_STRUCT_B_PACKED_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(288) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_STRUCT_B_PACKED_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load [[STRUCT_B_PACKED:%.*]], ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load [[STRUCT_B_PACKED:%.*]], ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    store [[STRUCT_B_PACKED]] [[ARG0_LOAD]], ptr addrspace(1) poison, align 16
 ; MESA-NEXT:    ret void
 ;
@@ -446,14 +446,14 @@ define amdgpu_kernel void @kern_implicit_arg_num_bytes(i32 %arg0) #1 {
 ; HSA-LABEL: @kern_implicit_arg_num_bytes(
 ; HSA-NEXT:    [[KERN_IMPLICIT_ARG_NUM_BYTES_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(48) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_IMPLICIT_ARG_NUM_BYTES_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    store i32 [[ARG0_LOAD]], ptr addrspace(1) poison, align 4
 ; HSA-NEXT:    ret void
 ;
 ; MESA-LABEL: @kern_implicit_arg_num_bytes(
 ; MESA-NEXT:    [[KERN_IMPLICIT_ARG_NUM_BYTES_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(44) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_IMPLICIT_ARG_NUM_BYTES_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    store i32 [[ARG0_LOAD]], ptr addrspace(1) poison, align 4
 ; MESA-NEXT:    ret void
 ;
@@ -465,14 +465,14 @@ define amdgpu_kernel void @kernel_implicitarg_no_struct_align(<16 x i32>, i32 %a
 ; HSA-LABEL: @kernel_implicitarg_no_struct_align(
 ; HSA-NEXT:    [[KERNEL_IMPLICITARG_NO_STRUCT_ALIGN_KERNARG_SEGMENT:%.*]] = call nonnull align 64 dereferenceable(112) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG1_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERNEL_IMPLICITARG_NO_STRUCT_ALIGN_KERNARG_SEGMENT]], i64 64
-; HSA-NEXT:    [[ARG1_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[ARG1_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    store i32 [[ARG1_LOAD]], ptr addrspace(1) poison, align 4
 ; HSA-NEXT:    ret void
 ;
 ; MESA-LABEL: @kernel_implicitarg_no_struct_align(
 ; MESA-NEXT:    [[KERNEL_IMPLICITARG_NO_STRUCT_ALIGN_KERNARG_SEGMENT:%.*]] = call nonnull align 64 dereferenceable(108) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG1_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERNEL_IMPLICITARG_NO_STRUCT_ALIGN_KERNARG_SEGMENT]], i64 100
-; MESA-NEXT:    [[ARG1_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[ARG1_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    store i32 [[ARG1_LOAD]], ptr addrspace(1) poison, align 4
 ; MESA-NEXT:    ret void
 ;
@@ -484,14 +484,14 @@ define amdgpu_kernel void @kern_lds_ptr(ptr addrspace(3) %lds) #0 {
 ; HSA-LABEL: @kern_lds_ptr(
 ; HSA-NEXT:    [[KERN_LDS_PTR_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[LDS_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_LDS_PTR_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[LDS_LOAD:%.*]] = load ptr addrspace(3), ptr addrspace(4) [[LDS_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[LDS_LOAD:%.*]] = load ptr addrspace(3), ptr addrspace(4) [[LDS_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    store i32 0, ptr addrspace(3) [[LDS_LOAD]], align 4
 ; HSA-NEXT:    ret void
 ;
 ; MESA-LABEL: @kern_lds_ptr(
 ; MESA-NEXT:    [[KERN_LDS_PTR_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[LDS_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_LDS_PTR_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[LDS_LOAD:%.*]] = load ptr addrspace(3), ptr addrspace(4) [[LDS_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[LDS_LOAD:%.*]] = load ptr addrspace(3), ptr addrspace(4) [[LDS_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    store i32 0, ptr addrspace(3) [[LDS_LOAD]], align 4
 ; MESA-NEXT:    ret void
 ;
@@ -513,10 +513,10 @@ define amdgpu_kernel void @kern_realign_i8_i8(i8 %arg0, i8 %arg1) #0 {
 ; HSA-LABEL: @kern_realign_i8_i8(
 ; HSA-NEXT:    [[KERN_REALIGN_I8_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
 ; HSA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
 ; HSA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
 ; HSA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1
@@ -526,10 +526,10 @@ define amdgpu_kernel void @kern_realign_i8_i8(i8 %arg0, i8 %arg1) #0 {
 ; MESA-LABEL: @kern_realign_i8_i8(
 ; MESA-NEXT:    [[KERN_REALIGN_I8_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
 ; MESA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
 ; MESA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
 ; MESA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1
@@ -545,14 +545,14 @@ define amdgpu_kernel void @kern_realign_i8_i8_i8(i8 %arg0, i8 %arg1, i8 %arg2) #
 ; HSA-LABEL: @kern_realign_i8_i8_i8(
 ; HSA-NEXT:    [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
 ; HSA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
 ; HSA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
 ; HSA-NEXT:    [[ARG2_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP7:%.*]] = lshr i32 [[TMP6]], 16
 ; HSA-NEXT:    [[TMP8:%.*]] = trunc i32 [[TMP7]] to i8
 ; HSA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1
@@ -563,14 +563,14 @@ define amdgpu_kernel void @kern_realign_i8_i8_i8(i8 %arg0, i8 %arg1, i8 %arg2) #
 ; MESA-LABEL: @kern_realign_i8_i8_i8(
 ; MESA-NEXT:    [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
 ; MESA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
 ; MESA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
 ; MESA-NEXT:    [[ARG2_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP7:%.*]] = lshr i32 [[TMP6]], 16
 ; MESA-NEXT:    [[TMP8:%.*]] = trunc i32 [[TMP7]] to i8
 ; MESA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1
@@ -588,18 +588,18 @@ define amdgpu_kernel void @kern_realign_i8_i8_i8_i8(i8 %arg0, i8 %arg1, i8 %arg2
 ; HSA-LABEL: @kern_realign_i8_i8_i8_i8(
 ; HSA-NEXT:    [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
 ; HSA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
 ; HSA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
 ; HSA-NEXT:    [[ARG2_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP7:%.*]] = lshr i32 [[TMP6]], 16
 ; HSA-NEXT:    [[TMP8:%.*]] = trunc i32 [[TMP7]] to i8
 ; HSA-NEXT:    [[ARG3_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP9:%.*]] = load i32, ptr addrspace(4) [[ARG3_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP9:%.*]] = load i32, ptr addrspace(4) [[ARG3_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP10:%.*]] = lshr i32 [[TMP9]], 24
 ; HSA-NEXT:    [[TMP11:%.*]] = trunc i32 [[TMP10]] to i8
 ; HSA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1
@@ -611,18 +611,18 @@ define amdgpu_kernel void @kern_realign_i8_i8_i8_i8(i8 %arg0, i8 %arg1, i8 %arg2
 ; MESA-LABEL: @kern_realign_i8_i8_i8_i8(
 ; MESA-NEXT:    [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
 ; MESA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
 ; MESA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
 ; MESA-NEXT:    [[ARG2_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP7:%.*]] = lshr i32 [[TMP6]], 16
 ; MESA-NEXT:    [[TMP8:%.*]] = trunc i32 [[TMP7]] to i8
 ; MESA-NEXT:    [[ARG3_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP9:%.*]] = load i32, ptr addrspace(4) [[ARG3_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP9:%.*]] = load i32, ptr addrspace(4) [[ARG3_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP10:%.*]] = lshr i32 [[TMP9]], 24
 ; MESA-NEXT:    [[TMP11:%.*]] = trunc i32 [[TMP10]] to i8
 ; MESA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1
@@ -642,10 +642,10 @@ define amdgpu_kernel void @kern_realign_i8_v3i8(i8 %arg0, <3 x i8> %arg1) #0 {
 ; HSA-LABEL: @kern_realign_i8_v3i8(
 ; HSA-NEXT:    [[KERN_REALIGN_I8_V3I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_V3I8_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
 ; HSA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_V3I8_KERNARG_SEGMENT]], i64 4
-; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP4:%.*]] = trunc i32 [[TMP3]] to i24
 ; HSA-NEXT:    [[ARG1_LOAD:%.*]] = bitcast i24 [[TMP4]] to <3 x i8>
 ; HSA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1
@@ -655,10 +655,10 @@ define amdgpu_kernel void @kern_realign_i8_v3i8(i8 %arg0, <3 x i8> %arg1) #0 {
 ; MESA-LABEL: @kern_realign_i8_v3i8(
 ; MESA-NEXT:    [[KERN_REALIGN_I8_V3I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_V3I8_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
 ; MESA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_V3I8_KERNARG_SEGMENT]], i64 40
-; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 8, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 8, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP4:%.*]] = trunc i32 [[TMP3]] to i24
 ; MESA-NEXT:    [[ARG1_LOAD:%.*]] = bitcast i24 [[TMP4]] to <3 x i8>
 ; MESA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1
@@ -674,10 +674,10 @@ define amdgpu_kernel void @kern_realign_i8_i16(i8 %arg0, i16 %arg1) #0 {
 ; HSA-LABEL: @kern_realign_i8_i16(
 ; HSA-NEXT:    [[KERN_REALIGN_I8_I16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I16_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
 ; HSA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I16_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 16
 ; HSA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16
 ; HSA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1
@@ -687,10 +687,10 @@ define amdgpu_kernel void @kern_realign_i8_i16(i8 %arg0, i16 %arg1) #0 {
 ; MESA-LABEL: @kern_realign_i8_i16(
 ; MESA-NEXT:    [[KERN_REALIGN_I8_I16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I16_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
 ; MESA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I16_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 16
 ; MESA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16
 ; MESA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1
@@ -706,10 +706,10 @@ define amdgpu_kernel void @kern_realign_i1_i1(i1 %arg0, i1 %arg1) #0 {
 ; HSA-LABEL: @kern_realign_i1_i1(
 ; HSA-NEXT:    [[KERN_REALIGN_I1_I1_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1
 ; HSA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
 ; HSA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i1
 ; HSA-NEXT:    store volatile i1 [[TMP2]], ptr addrspace(1) poison, align 1
@@ -719,10 +719,10 @@ define amdgpu_kernel void @kern_realign_i1_i1(i1 %arg0, i1 %arg1) #0 {
 ; MESA-LABEL: @kern_realign_i1_i1(
 ; MESA-NEXT:    [[KERN_REALIGN_I1_I1_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1
 ; MESA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
 ; MESA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i1
 ; MESA-NEXT:    store volatile i1 [[TMP2]], ptr addrspace(1) poison, align 1
@@ -738,14 +738,14 @@ define amdgpu_kernel void @kern_realign_i1_i1_i1(i1 %arg0, i1 %arg1, i1 %arg2) #
 ; HSA-LABEL: @kern_realign_i1_i1_i1(
 ; HSA-NEXT:    [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1
 ; HSA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
 ; HSA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i1
 ; HSA-NEXT:    [[ARG2_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP7:%.*]] = lshr i32 [[TMP6]], 16
 ; HSA-NEXT:    [[TMP8:%.*]] = trunc i32 [[TMP7]] to i1
 ; HSA-NEXT:    store volatile i1 [[TMP2]], ptr addrspace(1) poison, align 1
@@ -756,14 +756,14 @@ define amdgpu_kernel void @kern_realign_i1_i1_i1(i1 %arg0, i1 %arg1, i1 %arg2) #
 ; MESA-LABEL: @kern_realign_i1_i1_i1(
 ; MESA-NEXT:    [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1
 ; MESA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
 ; MESA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i1
 ; MESA-NEXT:    [[ARG2_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP7:%.*]] = lshr i32 [[TMP6]], 16
 ; MESA-NEXT:    [[TMP8:%.*]] = trunc i32 [[TMP7]] to i1
 ; MESA-NEXT:    store volatile i1 [[TMP2]], ptr addrspace(1) poison, align 1
@@ -781,18 +781,18 @@ define amdgpu_kernel void @kern_realign_i1_i1_i1_i1(i1 %arg0, i1 %arg1, i1 %arg2
 ; HSA-LABEL: @kern_realign_i1_i1_i1_i1(
 ; HSA-NEXT:    [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1
 ; HSA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
 ; HSA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i1
 ; HSA-NEXT:    [[ARG2_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP7:%.*]] = lshr i32 [[TMP6]], 16
 ; HSA-NEXT:    [[TMP8:%.*]] = trunc i32 [[TMP7]] to i1
 ; HSA-NEXT:    [[ARG3_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP9:%.*]] = load i32, ptr addrspace(4) [[ARG3_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP9:%.*]] = load i32, ptr addrspace(4) [[ARG3_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP10:%.*]] = lshr i32 [[TMP9]], 24
 ; HSA-NEXT:    [[TMP11:%.*]] = trunc i32 [[TMP10]] to i1
 ; HSA-NEXT:    store volatile i1 [[TMP2]], ptr addrspace(1) poison, align 1
@@ -804,18 +804,18 @@ define amdgpu_kernel void @kern_realign_i1_i1_i1_i1(i1 %arg0, i1 %arg1, i1 %arg2
 ; MESA-LABEL: @kern_realign_i1_i1_i1_i1(
 ; MESA-NEXT:    [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1
 ; MESA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
 ; MESA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i1
 ; MESA-NEXT:    [[ARG2_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP7:%.*]] = lshr i32 [[TMP6]], 16
 ; MESA-NEXT:    [[TMP8:%.*]] = trunc i32 [[TMP7]] to i1
 ; MESA-NEXT:    [[ARG3_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP9:%.*]] = load i32, ptr addrspace(4) [[ARG3_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP9:%.*]] = load i32, ptr addrspace(4) [[ARG3_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP10:%.*]] = lshr i32 [[TMP9]], 24
 ; MESA-NEXT:    [[TMP11:%.*]] = trunc i32 [[TMP10]] to i1
 ; MESA-NEXT:    store volatile i1 [[TMP2]], ptr addrspace(1) poison, align 1
@@ -835,10 +835,10 @@ define amdgpu_kernel void @kern_realign_i1_v3i1(i1 %arg0, <3 x i1> %arg1) #0 {
 ; HSA-LABEL: @kern_realign_i1_v3i1(
 ; HSA-NEXT:    [[KERN_REALIGN_I1_V3I1_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_V3I1_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1
 ; HSA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_V3I1_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
 ; HSA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i3
 ; HSA-NEXT:    [[ARG1_LOAD:%.*]] = bitcast i3 [[TMP5]] to <3 x i1>
@@ -849,10 +849,10 @@ define amdgpu_kernel void @kern_realign_i1_v3i1(i1 %arg0, <3 x i1> %arg1) #0 {
 ; MESA-LABEL: @kern_realign_i1_v3i1(
 ; MESA-NEXT:    [[KERN_REALIGN_I1_V3I1_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_V3I1_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1
 ; MESA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_V3I1_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
 ; MESA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i3
 ; MESA-NEXT:    [[ARG1_LOAD:%.*]] = bitcast i3 [[TMP5]] to <3 x i1>
@@ -869,10 +869,10 @@ define amdgpu_kernel void @kern_realign_i1_i16(i1 %arg0, i16 %arg1) #0 {
 ; HSA-LABEL: @kern_realign_i1_i16(
 ; HSA-NEXT:    [[KERN_REALIGN_I1_I16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I16_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1
 ; HSA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I16_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 16
 ; HSA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16
 ; HSA-NEXT:    store volatile i1 [[TMP2]], ptr addrspace(1) poison, align 1
@@ -882,10 +882,10 @@ define amdgpu_kernel void @kern_realign_i1_i16(i1 %arg0, i16 %arg1) #0 {
 ; MESA-LABEL: @kern_realign_i1_i16(
 ; MESA-NEXT:    [[KERN_REALIGN_I1_I16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I16_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1
 ; MESA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I16_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 16
 ; MESA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16
 ; MESA-NEXT:    store volatile i1 [[TMP2]], ptr addrspace(1) poison, align 1
@@ -901,30 +901,30 @@ define amdgpu_kernel void @kern_realign_i8_i8_i8_i8_i8_i8_i8_i8(i8 %arg0, i8 %ar
 ; HSA-LABEL: @kern_realign_i8_i8_i8_i8_i8_i8_i8_i8(
 ; HSA-NEXT:    [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
 ; HSA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
 ; HSA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
 ; HSA-NEXT:    [[ARG2_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP7:%.*]] = lshr i32 [[TMP6]], 16
 ; HSA-NEXT:    [[TMP8:%.*]] = trunc i32 [[TMP7]] to i8
 ; HSA-NEXT:    [[ARG3_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP9:%.*]] = load i32, ptr addrspace(4) [[ARG3_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP9:%.*]] = load i32, ptr addrspace(4) [[ARG3_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP10:%.*]] = lshr i32 [[TMP9]], 24
 ; HSA-NEXT:    [[TMP11:%.*]] = trunc i32 [[TMP10]] to i8
 ; HSA-NEXT:    [[ARG5_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 4
-; HSA-NEXT:    [[TMP12:%.*]] = load i32, ptr addrspace(4) [[ARG5_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP12:%.*]] = load i32, ptr addrspace(4) [[ARG5_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP13:%.*]] = lshr i32 [[TMP12]], 8
 ; HSA-NEXT:    [[TMP14:%.*]] = trunc i32 [[TMP13]] to i8
 ; HSA-NEXT:    [[ARG6_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 4
-; HSA-NEXT:    [[TMP15:%.*]] = load i32, ptr addrspace(4) [[ARG6_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP15:%.*]] = load i32, ptr addrspace(4) [[ARG6_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP16:%.*]] = lshr i32 [[TMP15]], 16
 ; HSA-NEXT:    [[TMP17:%.*]] = trunc i32 [[TMP16]] to i8
 ; HSA-NEXT:    [[ARG7_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 4
-; HSA-NEXT:    [[TMP18:%.*]] = load i32, ptr addrspace(4) [[ARG7_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP18:%.*]] = load i32, ptr addrspace(4) [[ARG7_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP19:%.*]] = lshr i32 [[TMP18]], 24
 ; HSA-NEXT:    [[TMP20:%.*]] = trunc i32 [[TMP19]] to i8
 ; HSA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1
@@ -939,30 +939,30 @@ define amdgpu_kernel void @kern_realign_i8_i8_i8_i8_i8_i8_i8_i8(i8 %arg0, i8 %ar
 ; MESA-LABEL: @kern_realign_i8_i8_i8_i8_i8_i8_i8_i8(
 ; MESA-NEXT:    [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
 ; MESA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
 ; MESA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
 ; MESA-NEXT:    [[ARG2_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP7:%.*]] = lshr i32 [[TMP6]], 16
 ; MESA-NEXT:    [[TMP8:%.*]] = trunc i32 [[TMP7]] to i8
 ; MESA-NEXT:    [[ARG3_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP9:%.*]] = load i32, ptr addrspace(4) [[ARG3_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP9:%.*]] = load i32, ptr addrspace(4) [[ARG3_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP10:%.*]] = lshr i32 [[TMP9]], 24
 ; MESA-NEXT:    [[TMP11:%.*]] = trunc i32 [[TMP10]] to i8
 ; MESA-NEXT:    [[ARG5_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 40
-; MESA-NEXT:    [[TMP12:%.*]] = load i32, ptr addrspace(4) [[ARG5_KERNARG_OFFSET_ALIGN_DOWN]], align 8, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP12:%.*]] = load i32, ptr addrspace(4) [[ARG5_KERNARG_OFFSET_ALIGN_DOWN]], align 8, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP13:%.*]] = lshr i32 [[TMP12]], 8
 ; MESA-NEXT:    [[TMP14:%.*]] = trunc i32 [[TMP13]] to i8
 ; MESA-NEXT:    [[ARG6_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 40
-; MESA-NEXT:    [[TMP15:%.*]] = load i32, ptr addrspace(4) [[ARG6_KERNARG_OFFSET_ALIGN_DOWN]], align 8, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP15:%.*]] = load i32, ptr addrspace(4) [[ARG6_KERNARG_OFFSET_ALIGN_DOWN]], align 8, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP16:%.*]] = lshr i32 [[TMP15]], 16
 ; MESA-NEXT:    [[TMP17:%.*]] = trunc i32 [[TMP16]] to i8
 ; MESA-NEXT:    [[ARG7_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 40
-; MESA-NEXT:    [[TMP18:%.*]] = load i32, ptr addrspace(4) [[ARG7_KERNARG_OFFSET_ALIGN_DOWN]], align 8, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP18:%.*]] = load i32, ptr addrspace(4) [[ARG7_KERNARG_OFFSET_ALIGN_DOWN]], align 8, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP19:%.*]] = lshr i32 [[TMP18]], 24
 ; MESA-NEXT:    [[TMP20:%.*]] = trunc i32 [[TMP19]] to i8
 ; MESA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1
@@ -988,11 +988,11 @@ define amdgpu_kernel void @kern_realign_f16_f16(half %arg0, half %arg1) #0 {
 ; HSA-LABEL: @kern_realign_f16_f16(
 ; HSA-NEXT:    [[KERN_REALIGN_F16_F16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_F16_F16_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
 ; HSA-NEXT:    [[ARG0_LOAD:%.*]] = bitcast i16 [[TMP2]] to half
 ; HSA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_F16_F16_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 16
 ; HSA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16
 ; HSA-NEXT:    [[ARG1_LOAD:%.*]] = bitcast i16 [[TMP5]] to half
@@ -1003,11 +1003,11 @@ define amdgpu_kernel void @kern_realign_f16_f16(half %arg0, half %arg1) #0 {
 ; MESA-LABEL: @kern_realign_f16_f16(
 ; MESA-NEXT:    [[KERN_REALIGN_F16_F16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_F16_F16_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
 ; MESA-NEXT:    [[ARG0_LOAD:%.*]] = bitcast i16 [[TMP2]] to half
 ; MESA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_F16_F16_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 16
 ; MESA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16
 ; MESA-NEXT:    [[ARG1_LOAD:%.*]] = bitcast i16 [[TMP5]] to half
@@ -1024,14 +1024,14 @@ define amdgpu_kernel void @kern_global_ptr(ptr addrspace(1) %ptr) #0 {
 ; HSA-LABEL: @kern_global_ptr(
 ; HSA-NEXT:    [[KERN_GLOBAL_PTR_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_GLOBAL_PTR_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    store volatile ptr addrspace(1) [[PTR_LOAD]], ptr addrspace(1) poison, align 8
 ; HSA-NEXT:    ret void
 ;
 ; MESA-LABEL: @kern_global_ptr(
 ; MESA-NEXT:    [[KERN_GLOBAL_PTR_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_GLOBAL_PTR_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    store volatile ptr addrspace(1) [[PTR_LOAD]], ptr addrspace(1) poison, align 8
 ; MESA-NEXT:    ret void
 ;
@@ -1043,14 +1043,14 @@ define amdgpu_kernel void @kern_global_ptr_dereferencable(ptr addrspace(1) deref
 ; HSA-LABEL: @kern_global_ptr_dereferencable(
 ; HSA-NEXT:    [[KERN_GLOBAL_PTR_DEREFERENCABLE_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_GLOBAL_PTR_DEREFERENCABLE_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 16, !invariant.load [[META1]], !dereferenceable [[META3:![0-9]+]]
+; HSA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 16, !invariant.load [[META0]], !dereferenceable [[META2:![0-9]+]]
 ; HSA-NEXT:    store volatile ptr addrspace(1) [[PTR_LOAD]], ptr addrspace(1) poison, align 8
 ; HSA-NEXT:    ret void
 ;
 ; MESA-LABEL: @kern_global_ptr_dereferencable(
 ; MESA-NEXT:    [[KERN_GLOBAL_PTR_DEREFERENCABLE_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_GLOBAL_PTR_DEREFERENCABLE_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 4, !invariant.load [[META1]], !dereferenceable [[META3:![0-9]+]]
+; MESA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 4, !invariant.load [[META0]], !dereferenceable [[META2:![0-9]+]]
 ; MESA-NEXT:    store volatile ptr addrspace(1) [[PTR_LOAD]], ptr addrspace(1) poison, align 8
 ; MESA-NEXT:    ret void
 ;
@@ -1062,14 +1062,14 @@ define amdgpu_kernel void @kern_global_ptr_dereferencable_or_null(ptr addrspace(
 ; HSA-LABEL: @kern_global_ptr_dereferencable_or_null(
 ; HSA-NEXT:    [[KERN_GLOBAL_PTR_DEREFERENCABLE_OR_NULL_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_GLOBAL_PTR_DEREFERENCABLE_OR_NULL_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 16, !invariant.load [[META1]], !dereferenceable_or_null [[META4:![0-9]+]]
+; HSA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 16, !invariant.load [[META0]], !dereferenceable_or_null [[META3:![0-9]+]]
 ; HSA-NEXT:    store volatile ptr addrspace(1) [[PTR_LOAD]], ptr addrspace(1) poison, align 8
 ; HSA-NEXT:    ret void
 ;
 ; MESA-LABEL: @kern_global_ptr_dereferencable_or_null(
 ; MESA-NEXT:    [[KERN_GLOBAL_PTR_DEREFERENCABLE_OR_NULL_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_GLOBAL_PTR_DEREFERENCABLE_OR_NULL_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 4, !invariant.load [[META1]], !dereferenceable_or_null [[META4:![0-9]+]]
+; MESA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 4, !invariant.load [[META0]], !dereferenceable_or_null [[META3:![0-9]+]]
 ; MESA-NEXT:    store volatile ptr addrspace(1) [[PTR_LOAD]], ptr addrspace(1) poison, align 8
 ; MESA-NEXT:    ret void
 ;
@@ -1081,14 +1081,14 @@ define amdgpu_kernel void @kern_nonnull_global_ptr(ptr addrspace(1) nonnull %ptr
 ; HSA-LABEL: @kern_nonnull_global_ptr(
 ; HSA-NEXT:    [[KERN_NONNULL_GLOBAL_PTR_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_NONNULL_GLOBAL_PTR_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 16, !invariant.load [[META1]], !nonnull [[META1]]
+; HSA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 16, !invariant.load [[META0]], !nonnull [[META0]]
 ; HSA-NEXT:    store volatile ptr addrspace(1) [[PTR_LOAD]], ptr addrspace(1) poison, align 8
 ; HSA-NEXT:    ret void
 ;
 ; MESA-LABEL: @kern_nonnull_global_ptr(
 ; MESA-NEXT:    [[KERN_NONNULL_GLOBAL_PTR_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_NONNULL_GLOBAL_PTR_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 4, !invariant.load [[META1]], !nonnull [[META1]]
+; MESA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 4, !invariant.load [[META0]], !nonnull [[META0]]
 ; MESA-NEXT:    store volatile ptr addrspace(1) [[PTR_LOAD]], ptr addrspace(1) poison, align 8
 ; MESA-NEXT:    ret void
 ;
@@ -1100,14 +1100,14 @@ define amdgpu_kernel void @kern_align32_global_ptr(ptr addrspace(1) align 1024 %
 ; HSA-LABEL: @kern_align32_global_ptr(
 ; HSA-NEXT:    [[KERN_ALIGN32_GLOBAL_PTR_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_ALIGN32_GLOBAL_PTR_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 16, !invariant.load [[META1]], !align [[META5:![0-9]+]]
+; HSA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 16, !invariant.load [[META0]], !align [[META4:![0-9]+]]
 ; HSA-NEXT:    store volatile ptr addrspace(1) [[PTR_LOAD]], ptr addrspace(1) poison, align 8
 ; HSA-NEXT:    ret void
 ;
 ; MESA-LABEL: @kern_align32_global_ptr(
 ; MESA-NEXT:    [[KERN_ALIGN32_GLOBAL_PTR_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_ALIGN32_GLOBAL_PTR_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 4, !invariant.load [[META1]], !align [[META5:![0-9]+]]
+; MESA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 4, !invariant.load [[META0]], !align [[META4:![0-9]+]]
 ; MESA-NEXT:    store volatile ptr addrspace(1) [[PTR_LOAD]], ptr addrspace(1) poison, align 8
 ; MESA-NEXT:    ret void
 ;
@@ -1141,14 +1141,14 @@ define amdgpu_kernel void @kern_noundef_global_ptr(ptr addrspace(1) noundef %ptr
 ; HSA-LABEL: @kern_noundef_global_ptr(
 ; HSA-NEXT:    [[KERN_NOUNDEF_GLOBAL_PTR_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_NOUNDEF_GLOBAL_PTR_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 16, !invariant.load [[META1]], !noundef [[META1]]
+; HSA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 16, !invariant.load [[META0]], !noundef [[META0]]
 ; HSA-NEXT:    store volatile ptr addrspace(1) [[PTR_LOAD]], ptr addrspace(1) null, align 8
 ; HSA-NEXT:    ret void
 ;
 ; MESA-LABEL: @kern_noundef_global_ptr(
 ; MESA-NEXT:    [[KERN_NOUNDEF_GLOBAL_PTR_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_NOUNDEF_GLOBAL_PTR_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 4, !invariant.load [[META1]], !noundef [[META1]]
+; MESA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 4, !invariant.load [[META0]], !noundef [[META0]]
 ; MESA-NEXT:    store volatile ptr addrspace(1) [[PTR_LOAD]], ptr addrspace(1) null, align 8
 ; MESA-NEXT:    ret void
 ;
@@ -1161,7 +1161,7 @@ define amdgpu_kernel void @struct_i8_i8_arg({i8, i8} %in) #0 {
 ; HSA-NEXT:  entry:
 ; HSA-NEXT:    [[STRUCT_I8_I8_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[IN_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[STRUCT_I8_I8_ARG_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[IN_LOAD:%.*]] = load { i8, i8 }, ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[IN_LOAD:%.*]] = load { i8, i8 }, ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[ELT0:%.*]] = extractvalue { i8, i8 } [[IN_LOAD]], 0
 ; HSA-NEXT:    [[ELT1:%.*]] = extractvalue { i8, i8 } [[IN_LOAD]], 1
 ; HSA-NEXT:    store volatile i8 [[ELT0]], ptr addrspace(1) null, align 4
@@ -1172,7 +1172,7 @@ define amdgpu_kernel void @struct_i8_i8_arg({i8, i8} %in) #0 {
 ; MESA-NEXT:  entry:
 ; MESA-NEXT:    [[STRUCT_I8_I8_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[IN_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[STRUCT_I8_I8_ARG_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[IN_LOAD:%.*]] = load { i8, i8 }, ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[IN_LOAD:%.*]] = load { i8, i8 }, ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[ELT0:%.*]] = extractvalue { i8, i8 } [[IN_LOAD]], 0
 ; MESA-NEXT:    [[ELT1:%.*]] = extractvalue { i8, i8 } [[IN_LOAD]], 1
 ; MESA-NEXT:    store volatile i8 [[ELT0]], ptr addrspace(1) null, align 4
@@ -1192,7 +1192,7 @@ define amdgpu_kernel void @struct_i8_i16_arg({i8, i16} %in) #0 {
 ; HSA-NEXT:  entry:
 ; HSA-NEXT:    [[STRUCT_I8_I16_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[IN_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[STRUCT_I8_I16_ARG_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[IN_LOAD:%.*]] = load { i8, i16 }, ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[IN_LOAD:%.*]] = load { i8, i16 }, ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[ELT0:%.*]] = extractvalue { i8, i16 } [[IN_LOAD]], 0
 ; HSA-NEXT:    [[ELT1:%.*]] = extractvalue { i8, i16 } [[IN_LOAD]], 1
 ; HSA-NEXT:    store volatile i8 [[ELT0]], ptr addrspace(1) null, align 4
@@ -1203,7 +1203,7 @@ define amdgpu_kernel void @struct_i8_i16_arg({i8, i16} %in) #0 {
 ; MESA-NEXT:  entry:
 ; MESA-NEXT:    [[STRUCT_I8_I16_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[IN_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[STRUCT_I8_I16_ARG_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[IN_LOAD:%.*]] = load { i8, i16 }, ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[IN_LOAD:%.*]] = load { i8, i16 }, ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[ELT0:%.*]] = extractvalue { i8, i16 } [[IN_LOAD]], 0
 ; MESA-NEXT:    [[ELT1:%.*]] = extractvalue { i8, i16 } [[IN_LOAD]], 1
 ; MESA-NEXT:    store volatile i8 [[ELT0]], ptr addrspace(1) null, align 4
@@ -1223,7 +1223,7 @@ define amdgpu_kernel void @array_2xi8_arg([2 x i8] %in) #0 {
 ; HSA-NEXT:  entry:
 ; HSA-NEXT:    [[ARRAY_2XI8_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[IN_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[ARRAY_2XI8_ARG_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[IN_LOAD:%.*]] = load [2 x i8], ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[IN_LOAD:%.*]] = load [2 x i8], ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[ELT0:%.*]] = extractvalue [2 x i8] [[IN_LOAD]], 0
 ; HSA-NEXT:    [[ELT1:%.*]] = extractvalue [2 x i8] [[IN_LOAD]], 1
 ; HSA-NEXT:    store volatile i8 [[ELT0]], ptr addrspace(1) null, align 4
@@ -1234,7 +1234,7 @@ define amdgpu_kernel void @array_2xi8_arg([2 x i8] %in) #0 {
 ; MESA-NEXT:  entry:
 ; MESA-NEXT:    [[ARRAY_2XI8_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[IN_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[ARRAY_2XI8_ARG_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[IN_LOAD:%.*]] = load [2 x i8], ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[IN_LOAD:%.*]] = load [2 x i8], ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[ELT0:%.*]] = extractvalue [2 x i8] [[IN_LOAD]], 0
 ; MESA-NEXT:    [[ELT1:%.*]] = extractvalue [2 x i8] [[IN_LOAD]], 1
 ; MESA-NEXT:    store volatile i8 [[ELT0]], ptr addrspace(1) null, align 4
@@ -1254,7 +1254,7 @@ define amdgpu_kernel void @array_2xi1_arg([2 x i1] %in) #0 {
 ; HSA-NEXT:  entry:
 ; HSA-NEXT:    [[ARRAY_2XI1_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[IN_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[ARRAY_2XI1_ARG_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[IN_LOAD:%.*]] = load [2 x i1], ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[IN_LOAD:%.*]] = load [2 x i1], ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[ELT0:%.*]] = extractvalue [2 x i1] [[IN_LOAD]], 0
 ; HSA-NEXT:    [[ELT1:%.*]] = extractvalue [2 x i1] [[IN_LOAD]], 1
 ; HSA-NEXT:    store volatile i1 [[ELT0]], ptr addrspace(1) null, align 4
@@ -1265,7 +1265,7 @@ define amdgpu_kernel void @array_2xi1_arg([2 x i1] %in) #0 {
 ; MESA-NEXT:  entry:
 ; MESA-NEXT:    [[ARRAY_2XI1_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[IN_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[ARRAY_2XI1_ARG_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[IN_LOAD:%.*]] = load [2 x i1], ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[IN_LOAD:%.*]] = load [2 x i1], ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[ELT0:%.*]] = extractvalue [2 x i1] [[IN_LOAD]], 0
 ; MESA-NEXT:    [[ELT1:%.*]] = extractvalue [2 x i1] [[IN_LOAD]], 1
 ; MESA-NEXT:    store volatile i1 [[ELT0]], ptr addrspace(1) null, align 4
@@ -1292,14 +1292,14 @@ define amdgpu_kernel void @empty_struct_with_other({} %empty, i32 %arg1) #0 {
 ; HSA-LABEL: @empty_struct_with_other(
 ; HSA-NEXT:    [[EMPTY_STRUCT_WITH_OTHER_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG1_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[EMPTY_STRUCT_WITH_OTHER_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[ARG1_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[ARG1_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    store i32 [[ARG1_LOAD]], ptr addrspace(1) poison, align 4
 ; HSA-NEXT:    ret void
 ;
 ; MESA-LABEL: @empty_struct_with_other(
 ; MESA-NEXT:    [[EMPTY_STRUCT_WITH_OTHER_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG1_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[EMPTY_STRUCT_WITH_OTHER_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[ARG1_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[ARG1_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    store i32 [[ARG1_LOAD]], ptr addrspace(1) poison, align 4
 ; MESA-NEXT:    ret void
 ;
@@ -1313,7 +1313,7 @@ define amdgpu_kernel void @static_alloca_kern_i32(i32 %arg0) {
 ; HSA-NEXT:    [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5)
 ; HSA-NEXT:    [[STATIC_ALLOCA_KERN_I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[STATIC_ALLOCA_KERN_I32_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    store volatile i32 [[ARG0_LOAD]], ptr addrspace(5) [[ALLOCA]], align 4
 ; HSA-NEXT:    ret void
 ;
@@ -1321,7 +1321,7 @@ define amdgpu_kernel void @static_alloca_kern_i32(i32 %arg0) {
 ; MESA-NEXT:    [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5)
 ; MESA-NEXT:    [[STATIC_ALLOCA_KERN_I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[STATIC_ALLOCA_KERN_I32_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    store volatile i32 [[ARG0_LOAD]], ptr addrspace(5) [[ALLOCA]], align 4
 ; MESA-NEXT:    ret void
 ;
@@ -1337,7 +1337,7 @@ define amdgpu_kernel void @dyn_alloca_kernarg_i32(i32 %n) {
 ; HSA-NEXT:    [[ALLOCA0:%.*]] = alloca i32, align 4, addrspace(5)
 ; HSA-NEXT:    [[DYN_ALLOCA_KERNARG_I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[N_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[DYN_ALLOCA_KERNARG_I32_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[N_LOAD:%.*]] = load i32, ptr addrspace(4) [[N_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[N_LOAD:%.*]] = load i32, ptr addrspace(4) [[N_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[ALLOCA1:%.*]] = alloca i32, i32 [[N_LOAD]], align 4, addrspace(5)
 ; HSA-NEXT:    store volatile i32 0, ptr addrspace(5) [[ALLOCA0]], align 4
 ; HSA-NEXT:    store volatile i32 1, ptr addrspace(5) [[ALLOCA1]], align 4
@@ -1347,7 +1347,7 @@ define amdgpu_kernel void @dyn_alloca_kernarg_i32(i32 %n) {
 ; MESA-NEXT:    [[ALLOCA0:%.*]] = alloca i32, align 4, addrspace(5)
 ; MESA-NEXT:    [[DYN_ALLOCA_KERNARG_I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[N_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[DYN_ALLOCA_KERNARG_I32_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[N_LOAD:%.*]] = load i32, ptr addrspace(4) [[N_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[N_LOAD:%.*]] = load i32, ptr addrspace(4) [[N_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[ALLOCA1:%.*]] = alloca i32, i32 [[N_LOAD]], align 4, addrspace(5)
 ; MESA-NEXT:    store volatile i32 0, ptr addrspace(5) [[ALLOCA0]], align 4
 ; MESA-NEXT:    store volatile i32 1, ptr addrspace(5) [[ALLOCA1]], align 4
@@ -1365,7 +1365,7 @@ define amdgpu_kernel void @byref_constant_i8_arg(ptr addrspace(1) nocapture %out
 ; HSA-LABEL: @byref_constant_i8_arg(
 ; HSA-NEXT:    [[BYREF_CONSTANT_I8_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I8_ARG_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I8_ARG_KERNARG_SEGMENT]], i64 8
 ; HSA-NEXT:    [[IN:%.*]] = load i8, ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 1
 ; HSA-NEXT:    [[EXT:%.*]] = zext i8 [[IN]] to i32
@@ -1375,7 +1375,7 @@ define amdgpu_kernel void @byref_constant_i8_arg(ptr addrspace(1) nocapture %out
 ; MESA-LABEL: @byref_constant_i8_arg(
 ; MESA-NEXT:    [[BYREF_CONSTANT_I8_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(268) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I8_ARG_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I8_ARG_KERNARG_SEGMENT]], i64 44
 ; MESA-NEXT:    [[IN:%.*]] = load i8, ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 1
 ; MESA-NEXT:    [[EXT:%.*]] = zext i8 [[IN]] to i32
@@ -1392,7 +1392,7 @@ define amdgpu_kernel void @byref_constant_i16_arg(ptr addrspace(1) nocapture %ou
 ; HSA-LABEL: @byref_constant_i16_arg(
 ; HSA-NEXT:    [[BYREF_CONSTANT_I16_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I16_ARG_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I16_ARG_KERNARG_SEGMENT]], i64 8
 ; HSA-NEXT:    [[IN:%.*]] = load i16, ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 2
 ; HSA-NEXT:    [[EXT:%.*]] = zext i16 [[IN]] to i32
@@ -1402,7 +1402,7 @@ define amdgpu_kernel void @byref_constant_i16_arg(ptr addrspace(1) nocapture %ou
 ; MESA-LABEL: @byref_constant_i16_arg(
 ; MESA-NEXT:    [[BYREF_CONSTANT_I16_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(268) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I16_ARG_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I16_ARG_KERNARG_SEGMENT]], i64 44
 ; MESA-NEXT:    [[IN:%.*]] = load i16, ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 2
 ; MESA-NEXT:    [[EXT:%.*]] = zext i16 [[IN]] to i32
@@ -1419,10 +1419,10 @@ define amdgpu_kernel void @byref_constant_i32_arg(ptr addrspace(1) nocapture %ou
 ; HSA-LABEL: @byref_constant_i32_arg(
 ; HSA-NEXT:    [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 8
 ; HSA-NEXT:    [[AFTER_OFFSET_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 12
-; HSA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; HSA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; HSA-NEXT:    [[IN:%.*]] = load i32, ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 4
 ; HSA-NEXT:    store volatile i32 [[IN]], ptr addrspace(1) [[OUT_LOAD]], align 4
 ; HSA-NEXT:    store volatile i32 [[AFTER_OFFSET_LOAD]], ptr addrspace(1) [[OUT_LOAD]], align 4
@@ -1431,10 +1431,10 @@ define amdgpu_kernel void @byref_constant_i32_arg(ptr addrspace(1) nocapture %ou
 ; MESA-LABEL: @byref_constant_i32_arg(
 ; MESA-NEXT:    [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 44
 ; MESA-NEXT:    [[AFTER_OFFSET_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 48
-; MESA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; MESA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; MESA-NEXT:    [[IN:%.*]] = load i32, ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 4
 ; MESA-NEXT:    store volatile i32 [[IN]], ptr addrspace(1) [[OUT_LOAD]], align 4
 ; MESA-NEXT:    store volatile i32 [[AFTER_OFFSET_LOAD]], ptr addrspace(1) [[OUT_LOAD]], align 4
@@ -1450,10 +1450,10 @@ define amdgpu_kernel void @byref_constant_v4i32_arg(ptr addrspace(1) nocapture %
 ; HSA-LABEL: @byref_constant_v4i32_arg(
 ; HSA-NEXT:    [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(296) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT]], i64 16
 ; HSA-NEXT:    [[AFTER_OFFSET_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT]], i64 32
-; HSA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[IN:%.*]] = load <4 x i32>, ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 16
 ; HSA-NEXT:    store volatile <4 x i32> [[IN]], ptr addrspace(1) [[OUT_LOAD]], align 4
 ; HSA-NEXT:    store volatile i32 [[AFTER_OFFSET_LOAD]], ptr addrspace(1) [[OUT_LOAD]], align 4
@@ -1462,10 +1462,10 @@ define amdgpu_kernel void @byref_constant_v4i32_arg(ptr addrspace(1) nocapture %
 ; MESA-LABEL: @byref_constant_v4i32_arg(
 ; MESA-NEXT:    [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(292) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT]], i64 52
 ; MESA-NEXT:    [[AFTER_OFFSET_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT]], i64 68
-; MESA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[IN:%.*]] = load <4 x i32>, ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 16
 ; MESA-NEXT:    store volatile <4 x i32> [[IN]], ptr addrspace(1) [[OUT_LOAD]], align 4
 ; MESA-NEXT:    store volatile i32 [[AFTER_OFFSET_LOAD]], ptr addrspace(1) [[OUT_LOAD]], align 4
@@ -1481,10 +1481,10 @@ define amdgpu_kernel void @byref_align_constant_i32_arg(ptr addrspace(1) nocaptu
 ; HSA-LABEL: @byref_align_constant_i32_arg(
 ; HSA-NEXT:    [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 256 dereferenceable(520) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 256
 ; HSA-NEXT:    [[AFTER_OFFSET_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 260
-; HSA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; HSA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; HSA-NEXT:    [[IN:%.*]] = load i32, ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 4
 ; HSA-NEXT:    store volatile i32 [[IN]], ptr addrspace(1) [[OUT_LOAD]], align 4
 ; HSA-NEXT:    store volatile i32 [[AFTER_OFFSET_LOAD]], ptr addrspace(1) [[OUT_LOAD]], align 4
@@ -1493,10 +1493,10 @@ define amdgpu_kernel void @byref_align_constant_i32_arg(ptr addrspace(1) nocaptu
 ; MESA-LABEL: @byref_align_constant_i32_arg(
 ; MESA-NEXT:    [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 256 dereferenceable(520) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 292
 ; MESA-NEXT:    [[AFTER_OFFSET_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 296
-; MESA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 8, !invariant.load [[META1]]
+; MESA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 8, !invariant.load [[META0]]
 ; MESA-NEXT:    [[IN:%.*]] = load i32, ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 4
 ; MESA-NEXT:    store volatile i32 [[IN]], ptr addrspace(1) [[OUT_LOAD]], align 4
 ; MESA-NEXT:    store volatile i32 [[AFTER_OFFSET_LOAD]], ptr addrspace(1) [[OUT_LOAD]], align 4
@@ -1512,10 +1512,10 @@ define amdgpu_kernel void @byref_natural_align_constant_v16i32_arg(ptr addrspace
 ; HSA-LABEL: @byref_natural_align_constant_v16i32_arg(
 ; HSA-NEXT:    [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 64 dereferenceable(392) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT]], i64 64
 ; HSA-NEXT:    [[AFTER_OFFSET_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT]], i64 128
-; HSA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[IN:%.*]] = load <16 x i32>, ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 64
 ; HSA-NEXT:    store volatile <16 x i32> [[IN]], ptr addrspace(1) [[OUT_LOAD]], align 4
 ; HSA-NEXT:    store volatile i32 [[AFTER_OFFSET_LOAD]], ptr addrspace(1) [[OUT_LOAD]], align 4
@@ -1524,10 +1524,10 @@ define amdgpu_kernel void @byref_natural_align_constant_v16i32_arg(ptr addrspace
 ; MESA-LABEL: @byref_natural_align_constant_v16i32_arg(
 ; MESA-NEXT:    [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 64 dereferenceable(388) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT]], i64 100
 ; MESA-NEXT:    [[AFTER_OFFSET_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT]], i64 164
-; MESA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[IN:%.*]] = load <16 x i32>, ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 64
 ; MESA-NEXT:    store volatile <16 x i32> [[IN]], ptr addrspace(1) [[OUT_LOAD]], align 4
 ; MESA-NEXT:    store volatile i32 [[AFTER_OFFSET_LOAD]], ptr addrspace(1) [[OUT_LOAD]], align 4
@@ -1544,7 +1544,7 @@ define amdgpu_kernel void @byref_global_i32_arg(ptr addrspace(1) nocapture %out,
 ; HSA-LABEL: @byref_global_i32_arg(
 ; HSA-NEXT:    [[BYREF_GLOBAL_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_GLOBAL_I32_ARG_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_GLOBAL_I32_ARG_KERNARG_SEGMENT]], i64 8
 ; HSA-NEXT:    [[TMP1:%.*]] = addrspacecast ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to ptr addrspace(1)
 ; HSA-NEXT:    [[IN:%.*]] = load i32, ptr addrspace(1) [[TMP1]], align 4
@@ -1554,7 +1554,7 @@ define amdgpu_kernel void @byref_global_i32_arg(ptr addrspace(1) nocapture %out,
 ; MESA-LABEL: @byref_global_i32_arg(
 ; MESA-NEXT:    [[BYREF_GLOBAL_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(268) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_GLOBAL_I32_ARG_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_GLOBAL_I32_ARG_KERNARG_SEGMENT]], i64 44
 ; MESA-NEXT:    [[TMP1:%.*]] = addrspacecast ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to ptr addrspace(1)
 ; MESA-NEXT:    [[IN:%.*]] = load i32, ptr addrspace(1) [[TMP1]], align 4
@@ -1570,7 +1570,7 @@ define amdgpu_kernel void @byref_flat_i32_arg(ptr addrspace(1) nocapture %out, p
 ; HSA-LABEL: @byref_flat_i32_arg(
 ; HSA-NEXT:    [[BYREF_FLAT_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_FLAT_I32_ARG_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_FLAT_I32_ARG_KERNARG_SEGMENT]], i64 8
 ; HSA-NEXT:    [[TMP1:%.*]] = addrspacecast ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to ptr
 ; HSA-NEXT:    [[IN:%.*]] = load i32, ptr [[TMP1]], align 4
@@ -1580,7 +1580,7 @@ define amdgpu_kernel void @byref_flat_i32_arg(ptr addrspace(1) nocapture %out, p
 ; MESA-LABEL: @byref_flat_i32_arg(
 ; MESA-NEXT:    [[BYREF_FLAT_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(268) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_FLAT_I32_ARG_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_FLAT_I32_ARG_KERNARG_SEGMENT]], i64 44
 ; MESA-NEXT:    [[TMP1:%.*]] = addrspacecast ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to ptr
 ; MESA-NEXT:    [[IN:%.*]] = load i32, ptr [[TMP1]], align 4
@@ -1596,7 +1596,7 @@ define amdgpu_kernel void @byref_constant_32bit_i32_arg(ptr addrspace(1) nocaptu
 ; HSA-LABEL: @byref_constant_32bit_i32_arg(
 ; HSA-NEXT:    [[BYREF_CONSTANT_32BIT_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_32BIT_I32_ARG_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_32BIT_I32_ARG_KERNARG_SEGMENT]], i64 8
 ; HSA-NEXT:    [[TMP1:%.*]] = addrspacecast ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to ptr addrspace(6)
 ; HSA-NEXT:    [[IN:%.*]] = load i32, ptr addrspace(6) [[TMP1]], align 4
@@ -1606,7 +1606,7 @@ define amdgpu_kernel void @byref_constant_32bit_i32_arg(ptr addrspace(1) nocaptu
 ; MESA-LABEL: @byref_constant_32bit_i32_arg(
 ; MESA-NEXT:    [[BYREF_CONSTANT_32BIT_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(268) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_32BIT_I32_ARG_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_32BIT_I32_ARG_KERNARG_SEGMENT]], i64 44
 ; MESA-NEXT:    [[TMP1:%.*]] = addrspacecast ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to ptr addrspace(6)
 ; MESA-NEXT:    [[IN:%.*]] = load i32, ptr addrspace(6) [[TMP1]], align 4
@@ -1622,7 +1622,7 @@ define amdgpu_kernel void @byref_unknown_as_i32_arg(ptr addrspace(1) nocapture %
 ; HSA-LABEL: @byref_unknown_as_i32_arg(
 ; HSA-NEXT:    [[BYREF_UNKNOWN_AS_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_UNKNOWN_AS_I32_ARG_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_UNKNOWN_AS_I32_ARG_KERNARG_SEGMENT]], i64 8
 ; HSA-NEXT:    [[TMP1:%.*]] = addrspacecast ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to ptr addrspace(999)
 ; HSA-NEXT:    [[IN:%.*]] = load i32, ptr addrspace(999) [[TMP1]], align 4
@@ -1632,7 +1632,7 @@ define amdgpu_kernel void @byref_unknown_as_i32_arg(ptr addrspace(1) nocapture %
 ; MESA-LABEL: @byref_unknown_as_i32_arg(
 ; MESA-NEXT:    [[BYREF_UNKNOWN_AS_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(268) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_UNKNOWN_AS_I32_ARG_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_UNKNOWN_AS_I32_ARG_KERNARG_SEGMENT]], i64 44
 ; MESA-NEXT:    [[TMP1:%.*]] = addrspacecast ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to ptr addrspace(999)
 ; MESA-NEXT:    [[IN:%.*]] = load i32, ptr addrspace(999) [[TMP1]], align 4
@@ -1649,7 +1649,7 @@ define amdgpu_kernel void @byref_local_i32_arg(ptr addrspace(1) nocapture %out,
 ; HSA-LABEL: @byref_local_i32_arg(
 ; HSA-NEXT:    [[BYREF_LOCAL_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_LOCAL_I32_ARG_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_LOCAL_I32_ARG_KERNARG_SEGMENT]], i64 8
 ; HSA-NEXT:    [[TMP1:%.*]] = addrspacecast ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to ptr addrspace(3)
 ; HSA-NEXT:    [[IN:%.*]] = load i32, ptr addrspace(3) [[TMP1]], align 4
@@ -1659,7 +1659,7 @@ define amdgpu_kernel void @byref_local_i32_arg(ptr addrspace(1) nocapture %out,
 ; MESA-LABEL: @byref_local_i32_arg(
 ; MESA-NEXT:    [[BYREF_LOCAL_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(268) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_LOCAL_I32_ARG_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_LOCAL_I32_ARG_KERNARG_SEGMENT]], i64 44
 ; MESA-NEXT:    [[TMP1:%.*]] = addrspacecast ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to ptr addrspace(3)
 ; MESA-NEXT:    [[IN:%.*]] = load i32, ptr addrspace(3) [[TMP1]], align 4
@@ -1675,11 +1675,11 @@ define amdgpu_kernel void @multi_byref_constant_i32_arg(ptr addrspace(1) nocaptu
 ; HSA-LABEL: @multi_byref_constant_i32_arg(
 ; HSA-NEXT:    [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(280) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[IN0_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 8
 ; HSA-NEXT:    [[IN1_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 12
 ; HSA-NEXT:    [[AFTER_OFFSET_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 16
-; HSA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 16, !invariant.load [[META1]]
+; HSA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
 ; HSA-NEXT:    [[IN0:%.*]] = load i32, ptr addrspace(4) [[IN0_BYREF_BYVAL_KERNARG_OFFSET]], align 4
 ; HSA-NEXT:    [[IN1:%.*]] = load i32, ptr addrspace(4) [[IN1_BYREF_BYVAL_KERNARG_OFFSET]], align 4
 ; HSA-NEXT:    store volatile i32 [[IN0]], ptr addrspace(1) [[OUT_LOAD]], align 4
@@ -1690,11 +1690,11 @@ define amdgpu_kernel void @multi_byref_constant_i32_arg(ptr addrspace(1) nocaptu
 ; MESA-LABEL: @multi_byref_constant_i32_arg(
 ; MESA-NEXT:    [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(276) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[IN0_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 44
 ; MESA-NEXT:    [[IN1_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 48
 ; MESA-NEXT:    [[AFTER_OFFSET_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 52
-; MESA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 4, !invariant.load [[META1]]
+; MESA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
 ; MESA-NEXT:    [[IN0:%.*]] = load i32, ptr addrspace(4) [[IN0_BYREF_BYVAL_KERNARG_OFFSET]], align 4
 ; MESA-NEXT:    [[IN1:%.*]] = load i32, ptr addrspace(4) [[IN1_BYREF_BYVAL_KERNARG_OFFSET]], align 4
 ; MESA-NEXT:    store volatile i32 [[IN0]], ptr addrspace(1) [[OUT_LOAD]], align 4
@@ -1734,14 +1734,14 @@ define amdgpu_kernel void @noundef_f32(float noundef %arg0) {
 ; HSA-LABEL: @noundef_f32(
 ; HSA-NEXT:    [[NOUNDEF_F32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[NOUNDEF_F32_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load float, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META1]], !noundef [[META1]]
+; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load float, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META0]], !noundef [[META0]]
 ; HSA-NEXT:    call void (...) @llvm.fake.use(float [[ARG0_LOAD]])
 ; HSA-NEXT:    ret void
 ;
 ; MESA-LABEL: @noundef_f32(
 ; MESA-NEXT:    [[NOUNDEF_F32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[NOUNDEF_F32_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load float, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META1]], !noundef [[META1]]
+; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load float, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META0]], !noundef [[META0]]
 ; MESA-NEXT:    call void (...) @llvm.fake.use(float [[ARG0_LOAD]])
 ; MESA-NEXT:    ret void
 ;
@@ -1753,7 +1753,7 @@ define amdgpu_kernel void @noundef_f16(half noundef %arg0) {
 ; HSA-LABEL: @noundef_f16(
 ; HSA-NEXT:    [[NOUNDEF_F16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[NOUNDEF_F16_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META1]], !noundef [[META1]]
+; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]], !noundef [[META0]]
 ; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
 ; HSA-NEXT:    [[ARG0_LOAD:%.*]] = bitcast i16 [[TMP2]] to half
 ; HSA-NEXT:    call void (...) @llvm.fake.use(half [[ARG0_LOAD]])
@@ -1762,7 +1762,7 @@ define amdgpu_kernel void @noundef_f16(half noundef %arg0) {
 ; MESA-LABEL: @noundef_f16(
 ; MESA-NEXT:    [[NOUNDEF_F16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[NOUNDEF_F16_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META1]], !noundef [[META1]]
+; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]], !noundef [[META0]]
 ; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
 ; MESA-NEXT:    [[ARG0_LOAD:%.*]] = bitcast i16 [[TMP2]] to half
 ; MESA-NEXT:    call void (...) @llvm.fake.use(half [[ARG0_LOAD]])
@@ -1776,14 +1776,14 @@ define amdgpu_kernel void @noundef_v2i32(<2 x i32> noundef %arg0) {
 ; HSA-LABEL: @noundef_v2i32(
 ; HSA-NEXT:    [[NOUNDEF_V2I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[NOUNDEF_V2I32_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load <2 x i32>, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META1]], !noundef [[META1]]
+; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load <2 x i32>, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META0]], !noundef [[META0]]
 ; HSA-NEXT:    call void (...) @llvm.fake.use(<2 x i32> [[ARG0_LOAD]])
 ; HSA-NEXT:    ret void
 ;
 ; MESA-LABEL: @noundef_v2i32(
 ; MESA-NEXT:    [[NOUNDEF_V2I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[NOUNDEF_V2I32_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load <2 x i32>, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META1]], !noundef [[META1]]
+; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load <2 x i32>, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META0]], !noundef [[META0]]
 ; MESA-NEXT:    call void (...) @llvm.fake.use(<2 x i32> [[ARG0_LOAD]])
 ; MESA-NEXT:    ret void
 ;
@@ -1795,14 +1795,14 @@ define amdgpu_kernel void @noundef_p0(ptr noundef %arg0) {
 ; HSA-LABEL: @noundef_p0(
 ; HSA-NEXT:    [[NOUNDEF_P0_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[NOUNDEF_P0_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load ptr, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META1]], !noundef [[META1]]
+; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load ptr, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META0]], !noundef [[META0]]
 ; HSA-NEXT:    call void (...) @llvm.fake.use(ptr [[ARG0_LOAD]])
 ; HSA-NEXT:    ret void
 ;
 ; MESA-LABEL: @noundef_p0(
 ; MESA-NEXT:    [[NOUNDEF_P0_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[NOUNDEF_P0_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load ptr, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META1]], !noundef [[META1]]
+; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load ptr, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META0]], !noundef [[META0]]
 ; MESA-NEXT:    call void (...) @llvm.fake.use(ptr [[ARG0_LOAD]])
 ; MESA-NEXT:    ret void
 ;
@@ -1814,14 +1814,14 @@ define amdgpu_kernel void @noundef_v2p0(<2 x ptr> noundef %arg0) {
 ; HSA-LABEL: @noundef_v2p0(
 ; HSA-NEXT:    [[NOUNDEF_V2P0_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; HSA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[NOUNDEF_V2P0_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load <2 x ptr>, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META1]], !noundef [[META1]]
+; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load <2 x ptr>, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META0]], !noundef [[META0]]
 ; HSA-NEXT:    call void (...) @llvm.fake.use(<2 x ptr> [[ARG0_LOAD]])
 ; HSA-NEXT:    ret void
 ;
 ; MESA-LABEL: @noundef_v2p0(
 ; MESA-NEXT:    [[NOUNDEF_V2P0_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
 ; MESA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[NOUNDEF_V2P0_KERNARG_SEGMENT]], i64 36
-; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load <2 x ptr>, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META1]], !noundef [[META1]]
+; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load <2 x ptr>, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META0]], !noundef [[META0]]
 ; MESA-NEXT:    call void (...) @llvm.fake.use(<2 x ptr> [[ARG0_LOAD]])
 ; MESA-NEXT:    ret void
 ;
@@ -1834,8 +1834,6 @@ attributes #1 = { nounwind "target-cpu"="kaveri" "amdgpu-implicitarg-num-bytes"=
 attributes #2 = { nounwind "target-cpu"="tahiti" }
 
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
 ;.
 ; HSA: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: readwrite) }
 ; HSA: attributes #[[ATTR1:[0-9]+]] = { nounwind "target-cpu"="kaveri" }
@@ -1849,17 +1847,15 @@ attributes #2 = { nounwind "target-cpu"="tahiti" }
 ; MESA: attributes #[[ATTR3:[0-9]+]] = { nounwind "target-cpu"="tahiti" }
 ; MESA: attributes #[[ATTR4:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
 ;.
-; HSA: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 500}
-; HSA: [[META1]] = !{}
-; HSA: [[RNG2]] = !{i32 0, i32 8}
-; HSA: [[META3]] = !{i64 42}
-; HSA: [[META4]] = !{i64 128}
-; HSA: [[META5]] = !{i64 1024}
+; HSA: [[META0]] = !{}
+; HSA: [[RNG1]] = !{i32 0, i32 8}
+; HSA: [[META2]] = !{i64 42}
+; HSA: [[META3]] = !{i64 128}
+; HSA: [[META4]] = !{i64 1024}
 ;.
-; MESA: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 500}
-; MESA: [[META1]] = !{}
-; MESA: [[RNG2]] = !{i32 0, i32 8}
-; MESA: [[META3]] = !{i64 42}
-; MESA: [[META4]] = !{i64 128}
-; MESA: [[META5]] = !{i64 1024}
+; MESA: [[META0]] = !{}
+; MESA: [[RNG1]] = !{i32 0, i32 8}
+; MESA: [[META2]] = !{i64 42}
+; MESA: [[META3]] = !{i64 128}
+; MESA: [[META4]] = !{i64 1024}
 ;.
diff --git a/llvm/test/CodeGen/AMDGPU/lrint.ll b/llvm/test/CodeGen/AMDGPU/lrint.ll
index 58f782fd4ecdd..2f8ea71c1d4be 100644
--- a/llvm/test/CodeGen/AMDGPU/lrint.ll
+++ b/llvm/test/CodeGen/AMDGPU/lrint.ll
@@ -4,8 +4,10 @@
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GCN,GFX10,GFX10-SDAG %s
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GCN,GFX10,GFX10-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
 
 declare float @llvm.rint.f32(float)
 declare i32 @llvm.lrint.i32.f32(float)
@@ -491,11 +493,41 @@ entry:
 }
 
 define half @intrinsic_frint_half(half %arg) {
-; GCN-LABEL: intrinsic_frint_half:
-; GCN:       ; %bb.0: ; %entry
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_rndne_f16_e32 v0, v0
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: intrinsic_frint_half:
+; GFX9:       ; %bb.0: ; %entry
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_rndne_f16_e32 v0, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: intrinsic_frint_half:
+; GFX10:       ; %bb.0: ; %entry
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_rndne_f16_e32 v0, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: intrinsic_frint_half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_rndne_f16_e32 v0.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: intrinsic_frint_half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_rndne_f16_e32 v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: intrinsic_frint_half:
+; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_rndne_f16_e32 v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: intrinsic_frint_half:
+; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_rndne_f16_e32 v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = tail call half @llvm.rint.f16(half %arg)
   ret half %res
@@ -518,14 +550,41 @@ define i32 @intrinsic_lrint_i32_f16(half %arg) {
 ; GFX10-NEXT:    v_cvt_i32_f32_e32 v0, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: intrinsic_lrint_i32_f16:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_rndne_f16_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-NEXT:    v_cvt_i32_f32_e32 v0, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: intrinsic_lrint_i32_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_rndne_f16_e32 v0.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_cvt_i32_f32_e32 v0, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: intrinsic_lrint_i32_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_rndne_f16_e32 v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cvt_i32_f32_e32 v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: intrinsic_lrint_i32_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_rndne_f16_e32 v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_cvt_i32_f32_e32 v0, v0
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: intrinsic_lrint_i32_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_rndne_f16_e32 v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cvt_i32_f32_e32 v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = tail call i32 @llvm.lrint.i32.f16(half %arg)
   ret i32 %res
diff --git a/llvm/test/CodeGen/AMDGPU/lround.ll b/llvm/test/CodeGen/AMDGPU/lround.ll
index 7911631483931..8036e32f90eb0 100644
--- a/llvm/test/CodeGen/AMDGPU/lround.ll
+++ b/llvm/test/CodeGen/AMDGPU/lround.ll
@@ -3,8 +3,10 @@
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9-GISEL %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10-SDAG %s
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-SDAG,GFX11-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-SDAG,GFX11-SDAG-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-GISEL,GFX11-GISEL-FAKE16 %s
 
 define i32 @intrinsic_lround_i32_f32(float %arg) {
 ; GFX9-SDAG-LABEL: intrinsic_lround_i32_f32:
@@ -816,34 +818,66 @@ define half @intrinsic_fround_half(half %arg) {
 ; GFX10-GISEL-NEXT:    v_add_f16_e32 v0, v1, v0
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: intrinsic_fround_half:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_trunc_f16_e32 v1, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_sub_f16_e32 v2, v0, v1
-; GFX11-SDAG-NEXT:    v_cmp_ge_f16_e64 s0, |v2|, 0.5
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e64 v2, 0, 0x3c00, s0
-; GFX11-SDAG-NEXT:    v_bfi_b32 v0, 0x7fff, v2, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_f16_e32 v0, v1, v0
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: intrinsic_fround_half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_trunc_f16_e32 v1.h, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_sub_f16_e32 v1.l, v1.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_ge_f16_e64 s0, |v1.l|, 0.5
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0, 0x3c00, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_bfi_b32 v0, 0x7fff, v2, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v1.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-GISEL-LABEL: intrinsic_fround_half:
-; GFX11-GISEL:       ; %bb.0: ; %entry
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_trunc_f16_e32 v1, v0
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT:    v_sub_f16_e32 v2, v0, v1
-; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff8000, v0
-; GFX11-GISEL-NEXT:    v_cmp_ge_f16_e64 s0, |v2|, 0.5
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 0x3c00, s0
-; GFX11-GISEL-NEXT:    v_or_b32_e32 v0, v2, v0
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_add_f16_e32 v0, v1, v0
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-FAKE16-LABEL: intrinsic_fround_half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_trunc_f16_e32 v1, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_sub_f16_e32 v2, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_ge_f16_e64 s0, |v2|, 0.5
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v2, 0, 0x3c00, s0
+; GFX11-SDAG-FAKE16-NEXT:    v_bfi_b32 v0, 0x7fff, v2, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v1, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: intrinsic_fround_half:
+; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_trunc_f16_e32 v0.h, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_sub_f16_e32 v1.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    v_and_b16 v0.l, 0x8000, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_ge_f16_e64 s0, |v1.l|, 0.5
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0, 0x3c00, s0
+; GFX11-GISEL-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.h, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: intrinsic_fround_half:
+; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_trunc_f16_e32 v1, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_sub_f16_e32 v2, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff8000, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_ge_f16_e64 s0, |v2|, 0.5
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v2, 0, 0x3c00, s0
+; GFX11-GISEL-FAKE16-NEXT:    v_or_b32_e32 v0, v2, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v1, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = tail call half @llvm.round.f16(half %arg)
   ret half %res
@@ -907,40 +941,78 @@ define i32 @intrinsic_lround_i32_f16(half %arg) {
 ; GFX10-GISEL-NEXT:    v_cvt_i32_f32_e32 v0, v0
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: intrinsic_lround_i32_f16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_trunc_f16_e32 v1, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_sub_f16_e32 v2, v0, v1
-; GFX11-SDAG-NEXT:    v_cmp_ge_f16_e64 s0, |v2|, 0.5
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_cndmask_b32_e64 v2, 0, 0x3c00, s0
-; GFX11-SDAG-NEXT:    v_bfi_b32 v0, 0x7fff, v2, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_f16_e32 v0, v1, v0
-; GFX11-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_cvt_i32_f32_e32 v0, v0
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: intrinsic_lround_i32_f16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_trunc_f16_e32 v1.h, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_sub_f16_e32 v1.l, v1.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_ge_f16_e64 s0, |v1.l|, 0.5
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0, 0x3c00, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_bfi_b32 v0, 0x7fff, v2, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v1.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cvt_i32_f32_e32 v0, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-GISEL-LABEL: intrinsic_lround_i32_f16:
-; GFX11-GISEL:       ; %bb.0: ; %entry
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_trunc_f16_e32 v1, v0
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT:    v_sub_f16_e32 v2, v0, v1
-; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff8000, v0
-; GFX11-GISEL-NEXT:    v_cmp_ge_f16_e64 s0, |v2|, 0.5
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 0x3c00, s0
-; GFX11-GISEL-NEXT:    v_or_b32_e32 v0, v2, v0
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_add_f16_e32 v0, v1, v0
-; GFX11-GISEL-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_cvt_i32_f32_e32 v0, v0
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-FAKE16-LABEL: intrinsic_lround_i32_f16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_trunc_f16_e32 v1, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_sub_f16_e32 v2, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_ge_f16_e64 s0, |v2|, 0.5
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e64 v2, 0, 0x3c00, s0
+; GFX11-SDAG-FAKE16-NEXT:    v_bfi_b32 v0, 0x7fff, v2, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v1, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_cvt_i32_f32_e32 v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: intrinsic_lround_i32_f16:
+; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_trunc_f16_e32 v0.h, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_sub_f16_e32 v1.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    v_and_b16 v0.l, 0x8000, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_cmp_ge_f16_e64 s0, |v1.l|, 0.5
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0, 0x3c00, s0
+; GFX11-GISEL-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.h, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_cvt_i32_f32_e32 v0, v0
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: intrinsic_lround_i32_f16:
+; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_trunc_f16_e32 v1, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_sub_f16_e32 v2, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff8000, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cmp_ge_f16_e64 s0, |v2|, 0.5
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_cndmask_b32_e64 v2, 0, 0x3c00, s0
+; GFX11-GISEL-FAKE16-NEXT:    v_or_b32_e32 v0, v2, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v1, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_cvt_i32_f32_e32 v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = tail call i32 @llvm.lround.i32.f16(half %arg)
   ret i32 %res
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
index b77bdbf89c7c9..cbd824e171976 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
@@ -5,7 +5,9 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=VI,SDAG-VI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=SDAG-CI %s
 
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GISEL-GFX11 %s
+; FIXME-TRUE16. fix gisel
+; XUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-FAKE16 %s
 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GISEL-GFX9 %s
 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=VI,GISEL-VI %s
 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=GISEL-CI %s
@@ -547,3 +549,5 @@ declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #
 
 attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
 attributes #1 = { nounwind readnone speculatable }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GISEL-GFX11-FAKE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
index ef325da272005..1e42717f118a6 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
@@ -6,7 +6,9 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=VI,SDAG-VI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=SDAG-CI %s
 
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100 %s
+; FIXME-TRUE16. enable gisel
+; XUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-FAKE16 %s
 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX900,GISEL-GFX900 %s
 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX906,GISEL-GFX906 %s
 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=VI,GISEL-VI %s
@@ -2723,3 +2725,5 @@ declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #
 
 attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
 attributes #1 = { nounwind readnone speculatable }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GISEL-GFX1100-FAKE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix.ll b/llvm/test/CodeGen/AMDGPU/mad-mix.ll
index e1e356a92f28e..4e07ac7653fc0 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix.ll
@@ -7,7 +7,9 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=VI,SDAG-VI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=CI,SDAG-CI %s
 
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100 %s
+; FIXME-TRUE16. enable gisel
+; XUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-FAKE16 %s
 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX900,GISEL-GFX900 %s
 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX906,GISEL-GFX906 %s
 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx9-generic --amdhsa-code-object-version=6 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9GEN,GISEL-GFX9GEN %s
@@ -2762,3 +2764,5 @@ declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #
 attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
 attributes #1 = { nounwind "denormal-fp-math-f32"="ieee,ieee" }
 attributes #2 = { nounwind readnone speculatable }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GISEL-GFX1100-FAKE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/maximumnum.ll b/llvm/test/CodeGen/AMDGPU/maximumnum.ll
index 64afe3cd01255..718a266f49f5d 100644
--- a/llvm/test/CodeGen/AMDGPU/maximumnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/maximumnum.ll
@@ -2,8 +2,10 @@
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck -check-prefix=GFX8 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
 
 define half @v_maximumnum_f16(half %x, half %y) {
 ; GFX8-LABEL: v_maximumnum_f16:
@@ -30,27 +32,49 @@ define half @v_maximumnum_f16(half %x, half %y) {
 ; GFX10-NEXT:    v_max_f16_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_maximumnum_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: v_maximumnum_f16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_max_num_f16_e32 v1, v1, v1
-; GFX12-NEXT:    v_max_num_f16_e32 v0, v0, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_max_num_f16_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_maximumnum_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.h, v1.l, v1.l
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_maximumnum_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_maximumnum_f16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.h, v1.l, v1.l
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_maximumnum_f16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v1, v1, v1
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = call half @llvm.maximumnum.f16(half %x, half %y)
   ret half %result
 }
@@ -74,21 +98,37 @@ define half @v_maximumnum_f16_nnan(half %x, half %y) {
 ; GFX10-NEXT:    v_max_f16_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_maximumnum_f16_nnan:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: v_maximumnum_f16_nnan:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_max_num_f16_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_maximumnum_f16_nnan:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_maximumnum_f16_nnan:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_maximumnum_f16_nnan:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_maximumnum_f16_nnan:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = call nnan half @llvm.maximumnum.f16(half %x, half %y)
   ret half %result
 }
@@ -115,25 +155,45 @@ define half @v_maximumnum_f16_1.0(half %x) {
 ; GFX10-NEXT:    v_max_f16_e32 v0, 1.0, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_maximumnum_f16_1.0:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_max_f16_e32 v0, 1.0, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: v_maximumnum_f16_1.0:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_max_num_f16_e32 v0, v0, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_max_num_f16_e32 v0, 1.0, v0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_maximumnum_f16_1.0:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, 1.0, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_maximumnum_f16_1.0:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, 1.0, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_maximumnum_f16_1.0:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, 1.0, v0.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_maximumnum_f16_1.0:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v0, 1.0, v0
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = call half @llvm.maximumnum.f16(half %x, half 1.0)
   ret half %result
 }
@@ -232,91 +292,183 @@ define bfloat @v_maximumnum_bf16(bfloat %x, bfloat %y) {
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_maximumnum_bf16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_max_f32_e32 v2, v2, v2
-; GFX11-NEXT:    v_bfe_u32 v3, v2, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v4, 0x400000, v2
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v3, v3, v2, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc_lo
-; GFX11-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
-; GFX11-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: v_maximumnum_bf16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshlrev_b32_e32 v2, 16, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX12-NEXT:    v_lshlrev_b32_e32 v3, 16, v1
-; GFX12-NEXT:    v_lshlrev_b32_e32 v2, 16, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc_lo
-; GFX12-NEXT:    v_lshlrev_b32_e32 v3, 16, v1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v3
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo
-; GFX12-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_max_num_f32_e32 v2, v2, v2
-; GFX12-NEXT:    v_bfe_u32 v3, v2, 16, 1
-; GFX12-NEXT:    v_or_b32_e32 v4, 0x400000, v2
-; GFX12-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_add3_u32 v3, v3, v2, 0x7fff
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc_lo
-; GFX12-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
-; GFX12-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v1
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX12-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_maximumnum_bf16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v1, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v0.h, v0.l, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v3
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v1.l, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_max_f32_e32 v2, v2, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v2, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v3, v3, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v2, v3, v4, s0
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0, v1.l
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v1.l, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_maximumnum_bf16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v3
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_max_f32_e32 v2, v2, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v3, v3, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_maximumnum_bf16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v0
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v1, v1
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v0.h, v0.l, s0
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v1.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v3
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.l, v1.l, v0.l, vcc_lo
+; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v0.l
+; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_max_num_f32_e32 v2, v2, v2
+; GFX12-TRUE16-NEXT:    v_bfe_u32 v3, v2, 16, 1
+; GFX12-TRUE16-NEXT:    v_or_b32_e32 v4, 0x400000, v2
+; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v2, v2
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_add3_u32 v3, v3, v2, 0x7fff
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v2, v3, v4, s0
+; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0, v1.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v2
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v1.l, s0
+; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_maximumnum_bf16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v1
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v3
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_max_num_f32_e32 v2, v2, v2
+; GFX12-FAKE16-NEXT:    v_bfe_u32 v3, v2, 16, 1
+; GFX12-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v2
+; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_add3_u32 v3, v3, v2, 0x7fff
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v1
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = call bfloat @llvm.maximumnum.bf16(bfloat %x, bfloat %y)
   ret bfloat %result
 }
@@ -370,49 +522,97 @@ define bfloat @v_maximumnum_bf16_nnan(bfloat %x, bfloat %y) {
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_maximumnum_bf16_nnan:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v3, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo
-; GFX11-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v0
-; GFX11-NEXT:    v_dual_cndmask_b32 v0, v2, v0 :: v_dual_lshlrev_b32 v3, 16, v2
-; GFX11-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: v_maximumnum_bf16_nnan:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshlrev_b32_e32 v2, 16, v1
-; GFX12-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v3, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo
-; GFX12-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v0
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_dual_cndmask_b32 v0, v2, v0 :: v_dual_lshlrev_b32 v3, 16, v2
-; GFX12-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v1
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX12-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_maximumnum_bf16_nnan:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v3, v2
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v1.l, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v0.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v2.l
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_maximumnum_bf16_nnan:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v3, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v0
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v2, v0 :: v_dual_lshlrev_b32 v3, 16, v2
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_maximumnum_bf16_nnan:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v1
+; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v3, v2
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.l, v1.l, v0.l, vcc_lo
+; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v0.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v2.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo
+; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v1.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_maximumnum_bf16_nnan:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v3, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v0
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v2, v0 :: v_dual_lshlrev_b32 v3, 16, v2
+; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v1
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = call nnan bfloat @llvm.maximumnum.bf16(bfloat %x, bfloat %y)
   ret bfloat %result
 }
@@ -854,27 +1054,49 @@ define half @v_maximumnum_f16_s_v(half inreg %x, half %y) {
 ; GFX10-NEXT:    v_max_f16_e32 v0, v1, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_maximumnum_f16_s_v:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-NEXT:    v_max_f16_e64 v1, s0, s0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_max_f16_e32 v0, v1, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: v_maximumnum_f16_s_v:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_max_num_f16_e32 v0, v0, v0
-; GFX12-NEXT:    v_max_num_f16_e64 v1, s0, s0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_max_num_f16_e32 v0, v1, v0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_maximumnum_f16_s_v:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-TRUE16-NEXT:    v_max_f16_e64 v0.h, s0, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.h, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_maximumnum_f16_s_v:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-FAKE16-NEXT:    v_max_f16_e64 v1, s0, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_maximumnum_f16_s_v:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e64 v0.h, s0, s0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.h, v0.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_maximumnum_f16_s_v:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e64 v1, s0, s0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v0, v1, v0
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %result = call half @llvm.maximumnum.f16(half %x, half %y)
   ret half %result
 }
@@ -904,27 +1126,49 @@ define half @v_maximumnum_f16_v_s(half %x, half inreg %y) {
 ; GFX10-NEXT:    v_max_f16_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_maximumnum_f16_v_s:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_max_f16_e64 v1, s0, s0
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: v_maximumnum_f16_v_s:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_max_num_f16_e64 v1, s0, s0
-; GFX12-NEXT:    v_max_num_f16_e32 v0, v0, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_max_num_f16_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_maximumnum_f16_v_s:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e64 v0.h, s0, s0
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_maximumnum_f16_v_s:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e64 v1, s0, s0
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_maximumnum_f16_v_s:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e64 v0.h, s0, s0
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_maximumnum_f16_v_s:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e64 v1, s0, s0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %result = call half @llvm.maximumnum.f16(half %x, half %y)
   ret half %result
 }
@@ -954,27 +1198,49 @@ define half @v_maximumnum_f16_s_s(half inreg %x, half inreg %y) {
 ; GFX10-NEXT:    v_max_f16_e32 v0, v1, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_maximumnum_f16_s_s:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_max_f16_e64 v0, s1, s1
-; GFX11-NEXT:    v_max_f16_e64 v1, s0, s0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_max_f16_e32 v0, v1, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: v_maximumnum_f16_s_s:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_max_num_f16_e64 v0, s1, s1
-; GFX12-NEXT:    v_max_num_f16_e64 v1, s0, s0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_max_num_f16_e32 v0, v1, v0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_maximumnum_f16_s_s:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e64 v0.l, s1, s1
+; GFX11-TRUE16-NEXT:    v_max_f16_e64 v0.h, s0, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.h, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_maximumnum_f16_s_s:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e64 v0, s1, s1
+; GFX11-FAKE16-NEXT:    v_max_f16_e64 v1, s0, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_maximumnum_f16_s_s:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e64 v0.l, s1, s1
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e64 v0.h, s0, s0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.h, v0.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_maximumnum_f16_s_s:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e64 v0, s1, s1
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e64 v1, s0, s0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v0, v1, v0
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %result = call half @llvm.maximumnum.f16(half %x, half %y)
   ret half %result
 }
@@ -1511,27 +1777,49 @@ define half @v_maximumnum_f16_fabs_rhs(half %x, half %y) {
 ; GFX10-NEXT:    v_max_f16_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_maximumnum_f16_fabs_rhs:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_max_f16_e64 v1, |v1|, |v1|
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: v_maximumnum_f16_fabs_rhs:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX12-NEXT:    v_max_num_f16_e32 v0, v0, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_max_num_f16_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_maximumnum_f16_fabs_rhs:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e64 v0.h, |v1.l|, |v1.l|
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_maximumnum_f16_fabs_rhs:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e64 v1, |v1|, |v1|
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_maximumnum_f16_fabs_rhs:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_maximumnum_f16_fabs_rhs:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e64 v1, |v1|, |v1|
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %fabs.y = call half @llvm.fabs.f16(half %y)
   %result = call half @llvm.maximumnum.f16(half %x, half %fabs.y)
   ret half %result
@@ -1562,27 +1850,49 @@ define half @v_maximumnum_f16_fneg_fabs_rhs(half %x, half %y) {
 ; GFX10-NEXT:    v_max_f16_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_maximumnum_f16_fneg_fabs_rhs:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_max_f16_e64 v1, -|v1|, -|v1|
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: v_maximumnum_f16_fneg_fabs_rhs:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_max_num_f16_e64 v1, -|v1|, -|v1|
-; GFX12-NEXT:    v_max_num_f16_e32 v0, v0, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_max_num_f16_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_maximumnum_f16_fneg_fabs_rhs:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e64 v0.h, -|v1.l|, -|v1.l|
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_maximumnum_f16_fneg_fabs_rhs:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e64 v1, -|v1|, -|v1|
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_maximumnum_f16_fneg_fabs_rhs:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e64 v0.h, -|v1.l|, -|v1.l|
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_maximumnum_f16_fneg_fabs_rhs:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e64 v1, -|v1|, -|v1|
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %fabs.y = call half @llvm.fabs.f16(half %y)
   %fneg.fabs.y = fneg half %fabs.y
   %result = call half @llvm.maximumnum.f16(half %x, half %fneg.fabs.y)
@@ -1614,27 +1924,49 @@ define half @v_maximumnum_f16_fabs(half %x, half %y) {
 ; GFX10-NEXT:    v_max_f16_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_maximumnum_f16_fabs:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_max_f16_e64 v1, |v1|, |v1|
-; GFX11-NEXT:    v_max_f16_e64 v0, |v0|, |v0|
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: v_maximumnum_f16_fabs:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX12-NEXT:    v_max_num_f16_e64 v0, |v0|, |v0|
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_max_num_f16_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_maximumnum_f16_fabs:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e64 v0.h, |v1.l|, |v1.l|
+; GFX11-TRUE16-NEXT:    v_max_f16_e64 v0.l, |v0.l|, |v0.l|
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_maximumnum_f16_fabs:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e64 v1, |v1|, |v1|
+; GFX11-FAKE16-NEXT:    v_max_f16_e64 v0, |v0|, |v0|
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_maximumnum_f16_fabs:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e64 v0.l, |v0.l|, |v0.l|
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_maximumnum_f16_fabs:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e64 v1, |v1|, |v1|
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e64 v0, |v0|, |v0|
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %fabs.x = call half @llvm.fabs.f16(half %x)
   %fabs.y = call half @llvm.fabs.f16(half %y)
   %result = call half @llvm.maximumnum.f16(half %fabs.x, half %fabs.y)
@@ -1666,27 +1998,49 @@ define half @v_maximumnum_f16_fneg(half %x, half %y) {
 ; GFX10-NEXT:    v_max_f16_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_maximumnum_f16_fneg:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_max_f16_e64 v1, -v1, -v1
-; GFX11-NEXT:    v_max_f16_e64 v0, -v0, -v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: v_maximumnum_f16_fneg:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_max_num_f16_e64 v1, -v1, -v1
-; GFX12-NEXT:    v_max_num_f16_e64 v0, -v0, -v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_max_num_f16_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_maximumnum_f16_fneg:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e64 v0.h, -v1.l, -v1.l
+; GFX11-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_maximumnum_f16_fneg:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e64 v1, -v1, -v1
+; GFX11-FAKE16-NEXT:    v_max_f16_e64 v0, -v0, -v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_maximumnum_f16_fneg:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e64 v0.h, -v1.l, -v1.l
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e64 v0.l, -v0.l, -v0.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_maximumnum_f16_fneg:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e64 v1, -v1, -v1
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e64 v0, -v0, -v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %fneg.x = fneg half %x
   %fneg.y = fneg half %y
   %result = call half @llvm.maximumnum.f16(half %fneg.x, half %fneg.y)
diff --git a/llvm/test/CodeGen/AMDGPU/min.ll b/llvm/test/CodeGen/AMDGPU/min.ll
index 07072f6a36296..d2f4f54cefe78 100644
--- a/llvm/test/CodeGen/AMDGPU/min.ll
+++ b/llvm/test/CodeGen/AMDGPU/min.ll
@@ -4,7 +4,8 @@
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=VI %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX9 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define amdgpu_kernel void @v_test_imin_sle_i32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
 ; EG-LABEL: v_test_imin_sle_i32:
@@ -713,45 +714,85 @@ define amdgpu_kernel void @s_test_imin_sle_v4i8(ptr addrspace(1) %out, [8 x i32]
 ; GFX10-NEXT:    global_store_dword v2, v0, s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: s_test_imin_sle_v4i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    s_load_b32 s0, s[4:5], 0x28
-; GFX11-NEXT:    s_load_b32 s1, s[4:5], 0x4c
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_sext_i32_i16 s2, s0
-; GFX11-NEXT:    s_lshr_b32 s3, s0, 16
-; GFX11-NEXT:    s_sext_i32_i16 s7, s1
-; GFX11-NEXT:    s_lshr_b32 s8, s1, 16
-; GFX11-NEXT:    s_ashr_i32 s6, s0, 24
-; GFX11-NEXT:    s_bfe_i32 s0, s0, 0x80000
-; GFX11-NEXT:    s_ashr_i32 s9, s1, 24
-; GFX11-NEXT:    s_bfe_i32 s1, s1, 0x80000
-; GFX11-NEXT:    s_lshr_b32 s2, s2, 8
-; GFX11-NEXT:    s_bfe_i32 s3, s3, 0x80000
-; GFX11-NEXT:    s_lshr_b32 s7, s7, 8
-; GFX11-NEXT:    s_bfe_i32 s8, s8, 0x80000
-; GFX11-NEXT:    v_min_i16 v0, s6, s9
-; GFX11-NEXT:    v_min_i16 v1, s0, s1
-; GFX11-NEXT:    v_min_i16 v2, s3, s8
-; GFX11-NEXT:    v_min_i16 v3, s2, s7
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 8, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 8, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v2, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v1, v3
-; GFX11-NEXT:    v_mov_b32_e32 v2, 0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_store_b32 v2, v0, s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: s_test_imin_sle_v4i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    s_load_b32 s0, s[4:5], 0x28
+; GFX11-TRUE16-NEXT:    s_load_b32 s1, s[4:5], 0x4c
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_sext_i32_i16 s2, s0
+; GFX11-TRUE16-NEXT:    s_lshr_b32 s3, s0, 16
+; GFX11-TRUE16-NEXT:    s_sext_i32_i16 s7, s1
+; GFX11-TRUE16-NEXT:    s_lshr_b32 s8, s1, 16
+; GFX11-TRUE16-NEXT:    s_ashr_i32 s6, s0, 24
+; GFX11-TRUE16-NEXT:    s_ashr_i32 s9, s1, 24
+; GFX11-TRUE16-NEXT:    s_lshr_b32 s2, s2, 8
+; GFX11-TRUE16-NEXT:    s_bfe_i32 s3, s3, 0x80000
+; GFX11-TRUE16-NEXT:    s_bfe_i32 s0, s0, 0x80000
+; GFX11-TRUE16-NEXT:    s_lshr_b32 s7, s7, 8
+; GFX11-TRUE16-NEXT:    s_bfe_i32 s8, s8, 0x80000
+; GFX11-TRUE16-NEXT:    s_bfe_i32 s1, s1, 0x80000
+; GFX11-TRUE16-NEXT:    v_min_i16 v0.l, s6, s9
+; GFX11-TRUE16-NEXT:    v_min_i16 v1.l, s3, s8
+; GFX11-TRUE16-NEXT:    v_min_i16 v2.l, s2, s7
+; GFX11-TRUE16-NEXT:    v_min_i16 v3.l, s0, s1
+; GFX11-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 8, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v1, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v3, v2
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v1, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_store_b32 v2, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: s_test_imin_sle_v4i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    s_load_b32 s0, s[4:5], 0x28
+; GFX11-FAKE16-NEXT:    s_load_b32 s1, s[4:5], 0x4c
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_sext_i32_i16 s2, s0
+; GFX11-FAKE16-NEXT:    s_lshr_b32 s3, s0, 16
+; GFX11-FAKE16-NEXT:    s_sext_i32_i16 s7, s1
+; GFX11-FAKE16-NEXT:    s_lshr_b32 s8, s1, 16
+; GFX11-FAKE16-NEXT:    s_ashr_i32 s6, s0, 24
+; GFX11-FAKE16-NEXT:    s_bfe_i32 s0, s0, 0x80000
+; GFX11-FAKE16-NEXT:    s_ashr_i32 s9, s1, 24
+; GFX11-FAKE16-NEXT:    s_bfe_i32 s1, s1, 0x80000
+; GFX11-FAKE16-NEXT:    s_lshr_b32 s2, s2, 8
+; GFX11-FAKE16-NEXT:    s_bfe_i32 s3, s3, 0x80000
+; GFX11-FAKE16-NEXT:    s_lshr_b32 s7, s7, 8
+; GFX11-FAKE16-NEXT:    s_bfe_i32 s8, s8, 0x80000
+; GFX11-FAKE16-NEXT:    v_min_i16 v0, s6, s9
+; GFX11-FAKE16-NEXT:    v_min_i16 v1, s0, s1
+; GFX11-FAKE16-NEXT:    v_min_i16 v2, s3, s8
+; GFX11-FAKE16-NEXT:    v_min_i16 v3, s2, s7
+; GFX11-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 8, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 8, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_store_b32 v2, v0, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %cmp = icmp sle <4 x i8> %a, %b
   %val = select <4 x i1> %cmp, <4 x i8> %a, <4 x i8> %b
   store <4 x i8> %val, ptr addrspace(1) %out
@@ -1249,22 +1290,39 @@ define amdgpu_kernel void @v_test_imin_slt_i16(ptr addrspace(1) %out, ptr addrsp
 ; GFX10-NEXT:    global_store_short v0, v1, s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: v_test_imin_slt_i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x10
-; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_load_u16 v1, v0, s[2:3]
-; GFX11-NEXT:    global_load_u16 v2, v0, s[4:5]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_min_i16 v1, v1, v2
-; GFX11-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: v_test_imin_slt_i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x10
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3]
+; GFX11-TRUE16-NEXT:    global_load_d16_hi_b16 v0, v1, s[4:5]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_min_i16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: v_test_imin_slt_i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3]
+; GFX11-FAKE16-NEXT:    global_load_u16 v2, v0, s[4:5]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_min_i16 v1, v1, v2
+; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %a.gep = getelementptr inbounds i16, ptr addrspace(1) %aptr, i32 %tid
   %b.gep = getelementptr inbounds i16, ptr addrspace(1) %bptr, i32 %tid
@@ -2372,20 +2430,35 @@ define amdgpu_kernel void @v_test_umin_ult_i8(ptr addrspace(1) %out, ptr addrspa
 ; GFX10-NEXT:    global_store_byte v0, v1, s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: v_test_umin_ult_i8:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x10
-; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_load_u8 v1, v0, s[2:3]
-; GFX11-NEXT:    global_load_u8 v2, v0, s[4:5]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_min_u16 v1, v1, v2
-; GFX11-NEXT:    global_store_b8 v0, v1, s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: v_test_umin_ult_i8:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x10
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0x3ff, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    global_load_d16_u8 v0, v1, s[2:3]
+; GFX11-TRUE16-NEXT:    global_load_d16_hi_u8 v0, v1, s[4:5]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_min_u16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    global_store_b8 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: v_test_umin_ult_i8:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    global_load_u8 v1, v0, s[2:3]
+; GFX11-FAKE16-NEXT:    global_load_u8 v2, v0, s[4:5]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_min_u16 v1, v1, v2
+; GFX11-FAKE16-NEXT:    global_store_b8 v0, v1, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %a.gep = getelementptr inbounds i8, ptr addrspace(1) %a.ptr, i32 %tid
   %b.gep = getelementptr inbounds i8, ptr addrspace(1) %b.ptr, i32 %tid
diff --git a/llvm/test/CodeGen/AMDGPU/minimumnum.ll b/llvm/test/CodeGen/AMDGPU/minimumnum.ll
index a32b3b71cd606..2b4d687bb0c29 100644
--- a/llvm/test/CodeGen/AMDGPU/minimumnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/minimumnum.ll
@@ -2,8 +2,10 @@
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck -check-prefix=GFX8 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
 
 define half @v_minimumnum_f16(half %x, half %y) {
 ; GFX8-LABEL: v_minimumnum_f16:
@@ -30,27 +32,49 @@ define half @v_minimumnum_f16(half %x, half %y) {
 ; GFX10-NEXT:    v_min_f16_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_minimumnum_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: v_minimumnum_f16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_max_num_f16_e32 v1, v1, v1
-; GFX12-NEXT:    v_max_num_f16_e32 v0, v0, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_min_num_f16_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_minimumnum_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.h, v1.l, v1.l
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_minimumnum_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_minimumnum_f16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.h, v1.l, v1.l
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_minimumnum_f16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v1, v1, v1
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = call half @llvm.minimumnum.f16(half %x, half %y)
   ret half %result
 }
@@ -74,21 +98,37 @@ define half @v_minimumnum_f16_nnan(half %x, half %y) {
 ; GFX10-NEXT:    v_min_f16_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_minimumnum_f16_nnan:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: v_minimumnum_f16_nnan:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_min_num_f16_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_minimumnum_f16_nnan:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_minimumnum_f16_nnan:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_minimumnum_f16_nnan:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_minimumnum_f16_nnan:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = call nnan half @llvm.minimumnum.f16(half %x, half %y)
   ret half %result
 }
@@ -115,25 +155,45 @@ define half @v_minimumnum_f16_1.0(half %x) {
 ; GFX10-NEXT:    v_min_f16_e32 v0, 1.0, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_minimumnum_f16_1.0:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_min_f16_e32 v0, 1.0, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: v_minimumnum_f16_1.0:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_max_num_f16_e32 v0, v0, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_min_num_f16_e32 v0, 1.0, v0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_minimumnum_f16_1.0:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_min_f16_e32 v0.l, 1.0, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_minimumnum_f16_1.0:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_min_f16_e32 v0, 1.0, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_minimumnum_f16_1.0:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, 1.0, v0.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_minimumnum_f16_1.0:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_min_num_f16_e32 v0, 1.0, v0
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = call half @llvm.minimumnum.f16(half %x, half 1.0)
   ret half %result
 }
@@ -234,91 +294,183 @@ define bfloat @v_minimumnum_bf16(bfloat %x, bfloat %y) {
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_minimumnum_bf16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v2, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo
-; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_max_f32_e32 v2, v2, v2
-; GFX11-NEXT:    v_bfe_u32 v3, v2, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v4, 0x400000, v2
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v3, v3, v2, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc_lo
-; GFX11-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
-; GFX11-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: v_minimumnum_bf16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshlrev_b32_e32 v2, 16, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX12-NEXT:    v_lshlrev_b32_e32 v3, 16, v1
-; GFX12-NEXT:    v_lshlrev_b32_e32 v2, 16, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc_lo
-; GFX12-NEXT:    v_lshlrev_b32_e32 v3, 16, v1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v2, v3
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo
-; GFX12-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_max_num_f32_e32 v2, v2, v2
-; GFX12-NEXT:    v_bfe_u32 v3, v2, 16, 1
-; GFX12-NEXT:    v_or_b32_e32 v4, 0x400000, v2
-; GFX12-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_add3_u32 v3, v3, v2, 0x7fff
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc_lo
-; GFX12-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
-; GFX12-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
-; GFX12-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX12-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_minimumnum_bf16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v1, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v0.h, v0.l, s0
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v1.l
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v2, v3
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v1.l, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT:    v_max_f32_e32 v2, v2, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v2, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, 0x400000, v2
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v2, v2
+; GFX11-TRUE16-NEXT:    v_add3_u32 v3, v3, v2, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v2, v3, v4, s0
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v1.l
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v1.l, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_minimumnum_bf16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v2, v3
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_max_f32_e32 v2, v2, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v2, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v2
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v3, v3, v2, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_minimumnum_bf16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v0
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v1, v1
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v0.h, v0.l, s0
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v1.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v2, v3
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.l, v1.l, v0.l, vcc_lo
+; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0.l
+; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_max_num_f32_e32 v2, v2, v2
+; GFX12-TRUE16-NEXT:    v_bfe_u32 v3, v2, 16, 1
+; GFX12-TRUE16-NEXT:    v_or_b32_e32 v4, 0x400000, v2
+; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v2, v2
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_add3_u32 v3, v3, v2, 0x7fff
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v2, v3, v4, s0
+; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v1.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v2
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v1.l, s0
+; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_minimumnum_bf16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v1
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v2, v3
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_max_num_f32_e32 v2, v2, v2
+; GFX12-FAKE16-NEXT:    v_bfe_u32 v3, v2, 16, 1
+; GFX12-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v2
+; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_add3_u32 v3, v3, v2, 0x7fff
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = call bfloat @llvm.minimumnum.bf16(bfloat %x, bfloat %y)
   ret bfloat %result
 }
@@ -374,49 +526,97 @@ define bfloat @v_minimumnum_bf16_nnan(bfloat %x, bfloat %y) {
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_minimumnum_bf16_nnan:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 16, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v3, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo
-; GFX11-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
-; GFX11-NEXT:    v_dual_cndmask_b32 v0, v2, v0 :: v_dual_lshlrev_b32 v3, 16, v2
-; GFX11-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: v_minimumnum_bf16_nnan:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshlrev_b32_e32 v2, 16, v1
-; GFX12-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v3, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo
-; GFX12-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_dual_cndmask_b32 v0, v2, v0 :: v_dual_lshlrev_b32 v3, 16, v2
-; GFX12-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX12-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_minimumnum_bf16_nnan:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v3, v2
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v1.l, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v2.l
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_minimumnum_bf16_nnan:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v3, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
+; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v2, v0 :: v_dual_lshlrev_b32 v3, 16, v2
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_minimumnum_bf16_nnan:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v1
+; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v3, v2
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.l, v1.l, v0.l, vcc_lo
+; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v2.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo
+; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_minimumnum_bf16_nnan:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v3, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v2, v0 :: v_dual_lshlrev_b32 v3, 16, v2
+; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = call nnan bfloat @llvm.minimumnum.bf16(bfloat %x, bfloat %y)
   ret bfloat %result
 }
@@ -858,27 +1058,49 @@ define half @v_minimumnum_f16_v_s(half %x, half inreg %y) {
 ; GFX10-NEXT:    v_min_f16_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_minimumnum_f16_v_s:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_max_f16_e64 v1, s0, s0
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: v_minimumnum_f16_v_s:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_max_num_f16_e64 v1, s0, s0
-; GFX12-NEXT:    v_max_num_f16_e32 v0, v0, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_min_num_f16_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_minimumnum_f16_v_s:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e64 v0.h, s0, s0
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_minimumnum_f16_v_s:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e64 v1, s0, s0
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_minimumnum_f16_v_s:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e64 v0.h, s0, s0
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_minimumnum_f16_v_s:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e64 v1, s0, s0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %result = call half @llvm.minimumnum.f16(half %x, half %y)
   ret half %result
 }
@@ -908,27 +1130,49 @@ define half @v_minimumnum_f16_s_s(half inreg %x, half inreg %y) {
 ; GFX10-NEXT:    v_min_f16_e32 v0, v1, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_minimumnum_f16_s_s:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_max_f16_e64 v0, s1, s1
-; GFX11-NEXT:    v_max_f16_e64 v1, s0, s0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_min_f16_e32 v0, v1, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: v_minimumnum_f16_s_s:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_max_num_f16_e64 v0, s1, s1
-; GFX12-NEXT:    v_max_num_f16_e64 v1, s0, s0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_min_num_f16_e32 v0, v1, v0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_minimumnum_f16_s_s:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e64 v0.l, s1, s1
+; GFX11-TRUE16-NEXT:    v_max_f16_e64 v0.h, s0, s0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.h, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_minimumnum_f16_s_s:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e64 v0, s1, s1
+; GFX11-FAKE16-NEXT:    v_max_f16_e64 v1, s0, s0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_min_f16_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_minimumnum_f16_s_s:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e64 v0.l, s1, s1
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e64 v0.h, s0, s0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.h, v0.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_minimumnum_f16_s_s:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e64 v0, s1, s1
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e64 v1, s0, s0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_min_num_f16_e32 v0, v1, v0
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %result = call half @llvm.minimumnum.f16(half %x, half %y)
   ret half %result
 }
@@ -1465,27 +1709,49 @@ define half @v_minimumnum_f16_fabs_rhs(half %x, half %y) {
 ; GFX10-NEXT:    v_min_f16_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_minimumnum_f16_fabs_rhs:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_max_f16_e64 v1, |v1|, |v1|
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: v_minimumnum_f16_fabs_rhs:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX12-NEXT:    v_max_num_f16_e32 v0, v0, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_min_num_f16_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_minimumnum_f16_fabs_rhs:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e64 v0.h, |v1.l|, |v1.l|
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_minimumnum_f16_fabs_rhs:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e64 v1, |v1|, |v1|
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_minimumnum_f16_fabs_rhs:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_minimumnum_f16_fabs_rhs:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e64 v1, |v1|, |v1|
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %fabs.y = call half @llvm.fabs.f16(half %y)
   %result = call half @llvm.minimumnum.f16(half %x, half %fabs.y)
   ret half %result
@@ -1516,27 +1782,49 @@ define half @v_minimumnum_f16_fneg_fabs_rhs(half %x, half %y) {
 ; GFX10-NEXT:    v_min_f16_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_max_f16_e64 v1, -|v1|, -|v1|
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_max_num_f16_e64 v1, -|v1|, -|v1|
-; GFX12-NEXT:    v_max_num_f16_e32 v0, v0, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_min_num_f16_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e64 v0.h, -|v1.l|, -|v1.l|
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e64 v1, -|v1|, -|v1|
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e64 v0.h, -|v1.l|, -|v1.l|
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e64 v1, -|v1|, -|v1|
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %fabs.y = call half @llvm.fabs.f16(half %y)
   %fneg.fabs.y = fneg half %fabs.y
   %result = call half @llvm.minimumnum.f16(half %x, half %fneg.fabs.y)
@@ -1568,27 +1856,49 @@ define half @v_minimumnum_f16_fabs(half %x, half %y) {
 ; GFX10-NEXT:    v_min_f16_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_minimumnum_f16_fabs:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_max_f16_e64 v1, |v1|, |v1|
-; GFX11-NEXT:    v_max_f16_e64 v0, |v0|, |v0|
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: v_minimumnum_f16_fabs:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_max_num_f16_e64 v1, |v1|, |v1|
-; GFX12-NEXT:    v_max_num_f16_e64 v0, |v0|, |v0|
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_min_num_f16_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_minimumnum_f16_fabs:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e64 v0.h, |v1.l|, |v1.l|
+; GFX11-TRUE16-NEXT:    v_max_f16_e64 v0.l, |v0.l|, |v0.l|
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_minimumnum_f16_fabs:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e64 v1, |v1|, |v1|
+; GFX11-FAKE16-NEXT:    v_max_f16_e64 v0, |v0|, |v0|
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_minimumnum_f16_fabs:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e64 v0.l, |v0.l|, |v0.l|
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_minimumnum_f16_fabs:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e64 v1, |v1|, |v1|
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e64 v0, |v0|, |v0|
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %fabs.x = call half @llvm.fabs.f16(half %x)
   %fabs.y = call half @llvm.fabs.f16(half %y)
   %result = call half @llvm.minimumnum.f16(half %fabs.x, half %fabs.y)
@@ -1620,27 +1930,49 @@ define half @v_minimumnum_f16_fneg(half %x, half %y) {
 ; GFX10-NEXT:    v_min_f16_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_minimumnum_f16_fneg:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_max_f16_e64 v1, -v1, -v1
-; GFX11-NEXT:    v_max_f16_e64 v0, -v0, -v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: v_minimumnum_f16_fneg:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_max_num_f16_e64 v1, -v1, -v1
-; GFX12-NEXT:    v_max_num_f16_e64 v0, -v0, -v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_min_num_f16_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_minimumnum_f16_fneg:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e64 v0.h, -v1.l, -v1.l
+; GFX11-TRUE16-NEXT:    v_max_f16_e64 v0.l, -v0.l, -v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_minimumnum_f16_fneg:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e64 v1, -v1, -v1
+; GFX11-FAKE16-NEXT:    v_max_f16_e64 v0, -v0, -v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_minimumnum_f16_fneg:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e64 v0.h, -v1.l, -v1.l
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e64 v0.l, -v0.l, -v0.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_minimumnum_f16_fneg:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e64 v1, -v1, -v1
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e64 v0, -v0, -v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %fneg.x = fneg half %x
   %fneg.y = fneg half %y
   %result = call half @llvm.minimumnum.f16(half %fneg.x, half %fneg.y)
diff --git a/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll b/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
index 11d73732bbbc7..15f93f173eae8 100644
--- a/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
+++ b/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
@@ -230,5 +230,3 @@ define amdgpu_kernel void @nocall_false_sharing() {
 }
 ; CHECK: ; LDSByteSize: 4 bytes
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll b/llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
index 2d853212166e9..f30a04a5a76cf 100644
--- a/llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
+++ b/llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
@@ -274,5 +274,3 @@ entry:
 attributes #0 = { "frame-pointer"="none" noinline }
 attributes #1 = { "frame-pointer"="all" noinline }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/offset-split-flat.ll b/llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
index bf450ab6e80c4..61ac1fe92c278 100644
--- a/llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
+++ b/llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
@@ -1,12 +1,16 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
 
 ; Test splitting flat instruction offsets into the low and high bits
 ; when the offset doesn't fit in the offset field.
@@ -28,23 +32,59 @@ define i8 @flat_inst_valu_offset_1(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: flat_inst_valu_offset_1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    flat_load_u8 v0, v[0:1] offset:1
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: flat_inst_valu_offset_1:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:1
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:1
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:1
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:1
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:1
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: flat_inst_valu_offset_1:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:1
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: flat_inst_valu_offset_1:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:1
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr %p, i64 1
   %load = load i8, ptr %gep, align 4
   ret i8 %load
@@ -67,23 +107,59 @@ define i8 @flat_inst_valu_offset_11bit_max(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: flat_inst_valu_offset_11bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    flat_load_u8 v0, v[0:1] offset:2047
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: flat_inst_valu_offset_11bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:2047
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_11bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:2047
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_11bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:2047
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_11bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:2047
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_11bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:2047
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: flat_inst_valu_offset_11bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:2047
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: flat_inst_valu_offset_11bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:2047
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr %p, i64 2047
   %load = load i8, ptr %gep, align 4
   ret i8 %load
@@ -106,23 +182,59 @@ define i8 @flat_inst_valu_offset_12bit_max(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: flat_inst_valu_offset_12bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    flat_load_u8 v0, v[0:1] offset:4095
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: flat_inst_valu_offset_12bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:4095
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_12bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:4095
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_12bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:4095
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_12bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:4095
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_12bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:4095
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: flat_inst_valu_offset_12bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:4095
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: flat_inst_valu_offset_12bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:4095
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr %p, i64 4095
   %load = load i8, ptr %gep, align 4
   ret i8 %load
@@ -147,26 +259,47 @@ define i8 @flat_inst_valu_offset_13bit_max(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: flat_inst_valu_offset_13bit_max:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:4095
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: flat_inst_valu_offset_13bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:8191
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_13bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:4095
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_13bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:4095
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_13bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:8191
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_13bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:8191
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-GISEL-LABEL: flat_inst_valu_offset_13bit_max:
 ; GFX9-GISEL:       ; %bb.0:
@@ -186,6 +319,17 @@ define i8 @flat_inst_valu_offset_13bit_max(ptr %p) {
 ; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1]
 ; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: flat_inst_valu_offset_13bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:8191
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr %p, i64 8191
   %load = load i8, ptr %gep, align 4
   ret i8 %load
@@ -210,26 +354,47 @@ define i8 @flat_inst_valu_offset_24bit_max(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: flat_inst_valu_offset_24bit_max:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x7ff000, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:4095
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: flat_inst_valu_offset_24bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:8388607
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_24bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x7ff000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:4095
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_24bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x7ff000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:4095
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_24bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:8388607
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_24bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:8388607
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-GISEL-LABEL: flat_inst_valu_offset_24bit_max:
 ; GFX9-GISEL:       ; %bb.0:
@@ -249,6 +414,17 @@ define i8 @flat_inst_valu_offset_24bit_max(ptr %p) {
 ; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1]
 ; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: flat_inst_valu_offset_24bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:8388607
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr %p, i64 8388607
   %load = load i8, ptr %gep, align 4
   ret i8 %load
@@ -273,26 +449,68 @@ define i8 @flat_inst_valu_offset_neg_11bit_max(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: flat_inst_valu_offset_neg_11bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX11-NEXT:    flat_load_u8 v0, v[0:1]
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: flat_inst_valu_offset_neg_11bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:-2048
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_neg_11bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1]
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_neg_11bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_neg_11bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:-2048
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_neg_11bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:-2048
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: flat_inst_valu_offset_neg_11bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: flat_inst_valu_offset_neg_11bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:-2048
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr %p, i64 -2048
   %load = load i8, ptr %gep, align 4
   ret i8 %load
@@ -317,26 +535,68 @@ define i8 @flat_inst_valu_offset_neg_12bit_max(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: flat_inst_valu_offset_neg_12bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfffff000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX11-NEXT:    flat_load_u8 v0, v[0:1]
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: flat_inst_valu_offset_neg_12bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:-4096
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_neg_12bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfffff000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1]
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_neg_12bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfffff000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_neg_12bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:-4096
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_neg_12bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:-4096
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: flat_inst_valu_offset_neg_12bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfffff000, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: flat_inst_valu_offset_neg_12bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:-4096
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr %p, i64 -4096
   %load = load i8, ptr %gep, align 4
   ret i8 %load
@@ -361,26 +621,68 @@ define i8 @flat_inst_valu_offset_neg_13bit_max(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: flat_inst_valu_offset_neg_13bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffe000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX11-NEXT:    flat_load_u8 v0, v[0:1]
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: flat_inst_valu_offset_neg_13bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:-8192
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_neg_13bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffe000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1]
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_neg_13bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffe000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_neg_13bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:-8192
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_neg_13bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:-8192
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: flat_inst_valu_offset_neg_13bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffe000, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: flat_inst_valu_offset_neg_13bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:-8192
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr %p, i64 -8192
   %load = load i8, ptr %gep, align 4
   ret i8 %load
@@ -405,26 +707,68 @@ define i8 @flat_inst_valu_offset_neg_24bit_max(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: flat_inst_valu_offset_neg_24bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, 0xff800000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX11-NEXT:    flat_load_u8 v0, v[0:1]
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: flat_inst_valu_offset_neg_24bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:-8388608
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_neg_24bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xff800000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1]
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_neg_24bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xff800000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_neg_24bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:-8388608
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_neg_24bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:-8388608
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: flat_inst_valu_offset_neg_24bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0xff800000, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: flat_inst_valu_offset_neg_24bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:-8388608
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr %p, i64 -8388608
   %load = load i8, ptr %gep, align 4
   ret i8 %load
@@ -448,23 +792,59 @@ define i8 @flat_inst_valu_offset_2x_11bit_max(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: flat_inst_valu_offset_2x_11bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    flat_load_u8 v0, v[0:1] offset:4095
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: flat_inst_valu_offset_2x_11bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:4095
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_2x_11bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:4095
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_2x_11bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:4095
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_2x_11bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:4095
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_2x_11bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:4095
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: flat_inst_valu_offset_2x_11bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:4095
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: flat_inst_valu_offset_2x_11bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:4095
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr %p, i64 4095
   %load = load i8, ptr %gep, align 4
   ret i8 %load
@@ -489,26 +869,47 @@ define i8 @flat_inst_valu_offset_2x_12bit_max(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: flat_inst_valu_offset_2x_12bit_max:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:4095
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: flat_inst_valu_offset_2x_12bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:8191
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_2x_12bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:4095
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_2x_12bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:4095
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_2x_12bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:8191
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_2x_12bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:8191
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-GISEL-LABEL: flat_inst_valu_offset_2x_12bit_max:
 ; GFX9-GISEL:       ; %bb.0:
@@ -528,6 +929,17 @@ define i8 @flat_inst_valu_offset_2x_12bit_max(ptr %p) {
 ; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1]
 ; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: flat_inst_valu_offset_2x_12bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:8191
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr %p, i64 8191
   %load = load i8, ptr %gep, align 4
   ret i8 %load
@@ -552,26 +964,47 @@ define i8 @flat_inst_valu_offset_2x_13bit_max(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: flat_inst_valu_offset_2x_13bit_max:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x3000, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:4095
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: flat_inst_valu_offset_2x_13bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:16383
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_2x_13bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x3000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:4095
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_2x_13bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x3000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:4095
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_2x_13bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:16383
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_2x_13bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:16383
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-GISEL-LABEL: flat_inst_valu_offset_2x_13bit_max:
 ; GFX9-GISEL:       ; %bb.0:
@@ -591,6 +1024,17 @@ define i8 @flat_inst_valu_offset_2x_13bit_max(ptr %p) {
 ; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1]
 ; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: flat_inst_valu_offset_2x_13bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:16383
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr %p, i64 16383
   %load = load i8, ptr %gep, align 4
   ret i8 %load
@@ -615,29 +1059,53 @@ define i8 @flat_inst_valu_offset_2x_24bit_max(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: flat_inst_valu_offset_2x_24bit_max:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfff000, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:4094
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: flat_inst_valu_offset_2x_24bit_max:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:8388606
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_2x_24bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfff000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:4094
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_2x_24bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfff000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:4094
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_2x_24bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:8388606
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_2x_24bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:8388606
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-GISEL-LABEL: flat_inst_valu_offset_2x_24bit_max:
 ; GFX9-GISEL:       ; %bb.0:
@@ -695,26 +1163,68 @@ define i8 @flat_inst_valu_offset_2x_neg_11bit_max(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: flat_inst_valu_offset_2x_neg_11bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfffff000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX11-NEXT:    flat_load_u8 v0, v[0:1]
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: flat_inst_valu_offset_2x_neg_11bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:-4096
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_2x_neg_11bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfffff000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1]
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_2x_neg_11bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfffff000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_2x_neg_11bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:-4096
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_2x_neg_11bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:-4096
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: flat_inst_valu_offset_2x_neg_11bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfffff000, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: flat_inst_valu_offset_2x_neg_11bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:-4096
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr %p, i64 -4096
   %load = load i8, ptr %gep, align 4
   ret i8 %load
@@ -739,26 +1249,68 @@ define i8 @flat_inst_valu_offset_2x_neg_12bit_max(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: flat_inst_valu_offset_2x_neg_12bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffe000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX11-NEXT:    flat_load_u8 v0, v[0:1]
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: flat_inst_valu_offset_2x_neg_12bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:-8192
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_2x_neg_12bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffe000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1]
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_2x_neg_12bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffe000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_2x_neg_12bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:-8192
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_2x_neg_12bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:-8192
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: flat_inst_valu_offset_2x_neg_12bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffe000, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: flat_inst_valu_offset_2x_neg_12bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:-8192
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr %p, i64 -8192
   %load = load i8, ptr %gep, align 4
   ret i8 %load
@@ -783,26 +1335,68 @@ define i8 @flat_inst_valu_offset_2x_neg_13bit_max(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: flat_inst_valu_offset_2x_neg_13bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffc000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX11-NEXT:    flat_load_u8 v0, v[0:1]
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: flat_inst_valu_offset_2x_neg_13bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:-16384
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_2x_neg_13bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffc000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1]
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_2x_neg_13bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffc000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_2x_neg_13bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:-16384
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_2x_neg_13bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:-16384
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: flat_inst_valu_offset_2x_neg_13bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffc000, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: flat_inst_valu_offset_2x_neg_13bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:-16384
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr %p, i64 -16384
   %load = load i8, ptr %gep, align 4
   ret i8 %load
@@ -827,29 +1421,63 @@ define i8 @flat_inst_valu_offset_2x_neg_24bit_max(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: flat_inst_valu_offset_2x_neg_24bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, 0xff000001, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX11-NEXT:    flat_load_u8 v0, v[0:1]
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: flat_inst_valu_offset_2x_neg_24bit_max:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0xff800000, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX12-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:-8388607
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_2x_neg_24bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xff000001, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1]
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_2x_neg_24bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xff000001, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_2x_neg_24bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xff800000, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:-8388607
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_2x_neg_24bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xff800000, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:-8388607
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: flat_inst_valu_offset_2x_neg_24bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0xff000001, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: flat_inst_valu_offset_2x_neg_24bit_max:
 ; GFX12-GISEL:       ; %bb.0:
@@ -889,29 +1517,53 @@ define i8 @flat_inst_valu_offset_64bit_11bit_split0(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: flat_inst_valu_offset_64bit_11bit_split0:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:2047
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: flat_inst_valu_offset_64bit_11bit_split0:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
-; GFX12-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:2047
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_64bit_11bit_split0:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:2047
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_64bit_11bit_split0:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:2047
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_64bit_11bit_split0:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:2047
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_64bit_11bit_split0:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:2047
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-GISEL-LABEL: flat_inst_valu_offset_64bit_11bit_split0:
 ; GFX9-GISEL:       ; %bb.0:
@@ -970,29 +1622,53 @@ define i8 @flat_inst_valu_offset_64bit_11bit_split1(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: flat_inst_valu_offset_64bit_11bit_split1:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:2048
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: flat_inst_valu_offset_64bit_11bit_split1:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
-; GFX12-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:2048
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_64bit_11bit_split1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:2048
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_64bit_11bit_split1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:2048
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_64bit_11bit_split1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:2048
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_64bit_11bit_split1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:2048
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-GISEL-LABEL: flat_inst_valu_offset_64bit_11bit_split1:
 ; GFX9-GISEL:       ; %bb.0:
@@ -1051,29 +1727,53 @@ define i8 @flat_inst_valu_offset_64bit_12bit_split0(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: flat_inst_valu_offset_64bit_12bit_split0:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:4095
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: flat_inst_valu_offset_64bit_12bit_split0:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
-; GFX12-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:4095
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_64bit_12bit_split0:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:4095
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_64bit_12bit_split0:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:4095
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_64bit_12bit_split0:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:4095
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_64bit_12bit_split0:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:4095
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-GISEL-LABEL: flat_inst_valu_offset_64bit_12bit_split0:
 ; GFX9-GISEL:       ; %bb.0:
@@ -1132,29 +1832,63 @@ define i8 @flat_inst_valu_offset_64bit_12bit_split1(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: flat_inst_valu_offset_64bit_12bit_split1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
-; GFX11-NEXT:    flat_load_u8 v0, v[0:1]
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: flat_inst_valu_offset_64bit_12bit_split1:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
-; GFX12-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:4096
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_64bit_12bit_split1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1]
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_64bit_12bit_split1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_64bit_12bit_split1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:4096
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_64bit_12bit_split1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:4096
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: flat_inst_valu_offset_64bit_12bit_split1:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: flat_inst_valu_offset_64bit_12bit_split1:
 ; GFX12-GISEL:       ; %bb.0:
@@ -1194,29 +1928,53 @@ define i8 @flat_inst_valu_offset_64bit_13bit_split0(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: flat_inst_valu_offset_64bit_13bit_split0:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:4095
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: flat_inst_valu_offset_64bit_13bit_split0:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
-; GFX12-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:8191
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_64bit_13bit_split0:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:4095
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_64bit_13bit_split0:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:4095
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_64bit_13bit_split0:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:8191
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_64bit_13bit_split0:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:8191
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-GISEL-LABEL: flat_inst_valu_offset_64bit_13bit_split0:
 ; GFX9-GISEL:       ; %bb.0:
@@ -1275,29 +2033,63 @@ define i8 @flat_inst_valu_offset_64bit_13bit_split1(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: flat_inst_valu_offset_64bit_13bit_split1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
-; GFX11-NEXT:    flat_load_u8 v0, v[0:1]
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: flat_inst_valu_offset_64bit_13bit_split1:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
-; GFX12-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:8192
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_64bit_13bit_split1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1]
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_64bit_13bit_split1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_64bit_13bit_split1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:8192
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_64bit_13bit_split1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:8192
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: flat_inst_valu_offset_64bit_13bit_split1:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: flat_inst_valu_offset_64bit_13bit_split1:
 ; GFX12-GISEL:       ; %bb.0:
@@ -1338,29 +2130,53 @@ define i8 @flat_inst_valu_offset_64bit_11bit_neg_high_split0(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split0:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, 0x7ff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX11-NEXT:    flat_load_u8 v0, v[0:1]
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split0:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX12-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:-8386561
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split0:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x7ff, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1]
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split0:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x7ff, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split0:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:-8386561
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split0:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:-8386561
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-GISEL-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split0:
 ; GFX9-GISEL:       ; %bb.0:
@@ -1372,6 +2188,16 @@ define i8 @flat_inst_valu_offset_64bit_11bit_neg_high_split0(ptr %p) {
 ; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
+; GFX11-GISEL-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split0:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0x7ff, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
 ; GFX12-GISEL-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split0:
 ; GFX12-GISEL:       ; %bb.0:
 ; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
@@ -1411,29 +2237,53 @@ define i8 @flat_inst_valu_offset_64bit_11bit_neg_high_split1(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX11-NEXT:    flat_load_u8 v0, v[0:1]
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split1:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX12-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:-8386560
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1]
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:-8386560
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:-8386560
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-GISEL-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split1:
 ; GFX9-GISEL:       ; %bb.0:
@@ -1445,6 +2295,16 @@ define i8 @flat_inst_valu_offset_64bit_11bit_neg_high_split1(ptr %p) {
 ; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
+; GFX11-GISEL-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split1:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
 ; GFX12-GISEL-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split1:
 ; GFX12-GISEL:       ; %bb.0:
 ; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
@@ -1484,29 +2344,53 @@ define i8 @flat_inst_valu_offset_64bit_12bit_neg_high_split0(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split0:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX11-NEXT:    flat_load_u8 v0, v[0:1]
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split0:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX12-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:-8384513
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split0:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfff, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1]
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split0:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfff, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split0:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:-8384513
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split0:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:-8384513
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-GISEL-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split0:
 ; GFX9-GISEL:       ; %bb.0:
@@ -1518,6 +2402,16 @@ define i8 @flat_inst_valu_offset_64bit_12bit_neg_high_split0(ptr %p) {
 ; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
+; GFX11-GISEL-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split0:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfff, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
 ; GFX12-GISEL-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split0:
 ; GFX12-GISEL:       ; %bb.0:
 ; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
@@ -1557,29 +2451,53 @@ define i8 @flat_inst_valu_offset_64bit_12bit_neg_high_split1(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX11-NEXT:    flat_load_u8 v0, v[0:1]
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split1:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX12-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:-8384512
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1]
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:-8384512
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:-8384512
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-GISEL-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split1:
 ; GFX9-GISEL:       ; %bb.0:
@@ -1591,6 +2509,16 @@ define i8 @flat_inst_valu_offset_64bit_12bit_neg_high_split1(ptr %p) {
 ; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
+; GFX11-GISEL-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split1:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
 ; GFX12-GISEL-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split1:
 ; GFX12-GISEL:       ; %bb.0:
 ; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
@@ -1630,29 +2558,53 @@ define i8 @flat_inst_valu_offset_64bit_13bit_neg_high_split0(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split0:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1fff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX11-NEXT:    flat_load_u8 v0, v[0:1]
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split0:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX12-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:-8380417
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split0:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1fff, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1]
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split0:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1fff, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split0:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:-8380417
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split0:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:-8380417
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-GISEL-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split0:
 ; GFX9-GISEL:       ; %bb.0:
@@ -1664,6 +2616,16 @@ define i8 @flat_inst_valu_offset_64bit_13bit_neg_high_split0(ptr %p) {
 ; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
+; GFX11-GISEL-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split0:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1fff, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
 ; GFX12-GISEL-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split0:
 ; GFX12-GISEL:       ; %bb.0:
 ; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
@@ -1703,29 +2665,53 @@ define i8 @flat_inst_valu_offset_64bit_13bit_neg_high_split1(ptr %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX11-NEXT:    flat_load_u8 v0, v[0:1]
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split1:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX12-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:-8380416
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1]
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:-8380416
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:-8380416
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-GISEL-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split1:
 ; GFX9-GISEL:       ; %bb.0:
@@ -1737,6 +2723,16 @@ define i8 @flat_inst_valu_offset_64bit_13bit_neg_high_split1(ptr %p) {
 ; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
+; GFX11-GISEL-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split1:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
 ; GFX12-GISEL-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split1:
 ; GFX12-GISEL:       ; %bb.0:
 ; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
@@ -1780,25 +2776,65 @@ define amdgpu_kernel void @flat_inst_salu_offset_1(ptr %p) {
 ; GFX10-NEXT:    flat_store_byte v[0:1], v0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: flat_inst_salu_offset_1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX11-NEXT:    flat_load_u8 v0, v[0:1] offset:1 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    flat_store_b8 v[0:1], v0
-; GFX11-NEXT:    s_endpgm
-;
-; GFX12-LABEL: flat_inst_salu_offset_1:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:1 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    flat_store_b8 v[0:1], v0
-; GFX12-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_salu_offset_1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:1 glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_salu_offset_1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:1 glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_salu_offset_1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:1 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_salu_offset_1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:1 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX11-GISEL-LABEL: flat_inst_salu_offset_1:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:1 glc dlc
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-GISEL-NEXT:    s_endpgm
+;
+; GFX12-GISEL-LABEL: flat_inst_salu_offset_1:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:1 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 1
   %load = load volatile i8, ptr %gep, align 1
   store i8 %load, ptr poison
@@ -1830,25 +2866,65 @@ define amdgpu_kernel void @flat_inst_salu_offset_11bit_max(ptr %p) {
 ; GFX10-NEXT:    flat_store_byte v[0:1], v0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: flat_inst_salu_offset_11bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX11-NEXT:    flat_load_u8 v0, v[0:1] offset:2047 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    flat_store_b8 v[0:1], v0
-; GFX11-NEXT:    s_endpgm
-;
-; GFX12-LABEL: flat_inst_salu_offset_11bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:2047 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    flat_store_b8 v[0:1], v0
-; GFX12-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_salu_offset_11bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:2047 glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_salu_offset_11bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:2047 glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_salu_offset_11bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:2047 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_salu_offset_11bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:2047 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX11-GISEL-LABEL: flat_inst_salu_offset_11bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:2047 glc dlc
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-GISEL-NEXT:    s_endpgm
+;
+; GFX12-GISEL-LABEL: flat_inst_salu_offset_11bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:2047 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 2047
   %load = load volatile i8, ptr %gep, align 1
   store i8 %load, ptr poison
@@ -1880,25 +2956,65 @@ define amdgpu_kernel void @flat_inst_salu_offset_12bit_max(ptr %p) {
 ; GFX10-NEXT:    flat_store_byte v[0:1], v0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: flat_inst_salu_offset_12bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX11-NEXT:    flat_load_u8 v0, v[0:1] offset:4095 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    flat_store_b8 v[0:1], v0
-; GFX11-NEXT:    s_endpgm
-;
-; GFX12-LABEL: flat_inst_salu_offset_12bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:4095 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    flat_store_b8 v[0:1], v0
-; GFX12-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_salu_offset_12bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:4095 glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_salu_offset_12bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:4095 glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_salu_offset_12bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:4095 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_salu_offset_12bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:4095 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX11-GISEL-LABEL: flat_inst_salu_offset_12bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:4095 glc dlc
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-GISEL-NEXT:    s_endpgm
+;
+; GFX12-GISEL-LABEL: flat_inst_salu_offset_12bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:4095 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 4095
   %load = load volatile i8, ptr %gep, align 1
   store i8 %load, ptr poison
@@ -1932,27 +3048,49 @@ define amdgpu_kernel void @flat_inst_salu_offset_13bit_max(ptr %p) {
 ; GFX10-NEXT:    flat_store_byte v[0:1], v0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: flat_inst_salu_offset_13bit_max:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, s0, 0x1000, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, s1, s0
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:4095 glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-LABEL: flat_inst_salu_offset_13bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:8191 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    flat_store_b8 v[0:1], v0
-; GFX12-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_salu_offset_13bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0x1000, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, s1, s0
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:4095 glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_salu_offset_13bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0x1000, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, s1, s0
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:4095 glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_salu_offset_13bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:8191 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_salu_offset_13bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:8191 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX9-GISEL-LABEL: flat_inst_salu_offset_13bit_max:
 ; GFX9-GISEL:       ; %bb.0:
@@ -1979,6 +3117,16 @@ define amdgpu_kernel void @flat_inst_salu_offset_13bit_max(ptr %p) {
 ; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX11-GISEL-NEXT:    flat_store_b8 v[0:1], v0
 ; GFX11-GISEL-NEXT:    s_endpgm
+;
+; GFX12-GISEL-LABEL: flat_inst_salu_offset_13bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:8191 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 8191
   %load = load volatile i8, ptr %gep, align 1
   store i8 %load, ptr poison
@@ -2012,27 +3160,49 @@ define amdgpu_kernel void @flat_inst_salu_offset_neg_11bit_max(ptr %p) {
 ; GFX10-NEXT:    flat_store_byte v[0:1], v0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: flat_inst_salu_offset_neg_11bit_max:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, s0, 0xfffff800, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-LABEL: flat_inst_salu_offset_neg_11bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:-2048 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    flat_store_b8 v[0:1], v0
-; GFX12-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_salu_offset_neg_11bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0xfffff800, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_salu_offset_neg_11bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0xfffff800, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_salu_offset_neg_11bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:-2048 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_salu_offset_neg_11bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:-2048 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX9-GISEL-LABEL: flat_inst_salu_offset_neg_11bit_max:
 ; GFX9-GISEL:       ; %bb.0:
@@ -2059,6 +3229,16 @@ define amdgpu_kernel void @flat_inst_salu_offset_neg_11bit_max(ptr %p) {
 ; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX11-GISEL-NEXT:    flat_store_b8 v[0:1], v0
 ; GFX11-GISEL-NEXT:    s_endpgm
+;
+; GFX12-GISEL-LABEL: flat_inst_salu_offset_neg_11bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:-2048 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 -2048
   %load = load volatile i8, ptr %gep, align 1
   store i8 %load, ptr poison
@@ -2092,27 +3272,49 @@ define amdgpu_kernel void @flat_inst_salu_offset_neg_12bit_max(ptr %p) {
 ; GFX10-NEXT:    flat_store_byte v[0:1], v0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: flat_inst_salu_offset_neg_12bit_max:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, s0, 0xfffff000, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-LABEL: flat_inst_salu_offset_neg_12bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:-4096 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    flat_store_b8 v[0:1], v0
-; GFX12-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_salu_offset_neg_12bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0xfffff000, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_salu_offset_neg_12bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0xfffff000, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_salu_offset_neg_12bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:-4096 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_salu_offset_neg_12bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:-4096 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX9-GISEL-LABEL: flat_inst_salu_offset_neg_12bit_max:
 ; GFX9-GISEL:       ; %bb.0:
@@ -2139,6 +3341,16 @@ define amdgpu_kernel void @flat_inst_salu_offset_neg_12bit_max(ptr %p) {
 ; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX11-GISEL-NEXT:    flat_store_b8 v[0:1], v0
 ; GFX11-GISEL-NEXT:    s_endpgm
+;
+; GFX12-GISEL-LABEL: flat_inst_salu_offset_neg_12bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:-4096 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 -4096
   %load = load volatile i8, ptr %gep, align 1
   store i8 %load, ptr poison
@@ -2172,27 +3384,49 @@ define amdgpu_kernel void @flat_inst_salu_offset_neg_13bit_max(ptr %p) {
 ; GFX10-NEXT:    flat_store_byte v[0:1], v0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: flat_inst_salu_offset_neg_13bit_max:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, s0, 0xffffe000, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-LABEL: flat_inst_salu_offset_neg_13bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:-8192 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    flat_store_b8 v[0:1], v0
-; GFX12-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_salu_offset_neg_13bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0xffffe000, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_salu_offset_neg_13bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0xffffe000, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_salu_offset_neg_13bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:-8192 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_salu_offset_neg_13bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:-8192 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX9-GISEL-LABEL: flat_inst_salu_offset_neg_13bit_max:
 ; GFX9-GISEL:       ; %bb.0:
@@ -2219,6 +3453,16 @@ define amdgpu_kernel void @flat_inst_salu_offset_neg_13bit_max(ptr %p) {
 ; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX11-GISEL-NEXT:    flat_store_b8 v[0:1], v0
 ; GFX11-GISEL-NEXT:    s_endpgm
+;
+; GFX12-GISEL-LABEL: flat_inst_salu_offset_neg_13bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:-8192 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 -8192
   %load = load volatile i8, ptr %gep, align 1
   store i8 %load, ptr poison
@@ -2250,25 +3494,65 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_11bit_max(ptr %p) {
 ; GFX10-NEXT:    flat_store_byte v[0:1], v0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: flat_inst_salu_offset_2x_11bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX11-NEXT:    flat_load_u8 v0, v[0:1] offset:4095 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    flat_store_b8 v[0:1], v0
-; GFX11-NEXT:    s_endpgm
-;
-; GFX12-LABEL: flat_inst_salu_offset_2x_11bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:4095 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    flat_store_b8 v[0:1], v0
-; GFX12-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_salu_offset_2x_11bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:4095 glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_salu_offset_2x_11bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:4095 glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_salu_offset_2x_11bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:4095 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_salu_offset_2x_11bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:4095 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX11-GISEL-LABEL: flat_inst_salu_offset_2x_11bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:4095 glc dlc
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-GISEL-NEXT:    s_endpgm
+;
+; GFX12-GISEL-LABEL: flat_inst_salu_offset_2x_11bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:4095 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 4095
   %load = load volatile i8, ptr %gep, align 1
   store i8 %load, ptr poison
@@ -2302,27 +3586,49 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_12bit_max(ptr %p) {
 ; GFX10-NEXT:    flat_store_byte v[0:1], v0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: flat_inst_salu_offset_2x_12bit_max:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, s0, 0x1000, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, s1, s0
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:4095 glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-LABEL: flat_inst_salu_offset_2x_12bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:8191 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    flat_store_b8 v[0:1], v0
-; GFX12-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_salu_offset_2x_12bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0x1000, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, s1, s0
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:4095 glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_salu_offset_2x_12bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0x1000, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, s1, s0
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:4095 glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_salu_offset_2x_12bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:8191 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_salu_offset_2x_12bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:8191 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX9-GISEL-LABEL: flat_inst_salu_offset_2x_12bit_max:
 ; GFX9-GISEL:       ; %bb.0:
@@ -2349,6 +3655,16 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_12bit_max(ptr %p) {
 ; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX11-GISEL-NEXT:    flat_store_b8 v[0:1], v0
 ; GFX11-GISEL-NEXT:    s_endpgm
+;
+; GFX12-GISEL-LABEL: flat_inst_salu_offset_2x_12bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:8191 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 8191
   %load = load volatile i8, ptr %gep, align 1
   store i8 %load, ptr poison
@@ -2382,27 +3698,49 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_13bit_max(ptr %p) {
 ; GFX10-NEXT:    flat_store_byte v[0:1], v0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: flat_inst_salu_offset_2x_13bit_max:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, s0, 0x3000, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, s1, s0
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:4095 glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-LABEL: flat_inst_salu_offset_2x_13bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:16383 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    flat_store_b8 v[0:1], v0
-; GFX12-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_salu_offset_2x_13bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0x3000, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, s1, s0
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:4095 glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_salu_offset_2x_13bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0x3000, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, s1, s0
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:4095 glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_salu_offset_2x_13bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:16383 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_salu_offset_2x_13bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:16383 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX9-GISEL-LABEL: flat_inst_salu_offset_2x_13bit_max:
 ; GFX9-GISEL:       ; %bb.0:
@@ -2429,6 +3767,16 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_13bit_max(ptr %p) {
 ; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX11-GISEL-NEXT:    flat_store_b8 v[0:1], v0
 ; GFX11-GISEL-NEXT:    s_endpgm
+;
+; GFX12-GISEL-LABEL: flat_inst_salu_offset_2x_13bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:16383 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 16383
   %load = load volatile i8, ptr %gep, align 1
   store i8 %load, ptr poison
@@ -2462,27 +3810,49 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_neg_11bit_max(ptr %p) {
 ; GFX10-NEXT:    flat_store_byte v[0:1], v0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: flat_inst_salu_offset_2x_neg_11bit_max:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, s0, 0xfffff000, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-LABEL: flat_inst_salu_offset_2x_neg_11bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:-4096 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    flat_store_b8 v[0:1], v0
-; GFX12-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_salu_offset_2x_neg_11bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0xfffff000, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_salu_offset_2x_neg_11bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0xfffff000, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_salu_offset_2x_neg_11bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:-4096 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_salu_offset_2x_neg_11bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:-4096 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX9-GISEL-LABEL: flat_inst_salu_offset_2x_neg_11bit_max:
 ; GFX9-GISEL:       ; %bb.0:
@@ -2509,6 +3879,16 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_neg_11bit_max(ptr %p) {
 ; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX11-GISEL-NEXT:    flat_store_b8 v[0:1], v0
 ; GFX11-GISEL-NEXT:    s_endpgm
+;
+; GFX12-GISEL-LABEL: flat_inst_salu_offset_2x_neg_11bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:-4096 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 -4096
   %load = load volatile i8, ptr %gep, align 1
   store i8 %load, ptr poison
@@ -2542,27 +3922,49 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_neg_12bit_max(ptr %p) {
 ; GFX10-NEXT:    flat_store_byte v[0:1], v0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: flat_inst_salu_offset_2x_neg_12bit_max:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, s0, 0xffffe000, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-LABEL: flat_inst_salu_offset_2x_neg_12bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:-8192 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    flat_store_b8 v[0:1], v0
-; GFX12-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_salu_offset_2x_neg_12bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0xffffe000, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_salu_offset_2x_neg_12bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0xffffe000, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_salu_offset_2x_neg_12bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:-8192 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_salu_offset_2x_neg_12bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:-8192 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX9-GISEL-LABEL: flat_inst_salu_offset_2x_neg_12bit_max:
 ; GFX9-GISEL:       ; %bb.0:
@@ -2589,6 +3991,16 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_neg_12bit_max(ptr %p) {
 ; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX11-GISEL-NEXT:    flat_store_b8 v[0:1], v0
 ; GFX11-GISEL-NEXT:    s_endpgm
+;
+; GFX12-GISEL-LABEL: flat_inst_salu_offset_2x_neg_12bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:-8192 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 -8192
   %load = load volatile i8, ptr %gep, align 1
   store i8 %load, ptr poison
@@ -2622,27 +4034,49 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_neg_13bit_max(ptr %p) {
 ; GFX10-NEXT:    flat_store_byte v[0:1], v0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: flat_inst_salu_offset_2x_neg_13bit_max:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, s0, 0xffffc000, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-LABEL: flat_inst_salu_offset_2x_neg_13bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX12-NEXT:    flat_load_u8 v0, v[0:1] offset:-16384 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    flat_store_b8 v[0:1], v0
-; GFX12-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_salu_offset_2x_neg_13bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0xffffc000, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_salu_offset_2x_neg_13bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0xffffc000, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_salu_offset_2x_neg_13bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:-16384 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_salu_offset_2x_neg_13bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:-16384 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX9-GISEL-LABEL: flat_inst_salu_offset_2x_neg_13bit_max:
 ; GFX9-GISEL:       ; %bb.0:
@@ -2669,6 +4103,16 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_neg_13bit_max(ptr %p) {
 ; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX11-GISEL-NEXT:    flat_store_b8 v[0:1], v0
 ; GFX11-GISEL-NEXT:    s_endpgm
+;
+; GFX12-GISEL-LABEL: flat_inst_salu_offset_2x_neg_13bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:-16384 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-GISEL-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr %p, i64 -16384
   %load = load volatile i8, ptr %gep, align 1
   store i8 %load, ptr poison
@@ -2702,29 +4146,53 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_11bit_split0(ptr %p) {
 ; GFX10-NEXT:    flat_store_byte v[0:1], v0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: flat_inst_salu_offset_64bit_11bit_split0:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, s0, 0, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:2047 glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-SDAG-LABEL: flat_inst_salu_offset_64bit_11bit_split0:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xf1ff
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
-; GFX12-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:2047 scope:SCOPE_SYS
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX12-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_salu_offset_64bit_11bit_split0:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:2047 glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_salu_offset_64bit_11bit_split0:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:2047 glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_salu_offset_64bit_11bit_split0:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:2047 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_salu_offset_64bit_11bit_split0:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:2047 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX9-GISEL-LABEL: flat_inst_salu_offset_64bit_11bit_split0:
 ; GFX9-GISEL:       ; %bb.0:
@@ -2797,29 +4265,53 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_11bit_split1(ptr %p) {
 ; GFX10-NEXT:    flat_store_byte v[0:1], v0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: flat_inst_salu_offset_64bit_11bit_split1:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, s0, 0, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:2048 glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-SDAG-LABEL: flat_inst_salu_offset_64bit_11bit_split1:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xf1ff
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
-; GFX12-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:2048 scope:SCOPE_SYS
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX12-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_salu_offset_64bit_11bit_split1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:2048 glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_salu_offset_64bit_11bit_split1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:2048 glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_salu_offset_64bit_11bit_split1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:2048 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_salu_offset_64bit_11bit_split1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:2048 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX9-GISEL-LABEL: flat_inst_salu_offset_64bit_11bit_split1:
 ; GFX9-GISEL:       ; %bb.0:
@@ -2892,29 +4384,53 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_12bit_split0(ptr %p) {
 ; GFX10-NEXT:    flat_store_byte v[0:1], v0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: flat_inst_salu_offset_64bit_12bit_split0:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, s0, 0, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:4095 glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-SDAG-LABEL: flat_inst_salu_offset_64bit_12bit_split0:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xf1ff
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
-; GFX12-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:4095 scope:SCOPE_SYS
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX12-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_salu_offset_64bit_12bit_split0:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:4095 glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_salu_offset_64bit_12bit_split0:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:4095 glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_salu_offset_64bit_12bit_split0:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:4095 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_salu_offset_64bit_12bit_split0:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:4095 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX9-GISEL-LABEL: flat_inst_salu_offset_64bit_12bit_split0:
 ; GFX9-GISEL:       ; %bb.0:
@@ -2988,29 +4504,53 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_12bit_split1(ptr %p) {
 ; GFX10-NEXT:    flat_store_byte v[0:1], v0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: flat_inst_salu_offset_64bit_12bit_split1:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, s0, 0x1000, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-SDAG-LABEL: flat_inst_salu_offset_64bit_12bit_split1:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xf1ff
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
-; GFX12-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:4096 scope:SCOPE_SYS
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX12-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_salu_offset_64bit_12bit_split1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0x1000, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_salu_offset_64bit_12bit_split1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0x1000, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_salu_offset_64bit_12bit_split1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:4096 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_salu_offset_64bit_12bit_split1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:4096 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX9-GISEL-LABEL: flat_inst_salu_offset_64bit_12bit_split1:
 ; GFX9-GISEL:       ; %bb.0:
@@ -3084,29 +4624,53 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_13bit_split0(ptr %p) {
 ; GFX10-NEXT:    flat_store_byte v[0:1], v0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: flat_inst_salu_offset_64bit_13bit_split0:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, s0, 0x1000, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:4095 glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-SDAG-LABEL: flat_inst_salu_offset_64bit_13bit_split0:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xf1ff
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
-; GFX12-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:8191 scope:SCOPE_SYS
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX12-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_salu_offset_64bit_13bit_split0:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0x1000, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:4095 glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_salu_offset_64bit_13bit_split0:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0x1000, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:4095 glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_salu_offset_64bit_13bit_split0:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:8191 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_salu_offset_64bit_13bit_split0:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:8191 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX9-GISEL-LABEL: flat_inst_salu_offset_64bit_13bit_split0:
 ; GFX9-GISEL:       ; %bb.0:
@@ -3180,29 +4744,53 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_13bit_split1(ptr %p) {
 ; GFX10-NEXT:    flat_store_byte v[0:1], v0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: flat_inst_salu_offset_64bit_13bit_split1:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, s0, 0x2000, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-SDAG-LABEL: flat_inst_salu_offset_64bit_13bit_split1:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xf1ff
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
-; GFX12-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:8192 scope:SCOPE_SYS
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX12-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_salu_offset_64bit_13bit_split1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0x2000, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_salu_offset_64bit_13bit_split1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0x2000, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_salu_offset_64bit_13bit_split1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:8192 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_salu_offset_64bit_13bit_split1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:8192 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX9-GISEL-LABEL: flat_inst_salu_offset_64bit_13bit_split1:
 ; GFX9-GISEL:       ; %bb.0:
@@ -3277,31 +4865,57 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_11bit_neg_high_split0(ptr
 ; GFX10-NEXT:    flat_store_byte v[0:1], v0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split0:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v1, s1
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x7ff, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-SDAG-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split0:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_mov_b32_e32 v1, s1
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, s0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX12-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:-8386561 scope:SCOPE_SYS
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX12-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split0:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v1, s1
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x7ff, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split0:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, s1
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x7ff, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split0:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v1, s1
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, s0
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:-8386561 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split0:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, s1
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, s0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:-8386561 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX9-GISEL-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split0:
 ; GFX9-GISEL:       ; %bb.0:
@@ -3376,31 +4990,57 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_11bit_neg_high_split1(ptr
 ; GFX10-NEXT:    flat_store_byte v[0:1], v0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split1:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v1, s1
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-SDAG-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split1:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_mov_b32_e32 v1, s1
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, s0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX12-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:-8386560 scope:SCOPE_SYS
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX12-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v1, s1
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, s1
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v1, s1
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, s0
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:-8386560 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, s1
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, s0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:-8386560 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX9-GISEL-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split1:
 ; GFX9-GISEL:       ; %bb.0:
@@ -3475,31 +5115,57 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_12bit_neg_high_split0(ptr
 ; GFX10-NEXT:    flat_store_byte v[0:1], v0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split0:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v1, s1
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfff, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-SDAG-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split0:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_mov_b32_e32 v1, s1
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, s0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX12-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:-8384513 scope:SCOPE_SYS
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX12-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split0:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v1, s1
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfff, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split0:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, s1
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfff, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split0:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v1, s1
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, s0
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:-8384513 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split0:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, s1
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, s0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:-8384513 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX9-GISEL-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split0:
 ; GFX9-GISEL:       ; %bb.0:
@@ -3574,31 +5240,57 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_12bit_neg_high_split1(ptr
 ; GFX10-NEXT:    flat_store_byte v[0:1], v0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split1:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v1, s1
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-SDAG-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split1:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_mov_b32_e32 v1, s1
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, s0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX12-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:-8384512 scope:SCOPE_SYS
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX12-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v1, s1
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, s1
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v1, s1
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, s0
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:-8384512 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, s1
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, s0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:-8384512 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX9-GISEL-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split1:
 ; GFX9-GISEL:       ; %bb.0:
@@ -3673,31 +5365,57 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_13bit_neg_high_split0(ptr
 ; GFX10-NEXT:    flat_store_byte v[0:1], v0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split0:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v1, s1
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1fff, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-SDAG-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split0:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_mov_b32_e32 v1, s1
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, s0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX12-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:-8380417 scope:SCOPE_SYS
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX12-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split0:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v1, s1
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1fff, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split0:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, s1
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1fff, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split0:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v1, s1
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, s0
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:-8380417 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split0:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, s1
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, s0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:-8380417 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX9-GISEL-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split0:
 ; GFX9-GISEL:       ; %bb.0:
@@ -3772,31 +5490,57 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_13bit_neg_high_split1(ptr
 ; GFX10-NEXT:    flat_store_byte v[0:1], v0
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split1:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mov_b32_e32 v1, s1
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX11-SDAG-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-SDAG-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split1:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_mov_b32_e32 v1, s1
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, s0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX12-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:-8380416 scope:SCOPE_SYS
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    flat_store_b8 v[0:1], v0
-; GFX12-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v1, s1
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, s1
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v1, s1
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, s0
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1] offset:-8380416 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, s1
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, s0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    flat_load_u8 v0, v[0:1] offset:-8380416 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    flat_store_b8 v[0:1], v0
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX9-GISEL-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split1:
 ; GFX9-GISEL:       ; %bb.0:
@@ -3844,3 +5588,11 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_13bit_neg_high_split1(ptr
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; GFX10-GISEL: {{.*}}
 ; GFX10-SDAG: {{.*}}
+; GFX11: {{.*}}
+; GFX11-GISEL-FAKE16: {{.*}}
+; GFX11-GISEL-TRUE16: {{.*}}
+; GFX11-SDAG: {{.*}}
+; GFX12: {{.*}}
+; GFX12-GISEL-FAKE16: {{.*}}
+; GFX12-GISEL-TRUE16: {{.*}}
+; GFX12-SDAG: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/offset-split-global.ll b/llvm/test/CodeGen/AMDGPU/offset-split-global.ll
index e426bc73af66d..de5f4f931070e 100644
--- a/llvm/test/CodeGen/AMDGPU/offset-split-global.ll
+++ b/llvm/test/CodeGen/AMDGPU/offset-split-global.ll
@@ -1,12 +1,16 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
 
 ; Test splitting flat instruction offsets into the low and high bits
 ; when the offset doesn't fit in the offset field.
@@ -26,23 +30,59 @@ define i8 @global_inst_valu_offset_1(ptr addrspace(1) %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: global_inst_valu_offset_1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_u8 v0, v[0:1], off offset:1
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: global_inst_valu_offset_1:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v[0:1], off offset:1
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-GISEL-LABEL: global_inst_valu_offset_1:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v[0:1], off offset:1
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: global_inst_valu_offset_1:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v[0:1], off offset:1
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:1
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:1
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:1
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:1
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 1
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -63,23 +103,59 @@ define i8 @global_inst_valu_offset_11bit_max(ptr addrspace(1) %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: global_inst_valu_offset_11bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_u8 v0, v[0:1], off offset:2047
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: global_inst_valu_offset_11bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v[0:1], off offset:2047
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-GISEL-LABEL: global_inst_valu_offset_11bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v[0:1], off offset:2047
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: global_inst_valu_offset_11bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v[0:1], off offset:2047
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_11bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:2047
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_11bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:2047
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_11bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:2047
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_11bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:2047
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 2047
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -102,23 +178,23 @@ define i8 @global_inst_valu_offset_12bit_max(ptr addrspace(1) %p) {
 ; GFX10-GISEL-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: global_inst_valu_offset_12bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_u8 v0, v[0:1], off offset:4095
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: global_inst_valu_offset_12bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v[0:1], off offset:4095
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-GISEL-LABEL: global_inst_valu_offset_12bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v[0:1], off offset:4095
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: global_inst_valu_offset_12bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v[0:1], off offset:4095
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-SDAG-LABEL: global_inst_valu_offset_12bit_max:
 ; GFX10-SDAG:       ; %bb.0:
@@ -128,6 +204,42 @@ define i8 @global_inst_valu_offset_12bit_max(ptr addrspace(1) %p) {
 ; GFX10-SDAG-NEXT:    global_load_ubyte v0, v[0:1], off offset:2047
 ; GFX10-SDAG-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_12bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:4095
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_12bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:4095
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_12bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:4095
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_12bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:4095
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 4095
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -162,16 +274,16 @@ define i8 @global_inst_valu_offset_13bit_max(ptr addrspace(1) %p) {
 ; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: global_inst_valu_offset_13bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v[0:1], off offset:8191
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-GISEL-LABEL: global_inst_valu_offset_13bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v[0:1], off offset:8191
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-SDAG-LABEL: global_inst_valu_offset_13bit_max:
 ; GFX9-SDAG:       ; %bb.0:
@@ -191,15 +303,47 @@ define i8 @global_inst_valu_offset_13bit_max(ptr addrspace(1) %p) {
 ; GFX10-SDAG-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: global_inst_valu_offset_13bit_max:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:4095
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_13bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:4095
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_13bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:4095
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_13bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:8191
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_13bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:8191
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 8191
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -234,16 +378,16 @@ define i8 @global_inst_valu_offset_24bit_max(ptr addrspace(1) %p) {
 ; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: global_inst_valu_offset_24bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v[0:1], off offset:8388607
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-GISEL-LABEL: global_inst_valu_offset_24bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v[0:1], off offset:8388607
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-SDAG-LABEL: global_inst_valu_offset_24bit_max:
 ; GFX9-SDAG:       ; %bb.0:
@@ -263,15 +407,47 @@ define i8 @global_inst_valu_offset_24bit_max(ptr addrspace(1) %p) {
 ; GFX10-SDAG-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: global_inst_valu_offset_24bit_max:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x7ff000, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:4095
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_24bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x7ff000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:4095
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_24bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x7ff000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:4095
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_24bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:8388607
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_24bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:8388607
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 8388607
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -292,23 +468,59 @@ define i8 @global_inst_valu_offset_neg_11bit_max(ptr addrspace(1) %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: global_inst_valu_offset_neg_11bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_u8 v0, v[0:1], off offset:-2048
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: global_inst_valu_offset_neg_11bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v[0:1], off offset:-2048
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-GISEL-LABEL: global_inst_valu_offset_neg_11bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v[0:1], off offset:-2048
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: global_inst_valu_offset_neg_11bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v[0:1], off offset:-2048
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_neg_11bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:-2048
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_neg_11bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:-2048
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_neg_11bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:-2048
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_neg_11bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:-2048
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 -2048
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -331,23 +543,59 @@ define i8 @global_inst_valu_offset_neg_12bit_max(ptr addrspace(1) %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: global_inst_valu_offset_neg_12bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_u8 v0, v[0:1], off offset:-4096
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: global_inst_valu_offset_neg_12bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v[0:1], off offset:-4096
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-GISEL-LABEL: global_inst_valu_offset_neg_12bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v[0:1], off offset:-4096
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: global_inst_valu_offset_neg_12bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v[0:1], off offset:-4096
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_neg_12bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:-4096
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_neg_12bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:-4096
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_neg_12bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:-4096
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_neg_12bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:-4096
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 -4096
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -372,26 +620,68 @@ define i8 @global_inst_valu_offset_neg_13bit_max(ptr addrspace(1) %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: global_inst_valu_offset_neg_13bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffe000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX11-NEXT:    global_load_u8 v0, v[0:1], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: global_inst_valu_offset_neg_13bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v[0:1], off offset:-8192
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-GISEL-LABEL: global_inst_valu_offset_neg_13bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffe000, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v[0:1], off
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: global_inst_valu_offset_neg_13bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v[0:1], off offset:-8192
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_neg_13bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffe000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_neg_13bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffe000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_neg_13bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:-8192
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_neg_13bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:-8192
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 -8192
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -416,26 +706,68 @@ define i8 @global_inst_valu_offset_neg_24bit_max(ptr addrspace(1) %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: global_inst_valu_offset_neg_24bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, 0xff800000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX11-NEXT:    global_load_u8 v0, v[0:1], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: global_inst_valu_offset_neg_24bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v[0:1], off offset:-8388608
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-GISEL-LABEL: global_inst_valu_offset_neg_24bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0xff800000, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v[0:1], off
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: global_inst_valu_offset_neg_24bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v[0:1], off offset:-8388608
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_neg_24bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xff800000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_neg_24bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xff800000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_neg_24bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:-8388608
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_neg_24bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:-8388608
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 -8388608
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -458,23 +790,23 @@ define i8 @global_inst_valu_offset_2x_11bit_max(ptr addrspace(1) %p) {
 ; GFX10-GISEL-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: global_inst_valu_offset_2x_11bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_u8 v0, v[0:1], off offset:4095
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: global_inst_valu_offset_2x_11bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v[0:1], off offset:4095
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-GISEL-LABEL: global_inst_valu_offset_2x_11bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v[0:1], off offset:4095
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: global_inst_valu_offset_2x_11bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v[0:1], off offset:4095
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-SDAG-LABEL: global_inst_valu_offset_2x_11bit_max:
 ; GFX10-SDAG:       ; %bb.0:
@@ -484,6 +816,42 @@ define i8 @global_inst_valu_offset_2x_11bit_max(ptr addrspace(1) %p) {
 ; GFX10-SDAG-NEXT:    global_load_ubyte v0, v[0:1], off offset:2047
 ; GFX10-SDAG-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_2x_11bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:4095
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_2x_11bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:4095
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_2x_11bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:4095
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_2x_11bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:4095
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 4095
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -518,16 +886,16 @@ define i8 @global_inst_valu_offset_2x_12bit_max(ptr addrspace(1) %p) {
 ; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: global_inst_valu_offset_2x_12bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v[0:1], off offset:8191
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-GISEL-LABEL: global_inst_valu_offset_2x_12bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v[0:1], off offset:8191
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-SDAG-LABEL: global_inst_valu_offset_2x_12bit_max:
 ; GFX9-SDAG:       ; %bb.0:
@@ -547,15 +915,47 @@ define i8 @global_inst_valu_offset_2x_12bit_max(ptr addrspace(1) %p) {
 ; GFX10-SDAG-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: global_inst_valu_offset_2x_12bit_max:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:4095
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_2x_12bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:4095
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_2x_12bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:4095
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_2x_12bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:8191
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_2x_12bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:8191
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 8191
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -590,16 +990,16 @@ define i8 @global_inst_valu_offset_2x_13bit_max(ptr addrspace(1) %p) {
 ; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: global_inst_valu_offset_2x_13bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v[0:1], off offset:16383
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-GISEL-LABEL: global_inst_valu_offset_2x_13bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v[0:1], off offset:16383
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-SDAG-LABEL: global_inst_valu_offset_2x_13bit_max:
 ; GFX9-SDAG:       ; %bb.0:
@@ -619,15 +1019,47 @@ define i8 @global_inst_valu_offset_2x_13bit_max(ptr addrspace(1) %p) {
 ; GFX10-SDAG-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: global_inst_valu_offset_2x_13bit_max:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x3000, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:4095
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_2x_13bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x3000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:4095
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_2x_13bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x3000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:4095
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_2x_13bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:16383
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_2x_13bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:16383
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 16383
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -694,29 +1126,53 @@ define i8 @global_inst_valu_offset_2x_24bit_max(ptr addrspace(1) %p) {
 ; GFX10-SDAG-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: global_inst_valu_offset_2x_24bit_max:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfff000, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:4094
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: global_inst_valu_offset_2x_24bit_max:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX12-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:8388606
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_2x_24bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfff000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:4094
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_2x_24bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfff000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:4094
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_2x_24bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:8388606
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_2x_24bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:8388606
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 16777214
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -739,23 +1195,59 @@ define i8 @global_inst_valu_offset_2x_neg_11bit_max(ptr addrspace(1) %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: global_inst_valu_offset_2x_neg_11bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_u8 v0, v[0:1], off offset:-4096
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: global_inst_valu_offset_2x_neg_11bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v[0:1], off offset:-4096
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-GISEL-LABEL: global_inst_valu_offset_2x_neg_11bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v[0:1], off offset:-4096
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: global_inst_valu_offset_2x_neg_11bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v[0:1], off offset:-4096
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_2x_neg_11bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:-4096
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_2x_neg_11bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:-4096
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_2x_neg_11bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:-4096
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_2x_neg_11bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:-4096
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 -4096
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -780,26 +1272,68 @@ define i8 @global_inst_valu_offset_2x_neg_12bit_max(ptr addrspace(1) %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: global_inst_valu_offset_2x_neg_12bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffe000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX11-NEXT:    global_load_u8 v0, v[0:1], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: global_inst_valu_offset_2x_neg_12bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v[0:1], off offset:-8192
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-GISEL-LABEL: global_inst_valu_offset_2x_neg_12bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffe000, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v[0:1], off
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: global_inst_valu_offset_2x_neg_12bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v[0:1], off offset:-8192
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_2x_neg_12bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffe000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_2x_neg_12bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffe000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_2x_neg_12bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:-8192
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_2x_neg_12bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:-8192
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 -8192
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -824,26 +1358,68 @@ define i8 @global_inst_valu_offset_2x_neg_13bit_max(ptr addrspace(1) %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: global_inst_valu_offset_2x_neg_13bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffc000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX11-NEXT:    global_load_u8 v0, v[0:1], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: global_inst_valu_offset_2x_neg_13bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v[0:1], off offset:-16384
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-GISEL-LABEL: global_inst_valu_offset_2x_neg_13bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffc000, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v[0:1], off
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: global_inst_valu_offset_2x_neg_13bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v[0:1], off offset:-16384
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_2x_neg_13bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffc000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_2x_neg_13bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffc000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_2x_neg_13bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:-16384
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_2x_neg_13bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:-16384
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 -16384
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -910,29 +1486,53 @@ define i8 @global_inst_valu_offset_2x_neg_24bit_max(ptr addrspace(1) %p) {
 ; GFX10-SDAG-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: global_inst_valu_offset_2x_neg_24bit_max:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0xff001000, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX11-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:-4095
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: global_inst_valu_offset_2x_neg_24bit_max:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0xff800000, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX12-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:-8388607
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_2x_neg_24bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xff001000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:-4095
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_2x_neg_24bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xff001000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:-4095
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_2x_neg_24bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xff800000, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:-8388607
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_2x_neg_24bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0xff800000, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:-8388607
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 -16777215
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -1001,29 +1601,53 @@ define i8 @global_inst_valu_offset_64bit_11bit_split0(ptr addrspace(1) %p) {
 ; GFX10-SDAG-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: global_inst_valu_offset_64bit_11bit_split0:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
-; GFX11-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:2047
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: global_inst_valu_offset_64bit_11bit_split0:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
-; GFX12-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:2047
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_64bit_11bit_split0:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:2047
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_64bit_11bit_split0:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:2047
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_64bit_11bit_split0:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:2047
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_64bit_11bit_split0:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:2047
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 8589936639
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -1082,29 +1706,53 @@ define i8 @global_inst_valu_offset_64bit_11bit_split1(ptr addrspace(1) %p) {
 ; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: global_inst_valu_offset_64bit_11bit_split1:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
-; GFX11-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:2048
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: global_inst_valu_offset_64bit_11bit_split1:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
-; GFX12-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:2048
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_64bit_11bit_split1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:2048
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_64bit_11bit_split1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:2048
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_64bit_11bit_split1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:2048
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_64bit_11bit_split1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:2048
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 8589936640
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -1172,29 +1820,53 @@ define i8 @global_inst_valu_offset_64bit_12bit_split0(ptr addrspace(1) %p) {
 ; GFX10-SDAG-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: global_inst_valu_offset_64bit_12bit_split0:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
-; GFX11-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:4095
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: global_inst_valu_offset_64bit_12bit_split0:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
-; GFX12-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:4095
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_64bit_12bit_split0:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:4095
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_64bit_12bit_split0:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:4095
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_64bit_12bit_split0:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:4095
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_64bit_12bit_split0:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:4095
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 8589938687
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -1220,15 +1892,15 @@ define i8 @global_inst_valu_offset_64bit_12bit_split1(ptr addrspace(1) %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: global_inst_valu_offset_64bit_12bit_split1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
-; GFX11-NEXT:    global_load_u8 v0, v[0:1], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-GISEL-LABEL: global_inst_valu_offset_64bit_12bit_split1:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v[0:1], off
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: global_inst_valu_offset_64bit_12bit_split1:
 ; GFX12-GISEL:       ; %bb.0:
@@ -1244,19 +1916,53 @@ define i8 @global_inst_valu_offset_64bit_12bit_split1(ptr addrspace(1) %p) {
 ; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
 ; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: global_inst_valu_offset_64bit_12bit_split1:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
-; GFX12-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:4096
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_64bit_12bit_split1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_64bit_12bit_split1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_64bit_12bit_split1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:4096
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_64bit_12bit_split1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:4096
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 8589938688
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -1324,29 +2030,53 @@ define i8 @global_inst_valu_offset_64bit_13bit_split0(ptr addrspace(1) %p) {
 ; GFX10-SDAG-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: global_inst_valu_offset_64bit_13bit_split0:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
-; GFX11-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:4095
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: global_inst_valu_offset_64bit_13bit_split0:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
-; GFX12-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:8191
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_64bit_13bit_split0:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:4095
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_64bit_13bit_split0:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:4095
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_64bit_13bit_split0:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:8191
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_64bit_13bit_split0:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:8191
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 8589942783
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -1372,15 +2102,15 @@ define i8 @global_inst_valu_offset_64bit_13bit_split1(ptr addrspace(1) %p) {
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: global_inst_valu_offset_64bit_13bit_split1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
-; GFX11-NEXT:    global_load_u8 v0, v[0:1], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-GISEL-LABEL: global_inst_valu_offset_64bit_13bit_split1:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v[0:1], off
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: global_inst_valu_offset_64bit_13bit_split1:
 ; GFX12-GISEL:       ; %bb.0:
@@ -1396,19 +2126,53 @@ define i8 @global_inst_valu_offset_64bit_13bit_split1(ptr addrspace(1) %p) {
 ; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
 ; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: global_inst_valu_offset_64bit_13bit_split1:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
-; GFX12-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:8192
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_64bit_13bit_split1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_64bit_13bit_split1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_64bit_13bit_split1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:8192
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_64bit_13bit_split1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:8192
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 8589942784
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -1478,29 +2242,53 @@ define i8 @global_inst_valu_offset_64bit_11bit_neg_high_split0(ptr addrspace(1)
 ; GFX10-SDAG-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split0:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX11-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:-2049
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split0:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX12-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:-8386561
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split0:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:-2049
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split0:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:-2049
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split0:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:-8386561
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split0:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:-8386561
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 -9223372036854773761
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -1561,29 +2349,53 @@ define i8 @global_inst_valu_offset_64bit_11bit_neg_high_split1(ptr addrspace(1)
 ; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split1:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX11-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:-2048
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split1:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX12-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:-8386560
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:-2048
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:-2048
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:-8386560
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:-8386560
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 -9223372036854773760
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -1653,29 +2465,53 @@ define i8 @global_inst_valu_offset_64bit_12bit_neg_high_split0(ptr addrspace(1)
 ; GFX10-SDAG-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split0:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX11-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:-1
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split0:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX12-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:-8384513
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split0:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:-1
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split0:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:-1
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split0:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:-8384513
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split0:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:-8384513
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 -9223372036854771713
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -1702,15 +2538,15 @@ define i8 @global_inst_valu_offset_64bit_12bit_neg_high_split1(ptr addrspace(1)
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX11-NEXT:    global_load_u8 v0, v[0:1], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-GISEL-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split1:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v[0:1], off
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split1:
 ; GFX12-GISEL:       ; %bb.0:
@@ -1736,19 +2572,53 @@ define i8 @global_inst_valu_offset_64bit_12bit_neg_high_split1(ptr addrspace(1)
 ; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split1:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX12-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:-8384512
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:-8384512
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:-8384512
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 -9223372036854771712
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -1818,29 +2688,53 @@ define i8 @global_inst_valu_offset_64bit_13bit_neg_high_split0(ptr addrspace(1)
 ; GFX10-SDAG-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split0:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX11-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:-1
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split0:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX12-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:-8380417
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split0:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:-1
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split0:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:-1
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split0:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:-8380417
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split0:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:-8380417
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 -9223372036854767617
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -1867,15 +2761,15 @@ define i8 @global_inst_valu_offset_64bit_13bit_neg_high_split1(ptr addrspace(1)
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX11-NEXT:    global_load_u8 v0, v[0:1], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-GISEL-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split1:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v[0:1], off
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split1:
 ; GFX12-GISEL:       ; %bb.0:
@@ -1901,19 +2795,53 @@ define i8 @global_inst_valu_offset_64bit_13bit_neg_high_split1(ptr addrspace(1)
 ; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split1:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffd
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
-; GFX12-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:-8380416
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:-8380416
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:-8380416
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 -9223372036854767616
   %load = load i8, ptr addrspace(1) %gep, align 4
   ret i8 %load
@@ -1940,25 +2868,65 @@ define amdgpu_kernel void @global_inst_salu_offset_1(ptr addrspace(1) %p) {
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_inst_salu_offset_1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u8 v0, v0, s[0:1] offset:1 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-NEXT:    s_endpgm
-;
-; GFX12-LABEL: global_inst_salu_offset_1:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v0, s[0:1] offset:1 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX12-NEXT:    s_endpgm
+; GFX11-GISEL-LABEL: global_inst_salu_offset_1:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] offset:1 glc dlc
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-GISEL-NEXT:    s_endpgm
+;
+; GFX12-GISEL-LABEL: global_inst_salu_offset_1:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] offset:1 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-GISEL-NEXT:    s_endpgm
+;
+; GFX11-SDAG-TRUE16-LABEL: global_inst_salu_offset_1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] offset:1 glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_salu_offset_1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] offset:1 glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_salu_offset_1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] offset:1 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_salu_offset_1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] offset:1 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 1
   %load = load volatile i8, ptr addrspace(1) %gep, align 1
   store i8 %load, ptr addrspace(1) poison
@@ -1986,25 +2954,65 @@ define amdgpu_kernel void @global_inst_salu_offset_11bit_max(ptr addrspace(1) %p
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_inst_salu_offset_11bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u8 v0, v0, s[0:1] offset:2047 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-NEXT:    s_endpgm
-;
-; GFX12-LABEL: global_inst_salu_offset_11bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v0, s[0:1] offset:2047 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX12-NEXT:    s_endpgm
+; GFX11-GISEL-LABEL: global_inst_salu_offset_11bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] offset:2047 glc dlc
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-GISEL-NEXT:    s_endpgm
+;
+; GFX12-GISEL-LABEL: global_inst_salu_offset_11bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] offset:2047 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-GISEL-NEXT:    s_endpgm
+;
+; GFX11-SDAG-TRUE16-LABEL: global_inst_salu_offset_11bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] offset:2047 glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_salu_offset_11bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] offset:2047 glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_salu_offset_11bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] offset:2047 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_salu_offset_11bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] offset:2047 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 2047
   %load = load volatile i8, ptr addrspace(1) %gep, align 1
   store i8 %load, ptr addrspace(1) poison
@@ -2032,25 +3040,65 @@ define amdgpu_kernel void @global_inst_salu_offset_12bit_max(ptr addrspace(1) %p
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_inst_salu_offset_12bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u8 v0, v0, s[0:1] offset:4095 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-NEXT:    s_endpgm
-;
-; GFX12-LABEL: global_inst_salu_offset_12bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v0, s[0:1] offset:4095 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX12-NEXT:    s_endpgm
+; GFX11-GISEL-LABEL: global_inst_salu_offset_12bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] offset:4095 glc dlc
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-GISEL-NEXT:    s_endpgm
+;
+; GFX12-GISEL-LABEL: global_inst_salu_offset_12bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] offset:4095 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-GISEL-NEXT:    s_endpgm
+;
+; GFX11-SDAG-TRUE16-LABEL: global_inst_salu_offset_12bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] offset:4095 glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_salu_offset_12bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] offset:4095 glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_salu_offset_12bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] offset:4095 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_salu_offset_12bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] offset:4095 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 4095
   %load = load volatile i8, ptr addrspace(1) %gep, align 1
   store i8 %load, ptr addrspace(1) poison
@@ -2078,25 +3126,65 @@ define amdgpu_kernel void @global_inst_salu_offset_13bit_max(ptr addrspace(1) %p
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_inst_salu_offset_13bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0x1000
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u8 v0, v0, s[0:1] offset:4095 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-NEXT:    s_endpgm
-;
-; GFX12-LABEL: global_inst_salu_offset_13bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v0, s[0:1] offset:8191 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX12-NEXT:    s_endpgm
+; GFX11-GISEL-LABEL: global_inst_salu_offset_13bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT:    v_mov_b32_e32 v0, 0x1000
+; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] offset:4095 glc dlc
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-GISEL-NEXT:    s_endpgm
+;
+; GFX12-GISEL-LABEL: global_inst_salu_offset_13bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] offset:8191 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-GISEL-NEXT:    s_endpgm
+;
+; GFX11-SDAG-TRUE16-LABEL: global_inst_salu_offset_13bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0x1000
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] offset:4095 glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_salu_offset_13bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0x1000
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] offset:4095 glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_salu_offset_13bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] offset:8191 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_salu_offset_13bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] offset:8191 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 8191
   %load = load volatile i8, ptr addrspace(1) %gep, align 1
   store i8 %load, ptr addrspace(1) poison
@@ -2124,25 +3212,65 @@ define amdgpu_kernel void @global_inst_salu_offset_neg_11bit_max(ptr addrspace(1
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_inst_salu_offset_neg_11bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-2048 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-NEXT:    s_endpgm
-;
-; GFX12-LABEL: global_inst_salu_offset_neg_11bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-2048 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX12-NEXT:    s_endpgm
+; GFX11-GISEL-LABEL: global_inst_salu_offset_neg_11bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-2048 glc dlc
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-GISEL-NEXT:    s_endpgm
+;
+; GFX12-GISEL-LABEL: global_inst_salu_offset_neg_11bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-2048 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-GISEL-NEXT:    s_endpgm
+;
+; GFX11-SDAG-TRUE16-LABEL: global_inst_salu_offset_neg_11bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] offset:-2048 glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_salu_offset_neg_11bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-2048 glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_salu_offset_neg_11bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] offset:-2048 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_salu_offset_neg_11bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-2048 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 -2048
   %load = load volatile i8, ptr addrspace(1) %gep, align 1
   store i8 %load, ptr addrspace(1) poison
@@ -2173,25 +3301,25 @@ define amdgpu_kernel void @global_inst_salu_offset_neg_12bit_max(ptr addrspace(1
 ; GFX10-GISEL-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-GISEL-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_inst_salu_offset_neg_12bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-4096 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-NEXT:    s_endpgm
-;
-; GFX12-LABEL: global_inst_salu_offset_neg_12bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-4096 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX12-NEXT:    s_endpgm
+; GFX11-GISEL-LABEL: global_inst_salu_offset_neg_12bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-4096 glc dlc
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-GISEL-NEXT:    s_endpgm
+;
+; GFX12-GISEL-LABEL: global_inst_salu_offset_neg_12bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-4096 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-GISEL-NEXT:    s_endpgm
 ;
 ; GFX10-SDAG-LABEL: global_inst_salu_offset_neg_12bit_max:
 ; GFX10-SDAG:       ; %bb.0:
@@ -2203,6 +3331,46 @@ define amdgpu_kernel void @global_inst_salu_offset_neg_12bit_max(ptr addrspace(1
 ; GFX10-SDAG-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-SDAG-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-SDAG-NEXT:    s_endpgm
+;
+; GFX11-SDAG-TRUE16-LABEL: global_inst_salu_offset_neg_12bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] offset:-4096 glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_salu_offset_neg_12bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-4096 glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_salu_offset_neg_12bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] offset:-4096 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_salu_offset_neg_12bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-4096 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 -4096
   %load = load volatile i8, ptr addrspace(1) %gep, align 1
   store i8 %load, ptr addrspace(1) poison
@@ -2248,15 +3416,15 @@ define amdgpu_kernel void @global_inst_salu_offset_neg_13bit_max(ptr addrspace(1
 ; GFX11-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
 ; GFX11-GISEL-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: global_inst_salu_offset_neg_13bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-8192 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX12-NEXT:    s_endpgm
+; GFX12-GISEL-LABEL: global_inst_salu_offset_neg_13bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-8192 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-GISEL-NEXT:    s_endpgm
 ;
 ; GFX10-SDAG-LABEL: global_inst_salu_offset_neg_13bit_max:
 ; GFX10-SDAG:       ; %bb.0:
@@ -2269,17 +3437,49 @@ define amdgpu_kernel void @global_inst_salu_offset_neg_13bit_max(ptr addrspace(1
 ; GFX10-SDAG-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-SDAG-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: global_inst_salu_offset_neg_13bit_max:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, s0, 0xffffe000, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
-; GFX11-SDAG-NEXT:    global_load_u8 v0, v[0:1], off glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: global_inst_salu_offset_neg_13bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0xffffe000, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_salu_offset_neg_13bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0xffffe000, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_salu_offset_neg_13bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] offset:-8192 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_salu_offset_neg_13bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-8192 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 -8192
   %load = load volatile i8, ptr addrspace(1) %gep, align 1
   store i8 %load, ptr addrspace(1) poison
@@ -2307,25 +3507,65 @@ define amdgpu_kernel void @global_inst_salu_offset_2x_11bit_max(ptr addrspace(1)
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_inst_salu_offset_2x_11bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u8 v0, v0, s[0:1] offset:4095 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-NEXT:    s_endpgm
-;
-; GFX12-LABEL: global_inst_salu_offset_2x_11bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v0, s[0:1] offset:4095 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX12-NEXT:    s_endpgm
+; GFX11-GISEL-LABEL: global_inst_salu_offset_2x_11bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] offset:4095 glc dlc
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-GISEL-NEXT:    s_endpgm
+;
+; GFX12-GISEL-LABEL: global_inst_salu_offset_2x_11bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] offset:4095 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-GISEL-NEXT:    s_endpgm
+;
+; GFX11-SDAG-TRUE16-LABEL: global_inst_salu_offset_2x_11bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] offset:4095 glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_salu_offset_2x_11bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] offset:4095 glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_salu_offset_2x_11bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] offset:4095 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_salu_offset_2x_11bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] offset:4095 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 4095
   %load = load volatile i8, ptr addrspace(1) %gep, align 1
   store i8 %load, ptr addrspace(1) poison
@@ -2353,25 +3593,65 @@ define amdgpu_kernel void @global_inst_salu_offset_2x_12bit_max(ptr addrspace(1)
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_inst_salu_offset_2x_12bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0x1000
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u8 v0, v0, s[0:1] offset:4095 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-NEXT:    s_endpgm
-;
-; GFX12-LABEL: global_inst_salu_offset_2x_12bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v0, s[0:1] offset:8191 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX12-NEXT:    s_endpgm
+; GFX11-GISEL-LABEL: global_inst_salu_offset_2x_12bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT:    v_mov_b32_e32 v0, 0x1000
+; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] offset:4095 glc dlc
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-GISEL-NEXT:    s_endpgm
+;
+; GFX12-GISEL-LABEL: global_inst_salu_offset_2x_12bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] offset:8191 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-GISEL-NEXT:    s_endpgm
+;
+; GFX11-SDAG-TRUE16-LABEL: global_inst_salu_offset_2x_12bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0x1000
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] offset:4095 glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_salu_offset_2x_12bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0x1000
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] offset:4095 glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_salu_offset_2x_12bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] offset:8191 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_salu_offset_2x_12bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] offset:8191 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 8191
   %load = load volatile i8, ptr addrspace(1) %gep, align 1
   store i8 %load, ptr addrspace(1) poison
@@ -2399,25 +3679,65 @@ define amdgpu_kernel void @global_inst_salu_offset_2x_13bit_max(ptr addrspace(1)
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_inst_salu_offset_2x_13bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0x3000
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u8 v0, v0, s[0:1] offset:4095 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-NEXT:    s_endpgm
-;
-; GFX12-LABEL: global_inst_salu_offset_2x_13bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v0, s[0:1] offset:16383 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX12-NEXT:    s_endpgm
+; GFX11-GISEL-LABEL: global_inst_salu_offset_2x_13bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT:    v_mov_b32_e32 v0, 0x3000
+; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] offset:4095 glc dlc
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-GISEL-NEXT:    s_endpgm
+;
+; GFX12-GISEL-LABEL: global_inst_salu_offset_2x_13bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] offset:16383 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-GISEL-NEXT:    s_endpgm
+;
+; GFX11-SDAG-TRUE16-LABEL: global_inst_salu_offset_2x_13bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0x3000
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] offset:4095 glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_salu_offset_2x_13bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0x3000
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] offset:4095 glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_salu_offset_2x_13bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] offset:16383 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_salu_offset_2x_13bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] offset:16383 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 16383
   %load = load volatile i8, ptr addrspace(1) %gep, align 1
   store i8 %load, ptr addrspace(1) poison
@@ -2448,25 +3768,25 @@ define amdgpu_kernel void @global_inst_salu_offset_2x_neg_11bit_max(ptr addrspac
 ; GFX10-GISEL-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-GISEL-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_inst_salu_offset_2x_neg_11bit_max:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-4096 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-NEXT:    s_endpgm
-;
-; GFX12-LABEL: global_inst_salu_offset_2x_neg_11bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-4096 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX12-NEXT:    s_endpgm
+; GFX11-GISEL-LABEL: global_inst_salu_offset_2x_neg_11bit_max:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-4096 glc dlc
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-GISEL-NEXT:    s_endpgm
+;
+; GFX12-GISEL-LABEL: global_inst_salu_offset_2x_neg_11bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-4096 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-GISEL-NEXT:    s_endpgm
 ;
 ; GFX10-SDAG-LABEL: global_inst_salu_offset_2x_neg_11bit_max:
 ; GFX10-SDAG:       ; %bb.0:
@@ -2478,6 +3798,46 @@ define amdgpu_kernel void @global_inst_salu_offset_2x_neg_11bit_max(ptr addrspac
 ; GFX10-SDAG-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-SDAG-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-SDAG-NEXT:    s_endpgm
+;
+; GFX11-SDAG-TRUE16-LABEL: global_inst_salu_offset_2x_neg_11bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] offset:-4096 glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_salu_offset_2x_neg_11bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-4096 glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_salu_offset_2x_neg_11bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] offset:-4096 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_salu_offset_2x_neg_11bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-4096 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 -4096
   %load = load volatile i8, ptr addrspace(1) %gep, align 1
   store i8 %load, ptr addrspace(1) poison
@@ -2523,15 +3883,15 @@ define amdgpu_kernel void @global_inst_salu_offset_2x_neg_12bit_max(ptr addrspac
 ; GFX11-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
 ; GFX11-GISEL-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: global_inst_salu_offset_2x_neg_12bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-8192 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX12-NEXT:    s_endpgm
+; GFX12-GISEL-LABEL: global_inst_salu_offset_2x_neg_12bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-8192 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-GISEL-NEXT:    s_endpgm
 ;
 ; GFX10-SDAG-LABEL: global_inst_salu_offset_2x_neg_12bit_max:
 ; GFX10-SDAG:       ; %bb.0:
@@ -2544,17 +3904,49 @@ define amdgpu_kernel void @global_inst_salu_offset_2x_neg_12bit_max(ptr addrspac
 ; GFX10-SDAG-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-SDAG-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: global_inst_salu_offset_2x_neg_12bit_max:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, s0, 0xffffe000, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
-; GFX11-SDAG-NEXT:    global_load_u8 v0, v[0:1], off glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: global_inst_salu_offset_2x_neg_12bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0xffffe000, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_salu_offset_2x_neg_12bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0xffffe000, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_salu_offset_2x_neg_12bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] offset:-8192 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_salu_offset_2x_neg_12bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-8192 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 -8192
   %load = load volatile i8, ptr addrspace(1) %gep, align 1
   store i8 %load, ptr addrspace(1) poison
@@ -2600,15 +3992,15 @@ define amdgpu_kernel void @global_inst_salu_offset_2x_neg_13bit_max(ptr addrspac
 ; GFX11-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
 ; GFX11-GISEL-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: global_inst_salu_offset_2x_neg_13bit_max:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-16384 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX12-NEXT:    s_endpgm
+; GFX12-GISEL-LABEL: global_inst_salu_offset_2x_neg_13bit_max:
+; GFX12-GISEL:       ; %bb.0:
+; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-GISEL-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-16384 scope:SCOPE_SYS
+; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-GISEL-NEXT:    s_endpgm
 ;
 ; GFX10-SDAG-LABEL: global_inst_salu_offset_2x_neg_13bit_max:
 ; GFX10-SDAG:       ; %bb.0:
@@ -2621,17 +4013,49 @@ define amdgpu_kernel void @global_inst_salu_offset_2x_neg_13bit_max(ptr addrspac
 ; GFX10-SDAG-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-SDAG-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: global_inst_salu_offset_2x_neg_13bit_max:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, s0, 0xffffc000, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
-; GFX11-SDAG-NEXT:    global_load_u8 v0, v[0:1], off glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: global_inst_salu_offset_2x_neg_13bit_max:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0xffffc000, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_salu_offset_2x_neg_13bit_max:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0xffffc000, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_salu_offset_2x_neg_13bit_max:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] offset:-16384 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_salu_offset_2x_neg_13bit_max:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] offset:-16384 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 -16384
   %load = load volatile i8, ptr addrspace(1) %gep, align 1
   store i8 %load, ptr addrspace(1) poison
@@ -2702,29 +4126,53 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_11bit_split0(ptr addrsp
 ; GFX10-SDAG-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-SDAG-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: global_inst_salu_offset_64bit_11bit_split0:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, s0, 0, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
-; GFX11-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:2047 glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-SDAG-LABEL: global_inst_salu_offset_64bit_11bit_split0:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xf1ff
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
-; GFX12-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:2047 scope:SCOPE_SYS
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX12-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: global_inst_salu_offset_64bit_11bit_split0:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:2047 glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_salu_offset_64bit_11bit_split0:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:2047 glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_salu_offset_64bit_11bit_split0:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:2047 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_salu_offset_64bit_11bit_split0:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:2047 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 8589936639
   %load = load volatile i8, ptr addrspace(1) %gep, align 1
   store i8 %load, ptr addrspace(1) poison
@@ -2795,29 +4243,53 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_11bit_split1(ptr addrsp
 ; GFX10-SDAG-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-SDAG-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: global_inst_salu_offset_64bit_11bit_split1:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, s0, 0, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
-; GFX11-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:2048 glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-SDAG-LABEL: global_inst_salu_offset_64bit_11bit_split1:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xf1ff
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
-; GFX12-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:2048 scope:SCOPE_SYS
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX12-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: global_inst_salu_offset_64bit_11bit_split1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:2048 glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_salu_offset_64bit_11bit_split1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:2048 glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_salu_offset_64bit_11bit_split1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:2048 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_salu_offset_64bit_11bit_split1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:2048 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 8589936640
   %load = load volatile i8, ptr addrspace(1) %gep, align 1
   store i8 %load, ptr addrspace(1) poison
@@ -2888,29 +4360,53 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_12bit_split0(ptr addrsp
 ; GFX10-SDAG-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-SDAG-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: global_inst_salu_offset_64bit_12bit_split0:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, s0, 0, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
-; GFX11-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:4095 glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-SDAG-LABEL: global_inst_salu_offset_64bit_12bit_split0:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xf1ff
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
-; GFX12-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:4095 scope:SCOPE_SYS
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX12-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: global_inst_salu_offset_64bit_12bit_split0:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:4095 glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_salu_offset_64bit_12bit_split0:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:4095 glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_salu_offset_64bit_12bit_split0:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:4095 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_salu_offset_64bit_12bit_split0:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:4095 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 8589938687
   %load = load volatile i8, ptr addrspace(1) %gep, align 1
   store i8 %load, ptr addrspace(1) poison
@@ -2981,29 +4477,53 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_12bit_split1(ptr addrsp
 ; GFX10-SDAG-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-SDAG-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: global_inst_salu_offset_64bit_12bit_split1:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, s0, 0x1000, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
-; GFX11-SDAG-NEXT:    global_load_u8 v0, v[0:1], off glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-SDAG-LABEL: global_inst_salu_offset_64bit_12bit_split1:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xf1ff
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
-; GFX12-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:4096 scope:SCOPE_SYS
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX12-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: global_inst_salu_offset_64bit_12bit_split1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0x1000, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_salu_offset_64bit_12bit_split1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0x1000, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_salu_offset_64bit_12bit_split1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:4096 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_salu_offset_64bit_12bit_split1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:4096 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 8589938688
   %load = load volatile i8, ptr addrspace(1) %gep, align 1
   store i8 %load, ptr addrspace(1) poison
@@ -3074,29 +4594,53 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_13bit_split0(ptr addrsp
 ; GFX10-SDAG-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-SDAG-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: global_inst_salu_offset_64bit_13bit_split0:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, s0, 0x1000, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
-; GFX11-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:4095 glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-SDAG-LABEL: global_inst_salu_offset_64bit_13bit_split0:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xf1ff
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
-; GFX12-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:8191 scope:SCOPE_SYS
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX12-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: global_inst_salu_offset_64bit_13bit_split0:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0x1000, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:4095 glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_salu_offset_64bit_13bit_split0:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0x1000, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:4095 glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_salu_offset_64bit_13bit_split0:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:8191 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_salu_offset_64bit_13bit_split0:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:8191 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 8589942783
   %load = load volatile i8, ptr addrspace(1) %gep, align 1
   store i8 %load, ptr addrspace(1) poison
@@ -3167,29 +4711,53 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_13bit_split1(ptr addrsp
 ; GFX10-SDAG-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-SDAG-NEXT:    s_endpgm
 ;
-; GFX11-SDAG-LABEL: global_inst_salu_offset_64bit_13bit_split1:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_co_u32 v0, s0, 0x2000, s0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
-; GFX11-SDAG-NEXT:    global_load_u8 v0, v[0:1], off glc dlc
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX12-SDAG-LABEL: global_inst_salu_offset_64bit_13bit_split1:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-NEXT:    s_wait_alu 0xf1ff
-; GFX12-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
-; GFX12-SDAG-NEXT:    global_load_u8 v0, v[0:1], off offset:8192 scope:SCOPE_SYS
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX12-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: global_inst_salu_offset_64bit_13bit_split1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0x2000, s0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_salu_offset_64bit_13bit_split1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0x2000, s0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_salu_offset_64bit_13bit_split1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v[0:1], off offset:8192 scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_salu_offset_64bit_13bit_split1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_u32 v0, s0, 0, s0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-SDAG-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, 2, s1, s0
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v[0:1], off offset:8192 scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 8589942784
   %load = load volatile i8, ptr addrspace(1) %gep, align 1
   store i8 %load, ptr addrspace(1) poison
@@ -3222,17 +4790,17 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_11bit_neg_high_split0(p
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_inst_salu_offset_64bit_11bit_neg_high_split0:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_add_u32 s0, s0, 0x7ff
-; GFX11-NEXT:    s_addc_u32 s1, s1, 0x80000000
-; GFX11-NEXT:    global_load_u8 v0, v0, s[0:1] glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-NEXT:    s_endpgm
+; GFX11-GISEL-LABEL: global_inst_salu_offset_64bit_11bit_neg_high_split0:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT:    s_add_u32 s0, s0, 0x7ff
+; GFX11-GISEL-NEXT:    s_addc_u32 s1, s1, 0x80000000
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] glc dlc
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-GISEL-NEXT:    s_endpgm
 ;
 ; GFX12-GISEL-LABEL: global_inst_salu_offset_64bit_11bit_neg_high_split0:
 ; GFX12-GISEL:       ; %bb.0:
@@ -3246,18 +4814,55 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_11bit_neg_high_split0(p
 ; GFX12-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
 ; GFX12-GISEL-NEXT:    s_endpgm
 ;
-; GFX12-SDAG-LABEL: global_inst_salu_offset_64bit_11bit_neg_high_split0:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-SDAG-NEXT:    s_movk_i32 s2, 0x7ff
-; GFX12-SDAG-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-SDAG-NEXT:    s_brev_b32 s3, 1
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    s_add_nc_u64 s[0:1], s[0:1], s[2:3]
-; GFX12-SDAG-NEXT:    global_load_u8 v0, v0, s[0:1] scope:SCOPE_SYS
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX12-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: global_inst_salu_offset_64bit_11bit_neg_high_split0:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_add_u32 s0, s0, 0x7ff
+; GFX11-SDAG-TRUE16-NEXT:    s_addc_u32 s1, s1, 0x80000000
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_salu_offset_64bit_11bit_neg_high_split0:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_add_u32 s0, s0, 0x7ff
+; GFX11-SDAG-FAKE16-NEXT:    s_addc_u32 s1, s1, 0x80000000
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_salu_offset_64bit_11bit_neg_high_split0:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_movk_i32 s2, 0x7ff
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-TRUE16-NEXT:    s_brev_b32 s3, 1
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_add_nc_u64 s[0:1], s[0:1], s[2:3]
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_salu_offset_64bit_11bit_neg_high_split0:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_movk_i32 s2, 0x7ff
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-FAKE16-NEXT:    s_brev_b32 s3, 1
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_add_nc_u64 s[0:1], s[0:1], s[2:3]
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 -9223372036854773761
   %load = load volatile i8, ptr addrspace(1) %gep, align 1
   store i8 %load, ptr addrspace(1) poison
@@ -3290,17 +4895,17 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_11bit_neg_high_split1(p
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_inst_salu_offset_64bit_11bit_neg_high_split1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_add_u32 s0, s0, 0x800
-; GFX11-NEXT:    s_addc_u32 s1, s1, 0x80000000
-; GFX11-NEXT:    global_load_u8 v0, v0, s[0:1] glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-NEXT:    s_endpgm
+; GFX11-GISEL-LABEL: global_inst_salu_offset_64bit_11bit_neg_high_split1:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT:    s_add_u32 s0, s0, 0x800
+; GFX11-GISEL-NEXT:    s_addc_u32 s1, s1, 0x80000000
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] glc dlc
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-GISEL-NEXT:    s_endpgm
 ;
 ; GFX12-GISEL-LABEL: global_inst_salu_offset_64bit_11bit_neg_high_split1:
 ; GFX12-GISEL:       ; %bb.0:
@@ -3314,18 +4919,55 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_11bit_neg_high_split1(p
 ; GFX12-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
 ; GFX12-GISEL-NEXT:    s_endpgm
 ;
-; GFX12-SDAG-LABEL: global_inst_salu_offset_64bit_11bit_neg_high_split1:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-SDAG-NEXT:    s_movk_i32 s2, 0x800
-; GFX12-SDAG-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-SDAG-NEXT:    s_brev_b32 s3, 1
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    s_add_nc_u64 s[0:1], s[0:1], s[2:3]
-; GFX12-SDAG-NEXT:    global_load_u8 v0, v0, s[0:1] scope:SCOPE_SYS
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX12-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: global_inst_salu_offset_64bit_11bit_neg_high_split1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_add_u32 s0, s0, 0x800
+; GFX11-SDAG-TRUE16-NEXT:    s_addc_u32 s1, s1, 0x80000000
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_salu_offset_64bit_11bit_neg_high_split1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_add_u32 s0, s0, 0x800
+; GFX11-SDAG-FAKE16-NEXT:    s_addc_u32 s1, s1, 0x80000000
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_salu_offset_64bit_11bit_neg_high_split1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_movk_i32 s2, 0x800
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-TRUE16-NEXT:    s_brev_b32 s3, 1
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_add_nc_u64 s[0:1], s[0:1], s[2:3]
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_salu_offset_64bit_11bit_neg_high_split1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_movk_i32 s2, 0x800
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-FAKE16-NEXT:    s_brev_b32 s3, 1
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_add_nc_u64 s[0:1], s[0:1], s[2:3]
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 -9223372036854773760
   %load = load volatile i8, ptr addrspace(1) %gep, align 1
   store i8 %load, ptr addrspace(1) poison
@@ -3358,17 +5000,17 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_12bit_neg_high_split0(p
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_inst_salu_offset_64bit_12bit_neg_high_split0:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_add_u32 s0, s0, 0xfff
-; GFX11-NEXT:    s_addc_u32 s1, s1, 0x80000000
-; GFX11-NEXT:    global_load_u8 v0, v0, s[0:1] glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-NEXT:    s_endpgm
+; GFX11-GISEL-LABEL: global_inst_salu_offset_64bit_12bit_neg_high_split0:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT:    s_add_u32 s0, s0, 0xfff
+; GFX11-GISEL-NEXT:    s_addc_u32 s1, s1, 0x80000000
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] glc dlc
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-GISEL-NEXT:    s_endpgm
 ;
 ; GFX12-GISEL-LABEL: global_inst_salu_offset_64bit_12bit_neg_high_split0:
 ; GFX12-GISEL:       ; %bb.0:
@@ -3382,18 +5024,55 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_12bit_neg_high_split0(p
 ; GFX12-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
 ; GFX12-GISEL-NEXT:    s_endpgm
 ;
-; GFX12-SDAG-LABEL: global_inst_salu_offset_64bit_12bit_neg_high_split0:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-SDAG-NEXT:    s_movk_i32 s2, 0xfff
-; GFX12-SDAG-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-SDAG-NEXT:    s_brev_b32 s3, 1
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    s_add_nc_u64 s[0:1], s[0:1], s[2:3]
-; GFX12-SDAG-NEXT:    global_load_u8 v0, v0, s[0:1] scope:SCOPE_SYS
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX12-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: global_inst_salu_offset_64bit_12bit_neg_high_split0:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_add_u32 s0, s0, 0xfff
+; GFX11-SDAG-TRUE16-NEXT:    s_addc_u32 s1, s1, 0x80000000
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_salu_offset_64bit_12bit_neg_high_split0:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_add_u32 s0, s0, 0xfff
+; GFX11-SDAG-FAKE16-NEXT:    s_addc_u32 s1, s1, 0x80000000
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_salu_offset_64bit_12bit_neg_high_split0:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_movk_i32 s2, 0xfff
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-TRUE16-NEXT:    s_brev_b32 s3, 1
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_add_nc_u64 s[0:1], s[0:1], s[2:3]
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_salu_offset_64bit_12bit_neg_high_split0:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_movk_i32 s2, 0xfff
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-FAKE16-NEXT:    s_brev_b32 s3, 1
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_add_nc_u64 s[0:1], s[0:1], s[2:3]
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 -9223372036854771713
   %load = load volatile i8, ptr addrspace(1) %gep, align 1
   store i8 %load, ptr addrspace(1) poison
@@ -3426,17 +5105,17 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_12bit_neg_high_split1(p
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_inst_salu_offset_64bit_12bit_neg_high_split1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_add_u32 s0, s0, 0x1000
-; GFX11-NEXT:    s_addc_u32 s1, s1, 0x80000000
-; GFX11-NEXT:    global_load_u8 v0, v0, s[0:1] glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-NEXT:    s_endpgm
+; GFX11-GISEL-LABEL: global_inst_salu_offset_64bit_12bit_neg_high_split1:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT:    s_add_u32 s0, s0, 0x1000
+; GFX11-GISEL-NEXT:    s_addc_u32 s1, s1, 0x80000000
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] glc dlc
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-GISEL-NEXT:    s_endpgm
 ;
 ; GFX12-GISEL-LABEL: global_inst_salu_offset_64bit_12bit_neg_high_split1:
 ; GFX12-GISEL:       ; %bb.0:
@@ -3450,18 +5129,55 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_12bit_neg_high_split1(p
 ; GFX12-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
 ; GFX12-GISEL-NEXT:    s_endpgm
 ;
-; GFX12-SDAG-LABEL: global_inst_salu_offset_64bit_12bit_neg_high_split1:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-SDAG-NEXT:    s_movk_i32 s2, 0x1000
-; GFX12-SDAG-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-SDAG-NEXT:    s_brev_b32 s3, 1
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    s_add_nc_u64 s[0:1], s[0:1], s[2:3]
-; GFX12-SDAG-NEXT:    global_load_u8 v0, v0, s[0:1] scope:SCOPE_SYS
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX12-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: global_inst_salu_offset_64bit_12bit_neg_high_split1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_add_u32 s0, s0, 0x1000
+; GFX11-SDAG-TRUE16-NEXT:    s_addc_u32 s1, s1, 0x80000000
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_salu_offset_64bit_12bit_neg_high_split1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_add_u32 s0, s0, 0x1000
+; GFX11-SDAG-FAKE16-NEXT:    s_addc_u32 s1, s1, 0x80000000
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_salu_offset_64bit_12bit_neg_high_split1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_movk_i32 s2, 0x1000
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-TRUE16-NEXT:    s_brev_b32 s3, 1
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_add_nc_u64 s[0:1], s[0:1], s[2:3]
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_salu_offset_64bit_12bit_neg_high_split1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_movk_i32 s2, 0x1000
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-FAKE16-NEXT:    s_brev_b32 s3, 1
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_add_nc_u64 s[0:1], s[0:1], s[2:3]
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 -9223372036854771712
   %load = load volatile i8, ptr addrspace(1) %gep, align 1
   store i8 %load, ptr addrspace(1) poison
@@ -3494,17 +5210,17 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_13bit_neg_high_split0(p
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_inst_salu_offset_64bit_13bit_neg_high_split0:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_add_u32 s0, s0, 0x1fff
-; GFX11-NEXT:    s_addc_u32 s1, s1, 0x80000000
-; GFX11-NEXT:    global_load_u8 v0, v0, s[0:1] glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-NEXT:    s_endpgm
+; GFX11-GISEL-LABEL: global_inst_salu_offset_64bit_13bit_neg_high_split0:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT:    s_add_u32 s0, s0, 0x1fff
+; GFX11-GISEL-NEXT:    s_addc_u32 s1, s1, 0x80000000
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] glc dlc
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-GISEL-NEXT:    s_endpgm
 ;
 ; GFX12-GISEL-LABEL: global_inst_salu_offset_64bit_13bit_neg_high_split0:
 ; GFX12-GISEL:       ; %bb.0:
@@ -3518,18 +5234,55 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_13bit_neg_high_split0(p
 ; GFX12-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
 ; GFX12-GISEL-NEXT:    s_endpgm
 ;
-; GFX12-SDAG-LABEL: global_inst_salu_offset_64bit_13bit_neg_high_split0:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-SDAG-NEXT:    s_movk_i32 s2, 0x1fff
-; GFX12-SDAG-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-SDAG-NEXT:    s_brev_b32 s3, 1
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    s_add_nc_u64 s[0:1], s[0:1], s[2:3]
-; GFX12-SDAG-NEXT:    global_load_u8 v0, v0, s[0:1] scope:SCOPE_SYS
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX12-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: global_inst_salu_offset_64bit_13bit_neg_high_split0:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_add_u32 s0, s0, 0x1fff
+; GFX11-SDAG-TRUE16-NEXT:    s_addc_u32 s1, s1, 0x80000000
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_salu_offset_64bit_13bit_neg_high_split0:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_add_u32 s0, s0, 0x1fff
+; GFX11-SDAG-FAKE16-NEXT:    s_addc_u32 s1, s1, 0x80000000
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_salu_offset_64bit_13bit_neg_high_split0:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_movk_i32 s2, 0x1fff
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-TRUE16-NEXT:    s_brev_b32 s3, 1
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_add_nc_u64 s[0:1], s[0:1], s[2:3]
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_salu_offset_64bit_13bit_neg_high_split0:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_movk_i32 s2, 0x1fff
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-FAKE16-NEXT:    s_brev_b32 s3, 1
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_add_nc_u64 s[0:1], s[0:1], s[2:3]
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 -9223372036854767617
   %load = load volatile i8, ptr addrspace(1) %gep, align 1
   store i8 %load, ptr addrspace(1) poison
@@ -3562,17 +5315,17 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_13bit_neg_high_split1(p
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: global_inst_salu_offset_64bit_13bit_neg_high_split1:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_add_u32 s0, s0, 0x2000
-; GFX11-NEXT:    s_addc_u32 s1, s1, 0x80000000
-; GFX11-NEXT:    global_load_u8 v0, v0, s[0:1] glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX11-NEXT:    s_endpgm
+; GFX11-GISEL-LABEL: global_inst_salu_offset_64bit_13bit_neg_high_split1:
+; GFX11-GISEL:       ; %bb.0:
+; GFX11-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT:    s_add_u32 s0, s0, 0x2000
+; GFX11-GISEL-NEXT:    s_addc_u32 s1, s1, 0x80000000
+; GFX11-GISEL-NEXT:    global_load_u8 v0, v0, s[0:1] glc dlc
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-GISEL-NEXT:    s_endpgm
 ;
 ; GFX12-GISEL-LABEL: global_inst_salu_offset_64bit_13bit_neg_high_split1:
 ; GFX12-GISEL:       ; %bb.0:
@@ -3586,20 +5339,66 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_13bit_neg_high_split1(p
 ; GFX12-GISEL-NEXT:    global_store_b8 v[0:1], v0, off
 ; GFX12-GISEL-NEXT:    s_endpgm
 ;
-; GFX12-SDAG-LABEL: global_inst_salu_offset_64bit_13bit_neg_high_split1:
-; GFX12-SDAG:       ; %bb.0:
-; GFX12-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-SDAG-NEXT:    s_movk_i32 s2, 0x2000
-; GFX12-SDAG-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-SDAG-NEXT:    s_brev_b32 s3, 1
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    s_add_nc_u64 s[0:1], s[0:1], s[2:3]
-; GFX12-SDAG-NEXT:    global_load_u8 v0, v0, s[0:1] scope:SCOPE_SYS
-; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT:    global_store_b8 v[0:1], v0, off
-; GFX12-SDAG-NEXT:    s_endpgm
+; GFX11-SDAG-TRUE16-LABEL: global_inst_salu_offset_64bit_13bit_neg_high_split1:
+; GFX11-SDAG-TRUE16:       ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    s_add_u32 s0, s0, 0x2000
+; GFX11-SDAG-TRUE16-NEXT:    s_addc_u32 s1, s1, 0x80000000
+; GFX11-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] glc dlc
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-SDAG-FAKE16-LABEL: global_inst_salu_offset_64bit_13bit_neg_high_split1:
+; GFX11-SDAG-FAKE16:       ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_add_u32 s0, s0, 0x2000
+; GFX11-SDAG-FAKE16-NEXT:    s_addc_u32 s1, s1, 0x80000000
+; GFX11-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] glc dlc
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX11-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-TRUE16-LABEL: global_inst_salu_offset_64bit_13bit_neg_high_split1:
+; GFX12-SDAG-TRUE16:       ; %bb.0:
+; GFX12-SDAG-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-TRUE16-NEXT:    s_movk_i32 s2, 0x2000
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-TRUE16-NEXT:    s_brev_b32 s3, 1
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_add_nc_u64 s[0:1], s[0:1], s[2:3]
+; GFX12-SDAG-TRUE16-NEXT:    global_load_d16_u8 v0, v0, s[0:1] scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-SDAG-FAKE16-LABEL: global_inst_salu_offset_64bit_13bit_neg_high_split1:
+; GFX12-SDAG-FAKE16:       ; %bb.0:
+; GFX12-SDAG-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-SDAG-FAKE16-NEXT:    s_movk_i32 s2, 0x2000
+; GFX12-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-SDAG-FAKE16-NEXT:    s_brev_b32 s3, 1
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_add_nc_u64 s[0:1], s[0:1], s[2:3]
+; GFX12-SDAG-FAKE16-NEXT:    global_load_u8 v0, v0, s[0:1] scope:SCOPE_SYS
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    global_store_b8 v[0:1], v0, off
+; GFX12-SDAG-FAKE16-NEXT:    s_endpgm
   %gep = getelementptr i8, ptr addrspace(1) %p, i64 -9223372036854767616
   %load = load volatile i8, ptr addrspace(1) %gep, align 1
   store i8 %load, ptr addrspace(1) poison
   ret void
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11: {{.*}}
+; GFX11-GISEL-FAKE16: {{.*}}
+; GFX11-GISEL-TRUE16: {{.*}}
+; GFX11-SDAG: {{.*}}
+; GFX12: {{.*}}
+; GFX12-GISEL-FAKE16: {{.*}}
+; GFX12-GISEL-TRUE16: {{.*}}
+; GFX12-SDAG: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/omod.ll b/llvm/test/CodeGen/AMDGPU/omod.ll
index 4e157b40570ed..dc2a2810c6274 100644
--- a/llvm/test/CodeGen/AMDGPU/omod.ll
+++ b/llvm/test/CodeGen/AMDGPU/omod.ll
@@ -1,8 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck --check-prefixes=SI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck --check-prefixes=VI %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11PLUS,GFX11 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11PLUS,GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11PLUS,GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11PLUS,GFX11,GFX11-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11PLUS,GFX12,GFX12-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11PLUS,GFX12,GFX12-FAKE16 %s
 
 ; IEEE bit enabled for compute kernel, so shouldn't use.
 define amdgpu_kernel void @v_omod_div2_f32_enable_ieee_signed_zeros(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #4 {
@@ -1097,13 +1099,51 @@ define amdgpu_ps void @v_omod_div2_f16_denormals(half %a) #0 {
 ; VI-NEXT:    flat_store_short v[0:1], v0
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11PLUS-LABEL: v_omod_div2_f16_denormals:
-; GFX11PLUS:       ; %bb.0:
-; GFX11PLUS-NEXT:    v_add_f16_e32 v0, 1.0, v0
-; GFX11PLUS-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11PLUS-NEXT:    v_mul_f16_e32 v0, 0.5, v0
-; GFX11PLUS-NEXT:    global_store_b16 v[0:1], v0, off
-; GFX11PLUS-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: v_omod_div2_f16_denormals:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_add_f16_e32 v0.l, 1.0, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0.5, v0.l
+; GFX11-TRUE16-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: v_omod_div2_f16_denormals:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_add_f16_e32 v0, 1.0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v0, 0.5, v0
+; GFX11-FAKE16-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX11-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-TRUE16-LABEL: v_omod_div2_f16_denormals:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    v_add_f16_e32 v0.l, 1.0, v0.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0.5, v0.l
+; GFX12-TRUE16-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: v_omod_div2_f16_denormals:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    v_add_f16_e32 v0, 1.0, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_mul_f16_e32 v0, 0.5, v0
+; GFX12-FAKE16-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX12-FAKE16-NEXT:    s_endpgm
+; GFX11-TRUE16PLUS-LABEL: v_omod_div2_f16_denormals:
+; GFX11-TRUE16PLUS:       ; %bb.0:
+; GFX11-TRUE16PLUS-NEXT:    v_add_f16_e32 v0.l, 1.0, v0.l
+; GFX11-TRUE16PLUS-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16PLUS-NEXT:    v_mul_f16_e32 v0.l, 0.5, v0.l
+; GFX11-TRUE16PLUS-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX11-TRUE16PLUS-NEXT:    s_endpgm
+; GFX11-FAKE16PLUS-LABEL: v_omod_div2_f16_denormals:
+; GFX11-FAKE16PLUS:       ; %bb.0:
+; GFX11-FAKE16PLUS-NEXT:    v_add_f16_e32 v0, 1.0, v0
+; GFX11-FAKE16PLUS-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16PLUS-NEXT:    v_mul_f16_e32 v0, 0.5, v0
+; GFX11-FAKE16PLUS-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX11-FAKE16PLUS-NEXT:    s_endpgm
   %add = fadd half %a, 1.0
   %div2 = fmul half %add, 0.5
   store half %div2, ptr addrspace(1) poison
@@ -1130,13 +1170,51 @@ define amdgpu_ps void @v_omod_mul2_f16_denormals(half %a) #0 {
 ; VI-NEXT:    flat_store_short v[0:1], v0
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11PLUS-LABEL: v_omod_mul2_f16_denormals:
-; GFX11PLUS:       ; %bb.0:
-; GFX11PLUS-NEXT:    v_add_f16_e32 v0, 1.0, v0
-; GFX11PLUS-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11PLUS-NEXT:    v_add_f16_e32 v0, v0, v0
-; GFX11PLUS-NEXT:    global_store_b16 v[0:1], v0, off
-; GFX11PLUS-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: v_omod_mul2_f16_denormals:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_add_f16_e32 v0.l, 1.0, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v0.l
+; GFX11-TRUE16-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: v_omod_mul2_f16_denormals:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_add_f16_e32 v0, 1.0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v0
+; GFX11-FAKE16-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX11-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-TRUE16-LABEL: v_omod_mul2_f16_denormals:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    v_add_f16_e32 v0.l, 1.0, v0.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v0.l
+; GFX12-TRUE16-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: v_omod_mul2_f16_denormals:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    v_add_f16_e32 v0, 1.0, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v0
+; GFX12-FAKE16-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX12-FAKE16-NEXT:    s_endpgm
+; GFX11-TRUE16PLUS-LABEL: v_omod_mul2_f16_denormals:
+; GFX11-TRUE16PLUS:       ; %bb.0:
+; GFX11-TRUE16PLUS-NEXT:    v_add_f16_e32 v0.l, 1.0, v0.l
+; GFX11-TRUE16PLUS-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16PLUS-NEXT:    v_add_f16_e32 v0.l, v0.l, v0.l
+; GFX11-TRUE16PLUS-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX11-TRUE16PLUS-NEXT:    s_endpgm
+; GFX11-FAKE16PLUS-LABEL: v_omod_mul2_f16_denormals:
+; GFX11-FAKE16PLUS:       ; %bb.0:
+; GFX11-FAKE16PLUS-NEXT:    v_add_f16_e32 v0, 1.0, v0
+; GFX11-FAKE16PLUS-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16PLUS-NEXT:    v_add_f16_e32 v0, v0, v0
+; GFX11-FAKE16PLUS-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX11-FAKE16PLUS-NEXT:    s_endpgm
   %add = fadd half %a, 1.0
   %mul2 = fadd half %add, %add
   store half %mul2, ptr addrspace(1) poison
@@ -1161,11 +1239,39 @@ define amdgpu_ps void @v_omod_div2_f16_no_denormals(half %a) #3 {
 ; VI-NEXT:    flat_store_short v[0:1], v0
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11PLUS-LABEL: v_omod_div2_f16_no_denormals:
-; GFX11PLUS:       ; %bb.0:
-; GFX11PLUS-NEXT:    v_add_f16_e64 v0, v0, 1.0 div:2
-; GFX11PLUS-NEXT:    global_store_b16 v[0:1], v0, off
-; GFX11PLUS-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: v_omod_div2_f16_no_denormals:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    v_add_f16_e64 v0.l, v0.l, 1.0 div:2
+; GFX11-TRUE16-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: v_omod_div2_f16_no_denormals:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    v_add_f16_e64 v0, v0, 1.0 div:2
+; GFX11-FAKE16-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX11-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-TRUE16-LABEL: v_omod_div2_f16_no_denormals:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    v_add_f16_e64 v0.l, v0.l, 1.0 div:2
+; GFX12-TRUE16-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: v_omod_div2_f16_no_denormals:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    v_add_f16_e64 v0, v0, 1.0 div:2
+; GFX12-FAKE16-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX12-FAKE16-NEXT:    s_endpgm
+; GFX11-TRUE16PLUS-LABEL: v_omod_div2_f16_no_denormals:
+; GFX11-TRUE16PLUS:       ; %bb.0:
+; GFX11-TRUE16PLUS-NEXT:    v_add_f16_e64 v0.l, v0.l, 1.0 div:2
+; GFX11-TRUE16PLUS-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX11-TRUE16PLUS-NEXT:    s_endpgm
+; GFX11-FAKE16PLUS-LABEL: v_omod_div2_f16_no_denormals:
+; GFX11-FAKE16PLUS:       ; %bb.0:
+; GFX11-FAKE16PLUS-NEXT:    v_add_f16_e64 v0, v0, 1.0 div:2
+; GFX11-FAKE16PLUS-NEXT:    global_store_b16 v[0:1], v0, off
+; GFX11-FAKE16PLUS-NEXT:    s_endpgm
   %add = fadd half %a, 1.0
   %div2 = fmul half %add, 0.5
   store half %div2, ptr addrspace(1) poison
diff --git a/llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll b/llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
index 5f2bd53dc91a3..5025c1d8a433f 100644
--- a/llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
+++ b/llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
@@ -1193,5 +1193,3 @@ ret:
 attributes #0 = { nounwind }
 attributes #1 = { nounwind "amdgpu-waves-per-eu"="7,7" }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll b/llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
index 20e5af1b87f1f..2d95ec6f699dc 100644
--- a/llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
+++ b/llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
@@ -825,5 +825,3 @@ declare void @foo()
 
 attributes #0 = { "amdgpu-num-vgpr"="42" "amdgpu-num-sgpr"="40"}
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll
index 6e76ee10292ea..a88acb69bc4da 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll
+++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll
@@ -95,5 +95,3 @@ declare i32 @llvm.amdgcn.workitem.id.x() #1
 attributes #0 = { nounwind "amdgpu-flat-work-group-size"="64,64" }
 attributes #1 = { nounwind readnone }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
index 35b55a0addd95..e452af7d60c0c 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
+++ b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
@@ -3,7 +3,8 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX900 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX90A %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 declare i64 @_Z13get_global_idj(i32) #0
 
@@ -2622,25 +2623,45 @@ define amdgpu_kernel void @negativeoffsetnullptr(ptr %buffer) {
 ; GFX10-NEXT:  ; %bb.2: ; %end
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: negativeoffsetnullptr:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_mov_b64 s[0:1], src_private_base
-; GFX11-NEXT:    v_add_co_u32 v0, s0, -1, 0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
-; GFX11-NEXT:    s_mov_b32 s0, 0
-; GFX11-NEXT:    flat_load_u8 v0, v[0:1]
-; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v0
-; GFX11-NEXT:  .LBB8_1: ; %branch
-; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GFX11-NEXT:    s_and_b32 s1, exec_lo, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT:    s_or_b32 s0, s1, s0
-; GFX11-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s0
-; GFX11-NEXT:    s_cbranch_execnz .LBB8_1
-; GFX11-NEXT:  ; %bb.2: ; %end
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: negativeoffsetnullptr:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_mov_b64 s[0:1], src_private_base
+; GFX11-TRUE16-NEXT:    v_add_co_u32 v0, s0, -1, 0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
+; GFX11-TRUE16-NEXT:    s_mov_b32 s0, 0
+; GFX11-TRUE16-NEXT:    flat_load_d16_u8 v0, v[0:1]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v0.l
+; GFX11-TRUE16-NEXT:  .LBB8_1: ; %branch
+; GFX11-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-TRUE16-NEXT:    s_and_b32 s1, exec_lo, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_or_b32 s0, s1, s0
+; GFX11-TRUE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB8_1
+; GFX11-TRUE16-NEXT:  ; %bb.2: ; %end
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: negativeoffsetnullptr:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_mov_b64 s[0:1], src_private_base
+; GFX11-FAKE16-NEXT:    v_add_co_u32 v0, s0, -1, 0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s1, s0
+; GFX11-FAKE16-NEXT:    s_mov_b32 s0, 0
+; GFX11-FAKE16-NEXT:    flat_load_u8 v0, v[0:1]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0, v0
+; GFX11-FAKE16-NEXT:  .LBB8_1: ; %branch
+; GFX11-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-FAKE16-NEXT:    s_and_b32 s1, exec_lo, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_or_b32 s0, s1, s0
+; GFX11-FAKE16-NEXT:    s_and_not1_b32 exec_lo, exec_lo, s0
+; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB8_1
+; GFX11-FAKE16-NEXT:  ; %bb.2: ; %end
+; GFX11-FAKE16-NEXT:    s_endpgm
 entry:
   %null = select i1 false, ptr %buffer, ptr addrspacecast (ptr addrspace(5) null to ptr)
   %gep = getelementptr i8, ptr %null, i64 -1
diff --git a/llvm/test/CodeGen/AMDGPU/repeated-divisor.ll b/llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
index e5f8de6bd521d..04eea20993608 100644
--- a/llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
+++ b/llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
@@ -1,7 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-FAKE16 %s
 
 define <2 x float> @v_repeat_divisor_f32_x2(float %x, float %y, float %D) #0 {
 ; GFX6-LABEL: v_repeat_divisor_f32_x2:
@@ -275,16 +276,27 @@ define <2 x half> @v_repeat_divisor_f16_x2_arcp(half %x, half %y, half %D) #0 {
 ; GFX9-NEXT:    v_pack_b32_f16 v0, v0, v1
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_repeat_divisor_f16_x2_arcp:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_rcp_f16_e32 v2, v2
-; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v2
-; GFX11-NEXT:    v_mul_f16_e32 v1, v1, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_repeat_divisor_f16_x2_arcp:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_rcp_f16_e32 v2.l, v2.l
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v0.h, v1.l, v2.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_repeat_divisor_f16_x2_arcp:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_rcp_f16_e32 v2, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v1, v1, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %div0 = fdiv arcp half %x, %D
   %div1 = fdiv arcp half %y, %D
   %insert.0 = insertelement <2 x half> poison, half %div0, i32 0
@@ -550,17 +562,29 @@ define <3 x half> @v_repeat_divisor_f16_x3_arcp(half %x, half %y, half %z, half
 ; GFX9-NEXT:    v_pack_b32_f16 v0, v0, v4
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_repeat_divisor_f16_x3_arcp:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_rcp_f16_e32 v3, v3
-; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v3
-; GFX11-NEXT:    v_mul_f16_e32 v1, v1, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT:    v_mul_f16_e32 v1, v2, v3
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_repeat_divisor_f16_x3_arcp:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_rcp_f16_e32 v3.l, v3.l
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v3.l
+; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v0.h, v1.l, v3.l
+; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v1.l, v2.l, v3.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_repeat_divisor_f16_x3_arcp:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_rcp_f16_e32 v3, v3
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v3
+; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v1, v1, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %div0 = fdiv arcp half %x, %D
   %div1 = fdiv arcp half %y, %D
   %div2 = fdiv arcp half %z, %D
@@ -812,18 +836,30 @@ define <4 x half> @v_repeat_divisor_v2f16_x2(<2 x half> %x, <2 x half> %y, <2 x
 ; GFX9-NEXT:    v_pk_mul_f16 v1, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_repeat_divisor_v2f16_x2:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
-; GFX11-NEXT:    v_rcp_f16_e32 v2, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_rcp_f16_e32 v3, v3
-; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_pack_b32_f16 v2, v2, v3
-; GFX11-NEXT:    v_pk_mul_f16 v0, v0, v2
-; GFX11-NEXT:    v_pk_mul_f16 v1, v1, v2
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_repeat_divisor_v2f16_x2:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_rcp_f16_e32 v2.h, v2.h
+; GFX11-TRUE16-NEXT:    v_rcp_f16_e32 v2.l, v2.l
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v2, v2.l, v2.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_pk_mul_f16 v0, v0, v2
+; GFX11-TRUE16-NEXT:    v_pk_mul_f16 v1, v1, v2
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_repeat_divisor_v2f16_x2:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
+; GFX11-FAKE16-NEXT:    v_rcp_f16_e32 v2, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_rcp_f16_e32 v3, v3
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v2, v2, v3
+; GFX11-FAKE16-NEXT:    v_pk_mul_f16 v0, v0, v2
+; GFX11-FAKE16-NEXT:    v_pk_mul_f16 v1, v1, v2
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %div0 = fdiv arcp <2 x half> %x, %D
   %div1 = fdiv arcp <2 x half> %y, %D
   %shuffle = shufflevector <2 x half> %div0, <2 x half> %div1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
@@ -910,26 +946,47 @@ define <6 x half> @v_repeat_divisor_v3f16_x2(<3 x half> %x, <3 x half> %y, <3 x
 ; GFX9-NEXT:    v_pack_b32_f16 v1, v1, v4
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_repeat_divisor_v3f16_x2:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-NEXT:    v_rcp_f16_e32 v4, v4
-; GFX11-NEXT:    v_rcp_f16_e32 v5, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_rcp_f16_e32 v6, v6
-; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_pack_b32_f16 v5, v5, 0x7e00
-; GFX11-NEXT:    v_pack_b32_f16 v4, v4, v6
-; GFX11-NEXT:    v_pk_mul_f16 v1, v1, v5
-; GFX11-NEXT:    v_pk_mul_f16 v3, v3, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_pk_mul_f16 v2, v2, v4
-; GFX11-NEXT:    v_pk_mul_f16 v0, v0, v4
-; GFX11-NEXT:    v_pack_b32_f16 v1, v1, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT:    v_alignbit_b32 v2, v3, v2, 16
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_repeat_divisor_v3f16_x2:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_rcp_f16_e32 v4.h, v4.h
+; GFX11-TRUE16-NEXT:    v_rcp_f16_e32 v5.l, v5.l
+; GFX11-TRUE16-NEXT:    v_rcp_f16_e32 v4.l, v4.l
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v5, v5.l, 0x7e00
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v4, v4.l, v4.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_pk_mul_f16 v1, v1, v5
+; GFX11-TRUE16-NEXT:    v_pk_mul_f16 v2, v2, v4
+; GFX11-TRUE16-NEXT:    v_pk_mul_f16 v3, v3, v5
+; GFX11-TRUE16-NEXT:    v_pk_mul_f16 v0, v0, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.l, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_repeat_divisor_v3f16_x2:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v4
+; GFX11-FAKE16-NEXT:    v_rcp_f16_e32 v4, v4
+; GFX11-FAKE16-NEXT:    v_rcp_f16_e32 v5, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_rcp_f16_e32 v6, v6
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v5, v5, 0x7e00
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v4, v4, v6
+; GFX11-FAKE16-NEXT:    v_pk_mul_f16 v1, v1, v5
+; GFX11-FAKE16-NEXT:    v_pk_mul_f16 v3, v3, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_pk_mul_f16 v2, v2, v4
+; GFX11-FAKE16-NEXT:    v_pk_mul_f16 v0, v0, v4
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v2, v3, v2, 16
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %div0 = fdiv arcp <3 x half> %x, %D
   %div1 = fdiv arcp <3 x half> %y, %D
   %shuffle = shufflevector <3 x half> %div0, <3 x half> %div1, <6 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5>
diff --git a/llvm/test/CodeGen/AMDGPU/rotl.ll b/llvm/test/CodeGen/AMDGPU/rotl.ll
index 017b37af4cdf2..0a746b0a3f572 100644
--- a/llvm/test/CodeGen/AMDGPU/rotl.ll
+++ b/llvm/test/CodeGen/AMDGPU/rotl.ll
@@ -3,7 +3,8 @@
 ; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=SI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define amdgpu_kernel void @rotl_i32(ptr addrspace(1) %in, i32 %x, i32 %y) {
 ; R600-LABEL: rotl_i32:
@@ -370,20 +371,35 @@ define void @test_rotl_i16(ptr addrspace(1) nocapture readonly %sourceA, ptr add
 ; GFX10-NEXT:    global_store_short v[4:5], v0, off offset:8
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_rotl_i16:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_u16 v2, v[2:3], off offset:48
-; GFX11-NEXT:    global_load_u16 v0, v[0:1], off offset:32
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_sub_nc_u16 v1, 0, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b16 v2, v2, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_lshrrev_b16 v0, v1, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v2, v0
-; GFX11-NEXT:    global_store_b16 v[4:5], v0, off offset:8
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test_rotl_i16:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v2, v[2:3], off offset:48
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v[0:1], off offset:32
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_sub_nc_u16 v0.h, 0, v2.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b16 v0.l, v0.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l
+; GFX11-TRUE16-NEXT:    global_store_b16 v[4:5], v0, off offset:8
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_rotl_i16:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_u16 v2, v[2:3], off offset:48
+; GFX11-FAKE16-NEXT:    global_load_u16 v0, v[0:1], off offset:32
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_sub_nc_u16 v1, 0, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v2, v2, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b16 v0, v1, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT:    global_store_b16 v[4:5], v0, off offset:8
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %arrayidx = getelementptr inbounds i16, ptr addrspace(1) %sourceA, i64 16
   %a = load i16, ptr addrspace(1) %arrayidx
diff --git a/llvm/test/CodeGen/AMDGPU/rotr.ll b/llvm/test/CodeGen/AMDGPU/rotr.ll
index db56589b799dd..d6e361d6e297e 100644
--- a/llvm/test/CodeGen/AMDGPU/rotr.ll
+++ b/llvm/test/CodeGen/AMDGPU/rotr.ll
@@ -3,7 +3,8 @@
 ; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=SI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define amdgpu_kernel void @rotr_i32(ptr addrspace(1) %in, i32 %x, i32 %y) {
 ; R600-LABEL: rotr_i32:
@@ -327,20 +328,35 @@ define void @test_rotr_i16(ptr addrspace(1) nocapture readonly %sourceA, ptr add
 ; GFX10-NEXT:    global_store_short v[4:5], v0, off offset:8
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_rotr_i16:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_u16 v2, v[2:3], off offset:48
-; GFX11-NEXT:    global_load_u16 v0, v[0:1], off offset:32
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_sub_nc_u16 v1, 0, v2
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b16 v2, v2, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_lshlrev_b16 v0, v1, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v2, v0
-; GFX11-NEXT:    global_store_b16 v[4:5], v0, off offset:8
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: test_rotr_i16:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v2, v[2:3], off offset:48
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v[0:1], off offset:32
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_sub_nc_u16 v0.h, 0, v2.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b16 v1.l, v2.l, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.l, v0.h, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l
+; GFX11-TRUE16-NEXT:    global_store_b16 v[4:5], v0, off offset:8
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_rotr_i16:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_u16 v2, v[2:3], off offset:48
+; GFX11-FAKE16-NEXT:    global_load_u16 v0, v[0:1], off offset:32
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_sub_nc_u16 v1, 0, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b16 v2, v2, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v0, v1, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT:    global_store_b16 v[4:5], v0, off offset:8
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %arrayidx = getelementptr inbounds i16, ptr addrspace(1) %sourceA, i64 16
   %a = load i16, ptr addrspace(1) %arrayidx
diff --git a/llvm/test/CodeGen/AMDGPU/roundeven.ll b/llvm/test/CodeGen/AMDGPU/roundeven.ll
index 0aff5ca25149f..59a1fe041bf90 100644
--- a/llvm/test/CodeGen/AMDGPU/roundeven.ll
+++ b/llvm/test/CodeGen/AMDGPU/roundeven.ll
@@ -4,13 +4,15 @@
 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=GFX8 %s
 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-FAKE16 %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SDAG_GFX6 %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefix=SDAG_GFX7 %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=SDAG_GFX8 %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=SDAG_GFX9 %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=SDAG_GFX10PLUS,SDAG_GFX10 %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=SDAG_GFX10PLUS,SDAG_GFX11 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=SDAG_GFX10PLUS,SDAG_GFX11,SDAG_GFX11-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=SDAG_GFX10PLUS,SDAG_GFX11,SDAG_GFX11-FAKE16 %s
 
 define float @v_roundeven_f32(float %x) {
 ; GFX6-LABEL: v_roundeven_f32:
@@ -357,11 +359,23 @@ define half @v_roundeven_f16(half %x) {
 ; GFX9-NEXT:    v_rndne_f16_e32 v0, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX10PLUS-LABEL: v_roundeven_f16:
-; GFX10PLUS:       ; %bb.0:
-; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT:    v_rndne_f16_e32 v0, v0
-; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_roundeven_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_rndne_f16_e32 v0, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: v_roundeven_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_rndne_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_roundeven_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_rndne_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SDAG_GFX6-LABEL: v_roundeven_f16:
 ; SDAG_GFX6:       ; %bb.0:
@@ -391,11 +405,23 @@ define half @v_roundeven_f16(half %x) {
 ; SDAG_GFX9-NEXT:    v_rndne_f16_e32 v0, v0
 ; SDAG_GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; SDAG_GFX10PLUS-LABEL: v_roundeven_f16:
-; SDAG_GFX10PLUS:       ; %bb.0:
-; SDAG_GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG_GFX10PLUS-NEXT:    v_rndne_f16_e32 v0, v0
-; SDAG_GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
+; SDAG_GFX10-LABEL: v_roundeven_f16:
+; SDAG_GFX10:       ; %bb.0:
+; SDAG_GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG_GFX10-NEXT:    v_rndne_f16_e32 v0, v0
+; SDAG_GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG_GFX11-TRUE16-LABEL: v_roundeven_f16:
+; SDAG_GFX11-TRUE16:       ; %bb.0:
+; SDAG_GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG_GFX11-TRUE16-NEXT:    v_rndne_f16_e32 v0.l, v0.l
+; SDAG_GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG_GFX11-FAKE16-LABEL: v_roundeven_f16:
+; SDAG_GFX11-FAKE16:       ; %bb.0:
+; SDAG_GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG_GFX11-FAKE16-NEXT:    v_rndne_f16_e32 v0, v0
+; SDAG_GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %roundeven = call half @llvm.roundeven.f16(half %x)
   ret half %roundeven
 }
@@ -447,14 +473,22 @@ define <2 x half> @v_roundeven_v2f16(<2 x half> %x) {
 ; GFX10-NEXT:    v_pack_b32_f16 v0, v1, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_roundeven_v2f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_rndne_f16_e32 v0, v0
-; GFX11-NEXT:    v_rndne_f16_e32 v1, v1
-; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_roundeven_v2f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_rndne_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT:    v_rndne_f16_e32 v0.h, v0.h
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_roundeven_v2f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_rndne_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_rndne_f16_e32 v1, v1
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SDAG_GFX6-LABEL: v_roundeven_v2f16:
 ; SDAG_GFX6:       ; %bb.0:
@@ -502,14 +536,22 @@ define <2 x half> @v_roundeven_v2f16(<2 x half> %x) {
 ; SDAG_GFX10-NEXT:    v_pack_b32_f16 v0, v0, v1
 ; SDAG_GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; SDAG_GFX11-LABEL: v_roundeven_v2f16:
-; SDAG_GFX11:       ; %bb.0:
-; SDAG_GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG_GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; SDAG_GFX11-NEXT:    v_rndne_f16_e32 v0, v0
-; SDAG_GFX11-NEXT:    v_rndne_f16_e32 v1, v1
-; SDAG_GFX11-NEXT:    v_pack_b32_f16 v0, v0, v1
-; SDAG_GFX11-NEXT:    s_setpc_b64 s[30:31]
+; SDAG_GFX11-TRUE16-LABEL: v_roundeven_v2f16:
+; SDAG_GFX11-TRUE16:       ; %bb.0:
+; SDAG_GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG_GFX11-TRUE16-NEXT:    v_rndne_f16_e32 v0.h, v0.h
+; SDAG_GFX11-TRUE16-NEXT:    v_rndne_f16_e32 v0.l, v0.l
+; SDAG_GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; SDAG_GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG_GFX11-FAKE16-LABEL: v_roundeven_v2f16:
+; SDAG_GFX11-FAKE16:       ; %bb.0:
+; SDAG_GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG_GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; SDAG_GFX11-FAKE16-NEXT:    v_rndne_f16_e32 v0, v0
+; SDAG_GFX11-FAKE16-NEXT:    v_rndne_f16_e32 v1, v1
+; SDAG_GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; SDAG_GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %roundeven = call <2 x half> @llvm.roundeven.v2f16(<2 x half> %x)
   ret <2 x half> %roundeven
 }
@@ -574,15 +616,24 @@ define <2 x half> @v_roundeven_v2f16_fneg(<2 x half> %x) {
 ; GFX10-NEXT:    v_pack_b32_f16 v0, v1, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_roundeven_v2f16_fneg:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_rndne_f16_e32 v0, v0
-; GFX11-NEXT:    v_rndne_f16_e32 v1, v1
-; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_roundeven_v2f16_fneg:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
+; GFX11-TRUE16-NEXT:    v_rndne_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT:    v_rndne_f16_e32 v0.h, v0.h
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_roundeven_v2f16_fneg:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_rndne_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_rndne_f16_e32 v1, v1
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SDAG_GFX6-LABEL: v_roundeven_v2f16_fneg:
 ; SDAG_GFX6:       ; %bb.0:
@@ -638,14 +689,22 @@ define <2 x half> @v_roundeven_v2f16_fneg(<2 x half> %x) {
 ; SDAG_GFX10-NEXT:    v_pack_b32_f16 v0, v0, v1
 ; SDAG_GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; SDAG_GFX11-LABEL: v_roundeven_v2f16_fneg:
-; SDAG_GFX11:       ; %bb.0:
-; SDAG_GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG_GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; SDAG_GFX11-NEXT:    v_rndne_f16_e64 v0, -v0
-; SDAG_GFX11-NEXT:    v_rndne_f16_e64 v1, -v1
-; SDAG_GFX11-NEXT:    v_pack_b32_f16 v0, v0, v1
-; SDAG_GFX11-NEXT:    s_setpc_b64 s[30:31]
+; SDAG_GFX11-TRUE16-LABEL: v_roundeven_v2f16_fneg:
+; SDAG_GFX11-TRUE16:       ; %bb.0:
+; SDAG_GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG_GFX11-TRUE16-NEXT:    v_rndne_f16_e64 v0.h, -v0.h
+; SDAG_GFX11-TRUE16-NEXT:    v_rndne_f16_e64 v0.l, -v0.l
+; SDAG_GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; SDAG_GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG_GFX11-FAKE16-LABEL: v_roundeven_v2f16_fneg:
+; SDAG_GFX11-FAKE16:       ; %bb.0:
+; SDAG_GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG_GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; SDAG_GFX11-FAKE16-NEXT:    v_rndne_f16_e64 v0, -v0
+; SDAG_GFX11-FAKE16-NEXT:    v_rndne_f16_e64 v1, -v1
+; SDAG_GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
+; SDAG_GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %x.fneg = fneg <2 x half> %x
   %roundeven = call <2 x half> @llvm.roundeven.v2f16(<2 x half> %x.fneg)
   ret <2 x half> %roundeven
@@ -719,18 +778,29 @@ define <4 x half> @v_roundeven_v4f16(<4 x half> %x) {
 ; GFX10-NEXT:    v_pack_b32_f16 v1, v3, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_roundeven_v4f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-NEXT:    v_rndne_f16_e32 v0, v0
-; GFX11-NEXT:    v_rndne_f16_e32 v1, v1
-; GFX11-NEXT:    v_rndne_f16_e32 v2, v2
-; GFX11-NEXT:    v_rndne_f16_e32 v3, v3
-; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v2
-; GFX11-NEXT:    v_pack_b32_f16 v1, v1, v3
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_roundeven_v4f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_rndne_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT:    v_rndne_f16_e32 v0.h, v0.h
+; GFX11-TRUE16-NEXT:    v_rndne_f16_e32 v1.l, v1.l
+; GFX11-TRUE16-NEXT:    v_rndne_f16_e32 v1.h, v1.h
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.l, v1.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_roundeven_v4f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX11-FAKE16-NEXT:    v_rndne_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_rndne_f16_e32 v1, v1
+; GFX11-FAKE16-NEXT:    v_rndne_f16_e32 v2, v2
+; GFX11-FAKE16-NEXT:    v_rndne_f16_e32 v3, v3
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, v3
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SDAG_GFX6-LABEL: v_roundeven_v4f16:
 ; SDAG_GFX6:       ; %bb.0:
@@ -799,18 +869,29 @@ define <4 x half> @v_roundeven_v4f16(<4 x half> %x) {
 ; SDAG_GFX10-NEXT:    v_pack_b32_f16 v1, v1, v2
 ; SDAG_GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; SDAG_GFX11-LABEL: v_roundeven_v4f16:
-; SDAG_GFX11:       ; %bb.0:
-; SDAG_GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG_GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; SDAG_GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; SDAG_GFX11-NEXT:    v_rndne_f16_e32 v1, v1
-; SDAG_GFX11-NEXT:    v_rndne_f16_e32 v0, v0
-; SDAG_GFX11-NEXT:    v_rndne_f16_e32 v2, v2
-; SDAG_GFX11-NEXT:    v_rndne_f16_e32 v3, v3
-; SDAG_GFX11-NEXT:    v_pack_b32_f16 v0, v0, v2
-; SDAG_GFX11-NEXT:    v_pack_b32_f16 v1, v1, v3
-; SDAG_GFX11-NEXT:    s_setpc_b64 s[30:31]
+; SDAG_GFX11-TRUE16-LABEL: v_roundeven_v4f16:
+; SDAG_GFX11-TRUE16:       ; %bb.0:
+; SDAG_GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG_GFX11-TRUE16-NEXT:    v_rndne_f16_e32 v1.h, v1.h
+; SDAG_GFX11-TRUE16-NEXT:    v_rndne_f16_e32 v0.h, v0.h
+; SDAG_GFX11-TRUE16-NEXT:    v_rndne_f16_e32 v0.l, v0.l
+; SDAG_GFX11-TRUE16-NEXT:    v_rndne_f16_e32 v1.l, v1.l
+; SDAG_GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; SDAG_GFX11-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.l, v1.h
+; SDAG_GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG_GFX11-FAKE16-LABEL: v_roundeven_v4f16:
+; SDAG_GFX11-FAKE16:       ; %bb.0:
+; SDAG_GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG_GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; SDAG_GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; SDAG_GFX11-FAKE16-NEXT:    v_rndne_f16_e32 v1, v1
+; SDAG_GFX11-FAKE16-NEXT:    v_rndne_f16_e32 v0, v0
+; SDAG_GFX11-FAKE16-NEXT:    v_rndne_f16_e32 v2, v2
+; SDAG_GFX11-FAKE16-NEXT:    v_rndne_f16_e32 v3, v3
+; SDAG_GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v2
+; SDAG_GFX11-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, v3
+; SDAG_GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %roundeven = call <4 x half> @llvm.roundeven.v4f16(<4 x half> %x)
   ret <4 x half> %roundeven
 }
@@ -1289,3 +1370,6 @@ declare half @llvm.fabs.f16(half) #0
 declare float @llvm.fabs.f32(float) #0
 
 attributes #0 = { nounwind readnone speculatable willreturn }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11: {{.*}}
+; SDAG_GFX11: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll b/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
index 9a168c133c552..f7bd5f8d5bfb4 100644
--- a/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
@@ -1,7 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GFX7 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
 
 ; Test if fcmp+select patterns form min/max instructions when allowed
 ; by flags.
@@ -548,17 +549,29 @@ define half @v_test_fmin_legacy_ule_f16_safe(half %a, half %b) {
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: v_test_fmin_legacy_ule_f16_safe:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_test_fmin_legacy_ule_f16_safe:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_f16_safe:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = fcmp ule half %a, %b
   %val = select i1 %cmp, half %a, half %b
   ret half %val
@@ -582,17 +595,29 @@ define half @v_test_fmin_legacy_ule_f16_nnan_flag(half %a, half %b) {
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: v_test_fmin_legacy_ule_f16_nnan_flag:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_test_fmin_legacy_ule_f16_nnan_flag:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_f16_nnan_flag:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = fcmp ule half %a, %b
   %val = select nnan i1 %cmp, half %a, half %b
   ret half %val
@@ -616,17 +641,29 @@ define half @v_test_fmin_legacy_ule_f16_nsz_flag(half %a, half %b) {
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: v_test_fmin_legacy_ule_f16_nsz_flag:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_test_fmin_legacy_ule_f16_nsz_flag:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_f16_nsz_flag:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = fcmp ule half %a, %b
   %val = select nsz i1 %cmp, half %a, half %b
   ret half %val
@@ -649,15 +686,25 @@ define half @v_test_fmin_legacy_ule_f16_nnan_nsz_flag(half %a, half %b) {
 ; GFX9-NEXT:    v_min_f16_e32 v0, v0, v1
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: v_test_fmin_legacy_ule_f16_nnan_nsz_flag:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_min_num_f16_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_test_fmin_legacy_ule_f16_nnan_nsz_flag:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_f16_nnan_nsz_flag:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = fcmp ule half %a, %b
   %val = select nnan nsz i1 %cmp, half %a, half %b
   ret half %val
@@ -681,17 +728,29 @@ define half @v_test_fmax_legacy_uge_f16_safe(half %a, half %b) {
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: v_test_fmax_legacy_uge_f16_safe:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_test_fmax_legacy_uge_f16_safe:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_f16_safe:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = fcmp uge half %a, %b
   %val = select i1 %cmp, half %a, half %b
   ret half %val
@@ -715,17 +774,29 @@ define half @v_test_fmax_legacy_uge_f16_nnan_flag(half %a, half %b) {
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: v_test_fmax_legacy_uge_f16_nnan_flag:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_test_fmax_legacy_uge_f16_nnan_flag:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_f16_nnan_flag:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = fcmp uge half %a, %b
   %val = select nnan i1 %cmp, half %a, half %b
   ret half %val
@@ -749,17 +820,29 @@ define half @v_test_fmax_legacy_uge_f16_nsz_flag(half %a, half %b) {
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: v_test_fmax_legacy_uge_f16_nsz_flag:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_test_fmax_legacy_uge_f16_nsz_flag:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_f16_nsz_flag:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = fcmp uge half %a, %b
   %val = select nsz i1 %cmp, half %a, half %b
   ret half %val
@@ -782,15 +865,25 @@ define half @v_test_fmax_legacy_uge_f16_nnan_nsz_flag(half %a, half %b) {
 ; GFX9-NEXT:    v_max_f16_e32 v0, v0, v1
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: v_test_fmax_legacy_uge_f16_nnan_nsz_flag:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_max_num_f16_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_test_fmax_legacy_uge_f16_nnan_nsz_flag:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_f16_nnan_nsz_flag:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = fcmp uge half %a, %b
   %val = select nnan nsz i1 %cmp, half %a, half %b
   ret half %val
@@ -825,25 +918,40 @@ define <2 x half> @v_test_fmin_legacy_ule_v2f16_safe(<2 x half> %a, <2 x half> %
 ; GFX9-NEXT:    v_perm_b32 v0, v2, v0, s4
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: v_test_fmin_legacy_ule_v2f16_safe:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v3, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
-; GFX12-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_test_fmin_legacy_ule_v2f16_safe:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0.h, v1.h
+; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e64 s0, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, s0
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_v2f16_safe:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v3, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = fcmp ule <2 x half> %a, %b
   %val = select <2 x i1> %cmp, <2 x half> %a, <2 x half> %b
   ret <2 x half> %val
@@ -878,25 +986,40 @@ define <2 x half> @v_test_fmin_legacy_ule_v2f16_nnan_flag(<2 x half> %a, <2 x ha
 ; GFX9-NEXT:    v_perm_b32 v0, v2, v0, s4
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: v_test_fmin_legacy_ule_v2f16_nnan_flag:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v3, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
-; GFX12-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_test_fmin_legacy_ule_v2f16_nnan_flag:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0.h, v1.h
+; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e64 s0, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, s0
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_v2f16_nnan_flag:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v3, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = fcmp ule <2 x half> %a, %b
   %val = select nnan <2 x i1> %cmp, <2 x half> %a, <2 x half> %b
   ret <2 x half> %val
@@ -931,25 +1054,40 @@ define <2 x half> @v_test_fmin_legacy_ule_v2f16_nsz_flag(<2 x half> %a, <2 x hal
 ; GFX9-NEXT:    v_perm_b32 v0, v2, v0, s4
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: v_test_fmin_legacy_ule_v2f16_nsz_flag:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v3, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
-; GFX12-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_test_fmin_legacy_ule_v2f16_nsz_flag:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0.h, v1.h
+; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e64 s0, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, s0
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_v2f16_nsz_flag:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v3, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = fcmp ule <2 x half> %a, %b
   %val = select nsz <2 x i1> %cmp, <2 x half> %a, <2 x half> %b
   ret <2 x half> %val
@@ -1020,25 +1158,40 @@ define <2 x half> @v_test_fmax_legacy_uge_v2f16_safe(<2 x half> %a, <2 x half> %
 ; GFX9-NEXT:    v_perm_b32 v0, v2, v0, s4
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: v_test_fmax_legacy_uge_v2f16_safe:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v3, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
-; GFX12-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_test_fmax_legacy_uge_v2f16_safe:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0.h, v1.h
+; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e64 s0, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, s0
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_v2f16_safe:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v3, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = fcmp uge <2 x half> %a, %b
   %val = select <2 x i1> %cmp, <2 x half> %a, <2 x half> %b
   ret <2 x half> %val
@@ -1073,25 +1226,40 @@ define <2 x half> @v_test_fmax_legacy_uge_v2f16_nnan_flag(<2 x half> %a, <2 x ha
 ; GFX9-NEXT:    v_perm_b32 v0, v2, v0, s4
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: v_test_fmax_legacy_uge_v2f16_nnan_flag:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v3, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
-; GFX12-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_test_fmax_legacy_uge_v2f16_nnan_flag:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0.h, v1.h
+; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e64 s0, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, s0
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_v2f16_nnan_flag:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v3, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = fcmp uge <2 x half> %a, %b
   %val = select nnan <2 x i1> %cmp, <2 x half> %a, <2 x half> %b
   ret <2 x half> %val
@@ -1126,25 +1294,40 @@ define <2 x half> @v_test_fmax_legacy_uge_v2f16_nsz_flag(<2 x half> %a, <2 x hal
 ; GFX9-NEXT:    v_perm_b32 v0, v2, v0, s4
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: v_test_fmax_legacy_uge_v2f16_nsz_flag:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v3, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
-; GFX12-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v1
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_test_fmax_legacy_uge_v2f16_nsz_flag:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0.h, v1.h
+; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e64 s0, v0.l, v1.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, s0
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_v2f16_nsz_flag:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v3, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v1
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = fcmp uge <2 x half> %a, %b
   %val = select nsz <2 x i1> %cmp, <2 x half> %a, <2 x half> %b
   ret <2 x half> %val
@@ -1232,34 +1415,53 @@ define <4 x half> @v_test_fmin_legacy_ule_v4f16_safe(<4 x half> %a, <4 x half> %
 ; GFX9-NEXT:    v_perm_b32 v1, v6, v1, s4
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: v_test_fmin_legacy_ule_v4f16_safe:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v4, 16, v3
-; GFX12-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
-; GFX12-NEXT:    v_lshrrev_b32_e32 v7, 16, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX12-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v5, v4
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc_lo
-; GFX12-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v7, v6
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v5, v6, v7, vcc_lo
-; GFX12-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX12-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v1, v3
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_perm_b32 v0, v5, v0, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v1, v4, v1, 0x5040100
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_test_fmin_legacy_ule_v4f16_safe:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v1.h, v3.h
+; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e64 s0, v0.h, v2.h
+; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e64 s1, v0.l, v2.l
+; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e64 s2, v1.l, v3.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v2.h, v0.h, s0
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.l, v0.l, s1
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, v1.l, s2
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_v4f16_safe:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v3
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v5, v4
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v7, v6
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v6, v7, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v1, v3
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v5, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v4, v1, 0x5040100
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = fcmp ule <4 x half> %a, %b
   %val = select <4 x i1> %cmp, <4 x half> %a, <4 x half> %b
   ret <4 x half> %val
@@ -1311,34 +1513,53 @@ define <4 x half> @v_test_fmin_legacy_ule_v4f16_nnan_flag(<4 x half> %a, <4 x ha
 ; GFX9-NEXT:    v_perm_b32 v1, v6, v1, s4
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_flag:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v4, 16, v3
-; GFX12-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
-; GFX12-NEXT:    v_lshrrev_b32_e32 v7, 16, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX12-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v5, v4
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc_lo
-; GFX12-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v7, v6
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v5, v6, v7, vcc_lo
-; GFX12-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX12-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v1, v3
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_perm_b32 v0, v5, v0, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v1, v4, v1, 0x5040100
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_flag:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v1.h, v3.h
+; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e64 s0, v0.h, v2.h
+; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e64 s1, v0.l, v2.l
+; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e64 s2, v1.l, v3.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v2.h, v0.h, s0
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.l, v0.l, s1
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, v1.l, s2
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_flag:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v3
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v5, v4
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v7, v6
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v6, v7, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v1, v3
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v5, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v4, v1, 0x5040100
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = fcmp ule <4 x half> %a, %b
   %val = select nnan <4 x i1> %cmp, <4 x half> %a, <4 x half> %b
   ret <4 x half> %val
@@ -1390,34 +1611,53 @@ define <4 x half> @v_test_fmin_legacy_ule_v4f16_nsz_flag(<4 x half> %a, <4 x hal
 ; GFX9-NEXT:    v_perm_b32 v1, v6, v1, s4
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: v_test_fmin_legacy_ule_v4f16_nsz_flag:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v4, 16, v3
-; GFX12-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
-; GFX12-NEXT:    v_lshrrev_b32_e32 v7, 16, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX12-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v5, v4
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc_lo
-; GFX12-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v7, v6
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v5, v6, v7, vcc_lo
-; GFX12-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX12-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v1, v3
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_perm_b32 v0, v5, v0, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v1, v4, v1, 0x5040100
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_test_fmin_legacy_ule_v4f16_nsz_flag:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v1.h, v3.h
+; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e64 s0, v0.h, v2.h
+; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e64 s1, v0.l, v2.l
+; GFX12-TRUE16-NEXT:    v_cmp_ngt_f16_e64 s2, v1.l, v3.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v2.h, v0.h, s0
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.l, v0.l, s1
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, v1.l, s2
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_v4f16_nsz_flag:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v3
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v5, v4
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v7, v6
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v6, v7, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v0, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, v1, v3
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v5, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v4, v1, 0x5040100
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = fcmp ule <4 x half> %a, %b
   %val = select nsz <4 x i1> %cmp, <4 x half> %a, <4 x half> %b
   ret <4 x half> %val
@@ -1517,34 +1757,53 @@ define <4 x half> @v_test_fmax_legacy_uge_v4f16_safe(<4 x half> %a, <4 x half> %
 ; GFX9-NEXT:    v_perm_b32 v1, v6, v1, s4
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: v_test_fmax_legacy_uge_v4f16_safe:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v4, 16, v3
-; GFX12-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
-; GFX12-NEXT:    v_lshrrev_b32_e32 v7, 16, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX12-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v5, v4
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc_lo
-; GFX12-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v7, v6
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v5, v6, v7, vcc_lo
-; GFX12-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX12-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v1, v3
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_perm_b32 v0, v5, v0, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v1, v4, v1, 0x5040100
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_test_fmax_legacy_uge_v4f16_safe:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v1.h, v3.h
+; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e64 s0, v0.h, v2.h
+; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e64 s1, v0.l, v2.l
+; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e64 s2, v1.l, v3.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v2.h, v0.h, s0
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.l, v0.l, s1
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, v1.l, s2
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_v4f16_safe:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v3
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v5, v4
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v7, v6
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v6, v7, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v1, v3
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v5, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v4, v1, 0x5040100
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = fcmp uge <4 x half> %a, %b
   %val = select <4 x i1> %cmp, <4 x half> %a, <4 x half> %b
   ret <4 x half> %val
@@ -1596,34 +1855,53 @@ define <4 x half> @v_test_fmax_legacy_uge_v4f16_nnan_flag(<4 x half> %a, <4 x ha
 ; GFX9-NEXT:    v_perm_b32 v1, v6, v1, s4
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_flag:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v4, 16, v3
-; GFX12-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
-; GFX12-NEXT:    v_lshrrev_b32_e32 v7, 16, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX12-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v5, v4
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc_lo
-; GFX12-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v7, v6
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v5, v6, v7, vcc_lo
-; GFX12-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX12-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v1, v3
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_perm_b32 v0, v5, v0, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v1, v4, v1, 0x5040100
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_flag:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v1.h, v3.h
+; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e64 s0, v0.h, v2.h
+; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e64 s1, v0.l, v2.l
+; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e64 s2, v1.l, v3.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v2.h, v0.h, s0
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.l, v0.l, s1
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, v1.l, s2
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_flag:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v3
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v5, v4
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v7, v6
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v6, v7, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v1, v3
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v5, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v4, v1, 0x5040100
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = fcmp uge <4 x half> %a, %b
   %val = select nnan <4 x i1> %cmp, <4 x half> %a, <4 x half> %b
   ret <4 x half> %val
@@ -1675,34 +1953,53 @@ define <4 x half> @v_test_fmax_legacy_uge_v4f16_nsz_flag(<4 x half> %a, <4 x hal
 ; GFX9-NEXT:    v_perm_b32 v1, v6, v1, s4
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: v_test_fmax_legacy_uge_v4f16_nsz_flag:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v4, 16, v3
-; GFX12-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
-; GFX12-NEXT:    v_lshrrev_b32_e32 v7, 16, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX12-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v5, v4
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc_lo
-; GFX12-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v7, v6
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v5, v6, v7, vcc_lo
-; GFX12-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v2
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX12-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v1, v3
-; GFX12-NEXT:    s_wait_alu 0xfffd
-; GFX12-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_perm_b32 v0, v5, v0, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v1, v4, v1, 0x5040100
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_test_fmax_legacy_uge_v4f16_nsz_flag:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v1.h, v3.h
+; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e64 s0, v0.h, v2.h
+; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e64 s1, v0.l, v2.l
+; GFX12-TRUE16-NEXT:    v_cmp_nlt_f16_e64 s2, v1.l, v3.l
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
+; GFX12-TRUE16-NEXT:    s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v2.h, v0.h, s0
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.l, v0.l, s1
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.l, v1.l, s2
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_v4f16_nsz_flag:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v3
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
+; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v5, v4
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v7, v6
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v6, v7, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v2
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX12-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v1, v3
+; GFX12-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v5, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v4, v1, 0x5040100
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = fcmp uge <4 x half> %a, %b
   %val = select nsz <4 x i1> %cmp, <4 x half> %a, <4 x half> %b
   ret <4 x half> %val
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll b/llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
index cdfba3cf0db7f..6d69b4ca6fa3e 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
@@ -231,5 +231,3 @@ ret:
 attributes #0 = { nounwind }
 attributes #1 = { nounwind "amdgpu-waves-per-eu"="10,10" }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll b/llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
index 47810346c50b7..c4610200d18a0 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
@@ -45,5 +45,3 @@ define amdgpu_kernel void @kernel() {
   ret void
 }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll b/llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
index 3c47e2504747d..2e3693b7250f3 100644
--- a/llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
@@ -63,13 +63,8 @@ define amdgpu_kernel void @test_simple_indirect_call() {
 }
 
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
 ;.
 ;.
 ; ATTRIBUTOR_GCN: attributes #[[ATTR0]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
 ; ATTRIBUTOR_GCN: attributes #[[ATTR1]] = { "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
 ;.
-;.
-; ATTRIBUTOR_GCN: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 500}
-;.
diff --git a/llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll b/llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
index a83ed902f1c9d..ebe6b232bfcbc 100644
--- a/llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
@@ -1,7 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX8 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11,GFX11-FAKE16 %s
 
 ; FIXME: This should be merged with sint_to_fp.ll, but s_sint_to_fp_v2i64 crashes on r600
 
@@ -52,31 +53,57 @@ define amdgpu_kernel void @s_sint_to_fp_i64_to_f16(ptr addrspace(1) %out, i64 %i
 ; GFX8-NEXT:    flat_store_short v[0:1], v2
 ; GFX8-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: s_sint_to_fp_i64_to_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v1, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_xor_b32 s4, s2, s3
-; GFX11-NEXT:    s_cls_i32 s5, s3
-; GFX11-NEXT:    s_ashr_i32 s4, s4, 31
-; GFX11-NEXT:    s_add_i32 s5, s5, -1
-; GFX11-NEXT:    s_add_i32 s4, s4, 32
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT:    s_min_u32 s4, s5, s4
-; GFX11-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT:    s_min_u32 s2, s2, 1
-; GFX11-NEXT:    s_or_b32 s2, s3, s2
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    v_cvt_f32_i32_e32 v0, s2
-; GFX11-NEXT:    s_sub_i32 s2, 32, s4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT:    v_ldexp_f32 v0, v0, s2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    global_store_b16 v1, v0, s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: s_sint_to_fp_i64_to_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s4, s2, s3
+; GFX11-TRUE16-NEXT:    s_cls_i32 s5, s3
+; GFX11-TRUE16-NEXT:    s_ashr_i32 s4, s4, 31
+; GFX11-TRUE16-NEXT:    s_add_i32 s5, s5, -1
+; GFX11-TRUE16-NEXT:    s_add_i32 s4, s4, 32
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_min_u32 s4, s5, s4
+; GFX11-TRUE16-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_min_u32 s2, s2, 1
+; GFX11-TRUE16-NEXT:    s_or_b32 s2, s3, s2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_i32_e32 v0, s2
+; GFX11-TRUE16-NEXT:    s_sub_i32 s2, 32, s4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v0, v0, s2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: s_sint_to_fp_i64_to_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s4, s2, s3
+; GFX11-FAKE16-NEXT:    s_cls_i32 s5, s3
+; GFX11-FAKE16-NEXT:    s_ashr_i32 s4, s4, 31
+; GFX11-FAKE16-NEXT:    s_add_i32 s5, s5, -1
+; GFX11-FAKE16-NEXT:    s_add_i32 s4, s4, 32
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_min_u32 s4, s5, s4
+; GFX11-FAKE16-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_min_u32 s2, s2, 1
+; GFX11-FAKE16-NEXT:    s_or_b32 s2, s3, s2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_i32_e32 v0, s2
+; GFX11-FAKE16-NEXT:    s_sub_i32 s2, 32, s4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v0, v0, s2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %result = sitofp i64 %in to half
   store half %result, ptr addrspace(1) %out
   ret void
@@ -142,36 +169,67 @@ define amdgpu_kernel void @v_sint_to_fp_i64_to_f16(ptr addrspace(1) %out, ptr ad
 ; GFX8-NEXT:    flat_store_short v[0:1], v3
 ; GFX8-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: v_sint_to_fp_i64_to_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT:    v_and_b32_e32 v2, 0x3ff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 3, v2
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[0:1], v0, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_xor_b32_e32 v3, v0, v1
-; GFX11-NEXT:    v_cls_i32_e32 v4, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_ashrrev_i32_e32 v3, 31, v3
-; GFX11-NEXT:    v_add_nc_u32_e32 v4, -1, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add_nc_u32_e32 v3, 32, v3
-; GFX11-NEXT:    v_min_u32_e32 v3, v4, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_lshlrev_b64 v[0:1], v3, v[0:1]
-; GFX11-NEXT:    v_min_u32_e32 v0, 1, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT:    v_sub_nc_u32_e32 v1, 32, v3
-; GFX11-NEXT:    v_cvt_f32_i32_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_ldexp_f32 v0, v0, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 1, v2
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    global_store_b16 v1, v0, s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: v_sint_to_fp_i64_to_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0x3ff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 3, v2
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b64 v[0:1], v0, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_xor_b32_e32 v3, v0, v1
+; GFX11-TRUE16-NEXT:    v_cls_i32_e32 v4, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_ashrrev_i32_e32 v3, 31, v3
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v4, -1, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 32, v3
+; GFX11-TRUE16-NEXT:    v_min_u32_e32 v3, v4, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b64 v[0:1], v3, v[0:1]
+; GFX11-TRUE16-NEXT:    v_min_u32_e32 v0, 1, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v1, v0
+; GFX11-TRUE16-NEXT:    v_sub_nc_u32_e32 v1, 32, v3
+; GFX11-TRUE16-NEXT:    v_cvt_f32_i32_e32 v0, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v0, v0, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v2
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: v_sint_to_fp_i64_to_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0x3ff, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 3, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[0:1], v0, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v3, v0, v1
+; GFX11-FAKE16-NEXT:    v_cls_i32_e32 v4, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_ashrrev_i32_e32 v3, 31, v3
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, -1, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, 32, v3
+; GFX11-FAKE16-NEXT:    v_min_u32_e32 v3, v4, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b64 v[0:1], v3, v[0:1]
+; GFX11-FAKE16-NEXT:    v_min_u32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT:    v_sub_nc_u32_e32 v1, 32, v3
+; GFX11-FAKE16-NEXT:    v_cvt_f32_i32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %in.gep = getelementptr i64, ptr addrspace(1) %in, i32 %tid
   %out.gep = getelementptr half, ptr addrspace(1) %out, i32 %tid
@@ -747,45 +805,85 @@ define amdgpu_kernel void @s_sint_to_fp_v2i64_to_v2f16(ptr addrspace(1) %out, <2
 ; GFX8-NEXT:    flat_store_dword v[0:1], v2
 ; GFX8-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: s_sint_to_fp_v2i64_to_v2f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x34
-; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v2, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_xor_b32 s7, s2, s3
-; GFX11-NEXT:    s_xor_b32 s9, s0, s1
-; GFX11-NEXT:    s_cls_i32 s6, s3
-; GFX11-NEXT:    s_cls_i32 s8, s1
-; GFX11-NEXT:    s_ashr_i32 s7, s7, 31
-; GFX11-NEXT:    s_ashr_i32 s9, s9, 31
-; GFX11-NEXT:    s_add_i32 s6, s6, -1
-; GFX11-NEXT:    s_add_i32 s8, s8, -1
-; GFX11-NEXT:    s_add_i32 s7, s7, 32
-; GFX11-NEXT:    s_add_i32 s9, s9, 32
-; GFX11-NEXT:    s_min_u32 s6, s6, s7
-; GFX11-NEXT:    s_min_u32 s7, s8, s9
-; GFX11-NEXT:    s_lshl_b64 s[2:3], s[2:3], s6
-; GFX11-NEXT:    s_lshl_b64 s[0:1], s[0:1], s7
-; GFX11-NEXT:    s_min_u32 s2, s2, 1
-; GFX11-NEXT:    s_min_u32 s0, s0, 1
-; GFX11-NEXT:    s_or_b32 s2, s3, s2
-; GFX11-NEXT:    s_or_b32 s0, s1, s0
-; GFX11-NEXT:    v_cvt_f32_i32_e32 v0, s2
-; GFX11-NEXT:    v_cvt_f32_i32_e32 v1, s0
-; GFX11-NEXT:    s_sub_i32 s0, 32, s6
-; GFX11-NEXT:    s_sub_i32 s1, 32, s7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_ldexp_f32 v0, v0, s0
-; GFX11-NEXT:    v_ldexp_f32 v1, v1, s1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_pack_b32_f16 v0, v1, v0
-; GFX11-NEXT:    global_store_b32 v2, v0, s[4:5]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: s_sint_to_fp_v2i64_to_v2f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x34
+; GFX11-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_xor_b32 s7, s2, s3
+; GFX11-TRUE16-NEXT:    s_xor_b32 s9, s0, s1
+; GFX11-TRUE16-NEXT:    s_cls_i32 s6, s3
+; GFX11-TRUE16-NEXT:    s_cls_i32 s8, s1
+; GFX11-TRUE16-NEXT:    s_ashr_i32 s7, s7, 31
+; GFX11-TRUE16-NEXT:    s_ashr_i32 s9, s9, 31
+; GFX11-TRUE16-NEXT:    s_add_i32 s6, s6, -1
+; GFX11-TRUE16-NEXT:    s_add_i32 s8, s8, -1
+; GFX11-TRUE16-NEXT:    s_add_i32 s7, s7, 32
+; GFX11-TRUE16-NEXT:    s_add_i32 s9, s9, 32
+; GFX11-TRUE16-NEXT:    s_min_u32 s6, s6, s7
+; GFX11-TRUE16-NEXT:    s_min_u32 s7, s8, s9
+; GFX11-TRUE16-NEXT:    s_lshl_b64 s[2:3], s[2:3], s6
+; GFX11-TRUE16-NEXT:    s_lshl_b64 s[0:1], s[0:1], s7
+; GFX11-TRUE16-NEXT:    s_min_u32 s2, s2, 1
+; GFX11-TRUE16-NEXT:    s_min_u32 s0, s0, 1
+; GFX11-TRUE16-NEXT:    s_or_b32 s2, s3, s2
+; GFX11-TRUE16-NEXT:    s_or_b32 s0, s1, s0
+; GFX11-TRUE16-NEXT:    v_cvt_f32_i32_e32 v0, s2
+; GFX11-TRUE16-NEXT:    v_cvt_f32_i32_e32 v1, s0
+; GFX11-TRUE16-NEXT:    s_sub_i32 s0, 32, s6
+; GFX11-TRUE16-NEXT:    s_sub_i32 s1, 32, s7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v0, v0, s0
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v1, v1, s1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v1
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v0.l
+; GFX11-TRUE16-NEXT:    global_store_b32 v1, v0, s[4:5]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: s_sint_to_fp_v2i64_to_v2f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x34
+; GFX11-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_xor_b32 s7, s2, s3
+; GFX11-FAKE16-NEXT:    s_xor_b32 s9, s0, s1
+; GFX11-FAKE16-NEXT:    s_cls_i32 s6, s3
+; GFX11-FAKE16-NEXT:    s_cls_i32 s8, s1
+; GFX11-FAKE16-NEXT:    s_ashr_i32 s7, s7, 31
+; GFX11-FAKE16-NEXT:    s_ashr_i32 s9, s9, 31
+; GFX11-FAKE16-NEXT:    s_add_i32 s6, s6, -1
+; GFX11-FAKE16-NEXT:    s_add_i32 s8, s8, -1
+; GFX11-FAKE16-NEXT:    s_add_i32 s7, s7, 32
+; GFX11-FAKE16-NEXT:    s_add_i32 s9, s9, 32
+; GFX11-FAKE16-NEXT:    s_min_u32 s6, s6, s7
+; GFX11-FAKE16-NEXT:    s_min_u32 s7, s8, s9
+; GFX11-FAKE16-NEXT:    s_lshl_b64 s[2:3], s[2:3], s6
+; GFX11-FAKE16-NEXT:    s_lshl_b64 s[0:1], s[0:1], s7
+; GFX11-FAKE16-NEXT:    s_min_u32 s2, s2, 1
+; GFX11-FAKE16-NEXT:    s_min_u32 s0, s0, 1
+; GFX11-FAKE16-NEXT:    s_or_b32 s2, s3, s2
+; GFX11-FAKE16-NEXT:    s_or_b32 s0, s1, s0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_i32_e32 v0, s2
+; GFX11-FAKE16-NEXT:    v_cvt_f32_i32_e32 v1, s0
+; GFX11-FAKE16-NEXT:    s_sub_i32 s0, 32, s6
+; GFX11-FAKE16-NEXT:    s_sub_i32 s1, 32, s7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v0, v0, s0
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v1, v1, s1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v1, v0
+; GFX11-FAKE16-NEXT:    global_store_b32 v2, v0, s[4:5]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %result = sitofp <2 x i64> %in to <2 x half>
   store <2 x half> %result, ptr addrspace(1) %out
   ret void
@@ -942,82 +1040,161 @@ define amdgpu_kernel void @v_sint_to_fp_v4i64_to_v4f16(ptr addrspace(1) %out, pt
 ; GFX8-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
 ; GFX8-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: v_sint_to_fp_v4i64_to_v4f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT:    v_and_b32_e32 v8, 0x3ff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 5, v8
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_load_b128 v[0:3], v4, s[2:3] offset:16
-; GFX11-NEXT:    global_load_b128 v[4:7], v4, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_xor_b32_e32 v9, v2, v3
-; GFX11-NEXT:    v_xor_b32_e32 v11, v0, v1
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_xor_b32_e32 v13, v6, v7
-; GFX11-NEXT:    v_xor_b32_e32 v15, v4, v5
-; GFX11-NEXT:    v_cls_i32_e32 v10, v3
-; GFX11-NEXT:    v_cls_i32_e32 v12, v1
-; GFX11-NEXT:    v_cls_i32_e32 v14, v7
-; GFX11-NEXT:    v_cls_i32_e32 v16, v5
-; GFX11-NEXT:    v_ashrrev_i32_e32 v9, 31, v9
-; GFX11-NEXT:    v_ashrrev_i32_e32 v11, 31, v11
-; GFX11-NEXT:    v_ashrrev_i32_e32 v13, 31, v13
-; GFX11-NEXT:    v_ashrrev_i32_e32 v15, 31, v15
-; GFX11-NEXT:    v_add_nc_u32_e32 v10, -1, v10
-; GFX11-NEXT:    v_add_nc_u32_e32 v12, -1, v12
-; GFX11-NEXT:    v_add_nc_u32_e32 v14, -1, v14
-; GFX11-NEXT:    v_add_nc_u32_e32 v16, -1, v16
-; GFX11-NEXT:    v_add_nc_u32_e32 v9, 32, v9
-; GFX11-NEXT:    v_add_nc_u32_e32 v11, 32, v11
-; GFX11-NEXT:    v_add_nc_u32_e32 v13, 32, v13
-; GFX11-NEXT:    v_add_nc_u32_e32 v15, 32, v15
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_min_u32_e32 v9, v10, v9
-; GFX11-NEXT:    v_min_u32_e32 v10, v12, v11
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_min_u32_e32 v11, v14, v13
-; GFX11-NEXT:    v_min_u32_e32 v12, v16, v15
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshlrev_b64 v[2:3], v9, v[2:3]
-; GFX11-NEXT:    v_lshlrev_b64 v[0:1], v10, v[0:1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshlrev_b64 v[6:7], v11, v[6:7]
-; GFX11-NEXT:    v_lshlrev_b64 v[4:5], v12, v[4:5]
-; GFX11-NEXT:    v_sub_nc_u32_e32 v9, 32, v9
-; GFX11-NEXT:    v_sub_nc_u32_e32 v10, 32, v10
-; GFX11-NEXT:    v_min_u32_e32 v2, 1, v2
-; GFX11-NEXT:    v_min_u32_e32 v0, 1, v0
-; GFX11-NEXT:    v_min_u32_e32 v6, 1, v6
-; GFX11-NEXT:    v_min_u32_e32 v4, 1, v4
-; GFX11-NEXT:    v_sub_nc_u32_e32 v11, 32, v11
-; GFX11-NEXT:    v_or_b32_e32 v2, v3, v2
-; GFX11-NEXT:    v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v7, v6
-; GFX11-NEXT:    v_or_b32_e32 v3, v5, v4
-; GFX11-NEXT:    v_sub_nc_u32_e32 v4, 32, v12
-; GFX11-NEXT:    v_cvt_f32_i32_e32 v2, v2
-; GFX11-NEXT:    v_cvt_f32_i32_e32 v0, v0
-; GFX11-NEXT:    v_cvt_f32_i32_e32 v1, v1
-; GFX11-NEXT:    v_cvt_f32_i32_e32 v3, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 3, v8
-; GFX11-NEXT:    v_ldexp_f32 v2, v2, v9
-; GFX11-NEXT:    v_ldexp_f32 v0, v0, v10
-; GFX11-NEXT:    v_ldexp_f32 v1, v1, v11
-; GFX11-NEXT:    v_ldexp_f32 v3, v3, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v4, v1
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v3, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_pack_b32_f16 v1, v0, v2
-; GFX11-NEXT:    v_pack_b32_f16 v0, v3, v4
-; GFX11-NEXT:    global_store_b64 v5, v[0:1], s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: v_sint_to_fp_v4i64_to_v4f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0x3ff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 5, v8
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    global_load_b128 v[0:3], v4, s[2:3] offset:16
+; GFX11-TRUE16-NEXT:    global_load_b128 v[4:7], v4, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_xor_b32_e32 v9, v2, v3
+; GFX11-TRUE16-NEXT:    v_xor_b32_e32 v11, v0, v1
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_xor_b32_e32 v13, v6, v7
+; GFX11-TRUE16-NEXT:    v_xor_b32_e32 v15, v4, v5
+; GFX11-TRUE16-NEXT:    v_cls_i32_e32 v10, v3
+; GFX11-TRUE16-NEXT:    v_cls_i32_e32 v12, v1
+; GFX11-TRUE16-NEXT:    v_cls_i32_e32 v14, v7
+; GFX11-TRUE16-NEXT:    v_cls_i32_e32 v16, v5
+; GFX11-TRUE16-NEXT:    v_ashrrev_i32_e32 v9, 31, v9
+; GFX11-TRUE16-NEXT:    v_ashrrev_i32_e32 v11, 31, v11
+; GFX11-TRUE16-NEXT:    v_ashrrev_i32_e32 v13, 31, v13
+; GFX11-TRUE16-NEXT:    v_ashrrev_i32_e32 v15, 31, v15
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v10, -1, v10
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v12, -1, v12
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v14, -1, v14
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v16, -1, v16
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v9, 32, v9
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v11, 32, v11
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v13, 32, v13
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v15, 32, v15
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_min_u32_e32 v9, v10, v9
+; GFX11-TRUE16-NEXT:    v_min_u32_e32 v10, v12, v11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_min_u32_e32 v11, v14, v13
+; GFX11-TRUE16-NEXT:    v_min_u32_e32 v12, v16, v15
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b64 v[2:3], v9, v[2:3]
+; GFX11-TRUE16-NEXT:    v_lshlrev_b64 v[0:1], v10, v[0:1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b64 v[6:7], v11, v[6:7]
+; GFX11-TRUE16-NEXT:    v_lshlrev_b64 v[4:5], v12, v[4:5]
+; GFX11-TRUE16-NEXT:    v_sub_nc_u32_e32 v9, 32, v9
+; GFX11-TRUE16-NEXT:    v_sub_nc_u32_e32 v10, 32, v10
+; GFX11-TRUE16-NEXT:    v_min_u32_e32 v2, 1, v2
+; GFX11-TRUE16-NEXT:    v_min_u32_e32 v0, 1, v0
+; GFX11-TRUE16-NEXT:    v_min_u32_e32 v6, 1, v6
+; GFX11-TRUE16-NEXT:    v_min_u32_e32 v4, 1, v4
+; GFX11-TRUE16-NEXT:    v_sub_nc_u32_e32 v11, 32, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v3, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v1, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v7, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v5, v4
+; GFX11-TRUE16-NEXT:    v_sub_nc_u32_e32 v4, 32, v12
+; GFX11-TRUE16-NEXT:    v_cvt_f32_i32_e32 v2, v2
+; GFX11-TRUE16-NEXT:    v_cvt_f32_i32_e32 v0, v0
+; GFX11-TRUE16-NEXT:    v_cvt_f32_i32_e32 v1, v1
+; GFX11-TRUE16-NEXT:    v_cvt_f32_i32_e32 v3, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v2, v2, v9
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v5, v0, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v1, v1, v11
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v3, v3, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v2
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v1.l, v1
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v1.h, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 3, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v2, v0.h, v0.l
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.h, v1.l
+; GFX11-TRUE16-NEXT:    global_store_b64 v3, v[1:2], s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: v_sint_to_fp_v4i64_to_v4f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0x3ff, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 5, v8
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    global_load_b128 v[0:3], v4, s[2:3] offset:16
+; GFX11-FAKE16-NEXT:    global_load_b128 v[4:7], v4, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v9, v2, v3
+; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v11, v0, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v13, v6, v7
+; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v15, v4, v5
+; GFX11-FAKE16-NEXT:    v_cls_i32_e32 v10, v3
+; GFX11-FAKE16-NEXT:    v_cls_i32_e32 v12, v1
+; GFX11-FAKE16-NEXT:    v_cls_i32_e32 v14, v7
+; GFX11-FAKE16-NEXT:    v_cls_i32_e32 v16, v5
+; GFX11-FAKE16-NEXT:    v_ashrrev_i32_e32 v9, 31, v9
+; GFX11-FAKE16-NEXT:    v_ashrrev_i32_e32 v11, 31, v11
+; GFX11-FAKE16-NEXT:    v_ashrrev_i32_e32 v13, 31, v13
+; GFX11-FAKE16-NEXT:    v_ashrrev_i32_e32 v15, 31, v15
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v10, -1, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v12, -1, v12
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v14, -1, v14
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v16, -1, v16
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v9, 32, v9
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v11, 32, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v13, 32, v13
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v15, 32, v15
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_min_u32_e32 v9, v10, v9
+; GFX11-FAKE16-NEXT:    v_min_u32_e32 v10, v12, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_min_u32_e32 v11, v14, v13
+; GFX11-FAKE16-NEXT:    v_min_u32_e32 v12, v16, v15
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b64 v[2:3], v9, v[2:3]
+; GFX11-FAKE16-NEXT:    v_lshlrev_b64 v[0:1], v10, v[0:1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b64 v[6:7], v11, v[6:7]
+; GFX11-FAKE16-NEXT:    v_lshlrev_b64 v[4:5], v12, v[4:5]
+; GFX11-FAKE16-NEXT:    v_sub_nc_u32_e32 v9, 32, v9
+; GFX11-FAKE16-NEXT:    v_sub_nc_u32_e32 v10, 32, v10
+; GFX11-FAKE16-NEXT:    v_min_u32_e32 v2, 1, v2
+; GFX11-FAKE16-NEXT:    v_min_u32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT:    v_min_u32_e32 v6, 1, v6
+; GFX11-FAKE16-NEXT:    v_min_u32_e32 v4, 1, v4
+; GFX11-FAKE16-NEXT:    v_sub_nc_u32_e32 v11, 32, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v7, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v5, v4
+; GFX11-FAKE16-NEXT:    v_sub_nc_u32_e32 v4, 32, v12
+; GFX11-FAKE16-NEXT:    v_cvt_f32_i32_e32 v2, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f32_i32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_i32_e32 v1, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f32_i32_e32 v3, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 3, v8
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v2, v2, v9
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v0, v0, v10
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v1, v1, v11
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v3, v3, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v4, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v1, v0, v2
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v3, v4
+; GFX11-FAKE16-NEXT:    global_store_b64 v5, v[0:1], s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %in.gep = getelementptr <4 x i64>, ptr addrspace(1) %in, i32 %tid
   %out.gep = getelementptr <4 x half>, ptr addrspace(1) %out, i32 %tid
diff --git a/llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll b/llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
index e59e3f6de697f..1aec329ac483c 100644
--- a/llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
+++ b/llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
@@ -23,5 +23,3 @@ define amdgpu_kernel void @test_sopk_size(i32 %var.mode) {
 
 declare void @llvm.amdgcn.s.setreg(i32 immarg, i32)
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/spill-m0.ll b/llvm/test/CodeGen/AMDGPU/spill-m0.ll
index 3abd1562dbbd8..72254023bb9de 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-m0.ll
+++ b/llvm/test/CodeGen/AMDGPU/spill-m0.ll
@@ -191,5 +191,3 @@ declare float @llvm.amdgcn.wqm.f32(float) #1
 attributes #0 = { nounwind }
 attributes #1 = { nounwind readnone }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll b/llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
index 8f16fcf6d0890..d2394bab82c77 100644
--- a/llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
+++ b/llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
@@ -1672,8 +1672,6 @@ define void @func_stacksave_stackrestore_call_with_stack_objects() {
   ret void
 }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
 
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; WAVE32: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll b/llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
index ef92cf3214e7f..92918f19a98a5 100644
--- a/llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
+++ b/llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
@@ -3,7 +3,8 @@
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CIVI,FIJI %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX9 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX10 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX11 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define void @local_store_i56(ptr addrspace(3) %ptr, i56 %arg) #0 {
 ; CIVI-LABEL: local_store_i56:
@@ -334,13 +335,21 @@ define void @local_store_i13(ptr addrspace(3) %ptr, i13 %arg) #0 {
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: local_store_i13:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v1, 0x1fff, v1
-; GFX11-NEXT:    ds_store_b16 v0, v1
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: local_store_i13:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v1.l, 0x1fff, v1.l
+; GFX11-TRUE16-NEXT:    ds_store_b16 v0, v1
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: local_store_i13:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0x1fff, v1
+; GFX11-FAKE16-NEXT:    ds_store_b16 v0, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   store i13 %arg, ptr addrspace(3) %ptr, align 8
   ret void
 }
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fpext.ll b/llvm/test/CodeGen/AMDGPU/strict_fpext.ll
index df6c1a0aa8c46..40aac82888de2 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fpext.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fpext.ll
@@ -3,7 +3,8 @@
 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx803 < %s | FileCheck -check-prefixes=GCN,GFX89,GFX8 %s
 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX89,GFX9 %s
 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX10 %s
-; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX11 %s
+; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX11,GFX11-FAKE16 %s
 
 define float @v_constrained_fpext_f16_to_f32_fpexcept_strict(half %arg) #0 {
 ; SI-LABEL: v_constrained_fpext_f16_to_f32_fpexcept_strict:
@@ -20,11 +21,23 @@ define float @v_constrained_fpext_f16_to_f32_fpexcept_strict(half %arg) #0 {
 ; GFX89-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; GFX89-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1011-LABEL: v_constrained_fpext_f16_to_f32_fpexcept_strict:
-; GFX1011:       ; %bb.0:
-; GFX1011-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1011-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX1011-NEXT:    s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_constrained_fpext_f16_to_f32_fpexcept_strict:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: v_constrained_fpext_f16_to_f32_fpexcept_strict:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_constrained_fpext_f16_to_f32_fpexcept_strict:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = call float @llvm.experimental.constrained.fpext.f32.f16(half %arg, metadata !"fpexcept.strict")
   ret float %result
 }
@@ -57,13 +70,21 @@ define <2 x float> @v_constrained_fpext_v2f16_to_v2f32_fpexcept_strict(<2 x half
 ; GFX10-NEXT:    v_mov_b32_e32 v0, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_constrained_fpext_v2f16_to_v2f32_fpexcept_strict:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_constrained_fpext_v2f16_to_v2f32_fpexcept_strict:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v2, v0.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v0.h
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, v2
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_constrained_fpext_v2f16_to_v2f32_fpexcept_strict:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = call <2 x float> @llvm.experimental.constrained.fpext.v2f32.v2f16(<2 x half> %arg, metadata !"fpexcept.strict")
   ret <2 x float>   %result
 }
@@ -103,15 +124,24 @@ define <3 x float> @v_constrained_fpext_v3f16_to_v3f32_fpexcept_strict(<3 x half
 ; GFX10-NEXT:    v_mov_b32_e32 v1, v3
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_constrained_fpext_v3f16_to_v3f32_fpexcept_strict:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v3, v2
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v2, v1
-; GFX11-NEXT:    v_mov_b32_e32 v1, v3
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_constrained_fpext_v3f16_to_v3f32_fpexcept_strict:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v4, v0.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v3, v0.h
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v2, v1.l
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v3
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_constrained_fpext_v3f16_to_v3f32_fpexcept_strict:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v3, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v2, v1
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v3
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = call <3 x float> @llvm.experimental.constrained.fpext.v3f32.v3f16(<3 x half> %arg, metadata !"fpexcept.strict")
   ret <3 x float>   %result
 }
@@ -189,12 +219,26 @@ define double @v_constrained_fpext_f16_to_f64_fpexcept_strict(half %arg) #0 {
 ; GFX89-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
 ; GFX89-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1011-LABEL: v_constrained_fpext_f16_to_f64_fpexcept_strict:
-; GFX1011:       ; %bb.0:
-; GFX1011-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1011-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX1011-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
-; GFX1011-NEXT:    s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_constrained_fpext_f16_to_f64_fpexcept_strict:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX10-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: v_constrained_fpext_f16_to_f64_fpexcept_strict:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_constrained_fpext_f16_to_f64_fpexcept_strict:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = call double @llvm.experimental.constrained.fpext.f64.f16(half %arg, metadata !"fpexcept.strict")
   ret double %result
 }
@@ -231,15 +275,24 @@ define <2 x double> @v_constrained_fpext_v2f16_to_v2f64_fpexcept_strict(<2 x hal
 ; GFX10-NEXT:    v_cvt_f64_f32_e32 v[2:3], v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_constrained_fpext_v2f16_to_v2f64_fpexcept_strict:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v2, v1
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[2:3], v2
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_constrained_fpext_v2f16_to_v2f64_fpexcept_strict:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v0.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v2, v0.h
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v1
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[2:3], v2
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_constrained_fpext_v2f16_to_v2f64_fpexcept_strict:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v2, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[2:3], v2
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = call <2 x double> @llvm.experimental.constrained.fpext.v2f64.v2f16(<2 x half> %arg, metadata !"fpexcept.strict")
   ret <2 x double>   %result
 }
@@ -284,17 +337,28 @@ define <3 x double> @v_constrained_fpext_v3f16_to_v2f64_fpexcept_strict(<3 x hal
 ; GFX10-NEXT:    v_cvt_f64_f32_e32 v[4:5], v4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_constrained_fpext_v3f16_to_v2f64_fpexcept_strict:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v3, v1
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v2, v2
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[4:5], v3
-; GFX11-NEXT:    v_cvt_f64_f32_e32 v[2:3], v2
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_constrained_fpext_v3f16_to_v2f64_fpexcept_strict:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v2, v0.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v3, v0.h
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v4, v1.l
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v2
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[2:3], v3
+; GFX11-TRUE16-NEXT:    v_cvt_f64_f32_e32 v[4:5], v4
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_constrained_fpext_v3f16_to_v2f64_fpexcept_strict:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v3, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v2, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[0:1], v0
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[4:5], v3
+; GFX11-FAKE16-NEXT:    v_cvt_f64_f32_e32 v[2:3], v2
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = call <3 x double> @llvm.experimental.constrained.fpext.v3f64.v3f16(<3 x half> %arg, metadata !"fpexcept.strict")
   ret <3 x double>   %result
 }
@@ -316,12 +380,26 @@ define float @v_constrained_fneg_fpext_f16_to_f32_fpexcept_strict(half %arg) #0
 ; GFX89-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
 ; GFX89-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1011-LABEL: v_constrained_fneg_fpext_f16_to_f32_fpexcept_strict:
-; GFX1011:       ; %bb.0:
-; GFX1011-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1011-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX1011-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
-; GFX1011-NEXT:    s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_constrained_fneg_fpext_f16_to_f32_fpexcept_strict:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX10-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: v_constrained_fneg_fpext_f16_to_f32_fpexcept_strict:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_constrained_fneg_fpext_f16_to_f32_fpexcept_strict:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %result = call float @llvm.experimental.constrained.fpext.f32.f16(half %arg, metadata !"fpexcept.strict")
   %neg.result = fneg float %result
   ret float %neg.result
@@ -343,11 +421,23 @@ define float @v_constrained_fpext_fneg_f16_to_f32_fpexcept_strict(half %arg) #0
 ; GFX89-NEXT:    v_cvt_f32_f16_e64 v0, -v0
 ; GFX89-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX1011-LABEL: v_constrained_fpext_fneg_f16_to_f32_fpexcept_strict:
-; GFX1011:       ; %bb.0:
-; GFX1011-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1011-NEXT:    v_cvt_f32_f16_e64 v0, -v0
-; GFX1011-NEXT:    s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_constrained_fpext_fneg_f16_to_f32_fpexcept_strict:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_cvt_f32_f16_e64 v0, -v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: v_constrained_fpext_fneg_f16_to_f32_fpexcept_strict:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v0, -v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_constrained_fpext_fneg_f16_to_f32_fpexcept_strict:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v0, -v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %neg.arg = fneg half %arg
   %result = call float @llvm.experimental.constrained.fpext.f32.f16(half %neg.arg, metadata !"fpexcept.strict")
   ret float %result
@@ -413,13 +503,21 @@ define float @v_constrained_fpext_f16_to_f32_noabi(ptr addrspace(1) %ptr) #0 {
 ; GFX10-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_constrained_fpext_f16_to_f32_noabi:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_u16 v0, v[0:1], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_constrained_fpext_f16_to_f32_noabi:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_constrained_fpext_f16_to_f32_noabi:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_u16 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val = load half, ptr addrspace(1) %ptr
   %result = call float @llvm.experimental.constrained.fpext.f32.f16(half %val, metadata !"fpexcept.strict")
   ret float %result
@@ -467,15 +565,24 @@ define <2 x float> @v_constrained_fpext_v2f16_to_v2f32_noabi(ptr addrspace(1) %p
 ; GFX10-NEXT:    v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: v_constrained_fpext_v2f16_to_v2f32_noabi:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX11-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_constrained_fpext_v2f16_to_v2f32_noabi:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v1, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v1.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v1.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_constrained_fpext_v2f16_to_v2f32_noabi:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val = load <2 x half>, ptr addrspace(1) %ptr
   %result = call <2 x float> @llvm.experimental.constrained.fpext.v2f32.v2f16(<2 x half> %val, metadata !"fpexcept.strict")
   ret <2 x float> %result
@@ -495,3 +602,5 @@ declare <3 x float> @llvm.experimental.constrained.fpext.v3f32.v3f16(<3 x half>,
 
 attributes #0 = { strictfp }
 attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: readwrite) }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/sub.ll b/llvm/test/CodeGen/AMDGPU/sub.ll
index 8118441df0cfc..a3aeea8a145cd 100644
--- a/llvm/test/CodeGen/AMDGPU/sub.ll
+++ b/llvm/test/CodeGen/AMDGPU/sub.ll
@@ -2,7 +2,8 @@
 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX6 %s
 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8 %s
 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
 
 declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone speculatable
 
@@ -432,21 +433,37 @@ define amdgpu_kernel void @test_sub_i16(ptr addrspace(1) %out, ptr addrspace(1)
 ; GFX9-NEXT:    global_store_short v0, v1, s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
-; GFX12-LABEL: test_sub_i16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX12-NEXT:    v_mov_b32_e32 v2, 0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u16 v1, v0, s[2:3] scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    global_load_u16 v0, v0, s[2:3] offset:2 scope:SCOPE_SYS
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_sub_nc_u16 v0, v1, v0
-; GFX12-NEXT:    global_store_b16 v2, v0, s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: test_sub_i16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3] scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_hi_b16 v0, v1, s[2:3] offset:2 scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-TRUE16-NEXT:    v_sub_nc_u16 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: test_sub_i16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3] scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u16 v0, v0, s[2:3] offset:2 scope:SCOPE_SYS
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_sub_nc_u16 v0, v1, v0
+; GFX12-FAKE16-NEXT:    global_store_b16 v2, v0, s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %gep = getelementptr i16, ptr addrspace(1) %in, i32 %tid
   %b_ptr = getelementptr i16, ptr addrspace(1) %gep, i32 1
diff --git a/llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll b/llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
index 474482b2d89ff..d23e314b9465f 100644
--- a/llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
+++ b/llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
@@ -771,5 +771,3 @@ bb73.i:                                           ; preds = %bb70.i
   br label %bb5.backedge
 }
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll b/llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
index 2d5e1bb483421..5b1a5206c3403 100644
--- a/llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
@@ -1,7 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX8 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11,GFX11-FAKE16 %s
 
 ; FIXME: This should be merged with uint_to_fp.ll, but s_uint_to_fp_v2i64 crashes on r600
 
@@ -44,27 +45,49 @@ define amdgpu_kernel void @s_uint_to_fp_i64_to_f16(ptr addrspace(1) %out, i64 %i
 ; GFX8-NEXT:    flat_store_short v[0:1], v2
 ; GFX8-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: s_uint_to_fp_i64_to_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v1, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_clz_i32_u32 s4, s3
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT:    s_min_u32 s4, s4, 32
-; GFX11-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT:    s_min_u32 s2, s2, 1
-; GFX11-NEXT:    s_or_b32 s2, s3, s2
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    v_cvt_f32_u32_e32 v0, s2
-; GFX11-NEXT:    s_sub_i32 s2, 32, s4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT:    v_ldexp_f32 v0, v0, s2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    global_store_b16 v1, v0, s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: s_uint_to_fp_i64_to_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clz_i32_u32 s4, s3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_min_u32 s4, s4, 32
+; GFX11-TRUE16-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_min_u32 s2, s2, 1
+; GFX11-TRUE16-NEXT:    s_or_b32 s2, s3, s2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_u32_e32 v0, s2
+; GFX11-TRUE16-NEXT:    s_sub_i32 s2, 32, s4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v0, v0, s2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: s_uint_to_fp_i64_to_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clz_i32_u32 s4, s3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_min_u32 s4, s4, 32
+; GFX11-FAKE16-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_min_u32 s2, s2, 1
+; GFX11-FAKE16-NEXT:    s_or_b32 s2, s3, s2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_u32_e32 v0, s2
+; GFX11-FAKE16-NEXT:    s_sub_i32 s2, 32, s4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v0, v0, s2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %result = uitofp i64 %in to half
   store half %result, ptr addrspace(1) %out
   ret void
@@ -122,30 +145,55 @@ define amdgpu_kernel void @v_uint_to_fp_i64_to_f16(ptr addrspace(1) %out, ptr ad
 ; GFX8-NEXT:    flat_store_short v[0:1], v3
 ; GFX8-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: v_uint_to_fp_i64_to_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT:    v_and_b32_e32 v2, 0x3ff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 3, v2
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[0:1], v0, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_clz_i32_u32_e32 v3, v1
-; GFX11-NEXT:    v_min_u32_e32 v3, 32, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_lshlrev_b64 v[0:1], v3, v[0:1]
-; GFX11-NEXT:    v_min_u32_e32 v0, 1, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT:    v_sub_nc_u32_e32 v1, 32, v3
-; GFX11-NEXT:    v_cvt_f32_u32_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_ldexp_f32 v0, v0, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 1, v2
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    global_store_b16 v1, v0, s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: v_uint_to_fp_i64_to_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0x3ff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 3, v2
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b64 v[0:1], v0, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_clz_i32_u32_e32 v3, v1
+; GFX11-TRUE16-NEXT:    v_min_u32_e32 v3, 32, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b64 v[0:1], v3, v[0:1]
+; GFX11-TRUE16-NEXT:    v_min_u32_e32 v0, 1, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v1, v0
+; GFX11-TRUE16-NEXT:    v_sub_nc_u32_e32 v1, 32, v3
+; GFX11-TRUE16-NEXT:    v_cvt_f32_u32_e32 v0, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v0, v0, v1
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v2
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: v_uint_to_fp_i64_to_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0x3ff, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 3, v2
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[0:1], v0, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_clz_i32_u32_e32 v3, v1
+; GFX11-FAKE16-NEXT:    v_min_u32_e32 v3, 32, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b64 v[0:1], v3, v[0:1]
+; GFX11-FAKE16-NEXT:    v_min_u32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT:    v_sub_nc_u32_e32 v1, 32, v3
+; GFX11-FAKE16-NEXT:    v_cvt_f32_u32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %in.gep = getelementptr i64, ptr addrspace(1) %in, i32 %tid
   %out.gep = getelementptr half, ptr addrspace(1) %out, i32 %tid
@@ -606,37 +654,69 @@ define amdgpu_kernel void @s_uint_to_fp_v2i64_to_v2f16(ptr addrspace(1) %out, <2
 ; GFX8-NEXT:    flat_store_dword v[0:1], v2
 ; GFX8-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: s_uint_to_fp_v2i64_to_v2f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x34
-; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v2, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_clz_i32_u32 s6, s3
-; GFX11-NEXT:    s_clz_i32_u32 s7, s1
-; GFX11-NEXT:    s_min_u32 s6, s6, 32
-; GFX11-NEXT:    s_min_u32 s7, s7, 32
-; GFX11-NEXT:    s_lshl_b64 s[2:3], s[2:3], s6
-; GFX11-NEXT:    s_lshl_b64 s[0:1], s[0:1], s7
-; GFX11-NEXT:    s_min_u32 s2, s2, 1
-; GFX11-NEXT:    s_min_u32 s0, s0, 1
-; GFX11-NEXT:    s_or_b32 s2, s3, s2
-; GFX11-NEXT:    s_or_b32 s0, s1, s0
-; GFX11-NEXT:    v_cvt_f32_u32_e32 v0, s2
-; GFX11-NEXT:    v_cvt_f32_u32_e32 v1, s0
-; GFX11-NEXT:    s_sub_i32 s0, 32, s6
-; GFX11-NEXT:    s_sub_i32 s1, 32, s7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_ldexp_f32 v0, v0, s0
-; GFX11-NEXT:    v_ldexp_f32 v1, v1, s1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_pack_b32_f16 v0, v1, v0
-; GFX11-NEXT:    global_store_b32 v2, v0, s[4:5]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: s_uint_to_fp_v2i64_to_v2f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x34
+; GFX11-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clz_i32_u32 s6, s3
+; GFX11-TRUE16-NEXT:    s_clz_i32_u32 s7, s1
+; GFX11-TRUE16-NEXT:    s_min_u32 s6, s6, 32
+; GFX11-TRUE16-NEXT:    s_min_u32 s7, s7, 32
+; GFX11-TRUE16-NEXT:    s_lshl_b64 s[2:3], s[2:3], s6
+; GFX11-TRUE16-NEXT:    s_lshl_b64 s[0:1], s[0:1], s7
+; GFX11-TRUE16-NEXT:    s_min_u32 s2, s2, 1
+; GFX11-TRUE16-NEXT:    s_min_u32 s0, s0, 1
+; GFX11-TRUE16-NEXT:    s_or_b32 s2, s3, s2
+; GFX11-TRUE16-NEXT:    s_or_b32 s0, s1, s0
+; GFX11-TRUE16-NEXT:    v_cvt_f32_u32_e32 v0, s2
+; GFX11-TRUE16-NEXT:    v_cvt_f32_u32_e32 v1, s0
+; GFX11-TRUE16-NEXT:    s_sub_i32 s0, 32, s6
+; GFX11-TRUE16-NEXT:    s_sub_i32 s1, 32, s7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v0, v0, s0
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v1, v1, s1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v1
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v0.l
+; GFX11-TRUE16-NEXT:    global_store_b32 v1, v0, s[4:5]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: s_uint_to_fp_v2i64_to_v2f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x34
+; GFX11-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clz_i32_u32 s6, s3
+; GFX11-FAKE16-NEXT:    s_clz_i32_u32 s7, s1
+; GFX11-FAKE16-NEXT:    s_min_u32 s6, s6, 32
+; GFX11-FAKE16-NEXT:    s_min_u32 s7, s7, 32
+; GFX11-FAKE16-NEXT:    s_lshl_b64 s[2:3], s[2:3], s6
+; GFX11-FAKE16-NEXT:    s_lshl_b64 s[0:1], s[0:1], s7
+; GFX11-FAKE16-NEXT:    s_min_u32 s2, s2, 1
+; GFX11-FAKE16-NEXT:    s_min_u32 s0, s0, 1
+; GFX11-FAKE16-NEXT:    s_or_b32 s2, s3, s2
+; GFX11-FAKE16-NEXT:    s_or_b32 s0, s1, s0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_u32_e32 v0, s2
+; GFX11-FAKE16-NEXT:    v_cvt_f32_u32_e32 v1, s0
+; GFX11-FAKE16-NEXT:    s_sub_i32 s0, 32, s6
+; GFX11-FAKE16-NEXT:    s_sub_i32 s1, 32, s7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v0, v0, s0
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v1, v1, s1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v1, v0
+; GFX11-FAKE16-NEXT:    global_store_b32 v2, v0, s[4:5]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %result = uitofp <2 x i64> %in to <2 x half>
   store <2 x half> %result, ptr addrspace(1) %out
   ret void
@@ -761,65 +841,127 @@ define amdgpu_kernel void @v_uint_to_fp_v4i64_to_v4f16(ptr addrspace(1) %out, pt
 ; GFX8-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
 ; GFX8-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: v_uint_to_fp_v4i64_to_v4f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT:    v_and_b32_e32 v8, 0x3ff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 5, v8
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_load_b128 v[0:3], v4, s[2:3] offset:16
-; GFX11-NEXT:    global_load_b128 v[4:7], v4, s[2:3]
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_clz_i32_u32_e32 v9, v3
-; GFX11-NEXT:    v_clz_i32_u32_e32 v10, v1
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_clz_i32_u32_e32 v11, v7
-; GFX11-NEXT:    v_clz_i32_u32_e32 v12, v5
-; GFX11-NEXT:    v_min_u32_e32 v9, 32, v9
-; GFX11-NEXT:    v_min_u32_e32 v10, 32, v10
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_min_u32_e32 v11, 32, v11
-; GFX11-NEXT:    v_min_u32_e32 v12, 32, v12
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshlrev_b64 v[2:3], v9, v[2:3]
-; GFX11-NEXT:    v_lshlrev_b64 v[0:1], v10, v[0:1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshlrev_b64 v[6:7], v11, v[6:7]
-; GFX11-NEXT:    v_lshlrev_b64 v[4:5], v12, v[4:5]
-; GFX11-NEXT:    v_sub_nc_u32_e32 v9, 32, v9
-; GFX11-NEXT:    v_sub_nc_u32_e32 v10, 32, v10
-; GFX11-NEXT:    v_min_u32_e32 v2, 1, v2
-; GFX11-NEXT:    v_min_u32_e32 v0, 1, v0
-; GFX11-NEXT:    v_min_u32_e32 v6, 1, v6
-; GFX11-NEXT:    v_min_u32_e32 v4, 1, v4
-; GFX11-NEXT:    v_sub_nc_u32_e32 v11, 32, v11
-; GFX11-NEXT:    v_or_b32_e32 v2, v3, v2
-; GFX11-NEXT:    v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT:    v_or_b32_e32 v1, v7, v6
-; GFX11-NEXT:    v_or_b32_e32 v3, v5, v4
-; GFX11-NEXT:    v_sub_nc_u32_e32 v4, 32, v12
-; GFX11-NEXT:    v_cvt_f32_u32_e32 v2, v2
-; GFX11-NEXT:    v_cvt_f32_u32_e32 v0, v0
-; GFX11-NEXT:    v_cvt_f32_u32_e32 v1, v1
-; GFX11-NEXT:    v_cvt_f32_u32_e32 v3, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v5, 3, v8
-; GFX11-NEXT:    v_ldexp_f32 v2, v2, v9
-; GFX11-NEXT:    v_ldexp_f32 v0, v0, v10
-; GFX11-NEXT:    v_ldexp_f32 v1, v1, v11
-; GFX11-NEXT:    v_ldexp_f32 v3, v3, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v4, v1
-; GFX11-NEXT:    v_cvt_f16_f32_e32 v3, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_pack_b32_f16 v1, v0, v2
-; GFX11-NEXT:    v_pack_b32_f16 v0, v3, v4
-; GFX11-NEXT:    global_store_b64 v5, v[0:1], s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: v_uint_to_fp_v4i64_to_v4f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0x3ff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 5, v8
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    global_load_b128 v[0:3], v4, s[2:3] offset:16
+; GFX11-TRUE16-NEXT:    global_load_b128 v[4:7], v4, s[2:3]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_clz_i32_u32_e32 v9, v3
+; GFX11-TRUE16-NEXT:    v_clz_i32_u32_e32 v10, v1
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_clz_i32_u32_e32 v11, v7
+; GFX11-TRUE16-NEXT:    v_clz_i32_u32_e32 v12, v5
+; GFX11-TRUE16-NEXT:    v_min_u32_e32 v9, 32, v9
+; GFX11-TRUE16-NEXT:    v_min_u32_e32 v10, 32, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_min_u32_e32 v11, 32, v11
+; GFX11-TRUE16-NEXT:    v_min_u32_e32 v12, 32, v12
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b64 v[2:3], v9, v[2:3]
+; GFX11-TRUE16-NEXT:    v_lshlrev_b64 v[0:1], v10, v[0:1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b64 v[6:7], v11, v[6:7]
+; GFX11-TRUE16-NEXT:    v_lshlrev_b64 v[4:5], v12, v[4:5]
+; GFX11-TRUE16-NEXT:    v_sub_nc_u32_e32 v9, 32, v9
+; GFX11-TRUE16-NEXT:    v_sub_nc_u32_e32 v10, 32, v10
+; GFX11-TRUE16-NEXT:    v_min_u32_e32 v2, 1, v2
+; GFX11-TRUE16-NEXT:    v_min_u32_e32 v0, 1, v0
+; GFX11-TRUE16-NEXT:    v_min_u32_e32 v6, 1, v6
+; GFX11-TRUE16-NEXT:    v_min_u32_e32 v4, 1, v4
+; GFX11-TRUE16-NEXT:    v_sub_nc_u32_e32 v11, 32, v11
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v3, v2
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v0, v1, v0
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v1, v7, v6
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, v5, v4
+; GFX11-TRUE16-NEXT:    v_sub_nc_u32_e32 v4, 32, v12
+; GFX11-TRUE16-NEXT:    v_cvt_f32_u32_e32 v2, v2
+; GFX11-TRUE16-NEXT:    v_cvt_f32_u32_e32 v0, v0
+; GFX11-TRUE16-NEXT:    v_cvt_f32_u32_e32 v1, v1
+; GFX11-TRUE16-NEXT:    v_cvt_f32_u32_e32 v3, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v2, v2, v9
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v5, v0, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v1, v1, v11
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v3, v3, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v2
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v1.l, v1
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v1.h, v3
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 3, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v2, v0.h, v0.l
+; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.h, v1.l
+; GFX11-TRUE16-NEXT:    global_store_b64 v3, v[1:2], s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: v_uint_to_fp_v4i64_to_v4f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0x3ff, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 5, v8
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    global_load_b128 v[0:3], v4, s[2:3] offset:16
+; GFX11-FAKE16-NEXT:    global_load_b128 v[4:7], v4, s[2:3]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_clz_i32_u32_e32 v9, v3
+; GFX11-FAKE16-NEXT:    v_clz_i32_u32_e32 v10, v1
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_clz_i32_u32_e32 v11, v7
+; GFX11-FAKE16-NEXT:    v_clz_i32_u32_e32 v12, v5
+; GFX11-FAKE16-NEXT:    v_min_u32_e32 v9, 32, v9
+; GFX11-FAKE16-NEXT:    v_min_u32_e32 v10, 32, v10
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_min_u32_e32 v11, 32, v11
+; GFX11-FAKE16-NEXT:    v_min_u32_e32 v12, 32, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b64 v[2:3], v9, v[2:3]
+; GFX11-FAKE16-NEXT:    v_lshlrev_b64 v[0:1], v10, v[0:1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b64 v[6:7], v11, v[6:7]
+; GFX11-FAKE16-NEXT:    v_lshlrev_b64 v[4:5], v12, v[4:5]
+; GFX11-FAKE16-NEXT:    v_sub_nc_u32_e32 v9, 32, v9
+; GFX11-FAKE16-NEXT:    v_sub_nc_u32_e32 v10, 32, v10
+; GFX11-FAKE16-NEXT:    v_min_u32_e32 v2, 1, v2
+; GFX11-FAKE16-NEXT:    v_min_u32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT:    v_min_u32_e32 v6, 1, v6
+; GFX11-FAKE16-NEXT:    v_min_u32_e32 v4, 1, v4
+; GFX11-FAKE16-NEXT:    v_sub_nc_u32_e32 v11, 32, v11
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v7, v6
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, v5, v4
+; GFX11-FAKE16-NEXT:    v_sub_nc_u32_e32 v4, 32, v12
+; GFX11-FAKE16-NEXT:    v_cvt_f32_u32_e32 v2, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f32_u32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_u32_e32 v1, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f32_u32_e32 v3, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 3, v8
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v2, v2, v9
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v0, v0, v10
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v1, v1, v11
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v3, v3, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v4, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v1, v0, v2
+; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v3, v4
+; GFX11-FAKE16-NEXT:    global_store_b64 v5, v[0:1], s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %in.gep = getelementptr <4 x i64>, ptr addrspace(1) %in, i32 %tid
   %out.gep = getelementptr <4 x half>, ptr addrspace(1) %out, i32 %tid
diff --git a/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll b/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
index f08e5be0fd742..e0d16987b31e7 100644
--- a/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
+++ b/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
@@ -522,5 +522,3 @@ declare i32 @llvm.amdgcn.workitem.id.x()
 
 declare hidden float @spam()
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/v_cndmask.ll b/llvm/test/CodeGen/AMDGPU/v_cndmask.ll
index a3f632267ccd6..a41063f467d01 100644
--- a/llvm/test/CodeGen/AMDGPU/v_cndmask.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_cndmask.ll
@@ -2,8 +2,10 @@
 ; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=SI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX10 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -mattr=+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -mattr=+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-FAKE16 %s
 
 declare i32 @llvm.amdgcn.workitem.id.x() #1
 declare half @llvm.fabs.f16(half)
@@ -2226,49 +2228,93 @@ define amdgpu_kernel void @v_cndmask_abs_neg_f16(ptr addrspace(1) %out, i32 %c,
 ; GFX10-NEXT:    global_store_short v2, v0, s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: v_cndmask_abs_neg_f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x34
-; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-NEXT:    v_mov_b32_e32 v2, 0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u16 v0, v0, s[0:1]
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_cmp_lg_u32 s2, 0
-; GFX11-NEXT:    s_cselect_b64 vcc, -1, 0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v1, 0x7fff, v0
-; GFX11-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX11-NEXT:    global_store_b16 v2, v0, s[0:1]
-; GFX11-NEXT:    s_endpgm
-;
-; GFX12-LABEL: v_cndmask_abs_neg_f16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x34
-; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX12-NEXT:    v_mov_b32_e32 v2, 0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    global_load_u16 v0, v0, s[0:1]
-; GFX12-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_cmp_lg_u32 s2, 0
-; GFX12-NEXT:    s_cselect_b64 vcc, -1, 0
-; GFX12-NEXT:    s_wait_loadcnt 0x0
-; GFX12-NEXT:    v_and_b32_e32 v1, 0x7fff, v0
-; GFX12-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX12-NEXT:    global_store_b16 v2, v0, s[0:1]
-; GFX12-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: v_cndmask_abs_neg_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    s_load_b32 s2, s[4:5], 0x2c
+; GFX11-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s2, 0
+; GFX11-TRUE16-NEXT:    s_cselect_b64 s[2:3], -1, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0x7fff, v0.l
+; GFX11-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v0.h, s[2:3]
+; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: v_cndmask_abs_neg_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_u16 v0, v0, s[0:1]
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    s_load_b32 s2, s[4:5], 0x2c
+; GFX11-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s2, 0
+; GFX11-FAKE16-NEXT:    s_cselect_b64 vcc, -1, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0x7fff, v0
+; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
+; GFX11-FAKE16-NEXT:    global_store_b16 v2, v0, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-TRUE16-LABEL: v_cndmask_abs_neg_f16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x34
+; GFX12-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    global_load_d16_b16 v0, v0, s[0:1]
+; GFX12-TRUE16-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    s_cmp_lg_u32 s2, 0
+; GFX12-TRUE16-NEXT:    s_cselect_b64 s[2:3], -1, 0
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT:    v_and_b16 v0.h, 0x7fff, v0.l
+; GFX12-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v0.h, s[2:3]
+; GFX12-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: v_cndmask_abs_neg_f16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x34
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    global_load_u16 v0, v0, s[0:1]
+; GFX12-FAKE16-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    s_cmp_lg_u32 s2, 0
+; GFX12-FAKE16-NEXT:    s_cselect_b64 vcc, -1, 0
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0x7fff, v0
+; GFX12-FAKE16-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
+; GFX12-FAKE16-NEXT:    global_store_b16 v2, v0, s[0:1]
+; GFX12-FAKE16-NEXT:    s_endpgm
   %idx = call i32 @llvm.amdgcn.workitem.id.x() #1
   %f.gep = getelementptr half, ptr addrspace(1) %fptr, i32 %idx
   %f = load half, ptr addrspace(1) %f.gep
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
index 1d921b0d6e254..dfa50ce55a521 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
@@ -7,10 +7,15 @@
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
+; FIXME-TRUE16. enable gisel
+; XUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
+; XUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
 
 define i8 @test_vector_reduce_add_v2i8(<2 x i8> %v) {
 ; GFX7-LABEL: test_vector_reduce_add_v2i8:
@@ -37,21 +42,53 @@ define i8 @test_vector_reduce_add_v2i8(<2 x i8> %v) {
 ; GFX10-NEXT:    v_add_nc_u16 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_add_v2i8:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_nc_u16 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_add_v2i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: test_vector_reduce_add_v2i8:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_add_nc_u16 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_add_v2i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: test_vector_reduce_add_v2i8:
+; GFX11-GISEL:       ; %bb.0: ; %entry
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_add_nc_u16 v0, v0, v1
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_add_v2i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_add_v2i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: test_vector_reduce_add_v2i8:
+; GFX12-GISEL:       ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    v_add_nc_u16 v0, v0, v1
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call i8 @llvm.vector.reduce.add.v2i8(<2 x i8> %v)
   ret i8 %res
@@ -114,13 +151,21 @@ define i8 @test_vector_reduce_add_v3i8(<3 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_add_nc_u16 v0, v0, v2
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_add_v3i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_add_v3i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_add_v3i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_add_v3i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -130,17 +175,29 @@ define i8 @test_vector_reduce_add_v3i8(<3 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_add_nc_u16 v0, v0, v2
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_add_v3i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_add_v3i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_add_v3i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_add_v3i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -240,21 +297,39 @@ define i8 @test_vector_reduce_add_v4i8(<4 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_add_v4i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v2, 0xffff, v1
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_add_v4i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v1.l, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_add_v4i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_add_v4i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -266,25 +341,47 @@ define i8 @test_vector_reduce_add_v4i8(<4 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_add_v4i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v2, 0xffff, v1
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_add_v4i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v1.l, v1.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_add_v4i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_add_v4i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -418,26 +515,49 @@ define i8 @test_vector_reduce_add_v8i8(<8 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_add_v8i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v3, v3, v7
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v1, v1, v5
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v2, v2, v6
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v0, v0, v4
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v2, 0xffff, v1
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_add_v8i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v1.h, v3.l, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v1.l, v1.l, v5.l
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.h, v1.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v1.l, v2.l, v6.l
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_add_v8i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v3, v3, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v1, v1, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v2, v2, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_add_v8i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -454,30 +574,57 @@ define i8 @test_vector_reduce_add_v8i8(<8 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_add_v8i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v3, v3, v7
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v1, v1, v5
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v2, v2, v6
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v0, v0, v4
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v2, 0xffff, v1
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_add_v8i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v1.h, v3.l, v7.l
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v1.l, v1.l, v5.l
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v4.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.h, v1.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v1.l, v2.l, v6.l
+; GFX12-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_add_v8i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v1, v1, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v2, v2, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_add_v8i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -680,35 +827,66 @@ define i8 @test_vector_reduce_add_v16i8(<16 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_add_v16i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v5, v5, v13
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v1, v1, v9
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v7, v7, v15
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v3, v3, v11
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v4, v4, v12
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v0, v0, v8
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v6, v6, v14
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v2, v2, v10
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v3, v3, v7
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v1, v1, v5
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v0, v0, v4
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v2, v2, v6
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v1, v1, v3
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v0, v0, v2
-; GFX11-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v2, 0xffff, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_add_v16i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v1.h, v5.l, v13.l
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v1.l, v1.l, v9.l
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v3.h, v7.l, v15.l
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v3.l, v3.l, v11.l
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v2.h, v6.l, v14.l
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v2.l, v2.l, v10.l
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v1.l, v1.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v1.h, v4.l, v12.l
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.h, v3.l, v3.h
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v8.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.h, v1.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v1.l, v2.l, v2.h
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_add_v16i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v5, v5, v13
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v1, v1, v9
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v7, v7, v15
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v3, v3, v11
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v4, v4, v12
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v8
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v6, v6, v14
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v2, v2, v10
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v3, v3, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v1, v1, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v2, v2, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_add_v16i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -735,39 +913,74 @@ define i8 @test_vector_reduce_add_v16i8(<16 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_add_v16i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v5, v5, v13
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v1, v1, v9
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v7, v7, v15
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v3, v3, v11
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v4, v4, v12
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v0, v0, v8
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v6, v6, v14
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v2, v2, v10
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v3, v3, v7
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v1, v1, v5
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v0, v0, v4
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v2, v2, v6
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v1, v1, v3
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v0, v0, v2
-; GFX12-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v2, 0xffff, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_add_v16i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v1.h, v5.l, v13.l
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v1.l, v1.l, v9.l
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v3.h, v7.l, v15.l
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v3.l, v3.l, v11.l
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v2.h, v6.l, v14.l
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v2.l, v2.l, v10.l
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v1.l, v1.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v1.h, v4.l, v12.l
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.h, v3.l, v3.h
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v8.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.h, v1.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v1.l, v2.l, v2.h
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v2.l, 8, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_add_v16i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v5, v5, v13
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v1, v1, v9
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v7, v7, v15
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v3, v3, v11
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v4, v4, v12
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v8
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v6, v6, v14
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v2, v2, v10
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v1, v1, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v2, v2, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_add_v16i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -858,13 +1071,19 @@ define i16 @test_vector_reduce_add_v2i16(<2 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_pk_add_u16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_add_v2i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_add_v2i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_add_v2i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_add_v2i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -874,17 +1093,27 @@ define i16 @test_vector_reduce_add_v2i16(<2 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_pk_add_u16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_add_v2i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_add_v2i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_add_v2i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_add_v2i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -960,14 +1189,22 @@ define i16 @test_vector_reduce_add_v3i16(<3 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_add_nc_u16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_add_v3i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-SDAG-NEXT:    v_pk_add_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_add_v3i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_add_u16 v1, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v1.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_add_v3i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_add_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_add_v3i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -978,18 +1215,30 @@ define i16 @test_vector_reduce_add_v3i16(<3 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_add_nc_u16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_add_v3i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-SDAG-NEXT:    v_pk_add_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_add_v3i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_add_u16 v1, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v1.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_add_v3i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_add_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_add_v3i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1082,14 +1331,22 @@ define i16 @test_vector_reduce_add_v4i16(<4 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_pk_add_u16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_add_v4i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_pk_add_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_add_v4i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_add_u16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_add_v4i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_add_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_add_v4i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1100,18 +1357,30 @@ define i16 @test_vector_reduce_add_v4i16(<4 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_pk_add_u16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_add_v4i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_pk_add_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_add_v4i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_add_u16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_add_v4i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_add_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_add_v4i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1230,17 +1499,27 @@ define i16 @test_vector_reduce_add_v8i16(<8 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_pk_add_u16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_add_v8i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_pk_add_u16 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_pk_add_u16 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_pk_add_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_add_v8i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_add_u16 v1, v1, v3
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_add_u16 v0, v0, v2
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_add_u16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_add_v8i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_add_u16 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_add_u16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_add_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_add_v8i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1254,21 +1533,35 @@ define i16 @test_vector_reduce_add_v8i16(<8 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_pk_add_u16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_add_v8i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_pk_add_u16 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_pk_add_u16 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_add_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_add_v8i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_add_u16 v1, v1, v3
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_add_u16 v0, v0, v2
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_add_u16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_add_v8i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_add_u16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_add_u16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_add_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_add_v8i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1438,22 +1731,37 @@ define i16 @test_vector_reduce_add_v16i16(<16 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_pk_add_u16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_add_v16i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_pk_add_u16 v2, v2, v6
-; GFX11-SDAG-NEXT:    v_pk_add_u16 v3, v3, v7
-; GFX11-SDAG-NEXT:    v_pk_add_u16 v1, v1, v5
-; GFX11-SDAG-NEXT:    v_pk_add_u16 v0, v0, v4
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_pk_add_u16 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_pk_add_u16 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_pk_add_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_nc_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_add_v16i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_add_u16 v2, v2, v6
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_add_u16 v3, v3, v7
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_add_u16 v1, v1, v5
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_add_u16 v0, v0, v4
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_add_u16 v1, v1, v3
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_add_u16 v0, v0, v2
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_add_u16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_add_v16i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_add_u16 v2, v2, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_add_u16 v3, v3, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_add_u16 v1, v1, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_add_u16 v0, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_add_u16 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_add_u16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_add_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_add_v16i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1472,26 +1780,45 @@ define i16 @test_vector_reduce_add_v16i16(<16 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_pk_add_u16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_add_v16i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_pk_add_u16 v2, v2, v6
-; GFX12-SDAG-NEXT:    v_pk_add_u16 v3, v3, v7
-; GFX12-SDAG-NEXT:    v_pk_add_u16 v1, v1, v5
-; GFX12-SDAG-NEXT:    v_pk_add_u16 v0, v0, v4
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_pk_add_u16 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_pk_add_u16 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_add_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_add_nc_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_add_v16i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_add_u16 v2, v2, v6
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_add_u16 v3, v3, v7
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_add_u16 v1, v1, v5
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_add_u16 v0, v0, v4
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_add_u16 v1, v1, v3
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_add_u16 v0, v0, v2
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_add_u16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_add_v16i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_add_u16 v2, v2, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_add_u16 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_add_u16 v1, v1, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_add_u16 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_add_u16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_add_u16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_add_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_add_v16i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -3132,3 +3459,6 @@ declare i64 @llvm.vector.reduce.add.v3i64(<3 x i64>)
 declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)
 declare i64 @llvm.vector.reduce.add.v8i64(<8 x i64>)
 declare i64 @llvm.vector.reduce.add.v16i64(<16 x i64>)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11-GISEL-FAKE16: {{.*}}
+; GFX12-GISEL-FAKE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
index 4eba4ff954b1f..801324eec454e 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
@@ -7,10 +7,15 @@
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
+; FIXME-TRUE16. enable gisel
+; XUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
+; XUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
 
 define i8 @test_vector_reduce_and_v2i8(<2 x i8> %v) {
 ; GFX7-SDAG-LABEL: test_vector_reduce_and_v2i8:
@@ -69,18 +74,31 @@ define i8 @test_vector_reduce_and_v2i8(<2 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_and_b32_e32 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_and_v2i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_lshrrev_b16 v2, 8, v1
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, v1, v2
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_and_v2i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b16 v0.h, 8, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, v1.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_and_v2i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b16 v2, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, v1, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_and_v2i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -88,22 +106,39 @@ define i8 @test_vector_reduce_and_v2i8(<2 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_and_v2i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_lshrrev_b16 v2, 8, v1
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, v1, v2
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_and_v2i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_lshrrev_b16 v0.h, 8, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, v1.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_and_v2i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b16 v2, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, v1, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_and_v2i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -176,13 +211,21 @@ define i8 @test_vector_reduce_and_v3i8(<3 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_and_b32_e32 v0, v0, v2
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_and_v3i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_and_v3i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_and_v3i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_and_v3i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -192,17 +235,29 @@ define i8 @test_vector_reduce_and_v3i8(<3 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, v0, v2
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_and_v3i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_and_v3i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_and_v3i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_and_v3i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -293,15 +348,25 @@ define i8 @test_vector_reduce_and_v4i8(<4 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_and_v4i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_and_v4i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_and_v4i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_and_v4i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -313,19 +378,33 @@ define i8 @test_vector_reduce_and_v4i8(<4 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_and_v4i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_and_v4i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, v1.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_and_v4i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_and_v4i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -450,20 +529,35 @@ define i8 @test_vector_reduce_and_v8i8(<8 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_and_v8i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v2, v2, v6
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v3, v3, v7
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, v1, v5
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, v0, v4
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_and_v8i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, v2.l, v6.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v1.h, v3.l, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, v1.l, v5.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, v1.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_and_v8i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, v2, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v3, v3, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, v1, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_and_v8i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -480,24 +574,43 @@ define i8 @test_vector_reduce_and_v8i8(<8 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_and_v8i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v2, v2, v6
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v3, v3, v7
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, v1, v5
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, v0, v4
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_and_v8i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, v2.l, v6.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v1.h, v3.l, v7.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, v1.l, v5.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, v4.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, v1.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_and_v8i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, v2, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, v1, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_and_v8i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -691,29 +804,53 @@ define i8 @test_vector_reduce_and_v16i8(<16 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_and_v16i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v5, v5, v13
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, v1, v9
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v7, v7, v15
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v6, v6, v14
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v2, v2, v10
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v3, v3, v11
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v4, v4, v12
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, v0, v8
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, v1, v5
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v2, v2, v6
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v3, v3, v7
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, v0, v4
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, v1, v3
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, v0, v2
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_and_v16i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v1.h, v5.l, v13.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, v1.l, v9.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v5.l, v7.l, v15.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, v6.l, v14.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v2.l, v2.l, v10.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v2.h, v3.l, v11.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v3.l, v4.l, v12.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, v8.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, v1.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, v2.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v2.l, v2.h, v5.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, v1.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_and_v16i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v5, v5, v13
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, v1, v9
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v7, v7, v15
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v6, v6, v14
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, v2, v10
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v3, v3, v11
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v4, v4, v12
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v8
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, v1, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, v2, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v3, v3, v7
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_and_v16i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -740,33 +877,61 @@ define i8 @test_vector_reduce_and_v16i8(<16 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_and_v16i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v5, v5, v13
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, v1, v9
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v7, v7, v15
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v6, v6, v14
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v2, v2, v10
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v3, v3, v11
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v4, v4, v12
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, v0, v8
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, v1, v5
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v2, v2, v6
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v3, v3, v7
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, v0, v4
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, v1, v3
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, v0, v2
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_and_v16i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v1.h, v5.l, v13.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, v1.l, v9.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v5.l, v7.l, v15.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, v6.l, v14.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v2.l, v2.l, v10.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v2.h, v3.l, v11.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v3.l, v4.l, v12.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, v8.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, v1.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, v2.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v2.l, v2.h, v5.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, v1.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_and_v16i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v5, v5, v13
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, v1, v9
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v7, v7, v15
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v6, v6, v14
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, v2, v10
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v3, v3, v11
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v4, v4, v12
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v8
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, v1, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, v2, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_and_v16i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -855,13 +1020,22 @@ define i16 @test_vector_reduce_and_v2i16(<2 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_and_b32_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_and_v2i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_alignbit_b32 v1, s0, v0, 16
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_and_v2i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_and_v2i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_alignbit_b32 v1, s0, v0, 16
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_and_v2i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -871,17 +1045,30 @@ define i16 @test_vector_reduce_and_v2i16(<2 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_and_v2i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_alignbit_b32 v1, s0, v0, 16
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_and_v2i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_and_v2i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_alignbit_b32 v1, s0, v0, 16
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_and_v2i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -936,27 +1123,73 @@ define i16 @test_vector_reduce_and_v3i16(<3 x i16> %v) {
 ; GFX10-NEXT:    v_and_b32_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_and_v3i16:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_and_b32_e32 v0, v0, v2
-; GFX11-NEXT:    v_and_b32_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_and_v3i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.h, 0
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, v0, v2
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_and_v3i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: test_vector_reduce_and_v3i16:
+; GFX11-GISEL:       ; %bb.0: ; %entry
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, v0, v2
+; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: test_vector_reduce_and_v3i16:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_and_b32_e32 v0, v0, v2
-; GFX12-NEXT:    v_and_b32_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_and_v3i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.h, 0
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, v0, v2
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_and_v3i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: test_vector_reduce_and_v3i16:
+; GFX12-GISEL:       ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT:    v_and_b32_e32 v0, v0, v2
+; GFX12-GISEL-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call i16 @llvm.vector.reduce.and.v3i16(<3 x i16> %v)
   ret i16 %res
@@ -1018,27 +1251,73 @@ define i16 @test_vector_reduce_and_v4i16(<4 x i16> %v) {
 ; GFX10-NEXT:    v_and_b32_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_and_v4i16:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_and_b32_e32 v0, v0, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_and_b32_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_and_v4i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, 0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_and_v4i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: test_vector_reduce_and_v4i16:
+; GFX11-GISEL:       ; %bb.0: ; %entry
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: test_vector_reduce_and_v4i16:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_and_b32_e32 v0, v0, v1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-NEXT:    v_and_b32_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_and_v4i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, 0
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_and_v4i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: test_vector_reduce_and_v4i16:
+; GFX12-GISEL:       ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-GISEL-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> %v)
   ret i16 %res
@@ -1134,17 +1413,30 @@ define i16 @test_vector_reduce_and_v8i16(<8 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_and_b32_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_and_v8i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_and_v8i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v1, v1, v3
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, v0, v2
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, 0
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_and_v8i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_and_v8i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1158,21 +1450,38 @@ define i16 @test_vector_reduce_and_v8i16(<8 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_and_v8i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_and_v8i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v1, v1, v3
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, v0, v2
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, 0
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_and_v8i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_and_v8i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1332,22 +1641,40 @@ define i16 @test_vector_reduce_and_v16i16(<16 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_and_b32_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_and_v16i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v2, v2, v6
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v3, v3, v7
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, v1, v5
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, v0, v4
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_and_v16i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v2, v2, v6
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v3, v3, v7
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v1, v1, v5
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, v0, v4
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v1, v1, v3
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, v0, v2
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, 0
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_and_v16i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, v2, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v3, v3, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, v1, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_and_v16i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1366,26 +1693,48 @@ define i16 @test_vector_reduce_and_v16i16(<16 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_and_b32_e32 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_and_v16i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v2, v2, v6
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v3, v3, v7
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, v1, v5
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, v0, v4
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_and_v16i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v2, v2, v6
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v3, v3, v7
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v1, v1, v5
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, v0, v4
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v1, v1, v3
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, v0, v2
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, 0
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_and_v16i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, v2, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, v1, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_and_v16i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -3116,3 +3465,6 @@ declare i64 @llvm.vector.reduce.and.v3i64(<3 x i64>)
 declare i64 @llvm.vector.reduce.and.v4i64(<4 x i64>)
 declare i64 @llvm.vector.reduce.and.v8i64(<8 x i64>)
 declare i64 @llvm.vector.reduce.and.v16i64(<16 x i64>)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11-GISEL-FAKE16: {{.*}}
+; GFX12-GISEL-FAKE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
index 64c396f14bc70..bce7c1e5e8ab7 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
@@ -7,10 +7,14 @@
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
 
 define half @test_vector_reduce_fadd_v2half(half %sp, <2 x half> %v) {
 ; GFX7-SDAG-LABEL: test_vector_reduce_fadd_v2half:
@@ -60,27 +64,91 @@ define half @test_vector_reduce_fadd_v2half(half %sp, <2 x half> %v) {
 ; GFX10-NEXT:    v_add_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_fadd_v2half:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: test_vector_reduce_fadd_v2half:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fadd_v2half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fadd_v2half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_fadd_v2half:
+; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fadd_v2half:
+; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fadd_v2half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fadd_v2half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fadd_v2half:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fadd_v2half:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fadd.v2half(half %sp, <2 x half> %v)
   ret half %res
@@ -144,53 +212,97 @@ define half @test_vector_reduce_fadd_v3half(half %sp, <3 x half> %v) {
 ; GFX10-NEXT:    v_add_f16_e32 v0, v0, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_fadd_v3half:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_add_f16_e32 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: test_vector_reduce_fadd_v3half:
-; GFX11-GISEL:       ; %bb.0: ; %entry
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-GISEL-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_add_f16_e32 v0, v0, v3
-; GFX11-GISEL-NEXT:    v_add_f16_e32 v0, v0, v2
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: test_vector_reduce_fadd_v3half:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_add_f16_e32 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: test_vector_reduce_fadd_v3half:
-; GFX12-GISEL:       ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-GISEL-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT:    v_add_f16_e32 v0, v0, v3
-; GFX12-GISEL-NEXT:    v_add_f16_e32 v0, v0, v2
-; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fadd_v3half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fadd_v3half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_fadd_v3half:
+; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.h
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fadd_v3half:
+; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fadd_v3half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fadd_v3half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fadd_v3half:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.l
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fadd_v3half:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v3
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v2
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fadd.v3half(half %sp, <3 x half> %v)
   ret half %res
@@ -264,35 +376,121 @@ define half @test_vector_reduce_fadd_v4half(half %sp, <4 x half> %v) {
 ; GFX10-NEXT:    v_add_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_fadd_v4half:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: test_vector_reduce_fadd_v4half:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v2
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fadd_v4half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fadd_v4half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_fadd_v4half:
+; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fadd_v4half:
+; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fadd_v4half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fadd_v4half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fadd_v4half:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fadd_v4half:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v2
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fadd.v4half(half %sp, <4 x half> %v)
   ret half %res
@@ -406,51 +604,181 @@ define half @test_vector_reduce_fadd_v8half(half %sp, <8 x half> %v) {
 ; GFX10-NEXT:    v_add_f16_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_fadd_v8half:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: test_vector_reduce_fadd_v8half:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v2
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v3
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v4
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fadd_v8half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.h
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v3.h
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v4.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fadd_v8half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v3
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_fadd_v8half:
+; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v3.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v4.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fadd_v8half:
+; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v3
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v4
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fadd_v8half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.h
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v3.h
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v4.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v4.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fadd_v8half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v3
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fadd_v8half:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v3.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v4.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fadd_v8half:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v2
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v3
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v4
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fadd.v8half(half %sp, <8 x half> %v)
   ret half %res
@@ -644,83 +972,301 @@ define half @test_vector_reduce_fadd_v16half(half %sp, <16 x half> %v) {
 ; GFX10-NEXT:    v_add_f16_sdwa v0, v0, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_fadd_v16half:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v5
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v6
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v7
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v8
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v8
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: test_vector_reduce_fadd_v16half:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v2
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v3
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v4
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v5
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v5
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v6
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v6
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v7
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v7
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v8
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v8
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fadd_v16half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.h
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v3.h
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v4.h
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v5.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v5.h
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v6.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v6.h
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v7.h
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v8.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v8.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fadd_v16half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v3
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v5
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v6
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v7
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v8
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v8
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_fadd_v16half:
+; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v3.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v4.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v5
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v5.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v6
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v6.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v7
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v7.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v8
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v8.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fadd_v16half:
+; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v3
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v4
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v5
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v5
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v6
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v6
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v7
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v7
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v8
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v8
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fadd_v16half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.h
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v3.h
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v4.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v4.h
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v5.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v5.h
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v6.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v6.h
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v7.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v7.h
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v8.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v8.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fadd_v16half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v3
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v5
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v6
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v7
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v8
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v8
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fadd_v16half:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v2.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v3.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v4.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v5
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v5.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v6
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v6.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v7
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v7.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v8
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v8.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fadd_v16half:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v2
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v3
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v4
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v5
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v5
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v6
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v6
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v7
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v7
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v8
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v8
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_add_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fadd.v16half(half %sp, <16 x half> %v)
   ret half %res
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
index 94ebd1184b594..d500a3e50f9f7 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
@@ -7,10 +7,14 @@
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
 
 define half @test_vector_reduce_fmax_v2half(<2 x half> %v) {
 ; GFX7-SDAG-LABEL: test_vector_reduce_fmax_v2half:
@@ -80,29 +84,97 @@ define half @test_vector_reduce_fmax_v2half(<2 x half> %v) {
 ; GFX10-GISEL-NEXT:    v_max_f16_e32 v0, v1, v0
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_fmax_v2half:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: test_vector_reduce_fmax_v2half:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-NEXT:    v_max_num_f16_e32 v0, v0, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_max_num_f16_e32 v1, v1, v1
-; GFX12-NEXT:    v_max_num_f16_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v2half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.h, v0.h, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v2half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_fmax_v2half:
+; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.h, v0.h, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v2half:
+; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v2half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v2half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_max_num_f16_e32 v1, v1, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fmax_v2half:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v2half:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v0
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v1, v1, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fmax.v2half(<2 x half> %v)
   ret half %res
@@ -197,65 +269,119 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
 ; GFX10-GISEL-NEXT:    v_max_f16_e32 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_fmax_v3half:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX11-SDAG-NEXT:    v_pk_max_f16 v0, v0, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_pack_b32_f16 v1, v1, 0x7e00
-; GFX11-SDAG-NEXT:    v_pk_max_f16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: test_vector_reduce_fmax_v3half:
-; GFX11-GISEL:       ; %bb.0: ; %entry
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v2, v2, v2
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v0, v0, v2
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: test_vector_reduce_fmax_v3half:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_max_num_f16_e32 v1, v1, v1
-; GFX12-SDAG-NEXT:    v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pack_b32_f16 v1, v1, 0x7e00
-; GFX12-SDAG-NEXT:    v_pk_max_num_f16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    v_max_num_f16_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: test_vector_reduce_fmax_v3half:
-; GFX12-GISEL:       ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v0, v0, v0
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v1, v1, v1
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v2, v2, v2
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v0, v0, v2
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v0, v0, v1
-; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v3half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v1.l, v1.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_f16 v0, v0, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.l, 0x7e00
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_f16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v3half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_f16 v0, v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, 0x7e00
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_f16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_fmax_v3half:
+; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.h, v0.h, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.h, v1.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v3half:
+; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v2, v2, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v3half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_max_num_f16_e32 v1.l, v1.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_num_f16 v0, v0, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.l, 0x7e00
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_num_f16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v3half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_max_num_f16_e32 v1, v1, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_num_f16 v0, v0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, 0x7e00
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_num_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fmax_v3half:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.h, v1.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v3half:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v1, v1, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v2, v2, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v2
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fmax.v3half(<3 x half> %v)
   ret half %res
@@ -362,71 +488,127 @@ define half @test_vector_reduce_fmax_v4half(<4 x half> %v) {
 ; GFX10-GISEL-NEXT:    v_max_f16_e32 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_fmax_v4half:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_pk_max_f16 v1, v1, v1
-; GFX11-SDAG-NEXT:    v_pk_max_f16 v0, v0, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_pk_max_f16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: test_vector_reduce_fmax_v4half:
-; GFX11-GISEL:       ; %bb.0: ; %entry
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v2, v2, v2
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v3, v3, v3
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v0, v0, v2
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v1, v1, v3
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: test_vector_reduce_fmax_v4half:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-NEXT:    v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_max_num_f16 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_max_num_f16_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: test_vector_reduce_fmax_v4half:
-; GFX12-GISEL:       ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v0, v0, v0
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v1, v1, v1
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v2, v2, v2
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v3, v3, v3
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v0, v0, v2
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v1, v1, v3
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v0, v0, v1
-; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v4half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_f16 v1, v1, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_f16 v0, v0, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_f16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v4half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_f16 v1, v1, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_f16 v0, v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_f16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_fmax_v4half:
+; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.h, v0.h, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v1.l, v1.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v1.h, v1.h, v1.h
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.h, v1.l, v1.h
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v4half:
+; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v2, v2, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v3, v3, v3
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v1, v1, v3
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v4half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_num_f16 v1, v1, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_num_f16 v0, v0, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_num_f16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v4half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_num_f16 v1, v1, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_num_f16 v0, v0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_num_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fmax_v4half:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v1.l, v1.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v1.h, v1.h, v1.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.h, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v4half:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v1, v1, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v2, v2, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v3, v3, v3
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v1, v1, v3
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fmax.v4half(<4 x half> %v)
   ret half %res
@@ -599,99 +781,181 @@ define half @test_vector_reduce_fmax_v8half(<8 x half> %v) {
 ; GFX10-GISEL-NEXT:    v_max_f16_e32 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_fmax_v8half:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_pk_max_f16 v3, v3, v3
-; GFX11-SDAG-NEXT:    v_pk_max_f16 v1, v1, v1
-; GFX11-SDAG-NEXT:    v_pk_max_f16 v2, v2, v2
-; GFX11-SDAG-NEXT:    v_pk_max_f16 v0, v0, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_pk_max_f16 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_pk_max_f16 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_pk_max_f16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: test_vector_reduce_fmax_v8half:
-; GFX11-GISEL:       ; %bb.0: ; %entry
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v7, 16, v3
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v4, v4, v4
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v5, v5, v5
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v2, v2, v2
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v6, v6, v6
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v3, v3, v3
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v7, v7, v7
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v0, v0, v4
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v1, v1, v5
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v2, v2, v6
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v3, v3, v7
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v1, v2, v3
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: test_vector_reduce_fmax_v8half:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_pk_max_num_f16 v3, v3, v3
-; GFX12-SDAG-NEXT:    v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-NEXT:    v_pk_max_num_f16 v2, v2, v2
-; GFX12-SDAG-NEXT:    v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_pk_max_num_f16 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_pk_max_num_f16 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_max_num_f16 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_max_num_f16_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: test_vector_reduce_fmax_v8half:
-; GFX12-GISEL:       ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v7, 16, v3
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v0, v0, v0
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v1, v1, v1
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v4, v4, v4
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v5, v5, v5
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v2, v2, v2
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v6, v6, v6
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v3, v3, v3
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v7, v7, v7
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v0, v0, v4
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v1, v1, v5
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v2, v2, v6
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v3, v3, v7
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v0, v0, v1
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v1, v2, v3
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v0, v0, v1
-; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v8half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_f16 v3, v3, v3
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_f16 v1, v1, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_f16 v2, v2, v2
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_f16 v0, v0, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_f16 v1, v1, v3
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_f16 v0, v0, v2
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_f16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v8half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_f16 v3, v3, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_f16 v1, v1, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_f16 v2, v2, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_f16 v0, v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_f16 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_f16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_f16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_fmax_v8half:
+; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.h, v0.h, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v1.l, v1.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v1.h, v1.h, v1.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v2.l, v2.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v2.h, v2.h, v2.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v3.l, v3.l, v3.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v3.h, v3.h, v3.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.h, v1.l, v1.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v1.l, v2.l, v2.h
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v1.h, v3.l, v3.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.h, v1.l, v1.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v8half:
+; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v4, v4, v4
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v5, v5, v5
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v2, v2, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v6, v6, v6
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v3, v3, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v7, v7, v7
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v4
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v1, v1, v5
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v2, v2, v6
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v3, v3, v7
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v1, v2, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v8half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_num_f16 v3, v3, v3
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_num_f16 v1, v1, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_num_f16 v2, v2, v2
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_num_f16 v0, v0, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_num_f16 v1, v1, v3
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_num_f16 v0, v0, v2
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_num_f16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v8half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_num_f16 v3, v3, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_num_f16 v1, v1, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_num_f16 v2, v2, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_num_f16 v0, v0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_num_f16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_num_f16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_num_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fmax_v8half:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v1.l, v1.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v1.h, v1.h, v1.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v2.l, v2.l, v2.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v2.h, v2.h, v2.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v3.l, v3.l, v3.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v3.h, v3.h, v3.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.h, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v1.l, v2.l, v2.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v1.h, v3.l, v3.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.h, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v8half:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v3
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v1, v1, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v4, v4, v4
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v5, v5, v5
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v2, v2, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v6, v6, v6
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v3, v3, v3
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v7, v7, v7
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v4
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v1, v1, v5
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v2, v2, v6
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v3, v3, v7
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v1, v2, v3
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fmax.v8half(<8 x half> %v)
   ret half %res
@@ -996,161 +1260,285 @@ define half @test_vector_reduce_fmax_v16half(<16 x half> %v) {
 ; GFX10-GISEL-NEXT:    v_max_f16_e32 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_fmax_v16half:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v8, 16, v0
-; GFX11-SDAG-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_max_f16_e32 v8, v8, v8
-; GFX11-SDAG-NEXT:    v_max_f16_e32 v0, v0, v8
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v8, 16, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_max3_f16 v0, v0, v1, v9
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
-; GFX11-SDAG-NEXT:    v_max3_f16 v0, v0, v2, v8
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 16, v4
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_max3_f16 v0, v0, v3, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v5
-; GFX11-SDAG-NEXT:    v_max3_f16 v0, v0, v4, v2
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 16, v6
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_max3_f16 v0, v0, v5, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v7
-; GFX11-SDAG-NEXT:    v_max3_f16 v0, v0, v6, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_max3_f16 v0, v0, v7, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: test_vector_reduce_fmax_v16half:
-; GFX11-GISEL:       ; %bb.0: ; %entry
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v8, 16, v0
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v10, 16, v2
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v11, 16, v3
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v12, 16, v4
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v13, 16, v5
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v8, v8, v8
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v9, v9, v9
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v2, v2, v2
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v10, v10, v10
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v14, 16, v6
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v15, 16, v7
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v0, v0, v8
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v1, v1, v9
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v2, v2, v10
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v3, v3, v3
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v8, v11, v11
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v4, v4, v4
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v9, v12, v12
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v5, v5, v5
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v10, v13, v13
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v6, v6, v6
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v11, v14, v14
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v7, v7, v7
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v12, v15, v15
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v3, v3, v8
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v4, v4, v9
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v5, v5, v10
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v6, v6, v11
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v7, v7, v12
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v1, v2, v3
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v2, v4, v5
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v3, v6, v7
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v1, v2, v3
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: test_vector_reduce_fmax_v16half:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v8, 16, v0
-; GFX12-SDAG-NEXT:    v_max_num_f16_e32 v0, v0, v0
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_max_num_f16_e32 v8, v8, v8
-; GFX12-SDAG-NEXT:    v_max_num_f16_e32 v0, v0, v8
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v8, 16, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_max3_num_f16 v0, v0, v1, v9
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
-; GFX12-SDAG-NEXT:    v_max3_num_f16 v0, v0, v2, v8
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 16, v4
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_max3_num_f16 v0, v0, v3, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v5
-; GFX12-SDAG-NEXT:    v_max3_num_f16 v0, v0, v4, v2
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_max3_num_f16 v0, v0, v5, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v7
-; GFX12-SDAG-NEXT:    v_max3_num_f16 v0, v0, v6, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_max3_num_f16 v0, v0, v7, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: test_vector_reduce_fmax_v16half:
-; GFX12-GISEL:       ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v8, 16, v0
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v10, 16, v2
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v11, 16, v3
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v12, 16, v4
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v13, 16, v5
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v0, v0, v0
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v8, v8, v8
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v1, v1, v1
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v9, v9, v9
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v2, v2, v2
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v10, v10, v10
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v14, 16, v6
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v15, 16, v7
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v0, v0, v8
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v1, v1, v9
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v2, v2, v10
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v3, v3, v3
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v8, v11, v11
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v4, v4, v4
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v9, v12, v12
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v5, v5, v5
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v10, v13, v13
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v6, v6, v6
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v11, v14, v14
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v7, v7, v7
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v12, v15, v15
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v3, v3, v8
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v4, v4, v9
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v5, v5, v10
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v6, v6, v11
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v7, v7, v12
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v0, v0, v1
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v1, v2, v3
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v2, v4, v5
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v3, v6, v7
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v0, v0, v1
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v1, v2, v3
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v0, v0, v1
-; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v16half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.h, v0.h, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max3_f16 v0.l, v0.l, v1.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_max3_f16 v0.l, v0.l, v2.l, v2.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max3_f16 v0.l, v0.l, v3.l, v3.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_max3_f16 v0.l, v0.l, v4.l, v4.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max3_f16 v0.l, v0.l, v5.l, v5.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_max3_f16 v0.l, v0.l, v6.l, v6.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max3_f16 v0.l, v0.l, v7.l, v7.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v16half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v8, v8, v8
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v8
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max3_f16 v0, v0, v1, v9
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_max3_f16 v0, v0, v2, v8
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v4
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max3_f16 v0, v0, v3, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_max3_f16 v0, v0, v4, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max3_f16 v0, v0, v5, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_max3_f16 v0, v0, v6, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_max3_f16 v0, v0, v7, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_fmax_v16half:
+; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.h, v0.h, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v1.l, v1.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v1.h, v1.h, v1.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v2.l, v2.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v2.h, v2.h, v2.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.h, v1.l, v1.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v1.h, v3.l, v3.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v1.l, v2.l, v2.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v2.l, v3.h, v3.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v2.h, v4.l, v4.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v3.l, v4.h, v4.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v3.h, v5.l, v5.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v4.l, v5.h, v5.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v4.h, v6.l, v6.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v5.l, v6.h, v6.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v5.h, v7.l, v7.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v6.l, v7.h, v7.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v1.h, v1.h, v2.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v2.l, v2.h, v3.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v2.h, v3.h, v4.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v3.l, v4.h, v5.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v3.h, v5.h, v6.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.h, v1.l, v1.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v1.l, v2.l, v2.h
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v1.h, v3.l, v3.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.h, v1.l, v1.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v16half:
+; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v11, 16, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v12, 16, v4
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 16, v5
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v8, v8, v8
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v9, v9, v9
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v2, v2, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v10, v10, v10
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v6
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 16, v7
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v8
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v1, v1, v9
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v2, v2, v10
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v3, v3, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v8, v11, v11
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v4, v4, v4
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v9, v12, v12
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v5, v5, v5
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v10, v13, v13
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v6, v6, v6
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v11, v14, v14
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v7, v7, v7
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v12, v15, v15
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v3, v3, v8
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v4, v4, v9
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v5, v5, v10
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v6, v6, v11
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v7, v7, v12
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v1, v2, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v2, v4, v5
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v3, v6, v7
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v1, v2, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v16half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_max3_num_f16 v0.l, v0.l, v1.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_max3_num_f16 v0.l, v0.l, v2.l, v2.h
+; GFX12-SDAG-TRUE16-NEXT:    v_max3_num_f16 v0.l, v0.l, v3.l, v3.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_max3_num_f16 v0.l, v0.l, v4.l, v4.h
+; GFX12-SDAG-TRUE16-NEXT:    v_max3_num_f16 v0.l, v0.l, v5.l, v5.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_max3_num_f16 v0.l, v0.l, v6.l, v6.h
+; GFX12-SDAG-TRUE16-NEXT:    v_max3_num_f16 v0.l, v0.l, v7.l, v7.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v16half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_max_num_f16_e32 v8, v8, v8
+; GFX12-SDAG-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v8
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_max3_num_f16 v0, v0, v1, v9
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_max3_num_f16 v0, v0, v2, v8
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v4
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_max3_num_f16 v0, v0, v3, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_max3_num_f16 v0, v0, v4, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v6
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_max3_num_f16 v0, v0, v5, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_max3_num_f16 v0, v0, v6, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_max3_num_f16 v0, v0, v7, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fmax_v16half:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v1.l, v1.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v1.h, v1.h, v1.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v2.l, v2.l, v2.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v2.h, v2.h, v2.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.h, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v1.h, v3.l, v3.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v1.l, v2.l, v2.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v2.l, v3.h, v3.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v2.h, v4.l, v4.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v3.l, v4.h, v4.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v3.h, v5.l, v5.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v4.l, v5.h, v5.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v4.h, v6.l, v6.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v5.l, v6.h, v6.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v5.h, v7.l, v7.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v6.l, v7.h, v7.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v1.h, v1.h, v2.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v2.l, v2.h, v3.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v2.h, v3.h, v4.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v3.l, v4.h, v5.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v3.h, v5.h, v6.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.h, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v1.l, v2.l, v2.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v1.h, v3.l, v3.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.h, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmax_v16half:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v11, 16, v3
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v12, 16, v4
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 16, v5
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v8, v8, v8
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v1, v1, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v9, v9, v9
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v2, v2, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v10, v10, v10
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v6
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 16, v7
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v8
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v1, v1, v9
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v2, v2, v10
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v3, v3, v3
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v8, v11, v11
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v4, v4, v4
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v9, v12, v12
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v5, v5, v5
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v10, v13, v13
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v6, v6, v6
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v11, v14, v14
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v7, v7, v7
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v12, v15, v15
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v3, v3, v8
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v4, v4, v9
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v5, v5, v10
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v6, v6, v11
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v7, v7, v12
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v1, v2, v3
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v2, v4, v5
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v3, v6, v7
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v1, v2, v3
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fmax.v16half(<16 x half> %v)
   ret half %res
@@ -3192,6 +3580,8 @@ declare double @llvm.vector.reduce.fmax.v8double(<8 x double>)
 declare double @llvm.vector.reduce.fmax.v16double(<16 x double>)
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; GFX10: {{.*}}
+; GFX11: {{.*}}
+; GFX12: {{.*}}
 ; GFX7: {{.*}}
 ; GFX8: {{.*}}
 ; GFX9: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
index c486f29ce60f3..389df695ba324 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
@@ -3,8 +3,10 @@
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck -check-prefixes=GFX8,GFX8-SDAG %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
 
 define half @test_vector_reduce_fmaximum_v2half(<2 x half> %v) {
 ; GFX7-LABEL: test_vector_reduce_fmaximum_v2half:
@@ -48,27 +50,46 @@ define half @test_vector_reduce_fmaximum_v2half(<2 x half> %v) {
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_fmaximum_v2half:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_max_f16_e32 v2, v0, v1
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v1
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: test_vector_reduce_fmaximum_v2half:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_maximum_f16 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmaximum_v2half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmaximum_v2half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v2, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fmaximum_v2half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_maximum_f16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmaximum_v2half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_maximum_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fmaximum.v2half(<2 x half> %v)
   ret half %res
@@ -131,36 +152,64 @@ define half @test_vector_reduce_fmaximum_v3half(<3 x half> %v) {
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_fmaximum_v3half:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_max_f16_e32 v3, v0, v2
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v3, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_max_f16_e32 v2, v0, v1
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v1
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: test_vector_reduce_fmaximum_v3half:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_mov_b32 s0, 0xfc00
-; GFX12-NEXT:    s_wait_alu 0xfffe
-; GFX12-NEXT:    v_perm_b32 v1, s0, v1, 0x5040100
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_pk_maximum_f16 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_maximum_f16 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmaximum_v3half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmaximum_v3half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v3, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v2, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fmaximum_v3half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v2, 0xfc00
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_maximum_f16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_maximum_f16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmaximum_v3half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_mov_b32 s0, 0xfc00
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX12-SDAG-FAKE16-NEXT:    v_perm_b32 v1, s0, v1, 0x5040100
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_maximum_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_maximum_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fmaximum.v3half(<3 x half> %v)
   ret half %res
@@ -239,37 +288,66 @@ define half @test_vector_reduce_fmaximum_v4half(<4 x half> %v) {
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_fmaximum_v4half:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_max_f16_e32 v3, v0, v2
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v3, vcc_lo
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_max_f16_e32 v2, v0, v1
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v1
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_max_f16_e32 v1, v0, v3
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: test_vector_reduce_fmaximum_v4half:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_pk_maximum_f16 v0, v0, v1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-NEXT:    v_maximum_f16 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmaximum_v4half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmaximum_v4half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v3, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v2, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v1, v0, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fmaximum_v4half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_maximum_f16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_maximum_f16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmaximum_v4half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_maximum_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_maximum_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fmaximum.v4half(<4 x half> %v)
   ret half %res
@@ -410,58 +488,105 @@ define half @test_vector_reduce_fmaximum_v8half(<8 x half> %v) {
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_fmaximum_v8half:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_max_f16_e32 v5, v0, v4
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v4
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v5, vcc_lo
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_max_f16_e32 v4, v0, v1
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v1
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v4, vcc_lo
-; GFX11-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_max_f16_e32 v1, v0, v5
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v5
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_max_f16_e32 v1, v0, v2
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_max_f16_e32 v1, v0, v4
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v4
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_max_f16_e32 v1, v0, v3
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_max_f16_e32 v1, v0, v2
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: test_vector_reduce_fmaximum_v8half:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_pk_maximum_f16 v1, v1, v3
-; GFX12-NEXT:    v_pk_maximum_f16 v0, v0, v2
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_pk_maximum_f16 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_maximum_f16 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmaximum_v8half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v2.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v2.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v3.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v3.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmaximum_v8half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v5, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v5, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v4, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v1, v0, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v1, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v1, v0, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fmaximum_v8half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_maximum_f16 v1, v1, v3
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_maximum_f16 v0, v0, v2
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_maximum_f16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_maximum_f16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmaximum_v8half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_maximum_f16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_maximum_f16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_maximum_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_maximum_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fmaximum.v8half(<8 x half> %v)
   ret half %res
@@ -726,99 +851,183 @@ define half @test_vector_reduce_fmaximum_v16half(<16 x half> %v) {
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_fmaximum_v16half:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v8, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_max_f16_e32 v9, v0, v8
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v8
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v9, vcc_lo
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_max_f16_e32 v8, v0, v1
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v1
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v8, vcc_lo
-; GFX11-NEXT:    v_lshrrev_b32_e32 v8, 16, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_max_f16_e32 v1, v0, v9
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v9
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_max_f16_e32 v1, v0, v2
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_max_f16_e32 v1, v0, v8
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v8
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_max_f16_e32 v1, v0, v3
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_max_f16_e32 v1, v0, v2
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v4
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_max_f16_e32 v1, v0, v4
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v4
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_max_f16_e32 v1, v0, v2
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v5
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_max_f16_e32 v1, v0, v5
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v5
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_max_f16_e32 v1, v0, v2
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v6
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_max_f16_e32 v1, v0, v6
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v6
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_max_f16_e32 v1, v0, v2
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v7
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_max_f16_e32 v1, v0, v7
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v7
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_max_f16_e32 v1, v0, v2
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: test_vector_reduce_fmaximum_v16half:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_pk_maximum_f16 v3, v3, v7
-; GFX12-NEXT:    v_pk_maximum_f16 v1, v1, v5
-; GFX12-NEXT:    v_pk_maximum_f16 v2, v2, v6
-; GFX12-NEXT:    v_pk_maximum_f16 v0, v0, v4
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_pk_maximum_f16 v1, v1, v3
-; GFX12-NEXT:    v_pk_maximum_f16 v0, v0, v2
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_pk_maximum_f16 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_maximum_f16 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmaximum_v16half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v2.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v2.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v3.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v3.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v4.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v4.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v5.l
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v5.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v5.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v5.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v6.l
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v6.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v6.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v6.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v7.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v7.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmaximum_v16half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v9, v0, v8
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v8
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v9, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v8, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v8, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v1, v0, v9
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v9
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v1, v0, v8
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v8
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v1, v0, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v1, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v1, v0, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v1, v0, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v1, v0, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fmaximum_v16half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_maximum_f16 v3, v3, v7
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_maximum_f16 v1, v1, v5
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_maximum_f16 v2, v2, v6
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_maximum_f16 v0, v0, v4
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_maximum_f16 v1, v1, v3
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_maximum_f16 v0, v0, v2
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_maximum_f16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_maximum_f16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmaximum_v16half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_maximum_f16 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_maximum_f16 v1, v1, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_maximum_f16 v2, v2, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_maximum_f16 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_maximum_f16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_maximum_f16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_maximum_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_maximum_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fmaximum.v16half(<16 x half> %v)
   ret half %res
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
index 502d5840d24bb..56e7e045e40eb 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
@@ -7,10 +7,14 @@
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
 
 define half @test_vector_reduce_fmin_v2half(<2 x half> %v) {
 ; GFX7-SDAG-LABEL: test_vector_reduce_fmin_v2half:
@@ -80,29 +84,97 @@ define half @test_vector_reduce_fmin_v2half(<2 x half> %v) {
 ; GFX10-GISEL-NEXT:    v_min_f16_e32 v0, v1, v0
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_fmin_v2half:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX11-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: test_vector_reduce_fmin_v2half:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-NEXT:    v_max_num_f16_e32 v0, v0, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_max_num_f16_e32 v1, v1, v1
-; GFX12-NEXT:    v_min_num_f16_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v2half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.h, v0.h, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v2half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_fmin_v2half:
+; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.h, v0.h, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v2half:
+; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v2half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v2half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_max_num_f16_e32 v1, v1, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_min_num_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fmin_v2half:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v2half:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v0
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v1, v1, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fmin.v2half(<2 x half> %v)
   ret half %res
@@ -197,65 +269,119 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
 ; GFX10-GISEL-NEXT:    v_min_f16_e32 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_fmin_v3half:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX11-SDAG-NEXT:    v_pk_max_f16 v0, v0, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_pack_b32_f16 v1, v1, 0x7e00
-; GFX11-SDAG-NEXT:    v_pk_min_f16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: test_vector_reduce_fmin_v3half:
-; GFX11-GISEL:       ; %bb.0: ; %entry
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v2, v2, v2
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v0, v0, v2
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: test_vector_reduce_fmin_v3half:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_max_num_f16_e32 v1, v1, v1
-; GFX12-SDAG-NEXT:    v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pack_b32_f16 v1, v1, 0x7e00
-; GFX12-SDAG-NEXT:    v_pk_min_num_f16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    v_min_num_f16_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: test_vector_reduce_fmin_v3half:
-; GFX12-GISEL:       ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v0, v0, v0
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v1, v1, v1
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v2, v2, v2
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v0, v0, v2
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v0, v0, v1
-; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v3half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v1.l, v1.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_f16 v0, v0, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.l, 0x7e00
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_f16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v3half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_f16 v0, v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, 0x7e00
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_f16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_fmin_v3half:
+; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.h, v0.h, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.h, v1.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v3half:
+; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v2, v2, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v3half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_max_num_f16_e32 v1.l, v1.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_num_f16 v0, v0, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.l, 0x7e00
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_num_f16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v3half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_max_num_f16_e32 v1, v1, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_num_f16 v0, v0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, 0x7e00
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_num_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_min_num_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fmin_v3half:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.h, v1.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v3half:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v1, v1, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v2, v2, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v0, v0, v2
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fmin.v3half(<3 x half> %v)
   ret half %res
@@ -362,71 +488,127 @@ define half @test_vector_reduce_fmin_v4half(<4 x half> %v) {
 ; GFX10-GISEL-NEXT:    v_min_f16_e32 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_fmin_v4half:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_pk_max_f16 v1, v1, v1
-; GFX11-SDAG-NEXT:    v_pk_max_f16 v0, v0, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_pk_min_f16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: test_vector_reduce_fmin_v4half:
-; GFX11-GISEL:       ; %bb.0: ; %entry
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v2, v2, v2
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v3, v3, v3
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v0, v0, v2
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v1, v1, v3
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: test_vector_reduce_fmin_v4half:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-NEXT:    v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_min_num_f16 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_min_num_f16_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: test_vector_reduce_fmin_v4half:
-; GFX12-GISEL:       ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v0, v0, v0
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v1, v1, v1
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v2, v2, v2
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v3, v3, v3
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v0, v0, v2
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v1, v1, v3
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v0, v0, v1
-; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v4half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_f16 v1, v1, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_f16 v0, v0, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_f16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v4half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_f16 v1, v1, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_f16 v0, v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_f16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_fmin_v4half:
+; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.h, v0.h, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v1.l, v1.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v1.h, v1.h, v1.h
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v0.h, v1.l, v1.h
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v4half:
+; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v2, v2, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v3, v3, v3
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v1, v1, v3
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v4half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_num_f16 v1, v1, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_num_f16 v0, v0, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_num_f16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v4half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_num_f16 v1, v1, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_num_f16 v0, v0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_num_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_min_num_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fmin_v4half:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v1.l, v1.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v1.h, v1.h, v1.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v0.h, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v4half:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v1, v1, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v2, v2, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v3, v3, v3
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v0, v0, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v1, v1, v3
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fmin.v4half(<4 x half> %v)
   ret half %res
@@ -599,99 +781,181 @@ define half @test_vector_reduce_fmin_v8half(<8 x half> %v) {
 ; GFX10-GISEL-NEXT:    v_min_f16_e32 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_fmin_v8half:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_pk_max_f16 v3, v3, v3
-; GFX11-SDAG-NEXT:    v_pk_max_f16 v1, v1, v1
-; GFX11-SDAG-NEXT:    v_pk_max_f16 v2, v2, v2
-; GFX11-SDAG-NEXT:    v_pk_max_f16 v0, v0, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_pk_min_f16 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_pk_min_f16 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_pk_min_f16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: test_vector_reduce_fmin_v8half:
-; GFX11-GISEL:       ; %bb.0: ; %entry
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v7, 16, v3
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v4, v4, v4
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v5, v5, v5
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v2, v2, v2
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v6, v6, v6
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v3, v3, v3
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v7, v7, v7
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v0, v0, v4
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v1, v1, v5
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v2, v2, v6
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v3, v3, v7
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v1, v2, v3
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: test_vector_reduce_fmin_v8half:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_pk_max_num_f16 v3, v3, v3
-; GFX12-SDAG-NEXT:    v_pk_max_num_f16 v1, v1, v1
-; GFX12-SDAG-NEXT:    v_pk_max_num_f16 v2, v2, v2
-; GFX12-SDAG-NEXT:    v_pk_max_num_f16 v0, v0, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_pk_min_num_f16 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_pk_min_num_f16 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_min_num_f16 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_min_num_f16_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: test_vector_reduce_fmin_v8half:
-; GFX12-GISEL:       ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v7, 16, v3
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v0, v0, v0
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v1, v1, v1
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v4, v4, v4
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v5, v5, v5
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v2, v2, v2
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v6, v6, v6
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v3, v3, v3
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v7, v7, v7
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v0, v0, v4
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v1, v1, v5
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v2, v2, v6
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v3, v3, v7
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v0, v0, v1
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v1, v2, v3
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v0, v0, v1
-; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v8half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_f16 v3, v3, v3
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_f16 v1, v1, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_f16 v2, v2, v2
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_f16 v0, v0, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_f16 v1, v1, v3
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_f16 v0, v0, v2
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_f16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v8half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_f16 v3, v3, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_f16 v1, v1, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_f16 v2, v2, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_f16 v0, v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_f16 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_f16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_f16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_fmin_v8half:
+; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.h, v0.h, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v1.l, v1.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v1.h, v1.h, v1.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v2.l, v2.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v2.h, v2.h, v2.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v3.l, v3.l, v3.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v3.h, v3.h, v3.h
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v0.h, v1.l, v1.h
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v1.l, v2.l, v2.h
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v1.h, v3.l, v3.h
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v0.h, v1.l, v1.h
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v8half:
+; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v4, v4, v4
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v5, v5, v5
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v2, v2, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v6, v6, v6
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v3, v3, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v7, v7, v7
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v4
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v1, v1, v5
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v2, v2, v6
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v3, v3, v7
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v1, v2, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v8half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_num_f16 v3, v3, v3
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_num_f16 v1, v1, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_num_f16 v2, v2, v2
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_num_f16 v0, v0, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_num_f16 v1, v1, v3
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_num_f16 v0, v0, v2
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_num_f16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v8half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_num_f16 v3, v3, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_num_f16 v1, v1, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_num_f16 v2, v2, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_num_f16 v0, v0, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_num_f16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_num_f16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_num_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_min_num_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fmin_v8half:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v1.l, v1.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v1.h, v1.h, v1.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v2.l, v2.l, v2.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v2.h, v2.h, v2.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v3.l, v3.l, v3.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v3.h, v3.h, v3.h
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v0.h, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v1.l, v2.l, v2.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v1.h, v3.l, v3.h
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v0.h, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v8half:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v3
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v1, v1, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v4, v4, v4
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v5, v5, v5
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v2, v2, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v6, v6, v6
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v3, v3, v3
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v7, v7, v7
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v0, v0, v4
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v1, v1, v5
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v2, v2, v6
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v3, v3, v7
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v1, v2, v3
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fmin.v8half(<8 x half> %v)
   ret half %res
@@ -996,161 +1260,285 @@ define half @test_vector_reduce_fmin_v16half(<16 x half> %v) {
 ; GFX10-GISEL-NEXT:    v_min_f16_e32 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_fmin_v16half:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v8, 16, v0
-; GFX11-SDAG-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_max_f16_e32 v8, v8, v8
-; GFX11-SDAG-NEXT:    v_min_f16_e32 v0, v0, v8
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v8, 16, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_min3_f16 v0, v0, v1, v9
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
-; GFX11-SDAG-NEXT:    v_min3_f16 v0, v0, v2, v8
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 16, v4
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_min3_f16 v0, v0, v3, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v5
-; GFX11-SDAG-NEXT:    v_min3_f16 v0, v0, v4, v2
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 16, v6
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_min3_f16 v0, v0, v5, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v7
-; GFX11-SDAG-NEXT:    v_min3_f16 v0, v0, v6, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_min3_f16 v0, v0, v7, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: test_vector_reduce_fmin_v16half:
-; GFX11-GISEL:       ; %bb.0: ; %entry
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v8, 16, v0
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v10, 16, v2
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v11, 16, v3
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v12, 16, v4
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v13, 16, v5
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v0, v0, v0
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v8, v8, v8
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v9, v9, v9
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v2, v2, v2
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v10, v10, v10
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v14, 16, v6
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v15, 16, v7
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v0, v0, v8
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v1, v1, v9
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v2, v2, v10
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v3, v3, v3
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v8, v11, v11
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v4, v4, v4
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v9, v12, v12
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v5, v5, v5
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v10, v13, v13
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v6, v6, v6
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v11, v14, v14
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v7, v7, v7
-; GFX11-GISEL-NEXT:    v_max_f16_e32 v12, v15, v15
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v3, v3, v8
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v4, v4, v9
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v5, v5, v10
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v6, v6, v11
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v7, v7, v12
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v1, v2, v3
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v2, v4, v5
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v3, v6, v7
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v1, v2, v3
-; GFX11-GISEL-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: test_vector_reduce_fmin_v16half:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v8, 16, v0
-; GFX12-SDAG-NEXT:    v_max_num_f16_e32 v0, v0, v0
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_max_num_f16_e32 v8, v8, v8
-; GFX12-SDAG-NEXT:    v_min_num_f16_e32 v0, v0, v8
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v8, 16, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_min3_num_f16 v0, v0, v1, v9
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
-; GFX12-SDAG-NEXT:    v_min3_num_f16 v0, v0, v2, v8
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 16, v4
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_min3_num_f16 v0, v0, v3, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v5
-; GFX12-SDAG-NEXT:    v_min3_num_f16 v0, v0, v4, v2
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_min3_num_f16 v0, v0, v5, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v7
-; GFX12-SDAG-NEXT:    v_min3_num_f16 v0, v0, v6, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_min3_num_f16 v0, v0, v7, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: test_vector_reduce_fmin_v16half:
-; GFX12-GISEL:       ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v8, 16, v0
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v10, 16, v2
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v11, 16, v3
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v12, 16, v4
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v13, 16, v5
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v0, v0, v0
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v8, v8, v8
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v1, v1, v1
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v9, v9, v9
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v2, v2, v2
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v10, v10, v10
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v14, 16, v6
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v15, 16, v7
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v0, v0, v8
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v1, v1, v9
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v2, v2, v10
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v3, v3, v3
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v8, v11, v11
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v4, v4, v4
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v9, v12, v12
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v5, v5, v5
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v10, v13, v13
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v6, v6, v6
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v11, v14, v14
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v7, v7, v7
-; GFX12-GISEL-NEXT:    v_max_num_f16_e32 v12, v15, v15
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v3, v3, v8
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v4, v4, v9
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v5, v5, v10
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v6, v6, v11
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v7, v7, v12
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v0, v0, v1
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v1, v2, v3
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v2, v4, v5
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v3, v6, v7
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v0, v0, v1
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v1, v2, v3
-; GFX12-GISEL-NEXT:    v_min_num_f16_e32 v0, v0, v1
-; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v16half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.h, v0.h, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_min3_f16 v0.l, v0.l, v1.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_min3_f16 v0.l, v0.l, v2.l, v2.h
+; GFX11-SDAG-TRUE16-NEXT:    v_min3_f16 v0.l, v0.l, v3.l, v3.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_min3_f16 v0.l, v0.l, v4.l, v4.h
+; GFX11-SDAG-TRUE16-NEXT:    v_min3_f16 v0.l, v0.l, v5.l, v5.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_min3_f16 v0.l, v0.l, v6.l, v6.h
+; GFX11-SDAG-TRUE16-NEXT:    v_min3_f16 v0.l, v0.l, v7.l, v7.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v16half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_f16_e32 v8, v8, v8
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v8
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min3_f16 v0, v0, v1, v9
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_min3_f16 v0, v0, v2, v8
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v4
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min3_f16 v0, v0, v3, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_min3_f16 v0, v0, v4, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min3_f16 v0, v0, v5, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_min3_f16 v0, v0, v6, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_min3_f16 v0, v0, v7, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_fmin_v16half:
+; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v0.h, v0.h, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v1.l, v1.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v1.h, v1.h, v1.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v2.l, v2.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v2.h, v2.h, v2.h
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v0.h, v1.l, v1.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v1.h, v3.l, v3.l
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v1.l, v2.l, v2.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v2.l, v3.h, v3.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v2.h, v4.l, v4.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v3.l, v4.h, v4.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v3.h, v5.l, v5.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v4.l, v5.h, v5.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v4.h, v6.l, v6.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v5.l, v6.h, v6.h
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v5.h, v7.l, v7.l
+; GFX11-GISEL-TRUE16-NEXT:    v_max_f16_e32 v6.l, v7.h, v7.h
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v1.h, v1.h, v2.l
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v2.l, v2.h, v3.l
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v2.h, v3.h, v4.l
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v3.l, v4.h, v5.l
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v3.h, v5.h, v6.l
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v0.h, v1.l, v1.h
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v1.l, v2.l, v2.h
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v1.h, v3.l, v3.h
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v0.h, v1.l, v1.h
+; GFX11-GISEL-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v16half:
+; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v11, 16, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v12, 16, v4
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 16, v5
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v8, v8, v8
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v9, v9, v9
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v2, v2, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v10, v10, v10
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v6
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 16, v7
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v8
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v1, v1, v9
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v2, v2, v10
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v3, v3, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v8, v11, v11
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v4, v4, v4
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v9, v12, v12
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v5, v5, v5
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v10, v13, v13
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v6, v6, v6
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v11, v14, v14
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v7, v7, v7
+; GFX11-GISEL-FAKE16-NEXT:    v_max_f16_e32 v12, v15, v15
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v3, v3, v8
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v4, v4, v9
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v5, v5, v10
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v6, v6, v11
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v7, v7, v12
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v1, v2, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v2, v4, v5
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v3, v6, v7
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v1, v2, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v16half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_min3_num_f16 v0.l, v0.l, v1.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_min3_num_f16 v0.l, v0.l, v2.l, v2.h
+; GFX12-SDAG-TRUE16-NEXT:    v_min3_num_f16 v0.l, v0.l, v3.l, v3.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_min3_num_f16 v0.l, v0.l, v4.l, v4.h
+; GFX12-SDAG-TRUE16-NEXT:    v_min3_num_f16 v0.l, v0.l, v5.l, v5.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_min3_num_f16 v0.l, v0.l, v6.l, v6.h
+; GFX12-SDAG-TRUE16-NEXT:    v_min3_num_f16 v0.l, v0.l, v7.l, v7.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v16half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_max_num_f16_e32 v8, v8, v8
+; GFX12-SDAG-FAKE16-NEXT:    v_min_num_f16_e32 v0, v0, v8
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_min3_num_f16 v0, v0, v1, v9
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_min3_num_f16 v0, v0, v2, v8
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v4
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_min3_num_f16 v0, v0, v3, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_min3_num_f16 v0, v0, v4, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v6
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_min3_num_f16 v0, v0, v5, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_min3_num_f16 v0, v0, v6, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_min3_num_f16 v0, v0, v7, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fmin_v16half:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v0.h, v0.h, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v1.l, v1.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v1.h, v1.h, v1.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v2.l, v2.l, v2.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v2.h, v2.h, v2.h
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v0.h, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v1.h, v3.l, v3.l
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v1.l, v2.l, v2.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v2.l, v3.h, v3.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v2.h, v4.l, v4.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v3.l, v4.h, v4.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v3.h, v5.l, v5.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v4.l, v5.h, v5.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v4.h, v6.l, v6.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v5.l, v6.h, v6.h
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v5.h, v7.l, v7.l
+; GFX12-GISEL-TRUE16-NEXT:    v_max_num_f16_e32 v6.l, v7.h, v7.h
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v1.h, v1.h, v2.l
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v2.l, v2.h, v3.l
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v2.h, v3.h, v4.l
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v3.l, v4.h, v5.l
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v3.h, v5.h, v6.l
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v0.h, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v1.l, v2.l, v2.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v1.h, v3.l, v3.h
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v0.h, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT:    v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmin_v16half:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v11, 16, v3
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v12, 16, v4
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 16, v5
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v0, v0, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v8, v8, v8
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v1, v1, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v9, v9, v9
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v2, v2, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v10, v10, v10
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v6
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 16, v7
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v0, v0, v8
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v1, v1, v9
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v2, v2, v10
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v3, v3, v3
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v8, v11, v11
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v4, v4, v4
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v9, v12, v12
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v5, v5, v5
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v10, v13, v13
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v6, v6, v6
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v11, v14, v14
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v7, v7, v7
+; GFX12-GISEL-FAKE16-NEXT:    v_max_num_f16_e32 v12, v15, v15
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v3, v3, v8
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v4, v4, v9
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v5, v5, v10
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v6, v6, v11
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v7, v7, v12
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v1, v2, v3
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v2, v4, v5
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v3, v6, v7
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v1, v2, v3
+; GFX12-GISEL-FAKE16-NEXT:    v_min_num_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fmin.v16half(<16 x half> %v)
   ret half %res
@@ -3191,6 +3579,8 @@ declare double @llvm.vector.reduce.fmin.v8double(<8 x double>)
 declare double @llvm.vector.reduce.fmin.v16double(<16 x double>)
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; GFX10: {{.*}}
+; GFX11: {{.*}}
+; GFX12: {{.*}}
 ; GFX7: {{.*}}
 ; GFX8: {{.*}}
 ; GFX9: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
index 9ca391682459a..2f628b7cdb281 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
@@ -3,9 +3,12 @@
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck -check-prefixes=GFX8,GFX8-SDAG %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
 
 define half @test_vector_reduce_fminimum_v2half(<2 x half> %v) {
 ; GFX7-LABEL: test_vector_reduce_fminimum_v2half:
@@ -49,27 +52,68 @@ define half @test_vector_reduce_fminimum_v2half(<2 x half> %v) {
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_fminimum_v2half:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_min_f16_e32 v2, v0, v1
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v1
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: test_vector_reduce_fminimum_v2half:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_minimum_f16 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fminimum_v2half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fminimum_v2half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v2, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fminimum_v2half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_minimum_f16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fminimum_v2half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_minimum_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fminimum_v2half:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fminimum_v2half:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fminimum.v2half(<2 x half> %v)
   ret half %res
@@ -132,49 +176,89 @@ define half @test_vector_reduce_fminimum_v3half(<3 x half> %v) {
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_fminimum_v3half:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_min_f16_e32 v3, v0, v2
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v3, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_min_f16_e32 v2, v0, v1
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v1
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: test_vector_reduce_fminimum_v3half:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    s_movk_i32 s0, 0x7c00
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffe
-; GFX12-SDAG-NEXT:    v_perm_b32 v1, s0, v1, 0x5040100
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_minimum_f16 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_minimum_f16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: test_vector_reduce_fminimum_v3half:
-; GFX12-GISEL:       ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT:    v_minimum_f16 v0, v0, v2
-; GFX12-GISEL-NEXT:    v_minimum_f16 v0, v0, v1
-; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fminimum_v3half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fminimum_v3half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v3, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v2, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fminimum_v3half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v2, 0x7c00
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_minimum_f16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_minimum_f16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fminimum_v3half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_movk_i32 s0, 0x7c00
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX12-SDAG-FAKE16-NEXT:    v_perm_b32 v1, s0, v1, 0x5040100
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_minimum_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_minimum_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fminimum_v3half:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fminimum_v3half:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v0, v0, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fminimum.v3half(<3 x half> %v)
   ret half %res
@@ -253,53 +337,95 @@ define half @test_vector_reduce_fminimum_v4half(<4 x half> %v) {
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_fminimum_v4half:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_min_f16_e32 v3, v0, v2
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v3, vcc_lo
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_min_f16_e32 v2, v0, v1
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v1
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_min_f16_e32 v1, v0, v3
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: test_vector_reduce_fminimum_v4half:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_pk_minimum_f16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    v_minimum_f16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: test_vector_reduce_fminimum_v4half:
-; GFX12-GISEL:       ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT:    v_minimum_f16 v0, v0, v2
-; GFX12-GISEL-NEXT:    v_minimum_f16 v1, v1, v3
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT:    v_minimum_f16 v0, v0, v1
-; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fminimum_v4half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fminimum_v4half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v3, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v3, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v2, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v1, v0, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fminimum_v4half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_minimum_f16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_minimum_f16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fminimum_v4half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_minimum_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_minimum_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fminimum_v4half:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v0.h, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fminimum_v4half:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v0, v0, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v1, v1, v3
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fminimum.v4half(<4 x half> %v)
   ret half %res
@@ -440,82 +566,147 @@ define half @test_vector_reduce_fminimum_v8half(<8 x half> %v) {
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_fminimum_v8half:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_min_f16_e32 v5, v0, v4
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v4
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v5, vcc_lo
-; GFX11-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_min_f16_e32 v4, v0, v1
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v1
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v4, vcc_lo
-; GFX11-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_min_f16_e32 v1, v0, v5
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v5
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_min_f16_e32 v1, v0, v2
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_min_f16_e32 v1, v0, v4
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v4
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_min_f16_e32 v1, v0, v3
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_min_f16_e32 v1, v0, v2
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: test_vector_reduce_fminimum_v8half:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_pk_minimum_f16 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_pk_minimum_f16 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_minimum_f16 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_minimum_f16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: test_vector_reduce_fminimum_v8half:
-; GFX12-GISEL:       ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v7, 16, v3
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT:    v_minimum_f16 v0, v0, v4
-; GFX12-GISEL-NEXT:    v_minimum_f16 v1, v1, v5
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-GISEL-NEXT:    v_minimum_f16 v2, v2, v6
-; GFX12-GISEL-NEXT:    v_minimum_f16 v3, v3, v7
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-NEXT:    v_minimum_f16 v0, v0, v1
-; GFX12-GISEL-NEXT:    v_minimum_f16 v1, v2, v3
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT:    v_minimum_f16 v0, v0, v1
-; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fminimum_v8half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v2.h
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v2.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v3.h
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v3.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fminimum_v8half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v5, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v5, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v4, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v4, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v1, v0, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v1, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v1, v0, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fminimum_v8half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_minimum_f16 v1, v1, v3
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_minimum_f16 v0, v0, v2
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_minimum_f16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_minimum_f16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fminimum_v8half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_minimum_f16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_minimum_f16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_minimum_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_minimum_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fminimum_v8half:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v0.h, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v1.l, v2.l, v2.h
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v1.h, v3.l, v3.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v0.h, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fminimum_v8half:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v3
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v0, v0, v4
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v1, v1, v5
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v2, v2, v6
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v3, v3, v7
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v1, v2, v3
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fminimum.v8half(<8 x half> %v)
   ret half %res
@@ -780,133 +971,243 @@ define half @test_vector_reduce_fminimum_v16half(<16 x half> %v) {
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_fminimum_v16half:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v8, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_min_f16_e32 v9, v0, v8
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v8
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v9, vcc_lo
-; GFX11-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_min_f16_e32 v8, v0, v1
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v1
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v8, vcc_lo
-; GFX11-NEXT:    v_lshrrev_b32_e32 v8, 16, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_min_f16_e32 v1, v0, v9
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v9
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_min_f16_e32 v1, v0, v2
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_min_f16_e32 v1, v0, v8
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v8
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_min_f16_e32 v1, v0, v3
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v3
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_min_f16_e32 v1, v0, v2
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v4
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_min_f16_e32 v1, v0, v4
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v4
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_min_f16_e32 v1, v0, v2
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v5
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_min_f16_e32 v1, v0, v5
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v5
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_min_f16_e32 v1, v0, v2
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v6
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_min_f16_e32 v1, v0, v6
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v6
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_min_f16_e32 v1, v0, v2
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v7
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_min_f16_e32 v1, v0, v7
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v7
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_min_f16_e32 v1, v0, v2
-; GFX11-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: test_vector_reduce_fminimum_v16half:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_pk_minimum_f16 v3, v3, v7
-; GFX12-SDAG-NEXT:    v_pk_minimum_f16 v1, v1, v5
-; GFX12-SDAG-NEXT:    v_pk_minimum_f16 v2, v2, v6
-; GFX12-SDAG-NEXT:    v_pk_minimum_f16 v0, v0, v4
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_pk_minimum_f16 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_pk_minimum_f16 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_minimum_f16 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_minimum_f16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: test_vector_reduce_fminimum_v16half:
-; GFX12-GISEL:       ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v8, 16, v0
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v10, 16, v2
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v11, 16, v3
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v12, 16, v4
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v13, 16, v5
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v14, 16, v6
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v15, 16, v7
-; GFX12-GISEL-NEXT:    v_minimum_f16 v0, v0, v8
-; GFX12-GISEL-NEXT:    v_minimum_f16 v1, v1, v9
-; GFX12-GISEL-NEXT:    v_minimum_f16 v2, v2, v10
-; GFX12-GISEL-NEXT:    v_minimum_f16 v3, v3, v11
-; GFX12-GISEL-NEXT:    v_minimum_f16 v4, v4, v12
-; GFX12-GISEL-NEXT:    v_minimum_f16 v5, v5, v13
-; GFX12-GISEL-NEXT:    v_minimum_f16 v6, v6, v14
-; GFX12-GISEL-NEXT:    v_minimum_f16 v7, v7, v15
-; GFX12-GISEL-NEXT:    v_minimum_f16 v0, v0, v1
-; GFX12-GISEL-NEXT:    v_minimum_f16 v1, v2, v3
-; GFX12-GISEL-NEXT:    v_minimum_f16 v2, v4, v5
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-GISEL-NEXT:    v_minimum_f16 v3, v6, v7
-; GFX12-GISEL-NEXT:    v_minimum_f16 v0, v0, v1
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT:    v_minimum_f16 v1, v2, v3
-; GFX12-GISEL-NEXT:    v_minimum_f16 v0, v0, v1
-; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fminimum_v16half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v2.h
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v2.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v3.h
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v3.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v4.h
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v4.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v5.l
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v5.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v5.h
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v5.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v6.l
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v6.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v6.h
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v6.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0.l, v7.h
+; GFX11-SDAG-TRUE16-NEXT:    v_min_f16_e32 v0.l, v0.l, v7.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fminimum_v16half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v9, v0, v8
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v8
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v9, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v8, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v8, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v1, v0, v9
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v9
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v1, v0, v8
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v8
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v1, v0, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v1, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v1, v0, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v1, v0, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v1, v0, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_f16_e32 v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cmp_o_f16_e32 vcc_lo, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v1, vcc_lo
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fminimum_v16half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_minimum_f16 v3, v3, v7
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_minimum_f16 v1, v1, v5
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_minimum_f16 v2, v2, v6
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_minimum_f16 v0, v0, v4
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_minimum_f16 v1, v1, v3
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_minimum_f16 v0, v0, v2
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_minimum_f16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_minimum_f16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fminimum_v16half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_minimum_f16 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_minimum_f16 v1, v1, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_minimum_f16 v2, v2, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_minimum_f16 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_minimum_f16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_minimum_f16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_minimum_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_minimum_f16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fminimum_v16half:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v0.h, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v1.l, v2.l, v2.h
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v1.h, v3.l, v3.h
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v2.l, v4.l, v4.h
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v2.h, v5.l, v5.h
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v3.l, v6.l, v6.h
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v3.h, v7.l, v7.h
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v0.h, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v1.l, v2.l, v2.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v1.h, v3.l, v3.h
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v0.h, v1.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT:    v_minimum_f16 v0.l, v0.l, v0.h
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fminimum_v16half:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v11, 16, v3
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v12, 16, v4
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 16, v5
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v14, 16, v6
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 16, v7
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v0, v0, v8
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v1, v1, v9
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v2, v2, v10
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v3, v3, v11
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v4, v4, v12
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v5, v5, v13
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v6, v6, v14
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v7, v7, v15
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v1, v2, v3
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v2, v4, v5
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v3, v6, v7
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v1, v2, v3
+; GFX12-GISEL-FAKE16-NEXT:    v_minimum_f16 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fminimum.v16half(<16 x half> %v)
   ret half %res
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
index d40625ac7353f..657fe0f0804f3 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
@@ -7,10 +7,14 @@
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
 
 define half @test_vector_reduce_fmul_v2half(half %sp, <2 x half> %v) {
 ; GFX7-SDAG-LABEL: test_vector_reduce_fmul_v2half:
@@ -60,27 +64,91 @@ define half @test_vector_reduce_fmul_v2half(half %sp, <2 x half> %v) {
 ; GFX10-NEXT:    v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_fmul_v2half:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: test_vector_reduce_fmul_v2half:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmul_v2half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmul_v2half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_fmul_v2half:
+; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmul_v2half:
+; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fmul_v2half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmul_v2half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fmul_v2half:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmul_v2half:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fmul.v2half(half %sp, <2 x half> %v)
   ret half %res
@@ -144,53 +212,97 @@ define half @test_vector_reduce_fmul_v3half(half %sp, <3 x half> %v) {
 ; GFX10-NEXT:    v_mul_f16_e32 v0, v0, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_fmul_v3half:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_mul_f16_e32 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-GISEL-LABEL: test_vector_reduce_fmul_v3half:
-; GFX11-GISEL:       ; %bb.0: ; %entry
-; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-GISEL-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_mul_f16_e32 v0, v0, v3
-; GFX11-GISEL-NEXT:    v_mul_f16_e32 v0, v0, v2
-; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-SDAG-LABEL: test_vector_reduce_fmul_v3half:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_mul_f16_e32 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-GISEL-LABEL: test_vector_reduce_fmul_v3half:
-; GFX12-GISEL:       ; %bb.0: ; %entry
-; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
-; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-GISEL-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-GISEL-NEXT:    v_mul_f16_e32 v0, v0, v3
-; GFX12-GISEL-NEXT:    v_mul_f16_e32 v0, v0, v2
-; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmul_v3half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmul_v3half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_fmul_v3half:
+; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.h
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmul_v3half:
+; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fmul_v3half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmul_v3half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fmul_v3half:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.h
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v2.l
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmul_v3half:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v3
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v2
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fmul.v3half(half %sp, <3 x half> %v)
   ret half %res
@@ -264,35 +376,121 @@ define half @test_vector_reduce_fmul_v4half(half %sp, <4 x half> %v) {
 ; GFX10-NEXT:    v_mul_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_fmul_v4half:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: test_vector_reduce_fmul_v4half:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v2
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmul_v4half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v2.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmul_v4half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_fmul_v4half:
+; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmul_v4half:
+; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fmul_v4half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v2.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmul_v4half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fmul_v4half:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v2.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmul_v4half:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v2
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fmul.v4half(half %sp, <4 x half> %v)
   ret half %res
@@ -406,51 +604,181 @@ define half @test_vector_reduce_fmul_v8half(half %sp, <8 x half> %v) {
 ; GFX10-NEXT:    v_mul_f16_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_fmul_v8half:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: test_vector_reduce_fmul_v8half:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v2
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v3
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v4
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmul_v8half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v2.h
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v3.h
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v4.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmul_v8half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v3
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_fmul_v8half:
+; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v3.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v4.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmul_v8half:
+; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v3
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v4
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fmul_v8half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v2.h
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v3.h
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v4.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v4.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmul_v8half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v3
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fmul_v8half:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v2.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v3.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v4.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmul_v8half:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v2
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v3
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v4
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fmul.v8half(half %sp, <8 x half> %v)
   ret half %res
@@ -644,83 +972,301 @@ define half @test_vector_reduce_fmul_v16half(half %sp, <16 x half> %v) {
 ; GFX10-NEXT:    v_mul_f16_sdwa v0, v0, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_fmul_v16half:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v5
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v5
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v6
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v6
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v7
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v8
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v8
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX12-LABEL: test_vector_reduce_fmul_v16half:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v2
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v3
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v4
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v5
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v5
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v6
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v6
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v7
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v7
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v8
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v8
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmul_v16half:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v2.h
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v3.h
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v4.h
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v5.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v5.h
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v6.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v6.h
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v7.h
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v8.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v8.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmul_v16half:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v3
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v5
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v6
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v7
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v8
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v8
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_fmul_v16half:
+; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v3.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v4.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v5
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v5.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v6
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v6.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v7
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v7.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v8
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v8.l
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: test_vector_reduce_fmul_v16half:
+; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v3
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v4
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v5
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v5
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v6
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v6
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v7
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v7
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v8
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v8
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_fmul_v16half:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v2.h
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v3.h
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v4.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v4.h
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v5.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v5.h
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v6.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v6.h
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v7.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v7.h
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v8.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v8.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmul_v16half:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v3
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v5
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v6
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v7
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v8
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v8
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_fmul_v16half:
+; GFX12-GISEL-TRUE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v2.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v3.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v4.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v5
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v5.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v6
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v6.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v7
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v7.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v8
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v8.l
+; GFX12-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-FAKE16-LABEL: test_vector_reduce_fmul_v16half:
+; GFX12-GISEL-FAKE16:       ; %bb.0: ; %entry
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v2
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v3
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v4
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v4
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v5
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v5
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v6
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v6
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v7
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v7
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v8
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v8
+; GFX12-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX12-GISEL-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call half @llvm.vector.reduce.fmul.v16half(half %sp, <16 x half> %v)
   ret half %res
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
index e035256694ad5..98919f565d902 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
@@ -7,10 +7,15 @@
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
+; FIXME-TRUE16. enable gisel
+; XUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
+; XUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
 
 define i8 @test_vector_reduce_mul_v2i8(<2 x i8> %v) {
 ; GFX7-SDAG-LABEL: test_vector_reduce_mul_v2i8:
@@ -71,18 +76,31 @@ define i8 @test_vector_reduce_mul_v2i8(<2 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_mul_lo_u16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_mul_v2i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_lshrrev_b16 v2, 8, v1
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v1, v1, v2
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_mul_v2i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b16 v0.h, 8, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.h, v1.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v2i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b16 v2, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v1, v1, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_mul_v2i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -90,22 +108,39 @@ define i8 @test_vector_reduce_mul_v2i8(<2 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_mul_lo_u16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_mul_v2i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_lshrrev_b16 v2, 8, v1
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v1, v1, v2
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_mul_v2i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_lshrrev_b16 v0.h, 8, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.h, v1.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v2i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b16 v2, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v1, v1, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_mul_v2i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -178,13 +213,21 @@ define i8 @test_vector_reduce_mul_v3i8(<3 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_mul_lo_u16 v0, v0, v2
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_mul_v3i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v0, v1, v0
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_mul_v3i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v3i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v0, v1, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_mul_v3i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -194,17 +237,29 @@ define i8 @test_vector_reduce_mul_v3i8(<3 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_mul_lo_u16 v0, v0, v2
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_mul_v3i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v0, v1, v0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_mul_v3i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v1.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v3i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v0, v1, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_mul_v3i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -295,15 +350,25 @@ define i8 @test_vector_reduce_mul_v4i8(<4 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_mul_v4i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_mul_v4i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.h, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v4i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_mul_v4i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -315,19 +380,33 @@ define i8 @test_vector_reduce_mul_v4i8(<4 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_mul_v4i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_mul_v4i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.h, v1.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v4i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_mul_v4i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -452,20 +531,35 @@ define i8 @test_vector_reduce_mul_v8i8(<8 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_mul_v8i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v2, v2, v6
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v3, v3, v7
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v1, v1, v5
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v0, v0, v4
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_mul_v8i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.h, v2.l, v6.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v1.h, v3.l, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v1.l, v1.l, v5.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v1.l, v1.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v8i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v2, v2, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v3, v3, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v1, v1, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_mul_v8i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -482,24 +576,43 @@ define i8 @test_vector_reduce_mul_v8i8(<8 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_mul_v8i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v2, v2, v6
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v3, v3, v7
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v1, v1, v5
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v0, v0, v4
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_mul_v8i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.h, v2.l, v6.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v1.h, v3.l, v7.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v1.l, v1.l, v5.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v4.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v1.l, v1.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v8i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v2, v2, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v1, v1, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_mul_v8i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -693,29 +806,53 @@ define i8 @test_vector_reduce_mul_v16i8(<16 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_mul_v16i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v5, v5, v13
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v1, v1, v9
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v7, v7, v15
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v6, v6, v14
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v2, v2, v10
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v3, v3, v11
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v4, v4, v12
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v0, v0, v8
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v1, v1, v5
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v2, v2, v6
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v3, v3, v7
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v0, v0, v4
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v1, v1, v3
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v0, v0, v2
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_mul_v16i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v1.h, v5.l, v13.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v1.l, v1.l, v9.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v5.l, v7.l, v15.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.h, v6.l, v14.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v2.l, v2.l, v10.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v2.h, v3.l, v11.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v3.l, v4.l, v12.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v8.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v1.l, v1.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.h, v2.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v2.l, v2.h, v5.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v1.l, v1.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v16i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v5, v5, v13
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v1, v1, v9
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v7, v7, v15
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v6, v6, v14
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v2, v2, v10
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v3, v3, v11
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v4, v4, v12
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v8
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v1, v1, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v2, v2, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v3, v3, v7
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_mul_v16i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -742,33 +879,61 @@ define i8 @test_vector_reduce_mul_v16i8(<16 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_mul_v16i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v5, v5, v13
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v1, v1, v9
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v7, v7, v15
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v6, v6, v14
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v2, v2, v10
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v3, v3, v11
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v4, v4, v12
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v0, v0, v8
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v1, v1, v5
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v2, v2, v6
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v3, v3, v7
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v0, v0, v4
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v1, v1, v3
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v0, v0, v2
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_mul_v16i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v1.h, v5.l, v13.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v1.l, v1.l, v9.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v5.l, v7.l, v15.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.h, v6.l, v14.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v2.l, v2.l, v10.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v2.h, v3.l, v11.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v3.l, v4.l, v12.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v8.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v1.l, v1.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.h, v2.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v2.l, v2.h, v5.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v1.l, v1.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v16i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v5, v5, v13
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v1, v1, v9
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v7, v7, v15
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v6, v6, v14
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v2, v2, v10
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v3, v3, v11
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v4, v4, v12
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v8
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v1, v1, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v2, v2, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_mul_v16i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -856,13 +1021,22 @@ define i16 @test_vector_reduce_mul_v2i16(<2 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_mul_v2i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_alignbit_b32 v1, s0, v0, 16
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_mul_v2i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v2i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_alignbit_b32 v1, s0, v0, 16
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_mul_v2i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -872,17 +1046,30 @@ define i16 @test_vector_reduce_mul_v2i16(<2 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_mul_v2i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_alignbit_b32 v1, s0, v0, 16
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_mul_v2i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v2i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_alignbit_b32 v1, s0, v0, 16
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_mul_v2i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -964,16 +1151,25 @@ define i16 @test_vector_reduce_mul_v3i16(<3 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_mul_lo_u16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_mul_v3i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_perm_b32 v1, 1, v1, 0x5040100
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_mul_lo_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_mul_v3i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, 1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v3i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_perm_b32 v1, 1, v1, 0x5040100
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_mul_v3i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -984,20 +1180,33 @@ define i16 @test_vector_reduce_mul_v3i16(<3 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_mul_lo_u16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_mul_v3i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_perm_b32 v1, 1, v1, 0x5040100
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_mul_lo_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_mul_v3i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, 1
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_mul_lo_u16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v3i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_perm_b32 v1, 1, v1, 0x5040100
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_mul_lo_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_mul_v3i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1085,14 +1294,25 @@ define i16 @test_vector_reduce_mul_v4i16(<4 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_mul_v4i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_alignbit_b32 v1, s0, v0, 16
-; GFX11-SDAG-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_mul_v4i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-TRUE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v4i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_alignbit_b32 v1, s0, v0, 16
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_mul_v4i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1103,18 +1323,33 @@ define i16 @test_vector_reduce_mul_v4i16(<4 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_mul_v4i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_alignbit_b32 v1, s0, v0, 16
-; GFX12-SDAG-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_mul_v4i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-TRUE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v4i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_alignbit_b32 v1, s0, v0, 16
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_mul_v4i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1228,17 +1463,30 @@ define i16 @test_vector_reduce_mul_v8i16(<8 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_mul_v8i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_pk_mul_lo_u16 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_pk_mul_lo_u16 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_alignbit_b32 v1, s0, v0, 16
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_mul_v8i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v1, v1, v3
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v2
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v8i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_alignbit_b32 v1, s0, v0, 16
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_mul_v8i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1252,21 +1500,38 @@ define i16 @test_vector_reduce_mul_v8i16(<8 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_mul_v8i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_pk_mul_lo_u16 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_pk_mul_lo_u16 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_alignbit_b32 v1, s0, v0, 16
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_mul_v8i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v1, v1, v3
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v2
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v8i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_alignbit_b32 v1, s0, v0, 16
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_mul_v8i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1431,22 +1696,40 @@ define i16 @test_vector_reduce_mul_v16i16(<16 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_mul_v16i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_pk_mul_lo_u16 v2, v2, v6
-; GFX11-SDAG-NEXT:    v_pk_mul_lo_u16 v3, v3, v7
-; GFX11-SDAG-NEXT:    v_pk_mul_lo_u16 v1, v1, v5
-; GFX11-SDAG-NEXT:    v_pk_mul_lo_u16 v0, v0, v4
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_pk_mul_lo_u16 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_pk_mul_lo_u16 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_alignbit_b32 v1, s0, v0, 16
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_mul_v16i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v2, v2, v6
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v3, v3, v7
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v1, v1, v5
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v4
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v1, v1, v3
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v2
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v16i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v2, v2, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v3, v3, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v1, v1, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_alignbit_b32 v1, s0, v0, 16
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_mul_v16i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1465,26 +1748,48 @@ define i16 @test_vector_reduce_mul_v16i16(<16 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_mul_v16i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_pk_mul_lo_u16 v2, v2, v6
-; GFX12-SDAG-NEXT:    v_pk_mul_lo_u16 v3, v3, v7
-; GFX12-SDAG-NEXT:    v_pk_mul_lo_u16 v1, v1, v5
-; GFX12-SDAG-NEXT:    v_pk_mul_lo_u16 v0, v0, v4
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_pk_mul_lo_u16 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_pk_mul_lo_u16 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_alignbit_b32 v1, s0, v0, 16
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_mul_v16i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v2, v2, v6
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v3, v3, v7
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v1, v1, v5
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v4
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v1, v1, v3
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v2
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v16i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v2, v2, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v1, v1, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_alignbit_b32 v1, s0, v0, 16
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_mul_lo_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_mul_v16i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -4029,3 +4334,6 @@ declare i64 @llvm.vector.reduce.mul.v3i64(<3 x i64>)
 declare i64 @llvm.vector.reduce.mul.v4i64(<4 x i64>)
 declare i64 @llvm.vector.reduce.mul.v8i64(<8 x i64>)
 declare i64 @llvm.vector.reduce.mul.v16i64(<16 x i64>)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11-GISEL-FAKE16: {{.*}}
+; GFX12-GISEL-FAKE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
index 46b6e0079a99c..bdb1c22ce7267 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
@@ -7,10 +7,15 @@
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
+; FIXME-TRUE16. enable gisel
+; XUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
+; XUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
 
 define i8 @test_vector_reduce_or_v2i8(<2 x i8> %v) {
 ; GFX7-SDAG-LABEL: test_vector_reduce_or_v2i8:
@@ -70,18 +75,31 @@ define i8 @test_vector_reduce_or_v2i8(<2 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_or_v2i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_lshrrev_b16 v2, 8, v1
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v1, v1, v2
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_or_v2i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b16 v0.h, 8, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.h, v1.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_or_v2i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b16 v2, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_or_v2i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -89,22 +107,39 @@ define i8 @test_vector_reduce_or_v2i8(<2 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_or_v2i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_lshrrev_b16 v2, 8, v1
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v1, v1, v2
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_or_v2i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_lshrrev_b16 v0.h, 8, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.h, v1.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_or_v2i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b16 v2, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_or_v2i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -175,13 +210,21 @@ define i8 @test_vector_reduce_or_v3i8(<3 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_or3_b32 v0, v0, v1, v2
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_or_v3i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_or_v3i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_or_v3i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_or_v3i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -189,17 +232,29 @@ define i8 @test_vector_reduce_or_v3i8(<3 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_or3_b32 v0, v0, v1, v2
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_or_v3i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_or_v3i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_or_v3i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_or_v3i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -300,15 +355,25 @@ define i8 @test_vector_reduce_or_v4i8(<4 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_or3_b32 v0, 0xff0000, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_or_v4i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, 0xffffff00, v0
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_or_v4i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.h, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, 0xff00, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_or_v4i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, 0xffffff00, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_or_v4i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -323,19 +388,33 @@ define i8 @test_vector_reduce_or_v4i8(<4 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_or3_b32 v0, 0xff0000, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_or_v4i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, 0xffffff00, v0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_or_v4i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.h, v1.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, 0xff00, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_or_v4i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, 0xffffff00, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_or_v4i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -473,20 +552,35 @@ define i8 @test_vector_reduce_or_v8i8(<8 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_or3_b32 v0, 0xff0000, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_or_v8i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v2, v2, v6
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v3, v3, v7
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v1, v1, v5
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v4
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, 0xffffff00, v0
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_or_v8i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.h, v2.l, v6.l
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v1.h, v3.l, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v5.l
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, 0xff00, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_or_v8i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, 0xffffff00, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_or_v8i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -504,24 +598,43 @@ define i8 @test_vector_reduce_or_v8i8(<8 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_or3_b32 v0, 0xff0000, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_or_v8i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v2, v2, v6
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v3, v3, v7
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v1, v1, v5
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, v0, v4
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, 0xffffff00, v0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_or_v8i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.h, v2.l, v6.l
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v1.h, v3.l, v7.l
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v5.l
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v4.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, 0xff00, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_or_v8i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, 0xffffff00, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_or_v8i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -720,29 +833,53 @@ define i8 @test_vector_reduce_or_v16i8(<16 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_or3_b32 v0, 0xff0000, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_or_v16i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v5, v5, v13
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v1, v1, v9
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v7, v7, v15
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v6, v6, v14
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v2, v2, v10
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v3, v3, v11
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v4, v4, v12
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v8
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v1, v1, v5
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v2, v2, v6
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v3, v3, v7
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v4
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v1, v1, v3
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v2
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, 0xffffff00, v0
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_or_v16i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v1.h, v5.l, v13.l
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v9.l
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v5.l, v7.l, v15.l
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.h, v6.l, v14.l
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v10.l
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v2.h, v3.l, v11.l
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v3.l, v4.l, v12.l
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v8.l
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.h, v2.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v2.l, v2.h, v5.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, 0xff00, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_or_v16i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v9
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v15
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v14
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v10
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v11
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v12
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v8
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v7
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, 0xffffff00, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_or_v16i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -766,33 +903,61 @@ define i8 @test_vector_reduce_or_v16i8(<16 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_or3_b32 v0, 0xff0000, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_or_v16i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v5, v5, v13
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v1, v1, v9
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v7, v7, v15
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v6, v6, v14
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v2, v2, v10
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v3, v3, v11
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v4, v4, v12
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, v0, v8
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v1, v1, v5
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v2, v2, v6
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v3, v3, v7
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, v0, v4
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v1, v1, v3
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, v0, v2
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, 0xffffff00, v0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_or_v16i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v1.h, v5.l, v13.l
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v9.l
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v5.l, v7.l, v15.l
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.h, v6.l, v14.l
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v2.l, v2.l, v10.l
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v2.h, v3.l, v11.l
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v3.l, v4.l, v12.l
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v8.l
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.h, v2.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v2.l, v2.h, v5.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v1.l, v1.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, 0xff00, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_or_v16i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v9
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v7, v7, v15
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v6, v6, v14
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v10
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v11
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v12
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v8
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, 0xffffff00, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_or_v16i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -878,13 +1043,22 @@ define i16 @test_vector_reduce_or_v2i16(<2 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_or_b32_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_or_v2i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_alignbit_b32 v1, s0, v0, 16
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_or_v2i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_or_v2i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_alignbit_b32 v1, s0, v0, 16
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_or_v2i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -894,17 +1068,30 @@ define i16 @test_vector_reduce_or_v2i16(<2 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_or_v2i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_alignbit_b32 v1, s0, v0, 16
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_or_v2i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_or_v2i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_alignbit_b32 v1, s0, v0, 16
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_or_v2i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -963,25 +1150,67 @@ define i16 @test_vector_reduce_or_v3i16(<3 x i16> %v) {
 ; GFX10-NEXT:    v_or3_b32 v0, v0, v2, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_or_v3i16:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_or3_b32 v0, v0, v2, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_or_v3i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.h, 0
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_or3_b32 v0, v0, v2, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_or_v3i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_or3_b32 v0, v0, v2, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: test_vector_reduce_or_v3i16:
+; GFX11-GISEL:       ; %bb.0: ; %entry
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_or3_b32 v0, v0, v2, v1
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: test_vector_reduce_or_v3i16:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_or3_b32 v0, v0, v2, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_or_v3i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.h, 0
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_or3_b32 v0, v0, v2, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_or_v3i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_or3_b32 v0, v0, v2, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: test_vector_reduce_or_v3i16:
+; GFX12-GISEL:       ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT:    v_or3_b32 v0, v0, v2, v1
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call i16 @llvm.vector.reduce.or.v3i16(<3 x i16> %v)
   ret i16 %res
@@ -1043,27 +1272,73 @@ define i16 @test_vector_reduce_or_v4i16(<4 x i16> %v) {
 ; GFX10-NEXT:    v_or_b32_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_or_v4i16:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_or_v4i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, 0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_or_v4i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: test_vector_reduce_or_v4i16:
+; GFX11-GISEL:       ; %bb.0: ; %entry
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-GISEL-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: test_vector_reduce_or_v4i16:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_or_v4i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, 0
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_or_v4i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: test_vector_reduce_or_v4i16:
+; GFX12-GISEL:       ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-GISEL-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> %v)
   ret i16 %res
@@ -1157,16 +1432,28 @@ define i16 @test_vector_reduce_or_v8i16(<8 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_or_b32_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_or_v8i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v1, v1, v3
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_or3_b32 v0, v0, v2, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_or_v8i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_or3_b32 v0, v0, v2, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, 0
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_or_v8i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_or3_b32 v0, v0, v2, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_or_v8i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1180,20 +1467,36 @@ define i16 @test_vector_reduce_or_v8i16(<8 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_or_v8i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v1, v1, v3
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_or3_b32 v0, v0, v2, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_or_v8i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_or3_b32 v0, v0, v2, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, 0
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_or_v8i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_or3_b32 v0, v0, v2, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_or_v8i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1349,19 +1652,34 @@ define i16 @test_vector_reduce_or_v16i16(<16 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_or_b32_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_or_v16i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v3, v3, v7
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v2, v2, v6
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v4
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_or3_b32 v1, v1, v5, v3
-; GFX11-SDAG-NEXT:    v_or3_b32 v0, v0, v2, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_or_v16i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v3, v3, v7
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v2, v2, v6
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v4
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_or3_b32 v1, v1, v5, v3
+; GFX11-SDAG-TRUE16-NEXT:    v_or3_b32 v0, v0, v2, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, 0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_or_v16i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_or3_b32 v1, v1, v5, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_or3_b32 v0, v0, v2, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_or_v16i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1380,23 +1698,42 @@ define i16 @test_vector_reduce_or_v16i16(<16 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_or_v16i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v3, v3, v7
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v2, v2, v6
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, v0, v4
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_or3_b32 v1, v1, v5, v3
-; GFX12-SDAG-NEXT:    v_or3_b32 v0, v0, v2, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_or_v16i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b32_e32 v3, v3, v7
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b32_e32 v2, v2, v6
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v4
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_or3_b32 v1, v1, v5, v3
+; GFX12-SDAG-TRUE16-NEXT:    v_or3_b32 v0, v0, v2, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, 0
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_or_v16i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v2, v2, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_or3_b32 v1, v1, v5, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_or3_b32 v0, v0, v2, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_or_v16i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -2826,3 +3163,6 @@ declare i64 @llvm.vector.reduce.or.v3i64(<3 x i64>)
 declare i64 @llvm.vector.reduce.or.v4i64(<4 x i64>)
 declare i64 @llvm.vector.reduce.or.v8i64(<8 x i64>)
 declare i64 @llvm.vector.reduce.or.v16i64(<16 x i64>)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11-GISEL-FAKE16: {{.*}}
+; GFX12-GISEL-FAKE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
index 05d826872da34..c7f9ec8632998 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
@@ -7,10 +7,15 @@
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
+; FIXME-TRUE16. enable gisel
+; XUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
+; XUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
 
 define i8 @test_vector_reduce_smax_v2i8(<2 x i8> %v) {
 ; GFX7-SDAG-LABEL: test_vector_reduce_smax_v2i8:
@@ -65,14 +70,23 @@ define i8 @test_vector_reduce_smax_v2i8(<2 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_max_i16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_smax_v2i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_max_i16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v2i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_max_i16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v2i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_smax_v2i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -83,18 +97,31 @@ define i8 @test_vector_reduce_smax_v2i8(<2 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_max_i16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_smax_v2i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_max_i16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v2i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_max_i16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v2i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_max_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_smax_v2i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -189,16 +216,27 @@ define i8 @test_vector_reduce_smax_v3i8(<3 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_max_i16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_smax_v3i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_bfe_i32 v2, v2, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_max_i16 v0, v0, v2
-; GFX11-SDAG-NEXT:    v_max3_i16 v0, v1, v0, 0xff80
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v3i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_max_i16 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    v_max3_i16 v0.l, v1.l, v0.l, 0xff80
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v3i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_i16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_max3_i16 v0, v1, v0, 0xff80
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_smax_v3i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -211,20 +249,35 @@ define i8 @test_vector_reduce_smax_v3i8(<3 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_max_i16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_smax_v3i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_bfe_i32 v2, v2, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_max_i16 v0, v0, v2
-; GFX12-SDAG-NEXT:    v_max3_i16 v0, v1, v0, 0xff80
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v3i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_max_i16 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    v_max3_i16 v0.l, v1.l, v0.l, 0xff80
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v3i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_max_i16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_max3_i16 v0, v1, v0, 0xff80
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_smax_v3i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -395,22 +448,41 @@ define i8 @test_vector_reduce_smax_v4i8(<4 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_or3_b32 v0, v0, v1, v2
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_smax_v4i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_bfe_i32 v3, v3, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v2, v2, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_max_i16 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX11-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_max3_i16 v0, v0, v2, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v4i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v3, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_max_i16 v1.l, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v1, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_max3_i16 v0.l, v0.l, v1.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v4i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v3, v3, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_i16 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_max3_i16 v0, v0, v2, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_smax_v4i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -446,26 +518,49 @@ define i8 @test_vector_reduce_smax_v4i8(<4 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_or3_b32 v0, v0, v1, v2
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_smax_v4i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_bfe_i32 v3, v3, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v2, v2, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_max_i16 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX12-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_max3_i16 v0, v0, v2, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v4i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v3, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_max_i16 v1.l, v1.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v1, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_max3_i16 v0.l, v0.l, v1.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v4i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v3, v3, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_max_i16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_max3_i16 v0, v0, v2, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_smax_v4i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -709,30 +804,66 @@ define i8 @test_vector_reduce_smax_v8i8(<8 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_or3_b32 v0, v0, v1, v2
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_smax_v8i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_bfe_i32 v7, v7, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v3, v3, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v5, v5, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v2, v2, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v4, v4, 0, 8
-; GFX11-SDAG-NEXT:    v_max_i16 v3, v3, v7
-; GFX11-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_max3_i16 v1, v1, v5, v3
-; GFX11-SDAG-NEXT:    v_bfe_i32 v3, v6, 0, 8
-; GFX11-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_max_i16 v2, v2, v3
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_max3_i16 v0, v0, v4, v2
-; GFX11-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_max_i16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v8i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v3, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v7, v7, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v8, v1, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v4, v4, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v7, v5, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v8.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-SDAG-TRUE16-NEXT:    v_max_i16 v1.l, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_max3_i16 v1.l, v5.l, v3.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v6, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v0, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_max_i16 v0.l, v1.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v5, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_max3_i16 v0.l, v1.l, v2.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_max_i16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v8i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v7, v7, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v3, v3, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v5, v5, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v4, v4, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_max_i16 v3, v3, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max3_i16 v1, v1, v5, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v3, v6, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_i16 v2, v2, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max3_i16 v0, v0, v4, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_smax_v8i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -776,34 +907,74 @@ define i8 @test_vector_reduce_smax_v8i8(<8 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_or3_b32 v0, v0, v1, v2
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_smax_v8i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_bfe_i32 v7, v7, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v3, v3, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v5, v5, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v2, v2, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v4, v4, 0, 8
-; GFX12-SDAG-NEXT:    v_max_i16 v3, v3, v7
-; GFX12-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_max3_i16 v1, v1, v5, v3
-; GFX12-SDAG-NEXT:    v_bfe_i32 v3, v6, 0, 8
-; GFX12-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_max_i16 v2, v2, v3
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_max3_i16 v0, v0, v4, v2
-; GFX12-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_max_i16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v8i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v3, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v7, v7, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v8, v1, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v4, v4, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v7.l
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v7, v5, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v8.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-SDAG-TRUE16-NEXT:    v_max_i16 v1.l, v1.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v7.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_max3_i16 v1.l, v5.l, v3.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v6, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX12-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v0, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_max_i16 v0.l, v1.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v4.l
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v5, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_max3_i16 v0.l, v1.l, v2.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_max_i16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v8i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v7, v7, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v3, v3, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v5, v5, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v4, v4, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_max_i16 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_max3_i16 v1, v1, v5, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v3, v6, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_max_i16 v2, v2, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_max3_i16 v0, v0, v4, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_max_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_smax_v8i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1153,44 +1324,97 @@ define i8 @test_vector_reduce_smax_v16i8(<16 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_or3_b32 v0, v0, v1, v2
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_smax_v16i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_bfe_i32 v15, v15, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v7, v7, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v11, v11, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v3, v3, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v9, v9, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v13, v13, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v5, v5, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX11-SDAG-NEXT:    v_max_i16 v7, v7, v15
-; GFX11-SDAG-NEXT:    v_bfe_i32 v6, v6, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v10, v10, 0, 8
-; GFX11-SDAG-NEXT:    v_max_i16 v5, v5, v13
-; GFX11-SDAG-NEXT:    v_max_i16 v1, v1, v9
-; GFX11-SDAG-NEXT:    v_max3_i16 v3, v3, v11, v7
-; GFX11-SDAG-NEXT:    v_bfe_i32 v7, v14, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v2, v2, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v8, v8, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v4, v4, 0, 8
-; GFX11-SDAG-NEXT:    v_max3_i16 v1, v1, v5, v3
-; GFX11-SDAG-NEXT:    v_bfe_i32 v3, v12, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX11-SDAG-NEXT:    v_max_i16 v5, v6, v7
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-SDAG-NEXT:    v_max_i16 v3, v4, v3
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-NEXT:    v_max_i16 v0, v0, v8
-; GFX11-SDAG-NEXT:    v_max3_i16 v2, v2, v10, v5
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX11-SDAG-NEXT:    v_max3_i16 v0, v0, v3, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX11-SDAG-NEXT:    v_max_i16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v16i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v7, v7, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v16, v11, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v17, v3, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v15, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v11, v9, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v9, v13, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v13, v1, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v5, v5, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v4, v4, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v9.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v13.l
+; GFX11-SDAG-TRUE16-NEXT:    v_max_i16 v1.l, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v17.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v16.l
+; GFX11-SDAG-TRUE16-NEXT:    v_max_i16 v1.h, v5.l, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    v_max_i16 v3.h, v9.l, v11.l
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v5, v6, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v6, v8, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_max3_i16 v1.l, v3.l, v13.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v8, v0, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v10, v10, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v7, v2, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v2, v14, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_max3_i16 v1.l, v3.h, v1.h, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v8.l
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v12, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v9.l, 8, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v5.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v6.l
+; GFX11-SDAG-TRUE16-NEXT:    v_max_i16 v0.l, v0.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v8, 8, v9
+; GFX11-SDAG-TRUE16-NEXT:    v_max_i16 v0.h, v1.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v10.l
+; GFX11-SDAG-TRUE16-NEXT:    v_max_i16 v1.h, v4.l, v5.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v8.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_max3_i16 v0.h, v1.l, v2.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v2, v6, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_max3_i16 v0.l, v1.h, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_max_i16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v16i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v15, v15, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v7, v7, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v11, v11, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v3, v3, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v9, v9, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v13, v13, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v5, v5, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_max_i16 v7, v7, v15
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v6, v6, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v10, v10, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_max_i16 v5, v5, v13
+; GFX11-SDAG-FAKE16-NEXT:    v_max_i16 v1, v1, v9
+; GFX11-SDAG-FAKE16-NEXT:    v_max3_i16 v3, v3, v11, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v7, v14, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v8, v8, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v4, v4, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_max3_i16 v1, v1, v5, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v3, v12, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_max_i16 v5, v6, v7
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_max_i16 v3, v4, v3
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_i16 v0, v0, v8
+; GFX11-SDAG-FAKE16-NEXT:    v_max3_i16 v2, v2, v10, v5
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_max3_i16 v0, v0, v3, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_max_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_smax_v16i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1249,48 +1473,105 @@ define i8 @test_vector_reduce_smax_v16i8(<16 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_or3_b32 v0, v0, v1, v2
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_smax_v16i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_bfe_i32 v15, v15, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v7, v7, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v11, v11, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v3, v3, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v9, v9, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v13, v13, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v5, v5, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX12-SDAG-NEXT:    v_max_i16 v7, v7, v15
-; GFX12-SDAG-NEXT:    v_bfe_i32 v6, v6, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v10, v10, 0, 8
-; GFX12-SDAG-NEXT:    v_max_i16 v5, v5, v13
-; GFX12-SDAG-NEXT:    v_max_i16 v1, v1, v9
-; GFX12-SDAG-NEXT:    v_max3_i16 v3, v3, v11, v7
-; GFX12-SDAG-NEXT:    v_bfe_i32 v7, v14, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v2, v2, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v8, v8, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v4, v4, 0, 8
-; GFX12-SDAG-NEXT:    v_max3_i16 v1, v1, v5, v3
-; GFX12-SDAG-NEXT:    v_bfe_i32 v3, v12, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX12-SDAG-NEXT:    v_max_i16 v5, v6, v7
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX12-SDAG-NEXT:    v_max_i16 v3, v4, v3
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-SDAG-NEXT:    v_max_i16 v0, v0, v8
-; GFX12-SDAG-NEXT:    v_max3_i16 v2, v2, v10, v5
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX12-SDAG-NEXT:    v_max3_i16 v0, v0, v3, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX12-SDAG-NEXT:    v_max_i16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v16i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v7, v7, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v16, v11, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v17, v3, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v15, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v11, v9, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v9, v13, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v13, v1, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v7.l
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v5, v5, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v4, v4, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v9.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v13.l
+; GFX12-SDAG-TRUE16-NEXT:    v_max_i16 v1.l, v1.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v17.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v16.l
+; GFX12-SDAG-TRUE16-NEXT:    v_max_i16 v1.h, v5.l, v7.l
+; GFX12-SDAG-TRUE16-NEXT:    v_max_i16 v3.h, v9.l, v11.l
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v5, v6, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v6, v8, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_max3_i16 v1.l, v3.l, v13.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v8, v0, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v10, v10, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v7, v2, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v2, v14, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_max3_i16 v1.l, v3.h, v1.h, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v4.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v8.l
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v12, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX12-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v9.l, 8, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v5.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v6.l
+; GFX12-SDAG-TRUE16-NEXT:    v_max_i16 v0.l, v0.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v8, 8, v9
+; GFX12-SDAG-TRUE16-NEXT:    v_max_i16 v0.h, v1.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v7.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v10.l
+; GFX12-SDAG-TRUE16-NEXT:    v_max_i16 v1.h, v4.l, v5.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v8.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_max3_i16 v0.h, v1.l, v2.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v2, v6, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_max3_i16 v0.l, v1.h, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_max_i16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v16i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v15, v15, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v7, v7, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v11, v11, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v3, v3, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v9, v9, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v13, v13, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v5, v5, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_max_i16 v7, v7, v15
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v6, v6, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v10, v10, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_max_i16 v5, v5, v13
+; GFX12-SDAG-FAKE16-NEXT:    v_max_i16 v1, v1, v9
+; GFX12-SDAG-FAKE16-NEXT:    v_max3_i16 v3, v3, v11, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v7, v14, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v8, v8, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v4, v4, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_max3_i16 v1, v1, v5, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v3, v12, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_max_i16 v5, v6, v7
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_max_i16 v3, v4, v3
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-SDAG-FAKE16-NEXT:    v_max_i16 v0, v0, v8
+; GFX12-SDAG-FAKE16-NEXT:    v_max3_i16 v2, v2, v10, v5
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_max3_i16 v0, v0, v3, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_max_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_smax_v16i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1421,13 +1702,19 @@ define i16 @test_vector_reduce_smax_v2i16(<2 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_pk_max_i16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_smax_v2i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_max_i16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v2i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_max_i16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v2i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_smax_v2i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1437,17 +1724,27 @@ define i16 @test_vector_reduce_smax_v2i16(<2 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_pk_max_i16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_smax_v2i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_max_i16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v2i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_max_i16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v2i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_max_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_smax_v2i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1532,17 +1829,26 @@ define i16 @test_vector_reduce_smax_v3i16(<3 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_max_i16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_smax_v3i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    s_movk_i32 s0, 0x8000
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_perm_b32 v1, s0, v1, 0x5040100
-; GFX11-SDAG-NEXT:    v_pk_max_i16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    v_max_i16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v3i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, 0x8000
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_i16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_max_i16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v3i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_movk_i32 s0, 0x8000
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_perm_b32 v1, s0, v1, 0x5040100
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_max_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_smax_v3i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1553,22 +1859,35 @@ define i16 @test_vector_reduce_smax_v3i16(<3 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_max_i16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_smax_v3i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    s_movk_i32 s0, 0x8000
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffe
-; GFX12-SDAG-NEXT:    v_perm_b32 v1, s0, v1, 0x5040100
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_max_i16 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_max_i16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v3i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, 0x8000
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_i16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_max_i16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v3i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_movk_i32 s0, 0x8000
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX12-SDAG-FAKE16-NEXT:    v_perm_b32 v1, s0, v1, 0x5040100
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_max_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_smax_v3i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1668,14 +1987,22 @@ define i16 @test_vector_reduce_smax_v4i16(<4 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_pk_max_i16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_smax_v4i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_pk_max_i16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    v_max_i16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v4i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_i16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_max_i16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v4i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_max_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_smax_v4i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1686,18 +2013,30 @@ define i16 @test_vector_reduce_smax_v4i16(<4 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_pk_max_i16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_smax_v4i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_pk_max_i16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    v_max_i16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v4i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_i16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_max_i16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v4i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_max_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_smax_v4i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1830,17 +2169,27 @@ define i16 @test_vector_reduce_smax_v8i16(<8 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_pk_max_i16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_smax_v8i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_pk_max_i16 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_pk_max_i16 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_pk_max_i16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_max_i16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v8i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_i16 v1, v1, v3
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_i16 v0, v0, v2
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_i16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_max_i16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v8i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_i16 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_i16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_smax_v8i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1854,21 +2203,35 @@ define i16 @test_vector_reduce_smax_v8i16(<8 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_pk_max_i16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_smax_v8i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_pk_max_i16 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_pk_max_i16 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_max_i16 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_max_i16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v8i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_i16 v1, v1, v3
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_i16 v0, v0, v2
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_i16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_max_i16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v8i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_i16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_i16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_max_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_smax_v8i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -2066,22 +2429,37 @@ define i16 @test_vector_reduce_smax_v16i16(<16 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_pk_max_i16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_smax_v16i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_pk_max_i16 v2, v2, v6
-; GFX11-SDAG-NEXT:    v_pk_max_i16 v3, v3, v7
-; GFX11-SDAG-NEXT:    v_pk_max_i16 v1, v1, v5
-; GFX11-SDAG-NEXT:    v_pk_max_i16 v0, v0, v4
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_pk_max_i16 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_pk_max_i16 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_pk_max_i16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_max_i16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v16i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_i16 v2, v2, v6
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_i16 v3, v3, v7
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_i16 v1, v1, v5
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_i16 v0, v0, v4
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_i16 v1, v1, v3
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_i16 v0, v0, v2
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_i16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_max_i16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v16i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_i16 v2, v2, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_i16 v3, v3, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_i16 v1, v1, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_i16 v0, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_i16 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_i16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_smax_v16i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -2100,26 +2478,45 @@ define i16 @test_vector_reduce_smax_v16i16(<16 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_pk_max_i16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_smax_v16i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_pk_max_i16 v2, v2, v6
-; GFX12-SDAG-NEXT:    v_pk_max_i16 v3, v3, v7
-; GFX12-SDAG-NEXT:    v_pk_max_i16 v1, v1, v5
-; GFX12-SDAG-NEXT:    v_pk_max_i16 v0, v0, v4
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_pk_max_i16 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_pk_max_i16 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_max_i16 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_max_i16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v16i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_i16 v2, v2, v6
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_i16 v3, v3, v7
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_i16 v1, v1, v5
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_i16 v0, v0, v4
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_i16 v1, v1, v3
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_i16 v0, v0, v2
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_i16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_max_i16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v16i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_i16 v2, v2, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_i16 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_i16 v1, v1, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_i16 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_i16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_i16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_max_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_smax_v16i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -4211,3 +4608,6 @@ declare i64 @llvm.vector.reduce.smax.v3i64(<3 x i64>)
 declare i64 @llvm.vector.reduce.smax.v4i64(<4 x i64>)
 declare i64 @llvm.vector.reduce.smax.v8i64(<8 x i64>)
 declare i64 @llvm.vector.reduce.smax.v16i64(<16 x i64>)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11-GISEL-FAKE16: {{.*}}
+; GFX12-GISEL-FAKE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
index db92e3b401340..f7ad431cae1e3 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
@@ -7,10 +7,15 @@
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
+; FIXME-TRUE16. enable gisel
+; XUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
+; XUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
 
 define i8 @test_vector_reduce_smin_v2i8(<2 x i8> %v) {
 ; GFX7-SDAG-LABEL: test_vector_reduce_smin_v2i8:
@@ -65,14 +70,23 @@ define i8 @test_vector_reduce_smin_v2i8(<2 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_min_i16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_smin_v2i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_min_i16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v2i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_min_i16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v2i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_smin_v2i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -83,18 +97,31 @@ define i8 @test_vector_reduce_smin_v2i8(<2 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_min_i16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_smin_v2i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_min_i16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v2i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_min_i16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v2i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_min_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_smin_v2i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -189,16 +216,27 @@ define i8 @test_vector_reduce_smin_v3i8(<3 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_min_i16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_smin_v3i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_bfe_i32 v2, v2, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_min_i16 v0, v0, v2
-; GFX11-SDAG-NEXT:    v_min3_i16 v0, v1, v0, 0x7f
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v3i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_min_i16 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    v_min3_i16 v0.l, v1.l, v0.l, 0x7f
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v3i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_i16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_min3_i16 v0, v1, v0, 0x7f
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_smin_v3i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -211,20 +249,35 @@ define i8 @test_vector_reduce_smin_v3i8(<3 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_min_i16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_smin_v3i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_bfe_i32 v2, v2, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_min_i16 v0, v0, v2
-; GFX12-SDAG-NEXT:    v_min3_i16 v0, v1, v0, 0x7f
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v3i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_min_i16 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    v_min3_i16 v0.l, v1.l, v0.l, 0x7f
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v3i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_min_i16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_min3_i16 v0, v1, v0, 0x7f
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_smin_v3i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -395,22 +448,41 @@ define i8 @test_vector_reduce_smin_v4i8(<4 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_or3_b32 v0, v0, v1, v2
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_smin_v4i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_bfe_i32 v3, v3, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v2, v2, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_min_i16 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX11-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_min3_i16 v0, v0, v2, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v4i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v3, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_min_i16 v1.l, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v1, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_min3_i16 v0.l, v0.l, v1.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v4i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v3, v3, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_i16 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_min3_i16 v0, v0, v2, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_smin_v4i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -446,26 +518,49 @@ define i8 @test_vector_reduce_smin_v4i8(<4 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_or3_b32 v0, v0, v1, v2
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_smin_v4i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_bfe_i32 v3, v3, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v2, v2, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_min_i16 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX12-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_min3_i16 v0, v0, v2, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v4i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v3, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_min_i16 v1.l, v1.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v1, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_min3_i16 v0.l, v0.l, v1.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v4i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v3, v3, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_min_i16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_min3_i16 v0, v0, v2, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_smin_v4i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -709,30 +804,66 @@ define i8 @test_vector_reduce_smin_v8i8(<8 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_or3_b32 v0, v0, v1, v2
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_smin_v8i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_bfe_i32 v7, v7, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v3, v3, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v5, v5, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v2, v2, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v4, v4, 0, 8
-; GFX11-SDAG-NEXT:    v_min_i16 v3, v3, v7
-; GFX11-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_min3_i16 v1, v1, v5, v3
-; GFX11-SDAG-NEXT:    v_bfe_i32 v3, v6, 0, 8
-; GFX11-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_min_i16 v2, v2, v3
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_min3_i16 v0, v0, v4, v2
-; GFX11-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_min_i16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v8i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v3, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v7, v7, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v8, v1, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v4, v4, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v7, v5, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v8.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-SDAG-TRUE16-NEXT:    v_min_i16 v1.l, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_min3_i16 v1.l, v5.l, v3.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v6, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v0, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_min_i16 v0.l, v1.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v5, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_min3_i16 v0.l, v1.l, v2.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_min_i16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v8i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v7, v7, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v3, v3, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v5, v5, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v4, v4, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_min_i16 v3, v3, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min3_i16 v1, v1, v5, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v3, v6, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_i16 v2, v2, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min3_i16 v0, v0, v4, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_smin_v8i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -776,34 +907,74 @@ define i8 @test_vector_reduce_smin_v8i8(<8 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_or3_b32 v0, v0, v1, v2
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_smin_v8i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_bfe_i32 v7, v7, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v3, v3, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v5, v5, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v2, v2, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v4, v4, 0, 8
-; GFX12-SDAG-NEXT:    v_min_i16 v3, v3, v7
-; GFX12-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_min3_i16 v1, v1, v5, v3
-; GFX12-SDAG-NEXT:    v_bfe_i32 v3, v6, 0, 8
-; GFX12-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_min_i16 v2, v2, v3
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_min3_i16 v0, v0, v4, v2
-; GFX12-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_min_i16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v8i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v3, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v7, v7, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v8, v1, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v4, v4, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v7.l
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v7, v5, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v8.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-SDAG-TRUE16-NEXT:    v_min_i16 v1.l, v1.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v7.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_min3_i16 v1.l, v5.l, v3.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v6, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX12-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v0, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_min_i16 v0.l, v1.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v4.l
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v5, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_min3_i16 v0.l, v1.l, v2.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_min_i16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v8i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v7, v7, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v3, v3, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v5, v5, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v4, v4, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_min_i16 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_min3_i16 v1, v1, v5, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v3, v6, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_min_i16 v2, v2, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_min3_i16 v0, v0, v4, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_min_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_smin_v8i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1153,44 +1324,97 @@ define i8 @test_vector_reduce_smin_v16i8(<16 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_or3_b32 v0, v0, v1, v2
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_smin_v16i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_bfe_i32 v15, v15, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v7, v7, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v11, v11, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v3, v3, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v9, v9, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v13, v13, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v5, v5, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX11-SDAG-NEXT:    v_min_i16 v7, v7, v15
-; GFX11-SDAG-NEXT:    v_bfe_i32 v6, v6, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v10, v10, 0, 8
-; GFX11-SDAG-NEXT:    v_min_i16 v5, v5, v13
-; GFX11-SDAG-NEXT:    v_min_i16 v1, v1, v9
-; GFX11-SDAG-NEXT:    v_min3_i16 v3, v3, v11, v7
-; GFX11-SDAG-NEXT:    v_bfe_i32 v7, v14, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v2, v2, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v8, v8, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v4, v4, 0, 8
-; GFX11-SDAG-NEXT:    v_min3_i16 v1, v1, v5, v3
-; GFX11-SDAG-NEXT:    v_bfe_i32 v3, v12, 0, 8
-; GFX11-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX11-SDAG-NEXT:    v_min_i16 v5, v6, v7
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-SDAG-NEXT:    v_min_i16 v3, v4, v3
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-NEXT:    v_min_i16 v0, v0, v8
-; GFX11-SDAG-NEXT:    v_min3_i16 v2, v2, v10, v5
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX11-SDAG-NEXT:    v_min3_i16 v0, v0, v3, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX11-SDAG-NEXT:    v_min_i16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v16i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v7, v7, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v16, v11, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v17, v3, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v15, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v11, v9, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v9, v13, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v13, v1, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v5, v5, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v4, v4, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v9.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v13.l
+; GFX11-SDAG-TRUE16-NEXT:    v_min_i16 v1.l, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v17.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v16.l
+; GFX11-SDAG-TRUE16-NEXT:    v_min_i16 v1.h, v5.l, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    v_min_i16 v3.h, v9.l, v11.l
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v5, v6, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v6, v8, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_min3_i16 v1.l, v3.l, v13.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v8, v0, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v10, v10, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v7, v2, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v2, v14, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    v_min3_i16 v1.l, v3.h, v1.h, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v8.l
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v12, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v9.l, 8, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v5.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v6.l
+; GFX11-SDAG-TRUE16-NEXT:    v_min_i16 v0.l, v0.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v8, 8, v9
+; GFX11-SDAG-TRUE16-NEXT:    v_min_i16 v0.h, v1.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v10.l
+; GFX11-SDAG-TRUE16-NEXT:    v_min_i16 v1.h, v4.l, v5.l
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v8.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_min3_i16 v0.h, v1.l, v2.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_bfe_i32 v2, v6, 0, 8
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_min3_i16 v0.l, v1.h, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_min_i16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v16i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v15, v15, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v7, v7, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v11, v11, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v3, v3, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v9, v9, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v13, v13, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v5, v5, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_min_i16 v7, v7, v15
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v6, v6, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v10, v10, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_min_i16 v5, v5, v13
+; GFX11-SDAG-FAKE16-NEXT:    v_min_i16 v1, v1, v9
+; GFX11-SDAG-FAKE16-NEXT:    v_min3_i16 v3, v3, v11, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v7, v14, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v8, v8, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v4, v4, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_min3_i16 v1, v1, v5, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v3, v12, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_min_i16 v5, v6, v7
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_min_i16 v3, v4, v3
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_i16 v0, v0, v8
+; GFX11-SDAG-FAKE16-NEXT:    v_min3_i16 v2, v2, v10, v5
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_min3_i16 v0, v0, v3, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-FAKE16-NEXT:    v_min_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_smin_v16i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1249,48 +1473,105 @@ define i8 @test_vector_reduce_smin_v16i8(<16 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_or3_b32 v0, v0, v1, v2
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_smin_v16i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_bfe_i32 v15, v15, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v7, v7, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v11, v11, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v3, v3, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v9, v9, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v13, v13, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v5, v5, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX12-SDAG-NEXT:    v_min_i16 v7, v7, v15
-; GFX12-SDAG-NEXT:    v_bfe_i32 v6, v6, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v10, v10, 0, 8
-; GFX12-SDAG-NEXT:    v_min_i16 v5, v5, v13
-; GFX12-SDAG-NEXT:    v_min_i16 v1, v1, v9
-; GFX12-SDAG-NEXT:    v_min3_i16 v3, v3, v11, v7
-; GFX12-SDAG-NEXT:    v_bfe_i32 v7, v14, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v2, v2, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v8, v8, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v4, v4, 0, 8
-; GFX12-SDAG-NEXT:    v_min3_i16 v1, v1, v5, v3
-; GFX12-SDAG-NEXT:    v_bfe_i32 v3, v12, 0, 8
-; GFX12-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX12-SDAG-NEXT:    v_min_i16 v5, v6, v7
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX12-SDAG-NEXT:    v_min_i16 v3, v4, v3
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-SDAG-NEXT:    v_min_i16 v0, v0, v8
-; GFX12-SDAG-NEXT:    v_min3_i16 v2, v2, v10, v5
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX12-SDAG-NEXT:    v_min3_i16 v0, v0, v3, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX12-SDAG-NEXT:    v_min_i16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v16i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v7, v7, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v16, v11, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v17, v3, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v15, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v11, v9, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v9, v13, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v13, v1, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v7.l
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v5, v5, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v4, v4, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v9.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v13.l
+; GFX12-SDAG-TRUE16-NEXT:    v_min_i16 v1.l, v1.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v17.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v16.l
+; GFX12-SDAG-TRUE16-NEXT:    v_min_i16 v1.h, v5.l, v7.l
+; GFX12-SDAG-TRUE16-NEXT:    v_min_i16 v3.h, v9.l, v11.l
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v5, v6, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v6, v8, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_min3_i16 v1.l, v3.l, v13.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v8, v0, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v10, v10, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v7, v2, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v2, v14, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    v_min3_i16 v1.l, v3.h, v1.h, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v4.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v8.l
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v3, v12, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX12-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v9.l, 8, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v5.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v6.l
+; GFX12-SDAG-TRUE16-NEXT:    v_min_i16 v0.l, v0.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v8, 8, v9
+; GFX12-SDAG-TRUE16-NEXT:    v_min_i16 v0.h, v1.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v7.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v10.l
+; GFX12-SDAG-TRUE16-NEXT:    v_min_i16 v1.h, v4.l, v5.l
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v8.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_min3_i16 v0.h, v1.l, v2.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_bfe_i32 v2, v6, 0, 8
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_min3_i16 v0.l, v1.h, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_min_i16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v16i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v15, v15, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v7, v7, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v11, v11, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v3, v3, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v9, v9, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v13, v13, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v5, v5, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_min_i16 v7, v7, v15
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v6, v6, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v10, v10, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_min_i16 v5, v5, v13
+; GFX12-SDAG-FAKE16-NEXT:    v_min_i16 v1, v1, v9
+; GFX12-SDAG-FAKE16-NEXT:    v_min3_i16 v3, v3, v11, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v7, v14, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v8, v8, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v4, v4, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_min3_i16 v1, v1, v5, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v3, v12, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_min_i16 v5, v6, v7
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_min_i16 v3, v4, v3
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-SDAG-FAKE16-NEXT:    v_min_i16 v0, v0, v8
+; GFX12-SDAG-FAKE16-NEXT:    v_min3_i16 v2, v2, v10, v5
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_min3_i16 v0, v0, v3, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-FAKE16-NEXT:    v_min_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_smin_v16i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1421,13 +1702,19 @@ define i16 @test_vector_reduce_smin_v2i16(<2 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_pk_min_i16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_smin_v2i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_min_i16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v2i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_min_i16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v2i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_smin_v2i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1437,17 +1724,27 @@ define i16 @test_vector_reduce_smin_v2i16(<2 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_pk_min_i16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_smin_v2i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_min_i16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v2i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_min_i16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v2i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_min_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_smin_v2i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1532,17 +1829,26 @@ define i16 @test_vector_reduce_smin_v3i16(<3 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_min_i16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_smin_v3i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    s_movk_i32 s0, 0x7fff
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_perm_b32 v1, s0, v1, 0x5040100
-; GFX11-SDAG-NEXT:    v_pk_min_i16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    v_min_i16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v3i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_i16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_min_i16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v3i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    s_movk_i32 s0, 0x7fff
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_perm_b32 v1, s0, v1, 0x5040100
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_min_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_smin_v3i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1553,22 +1859,35 @@ define i16 @test_vector_reduce_smin_v3i16(<3 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_min_i16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_smin_v3i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    s_movk_i32 s0, 0x7fff
-; GFX12-SDAG-NEXT:    s_wait_alu 0xfffe
-; GFX12-SDAG-NEXT:    v_perm_b32 v1, s0, v1, 0x5040100
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_min_i16 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_min_i16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v3i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, 0x7fff
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_i16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_min_i16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v3i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_movk_i32 s0, 0x7fff
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX12-SDAG-FAKE16-NEXT:    v_perm_b32 v1, s0, v1, 0x5040100
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_min_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_smin_v3i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1668,14 +1987,22 @@ define i16 @test_vector_reduce_smin_v4i16(<4 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_pk_min_i16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_smin_v4i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_pk_min_i16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    v_min_i16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v4i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_i16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_min_i16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v4i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_min_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_smin_v4i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1686,18 +2013,30 @@ define i16 @test_vector_reduce_smin_v4i16(<4 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_pk_min_i16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_smin_v4i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_pk_min_i16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    v_min_i16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v4i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_i16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_min_i16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v4i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_min_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_smin_v4i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1830,17 +2169,27 @@ define i16 @test_vector_reduce_smin_v8i16(<8 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_pk_min_i16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_smin_v8i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_pk_min_i16 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_pk_min_i16 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_pk_min_i16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_min_i16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v8i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_i16 v1, v1, v3
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_i16 v0, v0, v2
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_i16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_min_i16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v8i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_i16 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_i16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_smin_v8i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1854,21 +2203,35 @@ define i16 @test_vector_reduce_smin_v8i16(<8 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_pk_min_i16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_smin_v8i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_pk_min_i16 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_pk_min_i16 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_min_i16 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_min_i16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v8i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_i16 v1, v1, v3
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_i16 v0, v0, v2
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_i16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_min_i16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v8i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_i16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_i16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_min_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_smin_v8i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -2066,22 +2429,37 @@ define i16 @test_vector_reduce_smin_v16i16(<16 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_pk_min_i16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_smin_v16i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_pk_min_i16 v2, v2, v6
-; GFX11-SDAG-NEXT:    v_pk_min_i16 v3, v3, v7
-; GFX11-SDAG-NEXT:    v_pk_min_i16 v1, v1, v5
-; GFX11-SDAG-NEXT:    v_pk_min_i16 v0, v0, v4
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_pk_min_i16 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_pk_min_i16 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_pk_min_i16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_min_i16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v16i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_i16 v2, v2, v6
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_i16 v3, v3, v7
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_i16 v1, v1, v5
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_i16 v0, v0, v4
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_i16 v1, v1, v3
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_i16 v0, v0, v2
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_i16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_min_i16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v16i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_i16 v2, v2, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_i16 v3, v3, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_i16 v1, v1, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_i16 v0, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_i16 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_i16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_smin_v16i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -2100,26 +2478,45 @@ define i16 @test_vector_reduce_smin_v16i16(<16 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_pk_min_i16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_smin_v16i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_pk_min_i16 v2, v2, v6
-; GFX12-SDAG-NEXT:    v_pk_min_i16 v3, v3, v7
-; GFX12-SDAG-NEXT:    v_pk_min_i16 v1, v1, v5
-; GFX12-SDAG-NEXT:    v_pk_min_i16 v0, v0, v4
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_pk_min_i16 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_pk_min_i16 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_min_i16 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_min_i16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v16i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_i16 v2, v2, v6
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_i16 v3, v3, v7
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_i16 v1, v1, v5
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_i16 v0, v0, v4
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_i16 v1, v1, v3
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_i16 v0, v0, v2
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_i16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_min_i16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v16i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_i16 v2, v2, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_i16 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_i16 v1, v1, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_i16 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_i16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_i16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_min_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_smin_v16i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -4211,3 +4608,6 @@ declare i64 @llvm.vector.reduce.smin.v3i64(<3 x i64>)
 declare i64 @llvm.vector.reduce.smin.v4i64(<4 x i64>)
 declare i64 @llvm.vector.reduce.smin.v8i64(<8 x i64>)
 declare i64 @llvm.vector.reduce.smin.v16i64(<16 x i64>)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11-GISEL-FAKE16: {{.*}}
+; GFX12-GISEL-FAKE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
index 57e24d4e431aa..2eeedd4cfffba 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
@@ -7,10 +7,15 @@
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
+; FIXME-TRUE16. enable gisel
+; XUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
+; XUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
 
 define i8 @test_vector_reduce_umax_v2i8(<2 x i8> %v) {
 ; GFX7-SDAG-LABEL: test_vector_reduce_umax_v2i8:
@@ -57,14 +62,23 @@ define i8 @test_vector_reduce_umax_v2i8(<2 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_max_u16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_umax_v2i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_max_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v2i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_max_u16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v2i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_umax_v2i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -75,18 +89,31 @@ define i8 @test_vector_reduce_umax_v2i8(<2 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_max_u16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_umax_v2i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_max_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v2i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_max_u16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v2i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_max_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_umax_v2i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -174,15 +201,25 @@ define i8 @test_vector_reduce_umax_v3i8(<3 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_max_u16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_umax_v3i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_max3_u16 v0, v1, v0, v2
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v3i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_max3_u16 v0.l, v1.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v3i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_max3_u16 v0, v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_umax_v3i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -195,19 +232,33 @@ define i8 @test_vector_reduce_umax_v3i8(<3 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_max_u16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_umax_v3i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_max3_u16 v0, v1, v0, v2
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v3i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_max3_u16 v0.l, v1.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v3i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_max3_u16 v0, v1, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_umax_v3i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -367,22 +418,39 @@ define i8 @test_vector_reduce_umax_v4i8(<4 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_or3_b32 v0, v0, v1, v2
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_umax_v4i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_max_u16 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_max3_u16 v0, v0, v2, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v4i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_max_u16 v1.l, v1.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_max3_u16 v0.l, v0.l, v0.h, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v4i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_u16 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_max3_u16 v0, v0, v2, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_umax_v4i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -417,26 +485,47 @@ define i8 @test_vector_reduce_umax_v4i8(<4 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_or3_b32 v0, v0, v1, v2
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_umax_v4i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_max_u16 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_max3_u16 v0, v0, v2, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v4i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_max_u16 v1.l, v1.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_max3_u16 v0.l, v0.l, v0.h, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v4i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_max_u16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_max3_u16 v0, v0, v2, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_umax_v4i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -664,30 +753,56 @@ define i8 @test_vector_reduce_umax_v8i8(<8 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_or3_b32 v0, v0, v1, v2
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_umax_v8i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-SDAG-NEXT:    v_max_u16 v3, v3, v7
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_max3_u16 v1, v1, v5, v3
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v3, 0xff, v6
-; GFX11-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_max_u16 v2, v2, v3
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_max3_u16 v0, v0, v4, v2
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_max_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v8i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v5.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v6.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_max_u16 v1.h, v3.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_max3_u16 v1.l, v1.l, v3.h, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_max_u16 v0.h, v1.h, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v4.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-SDAG-TRUE16-NEXT:    v_max3_u16 v0.l, v0.l, v1.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-SDAG-TRUE16-NEXT:    v_max_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v8i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_max_u16 v3, v3, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max3_u16 v1, v1, v5, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_u16 v2, v2, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max3_u16 v0, v0, v4, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_umax_v8i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -730,34 +845,64 @@ define i8 @test_vector_reduce_umax_v8i8(<8 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_or3_b32 v0, v0, v1, v2
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_umax_v8i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX12-SDAG-NEXT:    v_max_u16 v3, v3, v7
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_max3_u16 v1, v1, v5, v3
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v3, 0xff, v6
-; GFX12-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_max_u16 v2, v2, v3
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_max3_u16 v0, v0, v4, v2
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_max_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v8i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v7.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v5.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v6.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    v_max_u16 v1.h, v3.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_max3_u16 v1.l, v1.l, v3.h, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_max_u16 v0.h, v1.h, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v4.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-SDAG-TRUE16-NEXT:    v_max3_u16 v0.l, v0.l, v1.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX12-SDAG-TRUE16-NEXT:    v_max_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v8i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX12-SDAG-FAKE16-NEXT:    v_max_u16 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_max3_u16 v1, v1, v5, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_max_u16 v2, v2, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_max3_u16 v0, v0, v4, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_max_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_umax_v8i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1089,46 +1234,89 @@ define i8 @test_vector_reduce_umax_v16i8(<16 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_or3_b32 v0, v0, v1, v2
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_umax_v16i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-SDAG-NEXT:    v_max_u16 v7, v7, v15
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-SDAG-NEXT:    v_max_u16 v5, v5, v13
-; GFX11-SDAG-NEXT:    v_max_u16 v1, v1, v9
-; GFX11-SDAG-NEXT:    v_max_u16 v6, v6, v14
-; GFX11-SDAG-NEXT:    v_max3_u16 v3, v3, v11, v7
-; GFX11-SDAG-NEXT:    v_max_u16 v4, v4, v12
-; GFX11-SDAG-NEXT:    v_max_u16 v0, v0, v8
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-NEXT:    v_max3_u16 v2, v2, v10, v6
-; GFX11-SDAG-NEXT:    v_max3_u16 v1, v1, v5, v3
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_max3_u16 v0, v0, v4, v2
-; GFX11-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, 0xffff, v0
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX11-SDAG-NEXT:    v_max_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v16i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v10.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v15.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v11.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v14.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v9.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v13.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v5.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_max_u16 v0.h, v0.h, v10.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v8.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v12.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-SDAG-TRUE16-NEXT:    v_max_u16 v4.h, v5.l, v4.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max_u16 v1.l, v1.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max_u16 v1.h, v6.l, v6.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max3_u16 v0.h, v3.l, v3.h, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max_u16 v3.l, v4.l, v5.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max_u16 v0.l, v0.l, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-TRUE16-NEXT:    v_max3_u16 v1.h, v2.l, v2.h, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_max3_u16 v0.h, v1.l, v4.h, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_max3_u16 v0.l, v0.l, v3.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_max_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v16i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_max_u16 v7, v7, v15
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_max_u16 v5, v5, v13
+; GFX11-SDAG-FAKE16-NEXT:    v_max_u16 v1, v1, v9
+; GFX11-SDAG-FAKE16-NEXT:    v_max_u16 v6, v6, v14
+; GFX11-SDAG-FAKE16-NEXT:    v_max3_u16 v3, v3, v11, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_max_u16 v4, v4, v12
+; GFX11-SDAG-FAKE16-NEXT:    v_max_u16 v0, v0, v8
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-FAKE16-NEXT:    v_max3_u16 v2, v2, v10, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_max3_u16 v1, v1, v5, v3
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_max3_u16 v0, v0, v4, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_max_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_umax_v16i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1187,50 +1375,97 @@ define i8 @test_vector_reduce_umax_v16i8(<16 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_or3_b32 v0, v0, v1, v2
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_umax_v16i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX12-SDAG-NEXT:    v_max_u16 v7, v7, v15
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX12-SDAG-NEXT:    v_max_u16 v5, v5, v13
-; GFX12-SDAG-NEXT:    v_max_u16 v1, v1, v9
-; GFX12-SDAG-NEXT:    v_max_u16 v6, v6, v14
-; GFX12-SDAG-NEXT:    v_max3_u16 v3, v3, v11, v7
-; GFX12-SDAG-NEXT:    v_max_u16 v4, v4, v12
-; GFX12-SDAG-NEXT:    v_max_u16 v0, v0, v8
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-SDAG-NEXT:    v_max3_u16 v2, v2, v10, v6
-; GFX12-SDAG-NEXT:    v_max3_u16 v1, v1, v5, v3
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_max3_u16 v0, v0, v4, v2
-; GFX12-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, 0xffff, v0
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX12-SDAG-NEXT:    v_max_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v16i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v10.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v15.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v7.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v11.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v14.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v9.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v13.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v5.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_max_u16 v0.h, v0.h, v10.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v8.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v12.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX12-SDAG-TRUE16-NEXT:    v_max_u16 v4.h, v5.l, v4.h
+; GFX12-SDAG-TRUE16-NEXT:    v_max_u16 v1.l, v1.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_max_u16 v1.h, v6.l, v6.h
+; GFX12-SDAG-TRUE16-NEXT:    v_max3_u16 v0.h, v3.l, v3.h, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_max_u16 v3.l, v4.l, v5.h
+; GFX12-SDAG-TRUE16-NEXT:    v_max_u16 v0.l, v0.l, v7.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-SDAG-TRUE16-NEXT:    v_max3_u16 v1.h, v2.l, v2.h, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_max3_u16 v0.h, v1.l, v4.h, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_max3_u16 v0.l, v0.l, v3.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_max_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v16i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_max_u16 v7, v7, v15
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX12-SDAG-FAKE16-NEXT:    v_max_u16 v5, v5, v13
+; GFX12-SDAG-FAKE16-NEXT:    v_max_u16 v1, v1, v9
+; GFX12-SDAG-FAKE16-NEXT:    v_max_u16 v6, v6, v14
+; GFX12-SDAG-FAKE16-NEXT:    v_max3_u16 v3, v3, v11, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_max_u16 v4, v4, v12
+; GFX12-SDAG-FAKE16-NEXT:    v_max_u16 v0, v0, v8
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-SDAG-FAKE16-NEXT:    v_max3_u16 v2, v2, v10, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_max3_u16 v1, v1, v5, v3
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_max3_u16 v0, v0, v4, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_max_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_umax_v16i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1359,13 +1594,19 @@ define i16 @test_vector_reduce_umax_v2i16(<2 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_pk_max_u16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_umax_v2i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_max_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v2i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_max_u16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v2i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_umax_v2i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1375,17 +1616,27 @@ define i16 @test_vector_reduce_umax_v2i16(<2 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_pk_max_u16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_umax_v2i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_max_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v2i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_max_u16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v2i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_max_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_umax_v2i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1464,16 +1715,25 @@ define i16 @test_vector_reduce_umax_v3i16(<3 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_max_u16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_umax_v3i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_pk_max_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_max_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v3i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_u16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_max_u16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v3i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_umax_v3i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1484,20 +1744,33 @@ define i16 @test_vector_reduce_umax_v3i16(<3 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_max_u16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_umax_v3i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_max_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_max_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v3i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_u16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_max_u16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v3i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_max_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_umax_v3i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1595,14 +1868,22 @@ define i16 @test_vector_reduce_umax_v4i16(<4 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_pk_max_u16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_umax_v4i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_pk_max_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    v_max_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v4i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_u16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_max_u16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v4i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_max_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_umax_v4i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1613,18 +1894,30 @@ define i16 @test_vector_reduce_umax_v4i16(<4 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_pk_max_u16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_umax_v4i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_pk_max_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    v_max_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v4i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_u16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_max_u16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v4i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_max_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_umax_v4i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1755,17 +2048,27 @@ define i16 @test_vector_reduce_umax_v8i16(<8 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_pk_max_u16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_umax_v8i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_pk_max_u16 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_pk_max_u16 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_pk_max_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_max_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v8i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_u16 v1, v1, v3
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_u16 v0, v0, v2
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_u16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_max_u16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v8i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_u16 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_u16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_umax_v8i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1779,21 +2082,35 @@ define i16 @test_vector_reduce_umax_v8i16(<8 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_pk_max_u16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_umax_v8i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_pk_max_u16 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_pk_max_u16 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_max_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_max_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v8i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_u16 v1, v1, v3
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_u16 v0, v0, v2
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_u16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_max_u16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v8i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_u16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_u16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_max_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_umax_v8i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1989,22 +2306,37 @@ define i16 @test_vector_reduce_umax_v16i16(<16 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_pk_max_u16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_umax_v16i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_pk_max_u16 v2, v2, v6
-; GFX11-SDAG-NEXT:    v_pk_max_u16 v3, v3, v7
-; GFX11-SDAG-NEXT:    v_pk_max_u16 v1, v1, v5
-; GFX11-SDAG-NEXT:    v_pk_max_u16 v0, v0, v4
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_pk_max_u16 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_pk_max_u16 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_pk_max_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_max_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v16i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_u16 v2, v2, v6
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_u16 v3, v3, v7
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_u16 v1, v1, v5
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_u16 v0, v0, v4
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_u16 v1, v1, v3
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_u16 v0, v0, v2
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_max_u16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_max_u16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v16i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_u16 v2, v2, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_u16 v3, v3, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_u16 v1, v1, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_u16 v0, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_u16 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_u16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_max_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_max_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_umax_v16i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -2023,26 +2355,45 @@ define i16 @test_vector_reduce_umax_v16i16(<16 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_pk_max_u16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_umax_v16i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_pk_max_u16 v2, v2, v6
-; GFX12-SDAG-NEXT:    v_pk_max_u16 v3, v3, v7
-; GFX12-SDAG-NEXT:    v_pk_max_u16 v1, v1, v5
-; GFX12-SDAG-NEXT:    v_pk_max_u16 v0, v0, v4
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_pk_max_u16 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_pk_max_u16 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_max_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_max_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v16i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_u16 v2, v2, v6
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_u16 v3, v3, v7
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_u16 v1, v1, v5
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_u16 v0, v0, v4
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_u16 v1, v1, v3
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_u16 v0, v0, v2
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_max_u16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_max_u16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v16i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_u16 v2, v2, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_u16 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_u16 v1, v1, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_u16 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_u16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_u16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_max_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_max_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_umax_v16i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -4134,3 +4485,6 @@ declare i64 @llvm.vector.reduce.umax.v3i64(<3 x i64>)
 declare i64 @llvm.vector.reduce.umax.v4i64(<4 x i64>)
 declare i64 @llvm.vector.reduce.umax.v8i64(<8 x i64>)
 declare i64 @llvm.vector.reduce.umax.v16i64(<16 x i64>)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11-GISEL-FAKE16: {{.*}}
+; GFX12-GISEL-FAKE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
index b44ec6a24e49d..6e4a06b3f8f4e 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
@@ -7,10 +7,15 @@
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
+; FIXME-TRUE16. enable gisel
+; XUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
+; XUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
 
 define i8 @test_vector_reduce_umin_v2i8(<2 x i8> %v) {
 ; GFX7-SDAG-LABEL: test_vector_reduce_umin_v2i8:
@@ -57,14 +62,23 @@ define i8 @test_vector_reduce_umin_v2i8(<2 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_min_u16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_umin_v2i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_min_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v2i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_min_u16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v2i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_umin_v2i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -75,18 +89,31 @@ define i8 @test_vector_reduce_umin_v2i8(<2 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_min_u16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_umin_v2i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_min_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v2i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_min_u16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v2i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_min_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_umin_v2i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -174,15 +201,25 @@ define i8 @test_vector_reduce_umin_v3i8(<3 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_min_u16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_umin_v3i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_min3_u16 v0, v1, v0, v2
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v3i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_min3_u16 v0.l, v1.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v3i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_min3_u16 v0, v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_umin_v3i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -195,19 +232,33 @@ define i8 @test_vector_reduce_umin_v3i8(<3 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_min_u16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_umin_v3i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_min3_u16 v0, v1, v0, v2
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v3i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_min3_u16 v0.l, v1.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v3i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_min3_u16 v0, v1, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_umin_v3i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -316,22 +367,39 @@ define i8 @test_vector_reduce_umin_v4i8(<4 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_umin_v4i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_min_u16 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_min3_u16 v0, v0, v2, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v4i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_min_u16 v1.l, v1.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_min3_u16 v0.l, v0.l, v0.h, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v4i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_u16 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_min3_u16 v0, v0, v2, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_umin_v4i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -348,26 +416,47 @@ define i8 @test_vector_reduce_umin_v4i8(<4 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_umin_v4i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_min_u16 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_min3_u16 v0, v0, v2, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v4i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_min_u16 v1.l, v1.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_min3_u16 v0.l, v0.l, v0.h, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v4i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_min_u16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_min3_u16 v0, v0, v2, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_umin_v4i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -528,30 +617,56 @@ define i8 @test_vector_reduce_umin_v8i8(<8 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_umin_v8i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-SDAG-NEXT:    v_min_u16 v3, v3, v7
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_min3_u16 v1, v1, v5, v3
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v3, 0xff, v6
-; GFX11-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_min_u16 v2, v2, v3
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_min3_u16 v0, v0, v4, v2
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_min_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v8i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v5.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v6.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_min_u16 v1.h, v3.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_min3_u16 v1.l, v1.l, v3.h, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_min_u16 v0.h, v1.h, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v4.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX11-SDAG-TRUE16-NEXT:    v_min3_u16 v0.l, v0.l, v1.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-SDAG-TRUE16-NEXT:    v_min_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v8i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_min_u16 v3, v3, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min3_u16 v1, v1, v5, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_u16 v2, v2, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min3_u16 v0, v0, v4, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_umin_v8i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -577,34 +692,64 @@ define i8 @test_vector_reduce_umin_v8i8(<8 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_umin_v8i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX12-SDAG-NEXT:    v_min_u16 v3, v3, v7
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_min3_u16 v1, v1, v5, v3
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v3, 0xff, v6
-; GFX12-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_min_u16 v2, v2, v3
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_min3_u16 v0, v0, v4, v2
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_min_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v8i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v7.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v5.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v6.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    v_min_u16 v1.h, v3.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_min3_u16 v1.l, v1.l, v3.h, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_min_u16 v0.h, v1.h, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v4.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX12-SDAG-TRUE16-NEXT:    v_min3_u16 v0.l, v0.l, v1.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v2
+; GFX12-SDAG-TRUE16-NEXT:    v_min_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v8i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX12-SDAG-FAKE16-NEXT:    v_min_u16 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_min3_u16 v1, v1, v5, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_min_u16 v2, v2, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_min3_u16 v0, v0, v4, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_min_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_umin_v8i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -870,46 +1015,89 @@ define i8 @test_vector_reduce_umin_v16i8(<16 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_umin_v16i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX11-SDAG-NEXT:    v_min_u16 v7, v7, v15
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX11-SDAG-NEXT:    v_min_u16 v5, v5, v13
-; GFX11-SDAG-NEXT:    v_min_u16 v1, v1, v9
-; GFX11-SDAG-NEXT:    v_min_u16 v6, v6, v14
-; GFX11-SDAG-NEXT:    v_min3_u16 v3, v3, v11, v7
-; GFX11-SDAG-NEXT:    v_min_u16 v4, v4, v12
-; GFX11-SDAG-NEXT:    v_min_u16 v0, v0, v8
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-NEXT:    v_min3_u16 v2, v2, v10, v6
-; GFX11-SDAG-NEXT:    v_min3_u16 v1, v1, v5, v3
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_min3_u16 v0, v0, v4, v2
-; GFX11-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v1, 0xffff, v0
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX11-SDAG-NEXT:    v_min_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v16i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v10.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v15.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v11.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v14.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v9.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v13.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v5.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_min_u16 v0.h, v0.h, v10.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v8.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v12.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX11-SDAG-TRUE16-NEXT:    v_min_u16 v4.h, v5.l, v4.h
+; GFX11-SDAG-TRUE16-NEXT:    v_min_u16 v1.l, v1.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_min_u16 v1.h, v6.l, v6.h
+; GFX11-SDAG-TRUE16-NEXT:    v_min3_u16 v0.h, v3.l, v3.h, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_min_u16 v3.l, v4.l, v5.h
+; GFX11-SDAG-TRUE16-NEXT:    v_min_u16 v0.l, v0.l, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-TRUE16-NEXT:    v_min3_u16 v1.h, v2.l, v2.h, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_min3_u16 v0.h, v1.l, v4.h, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_min3_u16 v0.l, v0.l, v3.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_min_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v16i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_min_u16 v7, v7, v15
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_min_u16 v5, v5, v13
+; GFX11-SDAG-FAKE16-NEXT:    v_min_u16 v1, v1, v9
+; GFX11-SDAG-FAKE16-NEXT:    v_min_u16 v6, v6, v14
+; GFX11-SDAG-FAKE16-NEXT:    v_min3_u16 v3, v3, v11, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_min_u16 v4, v4, v12
+; GFX11-SDAG-FAKE16-NEXT:    v_min_u16 v0, v0, v8
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-FAKE16-NEXT:    v_min3_u16 v2, v2, v10, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_min3_u16 v1, v1, v5, v3
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_min3_u16 v0, v0, v4, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_min_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_umin_v16i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -952,50 +1140,97 @@ define i8 @test_vector_reduce_umin_v16i8(<16 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_umin_v16i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v15, 0xff, v15
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v7, 0xff, v7
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v11, 0xff, v11
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v3, 0xff, v3
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v14, 0xff, v14
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v6, 0xff, v6
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v9, 0xff, v9
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v13, 0xff, v13
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v5, 0xff, v5
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX12-SDAG-NEXT:    v_min_u16 v7, v7, v15
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v10, 0xff, v10
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v2, 0xff, v2
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v8, 0xff, v8
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v12, 0xff, v12
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v4, 0xff, v4
-; GFX12-SDAG-NEXT:    v_min_u16 v5, v5, v13
-; GFX12-SDAG-NEXT:    v_min_u16 v1, v1, v9
-; GFX12-SDAG-NEXT:    v_min_u16 v6, v6, v14
-; GFX12-SDAG-NEXT:    v_min3_u16 v3, v3, v11, v7
-; GFX12-SDAG-NEXT:    v_min_u16 v4, v4, v12
-; GFX12-SDAG-NEXT:    v_min_u16 v0, v0, v8
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-SDAG-NEXT:    v_min3_u16 v2, v2, v10, v6
-; GFX12-SDAG-NEXT:    v_min3_u16 v1, v1, v5, v3
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_min3_u16 v0, v0, v4, v2
-; GFX12-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v1, 0xffff, v0
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX12-SDAG-NEXT:    v_min_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v16i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v2.h, 0xff, v10.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v10.l, 0xff, v15.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v7.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v3.h, 0xff, v11.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v3.l, 0xff, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v6.h, 0xff, v14.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v6.l, 0xff, v6.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v1.h, 0xff, v9.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v4.h, 0xff, v13.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v5.l, 0xff, v5.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v1.l, 0xff, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_min_u16 v0.h, v0.h, v10.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v2.l, 0xff, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v7.l, 0xff, v8.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v5.h, 0xff, v12.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v4.l, 0xff, v4.l
+; GFX12-SDAG-TRUE16-NEXT:    v_min_u16 v4.h, v5.l, v4.h
+; GFX12-SDAG-TRUE16-NEXT:    v_min_u16 v1.l, v1.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_min_u16 v1.h, v6.l, v6.h
+; GFX12-SDAG-TRUE16-NEXT:    v_min3_u16 v0.h, v3.l, v3.h, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_min_u16 v3.l, v4.l, v5.h
+; GFX12-SDAG-TRUE16-NEXT:    v_min_u16 v0.l, v0.l, v7.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-SDAG-TRUE16-NEXT:    v_min3_u16 v1.h, v2.l, v2.h, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_min3_u16 v0.h, v1.l, v4.h, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_min3_u16 v0.l, v0.l, v3.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_min_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v16i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v15, 0xff, v15
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v11, 0xff, v11
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v14, 0xff, v14
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v9, 0xff, v9
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v13, 0xff, v13
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_min_u16 v7, v7, v15
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v10, 0xff, v10
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff, v8
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v12, 0xff, v12
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff, v4
+; GFX12-SDAG-FAKE16-NEXT:    v_min_u16 v5, v5, v13
+; GFX12-SDAG-FAKE16-NEXT:    v_min_u16 v1, v1, v9
+; GFX12-SDAG-FAKE16-NEXT:    v_min_u16 v6, v6, v14
+; GFX12-SDAG-FAKE16-NEXT:    v_min3_u16 v3, v3, v11, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_min_u16 v4, v4, v12
+; GFX12-SDAG-FAKE16-NEXT:    v_min_u16 v0, v0, v8
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-SDAG-FAKE16-NEXT:    v_min3_u16 v2, v2, v10, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_min3_u16 v1, v1, v5, v3
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_min3_u16 v0, v0, v4, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_min_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_umin_v16i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1105,13 +1340,19 @@ define i16 @test_vector_reduce_umin_v2i16(<2 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_pk_min_u16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_umin_v2i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_min_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v2i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_min_u16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v2i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_umin_v2i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1121,17 +1362,27 @@ define i16 @test_vector_reduce_umin_v2i16(<2 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_pk_min_u16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_umin_v2i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_min_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v2i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_min_u16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v2i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_min_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_umin_v2i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1212,16 +1463,25 @@ define i16 @test_vector_reduce_umin_v3i16(<3 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_min_u16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_umin_v3i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_perm_b32 v1, -1, v1, 0x5040100
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_pk_min_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_min_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v3i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, -1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_u16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_min_u16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v3i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_perm_b32 v1, -1, v1, 0x5040100
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_umin_v3i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1232,20 +1492,33 @@ define i16 @test_vector_reduce_umin_v3i16(<3 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_min_u16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_umin_v3i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_perm_b32 v1, -1, v1, 0x5040100
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_min_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_min_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v3i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, -1
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_u16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_min_u16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v3i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_perm_b32 v1, -1, v1, 0x5040100
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_min_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_umin_v3i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1340,14 +1613,22 @@ define i16 @test_vector_reduce_umin_v4i16(<4 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_pk_min_u16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_umin_v4i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_pk_min_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    v_min_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v4i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_u16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_min_u16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v4i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_min_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_umin_v4i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1358,18 +1639,30 @@ define i16 @test_vector_reduce_umin_v4i16(<4 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_pk_min_u16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_umin_v4i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_pk_min_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    v_min_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v4i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_u16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_min_u16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v4i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_min_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_umin_v4i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1497,17 +1790,27 @@ define i16 @test_vector_reduce_umin_v8i16(<8 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_pk_min_u16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_umin_v8i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_pk_min_u16 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_pk_min_u16 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_pk_min_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_min_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v8i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_u16 v1, v1, v3
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_u16 v0, v0, v2
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_u16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_min_u16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v8i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_u16 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_u16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_umin_v8i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1521,21 +1824,35 @@ define i16 @test_vector_reduce_umin_v8i16(<8 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_pk_min_u16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_umin_v8i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_pk_min_u16 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_pk_min_u16 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_min_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_min_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v8i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_u16 v1, v1, v3
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_u16 v0, v0, v2
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_u16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_min_u16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v8i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_u16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_u16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_min_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_umin_v8i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1728,22 +2045,37 @@ define i16 @test_vector_reduce_umin_v16i16(<16 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_pk_min_u16 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_umin_v16i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_pk_min_u16 v2, v2, v6
-; GFX11-SDAG-NEXT:    v_pk_min_u16 v3, v3, v7
-; GFX11-SDAG-NEXT:    v_pk_min_u16 v1, v1, v5
-; GFX11-SDAG-NEXT:    v_pk_min_u16 v0, v0, v4
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_pk_min_u16 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_pk_min_u16 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_pk_min_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_min_u16 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v16i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_u16 v2, v2, v6
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_u16 v3, v3, v7
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_u16 v1, v1, v5
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_u16 v0, v0, v4
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_u16 v1, v1, v3
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_u16 v0, v0, v2
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_pk_min_u16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_min_u16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v16i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_u16 v2, v2, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_u16 v3, v3, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_u16 v1, v1, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_u16 v0, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_u16 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_u16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_pk_min_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_min_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_umin_v16i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1762,26 +2094,45 @@ define i16 @test_vector_reduce_umin_v16i16(<16 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_pk_min_u16 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_umin_v16i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_pk_min_u16 v2, v2, v6
-; GFX12-SDAG-NEXT:    v_pk_min_u16 v3, v3, v7
-; GFX12-SDAG-NEXT:    v_pk_min_u16 v1, v1, v5
-; GFX12-SDAG-NEXT:    v_pk_min_u16 v0, v0, v4
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_pk_min_u16 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_pk_min_u16 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_pk_min_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_min_u16 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v16i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_u16 v2, v2, v6
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_u16 v3, v3, v7
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_u16 v1, v1, v5
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_u16 v0, v0, v4
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_u16 v1, v1, v3
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_u16 v0, v0, v2
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_pk_min_u16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_min_u16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v16i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_u16 v2, v2, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_u16 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_u16 v1, v1, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_u16 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_u16 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_u16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_pk_min_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_min_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_umin_v16i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -3873,3 +4224,6 @@ declare i64 @llvm.vector.reduce.umin.v3i64(<3 x i64>)
 declare i64 @llvm.vector.reduce.umin.v4i64(<4 x i64>)
 declare i64 @llvm.vector.reduce.umin.v8i64(<8 x i64>)
 declare i64 @llvm.vector.reduce.umin.v16i64(<16 x i64>)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11-GISEL-FAKE16: {{.*}}
+; GFX12-GISEL-FAKE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
index 277a63f00c2c6..cf344ea9b92d4 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
@@ -7,10 +7,15 @@
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
 ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
+; FIXME-TRUE16. enable gisel
+; XUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
+; XUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
 
 define i8 @test_vector_reduce_xor_v2i8(<2 x i8> %v) {
 ; GFX7-SDAG-LABEL: test_vector_reduce_xor_v2i8:
@@ -69,18 +74,31 @@ define i8 @test_vector_reduce_xor_v2i8(<2 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_xor_v2i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_lshrrev_b16 v2, 8, v1
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v1, v1, v2
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX11-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_xor_v2i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b16 v0.h, 8, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v0.h, v1.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_xor_v2i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b16 v2, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v1, v1, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_xor_v2i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -88,22 +106,39 @@ define i8 @test_vector_reduce_xor_v2i8(<2 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_xor_v2i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_lshrrev_b16 v2, 8, v1
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v1, v1, v2
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_lshlrev_b16 v1, 8, v1
-; GFX12-SDAG-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_xor_v2i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_lshrrev_b16 v0.h, 8, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v0.h, v1.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_xor_v2i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b16 v2, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v1, v1, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_xor_v2i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -175,13 +210,21 @@ define i8 @test_vector_reduce_xor_v3i8(<3 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_xor3_b32 v0, v0, v1, v2
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_xor_v3i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_xor_v3i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_xor_v3i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_xor_v3i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -189,17 +232,29 @@ define i8 @test_vector_reduce_xor_v3i8(<3 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_xor3_b32 v0, v0, v1, v2
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_xor_v3i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_xor_v3i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_xor_v3i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_xor_v3i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -287,15 +342,25 @@ define i8 @test_vector_reduce_xor_v4i8(<4 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_xor_v4i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_xor_v4i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v0.h, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_xor_v4i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_xor_v4i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -306,19 +371,33 @@ define i8 @test_vector_reduce_xor_v4i8(<4 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_xor_v4i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_xor_v4i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v0.h, v1.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_xor_v4i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_xor_v4i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -440,20 +519,35 @@ define i8 @test_vector_reduce_xor_v8i8(<8 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_xor_v8i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v2, v2, v6
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v3, v3, v7
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v1, v1, v5
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v4
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v1, v1, v3
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v2
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_xor_v8i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v0.h, v2.l, v6.l
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v1.h, v3.l, v7.l
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v1.l, v1.l, v5.l
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v0.l, v0.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v1.l, v1.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_xor_v8i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v2, v2, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v3, v3, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v1, v1, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_xor_v8i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -468,24 +562,43 @@ define i8 @test_vector_reduce_xor_v8i8(<8 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_xor_v8i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v2, v2, v6
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v3, v3, v7
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v1, v1, v5
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v4
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v1, v1, v3
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v2
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_xor_v8i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v0.h, v2.l, v6.l
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v1.h, v3.l, v7.l
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v1.l, v1.l, v5.l
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v0.l, v0.l, v4.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v1.l, v1.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_xor_v8i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v2, v2, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v1, v1, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_xor_v8i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -672,29 +785,53 @@ define i8 @test_vector_reduce_xor_v16i8(<16 x i8> %v) {
 ; GFX10-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_xor_v16i8:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v5, v5, v13
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v1, v1, v9
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v7, v7, v15
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v6, v6, v14
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v2, v2, v10
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v3, v3, v11
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v4, v4, v12
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v8
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v1, v1, v5
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v2, v2, v6
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v3, v3, v7
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v4
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v1, v1, v3
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v2
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_xor_v16i8:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v1.h, v5.l, v13.l
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v1.l, v1.l, v9.l
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v5.l, v7.l, v15.l
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v0.h, v6.l, v14.l
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v2.l, v2.l, v10.l
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v2.h, v3.l, v11.l
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v3.l, v4.l, v12.l
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v0.l, v0.l, v8.l
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v1.l, v1.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v0.h, v2.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v2.l, v2.h, v5.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v0.l, v0.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v1.l, v1.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_xor_v16i8:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v5, v5, v13
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v1, v1, v9
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v7, v7, v15
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v6, v6, v14
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v2, v2, v10
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v3, v3, v11
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v4, v4, v12
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v8
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v1, v1, v5
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v2, v2, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v3, v3, v7
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_xor_v16i8:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -715,33 +852,61 @@ define i8 @test_vector_reduce_xor_v16i8(<16 x i8> %v) {
 ; GFX11-GISEL-NEXT:    v_bfe_u32 v0, v0, 0, 8
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_xor_v16i8:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v5, v5, v13
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v1, v1, v9
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v7, v7, v15
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v6, v6, v14
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v2, v2, v10
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v3, v3, v11
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v4, v4, v12
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v8
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v1, v1, v5
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v2, v2, v6
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v3, v3, v7
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v4
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v1, v1, v3
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v2
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_xor_v16i8:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v1.h, v5.l, v13.l
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v1.l, v1.l, v9.l
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v5.l, v7.l, v15.l
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v0.h, v6.l, v14.l
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v2.l, v2.l, v10.l
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v2.h, v3.l, v11.l
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v3.l, v4.l, v12.l
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v0.l, v0.l, v8.l
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v1.l, v1.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v0.h, v2.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v2.l, v2.h, v5.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v0.l, v0.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v1.l, v1.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_xor_v16i8:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v5, v5, v13
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v1, v1, v9
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v7, v7, v15
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v6, v6, v14
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v2, v2, v10
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v3, v3, v11
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v4, v4, v12
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v8
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v1, v1, v5
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v2, v2, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_xor_v16i8:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -824,13 +989,22 @@ define i16 @test_vector_reduce_xor_v2i16(<2 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_xor_b32_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_xor_v2i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_alignbit_b32 v1, s0, v0, 16
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_xor_v2i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_xor_v2i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_alignbit_b32 v1, s0, v0, 16
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_xor_v2i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -840,17 +1014,30 @@ define i16 @test_vector_reduce_xor_v2i16(<2 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_xor_v2i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_alignbit_b32 v1, s0, v0, 16
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_xor_v2i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_xor_v2i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_alignbit_b32 v1, s0, v0, 16
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_xor_v2i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -909,25 +1096,67 @@ define i16 @test_vector_reduce_xor_v3i16(<3 x i16> %v) {
 ; GFX10-NEXT:    v_xor3_b32 v0, v0, v2, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_xor_v3i16:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_xor3_b32 v0, v0, v2, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_xor_v3i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.h, 0
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_xor3_b32 v0, v0, v2, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_xor_v3i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_xor3_b32 v0, v0, v2, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: test_vector_reduce_xor_v3i16:
+; GFX11-GISEL:       ; %bb.0: ; %entry
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_xor3_b32 v0, v0, v2, v1
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: test_vector_reduce_xor_v3i16:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_xor3_b32 v0, v0, v2, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_xor_v3i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.h, 0
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_xor3_b32 v0, v0, v2, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_xor_v3i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_xor3_b32 v0, v0, v2, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: test_vector_reduce_xor_v3i16:
+; GFX12-GISEL:       ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT:    v_xor3_b32 v0, v0, v2, v1
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call i16 @llvm.vector.reduce.xor.v3i16(<3 x i16> %v)
   ret i16 %res
@@ -989,27 +1218,73 @@ define i16 @test_vector_reduce_xor_v4i16(<4 x i16> %v) {
 ; GFX10-NEXT:    v_xor_b32_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: test_vector_reduce_xor_v4i16:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_xor_b32_e32 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_xor_v4i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, 0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_xor_v4i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: test_vector_reduce_xor_v4i16:
+; GFX11-GISEL:       ; %bb.0: ; %entry
+; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: test_vector_reduce_xor_v4i16:
-; GFX12:       ; %bb.0: ; %entry
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_xor_b32_e32 v0, v0, v1
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-NEXT:    v_xor_b32_e32 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_xor_v4i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, 0
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_xor_v4i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-GISEL-LABEL: test_vector_reduce_xor_v4i16:
+; GFX12-GISEL:       ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX12-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %res = call i16 @llvm.vector.reduce.xor.v4i16(<4 x i16> %v)
   ret i16 %res
@@ -1104,16 +1379,28 @@ define i16 @test_vector_reduce_xor_v8i16(<8 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_xor_b32_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_xor_v8i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v1, v1, v3
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_xor3_b32 v0, v0, v2, v1
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_xor_v8i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b32_e32 v1, v1, v3
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT:    v_xor3_b32 v0, v0, v2, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, 0
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_xor_v8i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v1, v1, v3
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_xor3_b32 v0, v0, v2, v1
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_xor_v8i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1127,20 +1414,36 @@ define i16 @test_vector_reduce_xor_v8i16(<8 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_xor_v8i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v1, v1, v3
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_xor3_b32 v0, v0, v2, v1
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_xor_v8i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b32_e32 v1, v1, v3
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT:    v_xor3_b32 v0, v0, v2, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, 0
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_xor_v8i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v1, v1, v3
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_xor3_b32 v0, v0, v2, v1
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_xor_v8i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -1298,19 +1601,34 @@ define i16 @test_vector_reduce_xor_v16i16(<16 x i16> %v) {
 ; GFX10-GISEL-NEXT:    v_xor_b32_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-SDAG-LABEL: test_vector_reduce_xor_v16i16:
-; GFX11-SDAG:       ; %bb.0: ; %entry
-; GFX11-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v3, v3, v7
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v2, v2, v6
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v4
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_xor3_b32 v1, v1, v5, v3
-; GFX11-SDAG-NEXT:    v_xor3_b32 v0, v0, v2, v1
-; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v1
-; GFX11-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_xor_v16i16:
+; GFX11-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b32_e32 v3, v3, v7
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b32_e32 v2, v2, v6
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b32_e32 v0, v0, v4
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_xor3_b32 v1, v1, v5, v3
+; GFX11-SDAG-TRUE16-NEXT:    v_xor3_b32 v0, v0, v2, v1
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, 0
+; GFX11-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_xor_v16i16:
+; GFX11-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX11-SDAG-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v3, v3, v7
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v2, v2, v6
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v4
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_xor3_b32 v1, v1, v5, v3
+; GFX11-SDAG-FAKE16-NEXT:    v_xor3_b32 v0, v0, v2, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-GISEL-LABEL: test_vector_reduce_xor_v16i16:
 ; GFX11-GISEL:       ; %bb.0: ; %entry
@@ -1329,23 +1647,42 @@ define i16 @test_vector_reduce_xor_v16i16(<16 x i16> %v) {
 ; GFX11-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v1
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-SDAG-LABEL: test_vector_reduce_xor_v16i16:
-; GFX12-SDAG:       ; %bb.0: ; %entry
-; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v3, v3, v7
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v2, v2, v6
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v4
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_xor3_b32 v1, v1, v5, v3
-; GFX12-SDAG-NEXT:    v_xor3_b32 v0, v0, v2, v1
-; GFX12-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v1
-; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
+; GFX12-SDAG-TRUE16-LABEL: test_vector_reduce_xor_v16i16:
+; GFX12-SDAG-TRUE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b32_e32 v3, v3, v7
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b32_e32 v2, v2, v6
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b32_e32 v0, v0, v4
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_xor3_b32 v1, v1, v5, v3
+; GFX12-SDAG-TRUE16-NEXT:    v_xor3_b32 v0, v0, v2, v1
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.h, 0
+; GFX12-SDAG-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_xor_v16i16:
+; GFX12-SDAG-FAKE16:       ; %bb.0: ; %entry
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v3, v3, v7
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v2, v2, v6
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v4
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_xor3_b32 v1, v1, v5, v3
+; GFX12-SDAG-FAKE16-NEXT:    v_xor3_b32 v0, v0, v2, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX12-GISEL-LABEL: test_vector_reduce_xor_v16i16:
 ; GFX12-GISEL:       ; %bb.0: ; %entry
@@ -2957,3 +3294,6 @@ declare i64 @llvm.vector.reduce.xor.v3i64(<3 x i64>)
 declare i64 @llvm.vector.reduce.xor.v4i64(<4 x i64>)
 declare i64 @llvm.vector.reduce.xor.v8i64(<8 x i64>)
 declare i64 @llvm.vector.reduce.xor.v16i64(<16 x i64>)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11-GISEL-FAKE16: {{.*}}
+; GFX12-GISEL-FAKE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll b/llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll
index b079a94b5fcc3..587f5d05d358b 100644
--- a/llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll
@@ -1,35 +1,47 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define <2 x i8> @shuffle_v2i8_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v2i8_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_ushort v0, v[0:1], off
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_lshrrev_b16_e32 v0, 8, v0
-; GFX9-NEXT:  v_mov_b32_e32 v1, v0
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_ushort v0, v[0:1], off
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_lshrrev_b16_e32 v0, 8, v0
+; GFX9-NEXT:    v_mov_b32_e32 v1, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v2i8_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_ushort v0, v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_lshrrev_b16 v0, 8, v0
-; GFX10-NEXT:  v_mov_b32_e32 v1, v0
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: shuffle_v2i8_rebroadcast:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_u16 v0, v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_lshrrev_b16 v0, 8, v0
-; GFX11-NEXT:  s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:  v_mov_b32_e32 v1, v0
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_ushort v0, v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_lshrrev_b16 v0, 8, v0
+; GFX10-NEXT:    v_mov_b32_e32 v1, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: shuffle_v2i8_rebroadcast:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b16 v1.l, 8, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v1.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v2i8_rebroadcast:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_u16 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b16 v0, 8, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <2 x i8>, ptr addrspace(1) %arg0
   %val1 = shufflevector <2 x i8> %val0, <2 x i8> poison, <2 x i32> <i32 1, i32 1>
@@ -39,37 +51,49 @@ entry:
 define <4 x i8> @shuffle_v4i8_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v4i8_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v0, v[0:1], off
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_lshrrev_b32_e32 v0, 8, v0
-; GFX9-NEXT:  v_mov_b32_e32 v1, v0
-; GFX9-NEXT:  v_mov_b32_e32 v2, v0
-; GFX9-NEXT:  v_mov_b32_e32 v3, v0
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v[0:1], off
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
+; GFX9-NEXT:    v_mov_b32_e32 v1, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, v0
+; GFX9-NEXT:    v_mov_b32_e32 v3, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v4i8_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v0, v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_lshrrev_b32_e32 v0, 8, v0
-; GFX10-NEXT:  v_mov_b32_e32 v1, v0
-; GFX10-NEXT:  v_mov_b32_e32 v2, v0
-; GFX10-NEXT:  v_mov_b32_e32 v3, v0
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: shuffle_v4i8_rebroadcast:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_lshrrev_b32_e32 v0, 8, v0
-; GFX11-NEXT:  s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:  v_mov_b32_e32 v1, v0
-; GFX11-NEXT:  v_mov_b32_e32 v2, v0
-; GFX11-NEXT:  v_mov_b32_e32 v3, v0
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
+; GFX10-NEXT:    v_mov_b32_e32 v1, v0
+; GFX10-NEXT:    v_mov_b32_e32 v2, v0
+; GFX10-NEXT:    v_mov_b32_e32 v3, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: shuffle_v4i8_rebroadcast:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 8, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v3.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4i8_rebroadcast:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <4 x i8>, ptr addrspace(1) %arg0
   %val1 = shufflevector <4 x i8> %val0, <4 x i8> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
@@ -79,49 +103,65 @@ entry:
 define <8 x i8> @shuffle_v8i8_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v8i8_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v0, v[0:1], off
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_lshrrev_b32_e32 v0, 8, v0
-; GFX9-NEXT:  v_mov_b32_e32 v1, v0
-; GFX9-NEXT:  v_mov_b32_e32 v2, v0
-; GFX9-NEXT:  v_mov_b32_e32 v3, v0
-; GFX9-NEXT:  v_mov_b32_e32 v4, v0
-; GFX9-NEXT:  v_mov_b32_e32 v5, v0
-; GFX9-NEXT:  v_mov_b32_e32 v6, v0
-; GFX9-NEXT:  v_mov_b32_e32 v7, v0
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v[0:1], off
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
+; GFX9-NEXT:    v_mov_b32_e32 v1, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, v0
+; GFX9-NEXT:    v_mov_b32_e32 v3, v0
+; GFX9-NEXT:    v_mov_b32_e32 v4, v0
+; GFX9-NEXT:    v_mov_b32_e32 v5, v0
+; GFX9-NEXT:    v_mov_b32_e32 v6, v0
+; GFX9-NEXT:    v_mov_b32_e32 v7, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v8i8_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v0, v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_lshrrev_b32_e32 v0, 8, v0
-; GFX10-NEXT:  v_mov_b32_e32 v1, v0
-; GFX10-NEXT:  v_mov_b32_e32 v2, v0
-; GFX10-NEXT:  v_mov_b32_e32 v3, v0
-; GFX10-NEXT:  v_mov_b32_e32 v4, v0
-; GFX10-NEXT:  v_mov_b32_e32 v5, v0
-; GFX10-NEXT:  v_mov_b32_e32 v6, v0
-; GFX10-NEXT:  v_mov_b32_e32 v7, v0
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: shuffle_v8i8_rebroadcast:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_lshrrev_b32_e32 v0, 8, v0
-; GFX11-NEXT:  s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:  v_mov_b32_e32 v1, v0
-; GFX11-NEXT:  v_mov_b32_e32 v2, v0
-; GFX11-NEXT:  v_mov_b32_e32 v3, v0
-; GFX11-NEXT:  v_mov_b32_e32 v4, v0
-; GFX11-NEXT:  v_mov_b32_e32 v5, v0
-; GFX11-NEXT:  v_mov_b32_e32 v6, v0
-; GFX11-NEXT:  v_mov_b32_e32 v7, v0
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
+; GFX10-NEXT:    v_mov_b32_e32 v1, v0
+; GFX10-NEXT:    v_mov_b32_e32 v2, v0
+; GFX10-NEXT:    v_mov_b32_e32 v3, v0
+; GFX10-NEXT:    v_mov_b32_e32 v4, v0
+; GFX10-NEXT:    v_mov_b32_e32 v5, v0
+; GFX10-NEXT:    v_mov_b32_e32 v6, v0
+; GFX10-NEXT:    v_mov_b32_e32 v7, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: shuffle_v8i8_rebroadcast:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 8, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v7.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v7.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v8i8_rebroadcast:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v6, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v7, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <8 x i8>, ptr addrspace(1) %arg0
   %val1 = shufflevector <8 x i8> %val0, <8 x i8> poison, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -131,73 +171,97 @@ entry:
 define <16 x i8> @shuffle_v16i8_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v16i8_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v0, v[0:1], off
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_lshrrev_b32_e32 v0, 8, v0
-; GFX9-NEXT:  v_mov_b32_e32 v1, v0
-; GFX9-NEXT:  v_mov_b32_e32 v2, v0
-; GFX9-NEXT:  v_mov_b32_e32 v3, v0
-; GFX9-NEXT:  v_mov_b32_e32 v4, v0
-; GFX9-NEXT:  v_mov_b32_e32 v5, v0
-; GFX9-NEXT:  v_mov_b32_e32 v6, v0
-; GFX9-NEXT:  v_mov_b32_e32 v7, v0
-; GFX9-NEXT:  v_mov_b32_e32 v8, v0
-; GFX9-NEXT:  v_mov_b32_e32 v9, v0
-; GFX9-NEXT:  v_mov_b32_e32 v10, v0
-; GFX9-NEXT:  v_mov_b32_e32 v11, v0
-; GFX9-NEXT:  v_mov_b32_e32 v12, v0
-; GFX9-NEXT:  v_mov_b32_e32 v13, v0
-; GFX9-NEXT:  v_mov_b32_e32 v14, v0
-; GFX9-NEXT:  v_mov_b32_e32 v15, v0
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v[0:1], off
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
+; GFX9-NEXT:    v_mov_b32_e32 v1, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, v0
+; GFX9-NEXT:    v_mov_b32_e32 v3, v0
+; GFX9-NEXT:    v_mov_b32_e32 v4, v0
+; GFX9-NEXT:    v_mov_b32_e32 v5, v0
+; GFX9-NEXT:    v_mov_b32_e32 v6, v0
+; GFX9-NEXT:    v_mov_b32_e32 v7, v0
+; GFX9-NEXT:    v_mov_b32_e32 v8, v0
+; GFX9-NEXT:    v_mov_b32_e32 v9, v0
+; GFX9-NEXT:    v_mov_b32_e32 v10, v0
+; GFX9-NEXT:    v_mov_b32_e32 v11, v0
+; GFX9-NEXT:    v_mov_b32_e32 v12, v0
+; GFX9-NEXT:    v_mov_b32_e32 v13, v0
+; GFX9-NEXT:    v_mov_b32_e32 v14, v0
+; GFX9-NEXT:    v_mov_b32_e32 v15, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v16i8_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v0, v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_lshrrev_b32_e32 v0, 8, v0
-; GFX10-NEXT:  v_mov_b32_e32 v1, v0
-; GFX10-NEXT:  v_mov_b32_e32 v2, v0
-; GFX10-NEXT:  v_mov_b32_e32 v3, v0
-; GFX10-NEXT:  v_mov_b32_e32 v4, v0
-; GFX10-NEXT:  v_mov_b32_e32 v5, v0
-; GFX10-NEXT:  v_mov_b32_e32 v6, v0
-; GFX10-NEXT:  v_mov_b32_e32 v7, v0
-; GFX10-NEXT:  v_mov_b32_e32 v8, v0
-; GFX10-NEXT:  v_mov_b32_e32 v9, v0
-; GFX10-NEXT:  v_mov_b32_e32 v10, v0
-; GFX10-NEXT:  v_mov_b32_e32 v11, v0
-; GFX10-NEXT:  v_mov_b32_e32 v12, v0
-; GFX10-NEXT:  v_mov_b32_e32 v13, v0
-; GFX10-NEXT:  v_mov_b32_e32 v14, v0
-; GFX10-NEXT:  v_mov_b32_e32 v15, v0
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: shuffle_v16i8_rebroadcast:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_lshrrev_b32_e32 v0, 8, v0
-; GFX11-NEXT:  s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:  v_mov_b32_e32 v1, v0
-; GFX11-NEXT:  v_mov_b32_e32 v2, v0
-; GFX11-NEXT:  v_mov_b32_e32 v3, v0
-; GFX11-NEXT:  v_mov_b32_e32 v4, v0
-; GFX11-NEXT:  v_mov_b32_e32 v5, v0
-; GFX11-NEXT:  v_mov_b32_e32 v6, v0
-; GFX11-NEXT:  v_mov_b32_e32 v7, v0
-; GFX11-NEXT:  v_mov_b32_e32 v8, v0
-; GFX11-NEXT:  v_mov_b32_e32 v9, v0
-; GFX11-NEXT:  v_mov_b32_e32 v10, v0
-; GFX11-NEXT:  v_mov_b32_e32 v11, v0
-; GFX11-NEXT:  v_mov_b32_e32 v12, v0
-; GFX11-NEXT:  v_mov_b32_e32 v13, v0
-; GFX11-NEXT:  v_mov_b32_e32 v14, v0
-; GFX11-NEXT:  v_mov_b32_e32 v15, v0
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
+; GFX10-NEXT:    v_mov_b32_e32 v1, v0
+; GFX10-NEXT:    v_mov_b32_e32 v2, v0
+; GFX10-NEXT:    v_mov_b32_e32 v3, v0
+; GFX10-NEXT:    v_mov_b32_e32 v4, v0
+; GFX10-NEXT:    v_mov_b32_e32 v5, v0
+; GFX10-NEXT:    v_mov_b32_e32 v6, v0
+; GFX10-NEXT:    v_mov_b32_e32 v7, v0
+; GFX10-NEXT:    v_mov_b32_e32 v8, v0
+; GFX10-NEXT:    v_mov_b32_e32 v9, v0
+; GFX10-NEXT:    v_mov_b32_e32 v10, v0
+; GFX10-NEXT:    v_mov_b32_e32 v11, v0
+; GFX10-NEXT:    v_mov_b32_e32 v12, v0
+; GFX10-NEXT:    v_mov_b32_e32 v13, v0
+; GFX10-NEXT:    v_mov_b32_e32 v14, v0
+; GFX10-NEXT:    v_mov_b32_e32 v15, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: shuffle_v16i8_rebroadcast:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v15, 8, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v15.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v15.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v15.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v15.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v15.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v15.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v15.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v15.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v15.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v15.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v15.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v15.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v15.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v15.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v15.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v16i8_rebroadcast:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v6, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v7, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v10, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v11, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v12, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v13, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v14, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v15, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <16 x i8>, ptr addrspace(1) %arg0
   %val1 = shufflevector <16 x i8> %val0, <16 x i8> poison, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -207,121 +271,161 @@ entry:
 define <32 x i8> @shuffle_v32i8_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v32i8_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v0, v[0:1], off
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_lshrrev_b32_e32 v0, 8, v0
-; GFX9-NEXT:  v_mov_b32_e32 v1, v0
-; GFX9-NEXT:  v_mov_b32_e32 v2, v0
-; GFX9-NEXT:  v_mov_b32_e32 v3, v0
-; GFX9-NEXT:  v_mov_b32_e32 v4, v0
-; GFX9-NEXT:  v_mov_b32_e32 v5, v0
-; GFX9-NEXT:  v_mov_b32_e32 v6, v0
-; GFX9-NEXT:  v_mov_b32_e32 v7, v0
-; GFX9-NEXT:  v_mov_b32_e32 v8, v0
-; GFX9-NEXT:  v_mov_b32_e32 v9, v0
-; GFX9-NEXT:  v_mov_b32_e32 v10, v0
-; GFX9-NEXT:  v_mov_b32_e32 v11, v0
-; GFX9-NEXT:  v_mov_b32_e32 v12, v0
-; GFX9-NEXT:  v_mov_b32_e32 v13, v0
-; GFX9-NEXT:  v_mov_b32_e32 v14, v0
-; GFX9-NEXT:  v_mov_b32_e32 v15, v0
-; GFX9-NEXT:  v_mov_b32_e32 v16, v0
-; GFX9-NEXT:  v_mov_b32_e32 v17, v0
-; GFX9-NEXT:  v_mov_b32_e32 v18, v0
-; GFX9-NEXT:  v_mov_b32_e32 v19, v0
-; GFX9-NEXT:  v_mov_b32_e32 v20, v0
-; GFX9-NEXT:  v_mov_b32_e32 v21, v0
-; GFX9-NEXT:  v_mov_b32_e32 v22, v0
-; GFX9-NEXT:  v_mov_b32_e32 v23, v0
-; GFX9-NEXT:  v_mov_b32_e32 v24, v0
-; GFX9-NEXT:  v_mov_b32_e32 v25, v0
-; GFX9-NEXT:  v_mov_b32_e32 v26, v0
-; GFX9-NEXT:  v_mov_b32_e32 v27, v0
-; GFX9-NEXT:  v_mov_b32_e32 v28, v0
-; GFX9-NEXT:  v_mov_b32_e32 v29, v0
-; GFX9-NEXT:  v_mov_b32_e32 v30, v0
-; GFX9-NEXT:  v_mov_b32_e32 v31, v0
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v[0:1], off
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
+; GFX9-NEXT:    v_mov_b32_e32 v1, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, v0
+; GFX9-NEXT:    v_mov_b32_e32 v3, v0
+; GFX9-NEXT:    v_mov_b32_e32 v4, v0
+; GFX9-NEXT:    v_mov_b32_e32 v5, v0
+; GFX9-NEXT:    v_mov_b32_e32 v6, v0
+; GFX9-NEXT:    v_mov_b32_e32 v7, v0
+; GFX9-NEXT:    v_mov_b32_e32 v8, v0
+; GFX9-NEXT:    v_mov_b32_e32 v9, v0
+; GFX9-NEXT:    v_mov_b32_e32 v10, v0
+; GFX9-NEXT:    v_mov_b32_e32 v11, v0
+; GFX9-NEXT:    v_mov_b32_e32 v12, v0
+; GFX9-NEXT:    v_mov_b32_e32 v13, v0
+; GFX9-NEXT:    v_mov_b32_e32 v14, v0
+; GFX9-NEXT:    v_mov_b32_e32 v15, v0
+; GFX9-NEXT:    v_mov_b32_e32 v16, v0
+; GFX9-NEXT:    v_mov_b32_e32 v17, v0
+; GFX9-NEXT:    v_mov_b32_e32 v18, v0
+; GFX9-NEXT:    v_mov_b32_e32 v19, v0
+; GFX9-NEXT:    v_mov_b32_e32 v20, v0
+; GFX9-NEXT:    v_mov_b32_e32 v21, v0
+; GFX9-NEXT:    v_mov_b32_e32 v22, v0
+; GFX9-NEXT:    v_mov_b32_e32 v23, v0
+; GFX9-NEXT:    v_mov_b32_e32 v24, v0
+; GFX9-NEXT:    v_mov_b32_e32 v25, v0
+; GFX9-NEXT:    v_mov_b32_e32 v26, v0
+; GFX9-NEXT:    v_mov_b32_e32 v27, v0
+; GFX9-NEXT:    v_mov_b32_e32 v28, v0
+; GFX9-NEXT:    v_mov_b32_e32 v29, v0
+; GFX9-NEXT:    v_mov_b32_e32 v30, v0
+; GFX9-NEXT:    v_mov_b32_e32 v31, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v32i8_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v0, v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_lshrrev_b32_e32 v0, 8, v0
-; GFX10-NEXT:  v_mov_b32_e32 v1, v0
-; GFX10-NEXT:  v_mov_b32_e32 v2, v0
-; GFX10-NEXT:  v_mov_b32_e32 v3, v0
-; GFX10-NEXT:  v_mov_b32_e32 v4, v0
-; GFX10-NEXT:  v_mov_b32_e32 v5, v0
-; GFX10-NEXT:  v_mov_b32_e32 v6, v0
-; GFX10-NEXT:  v_mov_b32_e32 v7, v0
-; GFX10-NEXT:  v_mov_b32_e32 v8, v0
-; GFX10-NEXT:  v_mov_b32_e32 v9, v0
-; GFX10-NEXT:  v_mov_b32_e32 v10, v0
-; GFX10-NEXT:  v_mov_b32_e32 v11, v0
-; GFX10-NEXT:  v_mov_b32_e32 v12, v0
-; GFX10-NEXT:  v_mov_b32_e32 v13, v0
-; GFX10-NEXT:  v_mov_b32_e32 v14, v0
-; GFX10-NEXT:  v_mov_b32_e32 v15, v0
-; GFX10-NEXT:  v_mov_b32_e32 v16, v0
-; GFX10-NEXT:  v_mov_b32_e32 v17, v0
-; GFX10-NEXT:  v_mov_b32_e32 v18, v0
-; GFX10-NEXT:  v_mov_b32_e32 v19, v0
-; GFX10-NEXT:  v_mov_b32_e32 v20, v0
-; GFX10-NEXT:  v_mov_b32_e32 v21, v0
-; GFX10-NEXT:  v_mov_b32_e32 v22, v0
-; GFX10-NEXT:  v_mov_b32_e32 v23, v0
-; GFX10-NEXT:  v_mov_b32_e32 v24, v0
-; GFX10-NEXT:  v_mov_b32_e32 v25, v0
-; GFX10-NEXT:  v_mov_b32_e32 v26, v0
-; GFX10-NEXT:  v_mov_b32_e32 v27, v0
-; GFX10-NEXT:  v_mov_b32_e32 v28, v0
-; GFX10-NEXT:  v_mov_b32_e32 v29, v0
-; GFX10-NEXT:  v_mov_b32_e32 v30, v0
-; GFX10-NEXT:  v_mov_b32_e32 v31, v0
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: shuffle_v32i8_rebroadcast:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_lshrrev_b32_e32 v0, 8, v0
-; GFX11-NEXT:  s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:  v_mov_b32_e32 v1, v0
-; GFX11-NEXT:  v_mov_b32_e32 v2, v0
-; GFX11-NEXT:  v_mov_b32_e32 v3, v0
-; GFX11-NEXT:  v_mov_b32_e32 v4, v0
-; GFX11-NEXT:  v_mov_b32_e32 v5, v0
-; GFX11-NEXT:  v_mov_b32_e32 v6, v0
-; GFX11-NEXT:  v_mov_b32_e32 v7, v0
-; GFX11-NEXT:  v_mov_b32_e32 v8, v0
-; GFX11-NEXT:  v_mov_b32_e32 v9, v0
-; GFX11-NEXT:  v_mov_b32_e32 v10, v0
-; GFX11-NEXT:  v_mov_b32_e32 v11, v0
-; GFX11-NEXT:  v_mov_b32_e32 v12, v0
-; GFX11-NEXT:  v_mov_b32_e32 v13, v0
-; GFX11-NEXT:  v_mov_b32_e32 v14, v0
-; GFX11-NEXT:  v_mov_b32_e32 v15, v0
-; GFX11-NEXT:  v_mov_b32_e32 v16, v0
-; GFX11-NEXT:  v_mov_b32_e32 v17, v0
-; GFX11-NEXT:  v_mov_b32_e32 v18, v0
-; GFX11-NEXT:  v_mov_b32_e32 v19, v0
-; GFX11-NEXT:  v_mov_b32_e32 v20, v0
-; GFX11-NEXT:  v_mov_b32_e32 v21, v0
-; GFX11-NEXT:  v_mov_b32_e32 v22, v0
-; GFX11-NEXT:  v_mov_b32_e32 v23, v0
-; GFX11-NEXT:  v_mov_b32_e32 v24, v0
-; GFX11-NEXT:  v_mov_b32_e32 v25, v0
-; GFX11-NEXT:  v_mov_b32_e32 v26, v0
-; GFX11-NEXT:  v_mov_b32_e32 v27, v0
-; GFX11-NEXT:  v_mov_b32_e32 v28, v0
-; GFX11-NEXT:  v_mov_b32_e32 v29, v0
-; GFX11-NEXT:  v_mov_b32_e32 v30, v0
-; GFX11-NEXT:  v_mov_b32_e32 v31, v0
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
+; GFX10-NEXT:    v_mov_b32_e32 v1, v0
+; GFX10-NEXT:    v_mov_b32_e32 v2, v0
+; GFX10-NEXT:    v_mov_b32_e32 v3, v0
+; GFX10-NEXT:    v_mov_b32_e32 v4, v0
+; GFX10-NEXT:    v_mov_b32_e32 v5, v0
+; GFX10-NEXT:    v_mov_b32_e32 v6, v0
+; GFX10-NEXT:    v_mov_b32_e32 v7, v0
+; GFX10-NEXT:    v_mov_b32_e32 v8, v0
+; GFX10-NEXT:    v_mov_b32_e32 v9, v0
+; GFX10-NEXT:    v_mov_b32_e32 v10, v0
+; GFX10-NEXT:    v_mov_b32_e32 v11, v0
+; GFX10-NEXT:    v_mov_b32_e32 v12, v0
+; GFX10-NEXT:    v_mov_b32_e32 v13, v0
+; GFX10-NEXT:    v_mov_b32_e32 v14, v0
+; GFX10-NEXT:    v_mov_b32_e32 v15, v0
+; GFX10-NEXT:    v_mov_b32_e32 v16, v0
+; GFX10-NEXT:    v_mov_b32_e32 v17, v0
+; GFX10-NEXT:    v_mov_b32_e32 v18, v0
+; GFX10-NEXT:    v_mov_b32_e32 v19, v0
+; GFX10-NEXT:    v_mov_b32_e32 v20, v0
+; GFX10-NEXT:    v_mov_b32_e32 v21, v0
+; GFX10-NEXT:    v_mov_b32_e32 v22, v0
+; GFX10-NEXT:    v_mov_b32_e32 v23, v0
+; GFX10-NEXT:    v_mov_b32_e32 v24, v0
+; GFX10-NEXT:    v_mov_b32_e32 v25, v0
+; GFX10-NEXT:    v_mov_b32_e32 v26, v0
+; GFX10-NEXT:    v_mov_b32_e32 v27, v0
+; GFX10-NEXT:    v_mov_b32_e32 v28, v0
+; GFX10-NEXT:    v_mov_b32_e32 v29, v0
+; GFX10-NEXT:    v_mov_b32_e32 v30, v0
+; GFX10-NEXT:    v_mov_b32_e32 v31, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: shuffle_v32i8_rebroadcast:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v31, 8, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v17.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v18.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v20.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v21.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v22.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v23.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v24.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v25.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v26.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.l, v31.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.l, v31.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v32i8_rebroadcast:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v6, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v7, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v10, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v11, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v12, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v13, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v14, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v15, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v16, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v17, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v18, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v19, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v20, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v21, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v22, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v23, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v24, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v25, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v26, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v27, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v28, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v29, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v30, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v31, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <32 x i8>, ptr addrspace(1) %arg0
   %val1 = shufflevector <32 x i8> %val0, <32 x i8> poison, <32 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -331,28 +435,39 @@ entry:
 define <2 x i16> @shuffle_v2i16_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v2i16_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v0, v[0:1], off
-; GFX9-NEXT:  s_mov_b32 s4, 0x7060302
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_perm_b32 v0, v0, v0, s4
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v[0:1], off
+; GFX9-NEXT:    s_mov_b32 s4, 0x7060302
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_perm_b32 v0, v0, v0, s4
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v2i16_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v0, v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: shuffle_v2i16_rebroadcast:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: shuffle_v2i16_rebroadcast:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v2i16_rebroadcast:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <2 x i16>, ptr addrspace(1) %arg0
   %val1 = shufflevector <2 x i16> %val0, <2 x i16> poison, <2 x i32> <i32 1, i32 1>
@@ -362,32 +477,44 @@ entry:
 define <4 x i16> @shuffle_v4i16_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v4i16_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v0, v[0:1], off
-; GFX9-NEXT:  s_mov_b32 s4, 0x7060302
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_perm_b32 v0, v0, v0, s4
-; GFX9-NEXT:  v_mov_b32_e32 v1, v0
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v[0:1], off
+; GFX9-NEXT:    s_mov_b32 s4, 0x7060302
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_perm_b32 v0, v0, v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v1, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v4i16_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v0, v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX10-NEXT:  v_mov_b32_e32 v1, v0
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: shuffle_v4i16_rebroadcast:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX11-NEXT:  s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:  v_mov_b32_e32 v1, v0
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX10-NEXT:    v_mov_b32_e32 v1, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: shuffle_v4i16_rebroadcast:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4i16_rebroadcast:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <4 x i16>, ptr addrspace(1) %arg0
   %val1 = shufflevector <4 x i16> %val0, <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
@@ -397,38 +524,52 @@ entry:
 define <8 x i16> @shuffle_v8i16_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v8i16_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v0, v[0:1], off
-; GFX9-NEXT:  s_mov_b32 s4, 0x7060302
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_perm_b32 v0, v0, v0, s4
-; GFX9-NEXT:  v_mov_b32_e32 v1, v0
-; GFX9-NEXT:  v_mov_b32_e32 v2, v0
-; GFX9-NEXT:  v_mov_b32_e32 v3, v0
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v[0:1], off
+; GFX9-NEXT:    s_mov_b32 s4, 0x7060302
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_perm_b32 v0, v0, v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v1, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, v0
+; GFX9-NEXT:    v_mov_b32_e32 v3, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v8i16_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v0, v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX10-NEXT:  v_mov_b32_e32 v1, v0
-; GFX10-NEXT:  v_mov_b32_e32 v2, v0
-; GFX10-NEXT:  v_mov_b32_e32 v3, v0
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: shuffle_v8i16_rebroadcast:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX11-NEXT:  s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:  v_mov_b32_e32 v1, v0
-; GFX11-NEXT:  v_mov_b32_e32 v2, v0
-; GFX11-NEXT:  v_mov_b32_e32 v3, v0
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX10-NEXT:    v_mov_b32_e32 v1, v0
+; GFX10-NEXT:    v_mov_b32_e32 v2, v0
+; GFX10-NEXT:    v_mov_b32_e32 v3, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: shuffle_v8i16_rebroadcast:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v8i16_rebroadcast:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <8 x i16>, ptr addrspace(1) %arg0
   %val1 = shufflevector <8 x i16> %val0, <8 x i16> poison, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -438,50 +579,68 @@ entry:
 define <16 x i16> @shuffle_v16i16_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v16i16_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v0, v[0:1], off
-; GFX9-NEXT:  s_mov_b32 s4, 0x7060302
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_perm_b32 v0, v0, v0, s4
-; GFX9-NEXT:  v_mov_b32_e32 v1, v0
-; GFX9-NEXT:  v_mov_b32_e32 v2, v0
-; GFX9-NEXT:  v_mov_b32_e32 v3, v0
-; GFX9-NEXT:  v_mov_b32_e32 v4, v0
-; GFX9-NEXT:  v_mov_b32_e32 v5, v0
-; GFX9-NEXT:  v_mov_b32_e32 v6, v0
-; GFX9-NEXT:  v_mov_b32_e32 v7, v0
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v[0:1], off
+; GFX9-NEXT:    s_mov_b32 s4, 0x7060302
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_perm_b32 v0, v0, v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v1, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, v0
+; GFX9-NEXT:    v_mov_b32_e32 v3, v0
+; GFX9-NEXT:    v_mov_b32_e32 v4, v0
+; GFX9-NEXT:    v_mov_b32_e32 v5, v0
+; GFX9-NEXT:    v_mov_b32_e32 v6, v0
+; GFX9-NEXT:    v_mov_b32_e32 v7, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v16i16_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v0, v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX10-NEXT:  v_mov_b32_e32 v1, v0
-; GFX10-NEXT:  v_mov_b32_e32 v2, v0
-; GFX10-NEXT:  v_mov_b32_e32 v3, v0
-; GFX10-NEXT:  v_mov_b32_e32 v4, v0
-; GFX10-NEXT:  v_mov_b32_e32 v5, v0
-; GFX10-NEXT:  v_mov_b32_e32 v6, v0
-; GFX10-NEXT:  v_mov_b32_e32 v7, v0
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: shuffle_v16i16_rebroadcast:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX11-NEXT:  s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:  v_mov_b32_e32 v1, v0
-; GFX11-NEXT:  v_mov_b32_e32 v2, v0
-; GFX11-NEXT:  v_mov_b32_e32 v3, v0
-; GFX11-NEXT:  v_mov_b32_e32 v4, v0
-; GFX11-NEXT:  v_mov_b32_e32 v5, v0
-; GFX11-NEXT:  v_mov_b32_e32 v6, v0
-; GFX11-NEXT:  v_mov_b32_e32 v7, v0
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX10-NEXT:    v_mov_b32_e32 v1, v0
+; GFX10-NEXT:    v_mov_b32_e32 v2, v0
+; GFX10-NEXT:    v_mov_b32_e32 v3, v0
+; GFX10-NEXT:    v_mov_b32_e32 v4, v0
+; GFX10-NEXT:    v_mov_b32_e32 v5, v0
+; GFX10-NEXT:    v_mov_b32_e32 v6, v0
+; GFX10-NEXT:    v_mov_b32_e32 v7, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: shuffle_v16i16_rebroadcast:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v4, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v5, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v6, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v7, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v16i16_rebroadcast:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v6, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v7, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <16 x i16>, ptr addrspace(1) %arg0
   %val1 = shufflevector <16 x i16> %val0, <16 x i16> poison, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -491,74 +650,100 @@ entry:
 define <32 x i16> @shuffle_v32i16_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v32i16_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v0, v[0:1], off
-; GFX9-NEXT:  s_mov_b32 s4, 0x7060302
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_perm_b32 v0, v0, v0, s4
-; GFX9-NEXT:  v_mov_b32_e32 v1, v0
-; GFX9-NEXT:  v_mov_b32_e32 v2, v0
-; GFX9-NEXT:  v_mov_b32_e32 v3, v0
-; GFX9-NEXT:  v_mov_b32_e32 v4, v0
-; GFX9-NEXT:  v_mov_b32_e32 v5, v0
-; GFX9-NEXT:  v_mov_b32_e32 v6, v0
-; GFX9-NEXT:  v_mov_b32_e32 v7, v0
-; GFX9-NEXT:  v_mov_b32_e32 v8, v0
-; GFX9-NEXT:  v_mov_b32_e32 v9, v0
-; GFX9-NEXT:  v_mov_b32_e32 v10, v0
-; GFX9-NEXT:  v_mov_b32_e32 v11, v0
-; GFX9-NEXT:  v_mov_b32_e32 v12, v0
-; GFX9-NEXT:  v_mov_b32_e32 v13, v0
-; GFX9-NEXT:  v_mov_b32_e32 v14, v0
-; GFX9-NEXT:  v_mov_b32_e32 v15, v0
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v[0:1], off
+; GFX9-NEXT:    s_mov_b32 s4, 0x7060302
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_perm_b32 v0, v0, v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v1, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, v0
+; GFX9-NEXT:    v_mov_b32_e32 v3, v0
+; GFX9-NEXT:    v_mov_b32_e32 v4, v0
+; GFX9-NEXT:    v_mov_b32_e32 v5, v0
+; GFX9-NEXT:    v_mov_b32_e32 v6, v0
+; GFX9-NEXT:    v_mov_b32_e32 v7, v0
+; GFX9-NEXT:    v_mov_b32_e32 v8, v0
+; GFX9-NEXT:    v_mov_b32_e32 v9, v0
+; GFX9-NEXT:    v_mov_b32_e32 v10, v0
+; GFX9-NEXT:    v_mov_b32_e32 v11, v0
+; GFX9-NEXT:    v_mov_b32_e32 v12, v0
+; GFX9-NEXT:    v_mov_b32_e32 v13, v0
+; GFX9-NEXT:    v_mov_b32_e32 v14, v0
+; GFX9-NEXT:    v_mov_b32_e32 v15, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v32i16_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v0, v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX10-NEXT:  v_mov_b32_e32 v1, v0
-; GFX10-NEXT:  v_mov_b32_e32 v2, v0
-; GFX10-NEXT:  v_mov_b32_e32 v3, v0
-; GFX10-NEXT:  v_mov_b32_e32 v4, v0
-; GFX10-NEXT:  v_mov_b32_e32 v5, v0
-; GFX10-NEXT:  v_mov_b32_e32 v6, v0
-; GFX10-NEXT:  v_mov_b32_e32 v7, v0
-; GFX10-NEXT:  v_mov_b32_e32 v8, v0
-; GFX10-NEXT:  v_mov_b32_e32 v9, v0
-; GFX10-NEXT:  v_mov_b32_e32 v10, v0
-; GFX10-NEXT:  v_mov_b32_e32 v11, v0
-; GFX10-NEXT:  v_mov_b32_e32 v12, v0
-; GFX10-NEXT:  v_mov_b32_e32 v13, v0
-; GFX10-NEXT:  v_mov_b32_e32 v14, v0
-; GFX10-NEXT:  v_mov_b32_e32 v15, v0
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: shuffle_v32i16_rebroadcast:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX11-NEXT:  s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:  v_mov_b32_e32 v1, v0
-; GFX11-NEXT:  v_mov_b32_e32 v2, v0
-; GFX11-NEXT:  v_mov_b32_e32 v3, v0
-; GFX11-NEXT:  v_mov_b32_e32 v4, v0
-; GFX11-NEXT:  v_mov_b32_e32 v5, v0
-; GFX11-NEXT:  v_mov_b32_e32 v6, v0
-; GFX11-NEXT:  v_mov_b32_e32 v7, v0
-; GFX11-NEXT:  v_mov_b32_e32 v8, v0
-; GFX11-NEXT:  v_mov_b32_e32 v9, v0
-; GFX11-NEXT:  v_mov_b32_e32 v10, v0
-; GFX11-NEXT:  v_mov_b32_e32 v11, v0
-; GFX11-NEXT:  v_mov_b32_e32 v12, v0
-; GFX11-NEXT:  v_mov_b32_e32 v13, v0
-; GFX11-NEXT:  v_mov_b32_e32 v14, v0
-; GFX11-NEXT:  v_mov_b32_e32 v15, v0
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX10-NEXT:    v_mov_b32_e32 v1, v0
+; GFX10-NEXT:    v_mov_b32_e32 v2, v0
+; GFX10-NEXT:    v_mov_b32_e32 v3, v0
+; GFX10-NEXT:    v_mov_b32_e32 v4, v0
+; GFX10-NEXT:    v_mov_b32_e32 v5, v0
+; GFX10-NEXT:    v_mov_b32_e32 v6, v0
+; GFX10-NEXT:    v_mov_b32_e32 v7, v0
+; GFX10-NEXT:    v_mov_b32_e32 v8, v0
+; GFX10-NEXT:    v_mov_b32_e32 v9, v0
+; GFX10-NEXT:    v_mov_b32_e32 v10, v0
+; GFX10-NEXT:    v_mov_b32_e32 v11, v0
+; GFX10-NEXT:    v_mov_b32_e32 v12, v0
+; GFX10-NEXT:    v_mov_b32_e32 v13, v0
+; GFX10-NEXT:    v_mov_b32_e32 v14, v0
+; GFX10-NEXT:    v_mov_b32_e32 v15, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: shuffle_v32i16_rebroadcast:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v4, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v5, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v6, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v7, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v8, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v9, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v10, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v11, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v12, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v13, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v14, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v15, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v32i16_rebroadcast:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v6, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v7, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v10, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v11, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v12, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v13, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v14, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v15, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <32 x i16>, ptr addrspace(1) %arg0
   %val1 = shufflevector <32 x i16> %val0, <32 x i16> poison, <32 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -568,27 +753,27 @@ entry:
 define <2 x i32> @shuffle_v2i32_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v2i32_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v0, v[0:1], off offset:4
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_mov_b32_e32 v1, v0
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v[0:1], off offset:4
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v1, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v2i32_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v0, v[0:1], off offset:4
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_mov_b32_e32 v1, v0
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v[0:1], off offset:4
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_mov_b32_e32 v1, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-LABEL: shuffle_v2i32_rebroadcast:
 ; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_mov_b32_e32 v1, v0
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <2 x i32>, ptr addrspace(1) %arg0
   %val1 = shufflevector <2 x i32> %val0, <2 x i32> poison, <2 x i32> <i32 1, i32 1>
@@ -598,33 +783,33 @@ entry:
 define <4 x i32> @shuffle_v4i32_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v4i32_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v0, v[0:1], off offset:4
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_mov_b32_e32 v1, v0
-; GFX9-NEXT:  v_mov_b32_e32 v2, v0
-; GFX9-NEXT:  v_mov_b32_e32 v3, v0
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v[0:1], off offset:4
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v1, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, v0
+; GFX9-NEXT:    v_mov_b32_e32 v3, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v4i32_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v0, v[0:1], off offset:4
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_mov_b32_e32 v1, v0
-; GFX10-NEXT:  v_mov_b32_e32 v2, v0
-; GFX10-NEXT:  v_mov_b32_e32 v3, v0
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v[0:1], off offset:4
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_mov_b32_e32 v1, v0
+; GFX10-NEXT:    v_mov_b32_e32 v2, v0
+; GFX10-NEXT:    v_mov_b32_e32 v3, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-LABEL: shuffle_v4i32_rebroadcast:
 ; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_mov_b32_e32 v1, v0
-; GFX11-NEXT:  v_mov_b32_e32 v2, v0
-; GFX11-NEXT:  v_mov_b32_e32 v3, v0
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <4 x i32>, ptr addrspace(1) %arg0
   %val1 = shufflevector <4 x i32> %val0, <4 x i32> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
@@ -634,45 +819,45 @@ entry:
 define <8 x i32> @shuffle_v8i32_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v8i32_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v0, v[0:1], off offset:4
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_mov_b32_e32 v1, v0
-; GFX9-NEXT:  v_mov_b32_e32 v2, v0
-; GFX9-NEXT:  v_mov_b32_e32 v3, v0
-; GFX9-NEXT:  v_mov_b32_e32 v4, v0
-; GFX9-NEXT:  v_mov_b32_e32 v5, v0
-; GFX9-NEXT:  v_mov_b32_e32 v6, v0
-; GFX9-NEXT:  v_mov_b32_e32 v7, v0
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v[0:1], off offset:4
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v1, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, v0
+; GFX9-NEXT:    v_mov_b32_e32 v3, v0
+; GFX9-NEXT:    v_mov_b32_e32 v4, v0
+; GFX9-NEXT:    v_mov_b32_e32 v5, v0
+; GFX9-NEXT:    v_mov_b32_e32 v6, v0
+; GFX9-NEXT:    v_mov_b32_e32 v7, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v8i32_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v0, v[0:1], off offset:4
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_mov_b32_e32 v1, v0
-; GFX10-NEXT:  v_mov_b32_e32 v2, v0
-; GFX10-NEXT:  v_mov_b32_e32 v3, v0
-; GFX10-NEXT:  v_mov_b32_e32 v4, v0
-; GFX10-NEXT:  v_mov_b32_e32 v5, v0
-; GFX10-NEXT:  v_mov_b32_e32 v6, v0
-; GFX10-NEXT:  v_mov_b32_e32 v7, v0
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v[0:1], off offset:4
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_mov_b32_e32 v1, v0
+; GFX10-NEXT:    v_mov_b32_e32 v2, v0
+; GFX10-NEXT:    v_mov_b32_e32 v3, v0
+; GFX10-NEXT:    v_mov_b32_e32 v4, v0
+; GFX10-NEXT:    v_mov_b32_e32 v5, v0
+; GFX10-NEXT:    v_mov_b32_e32 v6, v0
+; GFX10-NEXT:    v_mov_b32_e32 v7, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-LABEL: shuffle_v8i32_rebroadcast:
 ; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_mov_b32_e32 v1, v0
-; GFX11-NEXT:  v_mov_b32_e32 v2, v0
-; GFX11-NEXT:  v_mov_b32_e32 v3, v0
-; GFX11-NEXT:  v_mov_b32_e32 v4, v0
-; GFX11-NEXT:  v_mov_b32_e32 v5, v0
-; GFX11-NEXT:  v_mov_b32_e32 v6, v0
-; GFX11-NEXT:  v_mov_b32_e32 v7, v0
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-NEXT:    v_mov_b32_e32 v4, v0
+; GFX11-NEXT:    v_mov_b32_e32 v5, v0
+; GFX11-NEXT:    v_mov_b32_e32 v6, v0
+; GFX11-NEXT:    v_mov_b32_e32 v7, v0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <8 x i32>, ptr addrspace(1) %arg0
   %val1 = shufflevector <8 x i32> %val0, <8 x i32> poison, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -682,69 +867,69 @@ entry:
 define <16 x i32> @shuffle_v16i32_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v16i32_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v0, v[0:1], off offset:4
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_mov_b32_e32 v1, v0
-; GFX9-NEXT:  v_mov_b32_e32 v2, v0
-; GFX9-NEXT:  v_mov_b32_e32 v3, v0
-; GFX9-NEXT:  v_mov_b32_e32 v4, v0
-; GFX9-NEXT:  v_mov_b32_e32 v5, v0
-; GFX9-NEXT:  v_mov_b32_e32 v6, v0
-; GFX9-NEXT:  v_mov_b32_e32 v7, v0
-; GFX9-NEXT:  v_mov_b32_e32 v8, v0
-; GFX9-NEXT:  v_mov_b32_e32 v9, v0
-; GFX9-NEXT:  v_mov_b32_e32 v10, v0
-; GFX9-NEXT:  v_mov_b32_e32 v11, v0
-; GFX9-NEXT:  v_mov_b32_e32 v12, v0
-; GFX9-NEXT:  v_mov_b32_e32 v13, v0
-; GFX9-NEXT:  v_mov_b32_e32 v14, v0
-; GFX9-NEXT:  v_mov_b32_e32 v15, v0
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v[0:1], off offset:4
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v1, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, v0
+; GFX9-NEXT:    v_mov_b32_e32 v3, v0
+; GFX9-NEXT:    v_mov_b32_e32 v4, v0
+; GFX9-NEXT:    v_mov_b32_e32 v5, v0
+; GFX9-NEXT:    v_mov_b32_e32 v6, v0
+; GFX9-NEXT:    v_mov_b32_e32 v7, v0
+; GFX9-NEXT:    v_mov_b32_e32 v8, v0
+; GFX9-NEXT:    v_mov_b32_e32 v9, v0
+; GFX9-NEXT:    v_mov_b32_e32 v10, v0
+; GFX9-NEXT:    v_mov_b32_e32 v11, v0
+; GFX9-NEXT:    v_mov_b32_e32 v12, v0
+; GFX9-NEXT:    v_mov_b32_e32 v13, v0
+; GFX9-NEXT:    v_mov_b32_e32 v14, v0
+; GFX9-NEXT:    v_mov_b32_e32 v15, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v16i32_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v0, v[0:1], off offset:4
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_mov_b32_e32 v1, v0
-; GFX10-NEXT:  v_mov_b32_e32 v2, v0
-; GFX10-NEXT:  v_mov_b32_e32 v3, v0
-; GFX10-NEXT:  v_mov_b32_e32 v4, v0
-; GFX10-NEXT:  v_mov_b32_e32 v5, v0
-; GFX10-NEXT:  v_mov_b32_e32 v6, v0
-; GFX10-NEXT:  v_mov_b32_e32 v7, v0
-; GFX10-NEXT:  v_mov_b32_e32 v8, v0
-; GFX10-NEXT:  v_mov_b32_e32 v9, v0
-; GFX10-NEXT:  v_mov_b32_e32 v10, v0
-; GFX10-NEXT:  v_mov_b32_e32 v11, v0
-; GFX10-NEXT:  v_mov_b32_e32 v12, v0
-; GFX10-NEXT:  v_mov_b32_e32 v13, v0
-; GFX10-NEXT:  v_mov_b32_e32 v14, v0
-; GFX10-NEXT:  v_mov_b32_e32 v15, v0
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v[0:1], off offset:4
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_mov_b32_e32 v1, v0
+; GFX10-NEXT:    v_mov_b32_e32 v2, v0
+; GFX10-NEXT:    v_mov_b32_e32 v3, v0
+; GFX10-NEXT:    v_mov_b32_e32 v4, v0
+; GFX10-NEXT:    v_mov_b32_e32 v5, v0
+; GFX10-NEXT:    v_mov_b32_e32 v6, v0
+; GFX10-NEXT:    v_mov_b32_e32 v7, v0
+; GFX10-NEXT:    v_mov_b32_e32 v8, v0
+; GFX10-NEXT:    v_mov_b32_e32 v9, v0
+; GFX10-NEXT:    v_mov_b32_e32 v10, v0
+; GFX10-NEXT:    v_mov_b32_e32 v11, v0
+; GFX10-NEXT:    v_mov_b32_e32 v12, v0
+; GFX10-NEXT:    v_mov_b32_e32 v13, v0
+; GFX10-NEXT:    v_mov_b32_e32 v14, v0
+; GFX10-NEXT:    v_mov_b32_e32 v15, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-LABEL: shuffle_v16i32_rebroadcast:
 ; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_mov_b32_e32 v1, v0
-; GFX11-NEXT:  v_mov_b32_e32 v2, v0
-; GFX11-NEXT:  v_mov_b32_e32 v3, v0
-; GFX11-NEXT:  v_mov_b32_e32 v4, v0
-; GFX11-NEXT:  v_mov_b32_e32 v5, v0
-; GFX11-NEXT:  v_mov_b32_e32 v6, v0
-; GFX11-NEXT:  v_mov_b32_e32 v7, v0
-; GFX11-NEXT:  v_mov_b32_e32 v8, v0
-; GFX11-NEXT:  v_mov_b32_e32 v9, v0
-; GFX11-NEXT:  v_mov_b32_e32 v10, v0
-; GFX11-NEXT:  v_mov_b32_e32 v11, v0
-; GFX11-NEXT:  v_mov_b32_e32 v12, v0
-; GFX11-NEXT:  v_mov_b32_e32 v13, v0
-; GFX11-NEXT:  v_mov_b32_e32 v14, v0
-; GFX11-NEXT:  v_mov_b32_e32 v15, v0
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-NEXT:    v_mov_b32_e32 v4, v0
+; GFX11-NEXT:    v_mov_b32_e32 v5, v0
+; GFX11-NEXT:    v_mov_b32_e32 v6, v0
+; GFX11-NEXT:    v_mov_b32_e32 v7, v0
+; GFX11-NEXT:    v_mov_b32_e32 v8, v0
+; GFX11-NEXT:    v_mov_b32_e32 v9, v0
+; GFX11-NEXT:    v_mov_b32_e32 v10, v0
+; GFX11-NEXT:    v_mov_b32_e32 v11, v0
+; GFX11-NEXT:    v_mov_b32_e32 v12, v0
+; GFX11-NEXT:    v_mov_b32_e32 v13, v0
+; GFX11-NEXT:    v_mov_b32_e32 v14, v0
+; GFX11-NEXT:    v_mov_b32_e32 v15, v0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <16 x i32>, ptr addrspace(1) %arg0
   %val1 = shufflevector <16 x i32> %val0, <16 x i32> poison, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -754,117 +939,117 @@ entry:
 define <32 x i32> @shuffle_v32i32_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v32i32_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v0, v[0:1], off offset:4
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_mov_b32_e32 v1, v0
-; GFX9-NEXT:  v_mov_b32_e32 v2, v0
-; GFX9-NEXT:  v_mov_b32_e32 v3, v0
-; GFX9-NEXT:  v_mov_b32_e32 v4, v0
-; GFX9-NEXT:  v_mov_b32_e32 v5, v0
-; GFX9-NEXT:  v_mov_b32_e32 v6, v0
-; GFX9-NEXT:  v_mov_b32_e32 v7, v0
-; GFX9-NEXT:  v_mov_b32_e32 v8, v0
-; GFX9-NEXT:  v_mov_b32_e32 v9, v0
-; GFX9-NEXT:  v_mov_b32_e32 v10, v0
-; GFX9-NEXT:  v_mov_b32_e32 v11, v0
-; GFX9-NEXT:  v_mov_b32_e32 v12, v0
-; GFX9-NEXT:  v_mov_b32_e32 v13, v0
-; GFX9-NEXT:  v_mov_b32_e32 v14, v0
-; GFX9-NEXT:  v_mov_b32_e32 v15, v0
-; GFX9-NEXT:  v_mov_b32_e32 v16, v0
-; GFX9-NEXT:  v_mov_b32_e32 v17, v0
-; GFX9-NEXT:  v_mov_b32_e32 v18, v0
-; GFX9-NEXT:  v_mov_b32_e32 v19, v0
-; GFX9-NEXT:  v_mov_b32_e32 v20, v0
-; GFX9-NEXT:  v_mov_b32_e32 v21, v0
-; GFX9-NEXT:  v_mov_b32_e32 v22, v0
-; GFX9-NEXT:  v_mov_b32_e32 v23, v0
-; GFX9-NEXT:  v_mov_b32_e32 v24, v0
-; GFX9-NEXT:  v_mov_b32_e32 v25, v0
-; GFX9-NEXT:  v_mov_b32_e32 v26, v0
-; GFX9-NEXT:  v_mov_b32_e32 v27, v0
-; GFX9-NEXT:  v_mov_b32_e32 v28, v0
-; GFX9-NEXT:  v_mov_b32_e32 v29, v0
-; GFX9-NEXT:  v_mov_b32_e32 v30, v0
-; GFX9-NEXT:  v_mov_b32_e32 v31, v0
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v[0:1], off offset:4
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v1, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, v0
+; GFX9-NEXT:    v_mov_b32_e32 v3, v0
+; GFX9-NEXT:    v_mov_b32_e32 v4, v0
+; GFX9-NEXT:    v_mov_b32_e32 v5, v0
+; GFX9-NEXT:    v_mov_b32_e32 v6, v0
+; GFX9-NEXT:    v_mov_b32_e32 v7, v0
+; GFX9-NEXT:    v_mov_b32_e32 v8, v0
+; GFX9-NEXT:    v_mov_b32_e32 v9, v0
+; GFX9-NEXT:    v_mov_b32_e32 v10, v0
+; GFX9-NEXT:    v_mov_b32_e32 v11, v0
+; GFX9-NEXT:    v_mov_b32_e32 v12, v0
+; GFX9-NEXT:    v_mov_b32_e32 v13, v0
+; GFX9-NEXT:    v_mov_b32_e32 v14, v0
+; GFX9-NEXT:    v_mov_b32_e32 v15, v0
+; GFX9-NEXT:    v_mov_b32_e32 v16, v0
+; GFX9-NEXT:    v_mov_b32_e32 v17, v0
+; GFX9-NEXT:    v_mov_b32_e32 v18, v0
+; GFX9-NEXT:    v_mov_b32_e32 v19, v0
+; GFX9-NEXT:    v_mov_b32_e32 v20, v0
+; GFX9-NEXT:    v_mov_b32_e32 v21, v0
+; GFX9-NEXT:    v_mov_b32_e32 v22, v0
+; GFX9-NEXT:    v_mov_b32_e32 v23, v0
+; GFX9-NEXT:    v_mov_b32_e32 v24, v0
+; GFX9-NEXT:    v_mov_b32_e32 v25, v0
+; GFX9-NEXT:    v_mov_b32_e32 v26, v0
+; GFX9-NEXT:    v_mov_b32_e32 v27, v0
+; GFX9-NEXT:    v_mov_b32_e32 v28, v0
+; GFX9-NEXT:    v_mov_b32_e32 v29, v0
+; GFX9-NEXT:    v_mov_b32_e32 v30, v0
+; GFX9-NEXT:    v_mov_b32_e32 v31, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v32i32_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v0, v[0:1], off offset:4
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_mov_b32_e32 v1, v0
-; GFX10-NEXT:  v_mov_b32_e32 v2, v0
-; GFX10-NEXT:  v_mov_b32_e32 v3, v0
-; GFX10-NEXT:  v_mov_b32_e32 v4, v0
-; GFX10-NEXT:  v_mov_b32_e32 v5, v0
-; GFX10-NEXT:  v_mov_b32_e32 v6, v0
-; GFX10-NEXT:  v_mov_b32_e32 v7, v0
-; GFX10-NEXT:  v_mov_b32_e32 v8, v0
-; GFX10-NEXT:  v_mov_b32_e32 v9, v0
-; GFX10-NEXT:  v_mov_b32_e32 v10, v0
-; GFX10-NEXT:  v_mov_b32_e32 v11, v0
-; GFX10-NEXT:  v_mov_b32_e32 v12, v0
-; GFX10-NEXT:  v_mov_b32_e32 v13, v0
-; GFX10-NEXT:  v_mov_b32_e32 v14, v0
-; GFX10-NEXT:  v_mov_b32_e32 v15, v0
-; GFX10-NEXT:  v_mov_b32_e32 v16, v0
-; GFX10-NEXT:  v_mov_b32_e32 v17, v0
-; GFX10-NEXT:  v_mov_b32_e32 v18, v0
-; GFX10-NEXT:  v_mov_b32_e32 v19, v0
-; GFX10-NEXT:  v_mov_b32_e32 v20, v0
-; GFX10-NEXT:  v_mov_b32_e32 v21, v0
-; GFX10-NEXT:  v_mov_b32_e32 v22, v0
-; GFX10-NEXT:  v_mov_b32_e32 v23, v0
-; GFX10-NEXT:  v_mov_b32_e32 v24, v0
-; GFX10-NEXT:  v_mov_b32_e32 v25, v0
-; GFX10-NEXT:  v_mov_b32_e32 v26, v0
-; GFX10-NEXT:  v_mov_b32_e32 v27, v0
-; GFX10-NEXT:  v_mov_b32_e32 v28, v0
-; GFX10-NEXT:  v_mov_b32_e32 v29, v0
-; GFX10-NEXT:  v_mov_b32_e32 v30, v0
-; GFX10-NEXT:  v_mov_b32_e32 v31, v0
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v[0:1], off offset:4
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_mov_b32_e32 v1, v0
+; GFX10-NEXT:    v_mov_b32_e32 v2, v0
+; GFX10-NEXT:    v_mov_b32_e32 v3, v0
+; GFX10-NEXT:    v_mov_b32_e32 v4, v0
+; GFX10-NEXT:    v_mov_b32_e32 v5, v0
+; GFX10-NEXT:    v_mov_b32_e32 v6, v0
+; GFX10-NEXT:    v_mov_b32_e32 v7, v0
+; GFX10-NEXT:    v_mov_b32_e32 v8, v0
+; GFX10-NEXT:    v_mov_b32_e32 v9, v0
+; GFX10-NEXT:    v_mov_b32_e32 v10, v0
+; GFX10-NEXT:    v_mov_b32_e32 v11, v0
+; GFX10-NEXT:    v_mov_b32_e32 v12, v0
+; GFX10-NEXT:    v_mov_b32_e32 v13, v0
+; GFX10-NEXT:    v_mov_b32_e32 v14, v0
+; GFX10-NEXT:    v_mov_b32_e32 v15, v0
+; GFX10-NEXT:    v_mov_b32_e32 v16, v0
+; GFX10-NEXT:    v_mov_b32_e32 v17, v0
+; GFX10-NEXT:    v_mov_b32_e32 v18, v0
+; GFX10-NEXT:    v_mov_b32_e32 v19, v0
+; GFX10-NEXT:    v_mov_b32_e32 v20, v0
+; GFX10-NEXT:    v_mov_b32_e32 v21, v0
+; GFX10-NEXT:    v_mov_b32_e32 v22, v0
+; GFX10-NEXT:    v_mov_b32_e32 v23, v0
+; GFX10-NEXT:    v_mov_b32_e32 v24, v0
+; GFX10-NEXT:    v_mov_b32_e32 v25, v0
+; GFX10-NEXT:    v_mov_b32_e32 v26, v0
+; GFX10-NEXT:    v_mov_b32_e32 v27, v0
+; GFX10-NEXT:    v_mov_b32_e32 v28, v0
+; GFX10-NEXT:    v_mov_b32_e32 v29, v0
+; GFX10-NEXT:    v_mov_b32_e32 v30, v0
+; GFX10-NEXT:    v_mov_b32_e32 v31, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-LABEL: shuffle_v32i32_rebroadcast:
 ; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_mov_b32_e32 v1, v0
-; GFX11-NEXT:  v_mov_b32_e32 v2, v0
-; GFX11-NEXT:  v_mov_b32_e32 v3, v0
-; GFX11-NEXT:  v_mov_b32_e32 v4, v0
-; GFX11-NEXT:  v_mov_b32_e32 v5, v0
-; GFX11-NEXT:  v_mov_b32_e32 v6, v0
-; GFX11-NEXT:  v_mov_b32_e32 v7, v0
-; GFX11-NEXT:  v_mov_b32_e32 v8, v0
-; GFX11-NEXT:  v_mov_b32_e32 v9, v0
-; GFX11-NEXT:  v_mov_b32_e32 v10, v0
-; GFX11-NEXT:  v_mov_b32_e32 v11, v0
-; GFX11-NEXT:  v_mov_b32_e32 v12, v0
-; GFX11-NEXT:  v_mov_b32_e32 v13, v0
-; GFX11-NEXT:  v_mov_b32_e32 v14, v0
-; GFX11-NEXT:  v_mov_b32_e32 v15, v0
-; GFX11-NEXT:  v_mov_b32_e32 v16, v0
-; GFX11-NEXT:  v_mov_b32_e32 v17, v0
-; GFX11-NEXT:  v_mov_b32_e32 v18, v0
-; GFX11-NEXT:  v_mov_b32_e32 v19, v0
-; GFX11-NEXT:  v_mov_b32_e32 v20, v0
-; GFX11-NEXT:  v_mov_b32_e32 v21, v0
-; GFX11-NEXT:  v_mov_b32_e32 v22, v0
-; GFX11-NEXT:  v_mov_b32_e32 v23, v0
-; GFX11-NEXT:  v_mov_b32_e32 v24, v0
-; GFX11-NEXT:  v_mov_b32_e32 v25, v0
-; GFX11-NEXT:  v_mov_b32_e32 v26, v0
-; GFX11-NEXT:  v_mov_b32_e32 v27, v0
-; GFX11-NEXT:  v_mov_b32_e32 v28, v0
-; GFX11-NEXT:  v_mov_b32_e32 v29, v0
-; GFX11-NEXT:  v_mov_b32_e32 v30, v0
-; GFX11-NEXT:  v_mov_b32_e32 v31, v0
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-NEXT:    v_mov_b32_e32 v4, v0
+; GFX11-NEXT:    v_mov_b32_e32 v5, v0
+; GFX11-NEXT:    v_mov_b32_e32 v6, v0
+; GFX11-NEXT:    v_mov_b32_e32 v7, v0
+; GFX11-NEXT:    v_mov_b32_e32 v8, v0
+; GFX11-NEXT:    v_mov_b32_e32 v9, v0
+; GFX11-NEXT:    v_mov_b32_e32 v10, v0
+; GFX11-NEXT:    v_mov_b32_e32 v11, v0
+; GFX11-NEXT:    v_mov_b32_e32 v12, v0
+; GFX11-NEXT:    v_mov_b32_e32 v13, v0
+; GFX11-NEXT:    v_mov_b32_e32 v14, v0
+; GFX11-NEXT:    v_mov_b32_e32 v15, v0
+; GFX11-NEXT:    v_mov_b32_e32 v16, v0
+; GFX11-NEXT:    v_mov_b32_e32 v17, v0
+; GFX11-NEXT:    v_mov_b32_e32 v18, v0
+; GFX11-NEXT:    v_mov_b32_e32 v19, v0
+; GFX11-NEXT:    v_mov_b32_e32 v20, v0
+; GFX11-NEXT:    v_mov_b32_e32 v21, v0
+; GFX11-NEXT:    v_mov_b32_e32 v22, v0
+; GFX11-NEXT:    v_mov_b32_e32 v23, v0
+; GFX11-NEXT:    v_mov_b32_e32 v24, v0
+; GFX11-NEXT:    v_mov_b32_e32 v25, v0
+; GFX11-NEXT:    v_mov_b32_e32 v26, v0
+; GFX11-NEXT:    v_mov_b32_e32 v27, v0
+; GFX11-NEXT:    v_mov_b32_e32 v28, v0
+; GFX11-NEXT:    v_mov_b32_e32 v29, v0
+; GFX11-NEXT:    v_mov_b32_e32 v30, v0
+; GFX11-NEXT:    v_mov_b32_e32 v31, v0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <32 x i32>, ptr addrspace(1) %arg0
   %val1 = shufflevector <32 x i32> %val0, <32 x i32> poison, <32 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -874,28 +1059,38 @@ entry:
 define <2 x bfloat> @shuffle_v2bf16_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v2bf16_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v0, v[0:1], off
-; GFX9-NEXT:  s_mov_b32 s4, 0x7060302
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_perm_b32 v0, v0, v0, s4
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v[0:1], off
+; GFX9-NEXT:    s_mov_b32 s4, 0x7060302
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_perm_b32 v0, v0, v0, s4
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v2bf16_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v0, v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: shuffle_v2bf16_rebroadcast:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: shuffle_v2bf16_rebroadcast:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v1, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v2bf16_rebroadcast:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <2 x bfloat>, ptr addrspace(1) %arg0
   %val1 = shufflevector <2 x bfloat> %val0, <2 x bfloat> poison, <2 x i32> <i32 1, i32 1>
@@ -905,31 +1100,42 @@ entry:
 define <3 x bfloat> @shuffle_v3bf16_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v3bf16_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v1, v[0:1], off
-; GFX9-NEXT:  s_mov_b32 s4, 0x7060302
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_perm_b32 v0, v1, v1, s4
-; GFX9-NEXT:  v_alignbit_b32 v1, s4, v1, 16
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v1, v[0:1], off
+; GFX9-NEXT:    s_mov_b32 s4, 0x7060302
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_perm_b32 v0, v1, v1, s4
+; GFX9-NEXT:    v_alignbit_b32 v1, s4, v1, 16
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v3bf16_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v1, v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_perm_b32 v0, v1, v1, 0x7060302
-; GFX10-NEXT:  v_alignbit_b32 v1, s4, v1, 16
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: shuffle_v3bf16_rebroadcast:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v1, v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_perm_b32 v0, v1, v1, 0x7060302
-; GFX11-NEXT:  v_alignbit_b32 v1, s0, v1, 16
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v1, v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_perm_b32 v0, v1, v1, 0x7060302
+; GFX10-NEXT:    v_alignbit_b32 v1, s4, v1, 16
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: shuffle_v3bf16_rebroadcast:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v1, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v0, v1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v3bf16_rebroadcast:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v1, 0x7060302
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v1, s0, v1, 16
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <3 x bfloat>, ptr addrspace(1) %arg0
   %val1 = shufflevector <3 x bfloat> %val0, <3 x bfloat> poison, <3 x i32> <i32 1, i32 1, i32 1>
@@ -939,32 +1145,43 @@ entry:
 define <4 x bfloat> @shuffle_v4bf16_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v4bf16_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v0, v[0:1], off
-; GFX9-NEXT:  s_mov_b32 s4, 0x7060302
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_perm_b32 v0, v0, v0, s4
-; GFX9-NEXT:  v_mov_b32_e32 v1, v0
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v[0:1], off
+; GFX9-NEXT:    s_mov_b32 s4, 0x7060302
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_perm_b32 v0, v0, v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v1, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v4bf16_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v0, v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX10-NEXT:  v_mov_b32_e32 v1, v0
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: shuffle_v4bf16_rebroadcast:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX11-NEXT:  s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:  v_mov_b32_e32 v1, v0
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX10-NEXT:    v_mov_b32_e32 v1, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: shuffle_v4bf16_rebroadcast:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v1, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4bf16_rebroadcast:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
   %val1 = shufflevector <4 x bfloat> %val0, <4 x bfloat> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
@@ -974,35 +1191,47 @@ entry:
 define <6 x bfloat> @shuffle_v6bf16_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v6bf16_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v0, v[0:1], off
-; GFX9-NEXT:  s_mov_b32 s4, 0x7060302
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_perm_b32 v0, v0, v0, s4
-; GFX9-NEXT:  v_mov_b32_e32 v1, v0
-; GFX9-NEXT:  v_mov_b32_e32 v2, v0
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v[0:1], off
+; GFX9-NEXT:    s_mov_b32 s4, 0x7060302
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_perm_b32 v0, v0, v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v1, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v6bf16_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v0, v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX10-NEXT:  v_mov_b32_e32 v1, v0
-; GFX10-NEXT:  v_mov_b32_e32 v2, v0
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: shuffle_v6bf16_rebroadcast:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX11-NEXT:  s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:  v_mov_b32_e32 v1, v0
-; GFX11-NEXT:  v_mov_b32_e32 v2, v0
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX10-NEXT:    v_mov_b32_e32 v1, v0
+; GFX10-NEXT:    v_mov_b32_e32 v2, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: shuffle_v6bf16_rebroadcast:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v1, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v6bf16_rebroadcast:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <6 x bfloat>, ptr addrspace(1) %arg0
   %val1 = shufflevector <6 x bfloat> %val0, <6 x bfloat> poison, <6 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -1012,38 +1241,51 @@ entry:
 define <8 x bfloat> @shuffle_v8bf16_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v8bf16_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v0, v[0:1], off
-; GFX9-NEXT:  s_mov_b32 s4, 0x7060302
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_perm_b32 v0, v0, v0, s4
-; GFX9-NEXT:  v_mov_b32_e32 v1, v0
-; GFX9-NEXT:  v_mov_b32_e32 v2, v0
-; GFX9-NEXT:  v_mov_b32_e32 v3, v0
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v[0:1], off
+; GFX9-NEXT:    s_mov_b32 s4, 0x7060302
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_perm_b32 v0, v0, v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v1, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, v0
+; GFX9-NEXT:    v_mov_b32_e32 v3, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v8bf16_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v0, v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX10-NEXT:  v_mov_b32_e32 v1, v0
-; GFX10-NEXT:  v_mov_b32_e32 v2, v0
-; GFX10-NEXT:  v_mov_b32_e32 v3, v0
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: shuffle_v8bf16_rebroadcast:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX11-NEXT:  s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:  v_mov_b32_e32 v1, v0
-; GFX11-NEXT:  v_mov_b32_e32 v2, v0
-; GFX11-NEXT:  v_mov_b32_e32 v3, v0
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX10-NEXT:    v_mov_b32_e32 v1, v0
+; GFX10-NEXT:    v_mov_b32_e32 v2, v0
+; GFX10-NEXT:    v_mov_b32_e32 v3, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: shuffle_v8bf16_rebroadcast:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v1, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v8bf16_rebroadcast:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <8 x bfloat>, ptr addrspace(1) %arg0
   %val1 = shufflevector <8 x bfloat> %val0, <8 x bfloat> poison, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -1053,50 +1295,67 @@ entry:
 define <16 x bfloat> @shuffle_v16bf16_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v16bf16_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v0, v[0:1], off
-; GFX9-NEXT:  s_mov_b32 s4, 0x7060302
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_perm_b32 v0, v0, v0, s4
-; GFX9-NEXT:  v_mov_b32_e32 v1, v0
-; GFX9-NEXT:  v_mov_b32_e32 v2, v0
-; GFX9-NEXT:  v_mov_b32_e32 v3, v0
-; GFX9-NEXT:  v_mov_b32_e32 v4, v0
-; GFX9-NEXT:  v_mov_b32_e32 v5, v0
-; GFX9-NEXT:  v_mov_b32_e32 v6, v0
-; GFX9-NEXT:  v_mov_b32_e32 v7, v0
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v[0:1], off
+; GFX9-NEXT:    s_mov_b32 s4, 0x7060302
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_perm_b32 v0, v0, v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v1, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, v0
+; GFX9-NEXT:    v_mov_b32_e32 v3, v0
+; GFX9-NEXT:    v_mov_b32_e32 v4, v0
+; GFX9-NEXT:    v_mov_b32_e32 v5, v0
+; GFX9-NEXT:    v_mov_b32_e32 v6, v0
+; GFX9-NEXT:    v_mov_b32_e32 v7, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v16bf16_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v0, v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX10-NEXT:  v_mov_b32_e32 v1, v0
-; GFX10-NEXT:  v_mov_b32_e32 v2, v0
-; GFX10-NEXT:  v_mov_b32_e32 v3, v0
-; GFX10-NEXT:  v_mov_b32_e32 v4, v0
-; GFX10-NEXT:  v_mov_b32_e32 v5, v0
-; GFX10-NEXT:  v_mov_b32_e32 v6, v0
-; GFX10-NEXT:  v_mov_b32_e32 v7, v0
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: shuffle_v16bf16_rebroadcast:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX11-NEXT:  s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:  v_mov_b32_e32 v1, v0
-; GFX11-NEXT:  v_mov_b32_e32 v2, v0
-; GFX11-NEXT:  v_mov_b32_e32 v3, v0
-; GFX11-NEXT:  v_mov_b32_e32 v4, v0
-; GFX11-NEXT:  v_mov_b32_e32 v5, v0
-; GFX11-NEXT:  v_mov_b32_e32 v6, v0
-; GFX11-NEXT:  v_mov_b32_e32 v7, v0
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX10-NEXT:    v_mov_b32_e32 v1, v0
+; GFX10-NEXT:    v_mov_b32_e32 v2, v0
+; GFX10-NEXT:    v_mov_b32_e32 v3, v0
+; GFX10-NEXT:    v_mov_b32_e32 v4, v0
+; GFX10-NEXT:    v_mov_b32_e32 v5, v0
+; GFX10-NEXT:    v_mov_b32_e32 v6, v0
+; GFX10-NEXT:    v_mov_b32_e32 v7, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: shuffle_v16bf16_rebroadcast:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v1, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v4, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v5, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v6, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v7, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v16bf16_rebroadcast:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v6, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v7, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <16 x bfloat>, ptr addrspace(1) %arg0
   %val1 = shufflevector <16 x bfloat> %val0, <16 x bfloat> poison, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -1106,74 +1365,99 @@ entry:
 define <32 x bfloat> @shuffle_v32bf16_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v32bf16_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v0, v[0:1], off
-; GFX9-NEXT:  s_mov_b32 s4, 0x7060302
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_perm_b32 v0, v0, v0, s4
-; GFX9-NEXT:  v_mov_b32_e32 v1, v0
-; GFX9-NEXT:  v_mov_b32_e32 v2, v0
-; GFX9-NEXT:  v_mov_b32_e32 v3, v0
-; GFX9-NEXT:  v_mov_b32_e32 v4, v0
-; GFX9-NEXT:  v_mov_b32_e32 v5, v0
-; GFX9-NEXT:  v_mov_b32_e32 v6, v0
-; GFX9-NEXT:  v_mov_b32_e32 v7, v0
-; GFX9-NEXT:  v_mov_b32_e32 v8, v0
-; GFX9-NEXT:  v_mov_b32_e32 v9, v0
-; GFX9-NEXT:  v_mov_b32_e32 v10, v0
-; GFX9-NEXT:  v_mov_b32_e32 v11, v0
-; GFX9-NEXT:  v_mov_b32_e32 v12, v0
-; GFX9-NEXT:  v_mov_b32_e32 v13, v0
-; GFX9-NEXT:  v_mov_b32_e32 v14, v0
-; GFX9-NEXT:  v_mov_b32_e32 v15, v0
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v[0:1], off
+; GFX9-NEXT:    s_mov_b32 s4, 0x7060302
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_perm_b32 v0, v0, v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v1, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, v0
+; GFX9-NEXT:    v_mov_b32_e32 v3, v0
+; GFX9-NEXT:    v_mov_b32_e32 v4, v0
+; GFX9-NEXT:    v_mov_b32_e32 v5, v0
+; GFX9-NEXT:    v_mov_b32_e32 v6, v0
+; GFX9-NEXT:    v_mov_b32_e32 v7, v0
+; GFX9-NEXT:    v_mov_b32_e32 v8, v0
+; GFX9-NEXT:    v_mov_b32_e32 v9, v0
+; GFX9-NEXT:    v_mov_b32_e32 v10, v0
+; GFX9-NEXT:    v_mov_b32_e32 v11, v0
+; GFX9-NEXT:    v_mov_b32_e32 v12, v0
+; GFX9-NEXT:    v_mov_b32_e32 v13, v0
+; GFX9-NEXT:    v_mov_b32_e32 v14, v0
+; GFX9-NEXT:    v_mov_b32_e32 v15, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v32bf16_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v0, v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX10-NEXT:  v_mov_b32_e32 v1, v0
-; GFX10-NEXT:  v_mov_b32_e32 v2, v0
-; GFX10-NEXT:  v_mov_b32_e32 v3, v0
-; GFX10-NEXT:  v_mov_b32_e32 v4, v0
-; GFX10-NEXT:  v_mov_b32_e32 v5, v0
-; GFX10-NEXT:  v_mov_b32_e32 v6, v0
-; GFX10-NEXT:  v_mov_b32_e32 v7, v0
-; GFX10-NEXT:  v_mov_b32_e32 v8, v0
-; GFX10-NEXT:  v_mov_b32_e32 v9, v0
-; GFX10-NEXT:  v_mov_b32_e32 v10, v0
-; GFX10-NEXT:  v_mov_b32_e32 v11, v0
-; GFX10-NEXT:  v_mov_b32_e32 v12, v0
-; GFX10-NEXT:  v_mov_b32_e32 v13, v0
-; GFX10-NEXT:  v_mov_b32_e32 v14, v0
-; GFX10-NEXT:  v_mov_b32_e32 v15, v0
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: shuffle_v32bf16_rebroadcast:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX11-NEXT:  s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:  v_mov_b32_e32 v1, v0
-; GFX11-NEXT:  v_mov_b32_e32 v2, v0
-; GFX11-NEXT:  v_mov_b32_e32 v3, v0
-; GFX11-NEXT:  v_mov_b32_e32 v4, v0
-; GFX11-NEXT:  v_mov_b32_e32 v5, v0
-; GFX11-NEXT:  v_mov_b32_e32 v6, v0
-; GFX11-NEXT:  v_mov_b32_e32 v7, v0
-; GFX11-NEXT:  v_mov_b32_e32 v8, v0
-; GFX11-NEXT:  v_mov_b32_e32 v9, v0
-; GFX11-NEXT:  v_mov_b32_e32 v10, v0
-; GFX11-NEXT:  v_mov_b32_e32 v11, v0
-; GFX11-NEXT:  v_mov_b32_e32 v12, v0
-; GFX11-NEXT:  v_mov_b32_e32 v13, v0
-; GFX11-NEXT:  v_mov_b32_e32 v14, v0
-; GFX11-NEXT:  v_mov_b32_e32 v15, v0
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX10-NEXT:    v_mov_b32_e32 v1, v0
+; GFX10-NEXT:    v_mov_b32_e32 v2, v0
+; GFX10-NEXT:    v_mov_b32_e32 v3, v0
+; GFX10-NEXT:    v_mov_b32_e32 v4, v0
+; GFX10-NEXT:    v_mov_b32_e32 v5, v0
+; GFX10-NEXT:    v_mov_b32_e32 v6, v0
+; GFX10-NEXT:    v_mov_b32_e32 v7, v0
+; GFX10-NEXT:    v_mov_b32_e32 v8, v0
+; GFX10-NEXT:    v_mov_b32_e32 v9, v0
+; GFX10-NEXT:    v_mov_b32_e32 v10, v0
+; GFX10-NEXT:    v_mov_b32_e32 v11, v0
+; GFX10-NEXT:    v_mov_b32_e32 v12, v0
+; GFX10-NEXT:    v_mov_b32_e32 v13, v0
+; GFX10-NEXT:    v_mov_b32_e32 v14, v0
+; GFX10-NEXT:    v_mov_b32_e32 v15, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: shuffle_v32bf16_rebroadcast:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v1, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v4, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v5, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v6, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v7, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v8, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v9, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v10, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v11, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v12, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v13, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v14, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v15, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v32bf16_rebroadcast:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v6, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v7, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v10, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v11, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v12, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v13, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v14, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v15, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <32 x bfloat>, ptr addrspace(1) %arg0
   %val1 = shufflevector <32 x bfloat> %val0, <32 x bfloat> poison, <32 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -1183,28 +1467,38 @@ entry:
 define <2 x half> @shuffle_v2f16_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v2f16_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v0, v[0:1], off
-; GFX9-NEXT:  s_mov_b32 s4, 0x7060302
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_perm_b32 v0, v0, v0, s4
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v[0:1], off
+; GFX9-NEXT:    s_mov_b32 s4, 0x7060302
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_perm_b32 v0, v0, v0, s4
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v2f16_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v0, v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: shuffle_v2f16_rebroadcast:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: shuffle_v2f16_rebroadcast:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v1, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v2f16_rebroadcast:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <2 x half>, ptr addrspace(1) %arg0
   %val1 = shufflevector <2 x half> %val0, <2 x half> poison, <2 x i32> <i32 1, i32 1>
@@ -1214,31 +1508,42 @@ entry:
 define <3 x half> @shuffle_v3f16_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v3f16_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v1, v[0:1], off
-; GFX9-NEXT:  s_mov_b32 s4, 0x7060302
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_perm_b32 v0, v1, v1, s4
-; GFX9-NEXT:  v_alignbit_b32 v1, s4, v1, 16
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v1, v[0:1], off
+; GFX9-NEXT:    s_mov_b32 s4, 0x7060302
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_perm_b32 v0, v1, v1, s4
+; GFX9-NEXT:    v_alignbit_b32 v1, s4, v1, 16
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v3f16_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v1, v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_perm_b32 v0, v1, v1, 0x7060302
-; GFX10-NEXT:  v_alignbit_b32 v1, s4, v1, 16
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: shuffle_v3f16_rebroadcast:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v1, v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_perm_b32 v0, v1, v1, 0x7060302
-; GFX11-NEXT:  v_alignbit_b32 v1, s0, v1, 16
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v1, v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_perm_b32 v0, v1, v1, 0x7060302
+; GFX10-NEXT:    v_alignbit_b32 v1, s4, v1, 16
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: shuffle_v3f16_rebroadcast:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v1, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v0, v1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v3f16_rebroadcast:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v1, 0x7060302
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v1, s0, v1, 16
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <3 x half>, ptr addrspace(1) %arg0
   %val1 = shufflevector <3 x half> %val0, <3 x half> poison, <3 x i32> <i32 1, i32 1, i32 1>
@@ -1248,32 +1553,43 @@ entry:
 define <4 x half> @shuffle_v4f16_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v4f16_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v0, v[0:1], off
-; GFX9-NEXT:  s_mov_b32 s4, 0x7060302
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_perm_b32 v0, v0, v0, s4
-; GFX9-NEXT:  v_mov_b32_e32 v1, v0
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v[0:1], off
+; GFX9-NEXT:    s_mov_b32 s4, 0x7060302
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_perm_b32 v0, v0, v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v1, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v4f16_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v0, v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX10-NEXT:  v_mov_b32_e32 v1, v0
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: shuffle_v4f16_rebroadcast:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX11-NEXT:  s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:  v_mov_b32_e32 v1, v0
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX10-NEXT:    v_mov_b32_e32 v1, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: shuffle_v4f16_rebroadcast:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v1, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4f16_rebroadcast:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <4 x half>, ptr addrspace(1) %arg0
   %val1 = shufflevector <4 x half> %val0, <4 x half> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
@@ -1283,35 +1599,47 @@ entry:
 define <6 x half> @shuffle_v6f16_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v6f16_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v0, v[0:1], off
-; GFX9-NEXT:  s_mov_b32 s4, 0x7060302
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_perm_b32 v0, v0, v0, s4
-; GFX9-NEXT:  v_mov_b32_e32 v1, v0
-; GFX9-NEXT:  v_mov_b32_e32 v2, v0
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v[0:1], off
+; GFX9-NEXT:    s_mov_b32 s4, 0x7060302
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_perm_b32 v0, v0, v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v1, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v6f16_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v0, v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX10-NEXT:  v_mov_b32_e32 v1, v0
-; GFX10-NEXT:  v_mov_b32_e32 v2, v0
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: shuffle_v6f16_rebroadcast:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX11-NEXT:  s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:  v_mov_b32_e32 v1, v0
-; GFX11-NEXT:  v_mov_b32_e32 v2, v0
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX10-NEXT:    v_mov_b32_e32 v1, v0
+; GFX10-NEXT:    v_mov_b32_e32 v2, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: shuffle_v6f16_rebroadcast:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v1, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v6f16_rebroadcast:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <6 x half>, ptr addrspace(1) %arg0
   %val1 = shufflevector <6 x half> %val0, <6 x half> poison, <6 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -1321,38 +1649,51 @@ entry:
 define <8 x half> @shuffle_v8f16_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v8f16_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v0, v[0:1], off
-; GFX9-NEXT:  s_mov_b32 s4, 0x7060302
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_perm_b32 v0, v0, v0, s4
-; GFX9-NEXT:  v_mov_b32_e32 v1, v0
-; GFX9-NEXT:  v_mov_b32_e32 v2, v0
-; GFX9-NEXT:  v_mov_b32_e32 v3, v0
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v[0:1], off
+; GFX9-NEXT:    s_mov_b32 s4, 0x7060302
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_perm_b32 v0, v0, v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v1, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, v0
+; GFX9-NEXT:    v_mov_b32_e32 v3, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v8f16_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v0, v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX10-NEXT:  v_mov_b32_e32 v1, v0
-; GFX10-NEXT:  v_mov_b32_e32 v2, v0
-; GFX10-NEXT:  v_mov_b32_e32 v3, v0
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: shuffle_v8f16_rebroadcast:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX11-NEXT:  s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:  v_mov_b32_e32 v1, v0
-; GFX11-NEXT:  v_mov_b32_e32 v2, v0
-; GFX11-NEXT:  v_mov_b32_e32 v3, v0
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX10-NEXT:    v_mov_b32_e32 v1, v0
+; GFX10-NEXT:    v_mov_b32_e32 v2, v0
+; GFX10-NEXT:    v_mov_b32_e32 v3, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: shuffle_v8f16_rebroadcast:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v1, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v8f16_rebroadcast:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <8 x half>, ptr addrspace(1) %arg0
   %val1 = shufflevector <8 x half> %val0, <8 x half> poison, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -1362,50 +1703,67 @@ entry:
 define <16 x half> @shuffle_v16f16_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v16f16_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v0, v[0:1], off
-; GFX9-NEXT:  s_mov_b32 s4, 0x7060302
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_perm_b32 v0, v0, v0, s4
-; GFX9-NEXT:  v_mov_b32_e32 v1, v0
-; GFX9-NEXT:  v_mov_b32_e32 v2, v0
-; GFX9-NEXT:  v_mov_b32_e32 v3, v0
-; GFX9-NEXT:  v_mov_b32_e32 v4, v0
-; GFX9-NEXT:  v_mov_b32_e32 v5, v0
-; GFX9-NEXT:  v_mov_b32_e32 v6, v0
-; GFX9-NEXT:  v_mov_b32_e32 v7, v0
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v[0:1], off
+; GFX9-NEXT:    s_mov_b32 s4, 0x7060302
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_perm_b32 v0, v0, v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v1, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, v0
+; GFX9-NEXT:    v_mov_b32_e32 v3, v0
+; GFX9-NEXT:    v_mov_b32_e32 v4, v0
+; GFX9-NEXT:    v_mov_b32_e32 v5, v0
+; GFX9-NEXT:    v_mov_b32_e32 v6, v0
+; GFX9-NEXT:    v_mov_b32_e32 v7, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v16f16_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v0, v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX10-NEXT:  v_mov_b32_e32 v1, v0
-; GFX10-NEXT:  v_mov_b32_e32 v2, v0
-; GFX10-NEXT:  v_mov_b32_e32 v3, v0
-; GFX10-NEXT:  v_mov_b32_e32 v4, v0
-; GFX10-NEXT:  v_mov_b32_e32 v5, v0
-; GFX10-NEXT:  v_mov_b32_e32 v6, v0
-; GFX10-NEXT:  v_mov_b32_e32 v7, v0
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: shuffle_v16f16_rebroadcast:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX11-NEXT:  s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:  v_mov_b32_e32 v1, v0
-; GFX11-NEXT:  v_mov_b32_e32 v2, v0
-; GFX11-NEXT:  v_mov_b32_e32 v3, v0
-; GFX11-NEXT:  v_mov_b32_e32 v4, v0
-; GFX11-NEXT:  v_mov_b32_e32 v5, v0
-; GFX11-NEXT:  v_mov_b32_e32 v6, v0
-; GFX11-NEXT:  v_mov_b32_e32 v7, v0
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX10-NEXT:    v_mov_b32_e32 v1, v0
+; GFX10-NEXT:    v_mov_b32_e32 v2, v0
+; GFX10-NEXT:    v_mov_b32_e32 v3, v0
+; GFX10-NEXT:    v_mov_b32_e32 v4, v0
+; GFX10-NEXT:    v_mov_b32_e32 v5, v0
+; GFX10-NEXT:    v_mov_b32_e32 v6, v0
+; GFX10-NEXT:    v_mov_b32_e32 v7, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: shuffle_v16f16_rebroadcast:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v1, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v4, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v5, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v6, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v7, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v16f16_rebroadcast:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v6, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v7, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <16 x half>, ptr addrspace(1) %arg0
   %val1 = shufflevector <16 x half> %val0, <16 x half> poison, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -1415,74 +1773,99 @@ entry:
 define <32 x half> @shuffle_v32f16_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v32f16_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dword v0, v[0:1], off
-; GFX9-NEXT:  s_mov_b32 s4, 0x7060302
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_perm_b32 v0, v0, v0, s4
-; GFX9-NEXT:  v_mov_b32_e32 v1, v0
-; GFX9-NEXT:  v_mov_b32_e32 v2, v0
-; GFX9-NEXT:  v_mov_b32_e32 v3, v0
-; GFX9-NEXT:  v_mov_b32_e32 v4, v0
-; GFX9-NEXT:  v_mov_b32_e32 v5, v0
-; GFX9-NEXT:  v_mov_b32_e32 v6, v0
-; GFX9-NEXT:  v_mov_b32_e32 v7, v0
-; GFX9-NEXT:  v_mov_b32_e32 v8, v0
-; GFX9-NEXT:  v_mov_b32_e32 v9, v0
-; GFX9-NEXT:  v_mov_b32_e32 v10, v0
-; GFX9-NEXT:  v_mov_b32_e32 v11, v0
-; GFX9-NEXT:  v_mov_b32_e32 v12, v0
-; GFX9-NEXT:  v_mov_b32_e32 v13, v0
-; GFX9-NEXT:  v_mov_b32_e32 v14, v0
-; GFX9-NEXT:  v_mov_b32_e32 v15, v0
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dword v0, v[0:1], off
+; GFX9-NEXT:    s_mov_b32 s4, 0x7060302
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_perm_b32 v0, v0, v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v1, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, v0
+; GFX9-NEXT:    v_mov_b32_e32 v3, v0
+; GFX9-NEXT:    v_mov_b32_e32 v4, v0
+; GFX9-NEXT:    v_mov_b32_e32 v5, v0
+; GFX9-NEXT:    v_mov_b32_e32 v6, v0
+; GFX9-NEXT:    v_mov_b32_e32 v7, v0
+; GFX9-NEXT:    v_mov_b32_e32 v8, v0
+; GFX9-NEXT:    v_mov_b32_e32 v9, v0
+; GFX9-NEXT:    v_mov_b32_e32 v10, v0
+; GFX9-NEXT:    v_mov_b32_e32 v11, v0
+; GFX9-NEXT:    v_mov_b32_e32 v12, v0
+; GFX9-NEXT:    v_mov_b32_e32 v13, v0
+; GFX9-NEXT:    v_mov_b32_e32 v14, v0
+; GFX9-NEXT:    v_mov_b32_e32 v15, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v32f16_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dword v0, v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX10-NEXT:  v_mov_b32_e32 v1, v0
-; GFX10-NEXT:  v_mov_b32_e32 v2, v0
-; GFX10-NEXT:  v_mov_b32_e32 v3, v0
-; GFX10-NEXT:  v_mov_b32_e32 v4, v0
-; GFX10-NEXT:  v_mov_b32_e32 v5, v0
-; GFX10-NEXT:  v_mov_b32_e32 v6, v0
-; GFX10-NEXT:  v_mov_b32_e32 v7, v0
-; GFX10-NEXT:  v_mov_b32_e32 v8, v0
-; GFX10-NEXT:  v_mov_b32_e32 v9, v0
-; GFX10-NEXT:  v_mov_b32_e32 v10, v0
-; GFX10-NEXT:  v_mov_b32_e32 v11, v0
-; GFX10-NEXT:  v_mov_b32_e32 v12, v0
-; GFX10-NEXT:  v_mov_b32_e32 v13, v0
-; GFX10-NEXT:  v_mov_b32_e32 v14, v0
-; GFX10-NEXT:  v_mov_b32_e32 v15, v0
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: shuffle_v32f16_rebroadcast:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_perm_b32 v0, v0, v0, 0x7060302
-; GFX11-NEXT:  s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:  v_mov_b32_e32 v1, v0
-; GFX11-NEXT:  v_mov_b32_e32 v2, v0
-; GFX11-NEXT:  v_mov_b32_e32 v3, v0
-; GFX11-NEXT:  v_mov_b32_e32 v4, v0
-; GFX11-NEXT:  v_mov_b32_e32 v5, v0
-; GFX11-NEXT:  v_mov_b32_e32 v6, v0
-; GFX11-NEXT:  v_mov_b32_e32 v7, v0
-; GFX11-NEXT:  v_mov_b32_e32 v8, v0
-; GFX11-NEXT:  v_mov_b32_e32 v9, v0
-; GFX11-NEXT:  v_mov_b32_e32 v10, v0
-; GFX11-NEXT:  v_mov_b32_e32 v11, v0
-; GFX11-NEXT:  v_mov_b32_e32 v12, v0
-; GFX11-NEXT:  v_mov_b32_e32 v13, v0
-; GFX11-NEXT:  v_mov_b32_e32 v14, v0
-; GFX11-NEXT:  v_mov_b32_e32 v15, v0
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dword v0, v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX10-NEXT:    v_mov_b32_e32 v1, v0
+; GFX10-NEXT:    v_mov_b32_e32 v2, v0
+; GFX10-NEXT:    v_mov_b32_e32 v3, v0
+; GFX10-NEXT:    v_mov_b32_e32 v4, v0
+; GFX10-NEXT:    v_mov_b32_e32 v5, v0
+; GFX10-NEXT:    v_mov_b32_e32 v6, v0
+; GFX10-NEXT:    v_mov_b32_e32 v7, v0
+; GFX10-NEXT:    v_mov_b32_e32 v8, v0
+; GFX10-NEXT:    v_mov_b32_e32 v9, v0
+; GFX10-NEXT:    v_mov_b32_e32 v10, v0
+; GFX10-NEXT:    v_mov_b32_e32 v11, v0
+; GFX10-NEXT:    v_mov_b32_e32 v12, v0
+; GFX10-NEXT:    v_mov_b32_e32 v13, v0
+; GFX10-NEXT:    v_mov_b32_e32 v14, v0
+; GFX10-NEXT:    v_mov_b32_e32 v15, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: shuffle_v32f16_rebroadcast:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v1, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v4, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v5, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v6, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v7, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v8, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v9, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v10, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v11, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v12, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v13, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v14, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v15, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v32f16_rebroadcast:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v6, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v7, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v10, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v11, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v12, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v13, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v14, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v15, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <32 x half>, ptr addrspace(1) %arg0
   %val1 = shufflevector <32 x half> %val0, <32 x half> poison, <32 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -1492,27 +1875,27 @@ entry:
 define <2 x float> @shuffle_v2f32_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v2f32_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dwordx2 v[0:1], v[0:1], off
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_mov_b32_e32 v0, v1
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dwordx2 v[0:1], v[0:1], off
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v0, v1
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v2f32_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dwordx2 v[0:1], v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_mov_b32_e32 v0, v1
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dwordx2 v[0:1], v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_mov_b32_e32 v0, v1
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-LABEL: shuffle_v2f32_rebroadcast:
 ; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b64 v[0:1], v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_mov_b32_e32 v0, v1
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    global_load_b64 v[0:1], v[0:1], off
+; GFX11-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-NEXT:    v_mov_b32_e32 v0, v1
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <2 x float>, ptr addrspace(1) %arg0
   %val1 = shufflevector <2 x float> %val0, <2 x float> poison, <2 x i32> <i32 1, i32 1>
@@ -1522,30 +1905,30 @@ entry:
 define <3 x float> @shuffle_v3f32_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v3f32_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dwordx3 v[0:2], v[0:1], off
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_mov_b32_e32 v0, v1
-; GFX9-NEXT:  v_mov_b32_e32 v2, v1
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dwordx3 v[0:2], v[0:1], off
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v0, v1
+; GFX9-NEXT:    v_mov_b32_e32 v2, v1
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v3f32_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dwordx3 v[0:2], v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_mov_b32_e32 v0, v1
-; GFX10-NEXT:  v_mov_b32_e32 v2, v1
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dwordx3 v[0:2], v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_mov_b32_e32 v0, v1
+; GFX10-NEXT:    v_mov_b32_e32 v2, v1
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-LABEL: shuffle_v3f32_rebroadcast:
 ; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b96 v[0:2], v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_mov_b32_e32 v0, v1
-; GFX11-NEXT:  v_mov_b32_e32 v2, v1
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    global_load_b96 v[0:2], v[0:1], off
+; GFX11-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-NEXT:    v_mov_b32_e32 v0, v1
+; GFX11-NEXT:    v_mov_b32_e32 v2, v1
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <3 x float>, ptr addrspace(1) %arg0
   %val1 = shufflevector <3 x float> %val0, <3 x float> poison, <3 x i32> <i32 1, i32 1, i32 1>
@@ -1555,33 +1938,33 @@ entry:
 define <4 x float> @shuffle_v4f32_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v4f32_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dwordx4 v[0:3], v[0:1], off
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_mov_b32_e32 v0, v1
-; GFX9-NEXT:  v_mov_b32_e32 v2, v1
-; GFX9-NEXT:  v_mov_b32_e32 v3, v1
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dwordx4 v[0:3], v[0:1], off
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v0, v1
+; GFX9-NEXT:    v_mov_b32_e32 v2, v1
+; GFX9-NEXT:    v_mov_b32_e32 v3, v1
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v4f32_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dwordx4 v[0:3], v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_mov_b32_e32 v0, v1
-; GFX10-NEXT:  v_mov_b32_e32 v2, v1
-; GFX10-NEXT:  v_mov_b32_e32 v3, v1
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dwordx4 v[0:3], v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_mov_b32_e32 v0, v1
+; GFX10-NEXT:    v_mov_b32_e32 v2, v1
+; GFX10-NEXT:    v_mov_b32_e32 v3, v1
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-LABEL: shuffle_v4f32_rebroadcast:
 ; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b128 v[0:3], v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_mov_b32_e32 v0, v1
-; GFX11-NEXT:  v_mov_b32_e32 v2, v1
-; GFX11-NEXT:  v_mov_b32_e32 v3, v1
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    global_load_b128 v[0:3], v[0:1], off
+; GFX11-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-NEXT:    v_mov_b32_e32 v0, v1
+; GFX11-NEXT:    v_mov_b32_e32 v2, v1
+; GFX11-NEXT:    v_mov_b32_e32 v3, v1
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <4 x float>, ptr addrspace(1) %arg0
   %val1 = shufflevector <4 x float> %val0, <4 x float> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
@@ -1591,39 +1974,39 @@ entry:
 define <6 x float> @shuffle_v6f32_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v6f32_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dwordx4 v[0:3], v[0:1], off
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_mov_b32_e32 v0, v1
-; GFX9-NEXT:  v_mov_b32_e32 v2, v1
-; GFX9-NEXT:  v_mov_b32_e32 v3, v1
-; GFX9-NEXT:  v_mov_b32_e32 v4, v1
-; GFX9-NEXT:  v_mov_b32_e32 v5, v1
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dwordx4 v[0:3], v[0:1], off
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v0, v1
+; GFX9-NEXT:    v_mov_b32_e32 v2, v1
+; GFX9-NEXT:    v_mov_b32_e32 v3, v1
+; GFX9-NEXT:    v_mov_b32_e32 v4, v1
+; GFX9-NEXT:    v_mov_b32_e32 v5, v1
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v6f32_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dwordx4 v[0:3], v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_mov_b32_e32 v0, v1
-; GFX10-NEXT:  v_mov_b32_e32 v2, v1
-; GFX10-NEXT:  v_mov_b32_e32 v3, v1
-; GFX10-NEXT:  v_mov_b32_e32 v4, v1
-; GFX10-NEXT:  v_mov_b32_e32 v5, v1
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dwordx4 v[0:3], v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_mov_b32_e32 v0, v1
+; GFX10-NEXT:    v_mov_b32_e32 v2, v1
+; GFX10-NEXT:    v_mov_b32_e32 v3, v1
+; GFX10-NEXT:    v_mov_b32_e32 v4, v1
+; GFX10-NEXT:    v_mov_b32_e32 v5, v1
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-LABEL: shuffle_v6f32_rebroadcast:
 ; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b128 v[0:3], v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_mov_b32_e32 v0, v1
-; GFX11-NEXT:  v_mov_b32_e32 v2, v1
-; GFX11-NEXT:  v_mov_b32_e32 v3, v1
-; GFX11-NEXT:  v_mov_b32_e32 v4, v1
-; GFX11-NEXT:  v_mov_b32_e32 v5, v1
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    global_load_b128 v[0:3], v[0:1], off
+; GFX11-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-NEXT:    v_mov_b32_e32 v0, v1
+; GFX11-NEXT:    v_mov_b32_e32 v2, v1
+; GFX11-NEXT:    v_mov_b32_e32 v3, v1
+; GFX11-NEXT:    v_mov_b32_e32 v4, v1
+; GFX11-NEXT:    v_mov_b32_e32 v5, v1
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <6 x float>, ptr addrspace(1) %arg0
   %val1 = shufflevector <6 x float> %val0, <6 x float> poison, <6 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -1633,45 +2016,45 @@ entry:
 define <8 x float> @shuffle_v8f32_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v8f32_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dwordx4 v[0:3], v[0:1], off
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_mov_b32_e32 v0, v1
-; GFX9-NEXT:  v_mov_b32_e32 v2, v1
-; GFX9-NEXT:  v_mov_b32_e32 v3, v1
-; GFX9-NEXT:  v_mov_b32_e32 v4, v1
-; GFX9-NEXT:  v_mov_b32_e32 v5, v1
-; GFX9-NEXT:  v_mov_b32_e32 v6, v1
-; GFX9-NEXT:  v_mov_b32_e32 v7, v1
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dwordx4 v[0:3], v[0:1], off
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v0, v1
+; GFX9-NEXT:    v_mov_b32_e32 v2, v1
+; GFX9-NEXT:    v_mov_b32_e32 v3, v1
+; GFX9-NEXT:    v_mov_b32_e32 v4, v1
+; GFX9-NEXT:    v_mov_b32_e32 v5, v1
+; GFX9-NEXT:    v_mov_b32_e32 v6, v1
+; GFX9-NEXT:    v_mov_b32_e32 v7, v1
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v8f32_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dwordx4 v[0:3], v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_mov_b32_e32 v0, v1
-; GFX10-NEXT:  v_mov_b32_e32 v2, v1
-; GFX10-NEXT:  v_mov_b32_e32 v3, v1
-; GFX10-NEXT:  v_mov_b32_e32 v4, v1
-; GFX10-NEXT:  v_mov_b32_e32 v5, v1
-; GFX10-NEXT:  v_mov_b32_e32 v6, v1
-; GFX10-NEXT:  v_mov_b32_e32 v7, v1
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dwordx4 v[0:3], v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_mov_b32_e32 v0, v1
+; GFX10-NEXT:    v_mov_b32_e32 v2, v1
+; GFX10-NEXT:    v_mov_b32_e32 v3, v1
+; GFX10-NEXT:    v_mov_b32_e32 v4, v1
+; GFX10-NEXT:    v_mov_b32_e32 v5, v1
+; GFX10-NEXT:    v_mov_b32_e32 v6, v1
+; GFX10-NEXT:    v_mov_b32_e32 v7, v1
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-LABEL: shuffle_v8f32_rebroadcast:
 ; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b128 v[0:3], v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_mov_b32_e32 v0, v1
-; GFX11-NEXT:  v_mov_b32_e32 v2, v1
-; GFX11-NEXT:  v_mov_b32_e32 v3, v1
-; GFX11-NEXT:  v_mov_b32_e32 v4, v1
-; GFX11-NEXT:  v_mov_b32_e32 v5, v1
-; GFX11-NEXT:  v_mov_b32_e32 v6, v1
-; GFX11-NEXT:  v_mov_b32_e32 v7, v1
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    global_load_b128 v[0:3], v[0:1], off
+; GFX11-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-NEXT:    v_mov_b32_e32 v0, v1
+; GFX11-NEXT:    v_mov_b32_e32 v2, v1
+; GFX11-NEXT:    v_mov_b32_e32 v3, v1
+; GFX11-NEXT:    v_mov_b32_e32 v4, v1
+; GFX11-NEXT:    v_mov_b32_e32 v5, v1
+; GFX11-NEXT:    v_mov_b32_e32 v6, v1
+; GFX11-NEXT:    v_mov_b32_e32 v7, v1
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <8 x float>, ptr addrspace(1) %arg0
   %val1 = shufflevector <8 x float> %val0, <8 x float> poison, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -1681,69 +2064,69 @@ entry:
 define <16 x float> @shuffle_v16f32_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v16f32_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dwordx4 v[0:3], v[0:1], off
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_mov_b32_e32 v0, v1
-; GFX9-NEXT:  v_mov_b32_e32 v2, v1
-; GFX9-NEXT:  v_mov_b32_e32 v3, v1
-; GFX9-NEXT:  v_mov_b32_e32 v4, v1
-; GFX9-NEXT:  v_mov_b32_e32 v5, v1
-; GFX9-NEXT:  v_mov_b32_e32 v6, v1
-; GFX9-NEXT:  v_mov_b32_e32 v7, v1
-; GFX9-NEXT:  v_mov_b32_e32 v8, v1
-; GFX9-NEXT:  v_mov_b32_e32 v9, v1
-; GFX9-NEXT:  v_mov_b32_e32 v10, v1
-; GFX9-NEXT:  v_mov_b32_e32 v11, v1
-; GFX9-NEXT:  v_mov_b32_e32 v12, v1
-; GFX9-NEXT:  v_mov_b32_e32 v13, v1
-; GFX9-NEXT:  v_mov_b32_e32 v14, v1
-; GFX9-NEXT:  v_mov_b32_e32 v15, v1
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dwordx4 v[0:3], v[0:1], off
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v0, v1
+; GFX9-NEXT:    v_mov_b32_e32 v2, v1
+; GFX9-NEXT:    v_mov_b32_e32 v3, v1
+; GFX9-NEXT:    v_mov_b32_e32 v4, v1
+; GFX9-NEXT:    v_mov_b32_e32 v5, v1
+; GFX9-NEXT:    v_mov_b32_e32 v6, v1
+; GFX9-NEXT:    v_mov_b32_e32 v7, v1
+; GFX9-NEXT:    v_mov_b32_e32 v8, v1
+; GFX9-NEXT:    v_mov_b32_e32 v9, v1
+; GFX9-NEXT:    v_mov_b32_e32 v10, v1
+; GFX9-NEXT:    v_mov_b32_e32 v11, v1
+; GFX9-NEXT:    v_mov_b32_e32 v12, v1
+; GFX9-NEXT:    v_mov_b32_e32 v13, v1
+; GFX9-NEXT:    v_mov_b32_e32 v14, v1
+; GFX9-NEXT:    v_mov_b32_e32 v15, v1
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v16f32_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dwordx4 v[0:3], v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_mov_b32_e32 v0, v1
-; GFX10-NEXT:  v_mov_b32_e32 v2, v1
-; GFX10-NEXT:  v_mov_b32_e32 v3, v1
-; GFX10-NEXT:  v_mov_b32_e32 v4, v1
-; GFX10-NEXT:  v_mov_b32_e32 v5, v1
-; GFX10-NEXT:  v_mov_b32_e32 v6, v1
-; GFX10-NEXT:  v_mov_b32_e32 v7, v1
-; GFX10-NEXT:  v_mov_b32_e32 v8, v1
-; GFX10-NEXT:  v_mov_b32_e32 v9, v1
-; GFX10-NEXT:  v_mov_b32_e32 v10, v1
-; GFX10-NEXT:  v_mov_b32_e32 v11, v1
-; GFX10-NEXT:  v_mov_b32_e32 v12, v1
-; GFX10-NEXT:  v_mov_b32_e32 v13, v1
-; GFX10-NEXT:  v_mov_b32_e32 v14, v1
-; GFX10-NEXT:  v_mov_b32_e32 v15, v1
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dwordx4 v[0:3], v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_mov_b32_e32 v0, v1
+; GFX10-NEXT:    v_mov_b32_e32 v2, v1
+; GFX10-NEXT:    v_mov_b32_e32 v3, v1
+; GFX10-NEXT:    v_mov_b32_e32 v4, v1
+; GFX10-NEXT:    v_mov_b32_e32 v5, v1
+; GFX10-NEXT:    v_mov_b32_e32 v6, v1
+; GFX10-NEXT:    v_mov_b32_e32 v7, v1
+; GFX10-NEXT:    v_mov_b32_e32 v8, v1
+; GFX10-NEXT:    v_mov_b32_e32 v9, v1
+; GFX10-NEXT:    v_mov_b32_e32 v10, v1
+; GFX10-NEXT:    v_mov_b32_e32 v11, v1
+; GFX10-NEXT:    v_mov_b32_e32 v12, v1
+; GFX10-NEXT:    v_mov_b32_e32 v13, v1
+; GFX10-NEXT:    v_mov_b32_e32 v14, v1
+; GFX10-NEXT:    v_mov_b32_e32 v15, v1
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-LABEL: shuffle_v16f32_rebroadcast:
 ; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b128 v[0:3], v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_mov_b32_e32 v0, v1
-; GFX11-NEXT:  v_mov_b32_e32 v2, v1
-; GFX11-NEXT:  v_mov_b32_e32 v3, v1
-; GFX11-NEXT:  v_mov_b32_e32 v4, v1
-; GFX11-NEXT:  v_mov_b32_e32 v5, v1
-; GFX11-NEXT:  v_mov_b32_e32 v6, v1
-; GFX11-NEXT:  v_mov_b32_e32 v7, v1
-; GFX11-NEXT:  v_mov_b32_e32 v8, v1
-; GFX11-NEXT:  v_mov_b32_e32 v9, v1
-; GFX11-NEXT:  v_mov_b32_e32 v10, v1
-; GFX11-NEXT:  v_mov_b32_e32 v11, v1
-; GFX11-NEXT:  v_mov_b32_e32 v12, v1
-; GFX11-NEXT:  v_mov_b32_e32 v13, v1
-; GFX11-NEXT:  v_mov_b32_e32 v14, v1
-; GFX11-NEXT:  v_mov_b32_e32 v15, v1
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    global_load_b128 v[0:3], v[0:1], off
+; GFX11-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-NEXT:    v_mov_b32_e32 v0, v1
+; GFX11-NEXT:    v_mov_b32_e32 v2, v1
+; GFX11-NEXT:    v_mov_b32_e32 v3, v1
+; GFX11-NEXT:    v_mov_b32_e32 v4, v1
+; GFX11-NEXT:    v_mov_b32_e32 v5, v1
+; GFX11-NEXT:    v_mov_b32_e32 v6, v1
+; GFX11-NEXT:    v_mov_b32_e32 v7, v1
+; GFX11-NEXT:    v_mov_b32_e32 v8, v1
+; GFX11-NEXT:    v_mov_b32_e32 v9, v1
+; GFX11-NEXT:    v_mov_b32_e32 v10, v1
+; GFX11-NEXT:    v_mov_b32_e32 v11, v1
+; GFX11-NEXT:    v_mov_b32_e32 v12, v1
+; GFX11-NEXT:    v_mov_b32_e32 v13, v1
+; GFX11-NEXT:    v_mov_b32_e32 v14, v1
+; GFX11-NEXT:    v_mov_b32_e32 v15, v1
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <16 x float>, ptr addrspace(1) %arg0
   %val1 = shufflevector <16 x float> %val0, <16 x float> poison, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -1753,117 +2136,117 @@ entry:
 define <32 x float> @shuffle_v32f32_rebroadcast(ptr addrspace(1) %arg0) {
 ; GFX9-LABEL: shuffle_v32f32_rebroadcast:
 ; GFX9:       ; %bb.0: ; %entry
-; GFX9-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:  global_load_dwordx4 v[0:3], v[0:1], off
-; GFX9-NEXT:  s_waitcnt vmcnt(0)
-; GFX9-NEXT:  v_mov_b32_e32 v0, v1
-; GFX9-NEXT:  v_mov_b32_e32 v2, v1
-; GFX9-NEXT:  v_mov_b32_e32 v3, v1
-; GFX9-NEXT:  v_mov_b32_e32 v4, v1
-; GFX9-NEXT:  v_mov_b32_e32 v5, v1
-; GFX9-NEXT:  v_mov_b32_e32 v6, v1
-; GFX9-NEXT:  v_mov_b32_e32 v7, v1
-; GFX9-NEXT:  v_mov_b32_e32 v8, v1
-; GFX9-NEXT:  v_mov_b32_e32 v9, v1
-; GFX9-NEXT:  v_mov_b32_e32 v10, v1
-; GFX9-NEXT:  v_mov_b32_e32 v11, v1
-; GFX9-NEXT:  v_mov_b32_e32 v12, v1
-; GFX9-NEXT:  v_mov_b32_e32 v13, v1
-; GFX9-NEXT:  v_mov_b32_e32 v14, v1
-; GFX9-NEXT:  v_mov_b32_e32 v15, v1
-; GFX9-NEXT:  v_mov_b32_e32 v16, v1
-; GFX9-NEXT:  v_mov_b32_e32 v17, v1
-; GFX9-NEXT:  v_mov_b32_e32 v18, v1
-; GFX9-NEXT:  v_mov_b32_e32 v19, v1
-; GFX9-NEXT:  v_mov_b32_e32 v20, v1
-; GFX9-NEXT:  v_mov_b32_e32 v21, v1
-; GFX9-NEXT:  v_mov_b32_e32 v22, v1
-; GFX9-NEXT:  v_mov_b32_e32 v23, v1
-; GFX9-NEXT:  v_mov_b32_e32 v24, v1
-; GFX9-NEXT:  v_mov_b32_e32 v25, v1
-; GFX9-NEXT:  v_mov_b32_e32 v26, v1
-; GFX9-NEXT:  v_mov_b32_e32 v27, v1
-; GFX9-NEXT:  v_mov_b32_e32 v28, v1
-; GFX9-NEXT:  v_mov_b32_e32 v29, v1
-; GFX9-NEXT:  v_mov_b32_e32 v30, v1
-; GFX9-NEXT:  v_mov_b32_e32 v31, v1
-; GFX9-NEXT:  s_setpc_b64 s[30:31]
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dwordx4 v[0:3], v[0:1], off
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v0, v1
+; GFX9-NEXT:    v_mov_b32_e32 v2, v1
+; GFX9-NEXT:    v_mov_b32_e32 v3, v1
+; GFX9-NEXT:    v_mov_b32_e32 v4, v1
+; GFX9-NEXT:    v_mov_b32_e32 v5, v1
+; GFX9-NEXT:    v_mov_b32_e32 v6, v1
+; GFX9-NEXT:    v_mov_b32_e32 v7, v1
+; GFX9-NEXT:    v_mov_b32_e32 v8, v1
+; GFX9-NEXT:    v_mov_b32_e32 v9, v1
+; GFX9-NEXT:    v_mov_b32_e32 v10, v1
+; GFX9-NEXT:    v_mov_b32_e32 v11, v1
+; GFX9-NEXT:    v_mov_b32_e32 v12, v1
+; GFX9-NEXT:    v_mov_b32_e32 v13, v1
+; GFX9-NEXT:    v_mov_b32_e32 v14, v1
+; GFX9-NEXT:    v_mov_b32_e32 v15, v1
+; GFX9-NEXT:    v_mov_b32_e32 v16, v1
+; GFX9-NEXT:    v_mov_b32_e32 v17, v1
+; GFX9-NEXT:    v_mov_b32_e32 v18, v1
+; GFX9-NEXT:    v_mov_b32_e32 v19, v1
+; GFX9-NEXT:    v_mov_b32_e32 v20, v1
+; GFX9-NEXT:    v_mov_b32_e32 v21, v1
+; GFX9-NEXT:    v_mov_b32_e32 v22, v1
+; GFX9-NEXT:    v_mov_b32_e32 v23, v1
+; GFX9-NEXT:    v_mov_b32_e32 v24, v1
+; GFX9-NEXT:    v_mov_b32_e32 v25, v1
+; GFX9-NEXT:    v_mov_b32_e32 v26, v1
+; GFX9-NEXT:    v_mov_b32_e32 v27, v1
+; GFX9-NEXT:    v_mov_b32_e32 v28, v1
+; GFX9-NEXT:    v_mov_b32_e32 v29, v1
+; GFX9-NEXT:    v_mov_b32_e32 v30, v1
+; GFX9-NEXT:    v_mov_b32_e32 v31, v1
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: shuffle_v32f32_rebroadcast:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:  global_load_dwordx4 v[0:3], v[0:1], off
-; GFX10-NEXT:  s_waitcnt vmcnt(0)
-; GFX10-NEXT:  v_mov_b32_e32 v0, v1
-; GFX10-NEXT:  v_mov_b32_e32 v2, v1
-; GFX10-NEXT:  v_mov_b32_e32 v3, v1
-; GFX10-NEXT:  v_mov_b32_e32 v4, v1
-; GFX10-NEXT:  v_mov_b32_e32 v5, v1
-; GFX10-NEXT:  v_mov_b32_e32 v6, v1
-; GFX10-NEXT:  v_mov_b32_e32 v7, v1
-; GFX10-NEXT:  v_mov_b32_e32 v8, v1
-; GFX10-NEXT:  v_mov_b32_e32 v9, v1
-; GFX10-NEXT:  v_mov_b32_e32 v10, v1
-; GFX10-NEXT:  v_mov_b32_e32 v11, v1
-; GFX10-NEXT:  v_mov_b32_e32 v12, v1
-; GFX10-NEXT:  v_mov_b32_e32 v13, v1
-; GFX10-NEXT:  v_mov_b32_e32 v14, v1
-; GFX10-NEXT:  v_mov_b32_e32 v15, v1
-; GFX10-NEXT:  v_mov_b32_e32 v16, v1
-; GFX10-NEXT:  v_mov_b32_e32 v17, v1
-; GFX10-NEXT:  v_mov_b32_e32 v18, v1
-; GFX10-NEXT:  v_mov_b32_e32 v19, v1
-; GFX10-NEXT:  v_mov_b32_e32 v20, v1
-; GFX10-NEXT:  v_mov_b32_e32 v21, v1
-; GFX10-NEXT:  v_mov_b32_e32 v22, v1
-; GFX10-NEXT:  v_mov_b32_e32 v23, v1
-; GFX10-NEXT:  v_mov_b32_e32 v24, v1
-; GFX10-NEXT:  v_mov_b32_e32 v25, v1
-; GFX10-NEXT:  v_mov_b32_e32 v26, v1
-; GFX10-NEXT:  v_mov_b32_e32 v27, v1
-; GFX10-NEXT:  v_mov_b32_e32 v28, v1
-; GFX10-NEXT:  v_mov_b32_e32 v29, v1
-; GFX10-NEXT:  v_mov_b32_e32 v30, v1
-; GFX10-NEXT:  v_mov_b32_e32 v31, v1
-; GFX10-NEXT:  s_setpc_b64 s[30:31]
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    global_load_dwordx4 v[0:3], v[0:1], off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_mov_b32_e32 v0, v1
+; GFX10-NEXT:    v_mov_b32_e32 v2, v1
+; GFX10-NEXT:    v_mov_b32_e32 v3, v1
+; GFX10-NEXT:    v_mov_b32_e32 v4, v1
+; GFX10-NEXT:    v_mov_b32_e32 v5, v1
+; GFX10-NEXT:    v_mov_b32_e32 v6, v1
+; GFX10-NEXT:    v_mov_b32_e32 v7, v1
+; GFX10-NEXT:    v_mov_b32_e32 v8, v1
+; GFX10-NEXT:    v_mov_b32_e32 v9, v1
+; GFX10-NEXT:    v_mov_b32_e32 v10, v1
+; GFX10-NEXT:    v_mov_b32_e32 v11, v1
+; GFX10-NEXT:    v_mov_b32_e32 v12, v1
+; GFX10-NEXT:    v_mov_b32_e32 v13, v1
+; GFX10-NEXT:    v_mov_b32_e32 v14, v1
+; GFX10-NEXT:    v_mov_b32_e32 v15, v1
+; GFX10-NEXT:    v_mov_b32_e32 v16, v1
+; GFX10-NEXT:    v_mov_b32_e32 v17, v1
+; GFX10-NEXT:    v_mov_b32_e32 v18, v1
+; GFX10-NEXT:    v_mov_b32_e32 v19, v1
+; GFX10-NEXT:    v_mov_b32_e32 v20, v1
+; GFX10-NEXT:    v_mov_b32_e32 v21, v1
+; GFX10-NEXT:    v_mov_b32_e32 v22, v1
+; GFX10-NEXT:    v_mov_b32_e32 v23, v1
+; GFX10-NEXT:    v_mov_b32_e32 v24, v1
+; GFX10-NEXT:    v_mov_b32_e32 v25, v1
+; GFX10-NEXT:    v_mov_b32_e32 v26, v1
+; GFX10-NEXT:    v_mov_b32_e32 v27, v1
+; GFX10-NEXT:    v_mov_b32_e32 v28, v1
+; GFX10-NEXT:    v_mov_b32_e32 v29, v1
+; GFX10-NEXT:    v_mov_b32_e32 v30, v1
+; GFX10-NEXT:    v_mov_b32_e32 v31, v1
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-LABEL: shuffle_v32f32_rebroadcast:
 ; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:  global_load_b128 v[0:3], v[0:1], off
-; GFX11-NEXT:  s_waitcnt vmcnt(0)
-; GFX11-NEXT:  v_mov_b32_e32 v0, v1
-; GFX11-NEXT:  v_mov_b32_e32 v2, v1
-; GFX11-NEXT:  v_mov_b32_e32 v3, v1
-; GFX11-NEXT:  v_mov_b32_e32 v4, v1
-; GFX11-NEXT:  v_mov_b32_e32 v5, v1
-; GFX11-NEXT:  v_mov_b32_e32 v6, v1
-; GFX11-NEXT:  v_mov_b32_e32 v7, v1
-; GFX11-NEXT:  v_mov_b32_e32 v8, v1
-; GFX11-NEXT:  v_mov_b32_e32 v9, v1
-; GFX11-NEXT:  v_mov_b32_e32 v10, v1
-; GFX11-NEXT:  v_mov_b32_e32 v11, v1
-; GFX11-NEXT:  v_mov_b32_e32 v12, v1
-; GFX11-NEXT:  v_mov_b32_e32 v13, v1
-; GFX11-NEXT:  v_mov_b32_e32 v14, v1
-; GFX11-NEXT:  v_mov_b32_e32 v15, v1
-; GFX11-NEXT:  v_mov_b32_e32 v16, v1
-; GFX11-NEXT:  v_mov_b32_e32 v17, v1
-; GFX11-NEXT:  v_mov_b32_e32 v18, v1
-; GFX11-NEXT:  v_mov_b32_e32 v19, v1
-; GFX11-NEXT:  v_mov_b32_e32 v20, v1
-; GFX11-NEXT:  v_mov_b32_e32 v21, v1
-; GFX11-NEXT:  v_mov_b32_e32 v22, v1
-; GFX11-NEXT:  v_mov_b32_e32 v23, v1
-; GFX11-NEXT:  v_mov_b32_e32 v24, v1
-; GFX11-NEXT:  v_mov_b32_e32 v25, v1
-; GFX11-NEXT:  v_mov_b32_e32 v26, v1
-; GFX11-NEXT:  v_mov_b32_e32 v27, v1
-; GFX11-NEXT:  v_mov_b32_e32 v28, v1
-; GFX11-NEXT:  v_mov_b32_e32 v29, v1
-; GFX11-NEXT:  v_mov_b32_e32 v30, v1
-; GFX11-NEXT:  v_mov_b32_e32 v31, v1
-; GFX11-NEXT:  s_setpc_b64 s[30:31]
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    global_load_b128 v[0:3], v[0:1], off
+; GFX11-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-NEXT:    v_mov_b32_e32 v0, v1
+; GFX11-NEXT:    v_mov_b32_e32 v2, v1
+; GFX11-NEXT:    v_mov_b32_e32 v3, v1
+; GFX11-NEXT:    v_mov_b32_e32 v4, v1
+; GFX11-NEXT:    v_mov_b32_e32 v5, v1
+; GFX11-NEXT:    v_mov_b32_e32 v6, v1
+; GFX11-NEXT:    v_mov_b32_e32 v7, v1
+; GFX11-NEXT:    v_mov_b32_e32 v8, v1
+; GFX11-NEXT:    v_mov_b32_e32 v9, v1
+; GFX11-NEXT:    v_mov_b32_e32 v10, v1
+; GFX11-NEXT:    v_mov_b32_e32 v11, v1
+; GFX11-NEXT:    v_mov_b32_e32 v12, v1
+; GFX11-NEXT:    v_mov_b32_e32 v13, v1
+; GFX11-NEXT:    v_mov_b32_e32 v14, v1
+; GFX11-NEXT:    v_mov_b32_e32 v15, v1
+; GFX11-NEXT:    v_mov_b32_e32 v16, v1
+; GFX11-NEXT:    v_mov_b32_e32 v17, v1
+; GFX11-NEXT:    v_mov_b32_e32 v18, v1
+; GFX11-NEXT:    v_mov_b32_e32 v19, v1
+; GFX11-NEXT:    v_mov_b32_e32 v20, v1
+; GFX11-NEXT:    v_mov_b32_e32 v21, v1
+; GFX11-NEXT:    v_mov_b32_e32 v22, v1
+; GFX11-NEXT:    v_mov_b32_e32 v23, v1
+; GFX11-NEXT:    v_mov_b32_e32 v24, v1
+; GFX11-NEXT:    v_mov_b32_e32 v25, v1
+; GFX11-NEXT:    v_mov_b32_e32 v26, v1
+; GFX11-NEXT:    v_mov_b32_e32 v27, v1
+; GFX11-NEXT:    v_mov_b32_e32 v28, v1
+; GFX11-NEXT:    v_mov_b32_e32 v29, v1
+; GFX11-NEXT:    v_mov_b32_e32 v30, v1
+; GFX11-NEXT:    v_mov_b32_e32 v31, v1
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %val0 = load <32 x float>, ptr addrspace(1) %arg0
   %val1 = shufflevector <32 x float> %val0, <32 x float> poison, <32 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
diff --git a/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll b/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
index bc8d0d1f8cd8f..58602a1ccd5ba 100644
--- a/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
@@ -2,7 +2,8 @@
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GX900 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX942 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define <4 x half> @shuffle_v4f16_23uu(ptr addrspace(1) %arg0, ptr addrspace(1) %arg1) {
 ; GFX9-LABEL: shuffle_v4f16_23uu:
@@ -205,15 +206,25 @@ define <4 x half> @shuffle_v4f16_3u6u(ptr addrspace(1) %arg0, ptr addrspace(1) %
 ; GFX10-NEXT:    v_mov_b32_e32 v1, v4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4f16_3u6u:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT:    global_load_b32 v1, v[2:3], off offset:4
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_alignbit_b32 v0, s0, v0, 16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4f16_3u6u:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT:    global_load_b32 v1, v[2:3], off offset:4
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4f16_3u6u:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[2:3], off offset:4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v0, s0, v0, 16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x half>, ptr addrspace(1) %arg0
   %val1 = load <4 x half>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x half> %val0, <4 x half> %val1, <4 x i32> <i32 3, i32 poison, i32 6, i32 poison>
@@ -254,15 +265,25 @@ define <4 x half> @shuffle_v4f16_3uu7(ptr addrspace(1) %arg0, ptr addrspace(1) %
 ; GFX10-NEXT:    v_mov_b32_e32 v1, v4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4f16_3uu7:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT:    global_load_b32 v1, v[2:3], off offset:4
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_alignbit_b32 v0, s0, v0, 16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4f16_3uu7:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT:    global_load_b32 v1, v[2:3], off offset:4
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4f16_3uu7:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[2:3], off offset:4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v0, s0, v0, 16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x half>, ptr addrspace(1) %arg0
   %val1 = load <4 x half>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x half> %val0, <4 x half> %val1, <4 x i32> <i32 3, i32 poison, i32 poison, i32 7>
@@ -302,14 +323,26 @@ define <4 x half> @shuffle_v4f16_35u5(ptr addrspace(1) %arg0, ptr addrspace(1) %
 ; GFX10-NEXT:    v_mov_b32_e32 v1, v4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4f16_35u5:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT:    global_load_b32 v1, v[2:3], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x7060302
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4f16_35u5:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT:    global_load_b32 v1, v[2:3], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v0, v1
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4f16_35u5:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[2:3], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x half>, ptr addrspace(1) %arg0
   %val1 = load <4 x half>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x half> %val0, <4 x half> %val1, <4 x i32> <i32 3, i32 5, i32 poison, i32 5>
@@ -352,16 +385,29 @@ define <4 x half> @shuffle_v4f16_357u(ptr addrspace(1) %arg0, ptr addrspace(1) %
 ; GFX10-NEXT:    v_perm_b32 v0, v4, v6, 0x7060302
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4f16_357u:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[2:3], v[2:3], off
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_alignbit_b32 v1, s0, v3, 16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v0, v2, v0, 0x7060302
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4f16_357u:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v4, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT:    global_load_b64 v[0:1], v[2:3], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v4.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v2, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4f16_357u:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[2:3], v[2:3], off
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v1, s0, v3, 16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x half>, ptr addrspace(1) %arg0
   %val1 = load <4 x half>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x half> %val0, <4 x half> %val1, <4 x i32> <i32 3, i32 5, i32 7, i32 poison>
@@ -950,15 +996,26 @@ define <4 x half> @shuffle_v4f16_2356(ptr addrspace(1) %arg0, ptr addrspace(1) %
 ; GFX10-NEXT:    v_mov_b32_e32 v0, v4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4f16_2356:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[2:3], v[2:3], off
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_alignbit_b32 v1, v3, v2, 16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4f16_2356:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b64 v[2:3], v[2:3], off
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v3.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4f16_2356:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[2:3], v[2:3], off
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v1, v3, v2, 16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x half>, ptr addrspace(1) %arg0
   %val1 = load <4 x half>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x half> %val0, <4 x half> %val1, <4 x i32> <i32 2, i32 3, i32 5, i32 6>
@@ -999,15 +1056,26 @@ define <4 x half> @shuffle_v4f16_5623(ptr addrspace(1) %arg0, ptr addrspace(1) %
 ; GFX10-NEXT:    v_mov_b32_e32 v1, v4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4f16_5623:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[2:3], v[2:3], off
-; GFX11-NEXT:    global_load_b32 v1, v[0:1], off offset:4
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_alignbit_b32 v0, v3, v2, 16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4f16_5623:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b64 v[2:3], v[2:3], off
+; GFX11-TRUE16-NEXT:    global_load_b32 v1, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v2.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v3.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4f16_5623:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[2:3], v[2:3], off
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v0, v3, v2, 16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x half>, ptr addrspace(1) %arg0
   %val1 = load <4 x half>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x half> %val0, <4 x half> %val1, <4 x i32> <i32 5, i32 6, i32 2, i32 3>
@@ -1037,16 +1105,29 @@ define <4 x half> @shuffle_v4f16_3456(ptr addrspace(1) %arg0, ptr addrspace(1) %
 ; GFX10-NEXT:    v_alignbit_b32 v0, v4, v6, 16
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4f16_3456:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[2:3], v[2:3], off
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_alignbit_b32 v1, v3, v2, 16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v0, v2, v0, 16
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4f16_3456:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT:    global_load_b64 v[1:2], v[2:3], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4f16_3456:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[2:3], v[2:3], off
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v1, v3, v2, 16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v0, v2, v0, 16
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x half>, ptr addrspace(1) %arg0
   %val1 = load <4 x half>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x half> %val0, <4 x half> %val1, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
@@ -1076,16 +1157,29 @@ define <4 x half> @shuffle_v4f16_5634(ptr addrspace(1) %arg0, ptr addrspace(1) %
 ; GFX10-NEXT:    v_alignbit_b32 v1, v4, v6, 16
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4f16_5634:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[2:3], v[2:3], off
-; GFX11-NEXT:    global_load_b32 v1, v[0:1], off offset:4
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_alignbit_b32 v0, v3, v2, 16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v1, v2, v1, 16
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4f16_5634:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT:    global_load_b64 v[2:3], v[2:3], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v2.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4f16_5634:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[2:3], v[2:3], off
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v0, v3, v2, 16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v1, v2, v1, 16
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x half>, ptr addrspace(1) %arg0
   %val1 = load <4 x half>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x half> %val0, <4 x half> %val1, <4 x i32> <i32 5, i32 6, i32 3, i32 4>
@@ -1128,16 +1222,28 @@ define <4 x half> @shuffle_v4f16_5734(ptr addrspace(1) %arg0, ptr addrspace(1) %
 ; GFX10-NEXT:    v_alignbit_b32 v1, v4, v6, 16
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4f16_5734:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[2:3], v[2:3], off
-; GFX11-NEXT:    global_load_b32 v1, v[0:1], off offset:4
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_perm_b32 v0, v3, v2, 0x7060302
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v1, v2, v1, 16
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4f16_5734:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b64 v[2:3], v[2:3], off
+; GFX11-TRUE16-NEXT:    global_load_b32 v1, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v2, v3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4f16_5734:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[2:3], v[2:3], off
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v3, v2, 0x7060302
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v1, v2, v1, 16
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x half>, ptr addrspace(1) %arg0
   %val1 = load <4 x half>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x half> %val0, <4 x half> %val1, <4 x i32> <i32 5, i32 7, i32 3, i32 4>
@@ -1178,15 +1284,27 @@ define <4 x i16> @shuffle_v4i16_2356(ptr addrspace(1) %arg0, ptr addrspace(1) %a
 ; GFX10-NEXT:    v_mov_b32_e32 v0, v4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4i16_2356:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[2:3], v[2:3], off
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_alignbit_b32 v1, v3, v2, 16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4i16_2356:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b64 v[2:3], v[2:3], off
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v1
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4i16_2356:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[2:3], v[2:3], off
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v1, v3, v2, 16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x i16>, ptr addrspace(1) %arg0
   %val1 = load <4 x i16>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x i16> %val0, <4 x i16> %val1, <4 x i32> <i32 2, i32 3, i32 5, i32 6>
@@ -1259,15 +1377,25 @@ define <4 x half> @shuffle_v4f16_0000(ptr addrspace(1) %arg0, ptr addrspace(1) %
 ; GFX10-NEXT:    v_mov_b32_e32 v1, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4f16_0000:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[0:1], v[0:1], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v0, v0, v0, 0x5040100
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_mov_b32_e32 v1, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4f16_0000:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b64 v[0:1], v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4f16_0000:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[0:1], v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x half>, ptr addrspace(1) %arg0
   %val1 = load <4 x half>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x half> %val0, <4 x half> %val1, <4 x i32> zeroinitializer
@@ -1293,15 +1421,26 @@ define <4 x half> @shuffle_v4f16_1010(ptr addrspace(1) %arg0, ptr addrspace(1) %
 ; GFX10-NEXT:    v_mov_b32_e32 v1, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4f16_1010:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[0:1], v[0:1], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v0, v0, v0, 16
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_mov_b32_e32 v1, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4f16_1010:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b64 v[1:2], v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v1.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4f16_1010:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[0:1], v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v0, v0, v0, 16
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x half>, ptr addrspace(1) %arg0
   %val1 = load <4 x half>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x half> %val0, <4 x half> %val1, <4 x i32> <i32 1, i32 0, i32 1, i32 0>
@@ -1340,14 +1479,23 @@ define <4 x half> @shuffle_v4f16_1100(ptr addrspace(1) %arg0, ptr addrspace(1) %
 ; GFX10-NEXT:    v_perm_b32 v1, v1, v1, 0x5040100
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4f16_1100:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[1:2], v[0:1], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v0, v1, v1, 0x7060302
-; GFX11-NEXT:    v_perm_b32 v1, v1, v1, 0x5040100
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4f16_1100:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b64 v[1:2], v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v1, v1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v1.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4f16_1100:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[1:2], v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v1, 0x7060302
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x half>, ptr addrspace(1) %arg0
   %val1 = load <4 x half>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x half> %val0, <4 x half> %val1, <4 x i32> <i32 1, i32 1, i32 0, i32 0>
@@ -1387,16 +1535,29 @@ define <4 x half> @shuffle_v4f16_6161(ptr addrspace(1) %arg0, ptr addrspace(1) %
 ; GFX10-NEXT:    v_mov_b32_e32 v1, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4f16_6161:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:    global_load_b32 v1, v[2:3], off offset:4
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_bfi_b32 v0, 0xffff, v1, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_mov_b32_e32 v1, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4f16_6161:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v2, v[2:3], off offset:4
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v1, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4f16_6161:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[2:3], off offset:4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_bfi_b32 v0, 0xffff, v1, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x half>, ptr addrspace(1) %arg0
   %val1 = load <4 x half>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x half> %val0, <4 x half> %val1, <4 x i32> <i32 6, i32 1, i32 6, i32 1>
@@ -1430,13 +1591,23 @@ define <4 x half> @shuffle_v4f16_2333(ptr addrspace(1) %arg0, ptr addrspace(1) %
 ; GFX10-NEXT:    v_perm_b32 v1, v0, v0, 0x7060302
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4f16_2333:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v1, v0, v0, 0x7060302
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4f16_2333:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4f16_2333:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v0, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x half>, ptr addrspace(1) %arg0
   %val1 = load <4 x half>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x half> %val0, <4 x half> %val1, <4 x i32> <i32 2, i32 3, i32 3, i32 3>
@@ -1470,13 +1641,23 @@ define <4 x half> @shuffle_v4f16_6667(ptr addrspace(1) %arg0, ptr addrspace(1) %
 ; GFX10-NEXT:    v_perm_b32 v1, v0, v0, 0x7060302
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4f16_6667:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v1, v0, v0, 0x7060302
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4f16_6667:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4f16_6667:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v0, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x half>, ptr addrspace(1) %arg0
   %val1 = load <4 x half>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x half> %val0, <4 x half> %val1, <4 x i32> <i32 2, i32 3, i32 3, i32 3>
@@ -1648,15 +1829,26 @@ define <4 x half> @shuffle_v8f16_13_14_2_3(ptr addrspace(1) %arg0, ptr addrspace
 ; GFX10-NEXT:    v_mov_b32_e32 v1, v4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v8f16_13_14_2_3:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[2:3], v[2:3], off offset:8
-; GFX11-NEXT:    global_load_b32 v1, v[0:1], off offset:4
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_alignbit_b32 v0, v3, v2, 16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v8f16_13_14_2_3:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b64 v[2:3], v[2:3], off offset:8
+; GFX11-TRUE16-NEXT:    global_load_b32 v1, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v2.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v3.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v8f16_13_14_2_3:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[2:3], v[2:3], off offset:8
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v0, v3, v2, 16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <8 x half>, ptr addrspace(1) %arg0
   %val1 = load <8 x half>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <8 x half> %val0, <8 x half> %val1, <4 x i32> <i32 13, i32 14, i32 2, i32 3>
@@ -1690,13 +1882,21 @@ define <4 x half> @shuffle_v3f16_0122(ptr addrspace(1) %arg0, ptr addrspace(1) %
 ; GFX10-NEXT:    v_perm_b32 v1, v1, v1, 0x5040100
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v3f16_0122:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[0:1], v[0:1], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v1, v1, v1, 0x5040100
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v3f16_0122:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b64 v[0:1], v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v1.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v3f16_0122:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[0:1], v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <3 x half>, ptr addrspace(1) %arg0
   %val1 = load <3 x half>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <3 x half> %val0, <3 x half> %val1, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
@@ -1720,13 +1920,22 @@ define <4 x half> @shuffle_v2f16_0122(ptr addrspace(1) %arg0, ptr addrspace(1) %
 ; GFX10-NEXT:    v_alignbit_b32 v1, v0, v0, 16
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v2f16_0122:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v1, v0, v0, 16
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v2f16_0122:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v2f16_0122:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v1, v0, v0, 16
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <2 x half>, ptr addrspace(1) %arg0
   %val1 = load <2 x half>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <2 x half> %val0, <2 x half> %val1, <4 x i32> <i32 0, i32 1, i32 1, i32 0>
@@ -1938,15 +2147,26 @@ define <4 x half> @shuffle_v4f16_0456(ptr addrspace(1) %arg0, ptr addrspace(1) %
 ; GFX10-NEXT:    v_alignbit_b32 v1, v6, v5, 16
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4f16_0456:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[0:1], v[0:1], off
-; GFX11-NEXT:    global_load_b64 v[1:2], v[2:3], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    v_alignbit_b32 v1, v2, v1, 16
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4f16_0456:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b64 v[2:3], v[2:3], off
+; GFX11-TRUE16-NEXT:    global_load_b64 v[0:1], v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v3.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4f16_0456:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[0:1], v[0:1], off
+; GFX11-FAKE16-NEXT:    global_load_b64 v[1:2], v[2:3], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v1, v2, v1, 16
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x half>, ptr addrspace(1) %arg0
   %val1 = load <4 x half>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x half> %val0, <4 x half> %val1, <4 x i32> <i32 0, i32 4, i32 5, i32 6>
@@ -2041,14 +2261,23 @@ define <2 x half> @low16bits_v2f16(ptr addrspace(1) %x0, ptr addrspace(1) %x1) {
 ; GFX10-NEXT:    v_perm_b32 v0, v5, v4, 0x5040100
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: low16bits_v2f16:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:    global_load_b32 v1, v[2:3], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: low16bits_v2f16:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v2, v[2:3], off
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v2.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: low16bits_v2f16:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[2:3], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %0 = load <2 x half>, ptr addrspace(1) %x0, align 4
   %1 = load <2 x half>, ptr addrspace(1) %x1, align 4
@@ -2087,14 +2316,26 @@ define <2 x half> @hi16bits_v2f16(ptr addrspace(1) %x0, ptr addrspace(1) %x1) {
 ; GFX10-NEXT:    v_perm_b32 v0, v5, v4, 0x7060302
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: hi16bits_v2f16:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:    global_load_b32 v1, v[2:3], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x7060302
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: hi16bits_v2f16:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    global_load_b32 v1, v[2:3], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v0, v1
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: hi16bits_v2f16:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[2:3], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %0 = load <2 x half>, ptr addrspace(1) %x0, align 4
   %1 = load <2 x half>, ptr addrspace(1) %x1, align 4
@@ -2168,14 +2409,25 @@ define <2 x half> @hi16low16bits_v2bf16(ptr addrspace(1) %x0, ptr addrspace(1) %
 ; GFX10-NEXT:    v_alignbit_b32 v0, v5, v4, 16
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: hi16low16bits_v2bf16:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:    global_load_b32 v1, v[2:3], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v0, v1, v0, 16
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: hi16low16bits_v2bf16:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    global_load_b32 v1, v[2:3], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: hi16low16bits_v2bf16:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[2:3], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v0, v1, v0, 16
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %0 = load <2 x half>, ptr addrspace(1) %x0, align 4
   %1 = load <2 x half>, ptr addrspace(1) %x1, align 4
@@ -2214,14 +2466,23 @@ define <2 x i16> @i16_low16bits(ptr addrspace(1) %x0, ptr addrspace(1) %x1) {
 ; GFX10-NEXT:    v_perm_b32 v0, v5, v4, 0x5040100
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: i16_low16bits:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:    global_load_b32 v1, v[2:3], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: i16_low16bits:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v2, v[2:3], off
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v2.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: i16_low16bits:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[2:3], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %0 = load <2 x i16>, ptr addrspace(1) %x0, align 4
   %1 = load <2 x i16>, ptr addrspace(1) %x1, align 4
@@ -2295,14 +2556,26 @@ define <2 x i16> @i16_hi16low16bits(ptr addrspace(1) %x0, ptr addrspace(1) %x1)
 ; GFX10-NEXT:    v_alignbit_b32 v0, v5, v4, 16
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: i16_hi16low16bits:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:    global_load_b32 v1, v[2:3], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v0, v1, v0, 16
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: i16_hi16low16bits:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    global_load_b32 v1, v[2:3], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: i16_hi16low16bits:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[2:3], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v0, v1, v0, 16
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %0 = load <2 x i16>, ptr addrspace(1) %x0, align 4
   %1 = load <2 x i16>, ptr addrspace(1) %x1, align 4
@@ -2341,14 +2614,27 @@ define <2 x i16> @i16_hi16bits(ptr addrspace(1) %x0, ptr addrspace(1) %x1) {
 ; GFX10-NEXT:    v_perm_b32 v0, v5, v4, 0x7060302
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: i16_hi16bits:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:    global_load_b32 v1, v[2:3], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x7060302
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: i16_hi16bits:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v2, v[2:3], off
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: i16_hi16bits:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[2:3], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %0 = load <2 x i16>, ptr addrspace(1) %x0, align 4
   %1 = load <2 x i16>, ptr addrspace(1) %x1, align 4
@@ -2732,14 +3018,23 @@ define void @shuffle_v4i8_concat(ptr addrspace(1) %arg0, ptr addrspace(1) %arg1,
 ; GFX10-NEXT:    global_store_dword v[4:5], v0, off
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4i8_concat:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_u16 v0, v[0:1], off
-; GFX11-NEXT:    global_load_d16_hi_b16 v0, v[2:3], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_store_b32 v[4:5], v0, off
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4i8_concat:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    global_load_d16_hi_b16 v0, v[2:3], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    global_store_b32 v[4:5], v0, off
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4i8_concat:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_u16 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    global_load_d16_hi_b16 v0, v[2:3], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    global_store_b32 v[4:5], v0, off
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <2 x i8>, ptr addrspace(1) %arg0
   %val1 = load <2 x i8>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <2 x i8> %val0, <2 x i8> %val1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
@@ -3198,15 +3493,25 @@ define <4 x bfloat> @shuffle_v4bf16_3u6u(ptr addrspace(1) %arg0, ptr addrspace(1
 ; GFX10-NEXT:    v_mov_b32_e32 v1, v4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4bf16_3u6u:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT:    global_load_b32 v1, v[2:3], off offset:4
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_alignbit_b32 v0, s0, v0, 16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4bf16_3u6u:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT:    global_load_b32 v1, v[2:3], off offset:4
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4bf16_3u6u:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[2:3], off offset:4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v0, s0, v0, 16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
   %val1 = load <4 x bfloat>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x bfloat> %val0, <4 x bfloat> %val1, <4 x i32> <i32 3, i32 poison, i32 6, i32 poison>
@@ -3247,15 +3552,25 @@ define <4 x bfloat> @shuffle_v4bf16_3uu7(ptr addrspace(1) %arg0, ptr addrspace(1
 ; GFX10-NEXT:    v_mov_b32_e32 v1, v4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4bf16_3uu7:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT:    global_load_b32 v1, v[2:3], off offset:4
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_alignbit_b32 v0, s0, v0, 16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4bf16_3uu7:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT:    global_load_b32 v1, v[2:3], off offset:4
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4bf16_3uu7:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[2:3], off offset:4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v0, s0, v0, 16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
   %val1 = load <4 x bfloat>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x bfloat> %val0, <4 x bfloat> %val1, <4 x i32> <i32 3, i32 poison, i32 poison, i32 7>
@@ -3295,14 +3610,26 @@ define <4 x bfloat> @shuffle_v4bf16_35u5(ptr addrspace(1) %arg0, ptr addrspace(1
 ; GFX10-NEXT:    v_mov_b32_e32 v1, v4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4bf16_35u5:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT:    global_load_b32 v1, v[2:3], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x7060302
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4bf16_35u5:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT:    global_load_b32 v1, v[2:3], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v0, v1
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4bf16_35u5:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[2:3], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
   %val1 = load <4 x bfloat>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x bfloat> %val0, <4 x bfloat> %val1, <4 x i32> <i32 3, i32 5, i32 poison, i32 5>
@@ -3345,16 +3672,29 @@ define <4 x bfloat> @shuffle_v4bf16_357u(ptr addrspace(1) %arg0, ptr addrspace(1
 ; GFX10-NEXT:    v_perm_b32 v0, v4, v6, 0x7060302
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4bf16_357u:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[2:3], v[2:3], off
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_alignbit_b32 v1, s0, v3, 16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v0, v2, v0, 0x7060302
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4bf16_357u:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v4, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT:    global_load_b64 v[0:1], v[2:3], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v4.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v2, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4bf16_357u:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[2:3], v[2:3], off
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v1, s0, v3, 16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
   %val1 = load <4 x bfloat>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x bfloat> %val0, <4 x bfloat> %val1, <4 x i32> <i32 3, i32 5, i32 7, i32 poison>
@@ -3943,15 +4283,26 @@ define <4 x bfloat> @shuffle_v4bf16_2356(ptr addrspace(1) %arg0, ptr addrspace(1
 ; GFX10-NEXT:    v_mov_b32_e32 v0, v4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4bf16_2356:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[2:3], v[2:3], off
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_alignbit_b32 v1, v3, v2, 16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4bf16_2356:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b64 v[2:3], v[2:3], off
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v3.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4bf16_2356:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[2:3], v[2:3], off
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v1, v3, v2, 16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
   %val1 = load <4 x bfloat>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x bfloat> %val0, <4 x bfloat> %val1, <4 x i32> <i32 2, i32 3, i32 5, i32 6>
@@ -3992,15 +4343,26 @@ define <4 x bfloat> @shuffle_v4bf16_5623(ptr addrspace(1) %arg0, ptr addrspace(1
 ; GFX10-NEXT:    v_mov_b32_e32 v1, v4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4bf16_5623:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[2:3], v[2:3], off
-; GFX11-NEXT:    global_load_b32 v1, v[0:1], off offset:4
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_alignbit_b32 v0, v3, v2, 16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4bf16_5623:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b64 v[2:3], v[2:3], off
+; GFX11-TRUE16-NEXT:    global_load_b32 v1, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v2.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v3.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4bf16_5623:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[2:3], v[2:3], off
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v0, v3, v2, 16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
   %val1 = load <4 x bfloat>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x bfloat> %val0, <4 x bfloat> %val1, <4 x i32> <i32 5, i32 6, i32 2, i32 3>
@@ -4030,16 +4392,29 @@ define <4 x bfloat> @shuffle_v4bf16_3456(ptr addrspace(1) %arg0, ptr addrspace(1
 ; GFX10-NEXT:    v_alignbit_b32 v0, v4, v6, 16
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4bf16_3456:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[2:3], v[2:3], off
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_alignbit_b32 v1, v3, v2, 16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v0, v2, v0, 16
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4bf16_3456:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT:    global_load_b64 v[1:2], v[2:3], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4bf16_3456:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[2:3], v[2:3], off
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v1, v3, v2, 16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v0, v2, v0, 16
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
   %val1 = load <4 x bfloat>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x bfloat> %val0, <4 x bfloat> %val1, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
@@ -4069,16 +4444,29 @@ define <4 x bfloat> @shuffle_v4bf16_5634(ptr addrspace(1) %arg0, ptr addrspace(1
 ; GFX10-NEXT:    v_alignbit_b32 v1, v4, v6, 16
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4bf16_5634:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[2:3], v[2:3], off
-; GFX11-NEXT:    global_load_b32 v1, v[0:1], off offset:4
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_alignbit_b32 v0, v3, v2, 16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v1, v2, v1, 16
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4bf16_5634:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT:    global_load_b64 v[2:3], v[2:3], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v2.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4bf16_5634:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[2:3], v[2:3], off
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v0, v3, v2, 16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v1, v2, v1, 16
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
   %val1 = load <4 x bfloat>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x bfloat> %val0, <4 x bfloat> %val1, <4 x i32> <i32 5, i32 6, i32 3, i32 4>
@@ -4121,16 +4509,28 @@ define <4 x bfloat> @shuffle_v4bf16_5734(ptr addrspace(1) %arg0, ptr addrspace(1
 ; GFX10-NEXT:    v_alignbit_b32 v1, v4, v6, 16
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4bf16_5734:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[2:3], v[2:3], off
-; GFX11-NEXT:    global_load_b32 v1, v[0:1], off offset:4
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_perm_b32 v0, v3, v2, 0x7060302
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v1, v2, v1, 16
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4bf16_5734:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b64 v[2:3], v[2:3], off
+; GFX11-TRUE16-NEXT:    global_load_b32 v1, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v2, v3
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4bf16_5734:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[2:3], v[2:3], off
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v3, v2, 0x7060302
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v1, v2, v1, 16
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
   %val1 = load <4 x bfloat>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x bfloat> %val0, <4 x bfloat> %val1, <4 x i32> <i32 5, i32 7, i32 3, i32 4>
@@ -4167,15 +4567,25 @@ define <4 x bfloat> @shuffle_v4bf16_0000(ptr addrspace(1) %arg0, ptr addrspace(1
 ; GFX10-NEXT:    v_mov_b32_e32 v1, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4bf16_0000:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[0:1], v[0:1], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v0, v0, v0, 0x5040100
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_mov_b32_e32 v1, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4bf16_0000:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b64 v[0:1], v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4bf16_0000:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[0:1], v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
   %val1 = load <4 x bfloat>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x bfloat> %val0, <4 x bfloat> %val1, <4 x i32> zeroinitializer
@@ -4201,15 +4611,26 @@ define <4 x bfloat> @shuffle_v4bf16_1010(ptr addrspace(1) %arg0, ptr addrspace(1
 ; GFX10-NEXT:    v_mov_b32_e32 v1, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4bf16_1010:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[0:1], v[0:1], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v0, v0, v0, 16
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_mov_b32_e32 v1, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4bf16_1010:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b64 v[1:2], v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v1.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4bf16_1010:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[0:1], v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v0, v0, v0, 16
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
   %val1 = load <4 x bfloat>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x bfloat> %val0, <4 x bfloat> %val1, <4 x i32> <i32 1, i32 0, i32 1, i32 0>
@@ -4248,14 +4669,23 @@ define <4 x bfloat> @shuffle_v4bf16_1100(ptr addrspace(1) %arg0, ptr addrspace(1
 ; GFX10-NEXT:    v_perm_b32 v1, v1, v1, 0x5040100
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4bf16_1100:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[1:2], v[0:1], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v0, v1, v1, 0x7060302
-; GFX11-NEXT:    v_perm_b32 v1, v1, v1, 0x5040100
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4bf16_1100:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b64 v[1:2], v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v1, v1
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v1.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4bf16_1100:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[1:2], v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v1, 0x7060302
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
   %val1 = load <4 x bfloat>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x bfloat> %val0, <4 x bfloat> %val1, <4 x i32> <i32 1, i32 1, i32 0, i32 0>
@@ -4295,16 +4725,29 @@ define <4 x bfloat> @shuffle_v4bf16_6161(ptr addrspace(1) %arg0, ptr addrspace(1
 ; GFX10-NEXT:    v_mov_b32_e32 v1, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4bf16_6161:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:    global_load_b32 v1, v[2:3], off offset:4
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_bfi_b32 v0, 0xffff, v1, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_mov_b32_e32 v1, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4bf16_6161:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v2, v[2:3], off offset:4
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v1, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4bf16_6161:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[2:3], off offset:4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_bfi_b32 v0, 0xffff, v1, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, v0
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
   %val1 = load <4 x bfloat>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x bfloat> %val0, <4 x bfloat> %val1, <4 x i32> <i32 6, i32 1, i32 6, i32 1>
@@ -4338,13 +4781,23 @@ define <4 x bfloat> @shuffle_v4bf16_2333(ptr addrspace(1) %arg0, ptr addrspace(1
 ; GFX10-NEXT:    v_perm_b32 v1, v0, v0, 0x7060302
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4bf16_2333:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v1, v0, v0, 0x7060302
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4bf16_2333:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4bf16_2333:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v0, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
   %val1 = load <4 x bfloat>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x bfloat> %val0, <4 x bfloat> %val1, <4 x i32> <i32 2, i32 3, i32 3, i32 3>
@@ -4378,13 +4831,23 @@ define <4 x bfloat> @shuffle_v4bf16_6667(ptr addrspace(1) %arg0, ptr addrspace(1
 ; GFX10-NEXT:    v_perm_b32 v1, v0, v0, 0x7060302
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4bf16_6667:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v1, v0, v0, 0x7060302
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4bf16_6667:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v1, v0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4bf16_6667:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v0, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
   %val1 = load <4 x bfloat>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x bfloat> %val0, <4 x bfloat> %val1, <4 x i32> <i32 2, i32 3, i32 3, i32 3>
@@ -4556,15 +5019,26 @@ define <4 x bfloat> @shuffle_v8bf16_13_14_2_3(ptr addrspace(1) %arg0, ptr addrsp
 ; GFX10-NEXT:    v_mov_b32_e32 v1, v4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v8bf16_13_14_2_3:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[2:3], v[2:3], off offset:8
-; GFX11-NEXT:    global_load_b32 v1, v[0:1], off offset:4
-; GFX11-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-NEXT:    v_alignbit_b32 v0, v3, v2, 16
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v8bf16_13_14_2_3:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b64 v[2:3], v[2:3], off offset:8
+; GFX11-TRUE16-NEXT:    global_load_b32 v1, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v2.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v3.l
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v8bf16_13_14_2_3:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[2:3], v[2:3], off offset:8
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[0:1], off offset:4
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v0, v3, v2, 16
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <8 x bfloat>, ptr addrspace(1) %arg0
   %val1 = load <8 x bfloat>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <8 x bfloat> %val0, <8 x bfloat> %val1, <4 x i32> <i32 13, i32 14, i32 2, i32 3>
@@ -4598,13 +5072,21 @@ define <4 x bfloat> @shuffle_v3bf16_0122(ptr addrspace(1) %arg0, ptr addrspace(1
 ; GFX10-NEXT:    v_perm_b32 v1, v1, v1, 0x5040100
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v3bf16_0122:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[0:1], v[0:1], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v1, v1, v1, 0x5040100
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v3bf16_0122:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b64 v[0:1], v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v1.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v3bf16_0122:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[0:1], v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <3 x bfloat>, ptr addrspace(1) %arg0
   %val1 = load <3 x bfloat>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <3 x bfloat> %val0, <3 x bfloat> %val1, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
@@ -4628,13 +5110,22 @@ define <4 x bfloat> @shuffle_v2bf16_0122(ptr addrspace(1) %arg0, ptr addrspace(1
 ; GFX10-NEXT:    v_alignbit_b32 v1, v0, v0, 16
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v2bf16_0122:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v1, v0, v0, 16
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v2bf16_0122:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v0.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v2bf16_0122:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v1, v0, v0, 16
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <2 x bfloat>, ptr addrspace(1) %arg0
   %val1 = load <2 x bfloat>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <2 x bfloat> %val0, <2 x bfloat> %val1, <4 x i32> <i32 0, i32 1, i32 1, i32 0>
@@ -4956,100 +5447,198 @@ define amdgpu_kernel void @fma_shuffle_v2bf16(ptr addrspace(1) nocapture readonl
 ; GFX10-NEXT:    global_store_dwordx2 v6, v[0:1], s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: fma_shuffle_v2bf16:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x10
-; GFX11-NEXT:    s_load_b128 s[4:7], s[4:5], 0x0
-; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v6, 3, v0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x2
-; GFX11-NEXT:    global_load_b64 v[0:1], v6, s[0:1]
-; GFX11-NEXT:    global_load_b64 v[2:3], v6, s[4:5]
-; GFX11-NEXT:    global_load_b64 v[4:5], v6, s[6:7]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v10, 16, v5
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT:    v_and_b32_e32 v9, 0xffff0000, v4
-; GFX11-NEXT:    v_lshlrev_b32_e32 v12, 16, v3
-; GFX11-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT:    v_and_b32_e32 v11, 0xffff0000, v1
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_dual_fmac_f32 v1, v12, v4 :: v_dual_lshlrev_b32 v8, 16, v2
-; GFX11-NEXT:    v_bfe_u32 v15, v1, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v16, 0x400000, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v15, v15, v1, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff0000, v0
-; GFX11-NEXT:    v_dual_fmac_f32 v7, v8, v9 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_fmac_f32_e32 v0, v8, v4
-; GFX11-NEXT:    v_bfe_u32 v4, v7, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v7
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v4, v4, v7, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v4, v4, v8, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT:    v_fmac_f32_e32 v4, v2, v5
-; GFX11-NEXT:    v_fmac_f32_e32 v11, v12, v9
-; GFX11-NEXT:    v_bfe_u32 v9, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_or_b32_e32 v8, 0x400000, v4
-; GFX11-NEXT:    v_bfe_u32 v13, v11, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_add3_u32 v9, v9, v0, 0x7fff
-; GFX11-NEXT:    v_or_b32_e32 v14, 0x400000, v11
-; GFX11-NEXT:    v_add3_u32 v13, v13, v11, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v9, v12, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v15, v16, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT:    v_cndmask_b32_e32 v7, v13, v14, vcc_lo
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_fmac_f32_e32 v1, v3, v10
-; GFX11-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_bfe_u32 v9, v1, 16, 1
-; GFX11-NEXT:    v_fmac_f32_e32 v7, v3, v5
-; GFX11-NEXT:    v_bfe_u32 v5, v4, 16, 1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_add3_u32 v9, v9, v1, 0x7fff
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT:    v_bfe_u32 v11, v7, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v12, 0x400000, v7
-; GFX11-NEXT:    v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_fmac_f32_e32 v0, v2, v10
-; GFX11-NEXT:    v_or_b32_e32 v10, 0x400000, v1
-; GFX11-NEXT:    v_add3_u32 v11, v11, v7, 0x7fff
-; GFX11-NEXT:    v_bfe_u32 v2, v0, 16, 1
-; GFX11-NEXT:    v_or_b32_e32 v3, 0x400000, v0
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_add3_u32 v2, v2, v0, 0x7fff
-; GFX11-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT:    v_cndmask_b32_e32 v1, v9, v10, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-NEXT:    v_cndmask_b32_e32 v2, v11, v12, vcc_lo
-; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_perm_b32 v1, v2, v1, 0x7060302
-; GFX11-NEXT:    v_cndmask_b32_e32 v3, v5, v8, vcc_lo
-; GFX11-NEXT:    v_perm_b32 v0, v3, v0, 0x7060302
-; GFX11-NEXT:    global_store_b64 v6, v[0:1], s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: fma_shuffle_v2bf16:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x10
+; GFX11-TRUE16-NEXT:    s_load_b128 s[4:7], s[4:5], 0x0
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 3, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x2
+; GFX11-TRUE16-NEXT:    global_load_b64 v[0:1], v6, s[0:1]
+; GFX11-TRUE16-NEXT:    global_load_b64 v[2:3], v6, s[4:5]
+; GFX11-TRUE16-NEXT:    global_load_b64 v[4:5], v6, s[6:7]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_dual_fmac_f32 v1, v12, v4 :: v_dual_lshlrev_b32 v8, 16, v2
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v15, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v16, 0x400000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v15, v15, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v0
+; GFX11-TRUE16-NEXT:    v_dual_fmac_f32 v7, v8, v9 :: v_dual_and_b32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v0, v8, v4
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v4, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, 0x400000, v7
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v4, v4, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v4, v8, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v4, v2, v5
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v11, v12, v9
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v0, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v13, v11, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v14, 0x400000, v11
+; GFX11-TRUE16-NEXT:    v_add3_u32 v13, v13, v11, 0x7fff
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v9, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v15, v16, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v0, v2, v10
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v7, v13, v14, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v2, v0, 16, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-TRUE16-NEXT:    v_add3_u32 v2, v2, v0, 0x7fff
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v7, v3, v5
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v5, v4, 16, 1
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v12, 0x400000, v7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v5, v5, v4, 0x7fff
+; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v4, v5, v8 :: v_dual_fmac_f32 v1, v3, v10
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v10, v7, 16, 1
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v3, 0x400000, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_bfe_u32 v9, v1, 16, 1
+; GFX11-TRUE16-NEXT:    v_add3_u32 v10, v10, v7, 0x7fff
+; GFX11-TRUE16-NEXT:    v_or_b32_e32 v11, 0x400000, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_add3_u32 v9, v9, v1, 0x7fff
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v10, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v5.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v4.h
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v3, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v1, 0xffff, v2, v1
+; GFX11-TRUE16-NEXT:    global_store_b64 v6, v[0:1], s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: fma_shuffle_v2bf16:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x10
+; GFX11-FAKE16-NEXT:    s_load_b128 s[4:7], s[4:5], 0x0
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 3, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x2
+; GFX11-FAKE16-NEXT:    global_load_b64 v[0:1], v6, s[0:1]
+; GFX11-FAKE16-NEXT:    global_load_b64 v[2:3], v6, s[4:5]
+; GFX11-FAKE16-NEXT:    global_load_b64 v[4:5], v6, s[6:7]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v4
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v3
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_dual_fmac_f32 v1, v12, v4 :: v_dual_lshlrev_b32 v8, 16, v2
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v15, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v16, 0x400000, v1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v15, v15, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_dual_fmac_f32 v7, v8, v9 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v0, v8, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v4, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v4, v4, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v8, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v4, v2, v5
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v11, v12, v9
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v8, 0x400000, v4
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v13, v11, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v14, 0x400000, v11
+; GFX11-FAKE16-NEXT:    v_add3_u32 v13, v13, v11, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v9, v12, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v15, v16, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v13, v14, vcc_lo
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v1, v3, v10
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v9, v1, 16, 1
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v7, v3, v5
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v5, v4, 16, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v9, v9, v1, 0x7fff
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v11, v7, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v12, 0x400000, v7
+; GFX11-FAKE16-NEXT:    v_add3_u32 v5, v5, v4, 0x7fff
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v0, v2, v10
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v10, 0x400000, v1
+; GFX11-FAKE16-NEXT:    v_add3_u32 v11, v11, v7, 0x7fff
+; GFX11-FAKE16-NEXT:    v_bfe_u32 v2, v0, 16, 1
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, 0x400000, v0
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add3_u32 v2, v2, v0, 0x7fff
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v9, v10, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v11, v12, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x7060302
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v5, v8, vcc_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v3, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    global_store_b64 v6, v[0:1], s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
 entry:
   %tmp1 = tail call i32 @llvm.amdgcn.workitem.id.x()
   %tmp12 = zext i32 %tmp1 to i64
@@ -5116,15 +5705,26 @@ define <4 x bfloat> @shuffle_v4bf16_0456(ptr addrspace(1) %arg0, ptr addrspace(1
 ; GFX10-NEXT:    v_alignbit_b32 v1, v6, v5, 16
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: shuffle_v4bf16_0456:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b64 v[0:1], v[0:1], off
-; GFX11-NEXT:    global_load_b64 v[1:2], v[2:3], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    v_alignbit_b32 v1, v2, v1, 16
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: shuffle_v4bf16_0456:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b64 v[2:3], v[2:3], off
+; GFX11-TRUE16-NEXT:    global_load_b64 v[0:1], v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v2.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.h
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v3.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: shuffle_v4bf16_0456:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b64 v[0:1], v[0:1], off
+; GFX11-FAKE16-NEXT:    global_load_b64 v[1:2], v[2:3], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v1, v2, v1, 16
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
   %val1 = load <4 x bfloat>, ptr addrspace(1) %arg1
   %shuffle = shufflevector <4 x bfloat> %val0, <4 x bfloat> %val1, <4 x i32> <i32 0, i32 4, i32 5, i32 6>
@@ -5161,14 +5761,23 @@ define <2 x bfloat> @low16bits(ptr addrspace(1) %x0, ptr addrspace(1) %x1) {
 ; GFX10-NEXT:    v_perm_b32 v0, v5, v4, 0x5040100
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: low16bits:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:    global_load_b32 v1, v[2:3], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: low16bits:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v2, v[2:3], off
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v2.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: low16bits:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[2:3], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %0 = load <2 x bfloat>, ptr addrspace(1) %x0, align 4
   %1 = load <2 x bfloat>, ptr addrspace(1) %x1, align 4
@@ -5207,14 +5816,26 @@ define <2 x bfloat> @hi16bits_v2bf16(ptr addrspace(1) %x0, ptr addrspace(1) %x1)
 ; GFX10-NEXT:    v_perm_b32 v0, v5, v4, 0x7060302
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: hi16bits_v2bf16:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:    global_load_b32 v1, v[2:3], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x7060302
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: hi16bits_v2bf16:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    global_load_b32 v1, v[2:3], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v0, v1
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: hi16bits_v2bf16:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[2:3], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x7060302
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %0 = load <2 x bfloat>, ptr addrspace(1) %x0, align 4
   %1 = load <2 x bfloat>, ptr addrspace(1) %x1, align 4
@@ -5253,14 +5874,23 @@ define <2 x bfloat> @low16hi16bits_v2bf16(ptr addrspace(1) %x0, ptr addrspace(1)
 ; GFX10-NEXT:    v_bfi_b32 v0, 0xffff, v5, v4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: low16hi16bits_v2bf16:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v2, v[2:3], off
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_bfi_b32 v0, 0xffff, v0, v2
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: low16hi16bits_v2bf16:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    global_load_b32 v1, v[2:3], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v0, 0xffff, v0, v1
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: low16hi16bits_v2bf16:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v2, v[2:3], off
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_bfi_b32 v0, 0xffff, v0, v2
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %0 = load <2 x bfloat>, ptr addrspace(1) %x0, align 4
   %1 = load <2 x bfloat>, ptr addrspace(1) %x1, align 4
@@ -5288,14 +5918,25 @@ define <2 x bfloat> @hi16low16bits(ptr addrspace(1) %x0, ptr addrspace(1) %x1) {
 ; GFX10-NEXT:    v_alignbit_b32 v0, v5, v4, 16
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: hi16low16bits:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v[0:1], off
-; GFX11-NEXT:    global_load_b32 v1, v[2:3], off
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v0, v1, v0, 16
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: hi16low16bits:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT:    global_load_b32 v1, v[2:3], off
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: hi16low16bits:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v[0:1], off
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v[2:3], off
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v0, v1, v0, 16
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %0 = load <2 x bfloat>, ptr addrspace(1) %x0, align 4
   %1 = load <2 x bfloat>, ptr addrspace(1) %x1, align 4
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll b/llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
index ab7e85fdff516..9ed533297e832 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
@@ -97,5 +97,3 @@ declare void @llvm.assume(i1 noundef)
 declare void @llvm.amdgcn.s.barrier()
 declare void @llvm.trap()
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/AMDGPU/vopc_dpp.mir b/llvm/test/CodeGen/AMDGPU/vopc_dpp.mir
index 656c849bbd56b..d07691997d6c1 100644
--- a/llvm/test/CodeGen/AMDGPU/vopc_dpp.mir
+++ b/llvm/test/CodeGen/AMDGPU/vopc_dpp.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=GCN
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN,GCN-TRUE16
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN,GCN-FAKE16
 
 ---
 
@@ -9,27 +10,51 @@ body:             |
   bb.0:
     liveins: $vgpr0, $vgpr1, $vgpr2
 
-    ; GCN-LABEL: name: vopc
-    ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
-    ; GCN-NEXT: {{  $}}
-    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-    ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-    ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
-    ; GCN-NEXT: V_CMP_LT_F32_e32_dpp 0, [[COPY1]], 0, [[COPY]], 1, 15, 15, 1, implicit-def $vcc, implicit $mode, implicit $exec
-    ; GCN-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[COPY1]], 1, 15, 15, 1, implicit $exec
-    ; GCN-NEXT: V_CMPX_EQ_I16_fake16_nosdst_e64 [[V_MOV_B32_dpp]], [[COPY]], implicit-def $exec, implicit-def $vcc_lo, implicit $mode, implicit $exec
-    ; GCN-NEXT: [[V_CMP_CLASS_F16_fake16_e64_dpp:%[0-9]+]]:sgpr_32 = V_CMP_CLASS_F16_fake16_e64_dpp 0, [[COPY1]], 0, [[COPY]], 1, 15, 15, 1, implicit $exec
-    ; GCN-NEXT: [[V_CMP_GE_F16_fake16_e64_dpp:%[0-9]+]]:sgpr_32 = V_CMP_GE_F16_fake16_e64_dpp 1, [[COPY1]], 0, [[COPY]], 1, 1, 15, 15, 1, implicit $mode, implicit $exec
-    ; GCN-NEXT: [[V_MOV_B32_dpp1:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[COPY1]], 1, 15, 15, 1, implicit $exec
-    ; GCN-NEXT: V_CMPX_GT_U32_nosdst_e64 [[V_MOV_B32_dpp1]], [[COPY]], implicit-def $exec, implicit $mode, implicit $exec
-    ; GCN-NEXT: V_CMP_CLASS_F32_e32_dpp 2, [[COPY1]], [[COPY]], 1, 15, 15, 1, implicit-def $vcc, implicit $exec
-    ; GCN-NEXT: V_CMP_NGE_F32_e32_dpp 0, [[COPY1]], 0, [[COPY]], 1, 15, 15, 1, implicit-def $vcc, implicit $mode, implicit $exec
-    ; GCN-NEXT: [[V_MOV_B32_dpp2:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[COPY1]], 1, 15, 15, 1, implicit $exec
-    ; GCN-NEXT: [[V_CMP_NGE_F16_fake16_e64_:%[0-9]+]]:sgpr_32 = V_CMP_NGE_F16_fake16_e64 0, [[V_CMP_NGE_F16_fake16_e64_]], 0, [[COPY]], 0, implicit $mode, implicit $exec
-    ; GCN-NEXT: [[V_CMP_NGE_F32_e64_dpp:%[0-9]+]]:sgpr_32 = V_CMP_NGE_F32_e64_dpp 0, [[COPY1]], 0, [[COPY]], 0, 1, 15, 15, 1, implicit $mode, implicit $exec
-    ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sgpr_32 = S_AND_B32 [[V_CMP_NGE_F32_e64_dpp]], 10101, implicit-def $scc
-    ; GCN-NEXT: V_CMP_GT_I32_e32_dpp [[COPY1]], [[COPY]], 1, 15, 15, 1, implicit-def $vcc, implicit $exec
+    ; GCN-TRUE16-LABEL: name: vopc
+    ; GCN-TRUE16: liveins: $vgpr0, $vgpr1, $vgpr2
+    ; GCN-TRUE16-NEXT: {{  $}}
+    ; GCN-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; GCN-TRUE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+    ; GCN-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+    ; GCN-TRUE16-NEXT: V_CMP_LT_F32_e32_dpp 0, [[COPY1]], 0, [[COPY]], 1, 15, 15, 1, implicit-def $vcc, implicit $mode, implicit $exec
+    ; GCN-TRUE16-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[COPY1]], 1, 15, 15, 1, implicit $exec
+    ; GCN-TRUE16-NEXT: V_CMPX_EQ_I16_fake16_nosdst_e64 [[V_MOV_B32_dpp]], [[COPY]], implicit-def $exec, implicit-def $vcc_lo, implicit $mode, implicit $exec
+    ; GCN-TRUE16-NEXT: [[V_MOV_B32_dpp1:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[COPY1]], 1, 15, 15, 1, implicit $exec
+    ; GCN-TRUE16-NEXT: [[V_CMP_CLASS_F16_fake16_e64_:%[0-9]+]]:sgpr_32 = V_CMP_CLASS_F16_fake16_e64 0, [[V_MOV_B32_dpp1]], 0, [[COPY]], implicit-def $vcc_lo, implicit $mode, implicit $exec
+    ; GCN-TRUE16-NEXT: [[V_MOV_B32_dpp2:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[COPY1]], 1, 15, 15, 1, implicit $exec
+    ; GCN-TRUE16-NEXT: [[V_CMP_GE_F16_fake16_e64_:%[0-9]+]]:sgpr_32 = V_CMP_GE_F16_fake16_e64 1, [[V_MOV_B32_dpp2]], 0, [[COPY]], 1, implicit $mode, implicit $exec
+    ; GCN-TRUE16-NEXT: [[V_MOV_B32_dpp3:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[COPY1]], 1, 15, 15, 1, implicit $exec
+    ; GCN-TRUE16-NEXT: V_CMPX_GT_U32_nosdst_e64 [[V_MOV_B32_dpp3]], [[COPY]], implicit-def $exec, implicit $mode, implicit $exec
+    ; GCN-TRUE16-NEXT: V_CMP_CLASS_F32_e32_dpp 2, [[COPY1]], [[COPY]], 1, 15, 15, 1, implicit-def $vcc, implicit $exec
+    ; GCN-TRUE16-NEXT: V_CMP_NGE_F32_e32_dpp 0, [[COPY1]], 0, [[COPY]], 1, 15, 15, 1, implicit-def $vcc, implicit $mode, implicit $exec
+    ; GCN-TRUE16-NEXT: [[V_MOV_B32_dpp4:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[COPY1]], 1, 15, 15, 1, implicit $exec
+    ; GCN-TRUE16-NEXT: [[V_CMP_NGE_F16_fake16_e64_:%[0-9]+]]:sgpr_32 = V_CMP_NGE_F16_fake16_e64 0, [[V_CMP_NGE_F16_fake16_e64_]], 0, [[COPY]], 0, implicit $mode, implicit $exec
+    ; GCN-TRUE16-NEXT: [[V_CMP_NGE_F32_e64_dpp:%[0-9]+]]:sgpr_32 = V_CMP_NGE_F32_e64_dpp 0, [[COPY1]], 0, [[COPY]], 0, 1, 15, 15, 1, implicit $mode, implicit $exec
+    ; GCN-TRUE16-NEXT: [[S_AND_B32_:%[0-9]+]]:sgpr_32 = S_AND_B32 [[V_CMP_NGE_F32_e64_dpp]], 10101, implicit-def $scc
+    ; GCN-TRUE16-NEXT: V_CMP_GT_I32_e32_dpp [[COPY1]], [[COPY]], 1, 15, 15, 1, implicit-def $vcc, implicit $exec
+    ;
+    ; GCN-FAKE16-LABEL: name: vopc
+    ; GCN-FAKE16: liveins: $vgpr0, $vgpr1, $vgpr2
+    ; GCN-FAKE16-NEXT: {{  $}}
+    ; GCN-FAKE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN-FAKE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; GCN-FAKE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+    ; GCN-FAKE16-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+    ; GCN-FAKE16-NEXT: V_CMP_LT_F32_e32_dpp 0, [[COPY1]], 0, [[COPY]], 1, 15, 15, 1, implicit-def $vcc, implicit $mode, implicit $exec
+    ; GCN-FAKE16-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[COPY1]], 1, 15, 15, 1, implicit $exec
+    ; GCN-FAKE16-NEXT: V_CMPX_EQ_I16_fake16_nosdst_e64 [[V_MOV_B32_dpp]], [[COPY]], implicit-def $exec, implicit-def $vcc_lo, implicit $mode, implicit $exec
+    ; GCN-FAKE16-NEXT: [[V_CMP_CLASS_F16_fake16_e64_dpp:%[0-9]+]]:sgpr_32 = V_CMP_CLASS_F16_fake16_e64_dpp 0, [[COPY1]], 0, [[COPY]], 1, 15, 15, 1, implicit $exec
+    ; GCN-FAKE16-NEXT: [[V_CMP_GE_F16_fake16_e64_dpp:%[0-9]+]]:sgpr_32 = V_CMP_GE_F16_fake16_e64_dpp 1, [[COPY1]], 0, [[COPY]], 1, 1, 15, 15, 1, implicit $mode, implicit $exec
+    ; GCN-FAKE16-NEXT: [[V_MOV_B32_dpp1:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[COPY1]], 1, 15, 15, 1, implicit $exec
+    ; GCN-FAKE16-NEXT: V_CMPX_GT_U32_nosdst_e64 [[V_MOV_B32_dpp1]], [[COPY]], implicit-def $exec, implicit $mode, implicit $exec
+    ; GCN-FAKE16-NEXT: V_CMP_CLASS_F32_e32_dpp 2, [[COPY1]], [[COPY]], 1, 15, 15, 1, implicit-def $vcc, implicit $exec
+    ; GCN-FAKE16-NEXT: V_CMP_NGE_F32_e32_dpp 0, [[COPY1]], 0, [[COPY]], 1, 15, 15, 1, implicit-def $vcc, implicit $mode, implicit $exec
+    ; GCN-FAKE16-NEXT: [[V_MOV_B32_dpp2:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[COPY1]], 1, 15, 15, 1, implicit $exec
+    ; GCN-FAKE16-NEXT: [[V_CMP_NGE_F16_fake16_e64_:%[0-9]+]]:sgpr_32 = V_CMP_NGE_F16_fake16_e64 0, [[V_CMP_NGE_F16_fake16_e64_]], 0, [[COPY]], 0, implicit $mode, implicit $exec
+    ; GCN-FAKE16-NEXT: [[V_CMP_NGE_F32_e64_dpp:%[0-9]+]]:sgpr_32 = V_CMP_NGE_F32_e64_dpp 0, [[COPY1]], 0, [[COPY]], 0, 1, 15, 15, 1, implicit $mode, implicit $exec
+    ; GCN-FAKE16-NEXT: [[S_AND_B32_:%[0-9]+]]:sgpr_32 = S_AND_B32 [[V_CMP_NGE_F32_e64_dpp]], 10101, implicit-def $scc
+    ; GCN-FAKE16-NEXT: V_CMP_GT_I32_e32_dpp [[COPY1]], [[COPY]], 1, 15, 15, 1, implicit-def $vcc, implicit $exec
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = COPY $vgpr2
diff --git a/llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll b/llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
index bac70b69650cd..d41720e19c217 100644
--- a/llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
+++ b/llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
@@ -1,7 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -amdgpu-codegenprepare-widen-constant-loads=0 -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=SI %s
 ; RUN: llc -amdgpu-codegenprepare-widen-constant-loads=0 -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=VI %s
-; RUN: llc -amdgpu-codegenprepare-widen-constant-loads=0 -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX11 %s
+; RUN: llc -amdgpu-codegenprepare-widen-constant-loads=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -amdgpu-codegenprepare-widen-constant-loads=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define amdgpu_kernel void @widen_i16_constant_load(ptr addrspace(4) %arg) {
 ; SI-LABEL: widen_i16_constant_load:
@@ -257,17 +258,29 @@ define amdgpu_kernel void @widen_f16_constant_load(ptr addrspace(4) %arg) {
 ; VI-NEXT:    flat_store_short v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: widen_f16_constant_load:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    v_mov_b32_e32 v1, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_load_b32 s0, s[0:1], 0x0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_add_f16_e64 v2, s0, 4.0
-; GFX11-NEXT:    global_store_b16 v[0:1], v2, off
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: widen_f16_constant_load:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_load_b32 s0, s[0:1], 0x0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_f16_e64 v0.l, s0, 4.0
+; GFX11-TRUE16-NEXT:    global_store_b16 v[1:2], v0, off
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: widen_f16_constant_load:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_load_b32 s0, s[0:1], 0x0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_f16_e64 v2, s0, 4.0
+; GFX11-FAKE16-NEXT:    global_store_b16 v[0:1], v2, off
+; GFX11-FAKE16-NEXT:    s_endpgm
   %load = load half, ptr addrspace(4) %arg, align 4
   %add = fadd half %load, 4.0
   store half %add, ptr addrspace(1) null
@@ -377,22 +390,37 @@ define amdgpu_kernel void @no_widen_i16_constant_divergent_load(ptr addrspace(4)
 ; VI-NEXT:    flat_store_short v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: no_widen_i16_constant_divergent_load:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_u16 v0, v0, s[0:1]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_add_nc_u16 v2, 0x3e7, v0
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-NEXT:    v_mov_b32_e32 v1, 0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT:    v_or_b32_e32 v2, 4, v2
-; GFX11-NEXT:    global_store_b16 v[0:1], v2, off
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: no_widen_i16_constant_divergent_load:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x3e7, v0.l
+; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, 4
+; GFX11-TRUE16-NEXT:    global_store_b16 v[1:2], v0, off
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: no_widen_i16_constant_divergent_load:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_u16 v0, v0, s[0:1]
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, 0x3e7, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, 4, v2
+; GFX11-FAKE16-NEXT:    global_store_b16 v[0:1], v2, off
+; GFX11-FAKE16-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %tid.ext = zext i32 %tid to i64
   %gep.arg = getelementptr inbounds i16, ptr addrspace(4) %arg, i64 %tid.ext
diff --git a/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll b/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
index 98da9ef2e8819..436825ed56d45 100644
--- a/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
+++ b/llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX12
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -mattr=+wavefrontsize64 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GFX12,GFX12-TRUE16
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -mattr=+wavefrontsize64 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GFX12,GFX12-FAKE16
 
 define amdgpu_ps void @test_wmma_f32_16x16x16_f16_negA(<4 x half> %A, <4 x half> %B, <4 x float> %C, ptr addrspace(1) %out) {
 ; GFX12-LABEL: test_wmma_f32_16x16x16_f16_negA:
@@ -366,16 +367,28 @@ bb:
 ; pack f16 elements with v_perm_b32 since they don't come from same b32
 
 define amdgpu_ps void @test_wmma_f16_16x16x16_f16_negC_pack(<4 x half> %A, <4 x half> %B, ptr %Caddr, ptr addrspace(1) %out) {
-; GFX12-LABEL: test_wmma_f16_16x16x16_f16_negC_pack:
-; GFX12:       ; %bb.0: ; %bb
-; GFX12-NEXT:    flat_load_b128 v[8:11], v[4:5]
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    v_perm_b32 v5, v11, v10, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v4, v9, v8, 0x5040100
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_wmma_f16_16x16x16_f16 v[4:5], v[0:1], v[2:3], v[4:5] neg_lo:[0,0,1]
-; GFX12-NEXT:    global_store_b64 v[6:7], v[4:5], off
-; GFX12-NEXT:    s_endpgm
+; GFX12-TRUE16-LABEL: test_wmma_f16_16x16x16_f16_negC_pack:
+; GFX12-TRUE16:       ; %bb.0: ; %bb
+; GFX12-TRUE16-NEXT:    flat_load_b128 v[8:11], v[4:5]
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v10.h, v11.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v8.h, v9.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v9, v10
+; GFX12-TRUE16-NEXT:    v_wmma_f16_16x16x16_f16 v[8:9], v[0:1], v[2:3], v[8:9] neg_lo:[0,0,1]
+; GFX12-TRUE16-NEXT:    global_store_b64 v[6:7], v[8:9], off
+; GFX12-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-FAKE16-LABEL: test_wmma_f16_16x16x16_f16_negC_pack:
+; GFX12-FAKE16:       ; %bb.0: ; %bb
+; GFX12-FAKE16-NEXT:    flat_load_b128 v[8:11], v[4:5]
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    v_perm_b32 v5, v11, v10, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v4, v9, v8, 0x5040100
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_wmma_f16_16x16x16_f16 v[4:5], v[0:1], v[2:3], v[4:5] neg_lo:[0,0,1]
+; GFX12-FAKE16-NEXT:    global_store_b64 v[6:7], v[4:5], off
+; GFX12-FAKE16-NEXT:    s_endpgm
 bb:
   %C = load <8 x half>, ptr %Caddr
   %C_shuffle = shufflevector <8 x half> %C, <8 x half> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
diff --git a/llvm/test/CodeGen/AMDGPU/wwm-reserved.ll b/llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
index ddc50b7d49504..68010fc45b5a5 100644
--- a/llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
+++ b/llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
@@ -1723,5 +1723,3 @@ declare void @llvm.amdgcn.raw.ptr.buffer.store.v4f32(<4 x float>, ptr addrspace(
 declare <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32>, i32, i32)
 declare <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32>, i32, i32)
 
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
diff --git a/llvm/test/CodeGen/ARM/popcnt.ll b/llvm/test/CodeGen/ARM/popcnt.ll
index edcae5e141e73..a70fdc580ca9b 100644
--- a/llvm/test/CodeGen/ARM/popcnt.ll
+++ b/llvm/test/CodeGen/ARM/popcnt.ll
@@ -352,7 +352,7 @@ define i32 @ctpop32(i32 %x) nounwind readnone {
   ret i32 %count
 }
 
-define i32 @ctpop64(i64 %x) nounwind readnone {
+define i64 @ctpop64(i64 %x) nounwind readnone {
 ; CHECK-LABEL: ctpop64:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    .save {r4, lr}
@@ -379,6 +379,7 @@ define i32 @ctpop64(i64 %x) nounwind readnone {
 ; CHECK-NEXT:    mul r1, r0, r12
 ; CHECK-NEXT:    lsr r0, r2, #24
 ; CHECK-NEXT:    add r0, r0, r1, lsr #24
+; CHECK-NEXT:    mov r1, #0
 ; CHECK-NEXT:    pop {r4, lr}
 ; CHECK-NEXT:    mov pc, lr
 ; CHECK-NEXT:    .p2align 2
@@ -392,8 +393,7 @@ define i32 @ctpop64(i64 %x) nounwind readnone {
 ; CHECK-NEXT:  .LCPI23_3:
 ; CHECK-NEXT:    .long 858993459 @ 0x33333333
   %count = tail call i64 @llvm.ctpop.i64(i64 %x)
-  %conv = trunc i64 %count to i32
-  ret i32 %conv
+  ret i64 %count
 }
 
 define i32 @ctpop_eq_one(i64 %x) nounwind readnone {
diff --git a/llvm/test/CodeGen/AVR/inline-asm/inline-asm-invalid.ll b/llvm/test/CodeGen/AVR/inline-asm/inline-asm-invalid.ll
index 416eb19c29db9..be54b4464f08c 100644
--- a/llvm/test/CodeGen/AVR/inline-asm/inline-asm-invalid.ll
+++ b/llvm/test/CodeGen/AVR/inline-asm/inline-asm-invalid.ll
@@ -21,3 +21,9 @@ define void @foo2() {
   call void asm sideeffect "ldd r24, X+2", ""()
   ret void
 }
+
+define void @foo3() {
+  ; AVR6: error: value out of range for constraint 'I'
+  call void asm sideeffect "out $0, r20", "I"(i16 64)
+  ret void
+}
diff --git a/llvm/test/CodeGen/DirectX/ForwardHandleAccesses/alloca.ll b/llvm/test/CodeGen/DirectX/ForwardHandleAccesses/alloca.ll
new file mode 100644
index 0000000000000..f9abfbddeae57
--- /dev/null
+++ b/llvm/test/CodeGen/DirectX/ForwardHandleAccesses/alloca.ll
@@ -0,0 +1,20 @@
+; RUN: not opt -S -dxil-forward-handle-accesses -mtriple=dxil--shadermodel6.3-library %s 2>&1 | FileCheck %s
+
+; CHECK: error: Load of "buf" is not a global resource handle
+
+%"class.hlsl::RWStructuredBuffer" = type { target("dx.RawBuffer", <4 x float>, 1, 0) }
+@Buf = internal global %"class.hlsl::RWStructuredBuffer" poison, align 4
+
+define float @f() {
+entry:
+  %buf = alloca target("dx.RawBuffer", <4 x float>, 1, 0), align 4
+  %h = call target("dx.RawBuffer", <4 x float>, 1, 0) @llvm.dx.resource.handlefrombinding(i32 0, i32 0, i32 1, i32 0, i1 false)
+  store target("dx.RawBuffer", <4 x float>, 1, 0) %h, ptr %buf, align 4
+
+  %b = load target("dx.RawBuffer", <4 x float>, 1, 0), ptr %buf, align 4
+  %l = call { <4 x float>, i1 } @llvm.dx.resource.load.rawbuffer(target("dx.RawBuffer", <4 x float>, 1, 0) %b, i32 0, i32 0)
+  %x = extractvalue { <4 x float>, i1 } %l, 0
+  %v = extractelement <4 x float> %x, i32 0
+
+  ret float %v
+}
diff --git a/llvm/test/CodeGen/DirectX/ForwardHandleAccesses/ambiguous.ll b/llvm/test/CodeGen/DirectX/ForwardHandleAccesses/ambiguous.ll
new file mode 100644
index 0000000000000..62cd04e0032fb
--- /dev/null
+++ b/llvm/test/CodeGen/DirectX/ForwardHandleAccesses/ambiguous.ll
@@ -0,0 +1,21 @@
+; RUN: not opt -S -dxil-forward-handle-accesses -mtriple=dxil--shadermodel6.3-library %s 2>&1 | FileCheck %s
+
+; CHECK: error: Handle at "h2" overwrites handle at "h1"
+
+%"class.hlsl::RWStructuredBuffer" = type { target("dx.RawBuffer", <4 x float>, 1, 0) }
+@Buf = internal global %"class.hlsl::RWStructuredBuffer" poison, align 4
+
+define float @f() {
+entry:
+  %h1 = call target("dx.RawBuffer", <4 x float>, 1, 0) @llvm.dx.resource.handlefrombinding(i32 0, i32 0, i32 1, i32 0, i1 false)
+  store target("dx.RawBuffer", <4 x float>, 1, 0) %h1, ptr @Buf, align 4
+  %h2 = call target("dx.RawBuffer", <4 x float>, 1, 0) @llvm.dx.resource.handlefrombinding(i32 0, i32 1, i32 1, i32 0, i1 false)
+  store target("dx.RawBuffer", <4 x float>, 1, 0) %h2, ptr @Buf, align 4
+
+  %b = load target("dx.RawBuffer", <4 x float>, 1, 0), ptr @Buf, align 4
+  %l = call { <4 x float>, i1 } @llvm.dx.resource.load.rawbuffer(target("dx.RawBuffer", <4 x float>, 1, 0) %b, i32 0, i32 0)
+  %x = extractvalue { <4 x float>, i1 } %l, 0
+  %v = extractelement <4 x float> %x, i32 0
+
+  ret float %v
+}
diff --git a/llvm/test/CodeGen/DirectX/ForwardHandleAccesses/buffer-O0.ll b/llvm/test/CodeGen/DirectX/ForwardHandleAccesses/buffer-O0.ll
new file mode 100644
index 0000000000000..880fefd57e029
--- /dev/null
+++ b/llvm/test/CodeGen/DirectX/ForwardHandleAccesses/buffer-O0.ll
@@ -0,0 +1,44 @@
+; RUN: opt -S -dxil-forward-handle-accesses -mtriple=dxil--shadermodel6.3-library %s | FileCheck %s
+
+%"class.hlsl::RWStructuredBuffer" = type { target("dx.RawBuffer", <4 x float>, 1, 0) }
+
+@_ZL2In = internal global %"class.hlsl::RWStructuredBuffer" poison, align 4
+@_ZL3Out = internal global %"class.hlsl::RWStructuredBuffer" poison, align 4
+
+define void @main() #1 {
+entry:
+  %this.addr.i.i.i = alloca ptr, align 4
+  %this.addr.i.i = alloca ptr, align 4
+  %this.addr.i1 = alloca ptr, align 4
+  %Index.addr.i2 = alloca i32, align 4
+  %this.addr.i = alloca ptr, align 4
+  %Index.addr.i = alloca i32, align 4
+  ; CHECK: [[IN:%.*]] = call target("dx.RawBuffer", <4 x float>, 1, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_v4f32_1_0t(i32 0, i32 0, i32 1, i32 0, i1 false)
+  %_ZL2In_h.i.i = call target("dx.RawBuffer", <4 x float>, 1, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_v4f32_1_0t(i32 0, i32 0, i32 1, i32 0, i1 false)
+  store target("dx.RawBuffer", <4 x float>, 1, 0) %_ZL2In_h.i.i, ptr @_ZL2In, align 4
+  store ptr @_ZL2In, ptr %this.addr.i.i, align 4
+  %this1.i.i = load ptr, ptr %this.addr.i.i, align 4
+  ; CHECK: [[OUT:%.*]] = call target("dx.RawBuffer", <4 x float>, 1, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_v4f32_1_0t(i32 0, i32 1, i32 1, i32 0, i1 false)
+  %_ZL3Out_h.i.i = call target("dx.RawBuffer", <4 x float>, 1, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_v4f32_1_0t(i32 0, i32 1, i32 1, i32 0, i1 false)
+  store target("dx.RawBuffer", <4 x float>, 1, 0) %_ZL3Out_h.i.i, ptr @_ZL3Out, align 4
+  store ptr @_ZL3Out, ptr %this.addr.i.i.i, align 4
+  %this1.i.i.i = load ptr, ptr %this.addr.i.i.i, align 4
+  store ptr @_ZL2In, ptr %this.addr.i1, align 4
+  store i32 0, ptr %Index.addr.i2, align 4
+  %this1.i3 = load ptr, ptr %this.addr.i1, align 4
+  ; CHECK-NOT: load target("dx.RawBuffer", <4 x float>, 1, 0)
+  %0 = load target("dx.RawBuffer", <4 x float>, 1, 0), ptr %this1.i3, align 4
+  %1 = load i32, ptr %Index.addr.i2, align 4
+  ; CHECK: call { <4 x float>, i1 } @llvm.dx.resource.load.rawbuffer.v4f32.tdx.RawBuffer_v4f32_1_0t(target("dx.RawBuffer", <4 x float>, 1, 0) [[IN]],
+  %2 = call { <4 x float>, i1 } @llvm.dx.resource.load.rawbuffer.v4f32.tdx.RawBuffer_v4f32_1_0t(target("dx.RawBuffer", <4 x float>, 1, 0) %0, i32 %1, i32 0)
+  %3 = extractvalue { <4 x float>, i1 } %2, 0
+  store ptr @_ZL3Out, ptr %this.addr.i, align 4
+  store i32 0, ptr %Index.addr.i, align 4
+  %this1.i = load ptr, ptr %this.addr.i, align 4
+  ; CHECK-NOT: load target("dx.RawBuffer", <4 x float>, 1, 0)
+  %4 = load target("dx.RawBuffer", <4 x float>, 1, 0), ptr %this1.i, align 4
+  %5 = load i32, ptr %Index.addr.i, align 4
+  ; CHECK: call void @llvm.dx.resource.store.rawbuffer.tdx.RawBuffer_v4f32_1_0t.v4f32(target("dx.RawBuffer", <4 x float>, 1, 0) [[OUT]],
+  call void @llvm.dx.resource.store.rawbuffer.tdx.RawBuffer_v4f32_1_0t.v4f32(target("dx.RawBuffer", <4 x float>, 1, 0) %4, i32 %5, i32 0, <4 x float> %3)
+  ret void
+}
diff --git a/llvm/test/CodeGen/DirectX/ForwardHandleAccesses/cbuffer-access.ll b/llvm/test/CodeGen/DirectX/ForwardHandleAccesses/cbuffer-access.ll
new file mode 100644
index 0000000000000..7790cd3ad2ec6
--- /dev/null
+++ b/llvm/test/CodeGen/DirectX/ForwardHandleAccesses/cbuffer-access.ll
@@ -0,0 +1,23 @@
+; RUN: opt -S -dxil-forward-handle-accesses -mtriple=dxil--shadermodel6.3-library %s | FileCheck %s
+
+%__cblayout_CB = type <{ float, i32, i32 }>
+%struct.Scalars = type { float, i32, i32 }
+
+@CB.cb = local_unnamed_addr global target("dx.CBuffer", target("dx.Layout", %__cblayout_CB, 12, 0, 4, 8)) poison
+
+define void @main() local_unnamed_addr #1 {
+entry:
+  ; CHECK: [[CB:%.*]] = tail call target({{.*}}) @llvm.dx.resource.handlefrombinding
+  %h = tail call target("dx.CBuffer", target("dx.Layout", %__cblayout_CB, 12, 0, 4, 8)) @llvm.dx.resource.handlefrombinding(i32 0, i32 0, i32 1, i32 0, i1 false)
+  store target("dx.CBuffer", target("dx.Layout", %__cblayout_CB, 12, 0, 4, 8)) %h, ptr @CB.cb, align 4
+  %_ZL3Out_h.i.i = tail call target("dx.RawBuffer", %struct.Scalars, 1, 0) @llvm.dx.resource.handlefrombinding(i32 0, i32 0, i32 1, i32 0, i1 false)
+  ; CHECK-NOT: load target({{.*}}), ptr @CB.cb
+  %cb = load target("dx.CBuffer", target("dx.Layout", %__cblayout_CB, 12, 0, 4, 8)), ptr @CB.cb, align 4
+  ; CHECK: call { float, float, float, float } @llvm.dx.resource.load.cbufferrow.4.{{.*}}(target({{.*}}) [[CB]], i32 0)
+  %0 = call { float, float, float, float } @llvm.dx.resource.load.cbufferrow.4(target("dx.CBuffer", target("dx.Layout", %__cblayout_CB, 12, 0, 4, 8)) %cb, i32 0)
+  %1 = extractvalue { float, float, float, float } %0, 0
+  call void @llvm.dx.resource.store.rawbuffer(target("dx.RawBuffer", %struct.Scalars, 1, 0) %_ZL3Out_h.i.i, i32 0, i32 0, float %1)
+  ret void
+}
+
+attributes #0 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, argmem: write, inaccessiblemem: none) "approx-func-fp-math"="false" "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
diff --git a/llvm/test/CodeGen/DirectX/ForwardHandleAccesses/undominated.ll b/llvm/test/CodeGen/DirectX/ForwardHandleAccesses/undominated.ll
new file mode 100644
index 0000000000000..03406ca97c62f
--- /dev/null
+++ b/llvm/test/CodeGen/DirectX/ForwardHandleAccesses/undominated.ll
@@ -0,0 +1,16 @@
+; RUN: not opt -S -dxil-forward-handle-accesses -mtriple=dxil--shadermodel6.3-library %s 2>&1 | FileCheck %s
+
+; CHECK: error: Load at "b" is not dominated by handle creation at "h1"
+
+%"class.hlsl::RWStructuredBuffer" = type { target("dx.RawBuffer", <4 x float>, 1, 0) }
+@Buf = internal global %"class.hlsl::RWStructuredBuffer" poison, align 4
+
+define void @f() {
+entry:
+  %b = load target("dx.RawBuffer", <4 x float>, 1, 0), ptr @Buf, align 4
+
+  %h1 = call target("dx.RawBuffer", <4 x float>, 1, 0) @llvm.dx.resource.handlefrombinding(i32 0, i32 0, i32 1, i32 0, i1 false)
+  store target("dx.RawBuffer", <4 x float>, 1, 0) %h1, ptr @Buf, align 4
+
+  ret void
+}
diff --git a/llvm/test/CodeGen/DirectX/llc-pipeline.ll b/llvm/test/CodeGen/DirectX/llc-pipeline.ll
index b1bd9f16f4efa..729258d27aec1 100644
--- a/llvm/test/CodeGen/DirectX/llc-pipeline.ll
+++ b/llvm/test/CodeGen/DirectX/llc-pipeline.ll
@@ -22,7 +22,8 @@
 ; CHECK-NEXT:     DXIL Resource Access
 ; CHECK-NEXT:     Dominator Tree Construction
 ; CHECK-NEXT:     Scalarize vector operations
-; CHECK-NEXT:   DXIL Legalizer
+; CHECK-NEXT:     DXIL Forward Handle Accesses
+; CHECK-NEXT:     DXIL Legalizer
 ; CHECK-NEXT:   DXIL Resource Binding Analysis
 ; CHECK-NEXT:   DXIL Module Metadata analysis
 ; CHECK-NEXT:   DXIL Shader Flag Analysis
diff --git a/llvm/test/CodeGen/Hexagon/swp-alias-cross-iteration.mir b/llvm/test/CodeGen/Hexagon/swp-alias-cross-iteration.mir
new file mode 100644
index 0000000000000..8163074b589d8
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/swp-alias-cross-iteration.mir
@@ -0,0 +1,72 @@
+# RUN: llc -mtriple=hexagon -run-pass pipeliner -debug-only=pipeliner %s -o /dev/null 2>&1 | FileCheck %s
+# REQUIRES: asserts
+
+# Test that pipeliner correctly detects the loop-carried dependency between the
+# load and the store, which is indicated by `Ord` dependency from SU(2) to
+# SU(4). Note that there is no dependency within a single iteration.
+
+# CHECK:      SU(2):   %7:intregs = L2_loadri_io %5:intregs, 0 :: (load (s32) from %ir.ptr.load)
+# CHECK-NEXT:   # preds left
+# CHECK-NEXT:   # succs left
+# CHECK-NEXT:   # rdefs left
+# CHECK-NEXT:   Latency
+# CHECK-NEXT:   Depth
+# CHECK-NEXT:   Height
+# CHECK-NEXT:   Predecessors:
+# CHECK-NEXT:     SU(0): Data Latency=0 Reg=%5
+# CHECK-NEXT:   Successors:
+# CHECK-DAG:      SU(3): Data Latency=2 Reg=%7
+# CHECK-DAG:      SU(4): Ord  Latency=1 Barrier
+# CHECK-NEXT: SU(3):   %8:intregs = F2_sfadd %7:intregs, %3:intregs, implicit $usr
+# CHECK:      SU(4):   S2_storeri_io %6:intregs, 0, %8:intregs :: (store (s32) into %ir.ptr.store)
+
+
+--- |
+  define void @foo(ptr noalias %p0, ptr noalias %p1, i32 %n) {
+  entry:
+    br label %body
+  
+  body:                                             ; preds = %body, %entry
+    %i = phi i32 [ 0, %entry ], [ %i.next, %body ]
+    %ptr.load = phi ptr [ %p0, %entry ], [ %p1, %body ]
+    %ptr.store = phi ptr [ %p1, %entry ], [ %p0, %body ]
+    %v = load float, ptr %ptr.load, align 4
+    %add = fadd float %v, 1.000000e+00
+    store float %add, ptr %ptr.store, align 4
+    %i.next = add i32 %i, 1
+    %cond = icmp slt i32 %i.next, %n
+    br i1 %cond, label %body, label %exit
+  
+  exit:                                             ; preds = %body
+    ret void
+  }
+...
+---
+name:            foo
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    successors: %bb.1(0x80000000)
+    liveins: $r0, $r1, $r2
+  
+    %6:intregs = COPY $r2
+    %5:intregs = COPY $r1
+    %4:intregs = COPY $r0
+    %9:intregs = A2_tfrsi 1065353216
+    %12:intregs = COPY %6
+    J2_loop0r %bb.1, %12, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
+  
+  bb.1.body (machine-block-address-taken):
+    successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+  
+    %1:intregs = PHI %4, %bb.0, %5, %bb.1
+    %2:intregs = PHI %5, %bb.0, %4, %bb.1
+    %8:intregs = L2_loadri_io %1, 0 :: (load (s32) from %ir.ptr.load)
+    %10:intregs = F2_sfadd killed %8, %9, implicit $usr
+    S2_storeri_io %2, 0, killed %10 :: (store (s32) into %ir.ptr.store)
+    ENDLOOP0 %bb.1, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
+    J2_jump %bb.2, implicit-def dead $pc
+  
+  bb.2.exit:
+    PS_jmpret $r31, implicit-def dead $pc
+...
diff --git a/llvm/test/CodeGen/Hexagon/swp-no-alias.mir b/llvm/test/CodeGen/Hexagon/swp-no-alias.mir
new file mode 100644
index 0000000000000..38b7212702ff9
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/swp-no-alias.mir
@@ -0,0 +1,151 @@
+# RUN: llc -mtriple=hexagon -run-pass pipeliner -debug-only=pipeliner %s -o /dev/null 2>&1 | FileCheck %s
+# REQUIRES: asserts
+
+# Test that there are no loop-carried dependencies between all memory instructions.
+
+# CHECK:      SU(0):   %8:intregs = PHI %1:intregs, %bb.1, %9:intregs, %bb.2
+# CHECK-NEXT:   # preds left
+# CHECK-NEXT:   # succs left
+# CHECK-NEXT:   # rdefs left
+# CHECK-NEXT:   Latency
+# CHECK-NEXT:   Depth
+# CHECK-NEXT:   Height
+# CHECK-NEXT:   Successors:
+# CHECK-DAG:      SU(6): Data Latency=0 Reg=%8
+# CHECK-DAG:      SU(5): Data Latency=0 Reg=%8
+# CHECK-DAG:      SU(3): Data Latency=0 Reg=%8
+# CHECK-DAG:      SU(6): Anti Latency=1
+# CHECK-NEXT: SU(1):   %10:intregs = PHI %2:intregs, %bb.1, %11:intregs, %bb.2
+# CHECK-NEXT:   # preds left
+# CHECK-NEXT:   # succs left
+# CHECK-NEXT:   # rdefs left
+# CHECK-NEXT:   Latency
+# CHECK-NEXT:   Depth
+# CHECK-NEXT:   Height
+# CHECK-NEXT:   Successors:
+# CHECK-DAG:      SU(7): Data Latency=0 Reg=%10
+# CHECK-DAG:      SU(4): Data Latency=0 Reg=%10
+# CHECK-DAG:      SU(2): Data Latency=0 Reg=%10
+# CHECK-DAG:      SU(7): Anti Latency=1
+# CHECK-NEXT: SU(2):   %12:hvxvr = V6_vL32b_ai %10:intregs, 0 :: (load (s1024) from %ir.iptr.09, !tbaa !4)
+# CHECK-NEXT:   # preds left
+# CHECK-NEXT:   # succs left
+# CHECK-NEXT:   # rdefs left
+# CHECK-NEXT:   Latency
+# CHECK-NEXT:   Depth
+# CHECK-NEXT:   Height
+# CHECK-NEXT:   Predecessors:
+# CHECK-NEXT:     SU(1): Data Latency=0 Reg=%10
+# CHECK-NEXT:   Successors:
+# CHECK-NEXT:     SU(3): Data Latency=0 Reg=%12
+# CHECK-NEXT: SU(3):   V6_vS32b_ai %8:intregs, 0, %12:hvxvr :: (store (s1024) into %ir.optr.010, !tbaa !4)
+# CHECK-NEXT:   # preds left
+# CHECK-NEXT:   # succs left
+# CHECK-NEXT:   # rdefs left
+# CHECK-NEXT:   Latency
+# CHECK-NEXT:   Depth
+# CHECK-NEXT:   Height
+# CHECK-NEXT:   Predecessors:
+# CHECK-DAG:      SU(2): Data Latency=0 Reg=%12
+# CHECK-DAG:      SU(0): Data Latency=0 Reg=%8
+# CHECK-NEXT: SU(4):   %13:hvxvr = V6_vL32b_ai %10:intregs, 128 :: (load (s1024) from %ir.cgep, !tbaa !4)
+# CHECK-NEXT:   # preds left
+# CHECK-NEXT:   # succs left
+# CHECK-NEXT:   # rdefs left
+# CHECK-NEXT:   Latency
+# CHECK-NEXT:   Depth
+# CHECK-NEXT:   Height
+# CHECK-NEXT:   Predecessors:
+# CHECK-NEXT:     SU(1): Data Latency=0 Reg=%10
+# CHECK-NEXT:   Successors:
+# CHECK-NEXT:     SU(5): Data Latency=0 Reg=%13
+# CHECK-NEXT: SU(5):   V6_vS32b_ai %8:intregs, 128, %13:hvxvr :: (store (s1024) into %ir.cgep3, !tbaa !4)
+
+
+
+
+--- |
+  define dso_local void @foo(ptr noundef readonly captures(none) %in, ptr noalias noundef writeonly captures(none) %out, i32 noundef %width) local_unnamed_addr #0 {
+  entry:
+    %cmp7 = icmp sgt i32 %width, 0
+    br i1 %cmp7, label %for.body.preheader, label %for.end
+  
+  for.body.preheader:                               ; preds = %entry
+    %0 = add i32 %width, 128
+    br label %for.body
+  
+  for.body:                                         ; preds = %for.body.preheader, %for.body
+    %lsr.iv = phi i32 [ %0, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
+    %optr.010 = phi ptr [ %cgep4, %for.body ], [ %out, %for.body.preheader ]
+    %iptr.09 = phi ptr [ %cgep5, %for.body ], [ %in, %for.body.preheader ]
+    %ald = load <128 x i8>, ptr %iptr.09, align 128, !tbaa !4
+    %cst = bitcast <128 x i8> %ald to <32 x i32>
+    store <32 x i32> %cst, ptr %optr.010, align 128, !tbaa !4
+    %cgep = getelementptr i8, ptr %iptr.09, i32 128
+    %ald1 = load <128 x i8>, ptr %cgep, align 128, !tbaa !4
+    %cst2 = bitcast <128 x i8> %ald1 to <32 x i32>
+    %cgep3 = getelementptr i8, ptr %optr.010, i32 128
+    store <32 x i32> %cst2, ptr %cgep3, align 128, !tbaa !4
+    %lsr.iv.next = add i32 %lsr.iv, -128
+    %cmp = icmp samesign ugt i32 %lsr.iv.next, 128
+    %cgep4 = getelementptr i8, ptr %optr.010, i32 256
+    %cgep5 = getelementptr i8, ptr %iptr.09, i32 256
+    br i1 %cmp, label %for.body, label %for.end
+  
+  for.end:                                          ; preds = %for.body, %entry
+    ret void
+  }
+  
+  attributes #0 = { "target-cpu"="hexagonv60" "target-features"="+hvx-length128b,+hvxv69,+v66,-long-calls" }
+  
+  !llvm.module.flags = !{!0, !1, !2, !3}
+  
+  !0 = !{i32 1, !"wchar_size", i32 4}
+  !1 = !{i32 8, !"PIC Level", i32 2}
+  !2 = !{i32 7, !"PIE Level", i32 2}
+  !3 = !{i32 7, !"frame-pointer", i32 2}
+  !4 = !{!5, !5, i64 0}
+  !5 = !{!"omnipotent char", !6, i64 0}
+  !6 = !{!"Simple C/C++ TBAA"}
+...
+---
+name:            foo
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    successors: %bb.1(0x50000000), %bb.3(0x30000000)
+    liveins: $r0, $r1, $r2
+  
+    %9:intregs = COPY $r2
+    %8:intregs = COPY $r1
+    %7:intregs = COPY $r0
+    %10:predregs = C2_cmpgti %9, 0
+    J2_jumpf %10, %bb.3, implicit-def dead $pc
+    J2_jump %bb.1, implicit-def dead $pc
+  
+  bb.1.for.body.preheader:
+    successors: %bb.2(0x80000000)
+  
+    %0:intregs = A2_addi %9, 128
+    %15:intregs = A2_addi %0, -1
+    %16:intregs = S2_lsr_i_r %15, 7
+    %17:intregs = COPY %16
+    J2_loop0r %bb.2, %17, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
+  
+  bb.2.for.body (machine-block-address-taken):
+    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+  
+    %2:intregs = PHI %8, %bb.1, %5, %bb.2
+    %3:intregs = PHI %7, %bb.1, %6, %bb.2
+    %12:hvxvr = V6_vL32b_ai %3, 0 :: (load (s1024) from %ir.iptr.09, !tbaa !4)
+    V6_vS32b_ai %2, 0, killed %12 :: (store (s1024) into %ir.optr.010, !tbaa !4)
+    %13:hvxvr = V6_vL32b_ai %3, 128 :: (load (s1024) from %ir.cgep, !tbaa !4)
+    V6_vS32b_ai %2, 128, killed %13 :: (store (s1024) into %ir.cgep3, !tbaa !4)
+    %5:intregs = A2_addi %2, 256
+    %6:intregs = A2_addi %3, 256
+    ENDLOOP0 %bb.2, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
+    J2_jump %bb.3, implicit-def dead $pc
+  
+  bb.3.for.end:
+    PS_jmpret $r31, implicit-def dead $pc
+...
diff --git a/llvm/test/CodeGen/LoongArch/lasx/widen-shuffle-mask.ll b/llvm/test/CodeGen/LoongArch/lasx/widen-shuffle-mask.ll
new file mode 100644
index 0000000000000..c32a60622f2a1
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lasx/widen-shuffle-mask.ll
@@ -0,0 +1,137 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+
+define <32 x i8> @widen_shuffle_mask_v32i8_to_v16i16(<32 x i8> %a, <32 x i8> %b) {
+; CHECK-LABEL: widen_shuffle_mask_v32i8_to_v16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI0_0)
+; CHECK-NEXT:    xvld $xr2, $a0, %pc_lo12(.LCPI0_0)
+; CHECK-NEXT:    xvshuf.b $xr0, $xr1, $xr0, $xr2
+; CHECK-NEXT:    ret
+    %r = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 32, i32 33, i32 34, i32 35, i32 24, i32 25, i32 26, i32 27, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 60, i32 61, i32 30, i32 31>
+    ret <32 x i8> %r
+}
+
+define <32 x i8> @widen_shuffle_mask_v32i8_to_v8i32(<32 x i8> %a, <32 x i8> %b) {
+; CHECK-LABEL: widen_shuffle_mask_v32i8_to_v8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI1_0)
+; CHECK-NEXT:    xvld $xr2, $a0, %pc_lo12(.LCPI1_0)
+; CHECK-NEXT:    xvshuf.b $xr0, $xr1, $xr0, $xr2
+; CHECK-NEXT:    ret
+    %r = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 32, i32 33, i32 34, i32 35, i32 24, i32 25, i32 26, i32 27, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 60, i32 61, i32 62, i32 63>
+    ret <32 x i8> %r
+}
+
+define <32 x i8> @widen_shuffle_mask_v32i8_to_v4i64(<32 x i8> %a, <32 x i8> %b) {
+; CHECK-LABEL: widen_shuffle_mask_v32i8_to_v4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI2_0)
+; CHECK-NEXT:    xvld $xr2, $a0, %pc_lo12(.LCPI2_0)
+; CHECK-NEXT:    xvshuf.b $xr0, $xr1, $xr0, $xr2
+; CHECK-NEXT:    ret
+    %r = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55>
+    ret <32 x i8> %r
+}
+
+define <16 x i16> @widen_shuffle_mask_v16i16_to_v8i32(<16 x i16> %a, <16 x i16> %b) {
+; CHECK-LABEL: widen_shuffle_mask_v16i16_to_v8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI3_0)
+; CHECK-NEXT:    xvld $xr2, $a0, %pc_lo12(.LCPI3_0)
+; CHECK-NEXT:    xvshuf.h $xr2, $xr1, $xr0
+; CHECK-NEXT:    xvori.b $xr0, $xr2, 0
+; CHECK-NEXT:    ret
+    %r = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 1, i32 6, i32 7, i32 16, i32 17, i32 2, i32 3, i32 10, i32 11, i32 12, i32 13, i32 24, i32 25, i32 26, i32 27>
+    ret <16 x i16> %r
+}
+
+define <16 x i16> @widen_shuffle_mask_v16i16_to_v4i64(<16 x i16> %a, <16 x i16> %b) {
+; CHECK-LABEL: widen_shuffle_mask_v16i16_to_v4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI4_0)
+; CHECK-NEXT:    xvld $xr2, $a0, %pc_lo12(.LCPI4_0)
+; CHECK-NEXT:    xvshuf.h $xr2, $xr1, $xr0
+; CHECK-NEXT:    xvori.b $xr0, $xr2, 0
+; CHECK-NEXT:    ret
+    %r = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 12, i32 13, i32 14, i32 15, i32 28, i32 29, i32 30, i32 31>
+    ret <16 x i16> %r
+}
+
+define <8 x i32> @widen_shuffle_mask_v8i32_to_v4i64(<8 x i32> %a, <8 x i32> %b) {
+; CHECK-LABEL: widen_shuffle_mask_v8i32_to_v4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI5_0)
+; CHECK-NEXT:    xvld $xr2, $a0, %pc_lo12(.LCPI5_0)
+; CHECK-NEXT:    xvshuf.w $xr2, $xr1, $xr0
+; CHECK-NEXT:    xvori.b $xr0, $xr2, 0
+; CHECK-NEXT:    ret
+    %r = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 14, i32 15, i32 6, i32 7>
+    ret <8 x i32> %r
+}
+
+define <32 x i8> @widen_shuffle_mask_v32i8_to_xvpackev_h(<32 x i8> %a, <32 x i8> %b) {
+; CHECK-LABEL: widen_shuffle_mask_v32i8_to_xvpackev_h:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI6_0)
+; CHECK-NEXT:    xvld $xr2, $a0, %pc_lo12(.LCPI6_0)
+; CHECK-NEXT:    xvshuf.b $xr0, $xr1, $xr0, $xr2
+; CHECK-NEXT:    ret
+    %r = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 1, i32 32, i32 33, i32 4, i32 5, i32 36, i32 37, i32 8, i32 9, i32 40, i32 41, i32 12, i32 13, i32 44, i32 45, i32 16, i32 17, i32 48, i32 49, i32 20, i32 21, i32 52, i32 53, i32 24, i32 25, i32 56, i32 57, i32 28, i32 29, i32 60, i32 61>
+    ret <32 x i8> %r
+}
+
+define <32 x i8> @widen_shuffle_mask_v32i8_to_xvpackod_h(<32 x i8> %a, <32 x i8> %b) {
+; CHECK-LABEL: widen_shuffle_mask_v32i8_to_xvpackod_h:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI7_0)
+; CHECK-NEXT:    xvld $xr2, $a0, %pc_lo12(.LCPI7_0)
+; CHECK-NEXT:    xvshuf.b $xr0, $xr1, $xr0, $xr2
+; CHECK-NEXT:    ret
+    %r = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 2, i32 3, i32 34, i32 35, i32 6, i32 7, i32 38, i32 39, i32 10, i32 11, i32 42, i32 43, i32 14, i32 15, i32 46, i32 47, i32 18, i32 19, i32 50, i32 51, i32 22, i32 23, i32 54, i32 55, i32 26, i32 27, i32 58, i32 59, i32 30, i32 31, i32 62, i32 63>
+    ret <32 x i8> %r
+}
+
+define <32 x i8> @widen_shuffle_mask_v32i8_to_xvpickev_h(<32 x i8> %a, <32 x i8> %b) {
+; CHECK-LABEL: widen_shuffle_mask_v32i8_to_xvpickev_h:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI8_0)
+; CHECK-NEXT:    xvld $xr2, $a0, %pc_lo12(.LCPI8_0)
+; CHECK-NEXT:    xvshuf.b $xr0, $xr1, $xr0, $xr2
+; CHECK-NEXT:    ret
+    %r = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13, i32 32, i32 33, i32 36, i32 37, i32 40, i32 41, i32 44, i32 45, i32 16, i32 17, i32 20, i32 21, i32 24, i32 25, i32 28, i32 29, i32 48, i32 49, i32 52, i32 53, i32 56, i32 57, i32 60, i32 61>
+    ret <32 x i8> %r
+}
+
+define <32 x i8> @widen_shuffle_mask_v32i8_to_xvpickod_h(<32 x i8> %a, <32 x i8> %b) {
+; CHECK-LABEL: widen_shuffle_mask_v32i8_to_xvpickod_h:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI9_0)
+; CHECK-NEXT:    xvld $xr2, $a0, %pc_lo12(.LCPI9_0)
+; CHECK-NEXT:    xvshuf.b $xr0, $xr1, $xr0, $xr2
+; CHECK-NEXT:    ret
+    %r = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 2, i32 3, i32 6, i32 7, i32 10, i32 11, i32 14, i32 15, i32 34, i32 35, i32 38, i32 39, i32 42, i32 43, i32 46, i32 47, i32 18, i32 19, i32 22, i32 23, i32 26, i32 27, i32 30, i32 31, i32 50, i32 51, i32 54, i32 55, i32 58, i32 59, i32 62, i32 63>
+    ret <32 x i8> %r
+}
+
+define <32 x i8> @widen_shuffle_mask_v32i8_to_xvilvl_h(<32 x i8> %a, <32 x i8> %b) {
+; CHECK-LABEL: widen_shuffle_mask_v32i8_to_xvilvl_h:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI10_0)
+; CHECK-NEXT:    xvld $xr2, $a0, %pc_lo12(.LCPI10_0)
+; CHECK-NEXT:    xvshuf.b $xr0, $xr1, $xr0, $xr2
+; CHECK-NEXT:    ret
+    %r = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 1, i32 32, i32 33, i32 2, i32 3, i32 34, i32 35, i32 4, i32 5, i32 36, i32 37, i32 6, i32 7, i32 38, i32 39, i32 16, i32 17, i32 48, i32 49, i32 18, i32 19, i32 50, i32 51, i32 20, i32 21, i32 52, i32 53, i32 22, i32 23, i32 54, i32 55>
+    ret <32 x i8> %r
+}
+
+define <32 x i8> @widen_shuffle_mask_v32i8_to_xvilvh_h(<32 x i8> %a, <32 x i8> %b) {
+; CHECK-LABEL: widen_shuffle_mask_v32i8_to_xvilvh_h:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI11_0)
+; CHECK-NEXT:    xvld $xr2, $a0, %pc_lo12(.LCPI11_0)
+; CHECK-NEXT:    xvshuf.b $xr0, $xr1, $xr0, $xr2
+; CHECK-NEXT:    ret
+    %r = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 8, i32 9, i32 40, i32 41, i32 10, i32 11, i32 42, i32 43, i32 12, i32 13, i32 44, i32 45, i32 14, i32 15, i32 46, i32 47, i32 24, i32 25, i32 56, i32 57, i32 26, i32 27, i32 58, i32 59, i32 28, i32 29, i32 60, i32 61, i32 30, i32 31, i32 62, i32 63>
+    ret <32 x i8> %r
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/widen-shuffle-mask.ll b/llvm/test/CodeGen/LoongArch/lsx/widen-shuffle-mask.ll
new file mode 100644
index 0000000000000..35457ffa59586
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/widen-shuffle-mask.ll
@@ -0,0 +1,137 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+
+define <16 x i8> @widen_shuffle_mask_v16i8_to_v8i16(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: widen_shuffle_mask_v16i8_to_v8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI0_0)
+; CHECK-NEXT:    vld $vr2, $a0, %pc_lo12(.LCPI0_0)
+; CHECK-NEXT:    vshuf.b $vr0, $vr1, $vr0, $vr2
+; CHECK-NEXT:    ret
+    %r = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 24, i32 25, i32 26, i32 27, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19, i32 2, i32 3>
+    ret <16 x i8> %r
+}
+
+define <16 x i8> @widen_shuffle_mask_v16i8_to_v4i32(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: widen_shuffle_mask_v16i8_to_v4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI1_0)
+; CHECK-NEXT:    vld $vr2, $a0, %pc_lo12(.LCPI1_0)
+; CHECK-NEXT:    vshuf.b $vr0, $vr1, $vr0, $vr2
+; CHECK-NEXT:    ret
+    %r = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 24, i32 25, i32 26, i32 27, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19>
+    ret <16 x i8> %r
+}
+
+define <16 x i8> @widen_shuffle_mask_v16i8_to_v2i64(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: widen_shuffle_mask_v16i8_to_v2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI2_0)
+; CHECK-NEXT:    vld $vr2, $a0, %pc_lo12(.LCPI2_0)
+; CHECK-NEXT:    vshuf.b $vr0, $vr1, $vr0, $vr2
+; CHECK-NEXT:    ret
+    %r = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+    ret <16 x i8> %r
+}
+
+define <8 x i16> @widen_shuffle_mask_v8i16_to_v4i32(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: widen_shuffle_mask_v8i16_to_v4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI3_0)
+; CHECK-NEXT:    vld $vr2, $a0, %pc_lo12(.LCPI3_0)
+; CHECK-NEXT:    vshuf.h $vr2, $vr1, $vr0
+; CHECK-NEXT:    vori.b $vr0, $vr2, 0
+; CHECK-NEXT:    ret
+    %r = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 12, i32 13, i32 14, i32 15, i32 2, i32 3>
+    ret <8 x i16> %r
+}
+
+define <8 x i16> @widen_shuffle_mask_v8i16_to_v2i64(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: widen_shuffle_mask_v8i16_to_v2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI4_0)
+; CHECK-NEXT:    vld $vr2, $a0, %pc_lo12(.LCPI4_0)
+; CHECK-NEXT:    vshuf.h $vr2, $vr1, $vr0
+; CHECK-NEXT:    vori.b $vr0, $vr2, 0
+; CHECK-NEXT:    ret
+    %r = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
+    ret <8 x i16> %r
+}
+
+define <4 x i32> @widen_shuffle_mask_v4i32_to_v2i64(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: widen_shuffle_mask_v4i32_to_v2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI5_0)
+; CHECK-NEXT:    vld $vr2, $a0, %pc_lo12(.LCPI5_0)
+; CHECK-NEXT:    vshuf.w $vr2, $vr1, $vr0
+; CHECK-NEXT:    vori.b $vr0, $vr2, 0
+; CHECK-NEXT:    ret
+    %r = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+    ret <4 x i32> %r
+}
+
+define <16 x i8> @widen_shuffle_mask_v16i8_to_vpackev_h(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: widen_shuffle_mask_v16i8_to_vpackev_h:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI6_0)
+; CHECK-NEXT:    vld $vr2, $a0, %pc_lo12(.LCPI6_0)
+; CHECK-NEXT:    vshuf.b $vr0, $vr1, $vr0, $vr2
+; CHECK-NEXT:    ret
+    %r = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 4, i32 5, i32 20, i32 21, i32 8, i32 9, i32 24, i32 25, i32 12, i32 13, i32 28, i32 29>
+    ret <16 x i8> %r
+}
+
+define <16 x i8> @widen_shuffle_mask_v16i8_to_vpackod_h(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: widen_shuffle_mask_v16i8_to_vpackod_h:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI7_0)
+; CHECK-NEXT:    vld $vr2, $a0, %pc_lo12(.LCPI7_0)
+; CHECK-NEXT:    vshuf.b $vr0, $vr1, $vr0, $vr2
+; CHECK-NEXT:    ret
+    %r = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 18, i32 19, i32 6, i32 7, i32 22, i32 23, i32 10, i32 11, i32 26, i32 27, i32 14, i32 15, i32 30, i32 31>
+    ret <16 x i8> %r
+}
+
+define <16 x i8> @widen_shuffle_mask_v16i8_to_vpickev_h(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: widen_shuffle_mask_v16i8_to_vpickev_h:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI8_0)
+; CHECK-NEXT:    vld $vr2, $a0, %pc_lo12(.LCPI8_0)
+; CHECK-NEXT:    vshuf.b $vr0, $vr1, $vr0, $vr2
+; CHECK-NEXT:    ret
+    %r = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13, i32 16, i32 17, i32 20, i32 21, i32 24, i32 25, i32 28, i32 29>
+    ret <16 x i8> %r
+}
+
+define <16 x i8> @widen_shuffle_mask_v16i8_to_vpickod_h(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: widen_shuffle_mask_v16i8_to_vpickod_h:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI9_0)
+; CHECK-NEXT:    vld $vr2, $a0, %pc_lo12(.LCPI9_0)
+; CHECK-NEXT:    vshuf.b $vr0, $vr1, $vr0, $vr2
+; CHECK-NEXT:    ret
+    %r = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 6, i32 7, i32 10, i32 11, i32 14, i32 15, i32 18, i32 19, i32 22, i32 23, i32 26, i32 27, i32 30, i32 31>
+    ret <16 x i8> %r
+}
+
+define <16 x i8> @widen_shuffle_mask_v16i8_to_vilvl_h(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: widen_shuffle_mask_v16i8_to_vilvl_h:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI10_0)
+; CHECK-NEXT:    vld $vr2, $a0, %pc_lo12(.LCPI10_0)
+; CHECK-NEXT:    vshuf.b $vr0, $vr1, $vr0, $vr2
+; CHECK-NEXT:    ret
+    %r = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 2, i32 3, i32 18, i32 19, i32 4, i32 5, i32 20, i32 21, i32 6, i32 7, i32 22, i32 23>
+    ret <16 x i8> %r
+}
+
+define <16 x i8> @widen_shuffle_mask_v16i8_to_vilvh_h(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: widen_shuffle_mask_v16i8_to_vilvh_h:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI11_0)
+; CHECK-NEXT:    vld $vr2, $a0, %pc_lo12(.LCPI11_0)
+; CHECK-NEXT:    vshuf.b $vr0, $vr1, $vr0, $vr2
+; CHECK-NEXT:    ret
+    %r = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 9, i32 24, i32 25, i32 10, i32 11, i32 26, i32 27, i32 12, i32 13, i32 28, i32 29, i32 14, i32 15, i32 30, i32 31>
+    ret <16 x i8> %r
+}
diff --git a/llvm/test/CodeGen/NVPTX/LoadStoreVectorizer.ll b/llvm/test/CodeGen/NVPTX/LoadStoreVectorizer.ll
index e46657e4a582f..8f0964c2d5eba 100644
--- a/llvm/test/CodeGen/NVPTX/LoadStoreVectorizer.ll
+++ b/llvm/test/CodeGen/NVPTX/LoadStoreVectorizer.ll
@@ -45,7 +45,7 @@ define half @fh(ptr %p) {
 ; ENABLED-LABEL: fh(
 ; ENABLED:       {
 ; ENABLED-NEXT:    .reg .b16 %rs<10>;
-; ENABLED-NEXT:    .reg .f32 %f<13>;
+; ENABLED-NEXT:    .reg .b32 %f<13>;
 ; ENABLED-NEXT:    .reg .b64 %rd<2>;
 ; ENABLED-EMPTY:
 ; ENABLED-NEXT:  // %bb.0:
@@ -74,7 +74,7 @@ define half @fh(ptr %p) {
 ; DISABLED-LABEL: fh(
 ; DISABLED:       {
 ; DISABLED-NEXT:    .reg .b16 %rs<10>;
-; DISABLED-NEXT:    .reg .f32 %f<13>;
+; DISABLED-NEXT:    .reg .b32 %f<13>;
 ; DISABLED-NEXT:    .reg .b64 %rd<2>;
 ; DISABLED-EMPTY:
 ; DISABLED-NEXT:  // %bb.0:
@@ -121,7 +121,7 @@ define half @fh(ptr %p) {
 define float @ff(ptr %p) {
 ; ENABLED-LABEL: ff(
 ; ENABLED:       {
-; ENABLED-NEXT:    .reg .f32 %f<10>;
+; ENABLED-NEXT:    .reg .b32 %f<10>;
 ; ENABLED-NEXT:    .reg .b64 %rd<2>;
 ; ENABLED-EMPTY:
 ; ENABLED-NEXT:  // %bb.0:
@@ -137,7 +137,7 @@ define float @ff(ptr %p) {
 ;
 ; DISABLED-LABEL: ff(
 ; DISABLED:       {
-; DISABLED-NEXT:    .reg .f32 %f<10>;
+; DISABLED-NEXT:    .reg .b32 %f<10>;
 ; DISABLED-NEXT:    .reg .b64 %rd<2>;
 ; DISABLED-EMPTY:
 ; DISABLED-NEXT:  // %bb.0:
diff --git a/llvm/test/CodeGen/NVPTX/and-or-setcc.ll b/llvm/test/CodeGen/NVPTX/and-or-setcc.ll
index 6c3514c1ad946..5949de335b8cf 100644
--- a/llvm/test/CodeGen/NVPTX/and-or-setcc.ll
+++ b/llvm/test/CodeGen/NVPTX/and-or-setcc.ll
@@ -9,7 +9,7 @@ define i1 @and_ord(float %a, float %b) {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .pred %p<2>;
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [and_ord_param_0];
@@ -29,7 +29,7 @@ define i1 @or_uno(float %a, float %b) {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .pred %p<2>;
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [or_uno_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/atomics.ll b/llvm/test/CodeGen/NVPTX/atomics.ll
index bb04aa856d656..16de80d55a054 100644
--- a/llvm/test/CodeGen/NVPTX/atomics.ll
+++ b/llvm/test/CodeGen/NVPTX/atomics.ll
@@ -351,7 +351,7 @@ declare float @llvm.nvvm.atomic.load.add.f32.p0(ptr %addr, float %val)
 define float @atomic_add_f32_generic(ptr %addr, float %val) {
 ; CHECK-LABEL: atomic_add_f32_generic(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -370,7 +370,7 @@ declare float @llvm.nvvm.atomic.load.add.f32.p1(ptr addrspace(1) %addr, float %v
 define float @atomic_add_f32_addrspace1(ptr addrspace(1) %addr, float %val) {
 ; CHECK-LABEL: atomic_add_f32_addrspace1(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -389,7 +389,7 @@ declare float @llvm.nvvm.atomic.load.add.f32.p3(ptr addrspace(3) %addr, float %v
 define float @atomic_add_f32_addrspace3(ptr addrspace(3) %addr, float %val) {
 ; CHECK-LABEL: atomic_add_f32_addrspace3(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -406,7 +406,7 @@ define float @atomic_add_f32_addrspace3(ptr addrspace(3) %addr, float %val) {
 define float @atomicrmw_add_f32_generic(ptr %addr, float %val) {
 ; CHECK-LABEL: atomicrmw_add_f32_generic(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -426,7 +426,7 @@ define half @atomicrmw_add_f16_generic(ptr %addr, half %val) {
 ; CHECK-NEXT:    .reg .pred %p<2>;
 ; CHECK-NEXT:    .reg .b16 %rs<5>;
 ; CHECK-NEXT:    .reg .b32 %r<17>;
-; CHECK-NEXT:    .reg .f32 %f<4>;
+; CHECK-NEXT:    .reg .b32 %f<4>;
 ; CHECK-NEXT:    .reg .b64 %rd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -470,7 +470,7 @@ define half @atomicrmw_add_f16_generic(ptr %addr, half %val) {
 define float @atomicrmw_add_f32_addrspace1(ptr addrspace(1) %addr, float %val) {
 ; CHECK-LABEL: atomicrmw_add_f32_addrspace1(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -487,7 +487,7 @@ define float @atomicrmw_add_f32_addrspace1(ptr addrspace(1) %addr, float %val) {
 define float @atomicrmw_add_f32_addrspace3(ptr addrspace(3) %addr, float %val) {
 ; CHECK-LABEL: atomicrmw_add_f32_addrspace3(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
diff --git a/llvm/test/CodeGen/NVPTX/bf16-instructions.ll b/llvm/test/CodeGen/NVPTX/bf16-instructions.ll
index b97cb6fa3cbe4..6be13c3a6fdec 100644
--- a/llvm/test/CodeGen/NVPTX/bf16-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/bf16-instructions.ll
@@ -19,7 +19,7 @@ define bfloat @test_fadd(bfloat %0, bfloat %1) {
 ; SM70-NEXT:    .reg .pred %p<2>;
 ; SM70-NEXT:    .reg .b16 %rs<2>;
 ; SM70-NEXT:    .reg .b32 %r<11>;
-; SM70-NEXT:    .reg .f32 %f<4>;
+; SM70-NEXT:    .reg .b32 %f<4>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.u16 %r1, [test_fadd_param_1];
@@ -55,7 +55,7 @@ define bfloat @test_fadd(bfloat %0, bfloat %1) {
 ; SM80-FTZ-LABEL: test_fadd(
 ; SM80-FTZ:       {
 ; SM80-FTZ-NEXT:    .reg .b16 %rs<4>;
-; SM80-FTZ-NEXT:    .reg .f32 %f<4>;
+; SM80-FTZ-NEXT:    .reg .b32 %f<4>;
 ; SM80-FTZ-EMPTY:
 ; SM80-FTZ-NEXT:  // %bb.0:
 ; SM80-FTZ-NEXT:    ld.param.b16 %rs1, [test_fadd_param_0];
@@ -87,7 +87,7 @@ define bfloat @test_fsub(bfloat %0, bfloat %1) {
 ; SM70-NEXT:    .reg .pred %p<2>;
 ; SM70-NEXT:    .reg .b16 %rs<2>;
 ; SM70-NEXT:    .reg .b32 %r<11>;
-; SM70-NEXT:    .reg .f32 %f<4>;
+; SM70-NEXT:    .reg .b32 %f<4>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.u16 %r1, [test_fsub_param_1];
@@ -123,7 +123,7 @@ define bfloat @test_fsub(bfloat %0, bfloat %1) {
 ; SM80-FTZ-LABEL: test_fsub(
 ; SM80-FTZ:       {
 ; SM80-FTZ-NEXT:    .reg .b16 %rs<4>;
-; SM80-FTZ-NEXT:    .reg .f32 %f<4>;
+; SM80-FTZ-NEXT:    .reg .b32 %f<4>;
 ; SM80-FTZ-EMPTY:
 ; SM80-FTZ-NEXT:  // %bb.0:
 ; SM80-FTZ-NEXT:    ld.param.b16 %rs1, [test_fsub_param_0];
@@ -155,7 +155,7 @@ define <2 x bfloat> @test_faddx2(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
 ; SM70-NEXT:    .reg .pred %p<3>;
 ; SM70-NEXT:    .reg .b16 %rs<5>;
 ; SM70-NEXT:    .reg .b32 %r<24>;
-; SM70-NEXT:    .reg .f32 %f<7>;
+; SM70-NEXT:    .reg .b32 %f<7>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.b32 %r1, [test_faddx2_param_0];
@@ -210,7 +210,7 @@ define <2 x bfloat> @test_faddx2(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
 ; SM80-FTZ:       {
 ; SM80-FTZ-NEXT:    .reg .b16 %rs<5>;
 ; SM80-FTZ-NEXT:    .reg .b32 %r<4>;
-; SM80-FTZ-NEXT:    .reg .f32 %f<7>;
+; SM80-FTZ-NEXT:    .reg .b32 %f<7>;
 ; SM80-FTZ-EMPTY:
 ; SM80-FTZ-NEXT:  // %bb.0:
 ; SM80-FTZ-NEXT:    ld.param.b32 %r1, [test_faddx2_param_0];
@@ -247,7 +247,7 @@ define <2 x bfloat> @test_fsubx2(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
 ; SM70-NEXT:    .reg .pred %p<3>;
 ; SM70-NEXT:    .reg .b16 %rs<5>;
 ; SM70-NEXT:    .reg .b32 %r<24>;
-; SM70-NEXT:    .reg .f32 %f<7>;
+; SM70-NEXT:    .reg .b32 %f<7>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.b32 %r1, [test_fsubx2_param_0];
@@ -302,7 +302,7 @@ define <2 x bfloat> @test_fsubx2(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
 ; SM80-FTZ:       {
 ; SM80-FTZ-NEXT:    .reg .b16 %rs<5>;
 ; SM80-FTZ-NEXT:    .reg .b32 %r<4>;
-; SM80-FTZ-NEXT:    .reg .f32 %f<7>;
+; SM80-FTZ-NEXT:    .reg .b32 %f<7>;
 ; SM80-FTZ-EMPTY:
 ; SM80-FTZ-NEXT:  // %bb.0:
 ; SM80-FTZ-NEXT:    ld.param.b32 %r1, [test_fsubx2_param_0];
@@ -339,7 +339,7 @@ define <2 x bfloat> @test_fmulx2(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
 ; SM70-NEXT:    .reg .pred %p<3>;
 ; SM70-NEXT:    .reg .b16 %rs<5>;
 ; SM70-NEXT:    .reg .b32 %r<24>;
-; SM70-NEXT:    .reg .f32 %f<7>;
+; SM70-NEXT:    .reg .b32 %f<7>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.b32 %r1, [test_fmulx2_param_0];
@@ -394,7 +394,7 @@ define <2 x bfloat> @test_fmulx2(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
 ; SM80-FTZ:       {
 ; SM80-FTZ-NEXT:    .reg .b16 %rs<5>;
 ; SM80-FTZ-NEXT:    .reg .b32 %r<4>;
-; SM80-FTZ-NEXT:    .reg .f32 %f<7>;
+; SM80-FTZ-NEXT:    .reg .b32 %f<7>;
 ; SM80-FTZ-EMPTY:
 ; SM80-FTZ-NEXT:  // %bb.0:
 ; SM80-FTZ-NEXT:    ld.param.b32 %r1, [test_fmulx2_param_0];
@@ -431,7 +431,7 @@ define <2 x bfloat> @test_fdiv(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
 ; SM70-NEXT:    .reg .pred %p<3>;
 ; SM70-NEXT:    .reg .b16 %rs<5>;
 ; SM70-NEXT:    .reg .b32 %r<24>;
-; SM70-NEXT:    .reg .f32 %f<7>;
+; SM70-NEXT:    .reg .b32 %f<7>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.b32 %r1, [test_fdiv_param_0];
@@ -474,7 +474,7 @@ define <2 x bfloat> @test_fdiv(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
 ; SM80:       {
 ; SM80-NEXT:    .reg .b16 %rs<5>;
 ; SM80-NEXT:    .reg .b32 %r<4>;
-; SM80-NEXT:    .reg .f32 %f<7>;
+; SM80-NEXT:    .reg .b32 %f<7>;
 ; SM80-EMPTY:
 ; SM80-NEXT:  // %bb.0:
 ; SM80-NEXT:    ld.param.b32 %r1, [test_fdiv_param_0];
@@ -495,7 +495,7 @@ define <2 x bfloat> @test_fdiv(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
 ; SM80-FTZ:       {
 ; SM80-FTZ-NEXT:    .reg .b16 %rs<5>;
 ; SM80-FTZ-NEXT:    .reg .b32 %r<4>;
-; SM80-FTZ-NEXT:    .reg .f32 %f<7>;
+; SM80-FTZ-NEXT:    .reg .b32 %f<7>;
 ; SM80-FTZ-EMPTY:
 ; SM80-FTZ-NEXT:  // %bb.0:
 ; SM80-FTZ-NEXT:    ld.param.b32 %r1, [test_fdiv_param_0];
@@ -516,7 +516,7 @@ define <2 x bfloat> @test_fdiv(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
 ; SM90:       {
 ; SM90-NEXT:    .reg .b16 %rs<5>;
 ; SM90-NEXT:    .reg .b32 %r<4>;
-; SM90-NEXT:    .reg .f32 %f<7>;
+; SM90-NEXT:    .reg .b32 %f<7>;
 ; SM90-EMPTY:
 ; SM90-NEXT:  // %bb.0:
 ; SM90-NEXT:    ld.param.b32 %r1, [test_fdiv_param_0];
@@ -566,7 +566,7 @@ define float @test_fpext_float(bfloat %a) #0 {
 ; SM70-LABEL: test_fpext_float(
 ; SM70:       {
 ; SM70-NEXT:    .reg .b32 %r<3>;
-; SM70-NEXT:    .reg .f32 %f<2>;
+; SM70-NEXT:    .reg .b32 %f<2>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.u16 %r1, [test_fpext_float_param_0];
@@ -578,7 +578,7 @@ define float @test_fpext_float(bfloat %a) #0 {
 ; SM80-LABEL: test_fpext_float(
 ; SM80:       {
 ; SM80-NEXT:    .reg .b16 %rs<2>;
-; SM80-NEXT:    .reg .f32 %f<2>;
+; SM80-NEXT:    .reg .b32 %f<2>;
 ; SM80-EMPTY:
 ; SM80-NEXT:  // %bb.0:
 ; SM80-NEXT:    ld.param.b16 %rs1, [test_fpext_float_param_0];
@@ -589,7 +589,7 @@ define float @test_fpext_float(bfloat %a) #0 {
 ; SM80-FTZ-LABEL: test_fpext_float(
 ; SM80-FTZ:       {
 ; SM80-FTZ-NEXT:    .reg .b16 %rs<2>;
-; SM80-FTZ-NEXT:    .reg .f32 %f<2>;
+; SM80-FTZ-NEXT:    .reg .b32 %f<2>;
 ; SM80-FTZ-EMPTY:
 ; SM80-FTZ-NEXT:  // %bb.0:
 ; SM80-FTZ-NEXT:    ld.param.b16 %rs1, [test_fpext_float_param_0];
@@ -600,7 +600,7 @@ define float @test_fpext_float(bfloat %a) #0 {
 ; SM90-LABEL: test_fpext_float(
 ; SM90:       {
 ; SM90-NEXT:    .reg .b16 %rs<2>;
-; SM90-NEXT:    .reg .f32 %f<2>;
+; SM90-NEXT:    .reg .b32 %f<2>;
 ; SM90-EMPTY:
 ; SM90-NEXT:  // %bb.0:
 ; SM90-NEXT:    ld.param.b16 %rs1, [test_fpext_float_param_0];
@@ -617,7 +617,7 @@ define bfloat @test_fptrunc_float(float %a) #0 {
 ; SM70-NEXT:    .reg .pred %p<2>;
 ; SM70-NEXT:    .reg .b16 %rs<2>;
 ; SM70-NEXT:    .reg .b32 %r<7>;
-; SM70-NEXT:    .reg .f32 %f<2>;
+; SM70-NEXT:    .reg .b32 %f<2>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.f32 %f1, [test_fptrunc_float_param_0];
@@ -635,7 +635,7 @@ define bfloat @test_fptrunc_float(float %a) #0 {
 ; SM80-LABEL: test_fptrunc_float(
 ; SM80:       {
 ; SM80-NEXT:    .reg .b16 %rs<2>;
-; SM80-NEXT:    .reg .f32 %f<2>;
+; SM80-NEXT:    .reg .b32 %f<2>;
 ; SM80-EMPTY:
 ; SM80-NEXT:  // %bb.0:
 ; SM80-NEXT:    ld.param.f32 %f1, [test_fptrunc_float_param_0];
@@ -646,7 +646,7 @@ define bfloat @test_fptrunc_float(float %a) #0 {
 ; SM80-FTZ-LABEL: test_fptrunc_float(
 ; SM80-FTZ:       {
 ; SM80-FTZ-NEXT:    .reg .b16 %rs<2>;
-; SM80-FTZ-NEXT:    .reg .f32 %f<2>;
+; SM80-FTZ-NEXT:    .reg .b32 %f<2>;
 ; SM80-FTZ-EMPTY:
 ; SM80-FTZ-NEXT:  // %bb.0:
 ; SM80-FTZ-NEXT:    ld.param.f32 %f1, [test_fptrunc_float_param_0];
@@ -657,7 +657,7 @@ define bfloat @test_fptrunc_float(float %a) #0 {
 ; SM90-LABEL: test_fptrunc_float(
 ; SM90:       {
 ; SM90-NEXT:    .reg .b16 %rs<2>;
-; SM90-NEXT:    .reg .f32 %f<2>;
+; SM90-NEXT:    .reg .b32 %f<2>;
 ; SM90-EMPTY:
 ; SM90-NEXT:  // %bb.0:
 ; SM90-NEXT:    ld.param.f32 %f1, [test_fptrunc_float_param_0];
@@ -674,7 +674,7 @@ define bfloat @test_fadd_imm_1(bfloat %a) #0 {
 ; SM70-NEXT:    .reg .pred %p<2>;
 ; SM70-NEXT:    .reg .b16 %rs<2>;
 ; SM70-NEXT:    .reg .b32 %r<9>;
-; SM70-NEXT:    .reg .f32 %f<3>;
+; SM70-NEXT:    .reg .b32 %f<3>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.u16 %r1, [test_fadd_imm_1_param_0];
@@ -706,7 +706,7 @@ define bfloat @test_fadd_imm_1(bfloat %a) #0 {
 ; SM80-FTZ-LABEL: test_fadd_imm_1(
 ; SM80-FTZ:       {
 ; SM80-FTZ-NEXT:    .reg .b16 %rs<3>;
-; SM80-FTZ-NEXT:    .reg .f32 %f<3>;
+; SM80-FTZ-NEXT:    .reg .b32 %f<3>;
 ; SM80-FTZ-EMPTY:
 ; SM80-FTZ-NEXT:  // %bb.0:
 ; SM80-FTZ-NEXT:    ld.param.b16 %rs1, [test_fadd_imm_1_param_0];
@@ -735,7 +735,7 @@ define bfloat @test_select_cc_bf16_f64(double %a, double %b, bfloat %c, bfloat %
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .pred %p<2>;
 ; CHECK-NEXT:    .reg .b16 %rs<4>;
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f64 %fd1, [test_select_cc_bf16_f64_param_0];
@@ -756,7 +756,7 @@ define <8 x float> @test_extload_bf16x8(ptr addrspace(3) noundef %arg) #0 {
 ; SM70:       {
 ; SM70-NEXT:    .reg .b16 %rs<9>;
 ; SM70-NEXT:    .reg .b32 %r<21>;
-; SM70-NEXT:    .reg .f32 %f<9>;
+; SM70-NEXT:    .reg .b32 %f<9>;
 ; SM70-NEXT:    .reg .b64 %rd<2>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
@@ -798,7 +798,7 @@ define <8 x float> @test_extload_bf16x8(ptr addrspace(3) noundef %arg) #0 {
 ; SM80:       {
 ; SM80-NEXT:    .reg .b16 %rs<9>;
 ; SM80-NEXT:    .reg .b32 %r<5>;
-; SM80-NEXT:    .reg .f32 %f<9>;
+; SM80-NEXT:    .reg .b32 %f<9>;
 ; SM80-NEXT:    .reg .b64 %rd<2>;
 ; SM80-EMPTY:
 ; SM80-NEXT:  // %bb.0:
@@ -824,7 +824,7 @@ define <8 x float> @test_extload_bf16x8(ptr addrspace(3) noundef %arg) #0 {
 ; SM80-FTZ:       {
 ; SM80-FTZ-NEXT:    .reg .b16 %rs<9>;
 ; SM80-FTZ-NEXT:    .reg .b32 %r<5>;
-; SM80-FTZ-NEXT:    .reg .f32 %f<9>;
+; SM80-FTZ-NEXT:    .reg .b32 %f<9>;
 ; SM80-FTZ-NEXT:    .reg .b64 %rd<2>;
 ; SM80-FTZ-EMPTY:
 ; SM80-FTZ-NEXT:  // %bb.0:
@@ -850,7 +850,7 @@ define <8 x float> @test_extload_bf16x8(ptr addrspace(3) noundef %arg) #0 {
 ; SM90:       {
 ; SM90-NEXT:    .reg .b16 %rs<9>;
 ; SM90-NEXT:    .reg .b32 %r<5>;
-; SM90-NEXT:    .reg .f32 %f<9>;
+; SM90-NEXT:    .reg .b32 %f<9>;
 ; SM90-NEXT:    .reg .b64 %rd<2>;
 ; SM90-EMPTY:
 ; SM90-NEXT:  // %bb.0:
@@ -881,7 +881,7 @@ define i16 @test_fptosi_i16(bfloat %a) {
 ; SM70:       {
 ; SM70-NEXT:    .reg .b16 %rs<2>;
 ; SM70-NEXT:    .reg .b32 %r<4>;
-; SM70-NEXT:    .reg .f32 %f<2>;
+; SM70-NEXT:    .reg .b32 %f<2>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.u16 %r1, [test_fptosi_i16_param_0];
@@ -896,7 +896,7 @@ define i16 @test_fptosi_i16(bfloat %a) {
 ; SM80:       {
 ; SM80-NEXT:    .reg .b16 %rs<3>;
 ; SM80-NEXT:    .reg .b32 %r<2>;
-; SM80-NEXT:    .reg .f32 %f<2>;
+; SM80-NEXT:    .reg .b32 %f<2>;
 ; SM80-EMPTY:
 ; SM80-NEXT:  // %bb.0:
 ; SM80-NEXT:    ld.param.b16 %rs1, [test_fptosi_i16_param_0];
@@ -910,7 +910,7 @@ define i16 @test_fptosi_i16(bfloat %a) {
 ; SM80-FTZ:       {
 ; SM80-FTZ-NEXT:    .reg .b16 %rs<3>;
 ; SM80-FTZ-NEXT:    .reg .b32 %r<2>;
-; SM80-FTZ-NEXT:    .reg .f32 %f<2>;
+; SM80-FTZ-NEXT:    .reg .b32 %f<2>;
 ; SM80-FTZ-EMPTY:
 ; SM80-FTZ-NEXT:  // %bb.0:
 ; SM80-FTZ-NEXT:    ld.param.b16 %rs1, [test_fptosi_i16_param_0];
@@ -940,7 +940,7 @@ define i16 @test_fptoui_i16(bfloat %a) {
 ; SM70:       {
 ; SM70-NEXT:    .reg .b16 %rs<2>;
 ; SM70-NEXT:    .reg .b32 %r<4>;
-; SM70-NEXT:    .reg .f32 %f<2>;
+; SM70-NEXT:    .reg .b32 %f<2>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.u16 %r1, [test_fptoui_i16_param_0];
@@ -955,7 +955,7 @@ define i16 @test_fptoui_i16(bfloat %a) {
 ; SM80:       {
 ; SM80-NEXT:    .reg .b16 %rs<3>;
 ; SM80-NEXT:    .reg .b32 %r<2>;
-; SM80-NEXT:    .reg .f32 %f<2>;
+; SM80-NEXT:    .reg .b32 %f<2>;
 ; SM80-EMPTY:
 ; SM80-NEXT:  // %bb.0:
 ; SM80-NEXT:    ld.param.b16 %rs1, [test_fptoui_i16_param_0];
@@ -969,7 +969,7 @@ define i16 @test_fptoui_i16(bfloat %a) {
 ; SM80-FTZ:       {
 ; SM80-FTZ-NEXT:    .reg .b16 %rs<3>;
 ; SM80-FTZ-NEXT:    .reg .b32 %r<2>;
-; SM80-FTZ-NEXT:    .reg .f32 %f<2>;
+; SM80-FTZ-NEXT:    .reg .b32 %f<2>;
 ; SM80-FTZ-EMPTY:
 ; SM80-FTZ-NEXT:  // %bb.0:
 ; SM80-FTZ-NEXT:    ld.param.b16 %rs1, [test_fptoui_i16_param_0];
@@ -1000,7 +1000,7 @@ define bfloat @test_sitofp_i16(i16 %a) {
 ; SM70-NEXT:    .reg .pred %p<2>;
 ; SM70-NEXT:    .reg .b16 %rs<3>;
 ; SM70-NEXT:    .reg .b32 %r<7>;
-; SM70-NEXT:    .reg .f32 %f<2>;
+; SM70-NEXT:    .reg .b32 %f<2>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.u16 %rs1, [test_sitofp_i16_param_0];
@@ -1019,7 +1019,7 @@ define bfloat @test_sitofp_i16(i16 %a) {
 ; SM80-LABEL: test_sitofp_i16(
 ; SM80:       {
 ; SM80-NEXT:    .reg .b16 %rs<3>;
-; SM80-NEXT:    .reg .f32 %f<2>;
+; SM80-NEXT:    .reg .b32 %f<2>;
 ; SM80-EMPTY:
 ; SM80-NEXT:  // %bb.0:
 ; SM80-NEXT:    ld.param.u16 %rs1, [test_sitofp_i16_param_0];
@@ -1031,7 +1031,7 @@ define bfloat @test_sitofp_i16(i16 %a) {
 ; SM80-FTZ-LABEL: test_sitofp_i16(
 ; SM80-FTZ:       {
 ; SM80-FTZ-NEXT:    .reg .b16 %rs<3>;
-; SM80-FTZ-NEXT:    .reg .f32 %f<2>;
+; SM80-FTZ-NEXT:    .reg .b32 %f<2>;
 ; SM80-FTZ-EMPTY:
 ; SM80-FTZ-NEXT:  // %bb.0:
 ; SM80-FTZ-NEXT:    ld.param.u16 %rs1, [test_sitofp_i16_param_0];
@@ -1059,7 +1059,7 @@ define bfloat @test_uitofp_i8(i8 %a) {
 ; SM70-NEXT:    .reg .pred %p<2>;
 ; SM70-NEXT:    .reg .b16 %rs<3>;
 ; SM70-NEXT:    .reg .b32 %r<7>;
-; SM70-NEXT:    .reg .f32 %f<2>;
+; SM70-NEXT:    .reg .b32 %f<2>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.u8 %rs1, [test_uitofp_i8_param_0];
@@ -1078,7 +1078,7 @@ define bfloat @test_uitofp_i8(i8 %a) {
 ; SM80-LABEL: test_uitofp_i8(
 ; SM80:       {
 ; SM80-NEXT:    .reg .b16 %rs<3>;
-; SM80-NEXT:    .reg .f32 %f<2>;
+; SM80-NEXT:    .reg .b32 %f<2>;
 ; SM80-EMPTY:
 ; SM80-NEXT:  // %bb.0:
 ; SM80-NEXT:    ld.param.u8 %rs1, [test_uitofp_i8_param_0];
@@ -1090,7 +1090,7 @@ define bfloat @test_uitofp_i8(i8 %a) {
 ; SM80-FTZ-LABEL: test_uitofp_i8(
 ; SM80-FTZ:       {
 ; SM80-FTZ-NEXT:    .reg .b16 %rs<3>;
-; SM80-FTZ-NEXT:    .reg .f32 %f<2>;
+; SM80-FTZ-NEXT:    .reg .b32 %f<2>;
 ; SM80-FTZ-EMPTY:
 ; SM80-FTZ-NEXT:  // %bb.0:
 ; SM80-FTZ-NEXT:    ld.param.u8 %rs1, [test_uitofp_i8_param_0];
@@ -1118,7 +1118,7 @@ define bfloat @test_uitofp_i1(i1 %a) {
 ; SM70-NEXT:    .reg .pred %p<3>;
 ; SM70-NEXT:    .reg .b16 %rs<4>;
 ; SM70-NEXT:    .reg .b32 %r<8>;
-; SM70-NEXT:    .reg .f32 %f<2>;
+; SM70-NEXT:    .reg .b32 %f<2>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.u8 %rs1, [test_uitofp_i1_param_0];
@@ -1142,7 +1142,7 @@ define bfloat @test_uitofp_i1(i1 %a) {
 ; SM80-NEXT:    .reg .pred %p<2>;
 ; SM80-NEXT:    .reg .b16 %rs<4>;
 ; SM80-NEXT:    .reg .b32 %r<2>;
-; SM80-NEXT:    .reg .f32 %f<2>;
+; SM80-NEXT:    .reg .b32 %f<2>;
 ; SM80-EMPTY:
 ; SM80-NEXT:  // %bb.0:
 ; SM80-NEXT:    ld.param.u8 %rs1, [test_uitofp_i1_param_0];
@@ -1159,7 +1159,7 @@ define bfloat @test_uitofp_i1(i1 %a) {
 ; SM80-FTZ-NEXT:    .reg .pred %p<2>;
 ; SM80-FTZ-NEXT:    .reg .b16 %rs<4>;
 ; SM80-FTZ-NEXT:    .reg .b32 %r<2>;
-; SM80-FTZ-NEXT:    .reg .f32 %f<2>;
+; SM80-FTZ-NEXT:    .reg .b32 %f<2>;
 ; SM80-FTZ-EMPTY:
 ; SM80-FTZ-NEXT:  // %bb.0:
 ; SM80-FTZ-NEXT:    ld.param.u8 %rs1, [test_uitofp_i1_param_0];
@@ -1195,7 +1195,7 @@ define bfloat @test_uitofp_i16(i16 %a) {
 ; SM70-NEXT:    .reg .pred %p<2>;
 ; SM70-NEXT:    .reg .b16 %rs<3>;
 ; SM70-NEXT:    .reg .b32 %r<7>;
-; SM70-NEXT:    .reg .f32 %f<2>;
+; SM70-NEXT:    .reg .b32 %f<2>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.u16 %rs1, [test_uitofp_i16_param_0];
@@ -1214,7 +1214,7 @@ define bfloat @test_uitofp_i16(i16 %a) {
 ; SM80-LABEL: test_uitofp_i16(
 ; SM80:       {
 ; SM80-NEXT:    .reg .b16 %rs<3>;
-; SM80-NEXT:    .reg .f32 %f<2>;
+; SM80-NEXT:    .reg .b32 %f<2>;
 ; SM80-EMPTY:
 ; SM80-NEXT:  // %bb.0:
 ; SM80-NEXT:    ld.param.u16 %rs1, [test_uitofp_i16_param_0];
@@ -1226,7 +1226,7 @@ define bfloat @test_uitofp_i16(i16 %a) {
 ; SM80-FTZ-LABEL: test_uitofp_i16(
 ; SM80-FTZ:       {
 ; SM80-FTZ-NEXT:    .reg .b16 %rs<3>;
-; SM80-FTZ-NEXT:    .reg .f32 %f<2>;
+; SM80-FTZ-NEXT:    .reg .b32 %f<2>;
 ; SM80-FTZ-EMPTY:
 ; SM80-FTZ-NEXT:  // %bb.0:
 ; SM80-FTZ-NEXT:    ld.param.u16 %rs1, [test_uitofp_i16_param_0];
@@ -1254,7 +1254,7 @@ define bfloat @test_uitofp_i32(i32 %a) {
 ; SM70-NEXT:    .reg .pred %p<2>;
 ; SM70-NEXT:    .reg .b16 %rs<2>;
 ; SM70-NEXT:    .reg .b32 %r<8>;
-; SM70-NEXT:    .reg .f32 %f<2>;
+; SM70-NEXT:    .reg .b32 %f<2>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.u32 %r1, [test_uitofp_i32_param_0];
@@ -1274,7 +1274,7 @@ define bfloat @test_uitofp_i32(i32 %a) {
 ; SM80:       {
 ; SM80-NEXT:    .reg .b16 %rs<2>;
 ; SM80-NEXT:    .reg .b32 %r<2>;
-; SM80-NEXT:    .reg .f32 %f<2>;
+; SM80-NEXT:    .reg .b32 %f<2>;
 ; SM80-EMPTY:
 ; SM80-NEXT:  // %bb.0:
 ; SM80-NEXT:    ld.param.u32 %r1, [test_uitofp_i32_param_0];
@@ -1287,7 +1287,7 @@ define bfloat @test_uitofp_i32(i32 %a) {
 ; SM80-FTZ:       {
 ; SM80-FTZ-NEXT:    .reg .b16 %rs<2>;
 ; SM80-FTZ-NEXT:    .reg .b32 %r<2>;
-; SM80-FTZ-NEXT:    .reg .f32 %f<2>;
+; SM80-FTZ-NEXT:    .reg .b32 %f<2>;
 ; SM80-FTZ-EMPTY:
 ; SM80-FTZ-NEXT:  // %bb.0:
 ; SM80-FTZ-NEXT:    ld.param.u32 %r1, [test_uitofp_i32_param_0];
@@ -1316,7 +1316,7 @@ define bfloat @test_uitofp_i64(i64 %a) {
 ; SM70-NEXT:    .reg .pred %p<2>;
 ; SM70-NEXT:    .reg .b16 %rs<2>;
 ; SM70-NEXT:    .reg .b32 %r<7>;
-; SM70-NEXT:    .reg .f32 %f<2>;
+; SM70-NEXT:    .reg .b32 %f<2>;
 ; SM70-NEXT:    .reg .b64 %rd<2>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
@@ -1336,7 +1336,7 @@ define bfloat @test_uitofp_i64(i64 %a) {
 ; SM80-LABEL: test_uitofp_i64(
 ; SM80:       {
 ; SM80-NEXT:    .reg .b16 %rs<2>;
-; SM80-NEXT:    .reg .f32 %f<2>;
+; SM80-NEXT:    .reg .b32 %f<2>;
 ; SM80-NEXT:    .reg .b64 %rd<2>;
 ; SM80-EMPTY:
 ; SM80-NEXT:  // %bb.0:
@@ -1349,7 +1349,7 @@ define bfloat @test_uitofp_i64(i64 %a) {
 ; SM80-FTZ-LABEL: test_uitofp_i64(
 ; SM80-FTZ:       {
 ; SM80-FTZ-NEXT:    .reg .b16 %rs<2>;
-; SM80-FTZ-NEXT:    .reg .f32 %f<2>;
+; SM80-FTZ-NEXT:    .reg .b32 %f<2>;
 ; SM80-FTZ-NEXT:    .reg .b64 %rd<2>;
 ; SM80-FTZ-EMPTY:
 ; SM80-FTZ-NEXT:  // %bb.0:
@@ -1379,7 +1379,7 @@ define bfloat @test_roundeven(bfloat %a) {
 ; SM70-NEXT:    .reg .pred %p<2>;
 ; SM70-NEXT:    .reg .b16 %rs<2>;
 ; SM70-NEXT:    .reg .b32 %r<9>;
-; SM70-NEXT:    .reg .f32 %f<3>;
+; SM70-NEXT:    .reg .b32 %f<3>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.u16 %r1, [test_roundeven_param_0];
@@ -1400,7 +1400,7 @@ define bfloat @test_roundeven(bfloat %a) {
 ; SM80-LABEL: test_roundeven(
 ; SM80:       {
 ; SM80-NEXT:    .reg .b16 %rs<3>;
-; SM80-NEXT:    .reg .f32 %f<3>;
+; SM80-NEXT:    .reg .b32 %f<3>;
 ; SM80-EMPTY:
 ; SM80-NEXT:  // %bb.0:
 ; SM80-NEXT:    ld.param.b16 %rs1, [test_roundeven_param_0];
@@ -1413,7 +1413,7 @@ define bfloat @test_roundeven(bfloat %a) {
 ; SM80-FTZ-LABEL: test_roundeven(
 ; SM80-FTZ:       {
 ; SM80-FTZ-NEXT:    .reg .b16 %rs<3>;
-; SM80-FTZ-NEXT:    .reg .f32 %f<3>;
+; SM80-FTZ-NEXT:    .reg .b32 %f<3>;
 ; SM80-FTZ-EMPTY:
 ; SM80-FTZ-NEXT:  // %bb.0:
 ; SM80-FTZ-NEXT:    ld.param.b16 %rs1, [test_roundeven_param_0];
@@ -1442,7 +1442,7 @@ define bfloat @test_maximum(bfloat %a, bfloat %b) {
 ; SM70-NEXT:    .reg .pred %p<6>;
 ; SM70-NEXT:    .reg .b16 %rs<8>;
 ; SM70-NEXT:    .reg .b32 %r<7>;
-; SM70-NEXT:    .reg .f32 %f<4>;
+; SM70-NEXT:    .reg .b32 %f<4>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.b16 %rs1, [test_maximum_param_0];
@@ -1511,7 +1511,7 @@ define bfloat @test_maxnum(bfloat %a, bfloat %b) {
 ; SM70-NEXT:    .reg .pred %p<2>;
 ; SM70-NEXT:    .reg .b16 %rs<2>;
 ; SM70-NEXT:    .reg .b32 %r<11>;
-; SM70-NEXT:    .reg .f32 %f<4>;
+; SM70-NEXT:    .reg .b32 %f<4>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.u16 %r1, [test_maxnum_param_1];
@@ -1574,7 +1574,7 @@ define <2 x bfloat> @test_maximum_v2(<2 x bfloat> %a, <2 x bfloat> %b) {
 ; SM70-NEXT:    .reg .pred %p<11>;
 ; SM70-NEXT:    .reg .b16 %rs<15>;
 ; SM70-NEXT:    .reg .b32 %r<16>;
-; SM70-NEXT:    .reg .f32 %f<7>;
+; SM70-NEXT:    .reg .b32 %f<7>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.b32 %r1, [test_maximum_v2_param_0];
@@ -1665,7 +1665,7 @@ define <2 x bfloat> @test_maxnum_v2(<2 x bfloat> %a, <2 x bfloat> %b) {
 ; SM70-NEXT:    .reg .pred %p<3>;
 ; SM70-NEXT:    .reg .b16 %rs<5>;
 ; SM70-NEXT:    .reg .b32 %r<24>;
-; SM70-NEXT:    .reg .f32 %f<7>;
+; SM70-NEXT:    .reg .b32 %f<7>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.b32 %r1, [test_maxnum_v2_param_0];
@@ -1741,4 +1741,4 @@ define <2 x bfloat> @test_maxnum_v2(<2 x bfloat> %a, <2 x bfloat> %b) {
 }
 
 declare bfloat @llvm.maximum.bf16(bfloat, bfloat)
-declare <2 x bfloat> @llvm.maximum.v2bf16(<2 x bfloat>, <2 x bfloat>)
\ No newline at end of file
+declare <2 x bfloat> @llvm.maximum.v2bf16(<2 x bfloat>, <2 x bfloat>)
diff --git a/llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll b/llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll
index fdf481e1767a9..5ab684adac58e 100644
--- a/llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll
+++ b/llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll
@@ -12,7 +12,7 @@ define <2 x bfloat> @test_sin(<2 x bfloat> %a) #0 #1 {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<3>;
 ; CHECK-NEXT:    .reg .b32 %r<3>;
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.b32 %r1, [test_sin_param_0];
@@ -33,7 +33,7 @@ define <2 x bfloat> @test_cos(<2 x bfloat> %a) #0 #1 {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<3>;
 ; CHECK-NEXT:    .reg .b32 %r<3>;
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.b32 %r1, [test_cos_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll b/llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
index 706a88f2cb901..677f0d795dde8 100644
--- a/llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
@@ -131,7 +131,7 @@ define <2 x bfloat> @test_fdiv(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<5>;
 ; CHECK-NEXT:    .reg .b32 %r<4>;
-; CHECK-NEXT:    .reg .f32 %f<7>;
+; CHECK-NEXT:    .reg .b32 %f<7>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.b32 %r1, [test_fdiv_param_0];
@@ -259,7 +259,7 @@ define <2 x bfloat> @test_select_cc(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloa
 ; SM80-NEXT:    .reg .pred %p<3>;
 ; SM80-NEXT:    .reg .b16 %rs<11>;
 ; SM80-NEXT:    .reg .b32 %r<6>;
-; SM80-NEXT:    .reg .f32 %f<5>;
+; SM80-NEXT:    .reg .b32 %f<5>;
 ; SM80-EMPTY:
 ; SM80-NEXT:  // %bb.0:
 ; SM80-NEXT:    ld.param.b32 %r1, [test_select_cc_param_0];
@@ -312,7 +312,7 @@ define <2 x float> @test_select_cc_f32_bf16(<2 x float> %a, <2 x float> %b,
 ; SM80-NEXT:    .reg .pred %p<3>;
 ; SM80-NEXT:    .reg .b16 %rs<5>;
 ; SM80-NEXT:    .reg .b32 %r<3>;
-; SM80-NEXT:    .reg .f32 %f<11>;
+; SM80-NEXT:    .reg .b32 %f<11>;
 ; SM80-EMPTY:
 ; SM80-NEXT:  // %bb.0:
 ; SM80-NEXT:    ld.param.v2.f32 {%f1, %f2}, [test_select_cc_f32_bf16_param_0];
@@ -336,7 +336,7 @@ define <2 x float> @test_select_cc_f32_bf16(<2 x float> %a, <2 x float> %b,
 ; SM90:       {
 ; SM90-NEXT:    .reg .pred %p<3>;
 ; SM90-NEXT:    .reg .b32 %r<3>;
-; SM90-NEXT:    .reg .f32 %f<7>;
+; SM90-NEXT:    .reg .b32 %f<7>;
 ; SM90-EMPTY:
 ; SM90-NEXT:  // %bb.0:
 ; SM90-NEXT:    ld.param.v2.f32 {%f1, %f2}, [test_select_cc_f32_bf16_param_0];
@@ -360,7 +360,7 @@ define <2 x bfloat> @test_select_cc_bf16_f32(<2 x bfloat> %a, <2 x bfloat> %b,
 ; CHECK-NEXT:    .reg .pred %p<3>;
 ; CHECK-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NEXT:    .reg .b32 %r<4>;
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.b32 %r1, [test_select_cc_bf16_f32_param_0];
@@ -386,7 +386,7 @@ define <2 x bfloat> @test_fptrunc_2xfloat(<2 x float> %a) #0 {
 ; CHECK-LABEL: test_fptrunc_2xfloat(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.v2.f32 {%f1, %f2}, [test_fptrunc_2xfloat_param_0];
@@ -402,7 +402,7 @@ define <2 x float> @test_fpext_2xfloat(<2 x bfloat> %a) #0 {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<3>;
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.b32 %r1, [test_fpext_2xfloat_param_0];
@@ -469,7 +469,7 @@ define <2 x bfloat> @test_sqrt(<2 x bfloat> %a) #0 {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<3>;
 ; CHECK-NEXT:    .reg .b32 %r<3>;
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.b32 %r1, [test_sqrt_param_0];
@@ -583,7 +583,7 @@ define <2 x bfloat> @test_floor(<2 x bfloat> %a) #0 {
 ; SM80:       {
 ; SM80-NEXT:    .reg .b16 %rs<3>;
 ; SM80-NEXT:    .reg .b32 %r<3>;
-; SM80-NEXT:    .reg .f32 %f<5>;
+; SM80-NEXT:    .reg .b32 %f<5>;
 ; SM80-EMPTY:
 ; SM80-NEXT:  // %bb.0:
 ; SM80-NEXT:    ld.param.b32 %r1, [test_floor_param_0];
@@ -618,7 +618,7 @@ define <2 x bfloat> @test_ceil(<2 x bfloat> %a) #0 {
 ; SM80:       {
 ; SM80-NEXT:    .reg .b16 %rs<3>;
 ; SM80-NEXT:    .reg .b32 %r<3>;
-; SM80-NEXT:    .reg .f32 %f<5>;
+; SM80-NEXT:    .reg .b32 %f<5>;
 ; SM80-EMPTY:
 ; SM80-NEXT:  // %bb.0:
 ; SM80-NEXT:    ld.param.b32 %r1, [test_ceil_param_0];
@@ -653,7 +653,7 @@ define <2 x bfloat> @test_trunc(<2 x bfloat> %a) #0 {
 ; SM80:       {
 ; SM80-NEXT:    .reg .b16 %rs<3>;
 ; SM80-NEXT:    .reg .b32 %r<3>;
-; SM80-NEXT:    .reg .f32 %f<5>;
+; SM80-NEXT:    .reg .b32 %f<5>;
 ; SM80-EMPTY:
 ; SM80-NEXT:  // %bb.0:
 ; SM80-NEXT:    ld.param.b32 %r1, [test_trunc_param_0];
@@ -688,7 +688,7 @@ define <2 x bfloat> @test_rint(<2 x bfloat> %a) #0 {
 ; SM80:       {
 ; SM80-NEXT:    .reg .b16 %rs<3>;
 ; SM80-NEXT:    .reg .b32 %r<3>;
-; SM80-NEXT:    .reg .f32 %f<5>;
+; SM80-NEXT:    .reg .b32 %f<5>;
 ; SM80-EMPTY:
 ; SM80-NEXT:  // %bb.0:
 ; SM80-NEXT:    ld.param.b32 %r1, [test_rint_param_0];
@@ -724,7 +724,7 @@ define <2 x bfloat> @test_round(<2 x bfloat> %a) #0 {
 ; CHECK-NEXT:    .reg .pred %p<5>;
 ; CHECK-NEXT:    .reg .b16 %rs<3>;
 ; CHECK-NEXT:    .reg .b32 %r<9>;
-; CHECK-NEXT:    .reg .f32 %f<17>;
+; CHECK-NEXT:    .reg .b32 %f<17>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.b32 %r1, [test_round_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/convert-fp-i8.ll b/llvm/test/CodeGen/NVPTX/convert-fp-i8.ll
index 93da39137afd8..670e112c26c76 100644
--- a/llvm/test/CodeGen/NVPTX/convert-fp-i8.ll
+++ b/llvm/test/CodeGen/NVPTX/convert-fp-i8.ll
@@ -8,7 +8,7 @@ define i8 @cvt_u8_f32(float %x) {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<2>;
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_u8_f32_param_0];
@@ -25,7 +25,7 @@ define i8 @cvt_u8_f64(double %x) {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<2>;
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f64 %fd<2>;
+; CHECK-NEXT:    .reg .b64 %fd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f64 %fd1, [cvt_u8_f64_param_0];
@@ -41,7 +41,7 @@ define float @cvt_f32_i8(i8 %x) {
 ; CHECK-LABEL: cvt_f32_i8(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<2>;
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u8 %rs1, [cvt_f32_i8_param_0];
@@ -56,7 +56,7 @@ define double @cvt_f64_i8(i8 %x) {
 ; CHECK-LABEL: cvt_f64_i8(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<2>;
-; CHECK-NEXT:    .reg .f64 %fd<2>;
+; CHECK-NEXT:    .reg .b64 %fd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u8 %rs1, [cvt_f64_i8_param_0];
@@ -71,7 +71,7 @@ define float @cvt_f32_s8(i8 %x) {
 ; CHECK-LABEL: cvt_f32_s8(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<2>;
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.s8 %rs1, [cvt_f32_s8_param_0];
@@ -86,7 +86,7 @@ define double @cvt_f64_s8(i8 %x) {
 ; CHECK-LABEL: cvt_f64_s8(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<2>;
-; CHECK-NEXT:    .reg .f64 %fd<2>;
+; CHECK-NEXT:    .reg .b64 %fd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.s8 %rs1, [cvt_f64_s8_param_0];
@@ -102,7 +102,7 @@ define i8 @cvt_s8_f32(float %x) {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<2>;
 ; CHECK-NEXT:    .reg .b32 %r<3>;
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_s8_f32_param_0];
@@ -120,7 +120,7 @@ define i8 @cvt_s8_f64(double %x) {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<2>;
 ; CHECK-NEXT:    .reg .b32 %r<3>;
-; CHECK-NEXT:    .reg .f64 %fd<2>;
+; CHECK-NEXT:    .reg .b64 %fd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f64 %fd1, [cvt_s8_f64_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/convert-sm100.ll b/llvm/test/CodeGen/NVPTX/convert-sm100.ll
index f92822f7e0c16..7230872b3427c 100644
--- a/llvm/test/CodeGen/NVPTX/convert-sm100.ll
+++ b/llvm/test/CodeGen/NVPTX/convert-sm100.ll
@@ -11,7 +11,7 @@ define i32 @cvt_rn_satf_tf32_f32(float %f1) {
 ; CHECK-LABEL: cvt_rn_satf_tf32_f32(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rn_satf_tf32_f32_param_0];
@@ -26,7 +26,7 @@ define i32 @cvt_rn_relu_satf_tf32_f32(float %f1) {
 ; CHECK-LABEL: cvt_rn_relu_satf_tf32_f32(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rn_relu_satf_tf32_f32_param_0];
@@ -41,7 +41,7 @@ define i32 @cvt_rz_satf_tf32_f32(float %f1) {
 ; CHECK-LABEL: cvt_rz_satf_tf32_f32(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rz_satf_tf32_f32_param_0];
@@ -56,7 +56,7 @@ define i32 @cvt_rz_relu_satf_tf32_f32(float %f1) {
 ; CHECK-LABEL: cvt_rz_relu_satf_tf32_f32(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rz_relu_satf_tf32_f32_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/convert-sm100a.ll b/llvm/test/CodeGen/NVPTX/convert-sm100a.ll
index f0dd5f084026b..04d7a65f9e40e 100644
--- a/llvm/test/CodeGen/NVPTX/convert-sm100a.ll
+++ b/llvm/test/CodeGen/NVPTX/convert-sm100a.ll
@@ -11,7 +11,7 @@ define i16 @cvt_rn_sf_e2m3x2_f32(float %f1, float %f2) {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<2>;
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rn_sf_e2m3x2_f32_param_0];
@@ -29,7 +29,7 @@ define i16 @cvt_rn_relu_sf_e2m3x2_f32(float %f1, float %f2) {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<2>;
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rn_relu_sf_e2m3x2_f32_param_0];
@@ -47,7 +47,7 @@ define i16 @cvt_rn_sf_e3m2x2_f32(float %f1, float %f2) {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<2>;
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rn_sf_e3m2x2_f32_param_0];
@@ -65,7 +65,7 @@ define i16 @cvt_rn_relu_sf_e3m2x2_f32(float %f1, float %f2) {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<2>;
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rn_relu_sf_e3m2x2_f32_param_0];
@@ -143,7 +143,7 @@ define i16 @cvt_rz_ue8m0x2_f32(float %f1, float %f2) {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<2>;
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rz_ue8m0x2_f32_param_0];
@@ -161,7 +161,7 @@ define i16 @cvt_rz_sf_ue8m0x2_f32(float %f1, float %f2) {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<2>;
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rz_sf_ue8m0x2_f32_param_0];
@@ -179,7 +179,7 @@ define i16 @cvt_rp_ue8m0x2_f32(float %f1, float %f2) {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<2>;
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rp_ue8m0x2_f32_param_0];
@@ -197,7 +197,7 @@ define i16 @cvt_rp_sf_ue8m0x2_f32(float %f1, float %f2) {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<2>;
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rp_sf_ue8m0x2_f32_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/convert-sm80.ll b/llvm/test/CodeGen/NVPTX/convert-sm80.ll
index aebc28b1cfea3..eb7a6bdd222bb 100644
--- a/llvm/test/CodeGen/NVPTX/convert-sm80.ll
+++ b/llvm/test/CodeGen/NVPTX/convert-sm80.ll
@@ -7,7 +7,7 @@ define <2 x bfloat> @cvt_rn_bf16x2_f32(float %f1, float %f2) {
 ; CHECK-LABEL: cvt_rn_bf16x2_f32(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rn_bf16x2_f32_param_0];
@@ -23,7 +23,7 @@ define <2 x bfloat> @cvt_rn_relu_bf16x2_f32(float %f1, float %f2) {
 ; CHECK-LABEL: cvt_rn_relu_bf16x2_f32(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rn_relu_bf16x2_f32_param_0];
@@ -39,7 +39,7 @@ define <2 x bfloat> @cvt_rz_bf16x2_f32(float %f1, float %f2) {
 ; CHECK-LABEL: cvt_rz_bf16x2_f32(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rz_bf16x2_f32_param_0];
@@ -55,7 +55,7 @@ define <2 x bfloat> @cvt_rz_relu_bf16x2_f32(float %f1, float %f2) {
 ; CHECK-LABEL: cvt_rz_relu_bf16x2_f32(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rz_relu_bf16x2_f32_param_0];
@@ -76,7 +76,7 @@ define <2 x half> @cvt_rn_f16x2_f32(float %f1, float %f2) {
 ; CHECK-LABEL: cvt_rn_f16x2_f32(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rn_f16x2_f32_param_0];
@@ -92,7 +92,7 @@ define <2 x half> @cvt_rn_relu_f16x2_f32(float %f1, float %f2) {
 ; CHECK-LABEL: cvt_rn_relu_f16x2_f32(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rn_relu_f16x2_f32_param_0];
@@ -108,7 +108,7 @@ define <2 x half> @cvt_rz_f16x2_f32(float %f1, float %f2) {
 ; CHECK-LABEL: cvt_rz_f16x2_f32(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rz_f16x2_f32_param_0];
@@ -124,7 +124,7 @@ define <2 x half> @cvt_rz_relu_f16x2_f32(float %f1, float %f2) {
 ; CHECK-LABEL: cvt_rz_relu_f16x2_f32(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rz_relu_f16x2_f32_param_0];
@@ -145,7 +145,7 @@ define bfloat @cvt_rn_bf16_f32(float %f1) {
 ; CHECK-LABEL: cvt_rn_bf16_f32(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<2>;
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rn_bf16_f32_param_0];
@@ -160,7 +160,7 @@ define bfloat @cvt_rn_relu_bf16_f32(float %f1) {
 ; CHECK-LABEL: cvt_rn_relu_bf16_f32(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<2>;
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rn_relu_bf16_f32_param_0];
@@ -175,7 +175,7 @@ define bfloat @cvt_rz_bf16_f32(float %f1) {
 ; CHECK-LABEL: cvt_rz_bf16_f32(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<2>;
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rz_bf16_f32_param_0];
@@ -190,7 +190,7 @@ define bfloat @cvt_rz_relu_bf16_f32(float %f1) {
 ; CHECK-LABEL: cvt_rz_relu_bf16_f32(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<2>;
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rz_relu_bf16_f32_param_0];
@@ -210,7 +210,7 @@ define i32 @cvt_rna_tf32_f32(float %f1) {
 ; CHECK-LABEL: cvt_rna_tf32_f32(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rna_tf32_f32_param_0];
@@ -228,7 +228,7 @@ define <2 x bfloat> @fold_ff2bf16x2(float %lo, float %hi) {
 ; CHECK-LABEL: fold_ff2bf16x2(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [fold_ff2bf16x2_param_0];
@@ -247,7 +247,7 @@ define <2 x half> @fold_ff2f16x2(float %lo, float %hi) {
 ; CHECK-LABEL: fold_ff2f16x2(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [fold_ff2f16x2_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/convert-sm90.ll b/llvm/test/CodeGen/NVPTX/convert-sm90.ll
index 5f610e0e91f88..340117f98cd94 100644
--- a/llvm/test/CodeGen/NVPTX/convert-sm90.ll
+++ b/llvm/test/CodeGen/NVPTX/convert-sm90.ll
@@ -11,7 +11,7 @@ define i32 @cvt_rn_tf32_f32(float %f1) {
 ; CHECK-LABEL: cvt_rn_tf32_f32(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rn_tf32_f32_param_0];
@@ -26,7 +26,7 @@ define i32 @cvt_rn_relu_tf32_f32(float %f1) {
 ; CHECK-LABEL: cvt_rn_relu_tf32_f32(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rn_relu_tf32_f32_param_0];
@@ -41,7 +41,7 @@ define i32 @cvt_rz_tf32_f32(float %f1) {
 ; CHECK-LABEL: cvt_rz_tf32_f32(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rz_tf32_f32_param_0];
@@ -56,7 +56,7 @@ define i32 @cvt_rz_relu_tf32_f32(float %f1) {
 ; CHECK-LABEL: cvt_rz_relu_tf32_f32(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [cvt_rz_relu_tf32_f32_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/copysign.ll b/llvm/test/CodeGen/NVPTX/copysign.ll
index 843ef4dbde367..2e305e683d777 100644
--- a/llvm/test/CodeGen/NVPTX/copysign.ll
+++ b/llvm/test/CodeGen/NVPTX/copysign.ll
@@ -8,7 +8,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 define float @fcopysign_f_f(float %a, float %b) {
 ; CHECK-LABEL: fcopysign_f_f(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<4>;
+; CHECK-NEXT:    .reg .b32 %f<4>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [fcopysign_f_f_param_0];
@@ -23,7 +23,7 @@ define float @fcopysign_f_f(float %a, float %b) {
 define double @fcopysign_d_d(double %a, double %b) {
 ; CHECK-LABEL: fcopysign_d_d(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f64 %fd<4>;
+; CHECK-NEXT:    .reg .b64 %fd<4>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f64 %fd1, [fcopysign_d_d_param_0];
@@ -39,7 +39,7 @@ define float @fcopysign_f_d(float %a, double %b) {
 ; CHECK-LABEL: fcopysign_f_d(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .pred %p<2>;
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NEXT:    .reg .b64 %rd<4>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -63,7 +63,7 @@ define float @fcopysign_f_h(float %a, half %b) {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .pred %p<2>;
 ; CHECK-NEXT:    .reg .b16 %rs<4>;
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [fcopysign_f_h_param_0];
@@ -86,7 +86,7 @@ define double @fcopysign_d_f(double %a, float %b) {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .pred %p<2>;
 ; CHECK-NEXT:    .reg .b32 %r<4>;
-; CHECK-NEXT:    .reg .f64 %fd<5>;
+; CHECK-NEXT:    .reg .b64 %fd<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f64 %fd1, [fcopysign_d_f_param_0];
@@ -109,7 +109,7 @@ define double @fcopysign_d_h(double %a, half %b) {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .pred %p<2>;
 ; CHECK-NEXT:    .reg .b16 %rs<4>;
-; CHECK-NEXT:    .reg .f64 %fd<5>;
+; CHECK-NEXT:    .reg .b64 %fd<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f64 %fd1, [fcopysign_d_h_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/distributed-shared-cluster.ll b/llvm/test/CodeGen/NVPTX/distributed-shared-cluster.ll
index 92b73799d6f1d..a233616563085 100644
--- a/llvm/test/CodeGen/NVPTX/distributed-shared-cluster.ll
+++ b/llvm/test/CodeGen/NVPTX/distributed-shared-cluster.ll
@@ -59,9 +59,9 @@ define void @test_distributed_shared_cluster_float_atomic(ptr addrspace(7) %dsme
 ; CHECK-LABEL: test_distributed_shared_cluster_float_atomic(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<5>;
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<2>;
+; CHECK-NEXT:    .reg .b64 %fd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0: // %entry
 ; CHECK-NEXT:    ld.param.u64 %rd1, [test_distributed_shared_cluster_float_atomic_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/div.ll b/llvm/test/CodeGen/NVPTX/div.ll
index 4f9d58758ca9e..f8711e3a83591 100644
--- a/llvm/test/CodeGen/NVPTX/div.ll
+++ b/llvm/test/CodeGen/NVPTX/div.ll
@@ -5,7 +5,7 @@
 define float @div_full(float %a, float %b) {
 ; CHECK-LABEL: div_full(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<9>;
+; CHECK-NEXT:    .reg .b32 %f<9>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [div_full_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/f16-abs.ll b/llvm/test/CodeGen/NVPTX/f16-abs.ll
index d12653e813bd1..d3aaedf84bce9 100644
--- a/llvm/test/CodeGen/NVPTX/f16-abs.ll
+++ b/llvm/test/CodeGen/NVPTX/f16-abs.ll
@@ -49,7 +49,7 @@ define half @test_fabs(half %a) {
 ; CHECK-NOF16-LABEL: test_fabs(
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<3>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<3>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b16 %rs1, [test_fabs_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll b/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
index e9edabd1ee8af..e854e5a6e5aaa 100644
--- a/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
@@ -109,7 +109,7 @@ define <2 x half> @test_fadd(<2 x half> %a, <2 x half> %b) #0 {
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<4>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<7>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<7>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r2, [test_fadd_param_1];
@@ -148,7 +148,7 @@ define <2 x half> @test_fadd_imm_0(<2 x half> %a) #0 {
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<5>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<5>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r1, [test_fadd_imm_0_param_0];
@@ -182,7 +182,7 @@ define <2 x half> @test_fadd_imm_1(<2 x half> %a) #0 {
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<5>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<5>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r1, [test_fadd_imm_1_param_0];
@@ -216,7 +216,7 @@ define <2 x half> @test_fsub(<2 x half> %a, <2 x half> %b) #0 {
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<4>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<7>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<7>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r2, [test_fsub_param_1];
@@ -254,7 +254,7 @@ define <2 x half> @test_fneg(<2 x half> %a) #0 {
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<5>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<6>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<6>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r1, [test_fneg_param_0];
@@ -289,7 +289,7 @@ define <2 x half> @test_fmul(<2 x half> %a, <2 x half> %b) #0 {
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<4>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<7>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<7>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r2, [test_fmul_param_1];
@@ -316,7 +316,7 @@ define <2 x half> @test_fdiv(<2 x half> %a, <2 x half> %b) #0 {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NEXT:    .reg .b32 %r<4>;
-; CHECK-NEXT:    .reg .f32 %f<7>;
+; CHECK-NEXT:    .reg .b32 %f<7>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.b32 %r2, [test_fdiv_param_1];
@@ -351,7 +351,7 @@ define <2 x half> @test_frem(<2 x half> %a, <2 x half> %b) #0 {
 ; CHECK-NEXT:    .reg .pred %p<3>;
 ; CHECK-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NEXT:    .reg .b32 %r<4>;
-; CHECK-NEXT:    .reg .f32 %f<15>;
+; CHECK-NEXT:    .reg .b32 %f<15>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.b32 %r2, [test_frem_param_1];
@@ -591,7 +591,7 @@ define <2 x half> @test_select_cc(<2 x half> %a, <2 x half> %b, <2 x half> %c, <
 ; CHECK-NOF16-NEXT:    .reg .pred %p<3>;
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<11>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<6>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<5>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r4, [test_select_cc_param_3];
@@ -623,7 +623,7 @@ define <2 x float> @test_select_cc_f32_f16(<2 x float> %a, <2 x float> %b,
 ; CHECK-F16:       {
 ; CHECK-F16-NEXT:    .reg .pred %p<3>;
 ; CHECK-F16-NEXT:    .reg .b32 %r<3>;
-; CHECK-F16-NEXT:    .reg .f32 %f<7>;
+; CHECK-F16-NEXT:    .reg .b32 %f<7>;
 ; CHECK-F16-EMPTY:
 ; CHECK-F16-NEXT:  // %bb.0:
 ; CHECK-F16-NEXT:    ld.param.v2.f32 {%f3, %f4}, [test_select_cc_f32_f16_param_1];
@@ -641,7 +641,7 @@ define <2 x float> @test_select_cc_f32_f16(<2 x float> %a, <2 x float> %b,
 ; CHECK-NOF16-NEXT:    .reg .pred %p<3>;
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<5>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<11>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<11>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.v2.f32 {%f3, %f4}, [test_select_cc_f32_f16_param_1];
@@ -672,7 +672,7 @@ define <2 x half> @test_select_cc_f16_f32(<2 x half> %a, <2 x half> %b,
 ; CHECK-NEXT:    .reg .pred %p<3>;
 ; CHECK-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NEXT:    .reg .b32 %r<4>;
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.v2.f32 {%f3, %f4}, [test_select_cc_f16_f32_param_3];
@@ -716,7 +716,7 @@ define <2 x i1> @test_fcmp_une(<2 x half> %a, <2 x half> %b) #0 {
 ; CHECK-NOF16-NEXT:    .reg .pred %p<3>;
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<5>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r2, [test_fcmp_une_param_1];
@@ -760,7 +760,7 @@ define <2 x i1> @test_fcmp_ueq(<2 x half> %a, <2 x half> %b) #0 {
 ; CHECK-NOF16-NEXT:    .reg .pred %p<3>;
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<5>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r2, [test_fcmp_ueq_param_1];
@@ -804,7 +804,7 @@ define <2 x i1> @test_fcmp_ugt(<2 x half> %a, <2 x half> %b) #0 {
 ; CHECK-NOF16-NEXT:    .reg .pred %p<3>;
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<5>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r2, [test_fcmp_ugt_param_1];
@@ -848,7 +848,7 @@ define <2 x i1> @test_fcmp_uge(<2 x half> %a, <2 x half> %b) #0 {
 ; CHECK-NOF16-NEXT:    .reg .pred %p<3>;
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<5>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r2, [test_fcmp_uge_param_1];
@@ -892,7 +892,7 @@ define <2 x i1> @test_fcmp_ult(<2 x half> %a, <2 x half> %b) #0 {
 ; CHECK-NOF16-NEXT:    .reg .pred %p<3>;
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<5>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r2, [test_fcmp_ult_param_1];
@@ -936,7 +936,7 @@ define <2 x i1> @test_fcmp_ule(<2 x half> %a, <2 x half> %b) #0 {
 ; CHECK-NOF16-NEXT:    .reg .pred %p<3>;
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<5>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r2, [test_fcmp_ule_param_1];
@@ -981,7 +981,7 @@ define <2 x i1> @test_fcmp_uno(<2 x half> %a, <2 x half> %b) #0 {
 ; CHECK-NOF16-NEXT:    .reg .pred %p<3>;
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<5>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r2, [test_fcmp_uno_param_1];
@@ -1025,7 +1025,7 @@ define <2 x i1> @test_fcmp_one(<2 x half> %a, <2 x half> %b) #0 {
 ; CHECK-NOF16-NEXT:    .reg .pred %p<3>;
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<5>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r2, [test_fcmp_one_param_1];
@@ -1069,7 +1069,7 @@ define <2 x i1> @test_fcmp_oeq(<2 x half> %a, <2 x half> %b) #0 {
 ; CHECK-NOF16-NEXT:    .reg .pred %p<3>;
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<5>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r2, [test_fcmp_oeq_param_1];
@@ -1113,7 +1113,7 @@ define <2 x i1> @test_fcmp_ogt(<2 x half> %a, <2 x half> %b) #0 {
 ; CHECK-NOF16-NEXT:    .reg .pred %p<3>;
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<5>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r2, [test_fcmp_ogt_param_1];
@@ -1157,7 +1157,7 @@ define <2 x i1> @test_fcmp_oge(<2 x half> %a, <2 x half> %b) #0 {
 ; CHECK-NOF16-NEXT:    .reg .pred %p<3>;
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<5>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r2, [test_fcmp_oge_param_1];
@@ -1201,7 +1201,7 @@ define <2 x i1> @test_fcmp_olt(<2 x half> %a, <2 x half> %b) #0 {
 ; CHECK-NOF16-NEXT:    .reg .pred %p<3>;
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<5>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r2, [test_fcmp_olt_param_1];
@@ -1245,7 +1245,7 @@ define <2 x i1> @test_fcmp_ole(<2 x half> %a, <2 x half> %b) #0 {
 ; CHECK-NOF16-NEXT:    .reg .pred %p<3>;
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<5>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r2, [test_fcmp_ole_param_1];
@@ -1289,7 +1289,7 @@ define <2 x i1> @test_fcmp_ord(<2 x half> %a, <2 x half> %b) #0 {
 ; CHECK-NOF16-NEXT:    .reg .pred %p<3>;
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<5>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r2, [test_fcmp_ord_param_1];
@@ -1472,7 +1472,7 @@ define <2 x half> @test_uitofp_2xi32_fadd(<2 x i32> %a, <2 x half> %b) #0 {
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<5>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<7>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<7>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.v2.u32 {%r1, %r2}, [test_uitofp_2xi32_fadd_param_0];
@@ -1516,7 +1516,7 @@ define <2 x half> @test_sitofp_2xi32_fadd(<2 x i32> %a, <2 x half> %b) #0 {
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<5>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<7>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<7>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.v2.u32 {%r1, %r2}, [test_sitofp_2xi32_fadd_param_0];
@@ -1545,7 +1545,7 @@ define <2 x half> @test_fptrunc_2xfloat(<2 x float> %a) #0 {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<3>;
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.v2.f32 {%f1, %f2}, [test_fptrunc_2xfloat_param_0];
@@ -1563,7 +1563,7 @@ define <2 x half> @test_fptrunc_2xdouble(<2 x double> %a) #0 {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<3>;
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.v2.f64 {%fd1, %fd2}, [test_fptrunc_2xdouble_param_0];
@@ -1581,7 +1581,7 @@ define <2 x float> @test_fpext_2xfloat(<2 x half> %a) #0 {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<3>;
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.b32 %r1, [test_fpext_2xfloat_param_0];
@@ -1599,7 +1599,7 @@ define <2 x double> @test_fpext_2xdouble(<2 x half> %a) #0 {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<3>;
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.b32 %r1, [test_fpext_2xdouble_param_0];
@@ -1643,7 +1643,7 @@ define <2 x half> @test_bitcast_float_to_2xhalf(float %a) #0 {
 ; CHECK-LABEL: test_bitcast_float_to_2xhalf(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [test_bitcast_float_to_2xhalf_param_0];
@@ -1658,7 +1658,7 @@ define float @test_bitcast_2xhalf_to_float(<2 x half> %a) #0 {
 ; CHECK-LABEL: test_bitcast_2xhalf_to_float(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u32 %r1, [test_bitcast_2xhalf_to_float_param_0];
@@ -1698,7 +1698,7 @@ define <2 x half> @test_sqrt(<2 x half> %a) #0 {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<5>;
 ; CHECK-NEXT:    .reg .b32 %r<3>;
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.b32 %r1, [test_sqrt_param_0];
@@ -1728,7 +1728,7 @@ define <2 x half> @test_sin(<2 x half> %a) #0 #1 {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<5>;
 ; CHECK-NEXT:    .reg .b32 %r<3>;
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.b32 %r1, [test_sin_param_0];
@@ -1751,7 +1751,7 @@ define <2 x half> @test_cos(<2 x half> %a) #0 #1 {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<5>;
 ; CHECK-NEXT:    .reg .b32 %r<3>;
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.b32 %r1, [test_cos_param_0];
@@ -1829,7 +1829,7 @@ define <2 x half> @test_fma(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 {
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<9>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<5>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<9>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<9>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r3, [test_fma_param_2];
@@ -1870,7 +1870,7 @@ define <2 x half> @test_fabs(<2 x half> %a) #0 {
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<5>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<5>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r1, [test_fabs_param_0];
@@ -1893,7 +1893,7 @@ define <2 x half> @test_minnum(<2 x half> %a, <2 x half> %b) #0 {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NEXT:    .reg .b32 %r<4>;
-; CHECK-NEXT:    .reg .f32 %f<7>;
+; CHECK-NEXT:    .reg .b32 %f<7>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.b32 %r2, [test_minnum_param_1];
@@ -1920,7 +1920,7 @@ define <2 x half> @test_maxnum(<2 x half> %a, <2 x half> %b) #0 {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NEXT:    .reg .b32 %r<4>;
-; CHECK-NEXT:    .reg .f32 %f<7>;
+; CHECK-NEXT:    .reg .b32 %f<7>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.b32 %r2, [test_maxnum_param_1];
@@ -1984,7 +1984,7 @@ define <2 x half> @test_copysign_f32(<2 x half> %a, <2 x float> %b) #0 {
 ; CHECK-F16:       {
 ; CHECK-F16-NEXT:    .reg .b16 %rs<3>;
 ; CHECK-F16-NEXT:    .reg .b32 %r<6>;
-; CHECK-F16-NEXT:    .reg .f32 %f<3>;
+; CHECK-F16-NEXT:    .reg .b32 %f<3>;
 ; CHECK-F16-EMPTY:
 ; CHECK-F16-NEXT:  // %bb.0:
 ; CHECK-F16-NEXT:    ld.param.v2.f32 {%f1, %f2}, [test_copysign_f32_param_1];
@@ -2002,7 +2002,7 @@ define <2 x half> @test_copysign_f32(<2 x half> %a, <2 x float> %b) #0 {
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<9>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<7>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<3>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<3>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.v2.f32 {%f1, %f2}, [test_copysign_f32_param_1];
@@ -2031,7 +2031,7 @@ define <2 x half> @test_copysign_f64(<2 x half> %a, <2 x double> %b) #0 {
 ; CHECK-F16:       {
 ; CHECK-F16-NEXT:    .reg .b16 %rs<3>;
 ; CHECK-F16-NEXT:    .reg .b32 %r<6>;
-; CHECK-F16-NEXT:    .reg .f64 %fd<3>;
+; CHECK-F16-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-F16-EMPTY:
 ; CHECK-F16-NEXT:  // %bb.0:
 ; CHECK-F16-NEXT:    ld.param.v2.f64 {%fd1, %fd2}, [test_copysign_f64_param_1];
@@ -2050,7 +2050,7 @@ define <2 x half> @test_copysign_f64(<2 x half> %a, <2 x double> %b) #0 {
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<9>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<3>;
 ; CHECK-NOF16-NEXT:    .reg .b64 %rd<7>;
-; CHECK-NOF16-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NOF16-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.v2.f64 {%fd1, %fd2}, [test_copysign_f64_param_1];
@@ -2081,7 +2081,7 @@ define <2 x float> @test_copysign_extended(<2 x half> %a, <2 x half> %b) #0 {
 ; CHECK-F16:       {
 ; CHECK-F16-NEXT:    .reg .b16 %rs<3>;
 ; CHECK-F16-NEXT:    .reg .b32 %r<6>;
-; CHECK-F16-NEXT:    .reg .f32 %f<3>;
+; CHECK-F16-NEXT:    .reg .b32 %f<3>;
 ; CHECK-F16-EMPTY:
 ; CHECK-F16-NEXT:  // %bb.0:
 ; CHECK-F16-NEXT:    ld.param.b32 %r2, [test_copysign_extended_param_1];
@@ -2099,7 +2099,7 @@ define <2 x float> @test_copysign_extended(<2 x half> %a, <2 x half> %b) #0 {
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<11>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<3>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<3>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r2, [test_copysign_extended_param_1];
@@ -2236,7 +2236,7 @@ define <2 x half> @test_round(<2 x half> %a) #0 {
 ; CHECK-NEXT:    .reg .pred %p<5>;
 ; CHECK-NEXT:    .reg .b16 %rs<5>;
 ; CHECK-NEXT:    .reg .b32 %r<9>;
-; CHECK-NEXT:    .reg .f32 %f<17>;
+; CHECK-NEXT:    .reg .b32 %f<17>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.b32 %r1, [test_round_param_0];
@@ -2293,7 +2293,7 @@ define <2 x half> @test_fmuladd(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<9>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<5>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<9>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<9>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r3, [test_fmuladd_param_2];
diff --git a/llvm/test/CodeGen/NVPTX/f32-ex2.ll b/llvm/test/CodeGen/NVPTX/f32-ex2.ll
index c9eff2a8ff17d..2c5c8146fbf61 100644
--- a/llvm/test/CodeGen/NVPTX/f32-ex2.ll
+++ b/llvm/test/CodeGen/NVPTX/f32-ex2.ll
@@ -9,7 +9,7 @@ declare float @llvm.nvvm.ex2.approx.f(float)
 define float @ex2_float(float %0) {
 ; CHECK-LABEL: ex2_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [ex2_float_param_0];
@@ -24,7 +24,7 @@ define float @ex2_float(float %0) {
 define float @ex2_float_ftz(float %0) {
 ; CHECK-LABEL: ex2_float_ftz(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [ex2_float_ftz_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/f32-lg2.ll b/llvm/test/CodeGen/NVPTX/f32-lg2.ll
index 43c521978fed8..9dac3083d6cb8 100644
--- a/llvm/test/CodeGen/NVPTX/f32-lg2.ll
+++ b/llvm/test/CodeGen/NVPTX/f32-lg2.ll
@@ -10,7 +10,7 @@ declare float @llvm.nvvm.lg2.approx.ftz.f(float)
 define float @lg2_float(float %0) {
 ; CHECK-LABEL: lg2_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [lg2_float_param_0];
@@ -25,7 +25,7 @@ define float @lg2_float(float %0) {
 define float @lg2_float_ftz(float %0) {
 ; CHECK-LABEL: lg2_float_ftz(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [lg2_float_ftz_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/fabs-intrinsics.ll b/llvm/test/CodeGen/NVPTX/fabs-intrinsics.ll
index dd9ef220a9b47..d9c5a527b901c 100644
--- a/llvm/test/CodeGen/NVPTX/fabs-intrinsics.ll
+++ b/llvm/test/CodeGen/NVPTX/fabs-intrinsics.ll
@@ -18,7 +18,7 @@ declare <2 x bfloat> @llvm.nvvm.fabs.v2bf16(<2 x bfloat>)
 define float @fabs_float(float %a) {
 ; CHECK-LABEL: fabs_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [fabs_float_param_0];
@@ -32,7 +32,7 @@ define float @fabs_float(float %a) {
 define float @fabs_float_ftz(float %a) {
 ; CHECK-LABEL: fabs_float_ftz(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [fabs_float_ftz_param_0];
@@ -46,7 +46,7 @@ define float @fabs_float_ftz(float %a) {
 define double @fabs_double(double %a) {
 ; CHECK-LABEL: fabs_double(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f64 %fd1, [fabs_double_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/fexp2.ll b/llvm/test/CodeGen/NVPTX/fexp2.ll
index 7e485dca65764..4664d700209fa 100644
--- a/llvm/test/CodeGen/NVPTX/fexp2.ll
+++ b/llvm/test/CodeGen/NVPTX/fexp2.ll
@@ -13,7 +13,7 @@ target triple = "nvptx64-nvidia-cuda"
 define float @exp2_test(float %in) {
 ; CHECK-LABEL: exp2_test(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0: // %entry
 ; CHECK-NEXT:    ld.param.f32 %f1, [exp2_test_param_0];
@@ -23,7 +23,7 @@ define float @exp2_test(float %in) {
 ;
 ; CHECK-FP16-LABEL: exp2_test(
 ; CHECK-FP16:       {
-; CHECK-FP16-NEXT:    .reg .f32 %f<3>;
+; CHECK-FP16-NEXT:    .reg .b32 %f<3>;
 ; CHECK-FP16-EMPTY:
 ; CHECK-FP16-NEXT:  // %bb.0: // %entry
 ; CHECK-FP16-NEXT:    ld.param.f32 %f1, [exp2_test_param_0];
@@ -33,7 +33,7 @@ define float @exp2_test(float %in) {
 ;
 ; CHECK-BF16-LABEL: exp2_test(
 ; CHECK-BF16:       {
-; CHECK-BF16-NEXT:    .reg .f32 %f<3>;
+; CHECK-BF16-NEXT:    .reg .b32 %f<3>;
 ; CHECK-BF16-EMPTY:
 ; CHECK-BF16-NEXT:  // %bb.0: // %entry
 ; CHECK-BF16-NEXT:    ld.param.f32 %f1, [exp2_test_param_0];
@@ -49,7 +49,7 @@ entry:
 define float @exp2_ftz_test(float %in) #0 {
 ; CHECK-LABEL: exp2_ftz_test(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0: // %entry
 ; CHECK-NEXT:    ld.param.f32 %f1, [exp2_ftz_test_param_0];
@@ -59,7 +59,7 @@ define float @exp2_ftz_test(float %in) #0 {
 ;
 ; CHECK-FP16-LABEL: exp2_ftz_test(
 ; CHECK-FP16:       {
-; CHECK-FP16-NEXT:    .reg .f32 %f<3>;
+; CHECK-FP16-NEXT:    .reg .b32 %f<3>;
 ; CHECK-FP16-EMPTY:
 ; CHECK-FP16-NEXT:  // %bb.0: // %entry
 ; CHECK-FP16-NEXT:    ld.param.f32 %f1, [exp2_ftz_test_param_0];
@@ -69,7 +69,7 @@ define float @exp2_ftz_test(float %in) #0 {
 ;
 ; CHECK-BF16-LABEL: exp2_ftz_test(
 ; CHECK-BF16:       {
-; CHECK-BF16-NEXT:    .reg .f32 %f<3>;
+; CHECK-BF16-NEXT:    .reg .b32 %f<3>;
 ; CHECK-BF16-EMPTY:
 ; CHECK-BF16-NEXT:  // %bb.0: // %entry
 ; CHECK-BF16-NEXT:    ld.param.f32 %f1, [exp2_ftz_test_param_0];
@@ -85,7 +85,7 @@ entry:
 define <2 x float> @exp2_test_v(<2 x float> %in) {
 ; CHECK-LABEL: exp2_test_v(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0: // %entry
 ; CHECK-NEXT:    ld.param.v2.f32 {%f1, %f2}, [exp2_test_v_param_0];
@@ -96,7 +96,7 @@ define <2 x float> @exp2_test_v(<2 x float> %in) {
 ;
 ; CHECK-FP16-LABEL: exp2_test_v(
 ; CHECK-FP16:       {
-; CHECK-FP16-NEXT:    .reg .f32 %f<5>;
+; CHECK-FP16-NEXT:    .reg .b32 %f<5>;
 ; CHECK-FP16-EMPTY:
 ; CHECK-FP16-NEXT:  // %bb.0: // %entry
 ; CHECK-FP16-NEXT:    ld.param.v2.f32 {%f1, %f2}, [exp2_test_v_param_0];
@@ -107,7 +107,7 @@ define <2 x float> @exp2_test_v(<2 x float> %in) {
 ;
 ; CHECK-BF16-LABEL: exp2_test_v(
 ; CHECK-BF16:       {
-; CHECK-BF16-NEXT:    .reg .f32 %f<5>;
+; CHECK-BF16-NEXT:    .reg .b32 %f<5>;
 ; CHECK-BF16-EMPTY:
 ; CHECK-BF16-NEXT:  // %bb.0: // %entry
 ; CHECK-BF16-NEXT:    ld.param.v2.f32 {%f1, %f2}, [exp2_test_v_param_0];
@@ -127,7 +127,7 @@ define half @exp2_f16_test(half %in) {
 ; CHECK-LABEL: exp2_f16_test(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<3>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0: // %entry
 ; CHECK-NEXT:    ld.param.b16 %rs1, [exp2_f16_test_param_0];
@@ -167,7 +167,7 @@ define half @exp2_f16_ftz_test(half %in) #0 {
 ; CHECK-LABEL: exp2_f16_ftz_test(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<3>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0: // %entry
 ; CHECK-NEXT:    ld.param.b16 %rs1, [exp2_f16_ftz_test_param_0];
@@ -207,7 +207,7 @@ define <2 x half> @exp2_f16_test_v(<2 x half> %in) {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<5>;
 ; CHECK-NEXT:    .reg .b32 %r<3>;
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0: // %entry
 ; CHECK-NEXT:    ld.param.b32 %r1, [exp2_f16_test_v_param_0];
@@ -256,7 +256,7 @@ define bfloat @exp2_bf16_test(bfloat %in) {
 ; CHECK-NEXT:    .reg .pred %p<2>;
 ; CHECK-NEXT:    .reg .b16 %rs<2>;
 ; CHECK-NEXT:    .reg .b32 %r<9>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0: // %entry
 ; CHECK-NEXT:    ld.param.u16 %r1, [exp2_bf16_test_param_0];
@@ -279,7 +279,7 @@ define bfloat @exp2_bf16_test(bfloat %in) {
 ; CHECK-FP16-NEXT:    .reg .pred %p<2>;
 ; CHECK-FP16-NEXT:    .reg .b16 %rs<2>;
 ; CHECK-FP16-NEXT:    .reg .b32 %r<9>;
-; CHECK-FP16-NEXT:    .reg .f32 %f<3>;
+; CHECK-FP16-NEXT:    .reg .b32 %f<3>;
 ; CHECK-FP16-EMPTY:
 ; CHECK-FP16-NEXT:  // %bb.0: // %entry
 ; CHECK-FP16-NEXT:    ld.param.u16 %r1, [exp2_bf16_test_param_0];
@@ -318,7 +318,7 @@ define <2 x bfloat> @exp2_bf16_test_v(<2 x bfloat> %in) {
 ; CHECK-NEXT:    .reg .pred %p<3>;
 ; CHECK-NEXT:    .reg .b16 %rs<3>;
 ; CHECK-NEXT:    .reg .b32 %r<19>;
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0: // %entry
 ; CHECK-NEXT:    ld.param.b32 %r1, [exp2_bf16_test_v_param_0];
@@ -354,7 +354,7 @@ define <2 x bfloat> @exp2_bf16_test_v(<2 x bfloat> %in) {
 ; CHECK-FP16-NEXT:    .reg .pred %p<3>;
 ; CHECK-FP16-NEXT:    .reg .b16 %rs<3>;
 ; CHECK-FP16-NEXT:    .reg .b32 %r<19>;
-; CHECK-FP16-NEXT:    .reg .f32 %f<5>;
+; CHECK-FP16-NEXT:    .reg .b32 %f<5>;
 ; CHECK-FP16-EMPTY:
 ; CHECK-FP16-NEXT:  // %bb.0: // %entry
 ; CHECK-FP16-NEXT:    ld.param.b32 %r1, [exp2_bf16_test_v_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/flog2.ll b/llvm/test/CodeGen/NVPTX/flog2.ll
index ff762dcf74b2f..4dfed3dd944ae 100644
--- a/llvm/test/CodeGen/NVPTX/flog2.ll
+++ b/llvm/test/CodeGen/NVPTX/flog2.ll
@@ -7,7 +7,7 @@ target triple = "nvptx64-nvidia-cuda"
 define float @log2_test(float %in) {
 ; CHECK-LABEL: log2_test(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0: // %entry
 ; CHECK-NEXT:    ld.param.f32 %f1, [log2_test_param_0];
@@ -23,7 +23,7 @@ entry:
 define float @log2_ftz_test(float %in) #0 {
 ; CHECK-LABEL: log2_ftz_test(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0: // %entry
 ; CHECK-NEXT:    ld.param.f32 %f1, [log2_ftz_test_param_0];
@@ -39,7 +39,7 @@ entry:
 define <2 x float> @log2_test_v(<2 x float> %in) {
 ; CHECK-LABEL: log2_test_v(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0: // %entry
 ; CHECK-NEXT:    ld.param.v2.f32 {%f1, %f2}, [log2_test_v_param_0];
@@ -59,7 +59,7 @@ define half @log2_f16_test(half %in) {
 ; CHECK-LABEL: log2_f16_test(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<3>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0: // %entry
 ; CHECK-NEXT:    ld.param.b16 %rs1, [log2_f16_test_param_0];
@@ -78,7 +78,7 @@ define half @log2_f16_ftz_test(half %in) #0 {
 ; CHECK-LABEL: log2_f16_ftz_test(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<3>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0: // %entry
 ; CHECK-NEXT:    ld.param.b16 %rs1, [log2_f16_ftz_test_param_0];
@@ -98,7 +98,7 @@ define <2 x half> @log2_f16_test_v(<2 x half> %in) {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<5>;
 ; CHECK-NEXT:    .reg .b32 %r<3>;
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0: // %entry
 ; CHECK-NEXT:    ld.param.b32 %r1, [log2_f16_test_v_param_0];
@@ -126,7 +126,7 @@ define bfloat @log2_bf16_test(bfloat %in) {
 ; CHECK-NEXT:    .reg .pred %p<2>;
 ; CHECK-NEXT:    .reg .b16 %rs<2>;
 ; CHECK-NEXT:    .reg .b32 %r<9>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0: // %entry
 ; CHECK-NEXT:    ld.param.u16 %r1, [log2_bf16_test_param_0];
@@ -155,7 +155,7 @@ define bfloat @log2_bf16_ftz_test(bfloat %in) #0 {
 ; CHECK-NEXT:    .reg .pred %p<2>;
 ; CHECK-NEXT:    .reg .b16 %rs<2>;
 ; CHECK-NEXT:    .reg .b32 %r<9>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0: // %entry
 ; CHECK-NEXT:    ld.param.u16 %r1, [log2_bf16_ftz_test_param_0];
@@ -184,7 +184,7 @@ define <2 x bfloat> @log2_bf16_test_v(<2 x bfloat> %in) {
 ; CHECK-NEXT:    .reg .pred %p<3>;
 ; CHECK-NEXT:    .reg .b16 %rs<3>;
 ; CHECK-NEXT:    .reg .b32 %r<19>;
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0: // %entry
 ; CHECK-NEXT:    ld.param.b32 %r1, [log2_bf16_test_v_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll b/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
index 7dce894620e6b..9051a0bce14cd 100644
--- a/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
+++ b/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
@@ -198,7 +198,7 @@ define half @fma_f16_expanded_maxnum_no_nans(half %a, half %b, half %c) #0 {
 ; CHECK-SM70-LABEL: fma_f16_expanded_maxnum_no_nans(
 ; CHECK-SM70:       {
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<6>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<3>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<3>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.b16 %rs1, [fma_f16_expanded_maxnum_no_nans_param_0];
@@ -250,7 +250,7 @@ define bfloat @fma_bf16_expanded_unsafe_with_nans(bfloat %a, bfloat %b, bfloat %
 ; CHECK-SM70-NEXT:    .reg .pred %p<3>;
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<3>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<14>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<6>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<6>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.u16 %r1, [fma_bf16_expanded_unsafe_with_nans_param_2];
@@ -314,7 +314,7 @@ define bfloat @fma_bf16_expanded_no_nans(bfloat %a, bfloat %b, bfloat %c) #0 {
 ; CHECK-SM70-NEXT:    .reg .pred %p<3>;
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<3>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<14>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<6>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<6>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.u16 %r1, [fma_bf16_expanded_no_nans_param_2];
@@ -372,7 +372,7 @@ define bfloat @fma_bf16_expanded_no_nans_multiple_uses_of_fma(bfloat %a, bfloat
 ; CHECK-FTZ:       {
 ; CHECK-FTZ-NEXT:    .reg .b16 %rs<9>;
 ; CHECK-FTZ-NEXT:    .reg .b32 %r<7>;
-; CHECK-FTZ-NEXT:    .reg .f32 %f<6>;
+; CHECK-FTZ-NEXT:    .reg .b32 %f<6>;
 ; CHECK-FTZ-EMPTY:
 ; CHECK-FTZ-NEXT:  // %bb.0:
 ; CHECK-FTZ-NEXT:    ld.param.b16 %rs1, [fma_bf16_expanded_no_nans_multiple_uses_of_fma_param_0];
@@ -402,7 +402,7 @@ define bfloat @fma_bf16_expanded_no_nans_multiple_uses_of_fma(bfloat %a, bfloat
 ; CHECK-SM70-NEXT:    .reg .pred %p<5>;
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<4>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<29>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<10>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<10>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.u16 %r1, [fma_bf16_expanded_no_nans_multiple_uses_of_fma_param_2];
@@ -490,7 +490,7 @@ define bfloat @fma_bf16_expanded_maxnum_no_nans(bfloat %a, bfloat %b, bfloat %c)
 ; CHECK-SM70-NEXT:    .reg .pred %p<3>;
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<2>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<20>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<7>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<7>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.u16 %r1, [fma_bf16_expanded_maxnum_no_nans_param_2];
@@ -731,7 +731,7 @@ define <2 x half> @fma_f16x2_expanded_maxnum_no_nans(<2 x half> %a, <2 x half> %
 ; CHECK-SM70:       {
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<5>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<6>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<5>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<5>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.b32 %r1, [fma_f16x2_expanded_maxnum_no_nans_param_2];
@@ -788,7 +788,7 @@ define <2 x bfloat> @fma_bf16x2_expanded_unsafe_with_nans(<2 x bfloat> %a, <2 x
 ; CHECK-SM70-NEXT:    .reg .pred %p<5>;
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<11>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<31>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<11>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<11>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.b32 %r1, [fma_bf16x2_expanded_unsafe_with_nans_param_0];
@@ -881,7 +881,7 @@ define <2 x bfloat> @fma_bf16x2_expanded_no_nans(<2 x bfloat> %a, <2 x bfloat> %
 ; CHECK-SM70-NEXT:    .reg .pred %p<5>;
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<11>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<31>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<11>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<11>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.b32 %r1, [fma_bf16x2_expanded_no_nans_param_0];
@@ -968,7 +968,7 @@ define <2 x bfloat> @fma_bf16x2_expanded_no_nans_multiple_uses_of_fma(<2 x bfloa
 ; CHECK-FTZ:       {
 ; CHECK-FTZ-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-FTZ-NEXT:    .reg .b32 %r<20>;
-; CHECK-FTZ-NEXT:    .reg .f32 %f<11>;
+; CHECK-FTZ-NEXT:    .reg .b32 %f<11>;
 ; CHECK-FTZ-EMPTY:
 ; CHECK-FTZ-NEXT:  // %bb.0:
 ; CHECK-FTZ-NEXT:    ld.param.b32 %r1, [fma_bf16x2_expanded_no_nans_multiple_uses_of_fma_param_2];
@@ -1012,7 +1012,7 @@ define <2 x bfloat> @fma_bf16x2_expanded_no_nans_multiple_uses_of_fma(<2 x bfloa
 ; CHECK-SM70-NEXT:    .reg .pred %p<9>;
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<11>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<61>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<19>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<19>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.b32 %r1, [fma_bf16x2_expanded_no_nans_multiple_uses_of_fma_param_0];
@@ -1149,7 +1149,7 @@ define <2 x bfloat> @fma_bf16x2_expanded_maxnum_no_nans(<2 x bfloat> %a, <2 x bf
 ; CHECK-SM70-NEXT:    .reg .pred %p<5>;
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<43>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<13>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<13>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.b32 %r1, [fma_bf16x2_expanded_maxnum_no_nans_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll b/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
index eb51d7db81372..73f808f1e06ee 100644
--- a/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
+++ b/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
@@ -137,7 +137,7 @@ define half @fma_f16_maxnum_no_nans(half %a, half %b, half %c) #0 {
 ; CHECK-SM70-LABEL: fma_f16_maxnum_no_nans(
 ; CHECK-SM70:       {
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<6>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<3>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<3>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.b16 %rs1, [fma_f16_maxnum_no_nans_param_0];
@@ -184,7 +184,7 @@ define bfloat @fma_bf16_no_nans(bfloat %a, bfloat %b, bfloat %c) #0 {
 ; CHECK-SM70-NEXT:    .reg .pred %p<3>;
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<3>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<14>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<6>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<6>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.u16 %r1, [fma_bf16_no_nans_param_2];
@@ -239,7 +239,7 @@ define bfloat @fma_bf16_no_nans_multiple_uses_of_fma(bfloat %a, bfloat %b, bfloa
 ; CHECK-FTZ:       {
 ; CHECK-FTZ-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-FTZ-NEXT:    .reg .b32 %r<5>;
-; CHECK-FTZ-NEXT:    .reg .f32 %f<5>;
+; CHECK-FTZ-NEXT:    .reg .b32 %f<5>;
 ; CHECK-FTZ-EMPTY:
 ; CHECK-FTZ-NEXT:  // %bb.0:
 ; CHECK-FTZ-NEXT:    ld.param.b16 %rs1, [fma_bf16_no_nans_multiple_uses_of_fma_param_0];
@@ -264,7 +264,7 @@ define bfloat @fma_bf16_no_nans_multiple_uses_of_fma(bfloat %a, bfloat %b, bfloa
 ; CHECK-SM70-NEXT:    .reg .pred %p<4>;
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<2>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<27>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<9>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<9>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.u16 %r1, [fma_bf16_no_nans_multiple_uses_of_fma_param_2];
@@ -345,7 +345,7 @@ define bfloat @fma_bf16_maxnum_no_nans(bfloat %a, bfloat %b, bfloat %c) #0 {
 ; CHECK-SM70-NEXT:    .reg .pred %p<3>;
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<2>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<20>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<7>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<7>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.u16 %r1, [fma_bf16_maxnum_no_nans_param_2];
@@ -516,7 +516,7 @@ define <2 x half> @fma_f16x2_maxnum_no_nans(<2 x half> %a, <2 x half> %b, <2 x h
 ; CHECK-SM70:       {
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<5>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<6>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<5>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<5>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.b32 %r1, [fma_f16x2_maxnum_no_nans_param_2];
@@ -568,7 +568,7 @@ define <2 x bfloat> @fma_bf16x2_no_nans(<2 x bfloat> %a, <2 x bfloat> %b, <2 x b
 ; CHECK-SM70-NEXT:    .reg .pred %p<5>;
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<11>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<31>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<11>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<11>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.b32 %r1, [fma_bf16x2_no_nans_param_0];
@@ -652,7 +652,7 @@ define <2 x bfloat> @fma_bf16x2_no_nans_multiple_uses_of_fma(<2 x bfloat> %a, <2
 ; CHECK-FTZ:       {
 ; CHECK-FTZ-NEXT:    .reg .b16 %rs<5>;
 ; CHECK-FTZ-NEXT:    .reg .b32 %r<14>;
-; CHECK-FTZ-NEXT:    .reg .f32 %f<9>;
+; CHECK-FTZ-NEXT:    .reg .b32 %f<9>;
 ; CHECK-FTZ-EMPTY:
 ; CHECK-FTZ-NEXT:  // %bb.0:
 ; CHECK-FTZ-NEXT:    ld.param.b32 %r1, [fma_bf16x2_no_nans_multiple_uses_of_fma_param_2];
@@ -687,7 +687,7 @@ define <2 x bfloat> @fma_bf16x2_no_nans_multiple_uses_of_fma(<2 x bfloat> %a, <2
 ; CHECK-SM70-NEXT:    .reg .pred %p<7>;
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<57>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<17>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<17>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.b32 %r1, [fma_bf16x2_no_nans_multiple_uses_of_fma_param_0];
@@ -811,7 +811,7 @@ define <2 x bfloat> @fma_bf16x2_maxnum_no_nans(<2 x bfloat> %a, <2 x bfloat> %b,
 ; CHECK-SM70-NEXT:    .reg .pred %p<5>;
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<43>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<13>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<13>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.b32 %r1, [fma_bf16x2_maxnum_no_nans_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/fma-relu-instruction-flag.ll b/llvm/test/CodeGen/NVPTX/fma-relu-instruction-flag.ll
index a3545f5171425..b94fa5a24b502 100644
--- a/llvm/test/CodeGen/NVPTX/fma-relu-instruction-flag.ll
+++ b/llvm/test/CodeGen/NVPTX/fma-relu-instruction-flag.ll
@@ -147,7 +147,7 @@ define half @fma_f16_expanded_maxnum_no_nans(half %a, half %b, half %c)  {
 ; CHECK-SM70-LABEL: fma_f16_expanded_maxnum_no_nans(
 ; CHECK-SM70:       {
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<6>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<3>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<3>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.b16 %rs1, [fma_f16_expanded_maxnum_no_nans_param_0];
@@ -195,7 +195,7 @@ define bfloat @fma_bf16_expanded_no_nans(bfloat %a, bfloat %b, bfloat %c)  {
 ; CHECK-SM70-NEXT:    .reg .pred %p<3>;
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<3>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<14>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<6>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<6>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.u16 %r1, [fma_bf16_expanded_no_nans_param_2];
@@ -253,7 +253,7 @@ define bfloat @fma_bf16_expanded_no_nans_multiple_uses_of_fma(bfloat %a, bfloat
 ; CHECK-FTZ:       {
 ; CHECK-FTZ-NEXT:    .reg .b16 %rs<9>;
 ; CHECK-FTZ-NEXT:    .reg .b32 %r<7>;
-; CHECK-FTZ-NEXT:    .reg .f32 %f<6>;
+; CHECK-FTZ-NEXT:    .reg .b32 %f<6>;
 ; CHECK-FTZ-EMPTY:
 ; CHECK-FTZ-NEXT:  // %bb.0:
 ; CHECK-FTZ-NEXT:    ld.param.b16 %rs1, [fma_bf16_expanded_no_nans_multiple_uses_of_fma_param_0];
@@ -283,7 +283,7 @@ define bfloat @fma_bf16_expanded_no_nans_multiple_uses_of_fma(bfloat %a, bfloat
 ; CHECK-SM70-NEXT:    .reg .pred %p<5>;
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<4>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<29>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<10>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<10>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.u16 %r1, [fma_bf16_expanded_no_nans_multiple_uses_of_fma_param_2];
@@ -373,7 +373,7 @@ define bfloat @fma_bf16_expanded_maxnum_no_nans(bfloat %a, bfloat %b, bfloat %c)
 ; CHECK-SM70-NEXT:    .reg .pred %p<3>;
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<2>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<20>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<7>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<7>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.u16 %r1, [fma_bf16_expanded_maxnum_no_nans_param_2];
@@ -563,7 +563,7 @@ define <2 x half> @fma_f16x2_expanded_maxnum_no_nans(<2 x half> %a, <2 x half> %
 ; CHECK-SM70:       {
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<5>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<6>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<5>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<5>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.b32 %r1, [fma_f16x2_expanded_maxnum_no_nans_param_2];
@@ -616,7 +616,7 @@ define <2 x bfloat> @fma_bf16x2_expanded_no_nans(<2 x bfloat> %a, <2 x bfloat> %
 ; CHECK-SM70-NEXT:    .reg .pred %p<5>;
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<11>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<31>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<11>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<11>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.b32 %r1, [fma_bf16x2_expanded_no_nans_param_0];
@@ -703,7 +703,7 @@ define <2 x bfloat> @fma_bf16x2_expanded_no_nans_multiple_uses_of_fma(<2 x bfloa
 ; CHECK-FTZ:       {
 ; CHECK-FTZ-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-FTZ-NEXT:    .reg .b32 %r<20>;
-; CHECK-FTZ-NEXT:    .reg .f32 %f<11>;
+; CHECK-FTZ-NEXT:    .reg .b32 %f<11>;
 ; CHECK-FTZ-EMPTY:
 ; CHECK-FTZ-NEXT:  // %bb.0:
 ; CHECK-FTZ-NEXT:    ld.param.b32 %r1, [fma_bf16x2_expanded_no_nans_multiple_uses_of_fma_param_2];
@@ -747,7 +747,7 @@ define <2 x bfloat> @fma_bf16x2_expanded_no_nans_multiple_uses_of_fma(<2 x bfloa
 ; CHECK-SM70-NEXT:    .reg .pred %p<9>;
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<11>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<61>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<19>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<19>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.b32 %r1, [fma_bf16x2_expanded_no_nans_multiple_uses_of_fma_param_0];
@@ -884,7 +884,7 @@ define <2 x bfloat> @fma_bf16x2_expanded_maxnum_no_nans(<2 x bfloat> %a, <2 x bf
 ; CHECK-SM70-NEXT:    .reg .pred %p<5>;
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<43>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<13>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<13>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.b32 %r1, [fma_bf16x2_expanded_maxnum_no_nans_param_0];
@@ -1084,7 +1084,7 @@ define half @fma_f16_maxnum_no_nans(half %a, half %b, half %c)  {
 ; CHECK-SM70-LABEL: fma_f16_maxnum_no_nans(
 ; CHECK-SM70:       {
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<6>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<3>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<3>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.b16 %rs1, [fma_f16_maxnum_no_nans_param_0];
@@ -1131,7 +1131,7 @@ define bfloat @fma_bf16_no_nans(bfloat %a, bfloat %b, bfloat %c)  {
 ; CHECK-SM70-NEXT:    .reg .pred %p<3>;
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<3>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<14>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<6>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<6>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.u16 %r1, [fma_bf16_no_nans_param_2];
@@ -1186,7 +1186,7 @@ define bfloat @fma_bf16_no_nans_multiple_uses_of_fma(bfloat %a, bfloat %b, bfloa
 ; CHECK-FTZ:       {
 ; CHECK-FTZ-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-FTZ-NEXT:    .reg .b32 %r<5>;
-; CHECK-FTZ-NEXT:    .reg .f32 %f<5>;
+; CHECK-FTZ-NEXT:    .reg .b32 %f<5>;
 ; CHECK-FTZ-EMPTY:
 ; CHECK-FTZ-NEXT:  // %bb.0:
 ; CHECK-FTZ-NEXT:    ld.param.b16 %rs1, [fma_bf16_no_nans_multiple_uses_of_fma_param_0];
@@ -1211,7 +1211,7 @@ define bfloat @fma_bf16_no_nans_multiple_uses_of_fma(bfloat %a, bfloat %b, bfloa
 ; CHECK-SM70-NEXT:    .reg .pred %p<4>;
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<2>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<27>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<9>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<9>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.u16 %r1, [fma_bf16_no_nans_multiple_uses_of_fma_param_2];
@@ -1292,7 +1292,7 @@ define bfloat @fma_bf16_maxnum_no_nans(bfloat %a, bfloat %b, bfloat %c)  {
 ; CHECK-SM70-NEXT:    .reg .pred %p<3>;
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<2>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<20>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<7>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<7>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.u16 %r1, [fma_bf16_maxnum_no_nans_param_2];
@@ -1467,7 +1467,7 @@ define <2 x half> @fma_f16x2_maxnum_no_nans(<2 x half> %a, <2 x half> %b, <2 x h
 ; CHECK-SM70:       {
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<5>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<6>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<5>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<5>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.b32 %r1, [fma_f16x2_maxnum_no_nans_param_2];
@@ -1519,7 +1519,7 @@ define <2 x bfloat> @fma_bf16x2_no_nans(<2 x bfloat> %a, <2 x bfloat> %b, <2 x b
 ; CHECK-SM70-NEXT:    .reg .pred %p<5>;
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<11>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<31>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<11>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<11>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.b32 %r1, [fma_bf16x2_no_nans_param_0];
@@ -1603,7 +1603,7 @@ define <2 x bfloat> @fma_bf16x2_no_nans_multiple_uses_of_fma(<2 x bfloat> %a, <2
 ; CHECK-FTZ:       {
 ; CHECK-FTZ-NEXT:    .reg .b16 %rs<5>;
 ; CHECK-FTZ-NEXT:    .reg .b32 %r<14>;
-; CHECK-FTZ-NEXT:    .reg .f32 %f<9>;
+; CHECK-FTZ-NEXT:    .reg .b32 %f<9>;
 ; CHECK-FTZ-EMPTY:
 ; CHECK-FTZ-NEXT:  // %bb.0:
 ; CHECK-FTZ-NEXT:    ld.param.b32 %r1, [fma_bf16x2_no_nans_multiple_uses_of_fma_param_2];
@@ -1638,7 +1638,7 @@ define <2 x bfloat> @fma_bf16x2_no_nans_multiple_uses_of_fma(<2 x bfloat> %a, <2
 ; CHECK-SM70-NEXT:    .reg .pred %p<7>;
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<57>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<17>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<17>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.b32 %r1, [fma_bf16x2_no_nans_multiple_uses_of_fma_param_0];
@@ -1762,7 +1762,7 @@ define <2 x bfloat> @fma_bf16x2_maxnum_no_nans(<2 x bfloat> %a, <2 x bfloat> %b,
 ; CHECK-SM70-NEXT:    .reg .pred %p<5>;
 ; CHECK-SM70-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-SM70-NEXT:    .reg .b32 %r<43>;
-; CHECK-SM70-NEXT:    .reg .f32 %f<13>;
+; CHECK-SM70-NEXT:    .reg .b32 %f<13>;
 ; CHECK-SM70-EMPTY:
 ; CHECK-SM70-NEXT:  // %bb.0:
 ; CHECK-SM70-NEXT:    ld.param.b32 %r1, [fma_bf16x2_maxnum_no_nans_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/fp-contract.ll b/llvm/test/CodeGen/NVPTX/fp-contract.ll
index ea5da6ee57f65..bd559ea157feb 100644
--- a/llvm/test/CodeGen/NVPTX/fp-contract.ll
+++ b/llvm/test/CodeGen/NVPTX/fp-contract.ll
@@ -15,7 +15,7 @@ target triple = "nvptx64-unknown-cuda"
 define float @t0(float %a, float %b, float %c) {
 ; FAST-LABEL: t0(
 ; FAST:       {
-; FAST-NEXT:    .reg .f32 %f<5>;
+; FAST-NEXT:    .reg .b32 %f<5>;
 ; FAST-EMPTY:
 ; FAST-NEXT:  // %bb.0:
 ; FAST-NEXT:    ld.param.f32 %f1, [t0_param_0];
@@ -27,7 +27,7 @@ define float @t0(float %a, float %b, float %c) {
 ;
 ; DEFAULT-LABEL: t0(
 ; DEFAULT:       {
-; DEFAULT-NEXT:    .reg .f32 %f<6>;
+; DEFAULT-NEXT:    .reg .b32 %f<6>;
 ; DEFAULT-EMPTY:
 ; DEFAULT-NEXT:  // %bb.0:
 ; DEFAULT-NEXT:    ld.param.f32 %f1, [t0_param_0];
@@ -47,7 +47,7 @@ define float @t0(float %a, float %b, float %c) {
 define float @t1(float %a, float %b) {
 ; FAST-LABEL: t1(
 ; FAST:       {
-; FAST-NEXT:    .reg .f32 %f<6>;
+; FAST-NEXT:    .reg .b32 %f<6>;
 ; FAST-EMPTY:
 ; FAST-NEXT:  // %bb.0:
 ; FAST-NEXT:    ld.param.f32 %f1, [t1_param_0];
@@ -60,7 +60,7 @@ define float @t1(float %a, float %b) {
 ;
 ; DEFAULT-LABEL: t1(
 ; DEFAULT:       {
-; DEFAULT-NEXT:    .reg .f32 %f<6>;
+; DEFAULT-NEXT:    .reg .b32 %f<6>;
 ; DEFAULT-EMPTY:
 ; DEFAULT-NEXT:  // %bb.0:
 ; DEFAULT-NEXT:    ld.param.f32 %f1, [t1_param_0];
@@ -81,7 +81,7 @@ define float @t1(float %a, float %b) {
 define float @t2(float %a, float %b) {
 ; CHECK-LABEL: t2(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<6>;
+; CHECK-NEXT:    .reg .b32 %f<6>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [t2_param_0];
@@ -101,7 +101,7 @@ define float @t2(float %a, float %b) {
 define float @t3(float %a, float %b, float %c) {
 ; CHECK-LABEL: t3(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [t3_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/frem.ll b/llvm/test/CodeGen/NVPTX/frem.ll
index 73debfbfcdf49..4077f6d1eb21b 100644
--- a/llvm/test/CodeGen/NVPTX/frem.ll
+++ b/llvm/test/CodeGen/NVPTX/frem.ll
@@ -9,7 +9,7 @@ define half @frem_f16(half %a, half %b) {
 ; FAST-LABEL: frem_f16(
 ; FAST:       {
 ; FAST-NEXT:    .reg .b16 %rs<4>;
-; FAST-NEXT:    .reg .f32 %f<7>;
+; FAST-NEXT:    .reg .b32 %f<7>;
 ; FAST-EMPTY:
 ; FAST-NEXT:  // %bb.0:
 ; FAST-NEXT:    ld.param.b16 %rs1, [frem_f16_param_0];
@@ -28,7 +28,7 @@ define half @frem_f16(half %a, half %b) {
 ; NORMAL:       {
 ; NORMAL-NEXT:    .reg .pred %p<2>;
 ; NORMAL-NEXT:    .reg .b16 %rs<4>;
-; NORMAL-NEXT:    .reg .f32 %f<8>;
+; NORMAL-NEXT:    .reg .b32 %f<8>;
 ; NORMAL-EMPTY:
 ; NORMAL-NEXT:  // %bb.0:
 ; NORMAL-NEXT:    ld.param.b16 %rs1, [frem_f16_param_0];
@@ -51,7 +51,7 @@ define half @frem_f16(half %a, half %b) {
 define float @frem_f32(float %a, float %b) {
 ; FAST-LABEL: frem_f32(
 ; FAST:       {
-; FAST-NEXT:    .reg .f32 %f<7>;
+; FAST-NEXT:    .reg .b32 %f<7>;
 ; FAST-EMPTY:
 ; FAST-NEXT:  // %bb.0:
 ; FAST-NEXT:    ld.param.f32 %f1, [frem_f32_param_0];
@@ -66,7 +66,7 @@ define float @frem_f32(float %a, float %b) {
 ; NORMAL-LABEL: frem_f32(
 ; NORMAL:       {
 ; NORMAL-NEXT:    .reg .pred %p<2>;
-; NORMAL-NEXT:    .reg .f32 %f<8>;
+; NORMAL-NEXT:    .reg .b32 %f<8>;
 ; NORMAL-EMPTY:
 ; NORMAL-NEXT:  // %bb.0:
 ; NORMAL-NEXT:    ld.param.f32 %f1, [frem_f32_param_0];
@@ -86,7 +86,7 @@ define float @frem_f32(float %a, float %b) {
 define double @frem_f64(double %a, double %b) {
 ; FAST-LABEL: frem_f64(
 ; FAST:       {
-; FAST-NEXT:    .reg .f64 %fd<7>;
+; FAST-NEXT:    .reg .b64 %fd<7>;
 ; FAST-EMPTY:
 ; FAST-NEXT:  // %bb.0:
 ; FAST-NEXT:    ld.param.f64 %fd1, [frem_f64_param_0];
@@ -101,7 +101,7 @@ define double @frem_f64(double %a, double %b) {
 ; NORMAL-LABEL: frem_f64(
 ; NORMAL:       {
 ; NORMAL-NEXT:    .reg .pred %p<2>;
-; NORMAL-NEXT:    .reg .f64 %fd<8>;
+; NORMAL-NEXT:    .reg .b64 %fd<8>;
 ; NORMAL-EMPTY:
 ; NORMAL-NEXT:  // %bb.0:
 ; NORMAL-NEXT:    ld.param.f64 %fd1, [frem_f64_param_0];
@@ -122,7 +122,7 @@ define half @frem_f16_ninf(half %a, half %b) {
 ; FAST-LABEL: frem_f16_ninf(
 ; FAST:       {
 ; FAST-NEXT:    .reg .b16 %rs<4>;
-; FAST-NEXT:    .reg .f32 %f<7>;
+; FAST-NEXT:    .reg .b32 %f<7>;
 ; FAST-EMPTY:
 ; FAST-NEXT:  // %bb.0:
 ; FAST-NEXT:    ld.param.b16 %rs1, [frem_f16_ninf_param_0];
@@ -140,7 +140,7 @@ define half @frem_f16_ninf(half %a, half %b) {
 ; NORMAL-LABEL: frem_f16_ninf(
 ; NORMAL:       {
 ; NORMAL-NEXT:    .reg .b16 %rs<4>;
-; NORMAL-NEXT:    .reg .f32 %f<7>;
+; NORMAL-NEXT:    .reg .b32 %f<7>;
 ; NORMAL-EMPTY:
 ; NORMAL-NEXT:  // %bb.0:
 ; NORMAL-NEXT:    ld.param.b16 %rs1, [frem_f16_ninf_param_0];
@@ -161,7 +161,7 @@ define half @frem_f16_ninf(half %a, half %b) {
 define float @frem_f32_ninf(float %a, float %b) {
 ; FAST-LABEL: frem_f32_ninf(
 ; FAST:       {
-; FAST-NEXT:    .reg .f32 %f<7>;
+; FAST-NEXT:    .reg .b32 %f<7>;
 ; FAST-EMPTY:
 ; FAST-NEXT:  // %bb.0:
 ; FAST-NEXT:    ld.param.f32 %f1, [frem_f32_ninf_param_0];
@@ -175,7 +175,7 @@ define float @frem_f32_ninf(float %a, float %b) {
 ;
 ; NORMAL-LABEL: frem_f32_ninf(
 ; NORMAL:       {
-; NORMAL-NEXT:    .reg .f32 %f<7>;
+; NORMAL-NEXT:    .reg .b32 %f<7>;
 ; NORMAL-EMPTY:
 ; NORMAL-NEXT:  // %bb.0:
 ; NORMAL-NEXT:    ld.param.f32 %f1, [frem_f32_ninf_param_0];
@@ -193,7 +193,7 @@ define float @frem_f32_ninf(float %a, float %b) {
 define double @frem_f64_ninf(double %a, double %b) {
 ; FAST-LABEL: frem_f64_ninf(
 ; FAST:       {
-; FAST-NEXT:    .reg .f64 %fd<7>;
+; FAST-NEXT:    .reg .b64 %fd<7>;
 ; FAST-EMPTY:
 ; FAST-NEXT:  // %bb.0:
 ; FAST-NEXT:    ld.param.f64 %fd1, [frem_f64_ninf_param_0];
@@ -207,7 +207,7 @@ define double @frem_f64_ninf(double %a, double %b) {
 ;
 ; NORMAL-LABEL: frem_f64_ninf(
 ; NORMAL:       {
-; NORMAL-NEXT:    .reg .f64 %fd<7>;
+; NORMAL-NEXT:    .reg .b64 %fd<7>;
 ; NORMAL-EMPTY:
 ; NORMAL-NEXT:  // %bb.0:
 ; NORMAL-NEXT:    ld.param.f64 %fd1, [frem_f64_ninf_param_0];
@@ -225,7 +225,7 @@ define double @frem_f64_ninf(double %a, double %b) {
 define float @frem_f32_imm1(float %a) {
 ; FAST-LABEL: frem_f32_imm1(
 ; FAST:       {
-; FAST-NEXT:    .reg .f32 %f<5>;
+; FAST-NEXT:    .reg .b32 %f<5>;
 ; FAST-EMPTY:
 ; FAST-NEXT:  // %bb.0:
 ; FAST-NEXT:    ld.param.f32 %f1, [frem_f32_imm1_param_0];
@@ -237,7 +237,7 @@ define float @frem_f32_imm1(float %a) {
 ;
 ; NORMAL-LABEL: frem_f32_imm1(
 ; NORMAL:       {
-; NORMAL-NEXT:    .reg .f32 %f<5>;
+; NORMAL-NEXT:    .reg .b32 %f<5>;
 ; NORMAL-EMPTY:
 ; NORMAL-NEXT:  // %bb.0:
 ; NORMAL-NEXT:    ld.param.f32 %f1, [frem_f32_imm1_param_0];
@@ -253,7 +253,7 @@ define float @frem_f32_imm1(float %a) {
 define float @frem_f32_imm2(float %a) {
 ; FAST-LABEL: frem_f32_imm2(
 ; FAST:       {
-; FAST-NEXT:    .reg .f32 %f<7>;
+; FAST-NEXT:    .reg .b32 %f<7>;
 ; FAST-EMPTY:
 ; FAST-NEXT:  // %bb.0:
 ; FAST-NEXT:    ld.param.f32 %f1, [frem_f32_imm2_param_0];
@@ -268,7 +268,7 @@ define float @frem_f32_imm2(float %a) {
 ; NORMAL-LABEL: frem_f32_imm2(
 ; NORMAL:       {
 ; NORMAL-NEXT:    .reg .pred %p<2>;
-; NORMAL-NEXT:    .reg .f32 %f<8>;
+; NORMAL-NEXT:    .reg .b32 %f<8>;
 ; NORMAL-EMPTY:
 ; NORMAL-NEXT:  // %bb.0:
 ; NORMAL-NEXT:    ld.param.f32 %f1, [frem_f32_imm2_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/i8x4-instructions.ll b/llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
index 1b779dbe5abeb..65edcf2e07159 100644
--- a/llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
@@ -1141,7 +1141,7 @@ define <4 x i8> @test_bitcast_float_to_4xi8(float %a) #0 {
 ; CHECK-LABEL: test_bitcast_float_to_4xi8(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [test_bitcast_float_to_4xi8_param_0];
@@ -1169,7 +1169,7 @@ define float @test_bitcast_4xi8_to_float(<4 x i8> %a) #0 {
 ; CHECK-LABEL: test_bitcast_4xi8_to_float(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u32 %r1, [test_bitcast_4xi8_to_float_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/intrinsics.ll b/llvm/test/CodeGen/NVPTX/intrinsics.ll
index cc6af060d6c0a..01c51bb72d055 100644
--- a/llvm/test/CodeGen/NVPTX/intrinsics.ll
+++ b/llvm/test/CodeGen/NVPTX/intrinsics.ll
@@ -7,7 +7,7 @@
 define float @test_fabsf(float %f) {
 ; CHECK-LABEL: test_fabsf(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [test_fabsf_param_0];
@@ -21,7 +21,7 @@ define float @test_fabsf(float %f) {
 define double @test_fabs(double %d) {
 ; CHECK-LABEL: test_fabs(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f64 %fd1, [test_fabs_param_0];
@@ -35,7 +35,7 @@ define double @test_fabs(double %d) {
 define float @test_nvvm_sqrt(float %a) {
 ; CHECK-LABEL: test_nvvm_sqrt(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [test_nvvm_sqrt_param_0];
@@ -49,7 +49,7 @@ define float @test_nvvm_sqrt(float %a) {
 define float @test_llvm_sqrt(float %a) {
 ; CHECK-LABEL: test_llvm_sqrt(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [test_llvm_sqrt_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/ldg-invariant.ll b/llvm/test/CodeGen/NVPTX/ldg-invariant.ll
index 16a0189e784bd..2fe2d28320f06 100644
--- a/llvm/test/CodeGen/NVPTX/ldg-invariant.ll
+++ b/llvm/test/CodeGen/NVPTX/ldg-invariant.ll
@@ -27,7 +27,7 @@ define half @ld_global_v2f16(ptr addrspace(1) %ptr) {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<4>;
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<4>;
+; CHECK-NEXT:    .reg .b32 %f<4>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -54,7 +54,7 @@ define half @ld_global_v4f16(ptr addrspace(1) %ptr) {
 ; CHECK-LABEL: ld_global_v4f16(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<8>;
-; CHECK-NEXT:    .reg .f32 %f<10>;
+; CHECK-NEXT:    .reg .b32 %f<10>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -92,7 +92,7 @@ define half @ld_global_v8f16(ptr addrspace(1) %ptr) {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b16 %rs<8>;
 ; CHECK-NEXT:    .reg .b32 %r<5>;
-; CHECK-NEXT:    .reg .f32 %f<10>;
+; CHECK-NEXT:    .reg .b32 %f<10>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
diff --git a/llvm/test/CodeGen/NVPTX/ldu-ldg.ll b/llvm/test/CodeGen/NVPTX/ldu-ldg.ll
index 4c5c44a9bf44d..2c1550aa082f0 100644
--- a/llvm/test/CodeGen/NVPTX/ldu-ldg.ll
+++ b/llvm/test/CodeGen/NVPTX/ldu-ldg.ll
@@ -104,7 +104,7 @@ define ptr @test_ldu_p(ptr addrspace(1) %ptr) {
 define float @test_ldu_f32(ptr addrspace(1) %ptr) {
 ; CHECK-LABEL: test_ldu_f32(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -120,7 +120,7 @@ define double @test_ldu_f64(ptr addrspace(1) %ptr) {
 ; CHECK-LABEL: test_ldu_f64(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<2>;
+; CHECK-NEXT:    .reg .b64 %fd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u64 %rd1, [test_ldu_f64_param_0];
@@ -241,7 +241,7 @@ define ptr @test_ldg_p(ptr addrspace(1) %ptr) {
 define float @test_ldg_f32(ptr addrspace(1) %ptr) {
 ; CHECK-LABEL: test_ldg_f32(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -257,7 +257,7 @@ define double @test_ldg_f64(ptr addrspace(1) %ptr) {
 ; CHECK-LABEL: test_ldg_f64(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<2>;
+; CHECK-NEXT:    .reg .b64 %fd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u64 %rd1, [test_ldg_f64_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/load-store-scalars.ll b/llvm/test/CodeGen/NVPTX/load-store-scalars.ll
index ed94cb416f472..cb2e247bd78c1 100644
--- a/llvm/test/CodeGen/NVPTX/load-store-scalars.ll
+++ b/llvm/test/CodeGen/NVPTX/load-store-scalars.ll
@@ -91,7 +91,7 @@ define void @generic_i64(ptr %a) {
 define void @generic_float(ptr %a) {
 ; CHECK-LABEL: generic_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -110,7 +110,7 @@ define void @generic_double(ptr %a) {
 ; CHECK-LABEL: generic_double(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u64 %rd1, [generic_double_param_0];
@@ -200,7 +200,7 @@ define void @generic_volatile_i64(ptr %a) {
 define void @generic_volatile_float(ptr %a) {
 ; CHECK-LABEL: generic_volatile_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -219,7 +219,7 @@ define void @generic_volatile_double(ptr %a) {
 ; CHECK-LABEL: generic_volatile_double(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u64 %rd1, [generic_volatile_double_param_0];
@@ -356,7 +356,7 @@ define void @generic_unordered_sys_i64(ptr %a) {
 define void @generic_unordered_sys_float(ptr %a) {
 ; SM60-LABEL: generic_unordered_sys_float(
 ; SM60:       {
-; SM60-NEXT:    .reg .f32 %f<3>;
+; SM60-NEXT:    .reg .b32 %f<3>;
 ; SM60-NEXT:    .reg .b64 %rd<2>;
 ; SM60-EMPTY:
 ; SM60-NEXT:  // %bb.0:
@@ -368,7 +368,7 @@ define void @generic_unordered_sys_float(ptr %a) {
 ;
 ; SM70-LABEL: generic_unordered_sys_float(
 ; SM70:       {
-; SM70-NEXT:    .reg .f32 %f<3>;
+; SM70-NEXT:    .reg .b32 %f<3>;
 ; SM70-NEXT:    .reg .b64 %rd<2>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
@@ -387,7 +387,7 @@ define void @generic_unordered_sys_double(ptr %a) {
 ; SM60-LABEL: generic_unordered_sys_double(
 ; SM60:       {
 ; SM60-NEXT:    .reg .b64 %rd<2>;
-; SM60-NEXT:    .reg .f64 %fd<3>;
+; SM60-NEXT:    .reg .b64 %fd<3>;
 ; SM60-EMPTY:
 ; SM60-NEXT:  // %bb.0:
 ; SM60-NEXT:    ld.param.u64 %rd1, [generic_unordered_sys_double_param_0];
@@ -399,7 +399,7 @@ define void @generic_unordered_sys_double(ptr %a) {
 ; SM70-LABEL: generic_unordered_sys_double(
 ; SM70:       {
 ; SM70-NEXT:    .reg .b64 %rd<2>;
-; SM70-NEXT:    .reg .f64 %fd<3>;
+; SM70-NEXT:    .reg .b64 %fd<3>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.u64 %rd1, [generic_unordered_sys_double_param_0];
@@ -489,7 +489,7 @@ define void @generic_unordered_volatile_sys_i64(ptr %a) {
 define void @generic_unordered_volatile_sys_float(ptr %a) {
 ; CHECK-LABEL: generic_unordered_volatile_sys_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -508,7 +508,7 @@ define void @generic_unordered_volatile_sys_double(ptr %a) {
 ; CHECK-LABEL: generic_unordered_volatile_sys_double(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u64 %rd1, [generic_unordered_volatile_sys_double_param_0];
@@ -645,7 +645,7 @@ define void @generic_monotonic_sys_i64(ptr %a) {
 define void @generic_monotonic_sys_float(ptr %a) {
 ; SM60-LABEL: generic_monotonic_sys_float(
 ; SM60:       {
-; SM60-NEXT:    .reg .f32 %f<3>;
+; SM60-NEXT:    .reg .b32 %f<3>;
 ; SM60-NEXT:    .reg .b64 %rd<2>;
 ; SM60-EMPTY:
 ; SM60-NEXT:  // %bb.0:
@@ -657,7 +657,7 @@ define void @generic_monotonic_sys_float(ptr %a) {
 ;
 ; SM70-LABEL: generic_monotonic_sys_float(
 ; SM70:       {
-; SM70-NEXT:    .reg .f32 %f<3>;
+; SM70-NEXT:    .reg .b32 %f<3>;
 ; SM70-NEXT:    .reg .b64 %rd<2>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
@@ -676,7 +676,7 @@ define void @generic_monotonic_sys_double(ptr %a) {
 ; SM60-LABEL: generic_monotonic_sys_double(
 ; SM60:       {
 ; SM60-NEXT:    .reg .b64 %rd<2>;
-; SM60-NEXT:    .reg .f64 %fd<3>;
+; SM60-NEXT:    .reg .b64 %fd<3>;
 ; SM60-EMPTY:
 ; SM60-NEXT:  // %bb.0:
 ; SM60-NEXT:    ld.param.u64 %rd1, [generic_monotonic_sys_double_param_0];
@@ -688,7 +688,7 @@ define void @generic_monotonic_sys_double(ptr %a) {
 ; SM70-LABEL: generic_monotonic_sys_double(
 ; SM70:       {
 ; SM70-NEXT:    .reg .b64 %rd<2>;
-; SM70-NEXT:    .reg .f64 %fd<3>;
+; SM70-NEXT:    .reg .b64 %fd<3>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.u64 %rd1, [generic_monotonic_sys_double_param_0];
@@ -778,7 +778,7 @@ define void @generic_monotonic_volatile_sys_i64(ptr %a) {
 define void @generic_monotonic_volatile_sys_float(ptr %a) {
 ; CHECK-LABEL: generic_monotonic_volatile_sys_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -797,7 +797,7 @@ define void @generic_monotonic_volatile_sys_double(ptr %a) {
 ; CHECK-LABEL: generic_monotonic_volatile_sys_double(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u64 %rd1, [generic_monotonic_volatile_sys_double_param_0];
@@ -889,7 +889,7 @@ define void @global_i64(ptr addrspace(1) %a) {
 define void @global_float(ptr addrspace(1) %a) {
 ; CHECK-LABEL: global_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -908,7 +908,7 @@ define void @global_double(ptr addrspace(1) %a) {
 ; CHECK-LABEL: global_double(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u64 %rd1, [global_double_param_0];
@@ -998,7 +998,7 @@ define void @global_volatile_i64(ptr addrspace(1) %a) {
 define void @global_volatile_float(ptr addrspace(1) %a) {
 ; CHECK-LABEL: global_volatile_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -1017,7 +1017,7 @@ define void @global_volatile_double(ptr addrspace(1) %a) {
 ; CHECK-LABEL: global_volatile_double(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u64 %rd1, [global_volatile_double_param_0];
@@ -1154,7 +1154,7 @@ define void @global_unordered_sys_i64(ptr addrspace(1) %a) {
 define void @global_unordered_sys_float(ptr addrspace(1) %a) {
 ; SM60-LABEL: global_unordered_sys_float(
 ; SM60:       {
-; SM60-NEXT:    .reg .f32 %f<3>;
+; SM60-NEXT:    .reg .b32 %f<3>;
 ; SM60-NEXT:    .reg .b64 %rd<2>;
 ; SM60-EMPTY:
 ; SM60-NEXT:  // %bb.0:
@@ -1166,7 +1166,7 @@ define void @global_unordered_sys_float(ptr addrspace(1) %a) {
 ;
 ; SM70-LABEL: global_unordered_sys_float(
 ; SM70:       {
-; SM70-NEXT:    .reg .f32 %f<3>;
+; SM70-NEXT:    .reg .b32 %f<3>;
 ; SM70-NEXT:    .reg .b64 %rd<2>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
@@ -1185,7 +1185,7 @@ define void @global_unordered_sys_double(ptr addrspace(1) %a) {
 ; SM60-LABEL: global_unordered_sys_double(
 ; SM60:       {
 ; SM60-NEXT:    .reg .b64 %rd<2>;
-; SM60-NEXT:    .reg .f64 %fd<3>;
+; SM60-NEXT:    .reg .b64 %fd<3>;
 ; SM60-EMPTY:
 ; SM60-NEXT:  // %bb.0:
 ; SM60-NEXT:    ld.param.u64 %rd1, [global_unordered_sys_double_param_0];
@@ -1197,7 +1197,7 @@ define void @global_unordered_sys_double(ptr addrspace(1) %a) {
 ; SM70-LABEL: global_unordered_sys_double(
 ; SM70:       {
 ; SM70-NEXT:    .reg .b64 %rd<2>;
-; SM70-NEXT:    .reg .f64 %fd<3>;
+; SM70-NEXT:    .reg .b64 %fd<3>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.u64 %rd1, [global_unordered_sys_double_param_0];
@@ -1334,7 +1334,7 @@ define void @global_unordered_volatile_sys_i64(ptr addrspace(1) %a) {
 define void @global_unordered_volatile_sys_float(ptr addrspace(1) %a) {
 ; SM60-LABEL: global_unordered_volatile_sys_float(
 ; SM60:       {
-; SM60-NEXT:    .reg .f32 %f<3>;
+; SM60-NEXT:    .reg .b32 %f<3>;
 ; SM60-NEXT:    .reg .b64 %rd<2>;
 ; SM60-EMPTY:
 ; SM60-NEXT:  // %bb.0:
@@ -1346,7 +1346,7 @@ define void @global_unordered_volatile_sys_float(ptr addrspace(1) %a) {
 ;
 ; SM70-LABEL: global_unordered_volatile_sys_float(
 ; SM70:       {
-; SM70-NEXT:    .reg .f32 %f<3>;
+; SM70-NEXT:    .reg .b32 %f<3>;
 ; SM70-NEXT:    .reg .b64 %rd<2>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
@@ -1365,7 +1365,7 @@ define void @global_unordered_volatile_sys_double(ptr addrspace(1) %a) {
 ; SM60-LABEL: global_unordered_volatile_sys_double(
 ; SM60:       {
 ; SM60-NEXT:    .reg .b64 %rd<2>;
-; SM60-NEXT:    .reg .f64 %fd<3>;
+; SM60-NEXT:    .reg .b64 %fd<3>;
 ; SM60-EMPTY:
 ; SM60-NEXT:  // %bb.0:
 ; SM60-NEXT:    ld.param.u64 %rd1, [global_unordered_volatile_sys_double_param_0];
@@ -1377,7 +1377,7 @@ define void @global_unordered_volatile_sys_double(ptr addrspace(1) %a) {
 ; SM70-LABEL: global_unordered_volatile_sys_double(
 ; SM70:       {
 ; SM70-NEXT:    .reg .b64 %rd<2>;
-; SM70-NEXT:    .reg .f64 %fd<3>;
+; SM70-NEXT:    .reg .b64 %fd<3>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.u64 %rd1, [global_unordered_volatile_sys_double_param_0];
@@ -1514,7 +1514,7 @@ define void @global_monotonic_sys_i64(ptr addrspace(1) %a) {
 define void @global_monotonic_sys_float(ptr addrspace(1) %a) {
 ; SM60-LABEL: global_monotonic_sys_float(
 ; SM60:       {
-; SM60-NEXT:    .reg .f32 %f<3>;
+; SM60-NEXT:    .reg .b32 %f<3>;
 ; SM60-NEXT:    .reg .b64 %rd<2>;
 ; SM60-EMPTY:
 ; SM60-NEXT:  // %bb.0:
@@ -1526,7 +1526,7 @@ define void @global_monotonic_sys_float(ptr addrspace(1) %a) {
 ;
 ; SM70-LABEL: global_monotonic_sys_float(
 ; SM70:       {
-; SM70-NEXT:    .reg .f32 %f<3>;
+; SM70-NEXT:    .reg .b32 %f<3>;
 ; SM70-NEXT:    .reg .b64 %rd<2>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
@@ -1545,7 +1545,7 @@ define void @global_monotonic_sys_double(ptr addrspace(1) %a) {
 ; SM60-LABEL: global_monotonic_sys_double(
 ; SM60:       {
 ; SM60-NEXT:    .reg .b64 %rd<2>;
-; SM60-NEXT:    .reg .f64 %fd<3>;
+; SM60-NEXT:    .reg .b64 %fd<3>;
 ; SM60-EMPTY:
 ; SM60-NEXT:  // %bb.0:
 ; SM60-NEXT:    ld.param.u64 %rd1, [global_monotonic_sys_double_param_0];
@@ -1557,7 +1557,7 @@ define void @global_monotonic_sys_double(ptr addrspace(1) %a) {
 ; SM70-LABEL: global_monotonic_sys_double(
 ; SM70:       {
 ; SM70-NEXT:    .reg .b64 %rd<2>;
-; SM70-NEXT:    .reg .f64 %fd<3>;
+; SM70-NEXT:    .reg .b64 %fd<3>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.u64 %rd1, [global_monotonic_sys_double_param_0];
@@ -1694,7 +1694,7 @@ define void @global_monotonic_volatile_sys_i64(ptr addrspace(1) %a) {
 define void @global_monotonic_volatile_sys_float(ptr addrspace(1) %a) {
 ; SM60-LABEL: global_monotonic_volatile_sys_float(
 ; SM60:       {
-; SM60-NEXT:    .reg .f32 %f<3>;
+; SM60-NEXT:    .reg .b32 %f<3>;
 ; SM60-NEXT:    .reg .b64 %rd<2>;
 ; SM60-EMPTY:
 ; SM60-NEXT:  // %bb.0:
@@ -1706,7 +1706,7 @@ define void @global_monotonic_volatile_sys_float(ptr addrspace(1) %a) {
 ;
 ; SM70-LABEL: global_monotonic_volatile_sys_float(
 ; SM70:       {
-; SM70-NEXT:    .reg .f32 %f<3>;
+; SM70-NEXT:    .reg .b32 %f<3>;
 ; SM70-NEXT:    .reg .b64 %rd<2>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
@@ -1725,7 +1725,7 @@ define void @global_monotonic_volatile_sys_double(ptr addrspace(1) %a) {
 ; SM60-LABEL: global_monotonic_volatile_sys_double(
 ; SM60:       {
 ; SM60-NEXT:    .reg .b64 %rd<2>;
-; SM60-NEXT:    .reg .f64 %fd<3>;
+; SM60-NEXT:    .reg .b64 %fd<3>;
 ; SM60-EMPTY:
 ; SM60-NEXT:  // %bb.0:
 ; SM60-NEXT:    ld.param.u64 %rd1, [global_monotonic_volatile_sys_double_param_0];
@@ -1737,7 +1737,7 @@ define void @global_monotonic_volatile_sys_double(ptr addrspace(1) %a) {
 ; SM70-LABEL: global_monotonic_volatile_sys_double(
 ; SM70:       {
 ; SM70-NEXT:    .reg .b64 %rd<2>;
-; SM70-NEXT:    .reg .f64 %fd<3>;
+; SM70-NEXT:    .reg .b64 %fd<3>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.u64 %rd1, [global_monotonic_volatile_sys_double_param_0];
@@ -1829,7 +1829,7 @@ define void @shared_i64(ptr addrspace(3) %a) {
 define void @shared_float(ptr addrspace(3) %a) {
 ; CHECK-LABEL: shared_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -1848,7 +1848,7 @@ define void @shared_double(ptr addrspace(3) %a) {
 ; CHECK-LABEL: shared_double(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u64 %rd1, [shared_double_param_0];
@@ -1938,7 +1938,7 @@ define void @shared_volatile_i64(ptr addrspace(3) %a) {
 define void @shared_volatile_float(ptr addrspace(3) %a) {
 ; CHECK-LABEL: shared_volatile_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -1957,7 +1957,7 @@ define void @shared_volatile_double(ptr addrspace(3) %a) {
 ; CHECK-LABEL: shared_volatile_double(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u64 %rd1, [shared_volatile_double_param_0];
@@ -2094,7 +2094,7 @@ define void @shared_unordered_sys_i64(ptr addrspace(3) %a) {
 define void @shared_unordered_sys_float(ptr addrspace(3) %a) {
 ; SM60-LABEL: shared_unordered_sys_float(
 ; SM60:       {
-; SM60-NEXT:    .reg .f32 %f<3>;
+; SM60-NEXT:    .reg .b32 %f<3>;
 ; SM60-NEXT:    .reg .b64 %rd<2>;
 ; SM60-EMPTY:
 ; SM60-NEXT:  // %bb.0:
@@ -2106,7 +2106,7 @@ define void @shared_unordered_sys_float(ptr addrspace(3) %a) {
 ;
 ; SM70-LABEL: shared_unordered_sys_float(
 ; SM70:       {
-; SM70-NEXT:    .reg .f32 %f<3>;
+; SM70-NEXT:    .reg .b32 %f<3>;
 ; SM70-NEXT:    .reg .b64 %rd<2>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
@@ -2125,7 +2125,7 @@ define void @shared_unordered_sys_double(ptr addrspace(3) %a) {
 ; SM60-LABEL: shared_unordered_sys_double(
 ; SM60:       {
 ; SM60-NEXT:    .reg .b64 %rd<2>;
-; SM60-NEXT:    .reg .f64 %fd<3>;
+; SM60-NEXT:    .reg .b64 %fd<3>;
 ; SM60-EMPTY:
 ; SM60-NEXT:  // %bb.0:
 ; SM60-NEXT:    ld.param.u64 %rd1, [shared_unordered_sys_double_param_0];
@@ -2137,7 +2137,7 @@ define void @shared_unordered_sys_double(ptr addrspace(3) %a) {
 ; SM70-LABEL: shared_unordered_sys_double(
 ; SM70:       {
 ; SM70-NEXT:    .reg .b64 %rd<2>;
-; SM70-NEXT:    .reg .f64 %fd<3>;
+; SM70-NEXT:    .reg .b64 %fd<3>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.u64 %rd1, [shared_unordered_sys_double_param_0];
@@ -2227,7 +2227,7 @@ define void @shared_unordered_volatile_sys_i64(ptr addrspace(3) %a) {
 define void @shared_unordered_volatile_sys_float(ptr addrspace(3) %a) {
 ; CHECK-LABEL: shared_unordered_volatile_sys_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -2246,7 +2246,7 @@ define void @shared_unordered_volatile_sys_double(ptr addrspace(3) %a) {
 ; CHECK-LABEL: shared_unordered_volatile_sys_double(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u64 %rd1, [shared_unordered_volatile_sys_double_param_0];
@@ -2383,7 +2383,7 @@ define void @shared_monotonic_sys_i64(ptr addrspace(3) %a) {
 define void @shared_monotonic_sys_float(ptr addrspace(3) %a) {
 ; SM60-LABEL: shared_monotonic_sys_float(
 ; SM60:       {
-; SM60-NEXT:    .reg .f32 %f<3>;
+; SM60-NEXT:    .reg .b32 %f<3>;
 ; SM60-NEXT:    .reg .b64 %rd<2>;
 ; SM60-EMPTY:
 ; SM60-NEXT:  // %bb.0:
@@ -2395,7 +2395,7 @@ define void @shared_monotonic_sys_float(ptr addrspace(3) %a) {
 ;
 ; SM70-LABEL: shared_monotonic_sys_float(
 ; SM70:       {
-; SM70-NEXT:    .reg .f32 %f<3>;
+; SM70-NEXT:    .reg .b32 %f<3>;
 ; SM70-NEXT:    .reg .b64 %rd<2>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
@@ -2414,7 +2414,7 @@ define void @shared_monotonic_sys_double(ptr addrspace(3) %a) {
 ; SM60-LABEL: shared_monotonic_sys_double(
 ; SM60:       {
 ; SM60-NEXT:    .reg .b64 %rd<2>;
-; SM60-NEXT:    .reg .f64 %fd<3>;
+; SM60-NEXT:    .reg .b64 %fd<3>;
 ; SM60-EMPTY:
 ; SM60-NEXT:  // %bb.0:
 ; SM60-NEXT:    ld.param.u64 %rd1, [shared_monotonic_sys_double_param_0];
@@ -2426,7 +2426,7 @@ define void @shared_monotonic_sys_double(ptr addrspace(3) %a) {
 ; SM70-LABEL: shared_monotonic_sys_double(
 ; SM70:       {
 ; SM70-NEXT:    .reg .b64 %rd<2>;
-; SM70-NEXT:    .reg .f64 %fd<3>;
+; SM70-NEXT:    .reg .b64 %fd<3>;
 ; SM70-EMPTY:
 ; SM70-NEXT:  // %bb.0:
 ; SM70-NEXT:    ld.param.u64 %rd1, [shared_monotonic_sys_double_param_0];
@@ -2516,7 +2516,7 @@ define void @shared_monotonic_volatile_sys_i64(ptr addrspace(3) %a) {
 define void @shared_monotonic_volatile_sys_float(ptr addrspace(3) %a) {
 ; CHECK-LABEL: shared_monotonic_volatile_sys_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -2535,7 +2535,7 @@ define void @shared_monotonic_volatile_sys_double(ptr addrspace(3) %a) {
 ; CHECK-LABEL: shared_monotonic_volatile_sys_double(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u64 %rd1, [shared_monotonic_volatile_sys_double_param_0];
@@ -2627,7 +2627,7 @@ define void @local_i64(ptr addrspace(5) %a) {
 define void @local_float(ptr addrspace(5) %a) {
 ; CHECK-LABEL: local_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -2646,7 +2646,7 @@ define void @local_double(ptr addrspace(5) %a) {
 ; CHECK-LABEL: local_double(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u64 %rd1, [local_double_param_0];
@@ -2736,7 +2736,7 @@ define void @local_volatile_i64(ptr addrspace(5) %a) {
 define void @local_volatile_float(ptr addrspace(5) %a) {
 ; CHECK-LABEL: local_volatile_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -2755,7 +2755,7 @@ define void @local_volatile_double(ptr addrspace(5) %a) {
 ; CHECK-LABEL: local_volatile_double(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u64 %rd1, [local_volatile_double_param_0];
@@ -2845,7 +2845,7 @@ define void @local_unordered_sys_i64(ptr addrspace(5) %a) {
 define void @local_unordered_sys_float(ptr addrspace(5) %a) {
 ; CHECK-LABEL: local_unordered_sys_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -2864,7 +2864,7 @@ define void @local_unordered_sys_double(ptr addrspace(5) %a) {
 ; CHECK-LABEL: local_unordered_sys_double(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u64 %rd1, [local_unordered_sys_double_param_0];
@@ -2954,7 +2954,7 @@ define void @local_unordered_volatile_sys_i64(ptr addrspace(5) %a) {
 define void @local_unordered_volatile_sys_float(ptr addrspace(5) %a) {
 ; CHECK-LABEL: local_unordered_volatile_sys_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -2973,7 +2973,7 @@ define void @local_unordered_volatile_sys_double(ptr addrspace(5) %a) {
 ; CHECK-LABEL: local_unordered_volatile_sys_double(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u64 %rd1, [local_unordered_volatile_sys_double_param_0];
@@ -3063,7 +3063,7 @@ define void @local_monotonic_sys_i64(ptr addrspace(5) %a) {
 define void @local_monotonic_sys_float(ptr addrspace(5) %a) {
 ; CHECK-LABEL: local_monotonic_sys_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -3082,7 +3082,7 @@ define void @local_monotonic_sys_double(ptr addrspace(5) %a) {
 ; CHECK-LABEL: local_monotonic_sys_double(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u64 %rd1, [local_monotonic_sys_double_param_0];
@@ -3172,7 +3172,7 @@ define void @local_monotonic_volatile_sys_i64(ptr addrspace(5) %a) {
 define void @local_monotonic_volatile_sys_float(ptr addrspace(5) %a) {
 ; CHECK-LABEL: local_monotonic_volatile_sys_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -3191,7 +3191,7 @@ define void @local_monotonic_volatile_sys_double(ptr addrspace(5) %a) {
 ; CHECK-LABEL: local_monotonic_volatile_sys_double(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u64 %rd1, [local_monotonic_volatile_sys_double_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/load-store-vectors.ll b/llvm/test/CodeGen/NVPTX/load-store-vectors.ll
index ba397dca68f1b..3215fce964005 100644
--- a/llvm/test/CodeGen/NVPTX/load-store-vectors.ll
+++ b/llvm/test/CodeGen/NVPTX/load-store-vectors.ll
@@ -371,7 +371,7 @@ define void @generic_2xi64(ptr %a) {
 define void @generic_2xfloat(ptr %a) {
 ; CHECK-LABEL: generic_2xfloat(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -390,7 +390,7 @@ define void @generic_2xfloat(ptr %a) {
 define void @generic_4xfloat(ptr %a) {
 ; CHECK-LABEL: generic_4xfloat(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<9>;
+; CHECK-NEXT:    .reg .b32 %f<9>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -412,7 +412,7 @@ define void @generic_2xdouble(ptr %a) {
 ; CHECK-LABEL: generic_2xdouble(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<5>;
+; CHECK-NEXT:    .reg .b64 %fd<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u64 %rd1, [generic_2xdouble_param_0];
@@ -792,7 +792,7 @@ define void @generic_volatile_2xi64(ptr %a) {
 define void @generic_volatile_2xfloat(ptr %a) {
 ; CHECK-LABEL: generic_volatile_2xfloat(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -811,7 +811,7 @@ define void @generic_volatile_2xfloat(ptr %a) {
 define void @generic_volatile_4xfloat(ptr %a) {
 ; CHECK-LABEL: generic_volatile_4xfloat(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<9>;
+; CHECK-NEXT:    .reg .b32 %f<9>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -833,7 +833,7 @@ define void @generic_volatile_2xdouble(ptr %a) {
 ; CHECK-LABEL: generic_volatile_2xdouble(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<5>;
+; CHECK-NEXT:    .reg .b64 %fd<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u64 %rd1, [generic_volatile_2xdouble_param_0];
@@ -1196,7 +1196,7 @@ define void @global_2xi64(ptr addrspace(1) %a) {
 define void @global_2xfloat(ptr addrspace(1) %a) {
 ; CHECK-LABEL: global_2xfloat(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -1215,7 +1215,7 @@ define void @global_2xfloat(ptr addrspace(1) %a) {
 define void @global_4xfloat(ptr addrspace(1) %a) {
 ; CHECK-LABEL: global_4xfloat(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<9>;
+; CHECK-NEXT:    .reg .b32 %f<9>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -1237,7 +1237,7 @@ define void @global_2xdouble(ptr addrspace(1) %a) {
 ; CHECK-LABEL: global_2xdouble(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<5>;
+; CHECK-NEXT:    .reg .b64 %fd<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u64 %rd1, [global_2xdouble_param_0];
@@ -1598,7 +1598,7 @@ define void @global_volatile_2xi64(ptr addrspace(1) %a) {
 define void @global_volatile_2xfloat(ptr addrspace(1) %a) {
 ; CHECK-LABEL: global_volatile_2xfloat(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -1617,7 +1617,7 @@ define void @global_volatile_2xfloat(ptr addrspace(1) %a) {
 define void @global_volatile_4xfloat(ptr addrspace(1) %a) {
 ; CHECK-LABEL: global_volatile_4xfloat(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<9>;
+; CHECK-NEXT:    .reg .b32 %f<9>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -1639,7 +1639,7 @@ define void @global_volatile_2xdouble(ptr addrspace(1) %a) {
 ; CHECK-LABEL: global_volatile_2xdouble(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<5>;
+; CHECK-NEXT:    .reg .b64 %fd<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u64 %rd1, [global_volatile_2xdouble_param_0];
@@ -2002,7 +2002,7 @@ define void @shared_2xi64(ptr addrspace(3) %a) {
 define void @shared_2xfloat(ptr addrspace(3) %a) {
 ; CHECK-LABEL: shared_2xfloat(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -2021,7 +2021,7 @@ define void @shared_2xfloat(ptr addrspace(3) %a) {
 define void @shared_4xfloat(ptr addrspace(3) %a) {
 ; CHECK-LABEL: shared_4xfloat(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<9>;
+; CHECK-NEXT:    .reg .b32 %f<9>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -2043,7 +2043,7 @@ define void @shared_2xdouble(ptr addrspace(3) %a) {
 ; CHECK-LABEL: shared_2xdouble(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<5>;
+; CHECK-NEXT:    .reg .b64 %fd<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u64 %rd1, [shared_2xdouble_param_0];
@@ -2404,7 +2404,7 @@ define void @shared_volatile_2xi64(ptr addrspace(3) %a) {
 define void @shared_volatile_2xfloat(ptr addrspace(3) %a) {
 ; CHECK-LABEL: shared_volatile_2xfloat(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -2423,7 +2423,7 @@ define void @shared_volatile_2xfloat(ptr addrspace(3) %a) {
 define void @shared_volatile_4xfloat(ptr addrspace(3) %a) {
 ; CHECK-LABEL: shared_volatile_4xfloat(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<9>;
+; CHECK-NEXT:    .reg .b32 %f<9>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -2445,7 +2445,7 @@ define void @shared_volatile_2xdouble(ptr addrspace(3) %a) {
 ; CHECK-LABEL: shared_volatile_2xdouble(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<5>;
+; CHECK-NEXT:    .reg .b64 %fd<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u64 %rd1, [shared_volatile_2xdouble_param_0];
@@ -2808,7 +2808,7 @@ define void @local_2xi64(ptr addrspace(5) %a) {
 define void @local_2xfloat(ptr addrspace(5) %a) {
 ; CHECK-LABEL: local_2xfloat(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -2827,7 +2827,7 @@ define void @local_2xfloat(ptr addrspace(5) %a) {
 define void @local_4xfloat(ptr addrspace(5) %a) {
 ; CHECK-LABEL: local_4xfloat(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<9>;
+; CHECK-NEXT:    .reg .b32 %f<9>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -2849,7 +2849,7 @@ define void @local_2xdouble(ptr addrspace(5) %a) {
 ; CHECK-LABEL: local_2xdouble(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<5>;
+; CHECK-NEXT:    .reg .b64 %fd<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u64 %rd1, [local_2xdouble_param_0];
@@ -3210,7 +3210,7 @@ define void @local_volatile_2xi64(ptr addrspace(5) %a) {
 define void @local_volatile_2xfloat(ptr addrspace(5) %a) {
 ; CHECK-LABEL: local_volatile_2xfloat(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -3229,7 +3229,7 @@ define void @local_volatile_2xfloat(ptr addrspace(5) %a) {
 define void @local_volatile_4xfloat(ptr addrspace(5) %a) {
 ; CHECK-LABEL: local_volatile_4xfloat(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<9>;
+; CHECK-NEXT:    .reg .b32 %f<9>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -3251,7 +3251,7 @@ define void @local_volatile_2xdouble(ptr addrspace(5) %a) {
 ; CHECK-LABEL: local_volatile_2xdouble(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<5>;
+; CHECK-NEXT:    .reg .b64 %fd<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u64 %rd1, [local_volatile_2xdouble_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/math-intrins.ll b/llvm/test/CodeGen/NVPTX/math-intrins.ll
index 189f3421cd03a..a6d01c16c0ab8 100644
--- a/llvm/test/CodeGen/NVPTX/math-intrins.ll
+++ b/llvm/test/CodeGen/NVPTX/math-intrins.ll
@@ -50,7 +50,7 @@ declare double @llvm.fma.f64(double, double, double) #0
 define float @ceil_float(float %a) {
 ; CHECK-LABEL: ceil_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [ceil_float_param_0];
@@ -64,7 +64,7 @@ define float @ceil_float(float %a) {
 define float @ceil_float_ftz(float %a) #1 {
 ; CHECK-LABEL: ceil_float_ftz(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [ceil_float_ftz_param_0];
@@ -78,7 +78,7 @@ define float @ceil_float_ftz(float %a) #1 {
 define double @ceil_double(double %a) {
 ; CHECK-LABEL: ceil_double(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f64 %fd1, [ceil_double_param_0];
@@ -94,7 +94,7 @@ define double @ceil_double(double %a) {
 define float @floor_float(float %a) {
 ; CHECK-LABEL: floor_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [floor_float_param_0];
@@ -108,7 +108,7 @@ define float @floor_float(float %a) {
 define float @floor_float_ftz(float %a) #1 {
 ; CHECK-LABEL: floor_float_ftz(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [floor_float_ftz_param_0];
@@ -122,7 +122,7 @@ define float @floor_float_ftz(float %a) #1 {
 define double @floor_double(double %a) {
 ; CHECK-LABEL: floor_double(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f64 %fd1, [floor_double_param_0];
@@ -141,7 +141,7 @@ define float @round_float(float %a) {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .pred %p<3>;
 ; CHECK-NEXT:    .reg .b32 %r<4>;
-; CHECK-NEXT:    .reg .f32 %f<9>;
+; CHECK-NEXT:    .reg .b32 %f<9>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [round_float_param_0];
@@ -169,7 +169,7 @@ define float @round_float_ftz(float %a) #1 {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .pred %p<3>;
 ; CHECK-NEXT:    .reg .b32 %r<4>;
-; CHECK-NEXT:    .reg .f32 %f<9>;
+; CHECK-NEXT:    .reg .b32 %f<9>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [round_float_ftz_param_0];
@@ -196,7 +196,7 @@ define double @round_double(double %a) {
 ; CHECK-LABEL: round_double(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .pred %p<3>;
-; CHECK-NEXT:    .reg .f64 %fd<8>;
+; CHECK-NEXT:    .reg .b64 %fd<8>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f64 %fd1, [round_double_param_0];
@@ -219,7 +219,7 @@ define double @round_double(double %a) {
 define float @nearbyint_float(float %a) {
 ; CHECK-LABEL: nearbyint_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [nearbyint_float_param_0];
@@ -233,7 +233,7 @@ define float @nearbyint_float(float %a) {
 define float @nearbyint_float_ftz(float %a) #1 {
 ; CHECK-LABEL: nearbyint_float_ftz(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [nearbyint_float_ftz_param_0];
@@ -247,7 +247,7 @@ define float @nearbyint_float_ftz(float %a) #1 {
 define double @nearbyint_double(double %a) {
 ; CHECK-LABEL: nearbyint_double(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f64 %fd1, [nearbyint_double_param_0];
@@ -263,7 +263,7 @@ define double @nearbyint_double(double %a) {
 define float @rint_float(float %a) {
 ; CHECK-LABEL: rint_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [rint_float_param_0];
@@ -277,7 +277,7 @@ define float @rint_float(float %a) {
 define float @rint_float_ftz(float %a) #1 {
 ; CHECK-LABEL: rint_float_ftz(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [rint_float_ftz_param_0];
@@ -291,7 +291,7 @@ define float @rint_float_ftz(float %a) #1 {
 define double @rint_double(double %a) {
 ; CHECK-LABEL: rint_double(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f64 %fd1, [rint_double_param_0];
@@ -307,7 +307,7 @@ define double @rint_double(double %a) {
 define float @roundeven_float(float %a) {
 ; CHECK-LABEL: roundeven_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [roundeven_float_param_0];
@@ -321,7 +321,7 @@ define float @roundeven_float(float %a) {
 define float @roundeven_float_ftz(float %a) #1 {
 ; CHECK-LABEL: roundeven_float_ftz(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [roundeven_float_ftz_param_0];
@@ -335,7 +335,7 @@ define float @roundeven_float_ftz(float %a) #1 {
 define double @roundeven_double(double %a) {
 ; CHECK-LABEL: roundeven_double(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f64 %fd1, [roundeven_double_param_0];
@@ -351,7 +351,7 @@ define double @roundeven_double(double %a) {
 define float @trunc_float(float %a) {
 ; CHECK-LABEL: trunc_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [trunc_float_param_0];
@@ -365,7 +365,7 @@ define float @trunc_float(float %a) {
 define float @trunc_float_ftz(float %a) #1 {
 ; CHECK-LABEL: trunc_float_ftz(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [trunc_float_ftz_param_0];
@@ -379,7 +379,7 @@ define float @trunc_float_ftz(float %a) #1 {
 define double @trunc_double(double %a) {
 ; CHECK-LABEL: trunc_double(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f64 %fd1, [trunc_double_param_0];
@@ -395,7 +395,7 @@ define double @trunc_double(double %a) {
 define float @abs_float(float %a) {
 ; CHECK-LABEL: abs_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [abs_float_param_0];
@@ -409,7 +409,7 @@ define float @abs_float(float %a) {
 define float @abs_float_ftz(float %a) #1 {
 ; CHECK-LABEL: abs_float_ftz(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [abs_float_ftz_param_0];
@@ -423,7 +423,7 @@ define float @abs_float_ftz(float %a) #1 {
 define double @abs_double(double %a) {
 ; CHECK-LABEL: abs_double(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f64 %fd<3>;
+; CHECK-NEXT:    .reg .b64 %fd<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f64 %fd1, [abs_double_param_0];
@@ -440,7 +440,7 @@ define half @minnum_half(half %a, half %b) {
 ; CHECK-NOF16-LABEL: minnum_half(
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<4>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<4>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<4>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b16 %rs1, [minnum_half_param_0];
@@ -466,7 +466,7 @@ define half @minnum_half(half %a, half %b) {
 ; CHECK-SM80-NOF16-LABEL: minnum_half(
 ; CHECK-SM80-NOF16:       {
 ; CHECK-SM80-NOF16-NEXT:    .reg .b16 %rs<4>;
-; CHECK-SM80-NOF16-NEXT:    .reg .f32 %f<4>;
+; CHECK-SM80-NOF16-NEXT:    .reg .b32 %f<4>;
 ; CHECK-SM80-NOF16-EMPTY:
 ; CHECK-SM80-NOF16-NEXT:  // %bb.0:
 ; CHECK-SM80-NOF16-NEXT:    ld.param.b16 %rs1, [minnum_half_param_0];
@@ -484,7 +484,7 @@ define half @minnum_half(half %a, half %b) {
 define float @minnum_float(float %a, float %b) {
 ; CHECK-LABEL: minnum_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<4>;
+; CHECK-NEXT:    .reg .b32 %f<4>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [minnum_float_param_0];
@@ -499,7 +499,7 @@ define float @minnum_float(float %a, float %b) {
 define float @minnum_imm1(float %a) {
 ; CHECK-LABEL: minnum_imm1(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [minnum_imm1_param_0];
@@ -513,7 +513,7 @@ define float @minnum_imm1(float %a) {
 define float @minnum_imm2(float %a) {
 ; CHECK-LABEL: minnum_imm2(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [minnum_imm2_param_0];
@@ -527,7 +527,7 @@ define float @minnum_imm2(float %a) {
 define float @minnum_float_ftz(float %a, float %b) #1 {
 ; CHECK-LABEL: minnum_float_ftz(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<4>;
+; CHECK-NEXT:    .reg .b32 %f<4>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [minnum_float_ftz_param_0];
@@ -542,7 +542,7 @@ define float @minnum_float_ftz(float %a, float %b) #1 {
 define double @minnum_double(double %a, double %b) {
 ; CHECK-LABEL: minnum_double(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f64 %fd<4>;
+; CHECK-NEXT:    .reg .b64 %fd<4>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f64 %fd1, [minnum_double_param_0];
@@ -559,7 +559,7 @@ define <2 x half> @minnum_v2half(<2 x half> %a, <2 x half> %b) {
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<4>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<7>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<7>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r1, [minnum_v2half_param_0];
@@ -593,7 +593,7 @@ define <2 x half> @minnum_v2half(<2 x half> %a, <2 x half> %b) {
 ; CHECK-SM80-NOF16:       {
 ; CHECK-SM80-NOF16-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-SM80-NOF16-NEXT:    .reg .b32 %r<4>;
-; CHECK-SM80-NOF16-NEXT:    .reg .f32 %f<7>;
+; CHECK-SM80-NOF16-NEXT:    .reg .b32 %f<7>;
 ; CHECK-SM80-NOF16-EMPTY:
 ; CHECK-SM80-NOF16-NEXT:  // %bb.0:
 ; CHECK-SM80-NOF16-NEXT:    ld.param.b32 %r1, [minnum_v2half_param_0];
@@ -622,7 +622,7 @@ define half @minimum_half(half %a, half %b) {
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .pred %p<6>;
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<8>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<4>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<4>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b16 %rs1, [minimum_half_param_0];
@@ -658,7 +658,7 @@ define half @minimum_half(half %a, half %b) {
 ; CHECK-SM80-NOF16:       {
 ; CHECK-SM80-NOF16-NEXT:    .reg .pred %p<6>;
 ; CHECK-SM80-NOF16-NEXT:    .reg .b16 %rs<8>;
-; CHECK-SM80-NOF16-NEXT:    .reg .f32 %f<4>;
+; CHECK-SM80-NOF16-NEXT:    .reg .b32 %f<4>;
 ; CHECK-SM80-NOF16-EMPTY:
 ; CHECK-SM80-NOF16-NEXT:  // %bb.0:
 ; CHECK-SM80-NOF16-NEXT:    ld.param.b16 %rs1, [minimum_half_param_0];
@@ -687,7 +687,7 @@ define float @minimum_float(float %a, float %b) {
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .pred %p<5>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<8>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<8>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.f32 %f1, [minimum_float_param_0];
@@ -708,7 +708,7 @@ define float @minimum_float(float %a, float %b) {
 ;
 ; CHECK-F16-LABEL: minimum_float(
 ; CHECK-F16:       {
-; CHECK-F16-NEXT:    .reg .f32 %f<4>;
+; CHECK-F16-NEXT:    .reg .b32 %f<4>;
 ; CHECK-F16-EMPTY:
 ; CHECK-F16-NEXT:  // %bb.0:
 ; CHECK-F16-NEXT:    ld.param.f32 %f1, [minimum_float_param_0];
@@ -719,7 +719,7 @@ define float @minimum_float(float %a, float %b) {
 ;
 ; CHECK-SM80-NOF16-LABEL: minimum_float(
 ; CHECK-SM80-NOF16:       {
-; CHECK-SM80-NOF16-NEXT:    .reg .f32 %f<4>;
+; CHECK-SM80-NOF16-NEXT:    .reg .b32 %f<4>;
 ; CHECK-SM80-NOF16-EMPTY:
 ; CHECK-SM80-NOF16-NEXT:  // %bb.0:
 ; CHECK-SM80-NOF16-NEXT:    ld.param.f32 %f1, [minimum_float_param_0];
@@ -736,7 +736,7 @@ define float @minimum_imm1(float %a) {
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .pred %p<4>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<2>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<6>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<6>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.f32 %f1, [minimum_imm1_param_0];
@@ -753,7 +753,7 @@ define float @minimum_imm1(float %a) {
 ;
 ; CHECK-F16-LABEL: minimum_imm1(
 ; CHECK-F16:       {
-; CHECK-F16-NEXT:    .reg .f32 %f<3>;
+; CHECK-F16-NEXT:    .reg .b32 %f<3>;
 ; CHECK-F16-EMPTY:
 ; CHECK-F16-NEXT:  // %bb.0:
 ; CHECK-F16-NEXT:    ld.param.f32 %f1, [minimum_imm1_param_0];
@@ -763,7 +763,7 @@ define float @minimum_imm1(float %a) {
 ;
 ; CHECK-SM80-NOF16-LABEL: minimum_imm1(
 ; CHECK-SM80-NOF16:       {
-; CHECK-SM80-NOF16-NEXT:    .reg .f32 %f<3>;
+; CHECK-SM80-NOF16-NEXT:    .reg .b32 %f<3>;
 ; CHECK-SM80-NOF16-EMPTY:
 ; CHECK-SM80-NOF16-NEXT:  // %bb.0:
 ; CHECK-SM80-NOF16-NEXT:    ld.param.f32 %f1, [minimum_imm1_param_0];
@@ -779,7 +779,7 @@ define float @minimum_imm2(float %a) {
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .pred %p<4>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<2>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<6>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<6>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.f32 %f1, [minimum_imm2_param_0];
@@ -796,7 +796,7 @@ define float @minimum_imm2(float %a) {
 ;
 ; CHECK-F16-LABEL: minimum_imm2(
 ; CHECK-F16:       {
-; CHECK-F16-NEXT:    .reg .f32 %f<3>;
+; CHECK-F16-NEXT:    .reg .b32 %f<3>;
 ; CHECK-F16-EMPTY:
 ; CHECK-F16-NEXT:  // %bb.0:
 ; CHECK-F16-NEXT:    ld.param.f32 %f1, [minimum_imm2_param_0];
@@ -806,7 +806,7 @@ define float @minimum_imm2(float %a) {
 ;
 ; CHECK-SM80-NOF16-LABEL: minimum_imm2(
 ; CHECK-SM80-NOF16:       {
-; CHECK-SM80-NOF16-NEXT:    .reg .f32 %f<3>;
+; CHECK-SM80-NOF16-NEXT:    .reg .b32 %f<3>;
 ; CHECK-SM80-NOF16-EMPTY:
 ; CHECK-SM80-NOF16-NEXT:  // %bb.0:
 ; CHECK-SM80-NOF16-NEXT:    ld.param.f32 %f1, [minimum_imm2_param_0];
@@ -822,7 +822,7 @@ define float @minimum_float_ftz(float %a, float %b) #1 {
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .pred %p<5>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<8>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<8>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.f32 %f1, [minimum_float_ftz_param_0];
@@ -843,7 +843,7 @@ define float @minimum_float_ftz(float %a, float %b) #1 {
 ;
 ; CHECK-F16-LABEL: minimum_float_ftz(
 ; CHECK-F16:       {
-; CHECK-F16-NEXT:    .reg .f32 %f<4>;
+; CHECK-F16-NEXT:    .reg .b32 %f<4>;
 ; CHECK-F16-EMPTY:
 ; CHECK-F16-NEXT:  // %bb.0:
 ; CHECK-F16-NEXT:    ld.param.f32 %f1, [minimum_float_ftz_param_0];
@@ -854,7 +854,7 @@ define float @minimum_float_ftz(float %a, float %b) #1 {
 ;
 ; CHECK-SM80-NOF16-LABEL: minimum_float_ftz(
 ; CHECK-SM80-NOF16:       {
-; CHECK-SM80-NOF16-NEXT:    .reg .f32 %f<4>;
+; CHECK-SM80-NOF16-NEXT:    .reg .b32 %f<4>;
 ; CHECK-SM80-NOF16-EMPTY:
 ; CHECK-SM80-NOF16-NEXT:  // %bb.0:
 ; CHECK-SM80-NOF16-NEXT:    ld.param.f32 %f1, [minimum_float_ftz_param_0];
@@ -871,7 +871,7 @@ define double @minimum_double(double %a, double %b) {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .pred %p<5>;
 ; CHECK-NEXT:    .reg .b64 %rd<3>;
-; CHECK-NEXT:    .reg .f64 %fd<8>;
+; CHECK-NEXT:    .reg .b64 %fd<8>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f64 %fd1, [minimum_double_param_0];
@@ -899,7 +899,7 @@ define <2 x half> @minimum_v2half(<2 x half> %a, <2 x half> %b) {
 ; CHECK-NOF16-NEXT:    .reg .pred %p<11>;
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<15>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<4>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<7>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<7>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r1, [minimum_v2half_param_0];
@@ -952,7 +952,7 @@ define <2 x half> @minimum_v2half(<2 x half> %a, <2 x half> %b) {
 ; CHECK-SM80-NOF16-NEXT:    .reg .pred %p<11>;
 ; CHECK-SM80-NOF16-NEXT:    .reg .b16 %rs<15>;
 ; CHECK-SM80-NOF16-NEXT:    .reg .b32 %r<4>;
-; CHECK-SM80-NOF16-NEXT:    .reg .f32 %f<7>;
+; CHECK-SM80-NOF16-NEXT:    .reg .b32 %f<7>;
 ; CHECK-SM80-NOF16-EMPTY:
 ; CHECK-SM80-NOF16-NEXT:  // %bb.0:
 ; CHECK-SM80-NOF16-NEXT:    ld.param.b32 %r1, [minimum_v2half_param_0];
@@ -998,7 +998,7 @@ define half @maxnum_half(half %a, half %b) {
 ; CHECK-NOF16-LABEL: maxnum_half(
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<4>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<4>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<4>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b16 %rs1, [maxnum_half_param_0];
@@ -1024,7 +1024,7 @@ define half @maxnum_half(half %a, half %b) {
 ; CHECK-SM80-NOF16-LABEL: maxnum_half(
 ; CHECK-SM80-NOF16:       {
 ; CHECK-SM80-NOF16-NEXT:    .reg .b16 %rs<4>;
-; CHECK-SM80-NOF16-NEXT:    .reg .f32 %f<4>;
+; CHECK-SM80-NOF16-NEXT:    .reg .b32 %f<4>;
 ; CHECK-SM80-NOF16-EMPTY:
 ; CHECK-SM80-NOF16-NEXT:  // %bb.0:
 ; CHECK-SM80-NOF16-NEXT:    ld.param.b16 %rs1, [maxnum_half_param_0];
@@ -1042,7 +1042,7 @@ define half @maxnum_half(half %a, half %b) {
 define float @maxnum_imm1(float %a) {
 ; CHECK-LABEL: maxnum_imm1(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [maxnum_imm1_param_0];
@@ -1056,7 +1056,7 @@ define float @maxnum_imm1(float %a) {
 define float @maxnum_imm2(float %a) {
 ; CHECK-LABEL: maxnum_imm2(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [maxnum_imm2_param_0];
@@ -1070,7 +1070,7 @@ define float @maxnum_imm2(float %a) {
 define float @maxnum_float(float %a, float %b) {
 ; CHECK-LABEL: maxnum_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<4>;
+; CHECK-NEXT:    .reg .b32 %f<4>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [maxnum_float_param_0];
@@ -1085,7 +1085,7 @@ define float @maxnum_float(float %a, float %b) {
 define float @maxnum_float_ftz(float %a, float %b) #1 {
 ; CHECK-LABEL: maxnum_float_ftz(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<4>;
+; CHECK-NEXT:    .reg .b32 %f<4>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [maxnum_float_ftz_param_0];
@@ -1100,7 +1100,7 @@ define float @maxnum_float_ftz(float %a, float %b) #1 {
 define double @maxnum_double(double %a, double %b) {
 ; CHECK-LABEL: maxnum_double(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f64 %fd<4>;
+; CHECK-NEXT:    .reg .b64 %fd<4>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f64 %fd1, [maxnum_double_param_0];
@@ -1117,7 +1117,7 @@ define <2 x half> @maxnum_v2half(<2 x half> %a, <2 x half> %b) {
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<4>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<7>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<7>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r1, [maxnum_v2half_param_0];
@@ -1151,7 +1151,7 @@ define <2 x half> @maxnum_v2half(<2 x half> %a, <2 x half> %b) {
 ; CHECK-SM80-NOF16:       {
 ; CHECK-SM80-NOF16-NEXT:    .reg .b16 %rs<7>;
 ; CHECK-SM80-NOF16-NEXT:    .reg .b32 %r<4>;
-; CHECK-SM80-NOF16-NEXT:    .reg .f32 %f<7>;
+; CHECK-SM80-NOF16-NEXT:    .reg .b32 %f<7>;
 ; CHECK-SM80-NOF16-EMPTY:
 ; CHECK-SM80-NOF16-NEXT:  // %bb.0:
 ; CHECK-SM80-NOF16-NEXT:    ld.param.b32 %r1, [maxnum_v2half_param_0];
@@ -1180,7 +1180,7 @@ define half @maximum_half(half %a, half %b) {
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .pred %p<6>;
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<8>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<4>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<4>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b16 %rs1, [maximum_half_param_0];
@@ -1216,7 +1216,7 @@ define half @maximum_half(half %a, half %b) {
 ; CHECK-SM80-NOF16:       {
 ; CHECK-SM80-NOF16-NEXT:    .reg .pred %p<6>;
 ; CHECK-SM80-NOF16-NEXT:    .reg .b16 %rs<8>;
-; CHECK-SM80-NOF16-NEXT:    .reg .f32 %f<4>;
+; CHECK-SM80-NOF16-NEXT:    .reg .b32 %f<4>;
 ; CHECK-SM80-NOF16-EMPTY:
 ; CHECK-SM80-NOF16-NEXT:  // %bb.0:
 ; CHECK-SM80-NOF16-NEXT:    ld.param.b16 %rs1, [maximum_half_param_0];
@@ -1244,7 +1244,7 @@ define float @maximum_imm1(float %a) {
 ; CHECK-NOF16-LABEL: maximum_imm1(
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .pred %p<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<5>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.f32 %f1, [maximum_imm1_param_0];
@@ -1258,7 +1258,7 @@ define float @maximum_imm1(float %a) {
 ;
 ; CHECK-F16-LABEL: maximum_imm1(
 ; CHECK-F16:       {
-; CHECK-F16-NEXT:    .reg .f32 %f<3>;
+; CHECK-F16-NEXT:    .reg .b32 %f<3>;
 ; CHECK-F16-EMPTY:
 ; CHECK-F16-NEXT:  // %bb.0:
 ; CHECK-F16-NEXT:    ld.param.f32 %f1, [maximum_imm1_param_0];
@@ -1268,7 +1268,7 @@ define float @maximum_imm1(float %a) {
 ;
 ; CHECK-SM80-NOF16-LABEL: maximum_imm1(
 ; CHECK-SM80-NOF16:       {
-; CHECK-SM80-NOF16-NEXT:    .reg .f32 %f<3>;
+; CHECK-SM80-NOF16-NEXT:    .reg .b32 %f<3>;
 ; CHECK-SM80-NOF16-EMPTY:
 ; CHECK-SM80-NOF16-NEXT:  // %bb.0:
 ; CHECK-SM80-NOF16-NEXT:    ld.param.f32 %f1, [maximum_imm1_param_0];
@@ -1283,7 +1283,7 @@ define float @maximum_imm2(float %a) {
 ; CHECK-NOF16-LABEL: maximum_imm2(
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .pred %p<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<5>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.f32 %f1, [maximum_imm2_param_0];
@@ -1297,7 +1297,7 @@ define float @maximum_imm2(float %a) {
 ;
 ; CHECK-F16-LABEL: maximum_imm2(
 ; CHECK-F16:       {
-; CHECK-F16-NEXT:    .reg .f32 %f<3>;
+; CHECK-F16-NEXT:    .reg .b32 %f<3>;
 ; CHECK-F16-EMPTY:
 ; CHECK-F16-NEXT:  // %bb.0:
 ; CHECK-F16-NEXT:    ld.param.f32 %f1, [maximum_imm2_param_0];
@@ -1307,7 +1307,7 @@ define float @maximum_imm2(float %a) {
 ;
 ; CHECK-SM80-NOF16-LABEL: maximum_imm2(
 ; CHECK-SM80-NOF16:       {
-; CHECK-SM80-NOF16-NEXT:    .reg .f32 %f<3>;
+; CHECK-SM80-NOF16-NEXT:    .reg .b32 %f<3>;
 ; CHECK-SM80-NOF16-EMPTY:
 ; CHECK-SM80-NOF16-NEXT:  // %bb.0:
 ; CHECK-SM80-NOF16-NEXT:    ld.param.f32 %f1, [maximum_imm2_param_0];
@@ -1323,7 +1323,7 @@ define float @maximum_float(float %a, float %b) {
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .pred %p<5>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<8>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<8>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.f32 %f1, [maximum_float_param_0];
@@ -1344,7 +1344,7 @@ define float @maximum_float(float %a, float %b) {
 ;
 ; CHECK-F16-LABEL: maximum_float(
 ; CHECK-F16:       {
-; CHECK-F16-NEXT:    .reg .f32 %f<4>;
+; CHECK-F16-NEXT:    .reg .b32 %f<4>;
 ; CHECK-F16-EMPTY:
 ; CHECK-F16-NEXT:  // %bb.0:
 ; CHECK-F16-NEXT:    ld.param.f32 %f1, [maximum_float_param_0];
@@ -1355,7 +1355,7 @@ define float @maximum_float(float %a, float %b) {
 ;
 ; CHECK-SM80-NOF16-LABEL: maximum_float(
 ; CHECK-SM80-NOF16:       {
-; CHECK-SM80-NOF16-NEXT:    .reg .f32 %f<4>;
+; CHECK-SM80-NOF16-NEXT:    .reg .b32 %f<4>;
 ; CHECK-SM80-NOF16-EMPTY:
 ; CHECK-SM80-NOF16-NEXT:  // %bb.0:
 ; CHECK-SM80-NOF16-NEXT:    ld.param.f32 %f1, [maximum_float_param_0];
@@ -1372,7 +1372,7 @@ define float @maximum_float_ftz(float %a, float %b) #1 {
 ; CHECK-NOF16:       {
 ; CHECK-NOF16-NEXT:    .reg .pred %p<5>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<3>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<8>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<8>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.f32 %f1, [maximum_float_ftz_param_0];
@@ -1393,7 +1393,7 @@ define float @maximum_float_ftz(float %a, float %b) #1 {
 ;
 ; CHECK-F16-LABEL: maximum_float_ftz(
 ; CHECK-F16:       {
-; CHECK-F16-NEXT:    .reg .f32 %f<4>;
+; CHECK-F16-NEXT:    .reg .b32 %f<4>;
 ; CHECK-F16-EMPTY:
 ; CHECK-F16-NEXT:  // %bb.0:
 ; CHECK-F16-NEXT:    ld.param.f32 %f1, [maximum_float_ftz_param_0];
@@ -1404,7 +1404,7 @@ define float @maximum_float_ftz(float %a, float %b) #1 {
 ;
 ; CHECK-SM80-NOF16-LABEL: maximum_float_ftz(
 ; CHECK-SM80-NOF16:       {
-; CHECK-SM80-NOF16-NEXT:    .reg .f32 %f<4>;
+; CHECK-SM80-NOF16-NEXT:    .reg .b32 %f<4>;
 ; CHECK-SM80-NOF16-EMPTY:
 ; CHECK-SM80-NOF16-NEXT:  // %bb.0:
 ; CHECK-SM80-NOF16-NEXT:    ld.param.f32 %f1, [maximum_float_ftz_param_0];
@@ -1421,7 +1421,7 @@ define double @maximum_double(double %a, double %b) {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .pred %p<5>;
 ; CHECK-NEXT:    .reg .b64 %rd<3>;
-; CHECK-NEXT:    .reg .f64 %fd<8>;
+; CHECK-NEXT:    .reg .b64 %fd<8>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f64 %fd1, [maximum_double_param_0];
@@ -1449,7 +1449,7 @@ define <2 x half> @maximum_v2half(<2 x half> %a, <2 x half> %b) {
 ; CHECK-NOF16-NEXT:    .reg .pred %p<11>;
 ; CHECK-NOF16-NEXT:    .reg .b16 %rs<15>;
 ; CHECK-NOF16-NEXT:    .reg .b32 %r<4>;
-; CHECK-NOF16-NEXT:    .reg .f32 %f<7>;
+; CHECK-NOF16-NEXT:    .reg .b32 %f<7>;
 ; CHECK-NOF16-EMPTY:
 ; CHECK-NOF16-NEXT:  // %bb.0:
 ; CHECK-NOF16-NEXT:    ld.param.b32 %r1, [maximum_v2half_param_0];
@@ -1502,7 +1502,7 @@ define <2 x half> @maximum_v2half(<2 x half> %a, <2 x half> %b) {
 ; CHECK-SM80-NOF16-NEXT:    .reg .pred %p<11>;
 ; CHECK-SM80-NOF16-NEXT:    .reg .b16 %rs<15>;
 ; CHECK-SM80-NOF16-NEXT:    .reg .b32 %r<4>;
-; CHECK-SM80-NOF16-NEXT:    .reg .f32 %f<7>;
+; CHECK-SM80-NOF16-NEXT:    .reg .b32 %f<7>;
 ; CHECK-SM80-NOF16-EMPTY:
 ; CHECK-SM80-NOF16-NEXT:  // %bb.0:
 ; CHECK-SM80-NOF16-NEXT:    ld.param.b32 %r1, [maximum_v2half_param_0];
@@ -1547,7 +1547,7 @@ define <2 x half> @maximum_v2half(<2 x half> %a, <2 x half> %b) {
 define float @fma_float(float %a, float %b, float %c) {
 ; CHECK-LABEL: fma_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [fma_float_param_0];
@@ -1563,7 +1563,7 @@ define float @fma_float(float %a, float %b, float %c) {
 define float @fma_float_ftz(float %a, float %b, float %c) #1 {
 ; CHECK-LABEL: fma_float_ftz(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [fma_float_ftz_param_0];
@@ -1579,7 +1579,7 @@ define float @fma_float_ftz(float %a, float %b, float %c) #1 {
 define double @fma_double(double %a, double %b, double %c) {
 ; CHECK-LABEL: fma_double(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f64 %fd<5>;
+; CHECK-NEXT:    .reg .b64 %fd<5>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f64 %fd1, [fma_double_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/misched_func_call.ll b/llvm/test/CodeGen/NVPTX/misched_func_call.ll
index e0d0197c6ead5..fb4c653b709f3 100644
--- a/llvm/test/CodeGen/NVPTX/misched_func_call.ll
+++ b/llvm/test/CodeGen/NVPTX/misched_func_call.ll
@@ -9,7 +9,7 @@ define ptx_kernel void @wombat(i32 %arg, i32 %arg1, i32 %arg2) {
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<11>;
 ; CHECK-NEXT:    .reg .b64 %rd<2>;
-; CHECK-NEXT:    .reg .f64 %fd<6>;
+; CHECK-NEXT:    .reg .b64 %fd<6>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0: // %bb
 ; CHECK-NEXT:    ld.param.u32 %r4, [wombat_param_2];
diff --git a/llvm/test/CodeGen/NVPTX/param-add.ll b/llvm/test/CodeGen/NVPTX/param-add.ll
index afabc113541c2..c8daf3b5760f5 100644
--- a/llvm/test/CodeGen/NVPTX/param-add.ll
+++ b/llvm/test/CodeGen/NVPTX/param-add.ll
@@ -15,7 +15,7 @@ define i32 @test(%struct.1float alignstack(32) %data) {
 ; CHECK-LABEL: test(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<18>;
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.u8 %r1, [test_param_0+1];
diff --git a/llvm/test/CodeGen/NVPTX/rcp-opt.ll b/llvm/test/CodeGen/NVPTX/rcp-opt.ll
index 31fd8ebae1a81..0b020b7751387 100644
--- a/llvm/test/CodeGen/NVPTX/rcp-opt.ll
+++ b/llvm/test/CodeGen/NVPTX/rcp-opt.ll
@@ -9,7 +9,7 @@ target triple = "nvptx64-nvidia-cuda"
 define double @test1(double %in) {
 ; CHECK-LABEL: test1(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f64 %fd<4>;
+; CHECK-NEXT:    .reg .b64 %fd<4>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f64 %fd1, [test1_param_0];
@@ -27,7 +27,7 @@ define double @test1(double %in) {
 define double @test2(double %in) {
 ; CHECK-LABEL: test2(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f64 %fd<4>;
+; CHECK-NEXT:    .reg .b64 %fd<4>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f64 %fd1, [test2_param_0];
@@ -44,7 +44,7 @@ define double @test2(double %in) {
 define double @test3(double %in) {
 ; CHECK-LABEL: test3(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f64 %fd<4>;
+; CHECK-NEXT:    .reg .b64 %fd<4>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f64 %fd1, [test3_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll b/llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
index 2a12e9b364a54..020a61a1675aa 100644
--- a/llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
+++ b/llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
@@ -115,7 +115,7 @@ define half @reduce_fadd_half_reassoc_nonpow2(<7 x half> %in) {
 define float @reduce_fadd_float(<8 x float> %in) {
 ; CHECK-LABEL: reduce_fadd_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<17>;
+; CHECK-NEXT:    .reg .b32 %f<17>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.v4.f32 {%f5, %f6, %f7, %f8}, [reduce_fadd_float_param_0+16];
@@ -137,7 +137,7 @@ define float @reduce_fadd_float(<8 x float> %in) {
 define float @reduce_fadd_float_reassoc(<8 x float> %in) {
 ; CHECK-LABEL: reduce_fadd_float_reassoc(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<17>;
+; CHECK-NEXT:    .reg .b32 %f<17>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.v4.f32 {%f5, %f6, %f7, %f8}, [reduce_fadd_float_reassoc_param_0+16];
@@ -159,7 +159,7 @@ define float @reduce_fadd_float_reassoc(<8 x float> %in) {
 define float @reduce_fadd_float_reassoc_nonpow2(<7 x float> %in) {
 ; CHECK-LABEL: reduce_fadd_float_reassoc_nonpow2(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<15>;
+; CHECK-NEXT:    .reg .b32 %f<15>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f7, [reduce_fadd_float_reassoc_nonpow2_param_0+24];
@@ -274,7 +274,7 @@ define half @reduce_fmul_half_reassoc_nonpow2(<7 x half> %in) {
 define float @reduce_fmul_float(<8 x float> %in) {
 ; CHECK-LABEL: reduce_fmul_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<16>;
+; CHECK-NEXT:    .reg .b32 %f<16>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.v4.f32 {%f5, %f6, %f7, %f8}, [reduce_fmul_float_param_0+16];
@@ -295,7 +295,7 @@ define float @reduce_fmul_float(<8 x float> %in) {
 define float @reduce_fmul_float_reassoc(<8 x float> %in) {
 ; CHECK-LABEL: reduce_fmul_float_reassoc(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<16>;
+; CHECK-NEXT:    .reg .b32 %f<16>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.v4.f32 {%f5, %f6, %f7, %f8}, [reduce_fmul_float_reassoc_param_0+16];
@@ -316,7 +316,7 @@ define float @reduce_fmul_float_reassoc(<8 x float> %in) {
 define float @reduce_fmul_float_reassoc_nonpow2(<7 x float> %in) {
 ; CHECK-LABEL: reduce_fmul_float_reassoc_nonpow2(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<14>;
+; CHECK-NEXT:    .reg .b32 %f<14>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f7, [reduce_fmul_float_reassoc_nonpow2_param_0+24];
@@ -404,7 +404,7 @@ define float @reduce_fmax_float(<8 x float> %in) {
 ;
 ; CHECK-LABEL: reduce_fmax_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<16>;
+; CHECK-NEXT:    .reg .b32 %f<16>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.v4.f32 {%f5, %f6, %f7, %f8}, [reduce_fmax_float_param_0+16];
@@ -426,7 +426,7 @@ define float @reduce_fmax_float_reassoc(<8 x float> %in) {
 ;
 ; CHECK-LABEL: reduce_fmax_float_reassoc(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<16>;
+; CHECK-NEXT:    .reg .b32 %f<16>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.v4.f32 {%f5, %f6, %f7, %f8}, [reduce_fmax_float_reassoc_param_0+16];
@@ -448,7 +448,7 @@ define float @reduce_fmax_float_reassoc_nonpow2(<7 x float> %in) {
 ;
 ; CHECK-LABEL: reduce_fmax_float_reassoc_nonpow2(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<14>;
+; CHECK-NEXT:    .reg .b32 %f<14>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f7, [reduce_fmax_float_reassoc_nonpow2_param_0+24];
@@ -536,7 +536,7 @@ define float @reduce_fmin_float(<8 x float> %in) {
 ;
 ; CHECK-LABEL: reduce_fmin_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<16>;
+; CHECK-NEXT:    .reg .b32 %f<16>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.v4.f32 {%f5, %f6, %f7, %f8}, [reduce_fmin_float_param_0+16];
@@ -558,7 +558,7 @@ define float @reduce_fmin_float_reassoc(<8 x float> %in) {
 ;
 ; CHECK-LABEL: reduce_fmin_float_reassoc(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<16>;
+; CHECK-NEXT:    .reg .b32 %f<16>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.v4.f32 {%f5, %f6, %f7, %f8}, [reduce_fmin_float_reassoc_param_0+16];
@@ -580,7 +580,7 @@ define float @reduce_fmin_float_reassoc_nonpow2(<7 x float> %in) {
 ;
 ; CHECK-LABEL: reduce_fmin_float_reassoc_nonpow2(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<14>;
+; CHECK-NEXT:    .reg .b32 %f<14>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f7, [reduce_fmin_float_reassoc_nonpow2_param_0+24];
@@ -668,7 +668,7 @@ define float @reduce_fmaximum_float(<8 x float> %in) {
 ;
 ; CHECK-LABEL: reduce_fmaximum_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<16>;
+; CHECK-NEXT:    .reg .b32 %f<16>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.v4.f32 {%f5, %f6, %f7, %f8}, [reduce_fmaximum_float_param_0+16];
@@ -690,7 +690,7 @@ define float @reduce_fmaximum_float_reassoc(<8 x float> %in) {
 ;
 ; CHECK-LABEL: reduce_fmaximum_float_reassoc(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<16>;
+; CHECK-NEXT:    .reg .b32 %f<16>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.v4.f32 {%f5, %f6, %f7, %f8}, [reduce_fmaximum_float_reassoc_param_0+16];
@@ -712,7 +712,7 @@ define float @reduce_fmaximum_float_reassoc_nonpow2(<7 x float> %in) {
 ;
 ; CHECK-LABEL: reduce_fmaximum_float_reassoc_nonpow2(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<14>;
+; CHECK-NEXT:    .reg .b32 %f<14>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f7, [reduce_fmaximum_float_reassoc_nonpow2_param_0+24];
@@ -800,7 +800,7 @@ define float @reduce_fminimum_float(<8 x float> %in) {
 ;
 ; CHECK-LABEL: reduce_fminimum_float(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<16>;
+; CHECK-NEXT:    .reg .b32 %f<16>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.v4.f32 {%f5, %f6, %f7, %f8}, [reduce_fminimum_float_param_0+16];
@@ -822,7 +822,7 @@ define float @reduce_fminimum_float_reassoc(<8 x float> %in) {
 ;
 ; CHECK-LABEL: reduce_fminimum_float_reassoc(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<16>;
+; CHECK-NEXT:    .reg .b32 %f<16>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.v4.f32 {%f5, %f6, %f7, %f8}, [reduce_fminimum_float_reassoc_param_0+16];
@@ -844,7 +844,7 @@ define float @reduce_fminimum_float_reassoc_nonpow2(<7 x float> %in) {
 ;
 ; CHECK-LABEL: reduce_fminimum_float_reassoc_nonpow2(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<14>;
+; CHECK-NEXT:    .reg .b32 %f<14>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f7, [reduce_fminimum_float_reassoc_nonpow2_param_0+24];
diff --git a/llvm/test/CodeGen/NVPTX/redux-sync-f32.ll b/llvm/test/CodeGen/NVPTX/redux-sync-f32.ll
index af113e75fd143..ed785298f5900 100644
--- a/llvm/test/CodeGen/NVPTX/redux-sync-f32.ll
+++ b/llvm/test/CodeGen/NVPTX/redux-sync-f32.ll
@@ -7,7 +7,7 @@ define float @redux_sync_fmin(float %src, i32 %mask) {
 ; CHECK-LABEL: redux_sync_fmin(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [redux_sync_fmin_param_0];
@@ -24,7 +24,7 @@ define float @redux_sync_fmin_abs(float %src, i32 %mask) {
 ; CHECK-LABEL: redux_sync_fmin_abs(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [redux_sync_fmin_abs_param_0];
@@ -41,7 +41,7 @@ define float @redux_sync_fmin_NaN(float %src, i32 %mask) {
 ; CHECK-LABEL: redux_sync_fmin_NaN(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [redux_sync_fmin_NaN_param_0];
@@ -58,7 +58,7 @@ define float @redux_sync_fmin_abs_NaN(float %src, i32 %mask) {
 ; CHECK-LABEL: redux_sync_fmin_abs_NaN(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [redux_sync_fmin_abs_NaN_param_0];
@@ -75,7 +75,7 @@ define float @redux_sync_fmax(float %src, i32 %mask) {
 ; CHECK-LABEL: redux_sync_fmax(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [redux_sync_fmax_param_0];
@@ -92,7 +92,7 @@ define float @redux_sync_fmax_abs(float %src, i32 %mask) {
 ; CHECK-LABEL: redux_sync_fmax_abs(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [redux_sync_fmax_abs_param_0];
@@ -109,7 +109,7 @@ define float @redux_sync_fmax_NaN(float %src, i32 %mask) {
 ; CHECK-LABEL: redux_sync_fmax_NaN(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [redux_sync_fmax_NaN_param_0];
@@ -126,7 +126,7 @@ define float @redux_sync_fmax_abs_NaN(float %src, i32 %mask) {
 ; CHECK-LABEL: redux_sync_fmax_abs_NaN(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [redux_sync_fmax_abs_NaN_param_0];
diff --git a/llvm/test/CodeGen/NVPTX/reg-types.ll b/llvm/test/CodeGen/NVPTX/reg-types.ll
index cf2433ad75a97..7b4ebcae8a67c 100644
--- a/llvm/test/CodeGen/NVPTX/reg-types.ll
+++ b/llvm/test/CodeGen/NVPTX/reg-types.ll
@@ -25,9 +25,9 @@ entry:
   %u64 = alloca i64, align 8
 ; CHECK-DAG: .reg .b64 %rd<
   %f32 = alloca float, align 4
-; CHECK-DAG: .reg .f32 %f<
+; CHECK-DAG: .reg .b32 %f<
   %f64 = alloca double, align 8
-; CHECK-DAG: .reg .f64 %fd<
+; CHECK-DAG: .reg .b64 %fd<
 
 ; Verify that we use correct register types.
   store i8 1, ptr %s8, align 1
diff --git a/llvm/test/CodeGen/NVPTX/st-param-imm.ll b/llvm/test/CodeGen/NVPTX/st-param-imm.ll
index ab1447607ab65..0e67e52d52dab 100644
--- a/llvm/test/CodeGen/NVPTX/st-param-imm.ll
+++ b/llvm/test/CodeGen/NVPTX/st-param-imm.ll
@@ -403,7 +403,7 @@ define void @st_param_v2_f32_ii(float %val) {
 define void @st_param_v2_f32_ir(float %val) {
 ; CHECK-LABEL: st_param_v2_f32_ir(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [st_param_v2_f32_ir_param_0];
@@ -425,7 +425,7 @@ define void @st_param_v2_f32_ir(float %val) {
 define void @st_param_v2_f32_ri(float %val) {
 ; CHECK-LABEL: st_param_v2_f32_ri(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [st_param_v2_f32_ri_param_0];
@@ -467,7 +467,7 @@ define void @st_param_v2_f64_ii(double %val) {
 define void @st_param_v2_f64_ir(double %val) {
 ; CHECK-LABEL: st_param_v2_f64_ir(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f64 %fd<2>;
+; CHECK-NEXT:    .reg .b64 %fd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f64 %fd1, [st_param_v2_f64_ir_param_0];
@@ -489,7 +489,7 @@ define void @st_param_v2_f64_ir(double %val) {
 define void @st_param_v2_f64_ri(double %val) {
 ; CHECK-LABEL: st_param_v2_f64_ri(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f64 %fd<2>;
+; CHECK-NEXT:    .reg .b64 %fd<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f64 %fd1, [st_param_v2_f64_ri_param_0];
@@ -1648,7 +1648,7 @@ define void @st_param_v4_f32_iiii() {
 define void @st_param_v4_f32_irrr(float %b, float %c, float %d) {
 ; CHECK-LABEL: st_param_v4_f32_irrr(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<4>;
+; CHECK-NEXT:    .reg .b32 %f<4>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [st_param_v4_f32_irrr_param_0];
@@ -1674,7 +1674,7 @@ define void @st_param_v4_f32_irrr(float %b, float %c, float %d) {
 define void @st_param_v4_f32_rirr(float %a, float %c, float %d) {
 ; CHECK-LABEL: st_param_v4_f32_rirr(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<4>;
+; CHECK-NEXT:    .reg .b32 %f<4>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [st_param_v4_f32_rirr_param_0];
@@ -1700,7 +1700,7 @@ define void @st_param_v4_f32_rirr(float %a, float %c, float %d) {
 define void @st_param_v4_f32_rrir(float %a, float %b, float %d) {
 ; CHECK-LABEL: st_param_v4_f32_rrir(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<4>;
+; CHECK-NEXT:    .reg .b32 %f<4>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [st_param_v4_f32_rrir_param_0];
@@ -1726,7 +1726,7 @@ define void @st_param_v4_f32_rrir(float %a, float %b, float %d) {
 define void @st_param_v4_f32_rrri(float %a, float %b, float %c) {
 ; CHECK-LABEL: st_param_v4_f32_rrri(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<4>;
+; CHECK-NEXT:    .reg .b32 %f<4>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [st_param_v4_f32_rrri_param_0];
@@ -1752,7 +1752,7 @@ define void @st_param_v4_f32_rrri(float %a, float %b, float %c) {
 define void @st_param_v4_f32_iirr(float %c, float %d) {
 ; CHECK-LABEL: st_param_v4_f32_iirr(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [st_param_v4_f32_iirr_param_0];
@@ -1777,7 +1777,7 @@ define void @st_param_v4_f32_iirr(float %c, float %d) {
 define void @st_param_v4_f32_irir(float %b, float %d) {
 ; CHECK-LABEL: st_param_v4_f32_irir(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [st_param_v4_f32_irir_param_0];
@@ -1802,7 +1802,7 @@ define void @st_param_v4_f32_irir(float %b, float %d) {
 define void @st_param_v4_f32_irri(float %b, float %c) {
 ; CHECK-LABEL: st_param_v4_f32_irri(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [st_param_v4_f32_irri_param_0];
@@ -1827,7 +1827,7 @@ define void @st_param_v4_f32_irri(float %b, float %c) {
 define void @st_param_v4_f32_riir(float %a, float %d) {
 ; CHECK-LABEL: st_param_v4_f32_riir(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [st_param_v4_f32_riir_param_0];
@@ -1852,7 +1852,7 @@ define void @st_param_v4_f32_riir(float %a, float %d) {
 define void @st_param_v4_f32_riri(float %a, float %c) {
 ; CHECK-LABEL: st_param_v4_f32_riri(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [st_param_v4_f32_riri_param_0];
@@ -1877,7 +1877,7 @@ define void @st_param_v4_f32_riri(float %a, float %c) {
 define void @st_param_v4_f32_rrii(float %a, float %b) {
 ; CHECK-LABEL: st_param_v4_f32_rrii(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<3>;
+; CHECK-NEXT:    .reg .b32 %f<3>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [st_param_v4_f32_rrii_param_0];
@@ -1902,7 +1902,7 @@ define void @st_param_v4_f32_rrii(float %a, float %b) {
 define void @st_param_v4_f32_iiir(float %d) {
 ; CHECK-LABEL: st_param_v4_f32_iiir(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [st_param_v4_f32_iiir_param_0];
@@ -1926,7 +1926,7 @@ define void @st_param_v4_f32_iiir(float %d) {
 define void @st_param_v4_f32_iiri(float %c) {
 ; CHECK-LABEL: st_param_v4_f32_iiri(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [st_param_v4_f32_iiri_param_0];
@@ -1950,7 +1950,7 @@ define void @st_param_v4_f32_iiri(float %c) {
 define void @st_param_v4_f32_irii(float %b) {
 ; CHECK-LABEL: st_param_v4_f32_irii(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [st_param_v4_f32_irii_param_0];
@@ -1974,7 +1974,7 @@ define void @st_param_v4_f32_irii(float %b) {
 define void @st_param_v4_f32_riii(float %a) {
 ; CHECK-LABEL: st_param_v4_f32_riii(
 ; CHECK:       {
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
 ; CHECK-NEXT:    ld.param.f32 %f1, [st_param_v4_f32_riii_param_0];
@@ -2000,3 +2000,27 @@ declare void @call_v4_i8(%struct.char4 alignstack(4))
 declare void @call_v4_i16(%struct.short4 alignstack(8))
 declare void @call_v4_i32(%struct.int4 alignstack(16))
 declare void @call_v4_f32(%struct.float4 alignstack(16))
+
+define void @st_param_bfloat() {
+; CHECK-LABEL: st_param_bfloat(
+; CHECK: {
+; CHECK-NEXT:	.reg .b16 	%rs<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT:// %bb.0:
+; CHECK-NEXT:	mov.b16 	%rs1, 0x4100;
+; CHECK-NEXT:	{ // callseq 83, 0
+; CHECK-NEXT:	.param .align 2 .b8 param0[2];
+; CHECK-NEXT:	st.param.b16 	[param0], %rs1;
+; CHECK-NEXT:	call.uni
+; CHECK-NEXT:	call_bfloat,
+; CHECK-NEXT:	(
+; CHECK-NEXT:	param0
+; CHECK-NEXT:	);
+; CHECK-NEXT:	} // callseq 83
+; CHECK-NEXT:	ret;
+  %five = bitcast i16 16640 to bfloat
+  call void @call_bfloat(bfloat %five)
+  ret void
+}
+
+declare void @call_bfloat(bfloat)
diff --git a/llvm/test/CodeGen/NVPTX/surf-read-cuda.ll b/llvm/test/CodeGen/NVPTX/surf-read-cuda.ll
index 7a7904a2f0425..3afff3245fbf6 100644
--- a/llvm/test/CodeGen/NVPTX/surf-read-cuda.ll
+++ b/llvm/test/CodeGen/NVPTX/surf-read-cuda.ll
@@ -14,7 +14,7 @@ define ptx_kernel void @foo(i64 %img, ptr %red, i32 %idx) {
 ; CHECK-LABEL: foo(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<3>;
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-NEXT:    .reg .b64 %rd<4>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -38,7 +38,7 @@ define ptx_kernel void @bar(ptr %red, i32 %idx) {
 ; CHECK-LABEL: bar(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<3>;
-; CHECK-NEXT:    .reg .f32 %f<2>;
+; CHECK-NEXT:    .reg .b32 %f<2>;
 ; CHECK-NEXT:    .reg .b64 %rd<4>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
diff --git a/llvm/test/CodeGen/NVPTX/tex-read-cuda.ll b/llvm/test/CodeGen/NVPTX/tex-read-cuda.ll
index 61837bde82ece..4e4e3f3aaec62 100644
--- a/llvm/test/CodeGen/NVPTX/tex-read-cuda.ll
+++ b/llvm/test/CodeGen/NVPTX/tex-read-cuda.ll
@@ -14,7 +14,7 @@ define ptx_kernel void @foo(i64 %img, ptr %red, i32 %idx) {
 ; CHECK-LABEL: foo(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NEXT:    .reg .b64 %rd<4>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -38,7 +38,7 @@ define ptx_kernel void @bar(ptr %red, i32 %idx) {
 ; CHECK-LABEL: bar(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<5>;
+; CHECK-NEXT:    .reg .b32 %f<5>;
 ; CHECK-NEXT:    .reg .b64 %rd<4>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
@@ -61,7 +61,7 @@ define ptx_kernel void @baz(ptr %red, i32 %idx) {
 ; CHECK-LABEL: baz(
 ; CHECK:       {
 ; CHECK-NEXT:    .reg .b32 %r<2>;
-; CHECK-NEXT:    .reg .f32 %f<8>;
+; CHECK-NEXT:    .reg .b32 %f<8>;
 ; CHECK-NEXT:    .reg .b64 %rd<4>;
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  // %bb.0:
diff --git a/llvm/test/CodeGen/NVPTX/variadics-backend.ll b/llvm/test/CodeGen/NVPTX/variadics-backend.ll
index 35db4894c1b49..9da361455a656 100644
--- a/llvm/test/CodeGen/NVPTX/variadics-backend.ll
+++ b/llvm/test/CodeGen/NVPTX/variadics-backend.ll
@@ -13,7 +13,7 @@ define dso_local i32 @variadics1(i32 noundef %first, ...) {
 ; CHECK-PTX:       {
 ; CHECK-PTX-NEXT:    .reg .b32 %r<11>;
 ; CHECK-PTX-NEXT:    .reg .b64 %rd<11>;
-; CHECK-PTX-NEXT:    .reg .f64 %fd<7>;
+; CHECK-PTX-NEXT:    .reg .b64 %fd<7>;
 ; CHECK-PTX-EMPTY:
 ; CHECK-PTX-NEXT:  // %bb.0: // %entry
 ; CHECK-PTX-NEXT:    ld.param.u32 %r1, [variadics1_param_0];
diff --git a/llvm/test/CodeGen/PowerPC/dmr-enable.ll b/llvm/test/CodeGen/PowerPC/dmr-enable.ll
index a6c99a751e2c5..1e3014405ac4e 100644
--- a/llvm/test/CodeGen/PowerPC/dmr-enable.ll
+++ b/llvm/test/CodeGen/PowerPC/dmr-enable.ll
@@ -129,6 +129,248 @@ entry:
   ret void
 }
 
+define void @text512(ptr %vp1, ptr %rp1, ptr %rp2, ptr %rp3, ptr %rp4)  {
+; CHECK-LABEL: text512:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    dmsetdmrz dmr0
+; CHECK-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0
+; CHECK-NEXT:    stxv v2, 16(r4)
+; CHECK-NEXT:    stxv v3, 0(r4)
+; CHECK-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
+; CHECK-NEXT:    stxv v2, 16(r6)
+; CHECK-NEXT:    stxv v3, 0(r6)
+; CHECK-NEXT:    blr
+;
+; CHECK-BE-LABEL: text512:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    dmsetdmrz dmr0
+; CHECK-BE-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0
+; CHECK-BE-NEXT:    stxv v3, 16(r4)
+; CHECK-BE-NEXT:    stxv v2, 0(r4)
+; CHECK-BE-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
+; CHECK-BE-NEXT:    stxv v3, 16(r6)
+; CHECK-BE-NEXT:    stxv v2, 0(r6)
+; CHECK-BE-NEXT:    blr
+entry:
+  %z = call <1024 x i1> @llvm.ppc.mma.dmsetdmrz()
+  %x = call { <256 x i1>, <256 x i1> } @llvm.ppc.mma.dmxxextfdmr512(<1024 x i1> %z, i32 0)
+  %p = extractvalue { <256 x i1>, <256 x i1 > } %x, 0
+  store <256 x i1> %p, ptr %rp1, align 16
+  %y = call { <256 x i1>, <256 x i1> } @llvm.ppc.mma.dmxxextfdmr512(<1024 x i1> %z, i32 1)
+  %q = extractvalue { <256 x i1>, <256 x i1 > } %y, 0
+  store <256 x i1> %q, ptr %rp3, align 16
+  ret void
+}
+
+define void @text256(ptr %vp1, ptr %rp1, ptr %rp2, ptr %rp3, ptr %rp4)  {
+; CHECK-LABEL: text256:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    dmsetdmrz dmr0
+; CHECK-NEXT:    dmxxextfdmr256 vsp34, dmr0, 0
+; CHECK-NEXT:    stxv v2, 16(r4)
+; CHECK-NEXT:    stxv v3, 0(r4)
+; CHECK-NEXT:    dmxxextfdmr256 vsp34, dmr0, 1
+; CHECK-NEXT:    stxv v2, 16(r5)
+; CHECK-NEXT:    stxv v3, 0(r5)
+; CHECK-NEXT:    dmxxextfdmr256 vsp34, dmr0, 2
+; CHECK-NEXT:    stxv v2, 16(r6)
+; CHECK-NEXT:    stxv v3, 0(r6)
+; CHECK-NEXT:    dmxxextfdmr256 vsp34, dmr0, 3
+; CHECK-NEXT:    stxv v2, 16(r7)
+; CHECK-NEXT:    stxv v3, 0(r7)
+; CHECK-NEXT:    blr
+;
+; CHECK-BE-LABEL: text256:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    dmsetdmrz dmr0
+; CHECK-BE-NEXT:    dmxxextfdmr256 vsp34, dmr0, 0
+; CHECK-BE-NEXT:    stxv v3, 16(r4)
+; CHECK-BE-NEXT:    stxv v2, 0(r4)
+; CHECK-BE-NEXT:    dmxxextfdmr256 vsp34, dmr0, 1
+; CHECK-BE-NEXT:    stxv v3, 16(r5)
+; CHECK-BE-NEXT:    stxv v2, 0(r5)
+; CHECK-BE-NEXT:    dmxxextfdmr256 vsp34, dmr0, 2
+; CHECK-BE-NEXT:    stxv v3, 16(r6)
+; CHECK-BE-NEXT:    stxv v2, 0(r6)
+; CHECK-BE-NEXT:    dmxxextfdmr256 vsp34, dmr0, 3
+; CHECK-BE-NEXT:    stxv v3, 16(r7)
+; CHECK-BE-NEXT:    stxv v2, 0(r7)
+; CHECK-BE-NEXT:    blr
+entry:
+  %z = call <1024 x i1> @llvm.ppc.mma.dmsetdmrz()
+  %x = call <256 x i1> @llvm.ppc.mma.dmxxextfdmr256(<1024 x i1> %z, i32 0)
+  store <256 x i1> %x, ptr %rp1, align 16
+  %q = call <256 x i1> @llvm.ppc.mma.dmxxextfdmr256(<1024 x i1> %z, i32 1)
+  store <256 x i1> %q, ptr %rp2, align 16
+  %w = call <256 x i1> @llvm.ppc.mma.dmxxextfdmr256(<1024 x i1> %z, i32 2)
+  store <256 x i1> %w, ptr %rp3, align 16
+  %y = call <256 x i1> @llvm.ppc.mma.dmxxextfdmr256(<1024 x i1> %z, i32 3)
+  store <256 x i1> %y, ptr %rp4, align 16
+  ret void
+}
+
+define void @tins512(ptr %vp1, ptr %vp2, ptr %vp3, ptr %vp4, ptr %rp1, ptr %rp2)  {
+; CHECK-LABEL: tins512:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lxv v2, 16(r3)
+; CHECK-NEXT:    lxv v3, 0(r3)
+; CHECK-NEXT:    lxv v4, 16(r4)
+; CHECK-NEXT:    lxv v5, 0(r4)
+; CHECK-NEXT:    dmsetdmrz dmr0
+; CHECK-NEXT:    dmxxinstdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0
+; CHECK-NEXT:    stxvp vsp34, 96(r7)
+; CHECK-NEXT:    stxvp vsp36, 64(r7)
+; CHECK-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
+; CHECK-NEXT:    stxvp vsp34, 32(r7)
+; CHECK-NEXT:    stxvp vsp36, 0(r7)
+; CHECK-NEXT:    lxv v2, 16(r5)
+; CHECK-NEXT:    lxv v4, 16(r6)
+; CHECK-NEXT:    lxv v3, 0(r5)
+; CHECK-NEXT:    lxv v5, 0(r6)
+; CHECK-NEXT:    dmxxinstdmr512 wacc_hi0, vsp34, vsp36, 1
+; CHECK-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0
+; CHECK-NEXT:    stxvp vsp34, 96(r8)
+; CHECK-NEXT:    stxvp vsp36, 64(r8)
+; CHECK-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
+; CHECK-NEXT:    stxvp vsp34, 32(r8)
+; CHECK-NEXT:    stxvp vsp36, 0(r8)
+; CHECK-NEXT:    blr
+;
+; CHECK-BE-LABEL: tins512:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    lxv v2, 0(r3)
+; CHECK-BE-NEXT:    lxv v3, 16(r3)
+; CHECK-BE-NEXT:    lxv v4, 0(r4)
+; CHECK-BE-NEXT:    lxv v5, 16(r4)
+; CHECK-BE-NEXT:    dmsetdmrz dmr0
+; CHECK-BE-NEXT:    dmxxinstdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-BE-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
+; CHECK-BE-NEXT:    stxvp vsp36, 96(r7)
+; CHECK-BE-NEXT:    stxvp vsp34, 64(r7)
+; CHECK-BE-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0
+; CHECK-BE-NEXT:    stxvp vsp36, 32(r7)
+; CHECK-BE-NEXT:    stxvp vsp34, 0(r7)
+; CHECK-BE-NEXT:    lxv v2, 0(r5)
+; CHECK-BE-NEXT:    lxv v4, 0(r6)
+; CHECK-BE-NEXT:    lxv v3, 16(r5)
+; CHECK-BE-NEXT:    lxv v5, 16(r6)
+; CHECK-BE-NEXT:    dmxxinstdmr512 wacc_hi0, vsp34, vsp36, 1
+; CHECK-BE-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
+; CHECK-BE-NEXT:    stxvp vsp36, 96(r8)
+; CHECK-BE-NEXT:    stxvp vsp34, 64(r8)
+; CHECK-BE-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0
+; CHECK-BE-NEXT:    stxvp vsp36, 32(r8)
+; CHECK-BE-NEXT:    stxvp vsp34, 0(r8)
+; CHECK-BE-NEXT:    blr
+entry:
+  %z = call <1024 x i1> @llvm.ppc.mma.dmsetdmrz()
+  %l1 = load <256 x i1>, ptr %vp1, align 16
+  %r1 = load <256 x i1>, ptr %vp2, align 16
+  %a = call <1024 x i1> @llvm.ppc.mma.dmxxinstdmr512(<1024 x i1> %z, <256 x i1> %l1, <256 x i1> %r1, i32 0)
+  store <1024 x i1> %a, ptr %rp1, align 16
+  %l2 = load <256 x i1>, ptr %vp3, align 16
+  %r2 = load <256 x i1>, ptr %vp4, align 16
+  %b = call <1024 x i1> @llvm.ppc.mma.dmxxinstdmr512(<1024 x i1> %a, <256 x i1> %l2, <256 x i1> %r2, i32 1)
+  store <1024 x i1> %b, ptr %rp2, align 16
+  ret void
+}
+
+define void @tins256(ptr %vp1, ptr %vp2, ptr %vp3, ptr %vp4, ptr %rp1, ptr %rp2, ptr %rp3, ptr %rp4)  {
+; CHECK-LABEL: tins256:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lxv v2, 16(r3)
+; CHECK-NEXT:    lxv v3, 0(r3)
+; CHECK-NEXT:    dmsetdmrz dmr0
+; CHECK-NEXT:    dmxxinstdmr256 dmr0, vsp34, 0
+; CHECK-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0
+; CHECK-NEXT:    stxvp vsp34, 96(r7)
+; CHECK-NEXT:    stxvp vsp36, 64(r7)
+; CHECK-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
+; CHECK-NEXT:    stxvp vsp34, 32(r7)
+; CHECK-NEXT:    stxvp vsp36, 0(r7)
+; CHECK-NEXT:    lxv v2, 16(r4)
+; CHECK-NEXT:    lxv v3, 0(r4)
+; CHECK-NEXT:    dmxxinstdmr256 dmr0, vsp34, 1
+; CHECK-NEXT:    dmxxextfdmr512 vsp36, vsp32, wacc0, 0
+; CHECK-NEXT:    stxvp vsp36, 96(r8)
+; CHECK-NEXT:    stxvp vsp32, 64(r8)
+; CHECK-NEXT:    dmxxextfdmr512 vsp36, vsp32, wacc_hi0, 1
+; CHECK-NEXT:    stxvp vsp36, 32(r8)
+; CHECK-NEXT:    stxvp vsp32, 0(r8)
+; CHECK-NEXT:    dmxxinstdmr256 dmr0, vsp34, 2
+; CHECK-NEXT:    dmxxextfdmr512 vsp36, vsp32, wacc0, 0
+; CHECK-NEXT:    stxvp vsp36, 96(r9)
+; CHECK-NEXT:    stxvp vsp32, 64(r9)
+; CHECK-NEXT:    dmxxextfdmr512 vsp36, vsp32, wacc_hi0, 1
+; CHECK-NEXT:    stxvp vsp36, 32(r9)
+; CHECK-NEXT:    stxvp vsp32, 0(r9)
+; CHECK-NEXT:    dmxxinstdmr256 dmr0, vsp34, 3
+; CHECK-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0
+; CHECK-NEXT:    stxvp vsp34, 96(r10)
+; CHECK-NEXT:    stxvp vsp36, 64(r10)
+; CHECK-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
+; CHECK-NEXT:    stxvp vsp34, 32(r10)
+; CHECK-NEXT:    stxvp vsp36, 0(r10)
+; CHECK-NEXT:    blr
+;
+; CHECK-BE-LABEL: tins256:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    lxv v2, 0(r3)
+; CHECK-BE-NEXT:    lxv v3, 16(r3)
+; CHECK-BE-NEXT:    dmsetdmrz dmr0
+; CHECK-BE-NEXT:    dmxxinstdmr256 dmr0, vsp34, 0
+; CHECK-BE-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
+; CHECK-BE-NEXT:    stxvp vsp36, 96(r7)
+; CHECK-BE-NEXT:    stxvp vsp34, 64(r7)
+; CHECK-BE-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0
+; CHECK-BE-NEXT:    stxvp vsp36, 32(r7)
+; CHECK-BE-NEXT:    stxvp vsp34, 0(r7)
+; CHECK-BE-NEXT:    lxv v2, 0(r4)
+; CHECK-BE-NEXT:    lxv v3, 16(r4)
+; CHECK-BE-NEXT:    dmxxinstdmr256 dmr0, vsp34, 1
+; CHECK-BE-NEXT:    dmxxextfdmr512 vsp36, vsp32, wacc_hi0, 1
+; CHECK-BE-NEXT:    stxvp vsp32, 96(r8)
+; CHECK-BE-NEXT:    stxvp vsp36, 64(r8)
+; CHECK-BE-NEXT:    dmxxextfdmr512 vsp36, vsp32, wacc0, 0
+; CHECK-BE-NEXT:    stxvp vsp32, 32(r8)
+; CHECK-BE-NEXT:    stxvp vsp36, 0(r8)
+; CHECK-BE-NEXT:    dmxxinstdmr256 dmr0, vsp34, 2
+; CHECK-BE-NEXT:    dmxxextfdmr512 vsp36, vsp32, wacc_hi0, 1
+; CHECK-BE-NEXT:    stxvp vsp32, 96(r9)
+; CHECK-BE-NEXT:    stxvp vsp36, 64(r9)
+; CHECK-BE-NEXT:    dmxxextfdmr512 vsp36, vsp32, wacc0, 0
+; CHECK-BE-NEXT:    stxvp vsp32, 32(r9)
+; CHECK-BE-NEXT:    stxvp vsp36, 0(r9)
+; CHECK-BE-NEXT:    dmxxinstdmr256 dmr0, vsp34, 3
+; CHECK-BE-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
+; CHECK-BE-NEXT:    stxvp vsp36, 96(r10)
+; CHECK-BE-NEXT:    stxvp vsp34, 64(r10)
+; CHECK-BE-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0
+; CHECK-BE-NEXT:    stxvp vsp36, 32(r10)
+; CHECK-BE-NEXT:    stxvp vsp34, 0(r10)
+; CHECK-BE-NEXT:    blr
+entry:
+  %z = call <1024 x i1> @llvm.ppc.mma.dmsetdmrz()
+  %l1 = load <256 x i1>, ptr %vp1, align 16
+  %a = call <1024 x i1> @llvm.ppc.mma.dmxxinstdmr256(<1024 x i1> %z, <256 x i1> %l1, i32 0)
+  store <1024 x i1> %a, ptr %rp1, align 16
+  %l2 = load <256 x i1>, ptr %vp2, align 16
+  %b = call <1024 x i1> @llvm.ppc.mma.dmxxinstdmr256(<1024 x i1> %a, <256 x i1> %l2, i32 1)
+  store <1024 x i1> %b, ptr %rp2, align 16
+  %l3 = load <256 x i1>, ptr %vp3, align 16
+  %c = call <1024 x i1> @llvm.ppc.mma.dmxxinstdmr256(<1024 x i1> %b, <256 x i1> %l2, i32 2)
+  store <1024 x i1> %c, ptr %rp3, align 16
+  %l4 = load <256 x i1>, ptr %vp4, align 16
+  %d = call <1024 x i1> @llvm.ppc.mma.dmxxinstdmr256(<1024 x i1> %c, <256 x i1> %l2, i32 3)
+  store <1024 x i1> %d, ptr %rp4, align 16
+  ret void
+}
+
 declare <1024 x i1> @llvm.ppc.mma.dmsetdmrz()
 declare <1024 x i1> @llvm.ppc.mma.dmmr(<1024 x i1>)
 declare <1024 x i1> @llvm.ppc.mma.dmxor(<1024 x i1>, <1024 x i1>)
+declare <1024 x i1> @llvm.ppc.mma.dmxxinstdmr512(<1024 x i1>, <256 x i1>, <256 x i1>, i32)
+declare <1024 x i1> @llvm.ppc.mma.dmxxinstdmr256(<1024 x i1>, <256 x i1>, i32)
+declare { <256 x i1>, <256 x i1> } @llvm.ppc.mma.dmxxextfdmr512(<1024 x i1>, i32)
+declare <256 x i1> @llvm.ppc.mma.dmxxextfdmr256(<1024 x i1>, i32)
diff --git a/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll b/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
index ff7f1fc902981..04351346745b3 100644
--- a/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
+++ b/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
@@ -11945,11 +11945,11 @@ define <2 x i64> @ugt_1_v2i64(<2 x i64> %0) {
 ; PWR5-LABEL: ugt_1_v2i64:
 ; PWR5:       # %bb.0:
 ; PWR5-NEXT:    addi 5, 3, -1
+; PWR5-NEXT:    addi 6, 4, -1
 ; PWR5-NEXT:    and 3, 3, 5
-; PWR5-NEXT:    addi 5, 4, -1
+; PWR5-NEXT:    and 4, 4, 6
 ; PWR5-NEXT:    subfic 3, 3, 0
 ; PWR5-NEXT:    subfe 3, 3, 3
-; PWR5-NEXT:    and 4, 4, 5
 ; PWR5-NEXT:    subfic 4, 4, 0
 ; PWR5-NEXT:    subfe 4, 4, 4
 ; PWR5-NEXT:    blr
@@ -11957,11 +11957,11 @@ define <2 x i64> @ugt_1_v2i64(<2 x i64> %0) {
 ; PWR6-LABEL: ugt_1_v2i64:
 ; PWR6:       # %bb.0:
 ; PWR6-NEXT:    addi 5, 3, -1
+; PWR6-NEXT:    addi 6, 4, -1
 ; PWR6-NEXT:    and 3, 3, 5
-; PWR6-NEXT:    addi 5, 4, -1
+; PWR6-NEXT:    and 4, 4, 6
 ; PWR6-NEXT:    subfic 3, 3, 0
 ; PWR6-NEXT:    subfe 3, 3, 3
-; PWR6-NEXT:    and 4, 4, 5
 ; PWR6-NEXT:    subfic 4, 4, 0
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
@@ -12016,11 +12016,11 @@ define <2 x i64> @ult_2_v2i64(<2 x i64> %0) {
 ; PWR5-LABEL: ult_2_v2i64:
 ; PWR5:       # %bb.0:
 ; PWR5-NEXT:    addi 5, 3, -1
+; PWR5-NEXT:    addi 6, 4, -1
 ; PWR5-NEXT:    and 3, 3, 5
-; PWR5-NEXT:    addi 5, 4, -1
+; PWR5-NEXT:    and 4, 4, 6
 ; PWR5-NEXT:    addic 3, 3, -1
 ; PWR5-NEXT:    subfe 3, 3, 3
-; PWR5-NEXT:    and 4, 4, 5
 ; PWR5-NEXT:    addic 4, 4, -1
 ; PWR5-NEXT:    subfe 4, 4, 4
 ; PWR5-NEXT:    blr
@@ -12028,11 +12028,11 @@ define <2 x i64> @ult_2_v2i64(<2 x i64> %0) {
 ; PWR6-LABEL: ult_2_v2i64:
 ; PWR6:       # %bb.0:
 ; PWR6-NEXT:    addi 5, 3, -1
+; PWR6-NEXT:    addi 6, 4, -1
 ; PWR6-NEXT:    and 3, 3, 5
-; PWR6-NEXT:    addi 5, 4, -1
+; PWR6-NEXT:    and 4, 4, 6
 ; PWR6-NEXT:    addic 3, 3, -1
 ; PWR6-NEXT:    subfe 3, 3, 3
-; PWR6-NEXT:    and 4, 4, 5
 ; PWR6-NEXT:    addic 4, 4, -1
 ; PWR6-NEXT:    subfe 4, 4, 4
 ; PWR6-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/vsx-fma-m-early.ll b/llvm/test/CodeGen/PowerPC/vsx-fma-m-early.ll
new file mode 100644
index 0000000000000..96f64f5d0cabb
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/vsx-fma-m-early.ll
@@ -0,0 +1,178 @@
+;; Tests that the ppc-vsx-fma-mutate pass with the schedule-ppc-vsx-fma-mutation-early pass does not hoist xxspltiw out of loops.
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -disable-ppc-vsx-fma-mutation=false \
+; RUN:   -ppc-asm-full-reg-names -schedule-ppc-vsx-fma-mutation-early \
+; RUN:    -mtriple powerpc64-ibm-aix < %s | FileCheck --check-prefixes=CHECK64,AIX64 %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -disable-ppc-vsx-fma-mutation=false \
+; RUN:   -ppc-asm-full-reg-names -schedule-ppc-vsx-fma-mutation-early \
+; RUN:   -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck --check-prefixes=CHECK64,LINUX64 %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -disable-ppc-vsx-fma-mutation=false \
+; RUN:   -ppc-asm-full-reg-names -schedule-ppc-vsx-fma-mutation-early \
+; RUN:    -mtriple powerpc-ibm-aix < %s | FileCheck --check-prefix=CHECK32 %s
+
+define void @bar(ptr noalias nocapture noundef writeonly %__output_a, ptr noalias nocapture noundef readonly %var1321In_a, ptr noalias nocapture noundef readonly %n) {
+entry:
+  %0 = load i32, ptr %n, align 4
+  %cmp11 = icmp sgt i32 %0, 0
+  br i1 %cmp11, label %for.body.preheader, label %for.end
+
+for.body.preheader:
+  %wide.trip.count = zext i32 %0 to i64
+  br label %for.body
+
+for.body:
+  %indvars.iv = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next, %for.body ]
+  %1 = shl nsw i64 %indvars.iv, 2
+  %add.ptr = getelementptr inbounds float, ptr %var1321In_a, i64 %1
+  %add.ptr.val = load <4 x float>, ptr %add.ptr, align 1
+  %2 = tail call contract <4 x float> @llvm.fma.v4f32(<4 x float> %add.ptr.val, <4 x float> <float 0x3FF7154760000000, float 0x3FF7154760000000, float 0x3FF7154760000000, float 0x3FF7154760000000>, <4 x float> <float 6.270500e+03, float 6.270500e+03, float 6.270500e+03, float 6.270500e+03>)
+  %add.ptr6 = getelementptr inbounds float, ptr %__output_a, i64 %1
+  store <4 x float> %2, ptr %add.ptr6, align 1 
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
+  br i1 %exitcond.not, label %for.end, label %for.body
+
+for.end:
+  ret void
+}
+
+define void @foo(i1 %cmp97) #0 {
+entry:
+  br i1 %cmp97, label %for.body, label %for.end
+
+for.body:                                         ; preds = %for.body, %entry
+  %0 = phi float [ %vecext.i, %for.body ], [ 0.000000e+00, %entry ]
+  %splat.splatinsert.i = insertelement <4 x float> zeroinitializer, float %0, i64 0
+  %1 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %splat.splatinsert.i, <4 x float> zeroinitializer, <4 x float> splat (float 6.270500e+03))
+  %2 = tail call <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float> zeroinitializer, <4 x float> %splat.splatinsert.i)
+  %3 = bitcast <4 x float> %1 to <4 x i32>
+  %and1.i8896 = and <4 x i32> %2, %3
+  %4 = bitcast <4 x i32> %and1.i8896 to <4 x float>
+  %vecext.i = extractelement <4 x float> %4, i64 0
+  br label %for.body
+
+for.end:                                          ; preds = %entry
+    ret void
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) 
+
+; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
+declare <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float>, <4 x float>)
+
+; CHECK64:      bar:
+; CHECK64:      # %bb.0:                                # %entry
+; CHECK64-NEXT:         lwz r5, 0(r5)
+; CHECK64-NEXT:         cmpwi   r5, 1
+; CHECK64-NEXT:         bltlr   cr0
+; CHECK64-NEXT: # %bb.1:                                # %for.body.preheader
+; CHECK64-NEXT:         xxspltiw vs0, 1069066811
+; CHECK64-NEXT:         mtctr r5
+; CHECK64-NEXT:         li r5, 0
+; CHECK64-NEXT:         {{.*}}align  5
+; CHECK64-NEXT: [[L2_bar:.*]]:                               # %for.body
+; CHECK64-NEXT:                                         # =>This Inner Loop Header: Depth=1
+; CHECK64-NEXT:         lxvx vs1, r4, r5
+; CHECK64-NEXT:         xxspltiw vs2, 1170469888
+; CHECK64-NEXT:         xvmaddasp vs2, vs1, vs0
+; CHECK64-NEXT:         stxvx vs2, r3, r5
+; CHECK64-NEXT:         addi r5, r5, 16
+; CHECK64-NEXT:         bdnz [[L2_bar]]
+; CHECK64-NEXT: # %bb.3:                                # %for.end
+; CHECK64-NEXT:         blr
+
+; AIX64:      .foo:
+; AIX64-NEXT: # %bb.0:                                # %entry
+; AIX64-NEXT:   andi. r3, r3, 1
+; AIX64-NEXT:   bclr 4, gt, 0
+; AIX64-NEXT: # %bb.1:                                # %for.body.preheader
+; AIX64-NEXT:   xxlxor f0, f0, f0
+; AIX64-NEXT:   xxlxor vs1, vs1, vs1
+; AIX64-NEXT:   xxlxor f2, f2, f2
+; AIX64-NEXT:   .align  4
+; AIX64-NEXT: L..BB1_2:                               # %for.body
+; AIX64-NEXT:                                         # =>This Inner Loop Header: Depth=1
+; AIX64-NEXT:   xxmrghd vs2, vs2, vs0
+; AIX64-NEXT:   xvcvdpsp vs34, vs2
+; AIX64-NEXT:   xxmrghd vs2, vs0, vs0
+; AIX64-NEXT:   xvcvdpsp vs35, vs2
+; AIX64-NEXT:   xxspltiw vs2, 1170469888
+; AIX64-NEXT:   vmrgew v2, v2, v3
+; AIX64-NEXT:   xvcmpgtsp vs3, vs1, vs34
+; AIX64-NEXT:   xvmaddasp vs2, vs34, vs1
+; AIX64-NEXT:   xxland vs2, vs3, vs2
+; AIX64-NEXT:   xscvspdpn f2, vs2
+; AIX64-NEXT:   b L..BB1_2
+
+; LINUX64:      foo:                                    # @foo
+; LINUX64-NEXT: .Lfunc_begin1:
+; LINUX64-NEXT:         .cfi_startproc
+; LINUX64-NEXT: # %bb.0:                                # %entry
+; LINUX64-NEXT:         andi. r3, r3, 1
+; LINUX64-NEXT:         bclr 4, gt, 0
+; LINUX64-NEXT: # %bb.1:                                # %for.body.preheader
+; LINUX64-NEXT:         xxlxor f0, f0, f0
+; LINUX64-NEXT:         xxlxor vs1, vs1, vs1
+; LINUX64-NEXT:         xxlxor f2, f2, f2
+; LINUX64-NEXT:         .p2align        4
+; LINUX64-NEXT: .LBB1_2:                                # %for.body
+; LINUX64-NEXT:                                         # =>This Inner Loop Header: Depth=1
+; LINUX64-NEXT:         xxmrghd vs2, vs0, vs2
+; LINUX64-NEXT:         xvcvdpsp vs34, vs2
+; LINUX64-NEXT:         xxspltd vs2, vs0, 0
+; LINUX64-NEXT:         xvcvdpsp vs35, vs2
+; LINUX64-NEXT:         xxspltiw vs2, 1170469888
+; LINUX64-NEXT:         vmrgew v2, v3, v2
+; LINUX64-NEXT:         xvcmpgtsp vs3, vs1, vs34
+; LINUX64-NEXT:         xvmaddasp vs2, vs34, vs1
+; LINUX64-NEXT:         xxland vs2, vs3, vs2
+; LINUX64-NEXT:         xxsldwi vs2, vs2, vs2, 3
+; LINUX64-NEXT:         xscvspdpn f2, vs2
+; LINUX64-NEXT:         b .LBB1_2
+
+; CHECK32:        .bar:
+; CHECK32-NEXT: # %bb.0:                                # %entry
+; CHECK32-NEXT:       lwz r5, 0(r5)
+; CHECK32-NEXT:       cmpwi   r5, 0
+; CHECK32-NEXT:       blelr cr0
+; CHECK32-NEXT: # %bb.1:                                # %for.body.preheader
+; CHECK32-NEXT:       xxspltiw vs0, 1069066811
+; CHECK32-NEXT:       li r6, 0
+; CHECK32-NEXT:       li r7, 0
+; CHECK32-NEXT:       .align  4
+; CHECK32-NEXT: [[L2_foo:.*]]:                               # %for.body
+; CHECK32-NEXT:                                         # =>This Inner Loop Header: Depth=1
+; CHECK32-NEXT:       slwi r8, r7, 4
+; CHECK32-NEXT:       xxspltiw vs2, 1170469888
+; CHECK32-NEXT:       addic r7, r7, 1
+; CHECK32-NEXT:       addze r6, r6
+; CHECK32-NEXT:       lxvx vs1, r4, r8
+; CHECK32-NEXT:       xvmaddasp vs2, vs1, vs0
+; CHECK32-NEXT:       stxvx vs2, r3, r8
+; CHECK32-NEXT:       xor r8, r7, r5
+; CHECK32-NEXT:       or. r8, r8, r6
+; CHECK32-NEXT:       bne     cr0, [[L2_foo]]
+
+; CHECK32:      .foo:
+; CHECK32-NEXT: # %bb.0:                                # %entry
+; CHECK32-NEXT:         andi. r3, r3, 1
+; CHECK32-NEXT:         bclr 4, gt, 0
+; CHECK32-NEXT: # %bb.1:                                # %for.body.preheader
+; CHECK32-NEXT:         lwz r3, L..C0(r2)                       # %const.0
+; CHECK32-NEXT:         xxlxor f1, f1, f1
+; CHECK32-NEXT:         xxlxor vs0, vs0, vs0
+; CHECK32-NEXT:         xscvdpspn vs35, f1
+; CHECK32-NEXT:         lxv vs34, 0(r3)
+; CHECK32-NEXT:         .align  4
+; CHECK32-NEXT: L..BB1_2:                               # %for.body
+; CHECK32-NEXT:                                         # =>This Inner Loop Header: Depth=1
+; CHECK32-NEXT:         xscvdpspn vs36, f1
+; CHECK32-NEXT:         xxspltiw vs1, 1170469888
+; CHECK32-NEXT:         vperm v4, v4, v3, v2
+; CHECK32-NEXT:         xvcmpgtsp vs2, vs0, vs36
+; CHECK32-NEXT:         xvmaddasp vs1, vs36, vs0
+; CHECK32-NEXT:         xxland vs1, vs2, vs1
+; CHECK32-NEXT:         xscvspdpn f1, vs1
+; CHECK32-NEXT:         b L..BB1_2
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
index 95af7861d4798..f9af74d6ec323 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
@@ -357,49 +357,14 @@ define i64 @ctpop_i64(i64 %a) nounwind {
 define i1 @ctpop_i64_ugt_two(i64 %a) nounwind {
 ; RV32I-LABEL: ctpop_i64_ugt_two:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    j .LBB6_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    sltiu a0, zero, 0
-; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB6_2:
-; RV32I-NEXT:    srli a2, a0, 1
-; RV32I-NEXT:    lui a3, 349525
-; RV32I-NEXT:    lui a4, 209715
-; RV32I-NEXT:    srli a5, a1, 1
-; RV32I-NEXT:    addi a3, a3, 1365
-; RV32I-NEXT:    and a2, a2, a3
-; RV32I-NEXT:    and a3, a5, a3
-; RV32I-NEXT:    lui a5, 61681
-; RV32I-NEXT:    addi a4, a4, 819
-; RV32I-NEXT:    addi a5, a5, -241
-; RV32I-NEXT:    sub a0, a0, a2
-; RV32I-NEXT:    sub a1, a1, a3
-; RV32I-NEXT:    srli a2, a0, 2
-; RV32I-NEXT:    and a0, a0, a4
-; RV32I-NEXT:    srli a3, a1, 2
-; RV32I-NEXT:    and a1, a1, a4
-; RV32I-NEXT:    and a2, a2, a4
-; RV32I-NEXT:    and a3, a3, a4
-; RV32I-NEXT:    add a0, a2, a0
-; RV32I-NEXT:    add a1, a3, a1
-; RV32I-NEXT:    srli a2, a0, 4
-; RV32I-NEXT:    srli a3, a1, 4
-; RV32I-NEXT:    add a0, a2, a0
-; RV32I-NEXT:    add a1, a3, a1
-; RV32I-NEXT:    and a0, a0, a5
-; RV32I-NEXT:    and a1, a1, a5
-; RV32I-NEXT:    slli a2, a0, 8
-; RV32I-NEXT:    slli a3, a1, 8
-; RV32I-NEXT:    add a0, a0, a2
-; RV32I-NEXT:    add a1, a1, a3
-; RV32I-NEXT:    slli a2, a0, 16
-; RV32I-NEXT:    slli a3, a1, 16
-; RV32I-NEXT:    add a0, a0, a2
-; RV32I-NEXT:    add a1, a1, a3
-; RV32I-NEXT:    srli a0, a0, 24
-; RV32I-NEXT:    srli a1, a1, 24
-; RV32I-NEXT:    add a0, a1, a0
-; RV32I-NEXT:    sltiu a0, a0, 2
+; RV32I-NEXT:    addi a2, a0, -1
+; RV32I-NEXT:    addi a3, a1, -1
+; RV32I-NEXT:    sltiu a4, a2, -1
+; RV32I-NEXT:    add a3, a3, a4
+; RV32I-NEXT:    and a0, a0, a2
+; RV32I-NEXT:    and a1, a1, a3
+; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: ctpop_i64_ugt_two:
@@ -422,50 +387,14 @@ define i1 @ctpop_i64_ugt_two(i64 %a) nounwind {
 define i1 @ctpop_i64_ugt_one(i64 %a) nounwind {
 ; RV32I-LABEL: ctpop_i64_ugt_one:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    j .LBB7_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    snez a0, zero
-; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB7_2:
-; RV32I-NEXT:    srli a2, a0, 1
-; RV32I-NEXT:    lui a3, 349525
-; RV32I-NEXT:    lui a4, 209715
-; RV32I-NEXT:    srli a5, a1, 1
-; RV32I-NEXT:    addi a3, a3, 1365
-; RV32I-NEXT:    and a2, a2, a3
-; RV32I-NEXT:    and a3, a5, a3
-; RV32I-NEXT:    lui a5, 61681
-; RV32I-NEXT:    addi a4, a4, 819
-; RV32I-NEXT:    addi a5, a5, -241
-; RV32I-NEXT:    sub a0, a0, a2
-; RV32I-NEXT:    sub a1, a1, a3
-; RV32I-NEXT:    srli a2, a0, 2
-; RV32I-NEXT:    and a0, a0, a4
-; RV32I-NEXT:    srli a3, a1, 2
-; RV32I-NEXT:    and a1, a1, a4
-; RV32I-NEXT:    and a2, a2, a4
-; RV32I-NEXT:    and a3, a3, a4
-; RV32I-NEXT:    add a0, a2, a0
-; RV32I-NEXT:    add a1, a3, a1
-; RV32I-NEXT:    srli a2, a0, 4
-; RV32I-NEXT:    srli a3, a1, 4
-; RV32I-NEXT:    add a0, a2, a0
-; RV32I-NEXT:    add a1, a3, a1
-; RV32I-NEXT:    and a0, a0, a5
-; RV32I-NEXT:    and a1, a1, a5
-; RV32I-NEXT:    slli a2, a0, 8
-; RV32I-NEXT:    slli a3, a1, 8
-; RV32I-NEXT:    add a0, a0, a2
-; RV32I-NEXT:    add a1, a1, a3
-; RV32I-NEXT:    slli a2, a0, 16
-; RV32I-NEXT:    slli a3, a1, 16
-; RV32I-NEXT:    add a0, a0, a2
-; RV32I-NEXT:    add a1, a1, a3
-; RV32I-NEXT:    srli a0, a0, 24
-; RV32I-NEXT:    srli a1, a1, 24
-; RV32I-NEXT:    add a0, a1, a0
-; RV32I-NEXT:    sltiu a0, a0, 2
-; RV32I-NEXT:    xori a0, a0, 1
+; RV32I-NEXT:    addi a2, a0, -1
+; RV32I-NEXT:    addi a3, a1, -1
+; RV32I-NEXT:    sltiu a4, a2, -1
+; RV32I-NEXT:    add a3, a3, a4
+; RV32I-NEXT:    and a0, a0, a2
+; RV32I-NEXT:    and a1, a1, a3
+; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: ctpop_i64_ugt_one:
@@ -489,45 +418,18 @@ define i1 @ctpop_i64_ugt_one(i64 %a) nounwind {
 define i1 @ctpop_i64_eq_one(i64 %a) nounwind {
 ; RV32I-LABEL: ctpop_i64_eq_one:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    srli a2, a0, 1
-; RV32I-NEXT:    lui a3, 349525
-; RV32I-NEXT:    lui a4, 209715
-; RV32I-NEXT:    srli a5, a1, 1
-; RV32I-NEXT:    addi a3, a3, 1365
-; RV32I-NEXT:    and a2, a2, a3
-; RV32I-NEXT:    and a3, a5, a3
-; RV32I-NEXT:    lui a5, 61681
-; RV32I-NEXT:    addi a4, a4, 819
-; RV32I-NEXT:    addi a5, a5, -241
-; RV32I-NEXT:    sub a0, a0, a2
-; RV32I-NEXT:    sub a1, a1, a3
-; RV32I-NEXT:    srli a2, a0, 2
-; RV32I-NEXT:    and a0, a0, a4
-; RV32I-NEXT:    srli a3, a1, 2
-; RV32I-NEXT:    and a1, a1, a4
-; RV32I-NEXT:    and a2, a2, a4
-; RV32I-NEXT:    and a3, a3, a4
-; RV32I-NEXT:    add a0, a2, a0
-; RV32I-NEXT:    add a1, a3, a1
-; RV32I-NEXT:    srli a2, a0, 4
-; RV32I-NEXT:    srli a3, a1, 4
-; RV32I-NEXT:    add a0, a2, a0
-; RV32I-NEXT:    add a1, a3, a1
-; RV32I-NEXT:    and a0, a0, a5
-; RV32I-NEXT:    and a1, a1, a5
-; RV32I-NEXT:    slli a2, a0, 8
-; RV32I-NEXT:    slli a3, a1, 8
-; RV32I-NEXT:    add a0, a0, a2
-; RV32I-NEXT:    add a1, a1, a3
-; RV32I-NEXT:    slli a2, a0, 16
-; RV32I-NEXT:    slli a3, a1, 16
-; RV32I-NEXT:    add a0, a0, a2
-; RV32I-NEXT:    add a1, a1, a3
-; RV32I-NEXT:    srli a0, a0, 24
-; RV32I-NEXT:    srli a1, a1, 24
-; RV32I-NEXT:    add a0, a1, a0
-; RV32I-NEXT:    xori a0, a0, 1
-; RV32I-NEXT:    seqz a0, a0
+; RV32I-NEXT:    addi a2, a0, -1
+; RV32I-NEXT:    sltiu a3, a2, -1
+; RV32I-NEXT:    addi a4, a1, -1
+; RV32I-NEXT:    add a3, a4, a3
+; RV32I-NEXT:    xor a1, a1, a3
+; RV32I-NEXT:    beq a1, a3, .LBB8_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    sltu a0, a3, a1
+; RV32I-NEXT:    ret
+; RV32I-NEXT:  .LBB8_2:
+; RV32I-NEXT:    xor a0, a0, a2
+; RV32I-NEXT:    sltu a0, a2, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: ctpop_i64_eq_one:
@@ -546,45 +448,20 @@ define i1 @ctpop_i64_eq_one(i64 %a) nounwind {
 define i1 @ctpop_i64_ne_one(i64 %a) nounwind {
 ; RV32I-LABEL: ctpop_i64_ne_one:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    srli a2, a0, 1
-; RV32I-NEXT:    lui a3, 349525
-; RV32I-NEXT:    lui a4, 209715
-; RV32I-NEXT:    srli a5, a1, 1
-; RV32I-NEXT:    addi a3, a3, 1365
-; RV32I-NEXT:    and a2, a2, a3
-; RV32I-NEXT:    and a3, a5, a3
-; RV32I-NEXT:    lui a5, 61681
-; RV32I-NEXT:    addi a4, a4, 819
-; RV32I-NEXT:    addi a5, a5, -241
-; RV32I-NEXT:    sub a0, a0, a2
-; RV32I-NEXT:    sub a1, a1, a3
-; RV32I-NEXT:    srli a2, a0, 2
-; RV32I-NEXT:    and a0, a0, a4
-; RV32I-NEXT:    srli a3, a1, 2
-; RV32I-NEXT:    and a1, a1, a4
-; RV32I-NEXT:    and a2, a2, a4
-; RV32I-NEXT:    and a3, a3, a4
-; RV32I-NEXT:    add a0, a2, a0
-; RV32I-NEXT:    add a1, a3, a1
-; RV32I-NEXT:    srli a2, a0, 4
-; RV32I-NEXT:    srli a3, a1, 4
-; RV32I-NEXT:    add a0, a2, a0
-; RV32I-NEXT:    add a1, a3, a1
-; RV32I-NEXT:    and a0, a0, a5
-; RV32I-NEXT:    and a1, a1, a5
-; RV32I-NEXT:    slli a2, a0, 8
-; RV32I-NEXT:    slli a3, a1, 8
-; RV32I-NEXT:    add a0, a0, a2
-; RV32I-NEXT:    add a1, a1, a3
-; RV32I-NEXT:    slli a2, a0, 16
-; RV32I-NEXT:    slli a3, a1, 16
-; RV32I-NEXT:    add a0, a0, a2
-; RV32I-NEXT:    add a1, a1, a3
-; RV32I-NEXT:    srli a0, a0, 24
-; RV32I-NEXT:    srli a1, a1, 24
-; RV32I-NEXT:    add a0, a1, a0
+; RV32I-NEXT:    addi a2, a0, -1
+; RV32I-NEXT:    sltiu a3, a2, -1
+; RV32I-NEXT:    addi a4, a1, -1
+; RV32I-NEXT:    add a3, a4, a3
+; RV32I-NEXT:    xor a1, a1, a3
+; RV32I-NEXT:    beq a1, a3, .LBB9_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    sltu a0, a3, a1
+; RV32I-NEXT:    xori a0, a0, 1
+; RV32I-NEXT:    ret
+; RV32I-NEXT:  .LBB9_2:
+; RV32I-NEXT:    xor a0, a0, a2
+; RV32I-NEXT:    sltu a0, a2, a0
 ; RV32I-NEXT:    xori a0, a0, 1
-; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: ctpop_i64_ne_one:
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
index 9a6c718703a27..8549a7c526e45 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
@@ -701,31 +701,9 @@ define signext i32 @ctpop_i32(i32 signext %a) nounwind {
 define i1 @ctpop_i32_ult_two(i32 signext %a) nounwind {
 ; RV64I-LABEL: ctpop_i32_ult_two:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -16
-; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    srliw a1, a0, 1
-; RV64I-NEXT:    lui a2, 349525
-; RV64I-NEXT:    addi a2, a2, 1365
-; RV64I-NEXT:    and a1, a1, a2
-; RV64I-NEXT:    lui a2, 209715
-; RV64I-NEXT:    addi a2, a2, 819
-; RV64I-NEXT:    subw a0, a0, a1
-; RV64I-NEXT:    srliw a1, a0, 2
-; RV64I-NEXT:    and a0, a0, a2
-; RV64I-NEXT:    and a1, a1, a2
-; RV64I-NEXT:    lui a2, 61681
-; RV64I-NEXT:    add a0, a1, a0
-; RV64I-NEXT:    sraiw a1, a0, 4
-; RV64I-NEXT:    addw a0, a1, a0
-; RV64I-NEXT:    lui a1, 4112
-; RV64I-NEXT:    addiw a2, a2, -241
-; RV64I-NEXT:    and a0, a0, a2
-; RV64I-NEXT:    addiw a1, a1, 257
-; RV64I-NEXT:    call __muldi3
-; RV64I-NEXT:    srliw a0, a0, 24
-; RV64I-NEXT:    sltiu a0, a0, 2
-; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    addiw a1, a0, -1
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    seqz a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: ctpop_i32_ult_two:
diff --git a/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll b/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
index f9f1ba60a8ac0..874cf897470e7 100644
--- a/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
+++ b/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
@@ -419,8 +419,8 @@ define void @callee() {
 ;
 ; RV32IZCMP-LABEL: callee:
 ; RV32IZCMP:       # %bb.0:
-; RV32IZCMP-NEXT:    cm.push {ra, s0-s11}, -80
-; RV32IZCMP-NEXT:    .cfi_def_cfa_offset 80
+; RV32IZCMP-NEXT:    cm.push {ra, s0-s11}, -96
+; RV32IZCMP-NEXT:    .cfi_def_cfa_offset 96
 ; RV32IZCMP-NEXT:    .cfi_offset ra, -52
 ; RV32IZCMP-NEXT:    .cfi_offset s0, -48
 ; RV32IZCMP-NEXT:    .cfi_offset s1, -44
@@ -436,18 +436,18 @@ define void @callee() {
 ; RV32IZCMP-NEXT:    .cfi_offset s11, -4
 ; RV32IZCMP-NEXT:    lui t0, %hi(var)
 ; RV32IZCMP-NEXT:    lw a0, %lo(var)(t0)
-; RV32IZCMP-NEXT:    sw a0, 24(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 28(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, %lo(var+4)(t0)
-; RV32IZCMP-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 24(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, %lo(var+8)(t0)
-; RV32IZCMP-NEXT:    sw a0, 16(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, %lo(var+12)(t0)
-; RV32IZCMP-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 16(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    addi a5, t0, %lo(var)
 ; RV32IZCMP-NEXT:    lw a0, 16(a5)
-; RV32IZCMP-NEXT:    sw a0, 8(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, 20(a5)
-; RV32IZCMP-NEXT:    sw a0, 4(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 8(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw t4, 24(a5)
 ; RV32IZCMP-NEXT:    lw t5, 28(a5)
 ; RV32IZCMP-NEXT:    lw t6, 32(a5)
@@ -500,19 +500,19 @@ define void @callee() {
 ; RV32IZCMP-NEXT:    sw t6, 32(a5)
 ; RV32IZCMP-NEXT:    sw t5, 28(a5)
 ; RV32IZCMP-NEXT:    sw t4, 24(a5)
-; RV32IZCMP-NEXT:    lw a0, 4(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, 20(a5)
 ; RV32IZCMP-NEXT:    lw a0, 8(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, 16(a5)
+; RV32IZCMP-NEXT:    sw a0, 20(a5)
 ; RV32IZCMP-NEXT:    lw a0, 12(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, %lo(var+12)(t0)
+; RV32IZCMP-NEXT:    sw a0, 16(a5)
 ; RV32IZCMP-NEXT:    lw a0, 16(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, %lo(var+8)(t0)
+; RV32IZCMP-NEXT:    sw a0, %lo(var+12)(t0)
 ; RV32IZCMP-NEXT:    lw a0, 20(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, %lo(var+4)(t0)
+; RV32IZCMP-NEXT:    sw a0, %lo(var+8)(t0)
 ; RV32IZCMP-NEXT:    lw a0, 24(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    sw a0, %lo(var+4)(t0)
+; RV32IZCMP-NEXT:    lw a0, 28(sp) # 4-byte Folded Reload
 ; RV32IZCMP-NEXT:    sw a0, %lo(var)(t0)
-; RV32IZCMP-NEXT:    cm.popret {ra, s0-s11}, 80
+; RV32IZCMP-NEXT:    cm.popret {ra, s0-s11}, 96
 ;
 ; RV32IZCMP-WITH-FP-LABEL: callee:
 ; RV32IZCMP-WITH-FP:       # %bb.0:
@@ -1055,18 +1055,18 @@ define void @callee() {
 ; RV64IZCMP-NEXT:    .cfi_offset s11, -8
 ; RV64IZCMP-NEXT:    lui t0, %hi(var)
 ; RV64IZCMP-NEXT:    lw a0, %lo(var)(t0)
-; RV64IZCMP-NEXT:    sd a0, 48(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, %lo(var+4)(t0)
 ; RV64IZCMP-NEXT:    sd a0, 40(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, %lo(var+8)(t0)
+; RV64IZCMP-NEXT:    lw a0, %lo(var+4)(t0)
 ; RV64IZCMP-NEXT:    sd a0, 32(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, %lo(var+12)(t0)
+; RV64IZCMP-NEXT:    lw a0, %lo(var+8)(t0)
 ; RV64IZCMP-NEXT:    sd a0, 24(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    lw a0, %lo(var+12)(t0)
+; RV64IZCMP-NEXT:    sd a0, 16(sp) # 8-byte Folded Spill
 ; RV64IZCMP-NEXT:    addi a5, t0, %lo(var)
 ; RV64IZCMP-NEXT:    lw a0, 16(a5)
-; RV64IZCMP-NEXT:    sd a0, 16(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, 20(a5)
 ; RV64IZCMP-NEXT:    sd a0, 8(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    lw a0, 20(a5)
+; RV64IZCMP-NEXT:    sd a0, 0(sp) # 8-byte Folded Spill
 ; RV64IZCMP-NEXT:    lw t4, 24(a5)
 ; RV64IZCMP-NEXT:    lw t5, 28(a5)
 ; RV64IZCMP-NEXT:    lw t6, 32(a5)
@@ -1119,17 +1119,17 @@ define void @callee() {
 ; RV64IZCMP-NEXT:    sw t6, 32(a5)
 ; RV64IZCMP-NEXT:    sw t5, 28(a5)
 ; RV64IZCMP-NEXT:    sw t4, 24(a5)
-; RV64IZCMP-NEXT:    ld a0, 8(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 0(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, 20(a5)
-; RV64IZCMP-NEXT:    ld a0, 16(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 8(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, 16(a5)
-; RV64IZCMP-NEXT:    ld a0, 24(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 16(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, %lo(var+12)(t0)
-; RV64IZCMP-NEXT:    ld a0, 32(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 24(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, %lo(var+8)(t0)
-; RV64IZCMP-NEXT:    ld a0, 40(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 32(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, %lo(var+4)(t0)
-; RV64IZCMP-NEXT:    ld a0, 48(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 40(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, %lo(var)(t0)
 ; RV64IZCMP-NEXT:    cm.popret {ra, s0-s11}, 160
 ;
@@ -1798,54 +1798,54 @@ define void @caller() {
 ; RV32IZCMP-NEXT:    .cfi_offset s9, -12
 ; RV32IZCMP-NEXT:    .cfi_offset s10, -8
 ; RV32IZCMP-NEXT:    .cfi_offset s11, -4
-; RV32IZCMP-NEXT:    addi sp, sp, -32
-; RV32IZCMP-NEXT:    .cfi_def_cfa_offset 144
+; RV32IZCMP-NEXT:    addi sp, sp, -48
+; RV32IZCMP-NEXT:    .cfi_def_cfa_offset 160
 ; RV32IZCMP-NEXT:    lui s0, %hi(var)
 ; RV32IZCMP-NEXT:    lw a0, %lo(var)(s0)
-; RV32IZCMP-NEXT:    sw a0, 88(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 92(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, %lo(var+4)(s0)
-; RV32IZCMP-NEXT:    sw a0, 84(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 88(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, %lo(var+8)(s0)
-; RV32IZCMP-NEXT:    sw a0, 80(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 84(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, %lo(var+12)(s0)
-; RV32IZCMP-NEXT:    sw a0, 76(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 80(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    addi s1, s0, %lo(var)
 ; RV32IZCMP-NEXT:    lw a0, 16(s1)
-; RV32IZCMP-NEXT:    sw a0, 72(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 76(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, 20(s1)
-; RV32IZCMP-NEXT:    sw a0, 68(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 72(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, 24(s1)
-; RV32IZCMP-NEXT:    sw a0, 64(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 68(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, 28(s1)
-; RV32IZCMP-NEXT:    sw a0, 60(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 64(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, 32(s1)
-; RV32IZCMP-NEXT:    sw a0, 56(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 60(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, 36(s1)
-; RV32IZCMP-NEXT:    sw a0, 52(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 56(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, 40(s1)
-; RV32IZCMP-NEXT:    sw a0, 48(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 52(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, 44(s1)
-; RV32IZCMP-NEXT:    sw a0, 44(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 48(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, 48(s1)
-; RV32IZCMP-NEXT:    sw a0, 40(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 44(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, 52(s1)
-; RV32IZCMP-NEXT:    sw a0, 36(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 40(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, 56(s1)
-; RV32IZCMP-NEXT:    sw a0, 32(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 36(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, 60(s1)
-; RV32IZCMP-NEXT:    sw a0, 28(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 32(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, 64(s1)
-; RV32IZCMP-NEXT:    sw a0, 24(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 28(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, 68(s1)
-; RV32IZCMP-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 24(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, 72(s1)
-; RV32IZCMP-NEXT:    sw a0, 16(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, 76(s1)
-; RV32IZCMP-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 16(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, 80(s1)
-; RV32IZCMP-NEXT:    sw a0, 8(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, 84(s1)
-; RV32IZCMP-NEXT:    sw a0, 4(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 8(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw s4, 88(s1)
 ; RV32IZCMP-NEXT:    lw s5, 92(s1)
 ; RV32IZCMP-NEXT:    lw s6, 96(s1)
@@ -1867,51 +1867,51 @@ define void @caller() {
 ; RV32IZCMP-NEXT:    sw s6, 96(s1)
 ; RV32IZCMP-NEXT:    sw s5, 92(s1)
 ; RV32IZCMP-NEXT:    sw s4, 88(s1)
-; RV32IZCMP-NEXT:    lw a0, 4(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, 84(s1)
 ; RV32IZCMP-NEXT:    lw a0, 8(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, 80(s1)
+; RV32IZCMP-NEXT:    sw a0, 84(s1)
 ; RV32IZCMP-NEXT:    lw a0, 12(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, 76(s1)
+; RV32IZCMP-NEXT:    sw a0, 80(s1)
 ; RV32IZCMP-NEXT:    lw a0, 16(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, 72(s1)
+; RV32IZCMP-NEXT:    sw a0, 76(s1)
 ; RV32IZCMP-NEXT:    lw a0, 20(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, 68(s1)
+; RV32IZCMP-NEXT:    sw a0, 72(s1)
 ; RV32IZCMP-NEXT:    lw a0, 24(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, 64(s1)
+; RV32IZCMP-NEXT:    sw a0, 68(s1)
 ; RV32IZCMP-NEXT:    lw a0, 28(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, 60(s1)
+; RV32IZCMP-NEXT:    sw a0, 64(s1)
 ; RV32IZCMP-NEXT:    lw a0, 32(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, 56(s1)
+; RV32IZCMP-NEXT:    sw a0, 60(s1)
 ; RV32IZCMP-NEXT:    lw a0, 36(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, 52(s1)
+; RV32IZCMP-NEXT:    sw a0, 56(s1)
 ; RV32IZCMP-NEXT:    lw a0, 40(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, 48(s1)
+; RV32IZCMP-NEXT:    sw a0, 52(s1)
 ; RV32IZCMP-NEXT:    lw a0, 44(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, 44(s1)
+; RV32IZCMP-NEXT:    sw a0, 48(s1)
 ; RV32IZCMP-NEXT:    lw a0, 48(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, 40(s1)
+; RV32IZCMP-NEXT:    sw a0, 44(s1)
 ; RV32IZCMP-NEXT:    lw a0, 52(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, 36(s1)
+; RV32IZCMP-NEXT:    sw a0, 40(s1)
 ; RV32IZCMP-NEXT:    lw a0, 56(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, 32(s1)
+; RV32IZCMP-NEXT:    sw a0, 36(s1)
 ; RV32IZCMP-NEXT:    lw a0, 60(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, 28(s1)
+; RV32IZCMP-NEXT:    sw a0, 32(s1)
 ; RV32IZCMP-NEXT:    lw a0, 64(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, 24(s1)
+; RV32IZCMP-NEXT:    sw a0, 28(s1)
 ; RV32IZCMP-NEXT:    lw a0, 68(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, 20(s1)
+; RV32IZCMP-NEXT:    sw a0, 24(s1)
 ; RV32IZCMP-NEXT:    lw a0, 72(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, 16(s1)
+; RV32IZCMP-NEXT:    sw a0, 20(s1)
 ; RV32IZCMP-NEXT:    lw a0, 76(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, %lo(var+12)(s0)
+; RV32IZCMP-NEXT:    sw a0, 16(s1)
 ; RV32IZCMP-NEXT:    lw a0, 80(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, %lo(var+8)(s0)
+; RV32IZCMP-NEXT:    sw a0, %lo(var+12)(s0)
 ; RV32IZCMP-NEXT:    lw a0, 84(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, %lo(var+4)(s0)
+; RV32IZCMP-NEXT:    sw a0, %lo(var+8)(s0)
 ; RV32IZCMP-NEXT:    lw a0, 88(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    sw a0, %lo(var+4)(s0)
+; RV32IZCMP-NEXT:    lw a0, 92(sp) # 4-byte Folded Reload
 ; RV32IZCMP-NEXT:    sw a0, %lo(var)(s0)
-; RV32IZCMP-NEXT:    addi sp, sp, 32
+; RV32IZCMP-NEXT:    addi sp, sp, 48
 ; RV32IZCMP-NEXT:    .cfi_def_cfa_offset 112
 ; RV32IZCMP-NEXT:    cm.popret {ra, s0-s11}, 112
 ;
@@ -2609,50 +2609,50 @@ define void @caller() {
 ; RV64IZCMP-NEXT:    .cfi_def_cfa_offset 288
 ; RV64IZCMP-NEXT:    lui s0, %hi(var)
 ; RV64IZCMP-NEXT:    lw a0, %lo(var)(s0)
-; RV64IZCMP-NEXT:    sd a0, 176(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, %lo(var+4)(s0)
 ; RV64IZCMP-NEXT:    sd a0, 168(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, %lo(var+8)(s0)
+; RV64IZCMP-NEXT:    lw a0, %lo(var+4)(s0)
 ; RV64IZCMP-NEXT:    sd a0, 160(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, %lo(var+12)(s0)
+; RV64IZCMP-NEXT:    lw a0, %lo(var+8)(s0)
 ; RV64IZCMP-NEXT:    sd a0, 152(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    lw a0, %lo(var+12)(s0)
+; RV64IZCMP-NEXT:    sd a0, 144(sp) # 8-byte Folded Spill
 ; RV64IZCMP-NEXT:    addi s1, s0, %lo(var)
 ; RV64IZCMP-NEXT:    lw a0, 16(s1)
-; RV64IZCMP-NEXT:    sd a0, 144(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, 20(s1)
 ; RV64IZCMP-NEXT:    sd a0, 136(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, 24(s1)
+; RV64IZCMP-NEXT:    lw a0, 20(s1)
 ; RV64IZCMP-NEXT:    sd a0, 128(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, 28(s1)
+; RV64IZCMP-NEXT:    lw a0, 24(s1)
 ; RV64IZCMP-NEXT:    sd a0, 120(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, 32(s1)
+; RV64IZCMP-NEXT:    lw a0, 28(s1)
 ; RV64IZCMP-NEXT:    sd a0, 112(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, 36(s1)
+; RV64IZCMP-NEXT:    lw a0, 32(s1)
 ; RV64IZCMP-NEXT:    sd a0, 104(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, 40(s1)
+; RV64IZCMP-NEXT:    lw a0, 36(s1)
 ; RV64IZCMP-NEXT:    sd a0, 96(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, 44(s1)
+; RV64IZCMP-NEXT:    lw a0, 40(s1)
 ; RV64IZCMP-NEXT:    sd a0, 88(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, 48(s1)
+; RV64IZCMP-NEXT:    lw a0, 44(s1)
 ; RV64IZCMP-NEXT:    sd a0, 80(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, 52(s1)
+; RV64IZCMP-NEXT:    lw a0, 48(s1)
 ; RV64IZCMP-NEXT:    sd a0, 72(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, 56(s1)
+; RV64IZCMP-NEXT:    lw a0, 52(s1)
 ; RV64IZCMP-NEXT:    sd a0, 64(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, 60(s1)
+; RV64IZCMP-NEXT:    lw a0, 56(s1)
 ; RV64IZCMP-NEXT:    sd a0, 56(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, 64(s1)
+; RV64IZCMP-NEXT:    lw a0, 60(s1)
 ; RV64IZCMP-NEXT:    sd a0, 48(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, 68(s1)
+; RV64IZCMP-NEXT:    lw a0, 64(s1)
 ; RV64IZCMP-NEXT:    sd a0, 40(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, 72(s1)
+; RV64IZCMP-NEXT:    lw a0, 68(s1)
 ; RV64IZCMP-NEXT:    sd a0, 32(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, 76(s1)
+; RV64IZCMP-NEXT:    lw a0, 72(s1)
 ; RV64IZCMP-NEXT:    sd a0, 24(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, 80(s1)
+; RV64IZCMP-NEXT:    lw a0, 76(s1)
 ; RV64IZCMP-NEXT:    sd a0, 16(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, 84(s1)
+; RV64IZCMP-NEXT:    lw a0, 80(s1)
 ; RV64IZCMP-NEXT:    sd a0, 8(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    lw a0, 84(s1)
+; RV64IZCMP-NEXT:    sd a0, 0(sp) # 8-byte Folded Spill
 ; RV64IZCMP-NEXT:    lw s4, 88(s1)
 ; RV64IZCMP-NEXT:    lw s5, 92(s1)
 ; RV64IZCMP-NEXT:    lw s6, 96(s1)
@@ -2674,49 +2674,49 @@ define void @caller() {
 ; RV64IZCMP-NEXT:    sw s6, 96(s1)
 ; RV64IZCMP-NEXT:    sw s5, 92(s1)
 ; RV64IZCMP-NEXT:    sw s4, 88(s1)
-; RV64IZCMP-NEXT:    ld a0, 8(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 0(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, 84(s1)
-; RV64IZCMP-NEXT:    ld a0, 16(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 8(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, 80(s1)
-; RV64IZCMP-NEXT:    ld a0, 24(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 16(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, 76(s1)
-; RV64IZCMP-NEXT:    ld a0, 32(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 24(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, 72(s1)
-; RV64IZCMP-NEXT:    ld a0, 40(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 32(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, 68(s1)
-; RV64IZCMP-NEXT:    ld a0, 48(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 40(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, 64(s1)
-; RV64IZCMP-NEXT:    ld a0, 56(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 48(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, 60(s1)
-; RV64IZCMP-NEXT:    ld a0, 64(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 56(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, 56(s1)
-; RV64IZCMP-NEXT:    ld a0, 72(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 64(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, 52(s1)
-; RV64IZCMP-NEXT:    ld a0, 80(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 72(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, 48(s1)
-; RV64IZCMP-NEXT:    ld a0, 88(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 80(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, 44(s1)
-; RV64IZCMP-NEXT:    ld a0, 96(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 88(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, 40(s1)
-; RV64IZCMP-NEXT:    ld a0, 104(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 96(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, 36(s1)
-; RV64IZCMP-NEXT:    ld a0, 112(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 104(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, 32(s1)
-; RV64IZCMP-NEXT:    ld a0, 120(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 112(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, 28(s1)
-; RV64IZCMP-NEXT:    ld a0, 128(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 120(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, 24(s1)
-; RV64IZCMP-NEXT:    ld a0, 136(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 128(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, 20(s1)
-; RV64IZCMP-NEXT:    ld a0, 144(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 136(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, 16(s1)
-; RV64IZCMP-NEXT:    ld a0, 152(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 144(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, %lo(var+12)(s0)
-; RV64IZCMP-NEXT:    ld a0, 160(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 152(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, %lo(var+8)(s0)
-; RV64IZCMP-NEXT:    ld a0, 168(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 160(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, %lo(var+4)(s0)
-; RV64IZCMP-NEXT:    ld a0, 176(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 168(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, %lo(var)(s0)
 ; RV64IZCMP-NEXT:    addi sp, sp, 128
 ; RV64IZCMP-NEXT:    .cfi_def_cfa_offset 160
diff --git a/llvm/test/CodeGen/RISCV/fold-mem-offset.mir b/llvm/test/CodeGen/RISCV/fold-mem-offset.mir
new file mode 100644
index 0000000000000..41afa26e70641
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/fold-mem-offset.mir
@@ -0,0 +1,43 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc %s -mtriple=riscv32 -run-pass=riscv-fold-mem-offset -verify-machineinstrs -o - | FileCheck %s
+
+---
+name:            crash
+tracksRegLiveness: true
+noPhis:          false
+isSSA:           true
+noVRegs:         false
+hasFakeUses:     false
+body:             |
+  bb.0:
+    liveins: $x10, $x11
+
+    ; CHECK-LABEL: name: crash
+    ; CHECK: liveins: $x10, $x11
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x11
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 3
+    ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD killed [[SLLI]], [[COPY1]]
+    ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 23
+    ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[ADD]], [[LUI]]
+    ; CHECK-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD [[ADD]], [[LUI]]
+    ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW killed [[ADD2]], 1792
+    ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW killed [[ADD1]], 1796
+    ; CHECK-NEXT: $x10 = COPY [[LW]]
+    ; CHECK-NEXT: $x11 = COPY [[LW1]]
+    ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
+    %1:gpr = COPY $x11
+    %0:gpr = COPY $x10
+    %3:gpr = SLLI %1, 3
+    %4:gpr = ADD killed %3, %0
+    %5:gpr = LUI 23
+    %6:gpr = ADDI %5, 1792
+    %7:gpr = ADD %4, killed %6
+    %8:gpr = ADD %4, %5
+    %9:gpr = LW killed %8, 1792
+    %10:gpr = LW killed %7, 4
+    $x10 = COPY %9
+    $x11 = COPY %10
+    PseudoRET implicit $x10, implicit $x11
+...
diff --git a/llvm/test/CodeGen/RISCV/pr101786.ll b/llvm/test/CodeGen/RISCV/pr101786.ll
new file mode 100644
index 0000000000000..6d0736edd3e89
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/pr101786.ll
@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=riscv64 -o - %s | FileCheck %s
+
+define i64 @test(i64 %x, ptr %p) {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mv a2, a0
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    bgtz a2, .LBB0_3
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    addi a3, a2, -1
+; CHECK-NEXT:    and a2, a2, a3
+; CHECK-NEXT:    bnez a2, .LBB0_3
+; CHECK-NEXT:  # %bb.2: # %if.else
+; CHECK-NEXT:    ld a0, 0(a1)
+; CHECK-NEXT:  .LBB0_3: # %if.end
+; CHECK-NEXT:    ret
+entry:
+  %ctpop = call i64 @llvm.ctpop.i64(i64 %x)
+  %cmp1 = icmp ugt i64 %ctpop, 1
+  %cmp2 = icmp sgt i64 %x, 0
+  %or = or i1 %cmp2, %cmp1
+  br i1 %or, label %if.end, label %if.else
+
+if.else:
+  %load = load i64, ptr %p, align 8
+  br label %if.end
+
+if.end:
+  %res = phi i64 [0, %entry], [%load, %if.else]
+  ret i64 %res
+}
diff --git a/llvm/test/CodeGen/RISCV/push-pop-popret.ll b/llvm/test/CodeGen/RISCV/push-pop-popret.ll
index 65f58d0ecbf24..8f9c97de7b911 100644
--- a/llvm/test/CodeGen/RISCV/push-pop-popret.ll
+++ b/llvm/test/CodeGen/RISCV/push-pop-popret.ll
@@ -24,7 +24,7 @@ define i32 @foo() {
 ; RV32IZCMP-NEXT:    .cfi_offset ra, -4
 ; RV32IZCMP-NEXT:    addi sp, sp, -464
 ; RV32IZCMP-NEXT:    .cfi_def_cfa_offset 528
-; RV32IZCMP-NEXT:    addi a0, sp, 12
+; RV32IZCMP-NEXT:    mv a0, sp
 ; RV32IZCMP-NEXT:    call test
 ; RV32IZCMP-NEXT:    addi sp, sp, 464
 ; RV32IZCMP-NEXT:    .cfi_def_cfa_offset 64
@@ -37,7 +37,7 @@ define i32 @foo() {
 ; RV64IZCMP-NEXT:    .cfi_offset ra, -8
 ; RV64IZCMP-NEXT:    addi sp, sp, -464
 ; RV64IZCMP-NEXT:    .cfi_def_cfa_offset 528
-; RV64IZCMP-NEXT:    addi a0, sp, 8
+; RV64IZCMP-NEXT:    mv a0, sp
 ; RV64IZCMP-NEXT:    call test
 ; RV64IZCMP-NEXT:    addi sp, sp, 464
 ; RV64IZCMP-NEXT:    .cfi_def_cfa_offset 64
@@ -50,7 +50,7 @@ define i32 @foo() {
 ; RV32IZCMP-SR-NEXT:    .cfi_offset ra, -4
 ; RV32IZCMP-SR-NEXT:    addi sp, sp, -464
 ; RV32IZCMP-SR-NEXT:    .cfi_def_cfa_offset 528
-; RV32IZCMP-SR-NEXT:    addi a0, sp, 12
+; RV32IZCMP-SR-NEXT:    mv a0, sp
 ; RV32IZCMP-SR-NEXT:    call test
 ; RV32IZCMP-SR-NEXT:    addi sp, sp, 464
 ; RV32IZCMP-SR-NEXT:    .cfi_def_cfa_offset 64
@@ -63,7 +63,7 @@ define i32 @foo() {
 ; RV64IZCMP-SR-NEXT:    .cfi_offset ra, -8
 ; RV64IZCMP-SR-NEXT:    addi sp, sp, -464
 ; RV64IZCMP-SR-NEXT:    .cfi_def_cfa_offset 528
-; RV64IZCMP-SR-NEXT:    addi a0, sp, 8
+; RV64IZCMP-SR-NEXT:    mv a0, sp
 ; RV64IZCMP-SR-NEXT:    call test
 ; RV64IZCMP-SR-NEXT:    addi sp, sp, 464
 ; RV64IZCMP-SR-NEXT:    .cfi_def_cfa_offset 64
@@ -1775,52 +1775,54 @@ define void @foo_with_irq() "interrupt"="machine" {
 ; RV32IZCMP-NEXT:    cm.push {ra}, -64
 ; RV32IZCMP-NEXT:    .cfi_def_cfa_offset 64
 ; RV32IZCMP-NEXT:    .cfi_offset ra, -4
-; RV32IZCMP-NEXT:    sw t0, 56(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw t1, 52(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw t2, 48(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw a0, 44(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw a1, 40(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw a2, 36(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw a3, 32(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw a4, 28(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw a5, 24(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw a6, 20(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw a7, 16(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw t3, 12(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw t4, 8(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw t5, 4(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw t6, 0(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    .cfi_offset t0, -8
-; RV32IZCMP-NEXT:    .cfi_offset t1, -12
-; RV32IZCMP-NEXT:    .cfi_offset t2, -16
-; RV32IZCMP-NEXT:    .cfi_offset a0, -20
-; RV32IZCMP-NEXT:    .cfi_offset a1, -24
-; RV32IZCMP-NEXT:    .cfi_offset a2, -28
-; RV32IZCMP-NEXT:    .cfi_offset a3, -32
-; RV32IZCMP-NEXT:    .cfi_offset a4, -36
-; RV32IZCMP-NEXT:    .cfi_offset a5, -40
-; RV32IZCMP-NEXT:    .cfi_offset a6, -44
-; RV32IZCMP-NEXT:    .cfi_offset a7, -48
-; RV32IZCMP-NEXT:    .cfi_offset t3, -52
-; RV32IZCMP-NEXT:    .cfi_offset t4, -56
-; RV32IZCMP-NEXT:    .cfi_offset t5, -60
-; RV32IZCMP-NEXT:    .cfi_offset t6, -64
+; RV32IZCMP-NEXT:    addi sp, sp, -16
+; RV32IZCMP-NEXT:    .cfi_def_cfa_offset 80
+; RV32IZCMP-NEXT:    sw t0, 60(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw t1, 56(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw t2, 52(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 48(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a1, 44(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a2, 40(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a3, 36(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a4, 32(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a5, 28(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a6, 24(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a7, 20(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw t3, 16(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw t4, 12(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw t5, 8(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw t6, 4(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    .cfi_offset t0, -20
+; RV32IZCMP-NEXT:    .cfi_offset t1, -24
+; RV32IZCMP-NEXT:    .cfi_offset t2, -28
+; RV32IZCMP-NEXT:    .cfi_offset a0, -32
+; RV32IZCMP-NEXT:    .cfi_offset a1, -36
+; RV32IZCMP-NEXT:    .cfi_offset a2, -40
+; RV32IZCMP-NEXT:    .cfi_offset a3, -44
+; RV32IZCMP-NEXT:    .cfi_offset a4, -48
+; RV32IZCMP-NEXT:    .cfi_offset a5, -52
+; RV32IZCMP-NEXT:    .cfi_offset a6, -56
+; RV32IZCMP-NEXT:    .cfi_offset a7, -60
+; RV32IZCMP-NEXT:    .cfi_offset t3, -64
+; RV32IZCMP-NEXT:    .cfi_offset t4, -68
+; RV32IZCMP-NEXT:    .cfi_offset t5, -72
+; RV32IZCMP-NEXT:    .cfi_offset t6, -76
 ; RV32IZCMP-NEXT:    call foo_test_irq
-; RV32IZCMP-NEXT:    lw t0, 56(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw t1, 52(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw t2, 48(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw a0, 44(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw a1, 40(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw a2, 36(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw a3, 32(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw a4, 28(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw a5, 24(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw a6, 20(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw a7, 16(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw t3, 12(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw t4, 8(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw t5, 4(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw t6, 0(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw t0, 60(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw t1, 56(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw t2, 52(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw a0, 48(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw a1, 44(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw a2, 40(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw a3, 36(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw a4, 32(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw a5, 28(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw a6, 24(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw a7, 20(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw t3, 16(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw t4, 12(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw t5, 8(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw t6, 4(sp) # 4-byte Folded Reload
 ; RV32IZCMP-NEXT:    .cfi_restore t0
 ; RV32IZCMP-NEXT:    .cfi_restore t1
 ; RV32IZCMP-NEXT:    .cfi_restore t2
@@ -1836,6 +1838,8 @@ define void @foo_with_irq() "interrupt"="machine" {
 ; RV32IZCMP-NEXT:    .cfi_restore t4
 ; RV32IZCMP-NEXT:    .cfi_restore t5
 ; RV32IZCMP-NEXT:    .cfi_restore t6
+; RV32IZCMP-NEXT:    addi sp, sp, 16
+; RV32IZCMP-NEXT:    .cfi_def_cfa_offset 64
 ; RV32IZCMP-NEXT:    cm.pop {ra}, 64
 ; RV32IZCMP-NEXT:    .cfi_restore ra
 ; RV32IZCMP-NEXT:    .cfi_def_cfa_offset 0
@@ -1846,54 +1850,54 @@ define void @foo_with_irq() "interrupt"="machine" {
 ; RV64IZCMP-NEXT:    cm.push {ra}, -64
 ; RV64IZCMP-NEXT:    .cfi_def_cfa_offset 64
 ; RV64IZCMP-NEXT:    .cfi_offset ra, -8
-; RV64IZCMP-NEXT:    addi sp, sp, -64
-; RV64IZCMP-NEXT:    .cfi_def_cfa_offset 128
-; RV64IZCMP-NEXT:    sd t0, 112(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd t1, 104(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd t2, 96(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd a0, 88(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd a1, 80(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd a2, 72(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd a3, 64(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd a4, 56(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd a5, 48(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd a6, 40(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd a7, 32(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd t3, 24(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd t4, 16(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd t5, 8(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd t6, 0(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    .cfi_offset t0, -16
-; RV64IZCMP-NEXT:    .cfi_offset t1, -24
-; RV64IZCMP-NEXT:    .cfi_offset t2, -32
-; RV64IZCMP-NEXT:    .cfi_offset a0, -40
-; RV64IZCMP-NEXT:    .cfi_offset a1, -48
-; RV64IZCMP-NEXT:    .cfi_offset a2, -56
-; RV64IZCMP-NEXT:    .cfi_offset a3, -64
-; RV64IZCMP-NEXT:    .cfi_offset a4, -72
-; RV64IZCMP-NEXT:    .cfi_offset a5, -80
-; RV64IZCMP-NEXT:    .cfi_offset a6, -88
-; RV64IZCMP-NEXT:    .cfi_offset a7, -96
-; RV64IZCMP-NEXT:    .cfi_offset t3, -104
-; RV64IZCMP-NEXT:    .cfi_offset t4, -112
-; RV64IZCMP-NEXT:    .cfi_offset t5, -120
-; RV64IZCMP-NEXT:    .cfi_offset t6, -128
+; RV64IZCMP-NEXT:    addi sp, sp, -80
+; RV64IZCMP-NEXT:    .cfi_def_cfa_offset 144
+; RV64IZCMP-NEXT:    sd t0, 120(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd t1, 112(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd t2, 104(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd a0, 96(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd a1, 88(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd a2, 80(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd a3, 72(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd a4, 64(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd a5, 56(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd a6, 48(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd a7, 40(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd t3, 32(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd t4, 24(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd t5, 16(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd t6, 8(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    .cfi_offset t0, -24
+; RV64IZCMP-NEXT:    .cfi_offset t1, -32
+; RV64IZCMP-NEXT:    .cfi_offset t2, -40
+; RV64IZCMP-NEXT:    .cfi_offset a0, -48
+; RV64IZCMP-NEXT:    .cfi_offset a1, -56
+; RV64IZCMP-NEXT:    .cfi_offset a2, -64
+; RV64IZCMP-NEXT:    .cfi_offset a3, -72
+; RV64IZCMP-NEXT:    .cfi_offset a4, -80
+; RV64IZCMP-NEXT:    .cfi_offset a5, -88
+; RV64IZCMP-NEXT:    .cfi_offset a6, -96
+; RV64IZCMP-NEXT:    .cfi_offset a7, -104
+; RV64IZCMP-NEXT:    .cfi_offset t3, -112
+; RV64IZCMP-NEXT:    .cfi_offset t4, -120
+; RV64IZCMP-NEXT:    .cfi_offset t5, -128
+; RV64IZCMP-NEXT:    .cfi_offset t6, -136
 ; RV64IZCMP-NEXT:    call foo_test_irq
-; RV64IZCMP-NEXT:    ld t0, 112(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld t1, 104(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld t2, 96(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld a0, 88(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld a1, 80(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld a2, 72(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld a3, 64(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld a4, 56(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld a5, 48(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld a6, 40(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld a7, 32(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld t3, 24(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld t4, 16(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld t5, 8(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld t6, 0(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld t0, 120(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld t1, 112(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld t2, 104(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 96(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a1, 88(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a2, 80(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a3, 72(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a4, 64(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a5, 56(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a6, 48(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a7, 40(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld t3, 32(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld t4, 24(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld t5, 16(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld t6, 8(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    .cfi_restore t0
 ; RV64IZCMP-NEXT:    .cfi_restore t1
 ; RV64IZCMP-NEXT:    .cfi_restore t2
@@ -1909,7 +1913,7 @@ define void @foo_with_irq() "interrupt"="machine" {
 ; RV64IZCMP-NEXT:    .cfi_restore t4
 ; RV64IZCMP-NEXT:    .cfi_restore t5
 ; RV64IZCMP-NEXT:    .cfi_restore t6
-; RV64IZCMP-NEXT:    addi sp, sp, 64
+; RV64IZCMP-NEXT:    addi sp, sp, 80
 ; RV64IZCMP-NEXT:    .cfi_def_cfa_offset 64
 ; RV64IZCMP-NEXT:    cm.pop {ra}, 64
 ; RV64IZCMP-NEXT:    .cfi_restore ra
@@ -1921,52 +1925,54 @@ define void @foo_with_irq() "interrupt"="machine" {
 ; RV32IZCMP-SR-NEXT:    cm.push {ra}, -64
 ; RV32IZCMP-SR-NEXT:    .cfi_def_cfa_offset 64
 ; RV32IZCMP-SR-NEXT:    .cfi_offset ra, -4
-; RV32IZCMP-SR-NEXT:    sw t0, 56(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw t1, 52(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw t2, 48(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw a0, 44(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw a1, 40(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw a2, 36(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw a3, 32(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw a4, 28(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw a5, 24(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw a6, 20(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw a7, 16(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw t3, 12(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw t4, 8(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw t5, 4(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw t6, 0(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    .cfi_offset t0, -8
-; RV32IZCMP-SR-NEXT:    .cfi_offset t1, -12
-; RV32IZCMP-SR-NEXT:    .cfi_offset t2, -16
-; RV32IZCMP-SR-NEXT:    .cfi_offset a0, -20
-; RV32IZCMP-SR-NEXT:    .cfi_offset a1, -24
-; RV32IZCMP-SR-NEXT:    .cfi_offset a2, -28
-; RV32IZCMP-SR-NEXT:    .cfi_offset a3, -32
-; RV32IZCMP-SR-NEXT:    .cfi_offset a4, -36
-; RV32IZCMP-SR-NEXT:    .cfi_offset a5, -40
-; RV32IZCMP-SR-NEXT:    .cfi_offset a6, -44
-; RV32IZCMP-SR-NEXT:    .cfi_offset a7, -48
-; RV32IZCMP-SR-NEXT:    .cfi_offset t3, -52
-; RV32IZCMP-SR-NEXT:    .cfi_offset t4, -56
-; RV32IZCMP-SR-NEXT:    .cfi_offset t5, -60
-; RV32IZCMP-SR-NEXT:    .cfi_offset t6, -64
+; RV32IZCMP-SR-NEXT:    addi sp, sp, -16
+; RV32IZCMP-SR-NEXT:    .cfi_def_cfa_offset 80
+; RV32IZCMP-SR-NEXT:    sw t0, 60(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw t1, 56(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw t2, 52(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a0, 48(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a1, 44(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a2, 40(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a3, 36(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a4, 32(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a5, 28(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a6, 24(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a7, 20(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw t3, 16(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw t4, 12(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw t5, 8(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw t6, 4(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    .cfi_offset t0, -20
+; RV32IZCMP-SR-NEXT:    .cfi_offset t1, -24
+; RV32IZCMP-SR-NEXT:    .cfi_offset t2, -28
+; RV32IZCMP-SR-NEXT:    .cfi_offset a0, -32
+; RV32IZCMP-SR-NEXT:    .cfi_offset a1, -36
+; RV32IZCMP-SR-NEXT:    .cfi_offset a2, -40
+; RV32IZCMP-SR-NEXT:    .cfi_offset a3, -44
+; RV32IZCMP-SR-NEXT:    .cfi_offset a4, -48
+; RV32IZCMP-SR-NEXT:    .cfi_offset a5, -52
+; RV32IZCMP-SR-NEXT:    .cfi_offset a6, -56
+; RV32IZCMP-SR-NEXT:    .cfi_offset a7, -60
+; RV32IZCMP-SR-NEXT:    .cfi_offset t3, -64
+; RV32IZCMP-SR-NEXT:    .cfi_offset t4, -68
+; RV32IZCMP-SR-NEXT:    .cfi_offset t5, -72
+; RV32IZCMP-SR-NEXT:    .cfi_offset t6, -76
 ; RV32IZCMP-SR-NEXT:    call foo_test_irq
-; RV32IZCMP-SR-NEXT:    lw t0, 56(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw t1, 52(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw t2, 48(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw a0, 44(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw a1, 40(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw a2, 36(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw a3, 32(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw a4, 28(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw a5, 24(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw a6, 20(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw a7, 16(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw t3, 12(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw t4, 8(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw t5, 4(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw t6, 0(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw t0, 60(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw t1, 56(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw t2, 52(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw a0, 48(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw a1, 44(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw a2, 40(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw a3, 36(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw a4, 32(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw a5, 28(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw a6, 24(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw a7, 20(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw t3, 16(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw t4, 12(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw t5, 8(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw t6, 4(sp) # 4-byte Folded Reload
 ; RV32IZCMP-SR-NEXT:    .cfi_restore t0
 ; RV32IZCMP-SR-NEXT:    .cfi_restore t1
 ; RV32IZCMP-SR-NEXT:    .cfi_restore t2
@@ -1982,6 +1988,8 @@ define void @foo_with_irq() "interrupt"="machine" {
 ; RV32IZCMP-SR-NEXT:    .cfi_restore t4
 ; RV32IZCMP-SR-NEXT:    .cfi_restore t5
 ; RV32IZCMP-SR-NEXT:    .cfi_restore t6
+; RV32IZCMP-SR-NEXT:    addi sp, sp, 16
+; RV32IZCMP-SR-NEXT:    .cfi_def_cfa_offset 64
 ; RV32IZCMP-SR-NEXT:    cm.pop {ra}, 64
 ; RV32IZCMP-SR-NEXT:    .cfi_restore ra
 ; RV32IZCMP-SR-NEXT:    .cfi_def_cfa_offset 0
@@ -1992,54 +2000,54 @@ define void @foo_with_irq() "interrupt"="machine" {
 ; RV64IZCMP-SR-NEXT:    cm.push {ra}, -64
 ; RV64IZCMP-SR-NEXT:    .cfi_def_cfa_offset 64
 ; RV64IZCMP-SR-NEXT:    .cfi_offset ra, -8
-; RV64IZCMP-SR-NEXT:    addi sp, sp, -64
-; RV64IZCMP-SR-NEXT:    .cfi_def_cfa_offset 128
-; RV64IZCMP-SR-NEXT:    sd t0, 112(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd t1, 104(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd t2, 96(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd a0, 88(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd a1, 80(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd a2, 72(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd a3, 64(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd a4, 56(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd a5, 48(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd a6, 40(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd a7, 32(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd t3, 24(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd t4, 16(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd t5, 8(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd t6, 0(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    .cfi_offset t0, -16
-; RV64IZCMP-SR-NEXT:    .cfi_offset t1, -24
-; RV64IZCMP-SR-NEXT:    .cfi_offset t2, -32
-; RV64IZCMP-SR-NEXT:    .cfi_offset a0, -40
-; RV64IZCMP-SR-NEXT:    .cfi_offset a1, -48
-; RV64IZCMP-SR-NEXT:    .cfi_offset a2, -56
-; RV64IZCMP-SR-NEXT:    .cfi_offset a3, -64
-; RV64IZCMP-SR-NEXT:    .cfi_offset a4, -72
-; RV64IZCMP-SR-NEXT:    .cfi_offset a5, -80
-; RV64IZCMP-SR-NEXT:    .cfi_offset a6, -88
-; RV64IZCMP-SR-NEXT:    .cfi_offset a7, -96
-; RV64IZCMP-SR-NEXT:    .cfi_offset t3, -104
-; RV64IZCMP-SR-NEXT:    .cfi_offset t4, -112
-; RV64IZCMP-SR-NEXT:    .cfi_offset t5, -120
-; RV64IZCMP-SR-NEXT:    .cfi_offset t6, -128
+; RV64IZCMP-SR-NEXT:    addi sp, sp, -80
+; RV64IZCMP-SR-NEXT:    .cfi_def_cfa_offset 144
+; RV64IZCMP-SR-NEXT:    sd t0, 120(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd t1, 112(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd t2, 104(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd a0, 96(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd a1, 88(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd a2, 80(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd a3, 72(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd a4, 64(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd a5, 56(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd a6, 48(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd a7, 40(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd t3, 32(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd t4, 24(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd t5, 16(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd t6, 8(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    .cfi_offset t0, -24
+; RV64IZCMP-SR-NEXT:    .cfi_offset t1, -32
+; RV64IZCMP-SR-NEXT:    .cfi_offset t2, -40
+; RV64IZCMP-SR-NEXT:    .cfi_offset a0, -48
+; RV64IZCMP-SR-NEXT:    .cfi_offset a1, -56
+; RV64IZCMP-SR-NEXT:    .cfi_offset a2, -64
+; RV64IZCMP-SR-NEXT:    .cfi_offset a3, -72
+; RV64IZCMP-SR-NEXT:    .cfi_offset a4, -80
+; RV64IZCMP-SR-NEXT:    .cfi_offset a5, -88
+; RV64IZCMP-SR-NEXT:    .cfi_offset a6, -96
+; RV64IZCMP-SR-NEXT:    .cfi_offset a7, -104
+; RV64IZCMP-SR-NEXT:    .cfi_offset t3, -112
+; RV64IZCMP-SR-NEXT:    .cfi_offset t4, -120
+; RV64IZCMP-SR-NEXT:    .cfi_offset t5, -128
+; RV64IZCMP-SR-NEXT:    .cfi_offset t6, -136
 ; RV64IZCMP-SR-NEXT:    call foo_test_irq
-; RV64IZCMP-SR-NEXT:    ld t0, 112(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld t1, 104(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld t2, 96(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld a0, 88(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld a1, 80(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld a2, 72(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld a3, 64(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld a4, 56(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld a5, 48(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld a6, 40(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld a7, 32(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld t3, 24(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld t4, 16(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld t5, 8(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld t6, 0(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld t0, 120(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld t1, 112(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld t2, 104(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld a0, 96(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld a1, 88(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld a2, 80(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld a3, 72(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld a4, 64(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld a5, 56(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld a6, 48(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld a7, 40(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld t3, 32(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld t4, 24(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld t5, 16(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld t6, 8(sp) # 8-byte Folded Reload
 ; RV64IZCMP-SR-NEXT:    .cfi_restore t0
 ; RV64IZCMP-SR-NEXT:    .cfi_restore t1
 ; RV64IZCMP-SR-NEXT:    .cfi_restore t2
@@ -2055,7 +2063,7 @@ define void @foo_with_irq() "interrupt"="machine" {
 ; RV64IZCMP-SR-NEXT:    .cfi_restore t4
 ; RV64IZCMP-SR-NEXT:    .cfi_restore t5
 ; RV64IZCMP-SR-NEXT:    .cfi_restore t6
-; RV64IZCMP-SR-NEXT:    addi sp, sp, 64
+; RV64IZCMP-SR-NEXT:    addi sp, sp, 80
 ; RV64IZCMP-SR-NEXT:    .cfi_def_cfa_offset 64
 ; RV64IZCMP-SR-NEXT:    cm.pop {ra}, 64
 ; RV64IZCMP-SR-NEXT:    .cfi_restore ra
@@ -2291,52 +2299,52 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV32IZCMP-NEXT:    .cfi_offset s9, -12
 ; RV32IZCMP-NEXT:    .cfi_offset s10, -8
 ; RV32IZCMP-NEXT:    .cfi_offset s11, -4
-; RV32IZCMP-NEXT:    addi sp, sp, -32
-; RV32IZCMP-NEXT:    .cfi_def_cfa_offset 144
-; RV32IZCMP-NEXT:    sw t0, 88(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw t1, 84(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw t2, 80(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw a0, 76(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw a1, 72(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw a2, 68(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw a3, 64(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw a4, 60(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw a5, 56(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw a6, 52(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw a7, 48(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw t3, 44(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw t4, 40(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw t5, 36(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    sw t6, 32(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT:    .cfi_offset t0, -56
-; RV32IZCMP-NEXT:    .cfi_offset t1, -60
-; RV32IZCMP-NEXT:    .cfi_offset t2, -64
-; RV32IZCMP-NEXT:    .cfi_offset a0, -68
-; RV32IZCMP-NEXT:    .cfi_offset a1, -72
-; RV32IZCMP-NEXT:    .cfi_offset a2, -76
-; RV32IZCMP-NEXT:    .cfi_offset a3, -80
-; RV32IZCMP-NEXT:    .cfi_offset a4, -84
-; RV32IZCMP-NEXT:    .cfi_offset a5, -88
-; RV32IZCMP-NEXT:    .cfi_offset a6, -92
-; RV32IZCMP-NEXT:    .cfi_offset a7, -96
-; RV32IZCMP-NEXT:    .cfi_offset t3, -100
-; RV32IZCMP-NEXT:    .cfi_offset t4, -104
-; RV32IZCMP-NEXT:    .cfi_offset t5, -108
-; RV32IZCMP-NEXT:    .cfi_offset t6, -112
+; RV32IZCMP-NEXT:    addi sp, sp, -48
+; RV32IZCMP-NEXT:    .cfi_def_cfa_offset 160
+; RV32IZCMP-NEXT:    sw t0, 92(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw t1, 88(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw t2, 84(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 80(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a1, 76(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a2, 72(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a3, 68(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a4, 64(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a5, 60(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a6, 56(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a7, 52(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw t3, 48(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw t4, 44(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw t5, 40(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw t6, 36(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    .cfi_offset t0, -68
+; RV32IZCMP-NEXT:    .cfi_offset t1, -72
+; RV32IZCMP-NEXT:    .cfi_offset t2, -76
+; RV32IZCMP-NEXT:    .cfi_offset a0, -80
+; RV32IZCMP-NEXT:    .cfi_offset a1, -84
+; RV32IZCMP-NEXT:    .cfi_offset a2, -88
+; RV32IZCMP-NEXT:    .cfi_offset a3, -92
+; RV32IZCMP-NEXT:    .cfi_offset a4, -96
+; RV32IZCMP-NEXT:    .cfi_offset a5, -100
+; RV32IZCMP-NEXT:    .cfi_offset a6, -104
+; RV32IZCMP-NEXT:    .cfi_offset a7, -108
+; RV32IZCMP-NEXT:    .cfi_offset t3, -112
+; RV32IZCMP-NEXT:    .cfi_offset t4, -116
+; RV32IZCMP-NEXT:    .cfi_offset t5, -120
+; RV32IZCMP-NEXT:    .cfi_offset t6, -124
 ; RV32IZCMP-NEXT:    lui t0, %hi(var_test_irq)
 ; RV32IZCMP-NEXT:    lw a0, %lo(var_test_irq)(t0)
-; RV32IZCMP-NEXT:    sw a0, 28(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 32(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, %lo(var_test_irq+4)(t0)
-; RV32IZCMP-NEXT:    sw a0, 24(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 28(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, %lo(var_test_irq+8)(t0)
-; RV32IZCMP-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 24(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, %lo(var_test_irq+12)(t0)
-; RV32IZCMP-NEXT:    sw a0, 16(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    addi a5, t0, %lo(var_test_irq)
 ; RV32IZCMP-NEXT:    lw a0, 16(a5)
-; RV32IZCMP-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 16(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, 20(a5)
-; RV32IZCMP-NEXT:    sw a0, 8(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw t4, 24(a5)
 ; RV32IZCMP-NEXT:    lw t5, 28(a5)
 ; RV32IZCMP-NEXT:    lw t6, 32(a5)
@@ -2389,33 +2397,33 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV32IZCMP-NEXT:    sw t6, 32(a5)
 ; RV32IZCMP-NEXT:    sw t5, 28(a5)
 ; RV32IZCMP-NEXT:    sw t4, 24(a5)
-; RV32IZCMP-NEXT:    lw a0, 8(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, 20(a5)
 ; RV32IZCMP-NEXT:    lw a0, 12(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, 16(a5)
+; RV32IZCMP-NEXT:    sw a0, 20(a5)
 ; RV32IZCMP-NEXT:    lw a0, 16(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
+; RV32IZCMP-NEXT:    sw a0, 16(a5)
 ; RV32IZCMP-NEXT:    lw a0, 20(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
+; RV32IZCMP-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
 ; RV32IZCMP-NEXT:    lw a0, 24(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
+; RV32IZCMP-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
 ; RV32IZCMP-NEXT:    lw a0, 28(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
+; RV32IZCMP-NEXT:    lw a0, 32(sp) # 4-byte Folded Reload
 ; RV32IZCMP-NEXT:    sw a0, %lo(var_test_irq)(t0)
-; RV32IZCMP-NEXT:    lw t0, 88(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw t1, 84(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw t2, 80(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw a0, 76(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw a1, 72(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw a2, 68(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw a3, 64(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw a4, 60(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw a5, 56(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw a6, 52(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw a7, 48(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw t3, 44(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw t4, 40(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw t5, 36(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    lw t6, 32(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw t0, 92(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw t1, 88(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw t2, 84(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw a0, 80(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw a1, 76(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw a2, 72(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw a3, 68(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw a4, 64(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw a5, 60(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw a6, 56(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw a7, 52(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw t3, 48(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw t4, 44(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw t5, 40(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    lw t6, 36(sp) # 4-byte Folded Reload
 ; RV32IZCMP-NEXT:    .cfi_restore t0
 ; RV32IZCMP-NEXT:    .cfi_restore t1
 ; RV32IZCMP-NEXT:    .cfi_restore t2
@@ -2431,7 +2439,7 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV32IZCMP-NEXT:    .cfi_restore t4
 ; RV32IZCMP-NEXT:    .cfi_restore t5
 ; RV32IZCMP-NEXT:    .cfi_restore t6
-; RV32IZCMP-NEXT:    addi sp, sp, 32
+; RV32IZCMP-NEXT:    addi sp, sp, 48
 ; RV32IZCMP-NEXT:    .cfi_def_cfa_offset 112
 ; RV32IZCMP-NEXT:    cm.pop {ra, s0-s11}, 112
 ; RV32IZCMP-NEXT:    .cfi_restore ra
@@ -2467,52 +2475,52 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV64IZCMP-NEXT:    .cfi_offset s9, -24
 ; RV64IZCMP-NEXT:    .cfi_offset s10, -16
 ; RV64IZCMP-NEXT:    .cfi_offset s11, -8
-; RV64IZCMP-NEXT:    addi sp, sp, -112
-; RV64IZCMP-NEXT:    .cfi_def_cfa_offset 272
-; RV64IZCMP-NEXT:    sd t0, 160(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd t1, 152(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd t2, 144(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd a0, 136(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd a1, 128(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd a2, 120(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd a3, 112(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd a4, 104(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd a5, 96(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd a6, 88(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd a7, 80(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd t3, 72(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd t4, 64(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd t5, 56(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    sd t6, 48(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    .cfi_offset t0, -112
-; RV64IZCMP-NEXT:    .cfi_offset t1, -120
-; RV64IZCMP-NEXT:    .cfi_offset t2, -128
-; RV64IZCMP-NEXT:    .cfi_offset a0, -136
-; RV64IZCMP-NEXT:    .cfi_offset a1, -144
-; RV64IZCMP-NEXT:    .cfi_offset a2, -152
-; RV64IZCMP-NEXT:    .cfi_offset a3, -160
-; RV64IZCMP-NEXT:    .cfi_offset a4, -168
-; RV64IZCMP-NEXT:    .cfi_offset a5, -176
-; RV64IZCMP-NEXT:    .cfi_offset a6, -184
-; RV64IZCMP-NEXT:    .cfi_offset a7, -192
-; RV64IZCMP-NEXT:    .cfi_offset t3, -200
-; RV64IZCMP-NEXT:    .cfi_offset t4, -208
-; RV64IZCMP-NEXT:    .cfi_offset t5, -216
-; RV64IZCMP-NEXT:    .cfi_offset t6, -224
+; RV64IZCMP-NEXT:    addi sp, sp, -128
+; RV64IZCMP-NEXT:    .cfi_def_cfa_offset 288
+; RV64IZCMP-NEXT:    sd t0, 168(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd t1, 160(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd t2, 152(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd a0, 144(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd a1, 136(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd a2, 128(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd a3, 120(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd a4, 112(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd a5, 104(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd a6, 96(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd a7, 88(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd t3, 80(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd t4, 72(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd t5, 64(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd t6, 56(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    .cfi_offset t0, -120
+; RV64IZCMP-NEXT:    .cfi_offset t1, -128
+; RV64IZCMP-NEXT:    .cfi_offset t2, -136
+; RV64IZCMP-NEXT:    .cfi_offset a0, -144
+; RV64IZCMP-NEXT:    .cfi_offset a1, -152
+; RV64IZCMP-NEXT:    .cfi_offset a2, -160
+; RV64IZCMP-NEXT:    .cfi_offset a3, -168
+; RV64IZCMP-NEXT:    .cfi_offset a4, -176
+; RV64IZCMP-NEXT:    .cfi_offset a5, -184
+; RV64IZCMP-NEXT:    .cfi_offset a6, -192
+; RV64IZCMP-NEXT:    .cfi_offset a7, -200
+; RV64IZCMP-NEXT:    .cfi_offset t3, -208
+; RV64IZCMP-NEXT:    .cfi_offset t4, -216
+; RV64IZCMP-NEXT:    .cfi_offset t5, -224
+; RV64IZCMP-NEXT:    .cfi_offset t6, -232
 ; RV64IZCMP-NEXT:    lui t0, %hi(var_test_irq)
 ; RV64IZCMP-NEXT:    lw a0, %lo(var_test_irq)(t0)
-; RV64IZCMP-NEXT:    sd a0, 40(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd a0, 48(sp) # 8-byte Folded Spill
 ; RV64IZCMP-NEXT:    lw a0, %lo(var_test_irq+4)(t0)
-; RV64IZCMP-NEXT:    sd a0, 32(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd a0, 40(sp) # 8-byte Folded Spill
 ; RV64IZCMP-NEXT:    lw a0, %lo(var_test_irq+8)(t0)
-; RV64IZCMP-NEXT:    sd a0, 24(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd a0, 32(sp) # 8-byte Folded Spill
 ; RV64IZCMP-NEXT:    lw a0, %lo(var_test_irq+12)(t0)
-; RV64IZCMP-NEXT:    sd a0, 16(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd a0, 24(sp) # 8-byte Folded Spill
 ; RV64IZCMP-NEXT:    addi a5, t0, %lo(var_test_irq)
 ; RV64IZCMP-NEXT:    lw a0, 16(a5)
-; RV64IZCMP-NEXT:    sd a0, 8(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd a0, 16(sp) # 8-byte Folded Spill
 ; RV64IZCMP-NEXT:    lw a0, 20(a5)
-; RV64IZCMP-NEXT:    sd a0, 0(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    sd a0, 8(sp) # 8-byte Folded Spill
 ; RV64IZCMP-NEXT:    lw t4, 24(a5)
 ; RV64IZCMP-NEXT:    lw t5, 28(a5)
 ; RV64IZCMP-NEXT:    lw t6, 32(a5)
@@ -2565,33 +2573,33 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV64IZCMP-NEXT:    sw t6, 32(a5)
 ; RV64IZCMP-NEXT:    sw t5, 28(a5)
 ; RV64IZCMP-NEXT:    sw t4, 24(a5)
-; RV64IZCMP-NEXT:    ld a0, 0(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    sw a0, 20(a5)
 ; RV64IZCMP-NEXT:    ld a0, 8(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    sw a0, 16(a5)
+; RV64IZCMP-NEXT:    sw a0, 20(a5)
 ; RV64IZCMP-NEXT:    ld a0, 16(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
+; RV64IZCMP-NEXT:    sw a0, 16(a5)
 ; RV64IZCMP-NEXT:    ld a0, 24(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
+; RV64IZCMP-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
 ; RV64IZCMP-NEXT:    ld a0, 32(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
+; RV64IZCMP-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
 ; RV64IZCMP-NEXT:    ld a0, 40(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
+; RV64IZCMP-NEXT:    ld a0, 48(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, %lo(var_test_irq)(t0)
-; RV64IZCMP-NEXT:    ld t0, 160(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld t1, 152(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld t2, 144(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld a0, 136(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld a1, 128(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld a2, 120(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld a3, 112(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld a4, 104(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld a5, 96(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld a6, 88(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld a7, 80(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld t3, 72(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld t4, 64(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld t5, 56(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT:    ld t6, 48(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld t0, 168(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld t1, 160(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld t2, 152(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 144(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a1, 136(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a2, 128(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a3, 120(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a4, 112(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a5, 104(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a6, 96(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a7, 88(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld t3, 80(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld t4, 72(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld t5, 64(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld t6, 56(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    .cfi_restore t0
 ; RV64IZCMP-NEXT:    .cfi_restore t1
 ; RV64IZCMP-NEXT:    .cfi_restore t2
@@ -2607,7 +2615,7 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV64IZCMP-NEXT:    .cfi_restore t4
 ; RV64IZCMP-NEXT:    .cfi_restore t5
 ; RV64IZCMP-NEXT:    .cfi_restore t6
-; RV64IZCMP-NEXT:    addi sp, sp, 112
+; RV64IZCMP-NEXT:    addi sp, sp, 128
 ; RV64IZCMP-NEXT:    .cfi_def_cfa_offset 160
 ; RV64IZCMP-NEXT:    cm.pop {ra, s0-s11}, 160
 ; RV64IZCMP-NEXT:    .cfi_restore ra
@@ -2643,52 +2651,52 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV32IZCMP-SR-NEXT:    .cfi_offset s9, -12
 ; RV32IZCMP-SR-NEXT:    .cfi_offset s10, -8
 ; RV32IZCMP-SR-NEXT:    .cfi_offset s11, -4
-; RV32IZCMP-SR-NEXT:    addi sp, sp, -32
-; RV32IZCMP-SR-NEXT:    .cfi_def_cfa_offset 144
-; RV32IZCMP-SR-NEXT:    sw t0, 88(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw t1, 84(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw t2, 80(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw a0, 76(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw a1, 72(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw a2, 68(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw a3, 64(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw a4, 60(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw a5, 56(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw a6, 52(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw a7, 48(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw t3, 44(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw t4, 40(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw t5, 36(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    sw t6, 32(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT:    .cfi_offset t0, -56
-; RV32IZCMP-SR-NEXT:    .cfi_offset t1, -60
-; RV32IZCMP-SR-NEXT:    .cfi_offset t2, -64
-; RV32IZCMP-SR-NEXT:    .cfi_offset a0, -68
-; RV32IZCMP-SR-NEXT:    .cfi_offset a1, -72
-; RV32IZCMP-SR-NEXT:    .cfi_offset a2, -76
-; RV32IZCMP-SR-NEXT:    .cfi_offset a3, -80
-; RV32IZCMP-SR-NEXT:    .cfi_offset a4, -84
-; RV32IZCMP-SR-NEXT:    .cfi_offset a5, -88
-; RV32IZCMP-SR-NEXT:    .cfi_offset a6, -92
-; RV32IZCMP-SR-NEXT:    .cfi_offset a7, -96
-; RV32IZCMP-SR-NEXT:    .cfi_offset t3, -100
-; RV32IZCMP-SR-NEXT:    .cfi_offset t4, -104
-; RV32IZCMP-SR-NEXT:    .cfi_offset t5, -108
-; RV32IZCMP-SR-NEXT:    .cfi_offset t6, -112
+; RV32IZCMP-SR-NEXT:    addi sp, sp, -48
+; RV32IZCMP-SR-NEXT:    .cfi_def_cfa_offset 160
+; RV32IZCMP-SR-NEXT:    sw t0, 92(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw t1, 88(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw t2, 84(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a0, 80(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a1, 76(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a2, 72(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a3, 68(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a4, 64(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a5, 60(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a6, 56(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a7, 52(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw t3, 48(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw t4, 44(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw t5, 40(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw t6, 36(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    .cfi_offset t0, -68
+; RV32IZCMP-SR-NEXT:    .cfi_offset t1, -72
+; RV32IZCMP-SR-NEXT:    .cfi_offset t2, -76
+; RV32IZCMP-SR-NEXT:    .cfi_offset a0, -80
+; RV32IZCMP-SR-NEXT:    .cfi_offset a1, -84
+; RV32IZCMP-SR-NEXT:    .cfi_offset a2, -88
+; RV32IZCMP-SR-NEXT:    .cfi_offset a3, -92
+; RV32IZCMP-SR-NEXT:    .cfi_offset a4, -96
+; RV32IZCMP-SR-NEXT:    .cfi_offset a5, -100
+; RV32IZCMP-SR-NEXT:    .cfi_offset a6, -104
+; RV32IZCMP-SR-NEXT:    .cfi_offset a7, -108
+; RV32IZCMP-SR-NEXT:    .cfi_offset t3, -112
+; RV32IZCMP-SR-NEXT:    .cfi_offset t4, -116
+; RV32IZCMP-SR-NEXT:    .cfi_offset t5, -120
+; RV32IZCMP-SR-NEXT:    .cfi_offset t6, -124
 ; RV32IZCMP-SR-NEXT:    lui t0, %hi(var_test_irq)
 ; RV32IZCMP-SR-NEXT:    lw a0, %lo(var_test_irq)(t0)
-; RV32IZCMP-SR-NEXT:    sw a0, 28(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a0, 32(sp) # 4-byte Folded Spill
 ; RV32IZCMP-SR-NEXT:    lw a0, %lo(var_test_irq+4)(t0)
-; RV32IZCMP-SR-NEXT:    sw a0, 24(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a0, 28(sp) # 4-byte Folded Spill
 ; RV32IZCMP-SR-NEXT:    lw a0, %lo(var_test_irq+8)(t0)
-; RV32IZCMP-SR-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a0, 24(sp) # 4-byte Folded Spill
 ; RV32IZCMP-SR-NEXT:    lw a0, %lo(var_test_irq+12)(t0)
-; RV32IZCMP-SR-NEXT:    sw a0, 16(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
 ; RV32IZCMP-SR-NEXT:    addi a5, t0, %lo(var_test_irq)
 ; RV32IZCMP-SR-NEXT:    lw a0, 16(a5)
-; RV32IZCMP-SR-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a0, 16(sp) # 4-byte Folded Spill
 ; RV32IZCMP-SR-NEXT:    lw a0, 20(a5)
-; RV32IZCMP-SR-NEXT:    sw a0, 8(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
 ; RV32IZCMP-SR-NEXT:    lw t4, 24(a5)
 ; RV32IZCMP-SR-NEXT:    lw t5, 28(a5)
 ; RV32IZCMP-SR-NEXT:    lw t6, 32(a5)
@@ -2741,33 +2749,33 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV32IZCMP-SR-NEXT:    sw t6, 32(a5)
 ; RV32IZCMP-SR-NEXT:    sw t5, 28(a5)
 ; RV32IZCMP-SR-NEXT:    sw t4, 24(a5)
-; RV32IZCMP-SR-NEXT:    lw a0, 8(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    sw a0, 20(a5)
 ; RV32IZCMP-SR-NEXT:    lw a0, 12(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    sw a0, 16(a5)
+; RV32IZCMP-SR-NEXT:    sw a0, 20(a5)
 ; RV32IZCMP-SR-NEXT:    lw a0, 16(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
+; RV32IZCMP-SR-NEXT:    sw a0, 16(a5)
 ; RV32IZCMP-SR-NEXT:    lw a0, 20(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
+; RV32IZCMP-SR-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
 ; RV32IZCMP-SR-NEXT:    lw a0, 24(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
+; RV32IZCMP-SR-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
 ; RV32IZCMP-SR-NEXT:    lw a0, 28(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
+; RV32IZCMP-SR-NEXT:    lw a0, 32(sp) # 4-byte Folded Reload
 ; RV32IZCMP-SR-NEXT:    sw a0, %lo(var_test_irq)(t0)
-; RV32IZCMP-SR-NEXT:    lw t0, 88(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw t1, 84(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw t2, 80(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw a0, 76(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw a1, 72(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw a2, 68(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw a3, 64(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw a4, 60(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw a5, 56(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw a6, 52(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw a7, 48(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw t3, 44(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw t4, 40(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw t5, 36(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    lw t6, 32(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw t0, 92(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw t1, 88(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw t2, 84(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw a0, 80(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw a1, 76(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw a2, 72(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw a3, 68(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw a4, 64(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw a5, 60(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw a6, 56(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw a7, 52(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw t3, 48(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw t4, 44(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw t5, 40(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    lw t6, 36(sp) # 4-byte Folded Reload
 ; RV32IZCMP-SR-NEXT:    .cfi_restore t0
 ; RV32IZCMP-SR-NEXT:    .cfi_restore t1
 ; RV32IZCMP-SR-NEXT:    .cfi_restore t2
@@ -2783,7 +2791,7 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV32IZCMP-SR-NEXT:    .cfi_restore t4
 ; RV32IZCMP-SR-NEXT:    .cfi_restore t5
 ; RV32IZCMP-SR-NEXT:    .cfi_restore t6
-; RV32IZCMP-SR-NEXT:    addi sp, sp, 32
+; RV32IZCMP-SR-NEXT:    addi sp, sp, 48
 ; RV32IZCMP-SR-NEXT:    .cfi_def_cfa_offset 112
 ; RV32IZCMP-SR-NEXT:    cm.pop {ra, s0-s11}, 112
 ; RV32IZCMP-SR-NEXT:    .cfi_restore ra
@@ -2819,52 +2827,52 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV64IZCMP-SR-NEXT:    .cfi_offset s9, -24
 ; RV64IZCMP-SR-NEXT:    .cfi_offset s10, -16
 ; RV64IZCMP-SR-NEXT:    .cfi_offset s11, -8
-; RV64IZCMP-SR-NEXT:    addi sp, sp, -112
-; RV64IZCMP-SR-NEXT:    .cfi_def_cfa_offset 272
-; RV64IZCMP-SR-NEXT:    sd t0, 160(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd t1, 152(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd t2, 144(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd a0, 136(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd a1, 128(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd a2, 120(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd a3, 112(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd a4, 104(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd a5, 96(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd a6, 88(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd a7, 80(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd t3, 72(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd t4, 64(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd t5, 56(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    sd t6, 48(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    .cfi_offset t0, -112
-; RV64IZCMP-SR-NEXT:    .cfi_offset t1, -120
-; RV64IZCMP-SR-NEXT:    .cfi_offset t2, -128
-; RV64IZCMP-SR-NEXT:    .cfi_offset a0, -136
-; RV64IZCMP-SR-NEXT:    .cfi_offset a1, -144
-; RV64IZCMP-SR-NEXT:    .cfi_offset a2, -152
-; RV64IZCMP-SR-NEXT:    .cfi_offset a3, -160
-; RV64IZCMP-SR-NEXT:    .cfi_offset a4, -168
-; RV64IZCMP-SR-NEXT:    .cfi_offset a5, -176
-; RV64IZCMP-SR-NEXT:    .cfi_offset a6, -184
-; RV64IZCMP-SR-NEXT:    .cfi_offset a7, -192
-; RV64IZCMP-SR-NEXT:    .cfi_offset t3, -200
-; RV64IZCMP-SR-NEXT:    .cfi_offset t4, -208
-; RV64IZCMP-SR-NEXT:    .cfi_offset t5, -216
-; RV64IZCMP-SR-NEXT:    .cfi_offset t6, -224
+; RV64IZCMP-SR-NEXT:    addi sp, sp, -128
+; RV64IZCMP-SR-NEXT:    .cfi_def_cfa_offset 288
+; RV64IZCMP-SR-NEXT:    sd t0, 168(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd t1, 160(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd t2, 152(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd a0, 144(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd a1, 136(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd a2, 128(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd a3, 120(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd a4, 112(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd a5, 104(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd a6, 96(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd a7, 88(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd t3, 80(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd t4, 72(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd t5, 64(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd t6, 56(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    .cfi_offset t0, -120
+; RV64IZCMP-SR-NEXT:    .cfi_offset t1, -128
+; RV64IZCMP-SR-NEXT:    .cfi_offset t2, -136
+; RV64IZCMP-SR-NEXT:    .cfi_offset a0, -144
+; RV64IZCMP-SR-NEXT:    .cfi_offset a1, -152
+; RV64IZCMP-SR-NEXT:    .cfi_offset a2, -160
+; RV64IZCMP-SR-NEXT:    .cfi_offset a3, -168
+; RV64IZCMP-SR-NEXT:    .cfi_offset a4, -176
+; RV64IZCMP-SR-NEXT:    .cfi_offset a5, -184
+; RV64IZCMP-SR-NEXT:    .cfi_offset a6, -192
+; RV64IZCMP-SR-NEXT:    .cfi_offset a7, -200
+; RV64IZCMP-SR-NEXT:    .cfi_offset t3, -208
+; RV64IZCMP-SR-NEXT:    .cfi_offset t4, -216
+; RV64IZCMP-SR-NEXT:    .cfi_offset t5, -224
+; RV64IZCMP-SR-NEXT:    .cfi_offset t6, -232
 ; RV64IZCMP-SR-NEXT:    lui t0, %hi(var_test_irq)
 ; RV64IZCMP-SR-NEXT:    lw a0, %lo(var_test_irq)(t0)
-; RV64IZCMP-SR-NEXT:    sd a0, 40(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd a0, 48(sp) # 8-byte Folded Spill
 ; RV64IZCMP-SR-NEXT:    lw a0, %lo(var_test_irq+4)(t0)
-; RV64IZCMP-SR-NEXT:    sd a0, 32(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd a0, 40(sp) # 8-byte Folded Spill
 ; RV64IZCMP-SR-NEXT:    lw a0, %lo(var_test_irq+8)(t0)
-; RV64IZCMP-SR-NEXT:    sd a0, 24(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd a0, 32(sp) # 8-byte Folded Spill
 ; RV64IZCMP-SR-NEXT:    lw a0, %lo(var_test_irq+12)(t0)
-; RV64IZCMP-SR-NEXT:    sd a0, 16(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd a0, 24(sp) # 8-byte Folded Spill
 ; RV64IZCMP-SR-NEXT:    addi a5, t0, %lo(var_test_irq)
 ; RV64IZCMP-SR-NEXT:    lw a0, 16(a5)
-; RV64IZCMP-SR-NEXT:    sd a0, 8(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd a0, 16(sp) # 8-byte Folded Spill
 ; RV64IZCMP-SR-NEXT:    lw a0, 20(a5)
-; RV64IZCMP-SR-NEXT:    sd a0, 0(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    sd a0, 8(sp) # 8-byte Folded Spill
 ; RV64IZCMP-SR-NEXT:    lw t4, 24(a5)
 ; RV64IZCMP-SR-NEXT:    lw t5, 28(a5)
 ; RV64IZCMP-SR-NEXT:    lw t6, 32(a5)
@@ -2917,33 +2925,33 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV64IZCMP-SR-NEXT:    sw t6, 32(a5)
 ; RV64IZCMP-SR-NEXT:    sw t5, 28(a5)
 ; RV64IZCMP-SR-NEXT:    sw t4, 24(a5)
-; RV64IZCMP-SR-NEXT:    ld a0, 0(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    sw a0, 20(a5)
 ; RV64IZCMP-SR-NEXT:    ld a0, 8(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    sw a0, 16(a5)
+; RV64IZCMP-SR-NEXT:    sw a0, 20(a5)
 ; RV64IZCMP-SR-NEXT:    ld a0, 16(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
+; RV64IZCMP-SR-NEXT:    sw a0, 16(a5)
 ; RV64IZCMP-SR-NEXT:    ld a0, 24(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
+; RV64IZCMP-SR-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
 ; RV64IZCMP-SR-NEXT:    ld a0, 32(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
+; RV64IZCMP-SR-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
 ; RV64IZCMP-SR-NEXT:    ld a0, 40(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
+; RV64IZCMP-SR-NEXT:    ld a0, 48(sp) # 8-byte Folded Reload
 ; RV64IZCMP-SR-NEXT:    sw a0, %lo(var_test_irq)(t0)
-; RV64IZCMP-SR-NEXT:    ld t0, 160(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld t1, 152(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld t2, 144(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld a0, 136(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld a1, 128(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld a2, 120(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld a3, 112(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld a4, 104(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld a5, 96(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld a6, 88(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld a7, 80(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld t3, 72(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld t4, 64(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld t5, 56(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT:    ld t6, 48(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld t0, 168(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld t1, 160(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld t2, 152(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld a0, 144(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld a1, 136(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld a2, 128(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld a3, 120(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld a4, 112(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld a5, 104(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld a6, 96(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld a7, 88(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld t3, 80(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld t4, 72(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld t5, 64(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld t6, 56(sp) # 8-byte Folded Reload
 ; RV64IZCMP-SR-NEXT:    .cfi_restore t0
 ; RV64IZCMP-SR-NEXT:    .cfi_restore t1
 ; RV64IZCMP-SR-NEXT:    .cfi_restore t2
@@ -2959,7 +2967,7 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV64IZCMP-SR-NEXT:    .cfi_restore t4
 ; RV64IZCMP-SR-NEXT:    .cfi_restore t5
 ; RV64IZCMP-SR-NEXT:    .cfi_restore t6
-; RV64IZCMP-SR-NEXT:    addi sp, sp, 112
+; RV64IZCMP-SR-NEXT:    addi sp, sp, 128
 ; RV64IZCMP-SR-NEXT:    .cfi_def_cfa_offset 160
 ; RV64IZCMP-SR-NEXT:    cm.pop {ra, s0-s11}, 160
 ; RV64IZCMP-SR-NEXT:    .cfi_restore ra
@@ -3381,8 +3389,8 @@ define void @callee_with_irq() "interrupt"="machine" {
 define void @callee_no_irq() {
 ; RV32IZCMP-LABEL: callee_no_irq:
 ; RV32IZCMP:       # %bb.0:
-; RV32IZCMP-NEXT:    cm.push {ra, s0-s11}, -80
-; RV32IZCMP-NEXT:    .cfi_def_cfa_offset 80
+; RV32IZCMP-NEXT:    cm.push {ra, s0-s11}, -96
+; RV32IZCMP-NEXT:    .cfi_def_cfa_offset 96
 ; RV32IZCMP-NEXT:    .cfi_offset ra, -52
 ; RV32IZCMP-NEXT:    .cfi_offset s0, -48
 ; RV32IZCMP-NEXT:    .cfi_offset s1, -44
@@ -3398,18 +3406,18 @@ define void @callee_no_irq() {
 ; RV32IZCMP-NEXT:    .cfi_offset s11, -4
 ; RV32IZCMP-NEXT:    lui t0, %hi(var_test_irq)
 ; RV32IZCMP-NEXT:    lw a0, %lo(var_test_irq)(t0)
-; RV32IZCMP-NEXT:    sw a0, 24(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 28(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, %lo(var_test_irq+4)(t0)
-; RV32IZCMP-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 24(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, %lo(var_test_irq+8)(t0)
-; RV32IZCMP-NEXT:    sw a0, 16(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, %lo(var_test_irq+12)(t0)
-; RV32IZCMP-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 16(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    addi a5, t0, %lo(var_test_irq)
 ; RV32IZCMP-NEXT:    lw a0, 16(a5)
-; RV32IZCMP-NEXT:    sw a0, 8(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw a0, 20(a5)
-; RV32IZCMP-NEXT:    sw a0, 4(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT:    sw a0, 8(sp) # 4-byte Folded Spill
 ; RV32IZCMP-NEXT:    lw t4, 24(a5)
 ; RV32IZCMP-NEXT:    lw t5, 28(a5)
 ; RV32IZCMP-NEXT:    lw t6, 32(a5)
@@ -3462,19 +3470,19 @@ define void @callee_no_irq() {
 ; RV32IZCMP-NEXT:    sw t6, 32(a5)
 ; RV32IZCMP-NEXT:    sw t5, 28(a5)
 ; RV32IZCMP-NEXT:    sw t4, 24(a5)
-; RV32IZCMP-NEXT:    lw a0, 4(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, 20(a5)
 ; RV32IZCMP-NEXT:    lw a0, 8(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, 16(a5)
+; RV32IZCMP-NEXT:    sw a0, 20(a5)
 ; RV32IZCMP-NEXT:    lw a0, 12(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
+; RV32IZCMP-NEXT:    sw a0, 16(a5)
 ; RV32IZCMP-NEXT:    lw a0, 16(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
+; RV32IZCMP-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
 ; RV32IZCMP-NEXT:    lw a0, 20(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
+; RV32IZCMP-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
 ; RV32IZCMP-NEXT:    lw a0, 24(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
+; RV32IZCMP-NEXT:    lw a0, 28(sp) # 4-byte Folded Reload
 ; RV32IZCMP-NEXT:    sw a0, %lo(var_test_irq)(t0)
-; RV32IZCMP-NEXT:    cm.popret {ra, s0-s11}, 80
+; RV32IZCMP-NEXT:    cm.popret {ra, s0-s11}, 96
 ;
 ; RV64IZCMP-LABEL: callee_no_irq:
 ; RV64IZCMP:       # %bb.0:
@@ -3495,18 +3503,18 @@ define void @callee_no_irq() {
 ; RV64IZCMP-NEXT:    .cfi_offset s11, -8
 ; RV64IZCMP-NEXT:    lui t0, %hi(var_test_irq)
 ; RV64IZCMP-NEXT:    lw a0, %lo(var_test_irq)(t0)
-; RV64IZCMP-NEXT:    sd a0, 48(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, %lo(var_test_irq+4)(t0)
 ; RV64IZCMP-NEXT:    sd a0, 40(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, %lo(var_test_irq+8)(t0)
+; RV64IZCMP-NEXT:    lw a0, %lo(var_test_irq+4)(t0)
 ; RV64IZCMP-NEXT:    sd a0, 32(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, %lo(var_test_irq+12)(t0)
+; RV64IZCMP-NEXT:    lw a0, %lo(var_test_irq+8)(t0)
 ; RV64IZCMP-NEXT:    sd a0, 24(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    lw a0, %lo(var_test_irq+12)(t0)
+; RV64IZCMP-NEXT:    sd a0, 16(sp) # 8-byte Folded Spill
 ; RV64IZCMP-NEXT:    addi a5, t0, %lo(var_test_irq)
 ; RV64IZCMP-NEXT:    lw a0, 16(a5)
-; RV64IZCMP-NEXT:    sd a0, 16(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT:    lw a0, 20(a5)
 ; RV64IZCMP-NEXT:    sd a0, 8(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT:    lw a0, 20(a5)
+; RV64IZCMP-NEXT:    sd a0, 0(sp) # 8-byte Folded Spill
 ; RV64IZCMP-NEXT:    lw t4, 24(a5)
 ; RV64IZCMP-NEXT:    lw t5, 28(a5)
 ; RV64IZCMP-NEXT:    lw t6, 32(a5)
@@ -3559,24 +3567,24 @@ define void @callee_no_irq() {
 ; RV64IZCMP-NEXT:    sw t6, 32(a5)
 ; RV64IZCMP-NEXT:    sw t5, 28(a5)
 ; RV64IZCMP-NEXT:    sw t4, 24(a5)
-; RV64IZCMP-NEXT:    ld a0, 8(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 0(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, 20(a5)
-; RV64IZCMP-NEXT:    ld a0, 16(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 8(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, 16(a5)
-; RV64IZCMP-NEXT:    ld a0, 24(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 16(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
-; RV64IZCMP-NEXT:    ld a0, 32(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 24(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
-; RV64IZCMP-NEXT:    ld a0, 40(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 32(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
-; RV64IZCMP-NEXT:    ld a0, 48(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT:    ld a0, 40(sp) # 8-byte Folded Reload
 ; RV64IZCMP-NEXT:    sw a0, %lo(var_test_irq)(t0)
 ; RV64IZCMP-NEXT:    cm.popret {ra, s0-s11}, 160
 ;
 ; RV32IZCMP-SR-LABEL: callee_no_irq:
 ; RV32IZCMP-SR:       # %bb.0:
-; RV32IZCMP-SR-NEXT:    cm.push {ra, s0-s11}, -80
-; RV32IZCMP-SR-NEXT:    .cfi_def_cfa_offset 80
+; RV32IZCMP-SR-NEXT:    cm.push {ra, s0-s11}, -96
+; RV32IZCMP-SR-NEXT:    .cfi_def_cfa_offset 96
 ; RV32IZCMP-SR-NEXT:    .cfi_offset ra, -52
 ; RV32IZCMP-SR-NEXT:    .cfi_offset s0, -48
 ; RV32IZCMP-SR-NEXT:    .cfi_offset s1, -44
@@ -3592,18 +3600,18 @@ define void @callee_no_irq() {
 ; RV32IZCMP-SR-NEXT:    .cfi_offset s11, -4
 ; RV32IZCMP-SR-NEXT:    lui t0, %hi(var_test_irq)
 ; RV32IZCMP-SR-NEXT:    lw a0, %lo(var_test_irq)(t0)
-; RV32IZCMP-SR-NEXT:    sw a0, 24(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a0, 28(sp) # 4-byte Folded Spill
 ; RV32IZCMP-SR-NEXT:    lw a0, %lo(var_test_irq+4)(t0)
-; RV32IZCMP-SR-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a0, 24(sp) # 4-byte Folded Spill
 ; RV32IZCMP-SR-NEXT:    lw a0, %lo(var_test_irq+8)(t0)
-; RV32IZCMP-SR-NEXT:    sw a0, 16(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
 ; RV32IZCMP-SR-NEXT:    lw a0, %lo(var_test_irq+12)(t0)
-; RV32IZCMP-SR-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a0, 16(sp) # 4-byte Folded Spill
 ; RV32IZCMP-SR-NEXT:    addi a5, t0, %lo(var_test_irq)
 ; RV32IZCMP-SR-NEXT:    lw a0, 16(a5)
-; RV32IZCMP-SR-NEXT:    sw a0, 8(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
 ; RV32IZCMP-SR-NEXT:    lw a0, 20(a5)
-; RV32IZCMP-SR-NEXT:    sw a0, 4(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT:    sw a0, 8(sp) # 4-byte Folded Spill
 ; RV32IZCMP-SR-NEXT:    lw t4, 24(a5)
 ; RV32IZCMP-SR-NEXT:    lw t5, 28(a5)
 ; RV32IZCMP-SR-NEXT:    lw t6, 32(a5)
@@ -3656,19 +3664,19 @@ define void @callee_no_irq() {
 ; RV32IZCMP-SR-NEXT:    sw t6, 32(a5)
 ; RV32IZCMP-SR-NEXT:    sw t5, 28(a5)
 ; RV32IZCMP-SR-NEXT:    sw t4, 24(a5)
-; RV32IZCMP-SR-NEXT:    lw a0, 4(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    sw a0, 20(a5)
 ; RV32IZCMP-SR-NEXT:    lw a0, 8(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    sw a0, 16(a5)
+; RV32IZCMP-SR-NEXT:    sw a0, 20(a5)
 ; RV32IZCMP-SR-NEXT:    lw a0, 12(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
+; RV32IZCMP-SR-NEXT:    sw a0, 16(a5)
 ; RV32IZCMP-SR-NEXT:    lw a0, 16(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
+; RV32IZCMP-SR-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
 ; RV32IZCMP-SR-NEXT:    lw a0, 20(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
+; RV32IZCMP-SR-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
 ; RV32IZCMP-SR-NEXT:    lw a0, 24(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
+; RV32IZCMP-SR-NEXT:    lw a0, 28(sp) # 4-byte Folded Reload
 ; RV32IZCMP-SR-NEXT:    sw a0, %lo(var_test_irq)(t0)
-; RV32IZCMP-SR-NEXT:    cm.popret {ra, s0-s11}, 80
+; RV32IZCMP-SR-NEXT:    cm.popret {ra, s0-s11}, 96
 ;
 ; RV64IZCMP-SR-LABEL: callee_no_irq:
 ; RV64IZCMP-SR:       # %bb.0:
@@ -3689,18 +3697,18 @@ define void @callee_no_irq() {
 ; RV64IZCMP-SR-NEXT:    .cfi_offset s11, -8
 ; RV64IZCMP-SR-NEXT:    lui t0, %hi(var_test_irq)
 ; RV64IZCMP-SR-NEXT:    lw a0, %lo(var_test_irq)(t0)
-; RV64IZCMP-SR-NEXT:    sd a0, 48(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    lw a0, %lo(var_test_irq+4)(t0)
 ; RV64IZCMP-SR-NEXT:    sd a0, 40(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    lw a0, %lo(var_test_irq+8)(t0)
+; RV64IZCMP-SR-NEXT:    lw a0, %lo(var_test_irq+4)(t0)
 ; RV64IZCMP-SR-NEXT:    sd a0, 32(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    lw a0, %lo(var_test_irq+12)(t0)
+; RV64IZCMP-SR-NEXT:    lw a0, %lo(var_test_irq+8)(t0)
 ; RV64IZCMP-SR-NEXT:    sd a0, 24(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    lw a0, %lo(var_test_irq+12)(t0)
+; RV64IZCMP-SR-NEXT:    sd a0, 16(sp) # 8-byte Folded Spill
 ; RV64IZCMP-SR-NEXT:    addi a5, t0, %lo(var_test_irq)
 ; RV64IZCMP-SR-NEXT:    lw a0, 16(a5)
-; RV64IZCMP-SR-NEXT:    sd a0, 16(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT:    lw a0, 20(a5)
 ; RV64IZCMP-SR-NEXT:    sd a0, 8(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT:    lw a0, 20(a5)
+; RV64IZCMP-SR-NEXT:    sd a0, 0(sp) # 8-byte Folded Spill
 ; RV64IZCMP-SR-NEXT:    lw t4, 24(a5)
 ; RV64IZCMP-SR-NEXT:    lw t5, 28(a5)
 ; RV64IZCMP-SR-NEXT:    lw t6, 32(a5)
@@ -3753,17 +3761,17 @@ define void @callee_no_irq() {
 ; RV64IZCMP-SR-NEXT:    sw t6, 32(a5)
 ; RV64IZCMP-SR-NEXT:    sw t5, 28(a5)
 ; RV64IZCMP-SR-NEXT:    sw t4, 24(a5)
-; RV64IZCMP-SR-NEXT:    ld a0, 8(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld a0, 0(sp) # 8-byte Folded Reload
 ; RV64IZCMP-SR-NEXT:    sw a0, 20(a5)
-; RV64IZCMP-SR-NEXT:    ld a0, 16(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld a0, 8(sp) # 8-byte Folded Reload
 ; RV64IZCMP-SR-NEXT:    sw a0, 16(a5)
-; RV64IZCMP-SR-NEXT:    ld a0, 24(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld a0, 16(sp) # 8-byte Folded Reload
 ; RV64IZCMP-SR-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
-; RV64IZCMP-SR-NEXT:    ld a0, 32(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld a0, 24(sp) # 8-byte Folded Reload
 ; RV64IZCMP-SR-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
-; RV64IZCMP-SR-NEXT:    ld a0, 40(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld a0, 32(sp) # 8-byte Folded Reload
 ; RV64IZCMP-SR-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
-; RV64IZCMP-SR-NEXT:    ld a0, 48(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT:    ld a0, 40(sp) # 8-byte Folded Reload
 ; RV64IZCMP-SR-NEXT:    sw a0, %lo(var_test_irq)(t0)
 ; RV64IZCMP-SR-NEXT:    cm.popret {ra, s0-s11}, 160
 ;
@@ -4053,71 +4061,71 @@ declare ptr @llvm.frameaddress.p0(i32 immarg)
 define i32 @use_fp(i32 %x) {
 ; RV32IZCMP-LABEL: use_fp:
 ; RV32IZCMP:       # %bb.0: # %entry
-; RV32IZCMP-NEXT:    cm.push {ra, s0-s1}, -16
-; RV32IZCMP-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZCMP-NEXT:    cm.push {ra, s0-s1}, -32
+; RV32IZCMP-NEXT:    .cfi_def_cfa_offset 32
 ; RV32IZCMP-NEXT:    .cfi_offset ra, -12
 ; RV32IZCMP-NEXT:    .cfi_offset s0, -8
 ; RV32IZCMP-NEXT:    .cfi_offset s1, -4
-; RV32IZCMP-NEXT:    addi s0, sp, 16
+; RV32IZCMP-NEXT:    addi s0, sp, 32
 ; RV32IZCMP-NEXT:    .cfi_def_cfa s0, 0
 ; RV32IZCMP-NEXT:    mv s1, a0
-; RV32IZCMP-NEXT:    addi a1, s0, -16
+; RV32IZCMP-NEXT:    addi a1, s0, -20
 ; RV32IZCMP-NEXT:    mv a0, s0
 ; RV32IZCMP-NEXT:    call bar
 ; RV32IZCMP-NEXT:    mv a0, s1
-; RV32IZCMP-NEXT:    .cfi_def_cfa sp, 16
-; RV32IZCMP-NEXT:    cm.popret {ra, s0-s1}, 16
+; RV32IZCMP-NEXT:    .cfi_def_cfa sp, 32
+; RV32IZCMP-NEXT:    cm.popret {ra, s0-s1}, 32
 ;
 ; RV64IZCMP-LABEL: use_fp:
 ; RV64IZCMP:       # %bb.0: # %entry
-; RV64IZCMP-NEXT:    cm.push {ra, s0-s1}, -32
-; RV64IZCMP-NEXT:    .cfi_def_cfa_offset 32
+; RV64IZCMP-NEXT:    cm.push {ra, s0-s1}, -48
+; RV64IZCMP-NEXT:    .cfi_def_cfa_offset 48
 ; RV64IZCMP-NEXT:    .cfi_offset ra, -24
 ; RV64IZCMP-NEXT:    .cfi_offset s0, -16
 ; RV64IZCMP-NEXT:    .cfi_offset s1, -8
-; RV64IZCMP-NEXT:    addi s0, sp, 32
+; RV64IZCMP-NEXT:    addi s0, sp, 48
 ; RV64IZCMP-NEXT:    .cfi_def_cfa s0, 0
 ; RV64IZCMP-NEXT:    mv s1, a0
-; RV64IZCMP-NEXT:    addi a1, s0, -28
+; RV64IZCMP-NEXT:    addi a1, s0, -36
 ; RV64IZCMP-NEXT:    mv a0, s0
 ; RV64IZCMP-NEXT:    call bar
 ; RV64IZCMP-NEXT:    mv a0, s1
-; RV64IZCMP-NEXT:    .cfi_def_cfa sp, 32
-; RV64IZCMP-NEXT:    cm.popret {ra, s0-s1}, 32
+; RV64IZCMP-NEXT:    .cfi_def_cfa sp, 48
+; RV64IZCMP-NEXT:    cm.popret {ra, s0-s1}, 48
 ;
 ; RV32IZCMP-SR-LABEL: use_fp:
 ; RV32IZCMP-SR:       # %bb.0: # %entry
-; RV32IZCMP-SR-NEXT:    cm.push {ra, s0-s1}, -16
-; RV32IZCMP-SR-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZCMP-SR-NEXT:    cm.push {ra, s0-s1}, -32
+; RV32IZCMP-SR-NEXT:    .cfi_def_cfa_offset 32
 ; RV32IZCMP-SR-NEXT:    .cfi_offset ra, -12
 ; RV32IZCMP-SR-NEXT:    .cfi_offset s0, -8
 ; RV32IZCMP-SR-NEXT:    .cfi_offset s1, -4
-; RV32IZCMP-SR-NEXT:    addi s0, sp, 16
+; RV32IZCMP-SR-NEXT:    addi s0, sp, 32
 ; RV32IZCMP-SR-NEXT:    .cfi_def_cfa s0, 0
 ; RV32IZCMP-SR-NEXT:    mv s1, a0
-; RV32IZCMP-SR-NEXT:    addi a1, s0, -16
+; RV32IZCMP-SR-NEXT:    addi a1, s0, -20
 ; RV32IZCMP-SR-NEXT:    mv a0, s0
 ; RV32IZCMP-SR-NEXT:    call bar
 ; RV32IZCMP-SR-NEXT:    mv a0, s1
-; RV32IZCMP-SR-NEXT:    .cfi_def_cfa sp, 16
-; RV32IZCMP-SR-NEXT:    cm.popret {ra, s0-s1}, 16
+; RV32IZCMP-SR-NEXT:    .cfi_def_cfa sp, 32
+; RV32IZCMP-SR-NEXT:    cm.popret {ra, s0-s1}, 32
 ;
 ; RV64IZCMP-SR-LABEL: use_fp:
 ; RV64IZCMP-SR:       # %bb.0: # %entry
-; RV64IZCMP-SR-NEXT:    cm.push {ra, s0-s1}, -32
-; RV64IZCMP-SR-NEXT:    .cfi_def_cfa_offset 32
+; RV64IZCMP-SR-NEXT:    cm.push {ra, s0-s1}, -48
+; RV64IZCMP-SR-NEXT:    .cfi_def_cfa_offset 48
 ; RV64IZCMP-SR-NEXT:    .cfi_offset ra, -24
 ; RV64IZCMP-SR-NEXT:    .cfi_offset s0, -16
 ; RV64IZCMP-SR-NEXT:    .cfi_offset s1, -8
-; RV64IZCMP-SR-NEXT:    addi s0, sp, 32
+; RV64IZCMP-SR-NEXT:    addi s0, sp, 48
 ; RV64IZCMP-SR-NEXT:    .cfi_def_cfa s0, 0
 ; RV64IZCMP-SR-NEXT:    mv s1, a0
-; RV64IZCMP-SR-NEXT:    addi a1, s0, -28
+; RV64IZCMP-SR-NEXT:    addi a1, s0, -36
 ; RV64IZCMP-SR-NEXT:    mv a0, s0
 ; RV64IZCMP-SR-NEXT:    call bar
 ; RV64IZCMP-SR-NEXT:    mv a0, s1
-; RV64IZCMP-SR-NEXT:    .cfi_def_cfa sp, 32
-; RV64IZCMP-SR-NEXT:    cm.popret {ra, s0-s1}, 32
+; RV64IZCMP-SR-NEXT:    .cfi_def_cfa sp, 48
+; RV64IZCMP-SR-NEXT:    cm.popret {ra, s0-s1}, 48
 ;
 ; RV32I-LABEL: use_fp:
 ; RV32I:       # %bb.0: # %entry
diff --git a/llvm/test/CodeGen/RISCV/rv32zbb.ll b/llvm/test/CodeGen/RISCV/rv32zbb.ll
index 1b9b1b89aeb7e..98c86da41afa1 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbb.ll
@@ -416,9 +416,9 @@ define <2 x i1> @ctpop_v2i32_ult_two(<2 x i32> %a) nounwind {
 ; RV32I-LABEL: ctpop_v2i32_ult_two:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, a0, -1
+; RV32I-NEXT:    addi a3, a1, -1
+; RV32I-NEXT:    and a1, a1, a3
 ; RV32I-NEXT:    and a0, a0, a2
-; RV32I-NEXT:    addi a2, a1, -1
-; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    seqz a1, a1
 ; RV32I-NEXT:    ret
@@ -439,9 +439,9 @@ define <2 x i1> @ctpop_v2i32_ugt_one(<2 x i32> %a) nounwind {
 ; RV32I-LABEL: ctpop_v2i32_ugt_one:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, a0, -1
+; RV32I-NEXT:    addi a3, a1, -1
+; RV32I-NEXT:    and a1, a1, a3
 ; RV32I-NEXT:    and a0, a0, a2
-; RV32I-NEXT:    addi a2, a1, -1
-; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    snez a1, a1
 ; RV32I-NEXT:    ret
@@ -464,11 +464,11 @@ define <2 x i1> @ctpop_v2i32_eq_one(<2 x i32> %a) nounwind {
 ; RV32I-LABEL: ctpop_v2i32_eq_one:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, a0, -1
+; RV32I-NEXT:    addi a3, a1, -1
+; RV32I-NEXT:    xor a1, a1, a3
 ; RV32I-NEXT:    xor a0, a0, a2
 ; RV32I-NEXT:    sltu a0, a2, a0
-; RV32I-NEXT:    addi a2, a1, -1
-; RV32I-NEXT:    xor a1, a1, a2
-; RV32I-NEXT:    sltu a1, a2, a1
+; RV32I-NEXT:    sltu a1, a3, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: ctpop_v2i32_eq_one:
@@ -489,11 +489,11 @@ define <2 x i1> @ctpop_v2i32_ne_one(<2 x i32> %a) nounwind {
 ; RV32I-LABEL: ctpop_v2i32_ne_one:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, a0, -1
+; RV32I-NEXT:    addi a3, a1, -1
+; RV32I-NEXT:    xor a1, a1, a3
 ; RV32I-NEXT:    xor a0, a0, a2
 ; RV32I-NEXT:    sltu a0, a2, a0
-; RV32I-NEXT:    addi a2, a1, -1
-; RV32I-NEXT:    xor a1, a1, a2
-; RV32I-NEXT:    sltu a1, a2, a1
+; RV32I-NEXT:    sltu a1, a3, a1
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    xori a1, a1, 1
 ; RV32I-NEXT:    ret
@@ -571,12 +571,12 @@ define i64 @ctpop_i64(i64 %a) nounwind {
 define i1 @ctpop_i64_ugt_two(i64 %a) nounwind {
 ; RV32I-LABEL: ctpop_i64_ugt_two:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi a2, a0, -1
-; RV32I-NEXT:    and a2, a0, a2
-; RV32I-NEXT:    seqz a0, a0
-; RV32I-NEXT:    sub a0, a1, a0
-; RV32I-NEXT:    and a0, a1, a0
-; RV32I-NEXT:    or a0, a2, a0
+; RV32I-NEXT:    seqz a2, a0
+; RV32I-NEXT:    addi a3, a0, -1
+; RV32I-NEXT:    sub a2, a1, a2
+; RV32I-NEXT:    and a0, a0, a3
+; RV32I-NEXT:    and a1, a1, a2
+; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    ret
 ;
@@ -595,12 +595,12 @@ define i1 @ctpop_i64_ugt_two(i64 %a) nounwind {
 define i1 @ctpop_i64_ugt_one(i64 %a) nounwind {
 ; RV32I-LABEL: ctpop_i64_ugt_one:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi a2, a0, -1
-; RV32I-NEXT:    and a2, a0, a2
-; RV32I-NEXT:    seqz a0, a0
-; RV32I-NEXT:    sub a0, a1, a0
-; RV32I-NEXT:    and a0, a1, a0
-; RV32I-NEXT:    or a0, a2, a0
+; RV32I-NEXT:    seqz a2, a0
+; RV32I-NEXT:    addi a3, a0, -1
+; RV32I-NEXT:    sub a2, a1, a2
+; RV32I-NEXT:    and a0, a0, a3
+; RV32I-NEXT:    and a1, a1, a2
+; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    ret
 ;
@@ -785,20 +785,20 @@ define <2 x i1> @ctpop_v2i64_ult_two(<2 x i64> %a) nounwind {
 ; RV32I-LABEL: ctpop_v2i64_ult_two:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lw a1, 0(a0)
-; RV32I-NEXT:    lw a2, 4(a0)
-; RV32I-NEXT:    lw a3, 8(a0)
+; RV32I-NEXT:    lw a2, 8(a0)
+; RV32I-NEXT:    lw a3, 4(a0)
 ; RV32I-NEXT:    lw a0, 12(a0)
-; RV32I-NEXT:    addi a4, a1, -1
-; RV32I-NEXT:    and a4, a1, a4
-; RV32I-NEXT:    seqz a1, a1
-; RV32I-NEXT:    sub a1, a2, a1
-; RV32I-NEXT:    and a1, a2, a1
-; RV32I-NEXT:    addi a2, a3, -1
-; RV32I-NEXT:    and a2, a3, a2
-; RV32I-NEXT:    seqz a3, a3
-; RV32I-NEXT:    sub a3, a0, a3
-; RV32I-NEXT:    and a0, a0, a3
-; RV32I-NEXT:    or a1, a4, a1
+; RV32I-NEXT:    seqz a4, a1
+; RV32I-NEXT:    seqz a5, a2
+; RV32I-NEXT:    addi a6, a1, -1
+; RV32I-NEXT:    addi a7, a2, -1
+; RV32I-NEXT:    sub a4, a3, a4
+; RV32I-NEXT:    sub a5, a0, a5
+; RV32I-NEXT:    and a2, a2, a7
+; RV32I-NEXT:    and a1, a1, a6
+; RV32I-NEXT:    and a0, a0, a5
+; RV32I-NEXT:    and a3, a3, a4
+; RV32I-NEXT:    or a1, a1, a3
 ; RV32I-NEXT:    or a2, a2, a0
 ; RV32I-NEXT:    seqz a0, a1
 ; RV32I-NEXT:    seqz a1, a2
@@ -828,20 +828,20 @@ define <2 x i1> @ctpop_v2i64_ugt_one(<2 x i64> %a) nounwind {
 ; RV32I-LABEL: ctpop_v2i64_ugt_one:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lw a1, 0(a0)
-; RV32I-NEXT:    lw a2, 4(a0)
-; RV32I-NEXT:    lw a3, 8(a0)
+; RV32I-NEXT:    lw a2, 8(a0)
+; RV32I-NEXT:    lw a3, 4(a0)
 ; RV32I-NEXT:    lw a0, 12(a0)
-; RV32I-NEXT:    addi a4, a1, -1
-; RV32I-NEXT:    and a4, a1, a4
-; RV32I-NEXT:    seqz a1, a1
-; RV32I-NEXT:    sub a1, a2, a1
-; RV32I-NEXT:    and a1, a2, a1
-; RV32I-NEXT:    addi a2, a3, -1
-; RV32I-NEXT:    and a2, a3, a2
-; RV32I-NEXT:    seqz a3, a3
-; RV32I-NEXT:    sub a3, a0, a3
-; RV32I-NEXT:    and a0, a0, a3
-; RV32I-NEXT:    or a1, a4, a1
+; RV32I-NEXT:    seqz a4, a1
+; RV32I-NEXT:    seqz a5, a2
+; RV32I-NEXT:    addi a6, a1, -1
+; RV32I-NEXT:    addi a7, a2, -1
+; RV32I-NEXT:    sub a4, a3, a4
+; RV32I-NEXT:    sub a5, a0, a5
+; RV32I-NEXT:    and a2, a2, a7
+; RV32I-NEXT:    and a1, a1, a6
+; RV32I-NEXT:    and a0, a0, a5
+; RV32I-NEXT:    and a3, a3, a4
+; RV32I-NEXT:    or a1, a1, a3
 ; RV32I-NEXT:    or a2, a2, a0
 ; RV32I-NEXT:    snez a0, a1
 ; RV32I-NEXT:    snez a1, a2
diff --git a/llvm/test/CodeGen/RISCV/rv64zbb.ll b/llvm/test/CodeGen/RISCV/rv64zbb.ll
index 25325ad7d50a4..17eb0817d548a 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbb.ll
@@ -719,11 +719,11 @@ define <2 x i1> @ctpop_v2i32_ult_two(<2 x i32> %a) nounwind {
 ; RV64I-LABEL: ctpop_v2i32_ult_two:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, a0, -1
+; RV64I-NEXT:    addi a3, a1, -1
+; RV64I-NEXT:    and a1, a1, a3
 ; RV64I-NEXT:    and a0, a0, a2
-; RV64I-NEXT:    addi a2, a1, -1
-; RV64I-NEXT:    and a1, a1, a2
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    sext.w a1, a1
+; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    seqz a0, a0
 ; RV64I-NEXT:    seqz a1, a1
 ; RV64I-NEXT:    ret
@@ -744,11 +744,11 @@ define <2 x i1> @ctpop_v2i32_ugt_one(<2 x i32> %a) nounwind {
 ; RV64I-LABEL: ctpop_v2i32_ugt_one:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, a0, -1
+; RV64I-NEXT:    addi a3, a1, -1
+; RV64I-NEXT:    and a1, a1, a3
 ; RV64I-NEXT:    and a0, a0, a2
-; RV64I-NEXT:    addi a2, a1, -1
-; RV64I-NEXT:    and a1, a1, a2
-; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    sext.w a1, a1
+; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    snez a1, a1
 ; RV64I-NEXT:    ret
@@ -771,13 +771,13 @@ define <2 x i1> @ctpop_v2i32_eq_one(<2 x i32> %a) nounwind {
 ; RV64I-LABEL: ctpop_v2i32_eq_one:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addiw a2, a0, -1
+; RV64I-NEXT:    addiw a3, a1, -1
+; RV64I-NEXT:    xor a1, a1, a3
 ; RV64I-NEXT:    xor a0, a0, a2
+; RV64I-NEXT:    sext.w a1, a1
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    sltu a0, a2, a0
-; RV64I-NEXT:    addiw a2, a1, -1
-; RV64I-NEXT:    xor a1, a1, a2
-; RV64I-NEXT:    sext.w a1, a1
-; RV64I-NEXT:    sltu a1, a2, a1
+; RV64I-NEXT:    sltu a1, a3, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: ctpop_v2i32_eq_one:
@@ -798,13 +798,13 @@ define <2 x i1> @ctpop_v2i32_ne_one(<2 x i32> %a) nounwind {
 ; RV64I-LABEL: ctpop_v2i32_ne_one:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addiw a2, a0, -1
+; RV64I-NEXT:    addiw a3, a1, -1
+; RV64I-NEXT:    xor a1, a1, a3
 ; RV64I-NEXT:    xor a0, a0, a2
+; RV64I-NEXT:    sext.w a1, a1
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    sltu a0, a2, a0
-; RV64I-NEXT:    addiw a2, a1, -1
-; RV64I-NEXT:    xor a1, a1, a2
-; RV64I-NEXT:    sext.w a1, a1
-; RV64I-NEXT:    sltu a1, a2, a1
+; RV64I-NEXT:    sltu a1, a3, a1
 ; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    xori a1, a1, 1
 ; RV64I-NEXT:    ret
@@ -1009,9 +1009,9 @@ define <2 x i1> @ctpop_v2i64_ult_two(<2 x i64> %a) nounwind {
 ; RV64I-LABEL: ctpop_v2i64_ult_two:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, a0, -1
+; RV64I-NEXT:    addi a3, a1, -1
+; RV64I-NEXT:    and a1, a1, a3
 ; RV64I-NEXT:    and a0, a0, a2
-; RV64I-NEXT:    addi a2, a1, -1
-; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    seqz a0, a0
 ; RV64I-NEXT:    seqz a1, a1
 ; RV64I-NEXT:    ret
@@ -1032,9 +1032,9 @@ define <2 x i1> @ctpop_v2i64_ugt_one(<2 x i64> %a) nounwind {
 ; RV64I-LABEL: ctpop_v2i64_ugt_one:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, a0, -1
+; RV64I-NEXT:    addi a3, a1, -1
+; RV64I-NEXT:    and a1, a1, a3
 ; RV64I-NEXT:    and a0, a0, a2
-; RV64I-NEXT:    addi a2, a1, -1
-; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    snez a1, a1
 ; RV64I-NEXT:    ret
@@ -1057,11 +1057,11 @@ define <2 x i1> @ctpop_v2i64_eq_one(<2 x i64> %a) nounwind {
 ; RV64I-LABEL: ctpop_v2i64_eq_one:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, a0, -1
+; RV64I-NEXT:    addi a3, a1, -1
+; RV64I-NEXT:    xor a1, a1, a3
 ; RV64I-NEXT:    xor a0, a0, a2
 ; RV64I-NEXT:    sltu a0, a2, a0
-; RV64I-NEXT:    addi a2, a1, -1
-; RV64I-NEXT:    xor a1, a1, a2
-; RV64I-NEXT:    sltu a1, a2, a1
+; RV64I-NEXT:    sltu a1, a3, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: ctpop_v2i64_eq_one:
@@ -1082,11 +1082,11 @@ define <2 x i1> @ctpop_v2i64_ne_one(<2 x i64> %a) nounwind {
 ; RV64I-LABEL: ctpop_v2i64_ne_one:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, a0, -1
+; RV64I-NEXT:    addi a3, a1, -1
+; RV64I-NEXT:    xor a1, a1, a3
 ; RV64I-NEXT:    xor a0, a0, a2
 ; RV64I-NEXT:    sltu a0, a2, a0
-; RV64I-NEXT:    addi a2, a1, -1
-; RV64I-NEXT:    xor a1, a1, a2
-; RV64I-NEXT:    sltu a1, a2, a1
+; RV64I-NEXT:    sltu a1, a3, a1
 ; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    xori a1, a1, 1
 ; RV64I-NEXT:    ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
index 9997646dce1a1..b39fff64b1090 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
@@ -876,3 +876,99 @@ define <2 x i64> @vwadd_v2i64_of_v2i16(ptr %x, ptr %y) {
   %e = add <2 x i64> %c, %d
   ret <2 x i64> %e
 }
+
+; %x.i32 and %y.i32 are disjoint, so DAGCombiner will combine it into an or.
+define <4 x i32> @vwaddu_vv_disjoint_or_add(<4 x i8> %x.i8, <4 x i8> %y.i8) {
+; CHECK-LABEL: vwaddu_vv_disjoint_or_add:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT:    vzext.vf2 v10, v8
+; CHECK-NEXT:    vsll.vi v10, v10, 8
+; CHECK-NEXT:    vzext.vf2 v11, v9
+; CHECK-NEXT:    vwaddu.vv v8, v10, v11
+; CHECK-NEXT:    ret
+  %x.i16 = zext <4 x i8> %x.i8 to <4 x i16>
+  %x.shl = shl <4 x i16> %x.i16, splat (i16 8)
+  %x.i32 = zext <4 x i16> %x.shl to <4 x i32>
+  %y.i32 = zext <4 x i8> %y.i8 to <4 x i32>
+  %add = add <4 x i32> %x.i32, %y.i32
+  ret <4 x i32> %add
+}
+
+define <4 x i32> @vwaddu_vv_disjoint_or(<4 x i16> %x.i16, <4 x i16> %y.i16) {
+; CHECK-LABEL: vwaddu_vv_disjoint_or:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT:    vwaddu.vv v10, v8, v9
+; CHECK-NEXT:    vmv1r.v v8, v10
+; CHECK-NEXT:    ret
+  %x.i32 = zext <4 x i16> %x.i16 to <4 x i32>
+  %y.i32 = zext <4 x i16> %y.i16 to <4 x i32>
+  %or = or disjoint <4 x i32> %x.i32, %y.i32
+  ret <4 x i32> %or
+}
+
+define <4 x i32> @vwadd_vv_disjoint_or(<4 x i16> %x.i16, <4 x i16> %y.i16) {
+; CHECK-LABEL: vwadd_vv_disjoint_or:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT:    vwadd.vv v10, v8, v9
+; CHECK-NEXT:    vmv1r.v v8, v10
+; CHECK-NEXT:    ret
+  %x.i32 = sext <4 x i16> %x.i16 to <4 x i32>
+  %y.i32 = sext <4 x i16> %y.i16 to <4 x i32>
+  %or = or disjoint <4 x i32> %x.i32, %y.i32
+  ret <4 x i32> %or
+}
+
+define <4 x i32> @vwaddu_vx_disjoint_or(<4 x i16> %x.i16, i16 %y.i16) {
+; CHECK-LABEL: vwaddu_vx_disjoint_or:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT:    vwaddu.vx v9, v8, a0
+; CHECK-NEXT:    vmv1r.v v8, v9
+; CHECK-NEXT:    ret
+  %x.i32 = zext <4 x i16> %x.i16 to <4 x i32>
+  %y.head = insertelement <4 x i16> poison, i16 %y.i16, i32 0
+  %y.splat = shufflevector <4 x i16> %y.head, <4 x i16> poison, <4 x i32> zeroinitializer
+  %y.i32 = zext <4 x i16> %y.splat to <4 x i32>
+  %or = or disjoint <4 x i32> %x.i32, %y.i32
+  ret <4 x i32> %or
+}
+
+define <4 x i32> @vwadd_vx_disjoint_or(<4 x i16> %x.i16, i16 %y.i16) {
+; CHECK-LABEL: vwadd_vx_disjoint_or:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT:    vwadd.vx v9, v8, a0
+; CHECK-NEXT:    vmv1r.v v8, v9
+; CHECK-NEXT:    ret
+  %x.i32 = sext <4 x i16> %x.i16 to <4 x i32>
+  %y.head = insertelement <4 x i16> poison, i16 %y.i16, i32 0
+  %y.splat = shufflevector <4 x i16> %y.head, <4 x i16> poison, <4 x i32> zeroinitializer
+  %y.i32 = sext <4 x i16> %y.splat to <4 x i32>
+  %or = or disjoint <4 x i32> %x.i32, %y.i32
+  ret <4 x i32> %or
+}
+
+define <4 x i32> @vwaddu_wv_disjoint_or(<4 x i32> %x.i32, <4 x i16> %y.i16) {
+; CHECK-LABEL: vwaddu_wv_disjoint_or:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT:    vwaddu.wv v8, v8, v9
+; CHECK-NEXT:    ret
+  %y.i32 = zext <4 x i16> %y.i16 to <4 x i32>
+  %or = or disjoint <4 x i32> %x.i32, %y.i32
+  ret <4 x i32> %or
+}
+
+define <4 x i32> @vwadd_wv_disjoint_or(<4 x i32> %x.i32, <4 x i16> %y.i16) {
+; CHECK-LABEL: vwadd_wv_disjoint_or:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT:    vwadd.wv v8, v8, v9
+; CHECK-NEXT:    ret
+  %y.i32 = sext <4 x i16> %y.i16 to <4 x i32>
+  %or = or disjoint <4 x i32> %x.i32, %y.i32
+  ret <4 x i32> %or
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll b/llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
index d78603c756050..526ff09d2f8b3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
@@ -108,35 +108,39 @@ define <vscale x 1 x double> @foo(<vscale x 1 x double> %a, <vscale x 1 x double
 ;
 ; SPILL-O2-ZCMP-LABEL: foo:
 ; SPILL-O2-ZCMP:       # %bb.0:
-; SPILL-O2-ZCMP-NEXT:    cm.push {ra, s0}, -16
-; SPILL-O2-ZCMP-NEXT:    .cfi_def_cfa_offset 16
+; SPILL-O2-ZCMP-NEXT:    cm.push {ra, s0}, -32
+; SPILL-O2-ZCMP-NEXT:    .cfi_def_cfa_offset 32
 ; SPILL-O2-ZCMP-NEXT:    .cfi_offset ra, -8
 ; SPILL-O2-ZCMP-NEXT:    .cfi_offset s0, -4
 ; SPILL-O2-ZCMP-NEXT:    csrr a1, vlenb
 ; SPILL-O2-ZCMP-NEXT:    slli a1, a1, 1
 ; SPILL-O2-ZCMP-NEXT:    sub sp, sp, a1
-; SPILL-O2-ZCMP-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
+; SPILL-O2-ZCMP-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 2 * vlenb
 ; SPILL-O2-ZCMP-NEXT:    mv s0, a0
-; SPILL-O2-ZCMP-NEXT:    vs1r.v v8, (sp) # vscale x 8-byte Folded Spill
+; SPILL-O2-ZCMP-NEXT:    addi a1, sp, 16
+; SPILL-O2-ZCMP-NEXT:    vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
 ; SPILL-O2-ZCMP-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
 ; SPILL-O2-ZCMP-NEXT:    vfadd.vv v9, v8, v9
 ; SPILL-O2-ZCMP-NEXT:    csrr a0, vlenb
 ; SPILL-O2-ZCMP-NEXT:    add a0, a0, sp
+; SPILL-O2-ZCMP-NEXT:    addi a0, a0, 16
 ; SPILL-O2-ZCMP-NEXT:    vs1r.v v9, (a0) # vscale x 8-byte Folded Spill
 ; SPILL-O2-ZCMP-NEXT:    lui a0, %hi(.L.str)
 ; SPILL-O2-ZCMP-NEXT:    addi a0, a0, %lo(.L.str)
 ; SPILL-O2-ZCMP-NEXT:    call puts
 ; SPILL-O2-ZCMP-NEXT:    csrr a0, vlenb
 ; SPILL-O2-ZCMP-NEXT:    add a0, a0, sp
+; SPILL-O2-ZCMP-NEXT:    addi a0, a0, 16
 ; SPILL-O2-ZCMP-NEXT:    vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
-; SPILL-O2-ZCMP-NEXT:    vl1r.v v9, (sp) # vscale x 8-byte Folded Reload
+; SPILL-O2-ZCMP-NEXT:    addi a0, sp, 16
+; SPILL-O2-ZCMP-NEXT:    vl1r.v v9, (a0) # vscale x 8-byte Folded Reload
 ; SPILL-O2-ZCMP-NEXT:    vsetvli zero, s0, e64, m1, ta, ma
 ; SPILL-O2-ZCMP-NEXT:    vfadd.vv v8, v9, v8
 ; SPILL-O2-ZCMP-NEXT:    csrr a0, vlenb
 ; SPILL-O2-ZCMP-NEXT:    slli a0, a0, 1
 ; SPILL-O2-ZCMP-NEXT:    add sp, sp, a0
-; SPILL-O2-ZCMP-NEXT:    .cfi_def_cfa sp, 16
-; SPILL-O2-ZCMP-NEXT:    cm.popret {ra, s0}, 16
+; SPILL-O2-ZCMP-NEXT:    .cfi_def_cfa sp, 32
+; SPILL-O2-ZCMP-NEXT:    cm.popret {ra, s0}, 32
 ;
 ; SPILL-O0-VSETVLI-LABEL: foo:
 ; SPILL-O0-VSETVLI:       # %bb.0:
@@ -227,33 +231,37 @@ define <vscale x 1 x double> @foo(<vscale x 1 x double> %a, <vscale x 1 x double
 ;
 ; SPILL-O2-ZCMP-VSETVLI-LABEL: foo:
 ; SPILL-O2-ZCMP-VSETVLI:       # %bb.0:
-; SPILL-O2-ZCMP-VSETVLI-NEXT:    cm.push {ra, s0}, -16
-; SPILL-O2-ZCMP-VSETVLI-NEXT:    .cfi_def_cfa_offset 16
+; SPILL-O2-ZCMP-VSETVLI-NEXT:    cm.push {ra, s0}, -32
+; SPILL-O2-ZCMP-VSETVLI-NEXT:    .cfi_def_cfa_offset 32
 ; SPILL-O2-ZCMP-VSETVLI-NEXT:    .cfi_offset ra, -8
 ; SPILL-O2-ZCMP-VSETVLI-NEXT:    .cfi_offset s0, -4
 ; SPILL-O2-ZCMP-VSETVLI-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
 ; SPILL-O2-ZCMP-VSETVLI-NEXT:    sub sp, sp, a1
-; SPILL-O2-ZCMP-VSETVLI-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
+; SPILL-O2-ZCMP-VSETVLI-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 2 * vlenb
 ; SPILL-O2-ZCMP-VSETVLI-NEXT:    mv s0, a0
-; SPILL-O2-ZCMP-VSETVLI-NEXT:    vs1r.v v8, (sp) # vscale x 8-byte Folded Spill
+; SPILL-O2-ZCMP-VSETVLI-NEXT:    addi a1, sp, 16
+; SPILL-O2-ZCMP-VSETVLI-NEXT:    vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
 ; SPILL-O2-ZCMP-VSETVLI-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
 ; SPILL-O2-ZCMP-VSETVLI-NEXT:    vfadd.vv v9, v8, v9
 ; SPILL-O2-ZCMP-VSETVLI-NEXT:    csrr a0, vlenb
 ; SPILL-O2-ZCMP-VSETVLI-NEXT:    add a0, a0, sp
+; SPILL-O2-ZCMP-VSETVLI-NEXT:    addi a0, a0, 16
 ; SPILL-O2-ZCMP-VSETVLI-NEXT:    vs1r.v v9, (a0) # vscale x 8-byte Folded Spill
 ; SPILL-O2-ZCMP-VSETVLI-NEXT:    lui a0, %hi(.L.str)
 ; SPILL-O2-ZCMP-VSETVLI-NEXT:    addi a0, a0, %lo(.L.str)
 ; SPILL-O2-ZCMP-VSETVLI-NEXT:    call puts
 ; SPILL-O2-ZCMP-VSETVLI-NEXT:    csrr a0, vlenb
 ; SPILL-O2-ZCMP-VSETVLI-NEXT:    add a0, a0, sp
+; SPILL-O2-ZCMP-VSETVLI-NEXT:    addi a0, a0, 16
 ; SPILL-O2-ZCMP-VSETVLI-NEXT:    vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
-; SPILL-O2-ZCMP-VSETVLI-NEXT:    vl1r.v v9, (sp) # vscale x 8-byte Folded Reload
+; SPILL-O2-ZCMP-VSETVLI-NEXT:    addi a0, sp, 16
+; SPILL-O2-ZCMP-VSETVLI-NEXT:    vl1r.v v9, (a0) # vscale x 8-byte Folded Reload
 ; SPILL-O2-ZCMP-VSETVLI-NEXT:    vsetvli zero, s0, e64, m1, ta, ma
 ; SPILL-O2-ZCMP-VSETVLI-NEXT:    vfadd.vv v8, v9, v8
 ; SPILL-O2-ZCMP-VSETVLI-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
 ; SPILL-O2-ZCMP-VSETVLI-NEXT:    add sp, sp, a0
-; SPILL-O2-ZCMP-VSETVLI-NEXT:    .cfi_def_cfa sp, 16
-; SPILL-O2-ZCMP-VSETVLI-NEXT:    cm.popret {ra, s0}, 16
+; SPILL-O2-ZCMP-VSETVLI-NEXT:    .cfi_def_cfa sp, 32
+; SPILL-O2-ZCMP-VSETVLI-NEXT:    cm.popret {ra, s0}, 32
 {
    %x = call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> %a, <vscale x 1 x double> %b, i32 7, i32 %gvl)
    %call = call signext i32 @puts(ptr @.str)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
index a6322c50ff233..469263a3247ce 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
@@ -260,18 +260,18 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv64i1(<vscale x 64 x i1
 ; ZIP-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
 ; ZIP-NEXT:    vmv1r.v v9, v0
 ; ZIP-NEXT:    vmv1r.v v0, v8
-; ZIP-NEXT:    vmv.v.i v24, 0
-; ZIP-NEXT:    vmerge.vim v16, v24, 1, v0
+; ZIP-NEXT:    vmv.v.i v16, 0
+; ZIP-NEXT:    vmerge.vim v24, v16, 1, v0
 ; ZIP-NEXT:    vmv1r.v v0, v9
-; ZIP-NEXT:    vmerge.vim v8, v24, 1, v0
+; ZIP-NEXT:    vmerge.vim v8, v16, 1, v0
 ; ZIP-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
-; ZIP-NEXT:    ri.vzip2b.vv v4, v8, v16
-; ZIP-NEXT:    ri.vzip2b.vv v28, v12, v20
-; ZIP-NEXT:    ri.vzip2a.vv v0, v8, v16
-; ZIP-NEXT:    ri.vzip2a.vv v24, v12, v20
+; ZIP-NEXT:    ri.vzip2b.vv v4, v8, v24
+; ZIP-NEXT:    ri.vzip2b.vv v20, v12, v28
+; ZIP-NEXT:    ri.vzip2a.vv v0, v8, v24
+; ZIP-NEXT:    ri.vzip2a.vv v16, v12, v28
 ; ZIP-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
 ; ZIP-NEXT:    vmsne.vi v9, v0, 0
-; ZIP-NEXT:    vmsne.vi v8, v24, 0
+; ZIP-NEXT:    vmsne.vi v8, v16, 0
 ; ZIP-NEXT:    vmv1r.v v0, v9
 ; ZIP-NEXT:    ret
   %res = call <vscale x 128 x i1> @llvm.vector.interleave2.nxv128i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
index 3f5d42f89337b..f94e46771f49c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
@@ -1417,15 +1417,12 @@ define <vscale x 2 x i32> @vwaddu_vv_disjoint_or_add(<vscale x 2 x i8> %x.i8, <v
   ret <vscale x 2 x i32> %add
 }
 
-; TODO: We could select vwaddu.vv, but when both arms of the or are the same
-; DAGCombiner::hoistLogicOpWithSameOpcodeHands moves the zext above the or.
 define <vscale x 2 x i32> @vwaddu_vv_disjoint_or(<vscale x 2 x i16> %x.i16, <vscale x 2 x i16> %y.i16) {
 ; CHECK-LABEL: vwaddu_vv_disjoint_or:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT:    vor.vv v9, v8, v9
-; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT:    vzext.vf2 v8, v9
+; CHECK-NEXT:    vwaddu.vv v10, v8, v9
+; CHECK-NEXT:    vmv1r.v v8, v10
 ; CHECK-NEXT:    ret
   %x.i32 = zext <vscale x 2 x i16> %x.i16 to <vscale x 2 x i32>
   %y.i32 = zext <vscale x 2 x i16> %y.i16 to <vscale x 2 x i32>
@@ -1433,15 +1430,12 @@ define <vscale x 2 x i32> @vwaddu_vv_disjoint_or(<vscale x 2 x i16> %x.i16, <vsc
   ret <vscale x 2 x i32> %or
 }
 
-; TODO: We could select vwadd.vv, but when both arms of the or are the same
-; DAGCombiner::hoistLogicOpWithSameOpcodeHands moves the zext above the or.
 define <vscale x 2 x i32> @vwadd_vv_disjoint_or(<vscale x 2 x i16> %x.i16, <vscale x 2 x i16> %y.i16) {
 ; CHECK-LABEL: vwadd_vv_disjoint_or:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT:    vor.vv v9, v8, v9
-; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT:    vsext.vf2 v8, v9
+; CHECK-NEXT:    vwadd.vv v10, v8, v9
+; CHECK-NEXT:    vmv1r.v v8, v10
 ; CHECK-NEXT:    ret
   %x.i32 = sext <vscale x 2 x i16> %x.i16 to <vscale x 2 x i32>
   %y.i32 = sext <vscale x 2 x i16> %y.i16 to <vscale x 2 x i32>
@@ -1449,6 +1443,36 @@ define <vscale x 2 x i32> @vwadd_vv_disjoint_or(<vscale x 2 x i16> %x.i16, <vsca
   ret <vscale x 2 x i32> %or
 }
 
+define <vscale x 2 x i32> @vwaddu_vx_disjoint_or(<vscale x 2 x i16> %x.i16, i16 %y.i16) {
+; CHECK-LABEL: vwaddu_vx_disjoint_or:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT:    vwaddu.vx v9, v8, a0
+; CHECK-NEXT:    vmv1r.v v8, v9
+; CHECK-NEXT:    ret
+  %x.i32 = zext <vscale x 2 x i16> %x.i16 to <vscale x 2 x i32>
+  %y.head = insertelement <vscale x 2 x i16> poison, i16 %y.i16, i32 0
+  %y.splat = shufflevector <vscale x 2 x i16> %y.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
+  %y.i32 = zext <vscale x 2 x i16> %y.splat to <vscale x 2 x i32>
+  %or = or disjoint <vscale x 2 x i32> %x.i32, %y.i32
+  ret <vscale x 2 x i32> %or
+}
+
+define <vscale x 2 x i32> @vwadd_vx_disjoint_or(<vscale x 2 x i16> %x.i16, i16 %y.i16) {
+; CHECK-LABEL: vwadd_vx_disjoint_or:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT:    vwadd.vx v9, v8, a0
+; CHECK-NEXT:    vmv1r.v v8, v9
+; CHECK-NEXT:    ret
+  %x.i32 = sext <vscale x 2 x i16> %x.i16 to <vscale x 2 x i32>
+  %y.head = insertelement <vscale x 2 x i16> poison, i16 %y.i16, i32 0
+  %y.splat = shufflevector <vscale x 2 x i16> %y.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
+  %y.i32 = sext <vscale x 2 x i16> %y.splat to <vscale x 2 x i32>
+  %or = or disjoint <vscale x 2 x i32> %x.i32, %y.i32
+  ret <vscale x 2 x i32> %or
+}
+
 define <vscale x 2 x i32> @vwaddu_wv_disjoint_or(<vscale x 2 x i32> %x.i32, <vscale x 2 x i16> %y.i16) {
 ; CHECK-LABEL: vwaddu_wv_disjoint_or:
 ; CHECK:       # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/xqccmp-additional-stack.ll b/llvm/test/CodeGen/RISCV/xqccmp-additional-stack.ll
index 5a5a1ccd2e63a..14e6b9bddd0a0 100644
--- a/llvm/test/CodeGen/RISCV/xqccmp-additional-stack.ll
+++ b/llvm/test/CodeGen/RISCV/xqccmp-additional-stack.ll
@@ -9,8 +9,8 @@ define ptr @func(ptr %s, i32 %_c, ptr %incdec.ptr, i1 %0, i8 %conv14) #0 {
 ; RV32-NEXT:    .cfi_offset ra, -4
 ; RV32-NEXT:    .cfi_offset s0, -8
 ; RV32-NEXT:    .cfi_offset s1, -12
-; RV32-NEXT:    addi sp, sp, -4
-; RV32-NEXT:    .cfi_def_cfa_offset 20
+; RV32-NEXT:    addi sp, sp, -8
+; RV32-NEXT:    .cfi_def_cfa_offset 24
 ; RV32-NEXT:    sw a4, 4(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    sw a2, 0(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    mv a2, a1
@@ -34,7 +34,7 @@ define ptr @func(ptr %s, i32 %_c, ptr %incdec.ptr, i1 %0, i8 %conv14) #0 {
 ; RV32-NEXT:    lw a0, 4(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    sb a0, 0(s0)
 ; RV32-NEXT:    mv a0, s1
-; RV32-NEXT:    addi sp, sp, 4
+; RV32-NEXT:    addi sp, sp, 8
 ; RV32-NEXT:    .cfi_def_cfa_offset 16
 ; RV32-NEXT:    qc.cm.popret {ra, s0-s1}, 16
 entry:
diff --git a/llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll b/llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll
index 957469a3dabe4..529d1d3984bec 100644
--- a/llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll
+++ b/llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll
@@ -16,8 +16,8 @@
 define void @callee() {
 ; RV32IXQCCMP-LABEL: callee:
 ; RV32IXQCCMP:       # %bb.0:
-; RV32IXQCCMP-NEXT:    qc.cm.push {ra, s0-s11}, -80
-; RV32IXQCCMP-NEXT:    .cfi_def_cfa_offset 80
+; RV32IXQCCMP-NEXT:    qc.cm.push {ra, s0-s11}, -96
+; RV32IXQCCMP-NEXT:    .cfi_def_cfa_offset 96
 ; RV32IXQCCMP-NEXT:    .cfi_offset ra, -4
 ; RV32IXQCCMP-NEXT:    .cfi_offset s0, -8
 ; RV32IXQCCMP-NEXT:    .cfi_offset s1, -12
@@ -33,18 +33,18 @@ define void @callee() {
 ; RV32IXQCCMP-NEXT:    .cfi_offset s11, -52
 ; RV32IXQCCMP-NEXT:    lui t0, %hi(var)
 ; RV32IXQCCMP-NEXT:    lw a0, %lo(var)(t0)
-; RV32IXQCCMP-NEXT:    sw a0, 24(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 28(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, %lo(var+4)(t0)
-; RV32IXQCCMP-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 24(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, %lo(var+8)(t0)
-; RV32IXQCCMP-NEXT:    sw a0, 16(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, %lo(var+12)(t0)
-; RV32IXQCCMP-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 16(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    addi a5, t0, %lo(var)
 ; RV32IXQCCMP-NEXT:    lw a0, 16(a5)
-; RV32IXQCCMP-NEXT:    sw a0, 8(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, 20(a5)
-; RV32IXQCCMP-NEXT:    sw a0, 4(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 8(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw t4, 24(a5)
 ; RV32IXQCCMP-NEXT:    lw t5, 28(a5)
 ; RV32IXQCCMP-NEXT:    lw t6, 32(a5)
@@ -97,24 +97,24 @@ define void @callee() {
 ; RV32IXQCCMP-NEXT:    sw t6, 32(a5)
 ; RV32IXQCCMP-NEXT:    sw t5, 28(a5)
 ; RV32IXQCCMP-NEXT:    sw t4, 24(a5)
-; RV32IXQCCMP-NEXT:    lw a0, 4(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, 20(a5)
 ; RV32IXQCCMP-NEXT:    lw a0, 8(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, 16(a5)
+; RV32IXQCCMP-NEXT:    sw a0, 20(a5)
 ; RV32IXQCCMP-NEXT:    lw a0, 12(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, %lo(var+12)(t0)
+; RV32IXQCCMP-NEXT:    sw a0, 16(a5)
 ; RV32IXQCCMP-NEXT:    lw a0, 16(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, %lo(var+8)(t0)
+; RV32IXQCCMP-NEXT:    sw a0, %lo(var+12)(t0)
 ; RV32IXQCCMP-NEXT:    lw a0, 20(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, %lo(var+4)(t0)
+; RV32IXQCCMP-NEXT:    sw a0, %lo(var+8)(t0)
 ; RV32IXQCCMP-NEXT:    lw a0, 24(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    sw a0, %lo(var+4)(t0)
+; RV32IXQCCMP-NEXT:    lw a0, 28(sp) # 4-byte Folded Reload
 ; RV32IXQCCMP-NEXT:    sw a0, %lo(var)(t0)
-; RV32IXQCCMP-NEXT:    qc.cm.popret {ra, s0-s11}, 80
+; RV32IXQCCMP-NEXT:    qc.cm.popret {ra, s0-s11}, 96
 ;
 ; RV32IXQCCMP-WITH-FP-LABEL: callee:
 ; RV32IXQCCMP-WITH-FP:       # %bb.0:
-; RV32IXQCCMP-WITH-FP-NEXT:    qc.cm.pushfp {ra, s0-s11}, -80
-; RV32IXQCCMP-WITH-FP-NEXT:    .cfi_def_cfa_offset 80
+; RV32IXQCCMP-WITH-FP-NEXT:    qc.cm.pushfp {ra, s0-s11}, -96
+; RV32IXQCCMP-WITH-FP-NEXT:    .cfi_def_cfa_offset 96
 ; RV32IXQCCMP-WITH-FP-NEXT:    .cfi_offset ra, -4
 ; RV32IXQCCMP-WITH-FP-NEXT:    .cfi_offset s0, -8
 ; RV32IXQCCMP-WITH-FP-NEXT:    .cfi_offset s1, -12
@@ -131,20 +131,20 @@ define void @callee() {
 ; RV32IXQCCMP-WITH-FP-NEXT:    .cfi_def_cfa s0, 0
 ; RV32IXQCCMP-WITH-FP-NEXT:    lui t1, %hi(var)
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, %lo(var)(t1)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -56(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -68(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, %lo(var+4)(t1)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -60(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -72(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, %lo(var+8)(t1)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -64(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -76(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, %lo(var+12)(t1)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -68(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -80(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    addi a5, t1, %lo(var)
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, 16(a5)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -72(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -84(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, 20(a5)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -76(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -88(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, 24(a5)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -80(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -92(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw t5, 28(a5)
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw t6, 32(a5)
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw s2, 36(a5)
@@ -195,22 +195,22 @@ define void @callee() {
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw s2, 36(a5)
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw t6, 32(a5)
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw t5, 28(a5)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -80(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -92(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, 24(a5)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -76(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -88(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, 20(a5)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -72(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -84(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, 16(a5)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -68(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -80(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, %lo(var+12)(t1)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -64(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -76(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, %lo(var+8)(t1)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -60(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -72(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, %lo(var+4)(t1)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -56(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -68(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, %lo(var)(t1)
-; RV32IXQCCMP-WITH-FP-NEXT:    .cfi_def_cfa sp, 80
-; RV32IXQCCMP-WITH-FP-NEXT:    qc.cm.popret {ra, s0-s11}, 80
+; RV32IXQCCMP-WITH-FP-NEXT:    .cfi_def_cfa sp, 96
+; RV32IXQCCMP-WITH-FP-NEXT:    qc.cm.popret {ra, s0-s11}, 96
 ;
 ; RV64IXQCCMP-LABEL: callee:
 ; RV64IXQCCMP:       # %bb.0:
@@ -231,18 +231,18 @@ define void @callee() {
 ; RV64IXQCCMP-NEXT:    .cfi_offset s11, -104
 ; RV64IXQCCMP-NEXT:    lui t0, %hi(var)
 ; RV64IXQCCMP-NEXT:    lw a0, %lo(var)(t0)
-; RV64IXQCCMP-NEXT:    sd a0, 48(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, %lo(var+4)(t0)
 ; RV64IXQCCMP-NEXT:    sd a0, 40(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, %lo(var+8)(t0)
+; RV64IXQCCMP-NEXT:    lw a0, %lo(var+4)(t0)
 ; RV64IXQCCMP-NEXT:    sd a0, 32(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, %lo(var+12)(t0)
+; RV64IXQCCMP-NEXT:    lw a0, %lo(var+8)(t0)
 ; RV64IXQCCMP-NEXT:    sd a0, 24(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    lw a0, %lo(var+12)(t0)
+; RV64IXQCCMP-NEXT:    sd a0, 16(sp) # 8-byte Folded Spill
 ; RV64IXQCCMP-NEXT:    addi a5, t0, %lo(var)
 ; RV64IXQCCMP-NEXT:    lw a0, 16(a5)
-; RV64IXQCCMP-NEXT:    sd a0, 16(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, 20(a5)
 ; RV64IXQCCMP-NEXT:    sd a0, 8(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    lw a0, 20(a5)
+; RV64IXQCCMP-NEXT:    sd a0, 0(sp) # 8-byte Folded Spill
 ; RV64IXQCCMP-NEXT:    lw t4, 24(a5)
 ; RV64IXQCCMP-NEXT:    lw t5, 28(a5)
 ; RV64IXQCCMP-NEXT:    lw t6, 32(a5)
@@ -295,17 +295,17 @@ define void @callee() {
 ; RV64IXQCCMP-NEXT:    sw t6, 32(a5)
 ; RV64IXQCCMP-NEXT:    sw t5, 28(a5)
 ; RV64IXQCCMP-NEXT:    sw t4, 24(a5)
-; RV64IXQCCMP-NEXT:    ld a0, 8(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 0(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, 20(a5)
-; RV64IXQCCMP-NEXT:    ld a0, 16(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 8(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, 16(a5)
-; RV64IXQCCMP-NEXT:    ld a0, 24(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 16(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, %lo(var+12)(t0)
-; RV64IXQCCMP-NEXT:    ld a0, 32(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 24(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, %lo(var+8)(t0)
-; RV64IXQCCMP-NEXT:    ld a0, 40(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 32(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, %lo(var+4)(t0)
-; RV64IXQCCMP-NEXT:    ld a0, 48(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 40(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, %lo(var)(t0)
 ; RV64IXQCCMP-NEXT:    qc.cm.popret {ra, s0-s11}, 160
 ;
@@ -326,23 +326,25 @@ define void @callee() {
 ; RV64IXQCCMP-WITH-FP-NEXT:    .cfi_offset s9, -88
 ; RV64IXQCCMP-WITH-FP-NEXT:    .cfi_offset s10, -96
 ; RV64IXQCCMP-WITH-FP-NEXT:    .cfi_offset s11, -104
+; RV64IXQCCMP-WITH-FP-NEXT:    addi sp, sp, -16
+; RV64IXQCCMP-WITH-FP-NEXT:    .cfi_def_cfa_offset 176
 ; RV64IXQCCMP-WITH-FP-NEXT:    .cfi_def_cfa s0, 0
 ; RV64IXQCCMP-WITH-FP-NEXT:    lui t1, %hi(var)
 ; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, %lo(var)(t1)
-; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -112(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, %lo(var+4)(t1)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -120(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, %lo(var+8)(t1)
+; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, %lo(var+4)(t1)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -128(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, %lo(var+12)(t1)
+; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, %lo(var+8)(t1)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -136(s0) # 8-byte Folded Spill
+; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, %lo(var+12)(t1)
+; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -144(s0) # 8-byte Folded Spill
 ; RV64IXQCCMP-WITH-FP-NEXT:    addi a5, t1, %lo(var)
 ; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 16(a5)
-; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -144(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 20(a5)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -152(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 24(a5)
+; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 20(a5)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -160(s0) # 8-byte Folded Spill
+; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 24(a5)
+; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -168(s0) # 8-byte Folded Spill
 ; RV64IXQCCMP-WITH-FP-NEXT:    lw t5, 28(a5)
 ; RV64IXQCCMP-WITH-FP-NEXT:    lw t6, 32(a5)
 ; RV64IXQCCMP-WITH-FP-NEXT:    lw s2, 36(a5)
@@ -393,21 +395,23 @@ define void @callee() {
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw s2, 36(a5)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw t6, 32(a5)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw t5, 28(a5)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -160(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -168(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, 24(a5)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -152(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -160(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, 20(a5)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -144(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -152(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, 16(a5)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -136(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -144(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, %lo(var+12)(t1)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -128(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -136(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, %lo(var+8)(t1)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -120(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -128(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, %lo(var+4)(t1)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -112(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -120(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, %lo(var)(t1)
-; RV64IXQCCMP-WITH-FP-NEXT:    .cfi_def_cfa sp, 160
+; RV64IXQCCMP-WITH-FP-NEXT:    .cfi_def_cfa sp, 176
+; RV64IXQCCMP-WITH-FP-NEXT:    addi sp, sp, 16
+; RV64IXQCCMP-WITH-FP-NEXT:    .cfi_def_cfa_offset 160
 ; RV64IXQCCMP-WITH-FP-NEXT:    qc.cm.popret {ra, s0-s11}, 160
   %val = load [32 x i32], ptr @var
   store volatile [32 x i32] %val, ptr @var
@@ -435,54 +439,54 @@ define void @caller() {
 ; RV32IXQCCMP-NEXT:    .cfi_offset s9, -44
 ; RV32IXQCCMP-NEXT:    .cfi_offset s10, -48
 ; RV32IXQCCMP-NEXT:    .cfi_offset s11, -52
-; RV32IXQCCMP-NEXT:    addi sp, sp, -32
-; RV32IXQCCMP-NEXT:    .cfi_def_cfa_offset 144
+; RV32IXQCCMP-NEXT:    addi sp, sp, -48
+; RV32IXQCCMP-NEXT:    .cfi_def_cfa_offset 160
 ; RV32IXQCCMP-NEXT:    lui s0, %hi(var)
 ; RV32IXQCCMP-NEXT:    lw a0, %lo(var)(s0)
-; RV32IXQCCMP-NEXT:    sw a0, 88(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 92(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, %lo(var+4)(s0)
-; RV32IXQCCMP-NEXT:    sw a0, 84(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 88(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, %lo(var+8)(s0)
-; RV32IXQCCMP-NEXT:    sw a0, 80(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 84(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, %lo(var+12)(s0)
-; RV32IXQCCMP-NEXT:    sw a0, 76(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 80(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    addi s1, s0, %lo(var)
 ; RV32IXQCCMP-NEXT:    lw a0, 16(s1)
-; RV32IXQCCMP-NEXT:    sw a0, 72(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 76(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, 20(s1)
-; RV32IXQCCMP-NEXT:    sw a0, 68(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 72(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, 24(s1)
-; RV32IXQCCMP-NEXT:    sw a0, 64(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 68(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, 28(s1)
-; RV32IXQCCMP-NEXT:    sw a0, 60(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 64(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, 32(s1)
-; RV32IXQCCMP-NEXT:    sw a0, 56(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 60(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, 36(s1)
-; RV32IXQCCMP-NEXT:    sw a0, 52(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 56(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, 40(s1)
-; RV32IXQCCMP-NEXT:    sw a0, 48(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 52(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, 44(s1)
-; RV32IXQCCMP-NEXT:    sw a0, 44(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 48(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, 48(s1)
-; RV32IXQCCMP-NEXT:    sw a0, 40(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 44(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, 52(s1)
-; RV32IXQCCMP-NEXT:    sw a0, 36(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 40(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, 56(s1)
-; RV32IXQCCMP-NEXT:    sw a0, 32(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 36(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, 60(s1)
-; RV32IXQCCMP-NEXT:    sw a0, 28(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 32(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, 64(s1)
-; RV32IXQCCMP-NEXT:    sw a0, 24(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 28(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, 68(s1)
-; RV32IXQCCMP-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 24(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, 72(s1)
-; RV32IXQCCMP-NEXT:    sw a0, 16(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, 76(s1)
-; RV32IXQCCMP-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 16(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, 80(s1)
-; RV32IXQCCMP-NEXT:    sw a0, 8(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, 84(s1)
-; RV32IXQCCMP-NEXT:    sw a0, 4(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 8(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw s4, 88(s1)
 ; RV32IXQCCMP-NEXT:    lw s5, 92(s1)
 ; RV32IXQCCMP-NEXT:    lw s6, 96(s1)
@@ -504,51 +508,51 @@ define void @caller() {
 ; RV32IXQCCMP-NEXT:    sw s6, 96(s1)
 ; RV32IXQCCMP-NEXT:    sw s5, 92(s1)
 ; RV32IXQCCMP-NEXT:    sw s4, 88(s1)
-; RV32IXQCCMP-NEXT:    lw a0, 4(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, 84(s1)
 ; RV32IXQCCMP-NEXT:    lw a0, 8(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, 80(s1)
+; RV32IXQCCMP-NEXT:    sw a0, 84(s1)
 ; RV32IXQCCMP-NEXT:    lw a0, 12(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, 76(s1)
+; RV32IXQCCMP-NEXT:    sw a0, 80(s1)
 ; RV32IXQCCMP-NEXT:    lw a0, 16(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, 72(s1)
+; RV32IXQCCMP-NEXT:    sw a0, 76(s1)
 ; RV32IXQCCMP-NEXT:    lw a0, 20(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, 68(s1)
+; RV32IXQCCMP-NEXT:    sw a0, 72(s1)
 ; RV32IXQCCMP-NEXT:    lw a0, 24(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, 64(s1)
+; RV32IXQCCMP-NEXT:    sw a0, 68(s1)
 ; RV32IXQCCMP-NEXT:    lw a0, 28(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, 60(s1)
+; RV32IXQCCMP-NEXT:    sw a0, 64(s1)
 ; RV32IXQCCMP-NEXT:    lw a0, 32(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, 56(s1)
+; RV32IXQCCMP-NEXT:    sw a0, 60(s1)
 ; RV32IXQCCMP-NEXT:    lw a0, 36(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, 52(s1)
+; RV32IXQCCMP-NEXT:    sw a0, 56(s1)
 ; RV32IXQCCMP-NEXT:    lw a0, 40(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, 48(s1)
+; RV32IXQCCMP-NEXT:    sw a0, 52(s1)
 ; RV32IXQCCMP-NEXT:    lw a0, 44(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, 44(s1)
+; RV32IXQCCMP-NEXT:    sw a0, 48(s1)
 ; RV32IXQCCMP-NEXT:    lw a0, 48(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, 40(s1)
+; RV32IXQCCMP-NEXT:    sw a0, 44(s1)
 ; RV32IXQCCMP-NEXT:    lw a0, 52(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, 36(s1)
+; RV32IXQCCMP-NEXT:    sw a0, 40(s1)
 ; RV32IXQCCMP-NEXT:    lw a0, 56(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, 32(s1)
+; RV32IXQCCMP-NEXT:    sw a0, 36(s1)
 ; RV32IXQCCMP-NEXT:    lw a0, 60(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, 28(s1)
+; RV32IXQCCMP-NEXT:    sw a0, 32(s1)
 ; RV32IXQCCMP-NEXT:    lw a0, 64(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, 24(s1)
+; RV32IXQCCMP-NEXT:    sw a0, 28(s1)
 ; RV32IXQCCMP-NEXT:    lw a0, 68(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, 20(s1)
+; RV32IXQCCMP-NEXT:    sw a0, 24(s1)
 ; RV32IXQCCMP-NEXT:    lw a0, 72(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, 16(s1)
+; RV32IXQCCMP-NEXT:    sw a0, 20(s1)
 ; RV32IXQCCMP-NEXT:    lw a0, 76(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, %lo(var+12)(s0)
+; RV32IXQCCMP-NEXT:    sw a0, 16(s1)
 ; RV32IXQCCMP-NEXT:    lw a0, 80(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, %lo(var+8)(s0)
+; RV32IXQCCMP-NEXT:    sw a0, %lo(var+12)(s0)
 ; RV32IXQCCMP-NEXT:    lw a0, 84(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, %lo(var+4)(s0)
+; RV32IXQCCMP-NEXT:    sw a0, %lo(var+8)(s0)
 ; RV32IXQCCMP-NEXT:    lw a0, 88(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    sw a0, %lo(var+4)(s0)
+; RV32IXQCCMP-NEXT:    lw a0, 92(sp) # 4-byte Folded Reload
 ; RV32IXQCCMP-NEXT:    sw a0, %lo(var)(s0)
-; RV32IXQCCMP-NEXT:    addi sp, sp, 32
+; RV32IXQCCMP-NEXT:    addi sp, sp, 48
 ; RV32IXQCCMP-NEXT:    .cfi_def_cfa_offset 112
 ; RV32IXQCCMP-NEXT:    qc.cm.popret {ra, s0-s11}, 112
 ;
@@ -569,57 +573,57 @@ define void @caller() {
 ; RV32IXQCCMP-WITH-FP-NEXT:    .cfi_offset s9, -44
 ; RV32IXQCCMP-WITH-FP-NEXT:    .cfi_offset s10, -48
 ; RV32IXQCCMP-WITH-FP-NEXT:    .cfi_offset s11, -52
-; RV32IXQCCMP-WITH-FP-NEXT:    addi sp, sp, -32
-; RV32IXQCCMP-WITH-FP-NEXT:    .cfi_def_cfa_offset 144
+; RV32IXQCCMP-WITH-FP-NEXT:    addi sp, sp, -48
+; RV32IXQCCMP-WITH-FP-NEXT:    .cfi_def_cfa_offset 160
 ; RV32IXQCCMP-WITH-FP-NEXT:    .cfi_def_cfa s0, 0
 ; RV32IXQCCMP-WITH-FP-NEXT:    lui s6, %hi(var)
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, %lo(var)(s6)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -56(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -68(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, %lo(var+4)(s6)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -60(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -72(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, %lo(var+8)(s6)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -64(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -76(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, %lo(var+12)(s6)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -68(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -80(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    addi s1, s6, %lo(var)
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, 16(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -72(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -84(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, 20(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -76(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -88(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, 24(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -80(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -92(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, 28(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -84(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -96(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, 32(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -88(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -100(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, 36(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -92(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -104(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, 40(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -96(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -108(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, 44(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -100(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -112(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, 48(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -104(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -116(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, 52(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -108(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -120(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, 56(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -112(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -124(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, 60(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -116(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -128(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, 64(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -120(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -132(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, 68(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -124(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -136(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, 72(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -128(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -140(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, 76(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -132(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -144(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, 80(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -136(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -148(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, 84(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -140(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -152(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, 88(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -144(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, -156(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw s8, 92(s1)
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw s9, 96(s1)
 ; RV32IXQCCMP-WITH-FP-NEXT:    lw s10, 100(s1)
@@ -639,54 +643,54 @@ define void @caller() {
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw s10, 100(s1)
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw s9, 96(s1)
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw s8, 92(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -144(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -156(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, 88(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -140(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -152(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, 84(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -136(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -148(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, 80(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -132(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -144(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, 76(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -128(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -140(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, 72(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -124(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -136(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, 68(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -120(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -132(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, 64(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -116(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -128(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, 60(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -112(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -124(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, 56(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -108(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -120(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, 52(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -104(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -116(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, 48(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -100(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -112(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, 44(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -96(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -108(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, 40(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -92(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -104(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, 36(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -88(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -100(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, 32(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -84(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -96(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, 28(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -80(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -92(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, 24(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -76(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -88(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, 20(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -72(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -84(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, 16(s1)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -68(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -80(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, %lo(var+12)(s6)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -64(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -76(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, %lo(var+8)(s6)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -60(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -72(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, %lo(var+4)(s6)
-; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -56(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT:    lw a0, -68(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-WITH-FP-NEXT:    sw a0, %lo(var)(s6)
-; RV32IXQCCMP-WITH-FP-NEXT:    .cfi_def_cfa sp, 144
-; RV32IXQCCMP-WITH-FP-NEXT:    addi sp, sp, 32
+; RV32IXQCCMP-WITH-FP-NEXT:    .cfi_def_cfa sp, 160
+; RV32IXQCCMP-WITH-FP-NEXT:    addi sp, sp, 48
 ; RV32IXQCCMP-WITH-FP-NEXT:    .cfi_def_cfa_offset 112
 ; RV32IXQCCMP-WITH-FP-NEXT:    qc.cm.popret {ra, s0-s11}, 112
 ;
@@ -711,50 +715,50 @@ define void @caller() {
 ; RV64IXQCCMP-NEXT:    .cfi_def_cfa_offset 288
 ; RV64IXQCCMP-NEXT:    lui s0, %hi(var)
 ; RV64IXQCCMP-NEXT:    lw a0, %lo(var)(s0)
-; RV64IXQCCMP-NEXT:    sd a0, 176(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, %lo(var+4)(s0)
 ; RV64IXQCCMP-NEXT:    sd a0, 168(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, %lo(var+8)(s0)
+; RV64IXQCCMP-NEXT:    lw a0, %lo(var+4)(s0)
 ; RV64IXQCCMP-NEXT:    sd a0, 160(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, %lo(var+12)(s0)
+; RV64IXQCCMP-NEXT:    lw a0, %lo(var+8)(s0)
 ; RV64IXQCCMP-NEXT:    sd a0, 152(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    lw a0, %lo(var+12)(s0)
+; RV64IXQCCMP-NEXT:    sd a0, 144(sp) # 8-byte Folded Spill
 ; RV64IXQCCMP-NEXT:    addi s1, s0, %lo(var)
 ; RV64IXQCCMP-NEXT:    lw a0, 16(s1)
-; RV64IXQCCMP-NEXT:    sd a0, 144(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, 20(s1)
 ; RV64IXQCCMP-NEXT:    sd a0, 136(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, 24(s1)
+; RV64IXQCCMP-NEXT:    lw a0, 20(s1)
 ; RV64IXQCCMP-NEXT:    sd a0, 128(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, 28(s1)
+; RV64IXQCCMP-NEXT:    lw a0, 24(s1)
 ; RV64IXQCCMP-NEXT:    sd a0, 120(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, 32(s1)
+; RV64IXQCCMP-NEXT:    lw a0, 28(s1)
 ; RV64IXQCCMP-NEXT:    sd a0, 112(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, 36(s1)
+; RV64IXQCCMP-NEXT:    lw a0, 32(s1)
 ; RV64IXQCCMP-NEXT:    sd a0, 104(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, 40(s1)
+; RV64IXQCCMP-NEXT:    lw a0, 36(s1)
 ; RV64IXQCCMP-NEXT:    sd a0, 96(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, 44(s1)
+; RV64IXQCCMP-NEXT:    lw a0, 40(s1)
 ; RV64IXQCCMP-NEXT:    sd a0, 88(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, 48(s1)
+; RV64IXQCCMP-NEXT:    lw a0, 44(s1)
 ; RV64IXQCCMP-NEXT:    sd a0, 80(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, 52(s1)
+; RV64IXQCCMP-NEXT:    lw a0, 48(s1)
 ; RV64IXQCCMP-NEXT:    sd a0, 72(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, 56(s1)
+; RV64IXQCCMP-NEXT:    lw a0, 52(s1)
 ; RV64IXQCCMP-NEXT:    sd a0, 64(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, 60(s1)
+; RV64IXQCCMP-NEXT:    lw a0, 56(s1)
 ; RV64IXQCCMP-NEXT:    sd a0, 56(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, 64(s1)
+; RV64IXQCCMP-NEXT:    lw a0, 60(s1)
 ; RV64IXQCCMP-NEXT:    sd a0, 48(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, 68(s1)
+; RV64IXQCCMP-NEXT:    lw a0, 64(s1)
 ; RV64IXQCCMP-NEXT:    sd a0, 40(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, 72(s1)
+; RV64IXQCCMP-NEXT:    lw a0, 68(s1)
 ; RV64IXQCCMP-NEXT:    sd a0, 32(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, 76(s1)
+; RV64IXQCCMP-NEXT:    lw a0, 72(s1)
 ; RV64IXQCCMP-NEXT:    sd a0, 24(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, 80(s1)
+; RV64IXQCCMP-NEXT:    lw a0, 76(s1)
 ; RV64IXQCCMP-NEXT:    sd a0, 16(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, 84(s1)
+; RV64IXQCCMP-NEXT:    lw a0, 80(s1)
 ; RV64IXQCCMP-NEXT:    sd a0, 8(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    lw a0, 84(s1)
+; RV64IXQCCMP-NEXT:    sd a0, 0(sp) # 8-byte Folded Spill
 ; RV64IXQCCMP-NEXT:    lw s4, 88(s1)
 ; RV64IXQCCMP-NEXT:    lw s5, 92(s1)
 ; RV64IXQCCMP-NEXT:    lw s6, 96(s1)
@@ -776,49 +780,49 @@ define void @caller() {
 ; RV64IXQCCMP-NEXT:    sw s6, 96(s1)
 ; RV64IXQCCMP-NEXT:    sw s5, 92(s1)
 ; RV64IXQCCMP-NEXT:    sw s4, 88(s1)
-; RV64IXQCCMP-NEXT:    ld a0, 8(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 0(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, 84(s1)
-; RV64IXQCCMP-NEXT:    ld a0, 16(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 8(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, 80(s1)
-; RV64IXQCCMP-NEXT:    ld a0, 24(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 16(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, 76(s1)
-; RV64IXQCCMP-NEXT:    ld a0, 32(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 24(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, 72(s1)
-; RV64IXQCCMP-NEXT:    ld a0, 40(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 32(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, 68(s1)
-; RV64IXQCCMP-NEXT:    ld a0, 48(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 40(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, 64(s1)
-; RV64IXQCCMP-NEXT:    ld a0, 56(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 48(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, 60(s1)
-; RV64IXQCCMP-NEXT:    ld a0, 64(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 56(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, 56(s1)
-; RV64IXQCCMP-NEXT:    ld a0, 72(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 64(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, 52(s1)
-; RV64IXQCCMP-NEXT:    ld a0, 80(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 72(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, 48(s1)
-; RV64IXQCCMP-NEXT:    ld a0, 88(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 80(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, 44(s1)
-; RV64IXQCCMP-NEXT:    ld a0, 96(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 88(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, 40(s1)
-; RV64IXQCCMP-NEXT:    ld a0, 104(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 96(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, 36(s1)
-; RV64IXQCCMP-NEXT:    ld a0, 112(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 104(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, 32(s1)
-; RV64IXQCCMP-NEXT:    ld a0, 120(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 112(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, 28(s1)
-; RV64IXQCCMP-NEXT:    ld a0, 128(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 120(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, 24(s1)
-; RV64IXQCCMP-NEXT:    ld a0, 136(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 128(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, 20(s1)
-; RV64IXQCCMP-NEXT:    ld a0, 144(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 136(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, 16(s1)
-; RV64IXQCCMP-NEXT:    ld a0, 152(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 144(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, %lo(var+12)(s0)
-; RV64IXQCCMP-NEXT:    ld a0, 160(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 152(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, %lo(var+8)(s0)
-; RV64IXQCCMP-NEXT:    ld a0, 168(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 160(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, %lo(var+4)(s0)
-; RV64IXQCCMP-NEXT:    ld a0, 176(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 168(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, %lo(var)(s0)
 ; RV64IXQCCMP-NEXT:    addi sp, sp, 128
 ; RV64IXQCCMP-NEXT:    .cfi_def_cfa_offset 160
@@ -841,57 +845,57 @@ define void @caller() {
 ; RV64IXQCCMP-WITH-FP-NEXT:    .cfi_offset s9, -88
 ; RV64IXQCCMP-WITH-FP-NEXT:    .cfi_offset s10, -96
 ; RV64IXQCCMP-WITH-FP-NEXT:    .cfi_offset s11, -104
-; RV64IXQCCMP-WITH-FP-NEXT:    addi sp, sp, -128
-; RV64IXQCCMP-WITH-FP-NEXT:    .cfi_def_cfa_offset 288
+; RV64IXQCCMP-WITH-FP-NEXT:    addi sp, sp, -144
+; RV64IXQCCMP-WITH-FP-NEXT:    .cfi_def_cfa_offset 304
 ; RV64IXQCCMP-WITH-FP-NEXT:    .cfi_def_cfa s0, 0
 ; RV64IXQCCMP-WITH-FP-NEXT:    lui s6, %hi(var)
 ; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, %lo(var)(s6)
-; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -112(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, %lo(var+4)(s6)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -120(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, %lo(var+8)(s6)
+; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, %lo(var+4)(s6)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -128(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, %lo(var+12)(s6)
+; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, %lo(var+8)(s6)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -136(s0) # 8-byte Folded Spill
+; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, %lo(var+12)(s6)
+; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -144(s0) # 8-byte Folded Spill
 ; RV64IXQCCMP-WITH-FP-NEXT:    addi s1, s6, %lo(var)
 ; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 16(s1)
-; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -144(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 20(s1)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -152(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 24(s1)
+; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 20(s1)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -160(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 28(s1)
+; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 24(s1)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -168(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 32(s1)
+; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 28(s1)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -176(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 36(s1)
+; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 32(s1)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -184(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 40(s1)
+; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 36(s1)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -192(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 44(s1)
+; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 40(s1)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -200(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 48(s1)
+; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 44(s1)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -208(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 52(s1)
+; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 48(s1)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -216(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 56(s1)
+; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 52(s1)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -224(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 60(s1)
+; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 56(s1)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -232(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 64(s1)
+; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 60(s1)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -240(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 68(s1)
+; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 64(s1)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -248(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 72(s1)
+; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 68(s1)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -256(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 76(s1)
+; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 72(s1)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -264(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 80(s1)
+; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 76(s1)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -272(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 84(s1)
+; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 80(s1)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -280(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 88(s1)
+; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 84(s1)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -288(s0) # 8-byte Folded Spill
+; RV64IXQCCMP-WITH-FP-NEXT:    lw a0, 88(s1)
+; RV64IXQCCMP-WITH-FP-NEXT:    sd a0, -296(s0) # 8-byte Folded Spill
 ; RV64IXQCCMP-WITH-FP-NEXT:    lw s8, 92(s1)
 ; RV64IXQCCMP-WITH-FP-NEXT:    lw s9, 96(s1)
 ; RV64IXQCCMP-WITH-FP-NEXT:    lw s10, 100(s1)
@@ -911,54 +915,54 @@ define void @caller() {
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw s10, 100(s1)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw s9, 96(s1)
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw s8, 92(s1)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -288(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -296(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, 88(s1)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -280(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -288(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, 84(s1)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -272(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -280(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, 80(s1)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -264(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -272(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, 76(s1)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -256(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -264(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, 72(s1)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -248(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -256(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, 68(s1)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -240(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -248(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, 64(s1)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -232(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -240(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, 60(s1)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -224(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -232(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, 56(s1)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -216(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -224(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, 52(s1)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -208(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -216(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, 48(s1)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -200(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -208(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, 44(s1)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -192(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -200(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, 40(s1)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -184(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -192(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, 36(s1)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -176(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -184(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, 32(s1)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -168(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -176(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, 28(s1)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -160(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -168(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, 24(s1)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -152(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -160(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, 20(s1)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -144(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -152(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, 16(s1)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -136(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -144(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, %lo(var+12)(s6)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -128(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -136(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, %lo(var+8)(s6)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -120(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -128(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, %lo(var+4)(s6)
-; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -112(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT:    ld a0, -120(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-WITH-FP-NEXT:    sw a0, %lo(var)(s6)
-; RV64IXQCCMP-WITH-FP-NEXT:    .cfi_def_cfa sp, 288
-; RV64IXQCCMP-WITH-FP-NEXT:    addi sp, sp, 128
+; RV64IXQCCMP-WITH-FP-NEXT:    .cfi_def_cfa sp, 304
+; RV64IXQCCMP-WITH-FP-NEXT:    addi sp, sp, 144
 ; RV64IXQCCMP-WITH-FP-NEXT:    .cfi_def_cfa_offset 160
 ; RV64IXQCCMP-WITH-FP-NEXT:    qc.cm.popret {ra, s0-s11}, 160
   %val = load [32 x i32], ptr @var
diff --git a/llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll b/llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
index c1a5e6093f1c5..415511fcfd995 100644
--- a/llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
+++ b/llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
@@ -24,7 +24,7 @@ define i32 @foo() {
 ; RV32IXQCCMP-NEXT:    .cfi_offset ra, -4
 ; RV32IXQCCMP-NEXT:    addi sp, sp, -464
 ; RV32IXQCCMP-NEXT:    .cfi_def_cfa_offset 528
-; RV32IXQCCMP-NEXT:    addi a0, sp, 12
+; RV32IXQCCMP-NEXT:    mv a0, sp
 ; RV32IXQCCMP-NEXT:    call test
 ; RV32IXQCCMP-NEXT:    addi sp, sp, 464
 ; RV32IXQCCMP-NEXT:    .cfi_def_cfa_offset 64
@@ -37,7 +37,7 @@ define i32 @foo() {
 ; RV64IXQCCMP-NEXT:    .cfi_offset ra, -8
 ; RV64IXQCCMP-NEXT:    addi sp, sp, -464
 ; RV64IXQCCMP-NEXT:    .cfi_def_cfa_offset 528
-; RV64IXQCCMP-NEXT:    addi a0, sp, 8
+; RV64IXQCCMP-NEXT:    mv a0, sp
 ; RV64IXQCCMP-NEXT:    call test
 ; RV64IXQCCMP-NEXT:    addi sp, sp, 464
 ; RV64IXQCCMP-NEXT:    .cfi_def_cfa_offset 64
@@ -52,7 +52,7 @@ define i32 @foo() {
 ; RV32IXQCCMP-FP-NEXT:    addi sp, sp, -464
 ; RV32IXQCCMP-FP-NEXT:    .cfi_def_cfa_offset 528
 ; RV32IXQCCMP-FP-NEXT:    .cfi_def_cfa s0, 0
-; RV32IXQCCMP-FP-NEXT:    addi a0, s0, -520
+; RV32IXQCCMP-FP-NEXT:    addi a0, s0, -528
 ; RV32IXQCCMP-FP-NEXT:    call test
 ; RV32IXQCCMP-FP-NEXT:    .cfi_def_cfa sp, 528
 ; RV32IXQCCMP-FP-NEXT:    addi sp, sp, 464
@@ -82,7 +82,7 @@ define i32 @foo() {
 ; RV32IXQCCMP-SR-NEXT:    .cfi_offset ra, -4
 ; RV32IXQCCMP-SR-NEXT:    addi sp, sp, -464
 ; RV32IXQCCMP-SR-NEXT:    .cfi_def_cfa_offset 528
-; RV32IXQCCMP-SR-NEXT:    addi a0, sp, 12
+; RV32IXQCCMP-SR-NEXT:    mv a0, sp
 ; RV32IXQCCMP-SR-NEXT:    call test
 ; RV32IXQCCMP-SR-NEXT:    addi sp, sp, 464
 ; RV32IXQCCMP-SR-NEXT:    .cfi_def_cfa_offset 64
@@ -95,7 +95,7 @@ define i32 @foo() {
 ; RV64IXQCCMP-SR-NEXT:    .cfi_offset ra, -8
 ; RV64IXQCCMP-SR-NEXT:    addi sp, sp, -464
 ; RV64IXQCCMP-SR-NEXT:    .cfi_def_cfa_offset 528
-; RV64IXQCCMP-SR-NEXT:    addi a0, sp, 8
+; RV64IXQCCMP-SR-NEXT:    mv a0, sp
 ; RV64IXQCCMP-SR-NEXT:    call test
 ; RV64IXQCCMP-SR-NEXT:    addi sp, sp, 464
 ; RV64IXQCCMP-SR-NEXT:    .cfi_def_cfa_offset 64
@@ -1595,52 +1595,54 @@ define void @foo_with_irq() "interrupt"="machine" {
 ; RV32IXQCCMP-NEXT:    qc.cm.push {ra}, -64
 ; RV32IXQCCMP-NEXT:    .cfi_def_cfa_offset 64
 ; RV32IXQCCMP-NEXT:    .cfi_offset ra, -4
-; RV32IXQCCMP-NEXT:    sw t0, 56(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw t1, 52(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw t2, 48(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw a0, 44(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw a1, 40(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw a2, 36(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw a3, 32(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw a4, 28(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw a5, 24(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw a6, 20(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw a7, 16(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw t3, 12(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw t4, 8(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw t5, 4(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw t6, 0(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    .cfi_offset t0, -8
-; RV32IXQCCMP-NEXT:    .cfi_offset t1, -12
-; RV32IXQCCMP-NEXT:    .cfi_offset t2, -16
-; RV32IXQCCMP-NEXT:    .cfi_offset a0, -20
-; RV32IXQCCMP-NEXT:    .cfi_offset a1, -24
-; RV32IXQCCMP-NEXT:    .cfi_offset a2, -28
-; RV32IXQCCMP-NEXT:    .cfi_offset a3, -32
-; RV32IXQCCMP-NEXT:    .cfi_offset a4, -36
-; RV32IXQCCMP-NEXT:    .cfi_offset a5, -40
-; RV32IXQCCMP-NEXT:    .cfi_offset a6, -44
-; RV32IXQCCMP-NEXT:    .cfi_offset a7, -48
-; RV32IXQCCMP-NEXT:    .cfi_offset t3, -52
-; RV32IXQCCMP-NEXT:    .cfi_offset t4, -56
-; RV32IXQCCMP-NEXT:    .cfi_offset t5, -60
-; RV32IXQCCMP-NEXT:    .cfi_offset t6, -64
+; RV32IXQCCMP-NEXT:    addi sp, sp, -16
+; RV32IXQCCMP-NEXT:    .cfi_def_cfa_offset 80
+; RV32IXQCCMP-NEXT:    sw t0, 60(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw t1, 56(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw t2, 52(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 48(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a1, 44(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a2, 40(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a3, 36(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a4, 32(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a5, 28(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a6, 24(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a7, 20(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw t3, 16(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw t4, 12(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw t5, 8(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw t6, 4(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    .cfi_offset t0, -20
+; RV32IXQCCMP-NEXT:    .cfi_offset t1, -24
+; RV32IXQCCMP-NEXT:    .cfi_offset t2, -28
+; RV32IXQCCMP-NEXT:    .cfi_offset a0, -32
+; RV32IXQCCMP-NEXT:    .cfi_offset a1, -36
+; RV32IXQCCMP-NEXT:    .cfi_offset a2, -40
+; RV32IXQCCMP-NEXT:    .cfi_offset a3, -44
+; RV32IXQCCMP-NEXT:    .cfi_offset a4, -48
+; RV32IXQCCMP-NEXT:    .cfi_offset a5, -52
+; RV32IXQCCMP-NEXT:    .cfi_offset a6, -56
+; RV32IXQCCMP-NEXT:    .cfi_offset a7, -60
+; RV32IXQCCMP-NEXT:    .cfi_offset t3, -64
+; RV32IXQCCMP-NEXT:    .cfi_offset t4, -68
+; RV32IXQCCMP-NEXT:    .cfi_offset t5, -72
+; RV32IXQCCMP-NEXT:    .cfi_offset t6, -76
 ; RV32IXQCCMP-NEXT:    call foo_test_irq
-; RV32IXQCCMP-NEXT:    lw t0, 56(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw t1, 52(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw t2, 48(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw a0, 44(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw a1, 40(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw a2, 36(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw a3, 32(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw a4, 28(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw a5, 24(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw a6, 20(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw a7, 16(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw t3, 12(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw t4, 8(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw t5, 4(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw t6, 0(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw t0, 60(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw t1, 56(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw t2, 52(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw a0, 48(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw a1, 44(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw a2, 40(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw a3, 36(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw a4, 32(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw a5, 28(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw a6, 24(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw a7, 20(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw t3, 16(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw t4, 12(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw t5, 8(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw t6, 4(sp) # 4-byte Folded Reload
 ; RV32IXQCCMP-NEXT:    .cfi_restore t0
 ; RV32IXQCCMP-NEXT:    .cfi_restore t1
 ; RV32IXQCCMP-NEXT:    .cfi_restore t2
@@ -1656,6 +1658,8 @@ define void @foo_with_irq() "interrupt"="machine" {
 ; RV32IXQCCMP-NEXT:    .cfi_restore t4
 ; RV32IXQCCMP-NEXT:    .cfi_restore t5
 ; RV32IXQCCMP-NEXT:    .cfi_restore t6
+; RV32IXQCCMP-NEXT:    addi sp, sp, 16
+; RV32IXQCCMP-NEXT:    .cfi_def_cfa_offset 64
 ; RV32IXQCCMP-NEXT:    qc.cm.pop {ra}, 64
 ; RV32IXQCCMP-NEXT:    .cfi_restore ra
 ; RV32IXQCCMP-NEXT:    .cfi_def_cfa_offset 0
@@ -1666,54 +1670,54 @@ define void @foo_with_irq() "interrupt"="machine" {
 ; RV64IXQCCMP-NEXT:    qc.cm.push {ra}, -64
 ; RV64IXQCCMP-NEXT:    .cfi_def_cfa_offset 64
 ; RV64IXQCCMP-NEXT:    .cfi_offset ra, -8
-; RV64IXQCCMP-NEXT:    addi sp, sp, -64
-; RV64IXQCCMP-NEXT:    .cfi_def_cfa_offset 128
-; RV64IXQCCMP-NEXT:    sd t0, 112(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd t1, 104(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd t2, 96(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd a0, 88(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd a1, 80(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd a2, 72(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd a3, 64(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd a4, 56(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd a5, 48(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd a6, 40(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd a7, 32(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd t3, 24(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd t4, 16(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd t5, 8(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd t6, 0(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    .cfi_offset t0, -16
-; RV64IXQCCMP-NEXT:    .cfi_offset t1, -24
-; RV64IXQCCMP-NEXT:    .cfi_offset t2, -32
-; RV64IXQCCMP-NEXT:    .cfi_offset a0, -40
-; RV64IXQCCMP-NEXT:    .cfi_offset a1, -48
-; RV64IXQCCMP-NEXT:    .cfi_offset a2, -56
-; RV64IXQCCMP-NEXT:    .cfi_offset a3, -64
-; RV64IXQCCMP-NEXT:    .cfi_offset a4, -72
-; RV64IXQCCMP-NEXT:    .cfi_offset a5, -80
-; RV64IXQCCMP-NEXT:    .cfi_offset a6, -88
-; RV64IXQCCMP-NEXT:    .cfi_offset a7, -96
-; RV64IXQCCMP-NEXT:    .cfi_offset t3, -104
-; RV64IXQCCMP-NEXT:    .cfi_offset t4, -112
-; RV64IXQCCMP-NEXT:    .cfi_offset t5, -120
-; RV64IXQCCMP-NEXT:    .cfi_offset t6, -128
+; RV64IXQCCMP-NEXT:    addi sp, sp, -80
+; RV64IXQCCMP-NEXT:    .cfi_def_cfa_offset 144
+; RV64IXQCCMP-NEXT:    sd t0, 120(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd t1, 112(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd t2, 104(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd a0, 96(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd a1, 88(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd a2, 80(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd a3, 72(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd a4, 64(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd a5, 56(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd a6, 48(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd a7, 40(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd t3, 32(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd t4, 24(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd t5, 16(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd t6, 8(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    .cfi_offset t0, -24
+; RV64IXQCCMP-NEXT:    .cfi_offset t1, -32
+; RV64IXQCCMP-NEXT:    .cfi_offset t2, -40
+; RV64IXQCCMP-NEXT:    .cfi_offset a0, -48
+; RV64IXQCCMP-NEXT:    .cfi_offset a1, -56
+; RV64IXQCCMP-NEXT:    .cfi_offset a2, -64
+; RV64IXQCCMP-NEXT:    .cfi_offset a3, -72
+; RV64IXQCCMP-NEXT:    .cfi_offset a4, -80
+; RV64IXQCCMP-NEXT:    .cfi_offset a5, -88
+; RV64IXQCCMP-NEXT:    .cfi_offset a6, -96
+; RV64IXQCCMP-NEXT:    .cfi_offset a7, -104
+; RV64IXQCCMP-NEXT:    .cfi_offset t3, -112
+; RV64IXQCCMP-NEXT:    .cfi_offset t4, -120
+; RV64IXQCCMP-NEXT:    .cfi_offset t5, -128
+; RV64IXQCCMP-NEXT:    .cfi_offset t6, -136
 ; RV64IXQCCMP-NEXT:    call foo_test_irq
-; RV64IXQCCMP-NEXT:    ld t0, 112(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld t1, 104(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld t2, 96(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld a0, 88(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld a1, 80(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld a2, 72(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld a3, 64(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld a4, 56(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld a5, 48(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld a6, 40(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld a7, 32(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld t3, 24(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld t4, 16(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld t5, 8(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld t6, 0(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld t0, 120(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld t1, 112(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld t2, 104(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 96(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a1, 88(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a2, 80(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a3, 72(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a4, 64(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a5, 56(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a6, 48(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a7, 40(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld t3, 32(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld t4, 24(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld t5, 16(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld t6, 8(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    .cfi_restore t0
 ; RV64IXQCCMP-NEXT:    .cfi_restore t1
 ; RV64IXQCCMP-NEXT:    .cfi_restore t2
@@ -1729,7 +1733,7 @@ define void @foo_with_irq() "interrupt"="machine" {
 ; RV64IXQCCMP-NEXT:    .cfi_restore t4
 ; RV64IXQCCMP-NEXT:    .cfi_restore t5
 ; RV64IXQCCMP-NEXT:    .cfi_restore t6
-; RV64IXQCCMP-NEXT:    addi sp, sp, 64
+; RV64IXQCCMP-NEXT:    addi sp, sp, 80
 ; RV64IXQCCMP-NEXT:    .cfi_def_cfa_offset 64
 ; RV64IXQCCMP-NEXT:    qc.cm.pop {ra}, 64
 ; RV64IXQCCMP-NEXT:    .cfi_restore ra
@@ -1744,54 +1748,54 @@ define void @foo_with_irq() "interrupt"="machine" {
 ; RV32IXQCCMP-FP-NEXT:    .cfi_offset s0, -8
 ; RV32IXQCCMP-FP-NEXT:    addi sp, sp, -16
 ; RV32IXQCCMP-FP-NEXT:    .cfi_def_cfa_offset 80
-; RV32IXQCCMP-FP-NEXT:    sw t0, 68(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw t1, 64(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw t2, 60(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw a0, 56(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw a1, 52(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw a2, 48(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw a3, 44(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw a4, 40(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw a5, 36(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw a6, 32(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw a7, 28(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw t3, 24(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw t4, 20(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw t5, 16(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw t6, 12(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset t0, -12
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset t1, -16
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset t2, -20
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset a0, -24
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset a1, -28
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset a2, -32
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset a3, -36
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset a4, -40
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset a5, -44
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset a6, -48
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset a7, -52
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset t3, -56
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset t4, -60
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset t5, -64
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset t6, -68
+; RV32IXQCCMP-FP-NEXT:    sw t0, 60(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw t1, 56(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw t2, 52(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a0, 48(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a1, 44(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a2, 40(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a3, 36(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a4, 32(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a5, 28(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a6, 24(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a7, 20(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw t3, 16(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw t4, 12(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw t5, 8(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw t6, 4(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset t0, -20
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset t1, -24
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset t2, -28
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset a0, -32
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset a1, -36
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset a2, -40
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset a3, -44
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset a4, -48
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset a5, -52
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset a6, -56
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset a7, -60
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset t3, -64
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset t4, -68
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset t5, -72
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset t6, -76
 ; RV32IXQCCMP-FP-NEXT:    .cfi_def_cfa s0, 0
 ; RV32IXQCCMP-FP-NEXT:    call foo_test_irq
 ; RV32IXQCCMP-FP-NEXT:    .cfi_def_cfa sp, 80
-; RV32IXQCCMP-FP-NEXT:    lw t0, 68(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw t1, 64(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw t2, 60(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw a0, 56(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw a1, 52(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw a2, 48(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw a3, 44(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw a4, 40(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw a5, 36(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw a6, 32(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw a7, 28(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw t3, 24(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw t4, 20(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw t5, 16(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw t6, 12(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw t0, 60(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw t1, 56(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw t2, 52(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a0, 48(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a1, 44(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a2, 40(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a3, 36(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a4, 32(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a5, 28(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a6, 24(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a7, 20(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw t3, 16(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw t4, 12(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw t5, 8(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw t6, 4(sp) # 4-byte Folded Reload
 ; RV32IXQCCMP-FP-NEXT:    .cfi_restore t0
 ; RV32IXQCCMP-FP-NEXT:    .cfi_restore t1
 ; RV32IXQCCMP-FP-NEXT:    .cfi_restore t2
@@ -1899,52 +1903,54 @@ define void @foo_with_irq() "interrupt"="machine" {
 ; RV32IXQCCMP-SR-NEXT:    qc.cm.push {ra}, -64
 ; RV32IXQCCMP-SR-NEXT:    .cfi_def_cfa_offset 64
 ; RV32IXQCCMP-SR-NEXT:    .cfi_offset ra, -4
-; RV32IXQCCMP-SR-NEXT:    sw t0, 56(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw t1, 52(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw t2, 48(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw a0, 44(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw a1, 40(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw a2, 36(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw a3, 32(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw a4, 28(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw a5, 24(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw a6, 20(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw a7, 16(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw t3, 12(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw t4, 8(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw t5, 4(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw t6, 0(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset t0, -8
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset t1, -12
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset t2, -16
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset a0, -20
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset a1, -24
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset a2, -28
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset a3, -32
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset a4, -36
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset a5, -40
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset a6, -44
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset a7, -48
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset t3, -52
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset t4, -56
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset t5, -60
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset t6, -64
+; RV32IXQCCMP-SR-NEXT:    addi sp, sp, -16
+; RV32IXQCCMP-SR-NEXT:    .cfi_def_cfa_offset 80
+; RV32IXQCCMP-SR-NEXT:    sw t0, 60(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw t1, 56(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw t2, 52(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a0, 48(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a1, 44(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a2, 40(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a3, 36(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a4, 32(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a5, 28(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a6, 24(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a7, 20(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw t3, 16(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw t4, 12(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw t5, 8(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw t6, 4(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset t0, -20
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset t1, -24
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset t2, -28
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset a0, -32
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset a1, -36
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset a2, -40
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset a3, -44
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset a4, -48
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset a5, -52
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset a6, -56
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset a7, -60
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset t3, -64
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset t4, -68
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset t5, -72
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset t6, -76
 ; RV32IXQCCMP-SR-NEXT:    call foo_test_irq
-; RV32IXQCCMP-SR-NEXT:    lw t0, 56(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw t1, 52(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw t2, 48(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw a0, 44(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw a1, 40(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw a2, 36(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw a3, 32(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw a4, 28(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw a5, 24(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw a6, 20(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw a7, 16(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw t3, 12(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw t4, 8(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw t5, 4(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw t6, 0(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw t0, 60(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw t1, 56(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw t2, 52(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw a0, 48(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw a1, 44(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw a2, 40(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw a3, 36(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw a4, 32(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw a5, 28(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw a6, 24(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw a7, 20(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw t3, 16(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw t4, 12(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw t5, 8(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw t6, 4(sp) # 4-byte Folded Reload
 ; RV32IXQCCMP-SR-NEXT:    .cfi_restore t0
 ; RV32IXQCCMP-SR-NEXT:    .cfi_restore t1
 ; RV32IXQCCMP-SR-NEXT:    .cfi_restore t2
@@ -1960,6 +1966,8 @@ define void @foo_with_irq() "interrupt"="machine" {
 ; RV32IXQCCMP-SR-NEXT:    .cfi_restore t4
 ; RV32IXQCCMP-SR-NEXT:    .cfi_restore t5
 ; RV32IXQCCMP-SR-NEXT:    .cfi_restore t6
+; RV32IXQCCMP-SR-NEXT:    addi sp, sp, 16
+; RV32IXQCCMP-SR-NEXT:    .cfi_def_cfa_offset 64
 ; RV32IXQCCMP-SR-NEXT:    qc.cm.pop {ra}, 64
 ; RV32IXQCCMP-SR-NEXT:    .cfi_restore ra
 ; RV32IXQCCMP-SR-NEXT:    .cfi_def_cfa_offset 0
@@ -1970,54 +1978,54 @@ define void @foo_with_irq() "interrupt"="machine" {
 ; RV64IXQCCMP-SR-NEXT:    qc.cm.push {ra}, -64
 ; RV64IXQCCMP-SR-NEXT:    .cfi_def_cfa_offset 64
 ; RV64IXQCCMP-SR-NEXT:    .cfi_offset ra, -8
-; RV64IXQCCMP-SR-NEXT:    addi sp, sp, -64
-; RV64IXQCCMP-SR-NEXT:    .cfi_def_cfa_offset 128
-; RV64IXQCCMP-SR-NEXT:    sd t0, 112(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd t1, 104(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd t2, 96(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd a0, 88(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd a1, 80(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd a2, 72(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd a3, 64(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd a4, 56(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd a5, 48(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd a6, 40(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd a7, 32(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd t3, 24(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd t4, 16(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd t5, 8(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd t6, 0(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset t0, -16
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset t1, -24
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset t2, -32
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset a0, -40
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset a1, -48
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset a2, -56
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset a3, -64
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset a4, -72
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset a5, -80
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset a6, -88
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset a7, -96
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset t3, -104
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset t4, -112
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset t5, -120
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset t6, -128
+; RV64IXQCCMP-SR-NEXT:    addi sp, sp, -80
+; RV64IXQCCMP-SR-NEXT:    .cfi_def_cfa_offset 144
+; RV64IXQCCMP-SR-NEXT:    sd t0, 120(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd t1, 112(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd t2, 104(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd a0, 96(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd a1, 88(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd a2, 80(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd a3, 72(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd a4, 64(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd a5, 56(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd a6, 48(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd a7, 40(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd t3, 32(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd t4, 24(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd t5, 16(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd t6, 8(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset t0, -24
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset t1, -32
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset t2, -40
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset a0, -48
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset a1, -56
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset a2, -64
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset a3, -72
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset a4, -80
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset a5, -88
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset a6, -96
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset a7, -104
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset t3, -112
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset t4, -120
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset t5, -128
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset t6, -136
 ; RV64IXQCCMP-SR-NEXT:    call foo_test_irq
-; RV64IXQCCMP-SR-NEXT:    ld t0, 112(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld t1, 104(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld t2, 96(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld a0, 88(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld a1, 80(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld a2, 72(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld a3, 64(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld a4, 56(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld a5, 48(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld a6, 40(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld a7, 32(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld t3, 24(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld t4, 16(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld t5, 8(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld t6, 0(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld t0, 120(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld t1, 112(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld t2, 104(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld a0, 96(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld a1, 88(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld a2, 80(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld a3, 72(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld a4, 64(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld a5, 56(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld a6, 48(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld a7, 40(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld t3, 32(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld t4, 24(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld t5, 16(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld t6, 8(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-SR-NEXT:    .cfi_restore t0
 ; RV64IXQCCMP-SR-NEXT:    .cfi_restore t1
 ; RV64IXQCCMP-SR-NEXT:    .cfi_restore t2
@@ -2033,7 +2041,7 @@ define void @foo_with_irq() "interrupt"="machine" {
 ; RV64IXQCCMP-SR-NEXT:    .cfi_restore t4
 ; RV64IXQCCMP-SR-NEXT:    .cfi_restore t5
 ; RV64IXQCCMP-SR-NEXT:    .cfi_restore t6
-; RV64IXQCCMP-SR-NEXT:    addi sp, sp, 64
+; RV64IXQCCMP-SR-NEXT:    addi sp, sp, 80
 ; RV64IXQCCMP-SR-NEXT:    .cfi_def_cfa_offset 64
 ; RV64IXQCCMP-SR-NEXT:    qc.cm.pop {ra}, 64
 ; RV64IXQCCMP-SR-NEXT:    .cfi_restore ra
@@ -2119,52 +2127,52 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV32IXQCCMP-NEXT:    .cfi_offset s9, -44
 ; RV32IXQCCMP-NEXT:    .cfi_offset s10, -48
 ; RV32IXQCCMP-NEXT:    .cfi_offset s11, -52
-; RV32IXQCCMP-NEXT:    addi sp, sp, -32
-; RV32IXQCCMP-NEXT:    .cfi_def_cfa_offset 144
-; RV32IXQCCMP-NEXT:    sw t0, 88(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw t1, 84(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw t2, 80(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw a0, 76(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw a1, 72(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw a2, 68(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw a3, 64(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw a4, 60(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw a5, 56(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw a6, 52(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw a7, 48(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw t3, 44(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw t4, 40(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw t5, 36(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    sw t6, 32(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT:    .cfi_offset t0, -56
-; RV32IXQCCMP-NEXT:    .cfi_offset t1, -60
-; RV32IXQCCMP-NEXT:    .cfi_offset t2, -64
-; RV32IXQCCMP-NEXT:    .cfi_offset a0, -68
-; RV32IXQCCMP-NEXT:    .cfi_offset a1, -72
-; RV32IXQCCMP-NEXT:    .cfi_offset a2, -76
-; RV32IXQCCMP-NEXT:    .cfi_offset a3, -80
-; RV32IXQCCMP-NEXT:    .cfi_offset a4, -84
-; RV32IXQCCMP-NEXT:    .cfi_offset a5, -88
-; RV32IXQCCMP-NEXT:    .cfi_offset a6, -92
-; RV32IXQCCMP-NEXT:    .cfi_offset a7, -96
-; RV32IXQCCMP-NEXT:    .cfi_offset t3, -100
-; RV32IXQCCMP-NEXT:    .cfi_offset t4, -104
-; RV32IXQCCMP-NEXT:    .cfi_offset t5, -108
-; RV32IXQCCMP-NEXT:    .cfi_offset t6, -112
+; RV32IXQCCMP-NEXT:    addi sp, sp, -48
+; RV32IXQCCMP-NEXT:    .cfi_def_cfa_offset 160
+; RV32IXQCCMP-NEXT:    sw t0, 92(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw t1, 88(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw t2, 84(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 80(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a1, 76(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a2, 72(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a3, 68(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a4, 64(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a5, 60(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a6, 56(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a7, 52(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw t3, 48(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw t4, 44(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw t5, 40(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw t6, 36(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    .cfi_offset t0, -68
+; RV32IXQCCMP-NEXT:    .cfi_offset t1, -72
+; RV32IXQCCMP-NEXT:    .cfi_offset t2, -76
+; RV32IXQCCMP-NEXT:    .cfi_offset a0, -80
+; RV32IXQCCMP-NEXT:    .cfi_offset a1, -84
+; RV32IXQCCMP-NEXT:    .cfi_offset a2, -88
+; RV32IXQCCMP-NEXT:    .cfi_offset a3, -92
+; RV32IXQCCMP-NEXT:    .cfi_offset a4, -96
+; RV32IXQCCMP-NEXT:    .cfi_offset a5, -100
+; RV32IXQCCMP-NEXT:    .cfi_offset a6, -104
+; RV32IXQCCMP-NEXT:    .cfi_offset a7, -108
+; RV32IXQCCMP-NEXT:    .cfi_offset t3, -112
+; RV32IXQCCMP-NEXT:    .cfi_offset t4, -116
+; RV32IXQCCMP-NEXT:    .cfi_offset t5, -120
+; RV32IXQCCMP-NEXT:    .cfi_offset t6, -124
 ; RV32IXQCCMP-NEXT:    lui t0, %hi(var_test_irq)
 ; RV32IXQCCMP-NEXT:    lw a0, %lo(var_test_irq)(t0)
-; RV32IXQCCMP-NEXT:    sw a0, 28(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 32(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, %lo(var_test_irq+4)(t0)
-; RV32IXQCCMP-NEXT:    sw a0, 24(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 28(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, %lo(var_test_irq+8)(t0)
-; RV32IXQCCMP-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 24(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, %lo(var_test_irq+12)(t0)
-; RV32IXQCCMP-NEXT:    sw a0, 16(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    addi a5, t0, %lo(var_test_irq)
 ; RV32IXQCCMP-NEXT:    lw a0, 16(a5)
-; RV32IXQCCMP-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 16(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, 20(a5)
-; RV32IXQCCMP-NEXT:    sw a0, 8(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw t4, 24(a5)
 ; RV32IXQCCMP-NEXT:    lw t5, 28(a5)
 ; RV32IXQCCMP-NEXT:    lw t6, 32(a5)
@@ -2217,33 +2225,33 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV32IXQCCMP-NEXT:    sw t6, 32(a5)
 ; RV32IXQCCMP-NEXT:    sw t5, 28(a5)
 ; RV32IXQCCMP-NEXT:    sw t4, 24(a5)
-; RV32IXQCCMP-NEXT:    lw a0, 8(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, 20(a5)
 ; RV32IXQCCMP-NEXT:    lw a0, 12(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, 16(a5)
+; RV32IXQCCMP-NEXT:    sw a0, 20(a5)
 ; RV32IXQCCMP-NEXT:    lw a0, 16(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
+; RV32IXQCCMP-NEXT:    sw a0, 16(a5)
 ; RV32IXQCCMP-NEXT:    lw a0, 20(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
+; RV32IXQCCMP-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
 ; RV32IXQCCMP-NEXT:    lw a0, 24(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
+; RV32IXQCCMP-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
 ; RV32IXQCCMP-NEXT:    lw a0, 28(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
+; RV32IXQCCMP-NEXT:    lw a0, 32(sp) # 4-byte Folded Reload
 ; RV32IXQCCMP-NEXT:    sw a0, %lo(var_test_irq)(t0)
-; RV32IXQCCMP-NEXT:    lw t0, 88(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw t1, 84(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw t2, 80(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw a0, 76(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw a1, 72(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw a2, 68(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw a3, 64(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw a4, 60(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw a5, 56(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw a6, 52(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw a7, 48(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw t3, 44(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw t4, 40(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw t5, 36(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    lw t6, 32(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw t0, 92(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw t1, 88(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw t2, 84(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw a0, 80(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw a1, 76(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw a2, 72(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw a3, 68(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw a4, 64(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw a5, 60(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw a6, 56(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw a7, 52(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw t3, 48(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw t4, 44(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw t5, 40(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    lw t6, 36(sp) # 4-byte Folded Reload
 ; RV32IXQCCMP-NEXT:    .cfi_restore t0
 ; RV32IXQCCMP-NEXT:    .cfi_restore t1
 ; RV32IXQCCMP-NEXT:    .cfi_restore t2
@@ -2259,7 +2267,7 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV32IXQCCMP-NEXT:    .cfi_restore t4
 ; RV32IXQCCMP-NEXT:    .cfi_restore t5
 ; RV32IXQCCMP-NEXT:    .cfi_restore t6
-; RV32IXQCCMP-NEXT:    addi sp, sp, 32
+; RV32IXQCCMP-NEXT:    addi sp, sp, 48
 ; RV32IXQCCMP-NEXT:    .cfi_def_cfa_offset 112
 ; RV32IXQCCMP-NEXT:    qc.cm.pop {ra, s0-s11}, 112
 ; RV32IXQCCMP-NEXT:    .cfi_restore ra
@@ -2295,52 +2303,52 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV64IXQCCMP-NEXT:    .cfi_offset s9, -88
 ; RV64IXQCCMP-NEXT:    .cfi_offset s10, -96
 ; RV64IXQCCMP-NEXT:    .cfi_offset s11, -104
-; RV64IXQCCMP-NEXT:    addi sp, sp, -112
-; RV64IXQCCMP-NEXT:    .cfi_def_cfa_offset 272
-; RV64IXQCCMP-NEXT:    sd t0, 160(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd t1, 152(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd t2, 144(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd a0, 136(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd a1, 128(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd a2, 120(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd a3, 112(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd a4, 104(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd a5, 96(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd a6, 88(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd a7, 80(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd t3, 72(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd t4, 64(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd t5, 56(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    sd t6, 48(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    .cfi_offset t0, -112
-; RV64IXQCCMP-NEXT:    .cfi_offset t1, -120
-; RV64IXQCCMP-NEXT:    .cfi_offset t2, -128
-; RV64IXQCCMP-NEXT:    .cfi_offset a0, -136
-; RV64IXQCCMP-NEXT:    .cfi_offset a1, -144
-; RV64IXQCCMP-NEXT:    .cfi_offset a2, -152
-; RV64IXQCCMP-NEXT:    .cfi_offset a3, -160
-; RV64IXQCCMP-NEXT:    .cfi_offset a4, -168
-; RV64IXQCCMP-NEXT:    .cfi_offset a5, -176
-; RV64IXQCCMP-NEXT:    .cfi_offset a6, -184
-; RV64IXQCCMP-NEXT:    .cfi_offset a7, -192
-; RV64IXQCCMP-NEXT:    .cfi_offset t3, -200
-; RV64IXQCCMP-NEXT:    .cfi_offset t4, -208
-; RV64IXQCCMP-NEXT:    .cfi_offset t5, -216
-; RV64IXQCCMP-NEXT:    .cfi_offset t6, -224
+; RV64IXQCCMP-NEXT:    addi sp, sp, -128
+; RV64IXQCCMP-NEXT:    .cfi_def_cfa_offset 288
+; RV64IXQCCMP-NEXT:    sd t0, 168(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd t1, 160(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd t2, 152(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd a0, 144(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd a1, 136(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd a2, 128(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd a3, 120(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd a4, 112(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd a5, 104(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd a6, 96(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd a7, 88(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd t3, 80(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd t4, 72(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd t5, 64(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd t6, 56(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    .cfi_offset t0, -120
+; RV64IXQCCMP-NEXT:    .cfi_offset t1, -128
+; RV64IXQCCMP-NEXT:    .cfi_offset t2, -136
+; RV64IXQCCMP-NEXT:    .cfi_offset a0, -144
+; RV64IXQCCMP-NEXT:    .cfi_offset a1, -152
+; RV64IXQCCMP-NEXT:    .cfi_offset a2, -160
+; RV64IXQCCMP-NEXT:    .cfi_offset a3, -168
+; RV64IXQCCMP-NEXT:    .cfi_offset a4, -176
+; RV64IXQCCMP-NEXT:    .cfi_offset a5, -184
+; RV64IXQCCMP-NEXT:    .cfi_offset a6, -192
+; RV64IXQCCMP-NEXT:    .cfi_offset a7, -200
+; RV64IXQCCMP-NEXT:    .cfi_offset t3, -208
+; RV64IXQCCMP-NEXT:    .cfi_offset t4, -216
+; RV64IXQCCMP-NEXT:    .cfi_offset t5, -224
+; RV64IXQCCMP-NEXT:    .cfi_offset t6, -232
 ; RV64IXQCCMP-NEXT:    lui t0, %hi(var_test_irq)
 ; RV64IXQCCMP-NEXT:    lw a0, %lo(var_test_irq)(t0)
-; RV64IXQCCMP-NEXT:    sd a0, 40(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd a0, 48(sp) # 8-byte Folded Spill
 ; RV64IXQCCMP-NEXT:    lw a0, %lo(var_test_irq+4)(t0)
-; RV64IXQCCMP-NEXT:    sd a0, 32(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd a0, 40(sp) # 8-byte Folded Spill
 ; RV64IXQCCMP-NEXT:    lw a0, %lo(var_test_irq+8)(t0)
-; RV64IXQCCMP-NEXT:    sd a0, 24(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd a0, 32(sp) # 8-byte Folded Spill
 ; RV64IXQCCMP-NEXT:    lw a0, %lo(var_test_irq+12)(t0)
-; RV64IXQCCMP-NEXT:    sd a0, 16(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd a0, 24(sp) # 8-byte Folded Spill
 ; RV64IXQCCMP-NEXT:    addi a5, t0, %lo(var_test_irq)
 ; RV64IXQCCMP-NEXT:    lw a0, 16(a5)
-; RV64IXQCCMP-NEXT:    sd a0, 8(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd a0, 16(sp) # 8-byte Folded Spill
 ; RV64IXQCCMP-NEXT:    lw a0, 20(a5)
-; RV64IXQCCMP-NEXT:    sd a0, 0(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    sd a0, 8(sp) # 8-byte Folded Spill
 ; RV64IXQCCMP-NEXT:    lw t4, 24(a5)
 ; RV64IXQCCMP-NEXT:    lw t5, 28(a5)
 ; RV64IXQCCMP-NEXT:    lw t6, 32(a5)
@@ -2393,33 +2401,33 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV64IXQCCMP-NEXT:    sw t6, 32(a5)
 ; RV64IXQCCMP-NEXT:    sw t5, 28(a5)
 ; RV64IXQCCMP-NEXT:    sw t4, 24(a5)
-; RV64IXQCCMP-NEXT:    ld a0, 0(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    sw a0, 20(a5)
 ; RV64IXQCCMP-NEXT:    ld a0, 8(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    sw a0, 16(a5)
+; RV64IXQCCMP-NEXT:    sw a0, 20(a5)
 ; RV64IXQCCMP-NEXT:    ld a0, 16(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
+; RV64IXQCCMP-NEXT:    sw a0, 16(a5)
 ; RV64IXQCCMP-NEXT:    ld a0, 24(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
+; RV64IXQCCMP-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
 ; RV64IXQCCMP-NEXT:    ld a0, 32(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
+; RV64IXQCCMP-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
 ; RV64IXQCCMP-NEXT:    ld a0, 40(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
+; RV64IXQCCMP-NEXT:    ld a0, 48(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, %lo(var_test_irq)(t0)
-; RV64IXQCCMP-NEXT:    ld t0, 160(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld t1, 152(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld t2, 144(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld a0, 136(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld a1, 128(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld a2, 120(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld a3, 112(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld a4, 104(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld a5, 96(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld a6, 88(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld a7, 80(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld t3, 72(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld t4, 64(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld t5, 56(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT:    ld t6, 48(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld t0, 168(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld t1, 160(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld t2, 152(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 144(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a1, 136(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a2, 128(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a3, 120(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a4, 112(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a5, 104(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a6, 96(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a7, 88(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld t3, 80(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld t4, 72(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld t5, 64(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld t6, 56(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    .cfi_restore t0
 ; RV64IXQCCMP-NEXT:    .cfi_restore t1
 ; RV64IXQCCMP-NEXT:    .cfi_restore t2
@@ -2435,7 +2443,7 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV64IXQCCMP-NEXT:    .cfi_restore t4
 ; RV64IXQCCMP-NEXT:    .cfi_restore t5
 ; RV64IXQCCMP-NEXT:    .cfi_restore t6
-; RV64IXQCCMP-NEXT:    addi sp, sp, 112
+; RV64IXQCCMP-NEXT:    addi sp, sp, 128
 ; RV64IXQCCMP-NEXT:    .cfi_def_cfa_offset 160
 ; RV64IXQCCMP-NEXT:    qc.cm.pop {ra, s0-s11}, 160
 ; RV64IXQCCMP-NEXT:    .cfi_restore ra
@@ -2471,55 +2479,55 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV32IXQCCMP-FP-NEXT:    .cfi_offset s9, -44
 ; RV32IXQCCMP-FP-NEXT:    .cfi_offset s10, -48
 ; RV32IXQCCMP-FP-NEXT:    .cfi_offset s11, -52
-; RV32IXQCCMP-FP-NEXT:    addi sp, sp, -32
-; RV32IXQCCMP-FP-NEXT:    .cfi_def_cfa_offset 144
-; RV32IXQCCMP-FP-NEXT:    sw t0, 88(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw t1, 84(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw t2, 80(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw a0, 76(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw a1, 72(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw a2, 68(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw a3, 64(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw a4, 60(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw a5, 56(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw a6, 52(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw a7, 48(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw t3, 44(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw t4, 40(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw t5, 36(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    sw t6, 32(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset t0, -56
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset t1, -60
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset t2, -64
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset a0, -68
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset a1, -72
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset a2, -76
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset a3, -80
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset a4, -84
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset a5, -88
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset a6, -92
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset a7, -96
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset t3, -100
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset t4, -104
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset t5, -108
-; RV32IXQCCMP-FP-NEXT:    .cfi_offset t6, -112
+; RV32IXQCCMP-FP-NEXT:    addi sp, sp, -48
+; RV32IXQCCMP-FP-NEXT:    .cfi_def_cfa_offset 160
+; RV32IXQCCMP-FP-NEXT:    sw t0, 92(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw t1, 88(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw t2, 84(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a0, 80(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a1, 76(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a2, 72(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a3, 68(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a4, 64(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a5, 60(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a6, 56(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a7, 52(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw t3, 48(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw t4, 44(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw t5, 40(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw t6, 36(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset t0, -68
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset t1, -72
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset t2, -76
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset a0, -80
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset a1, -84
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset a2, -88
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset a3, -92
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset a4, -96
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset a5, -100
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset a6, -104
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset a7, -108
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset t3, -112
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset t4, -116
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset t5, -120
+; RV32IXQCCMP-FP-NEXT:    .cfi_offset t6, -124
 ; RV32IXQCCMP-FP-NEXT:    .cfi_def_cfa s0, 0
 ; RV32IXQCCMP-FP-NEXT:    lui t1, %hi(var_test_irq)
 ; RV32IXQCCMP-FP-NEXT:    lw a0, %lo(var_test_irq)(t1)
-; RV32IXQCCMP-FP-NEXT:    sw a0, -116(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a0, -128(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-FP-NEXT:    lw a0, %lo(var_test_irq+4)(t1)
-; RV32IXQCCMP-FP-NEXT:    sw a0, -120(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a0, -132(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-FP-NEXT:    lw a0, %lo(var_test_irq+8)(t1)
-; RV32IXQCCMP-FP-NEXT:    sw a0, -124(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a0, -136(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-FP-NEXT:    lw a0, %lo(var_test_irq+12)(t1)
-; RV32IXQCCMP-FP-NEXT:    sw a0, -128(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a0, -140(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-FP-NEXT:    addi a5, t1, %lo(var_test_irq)
 ; RV32IXQCCMP-FP-NEXT:    lw a0, 16(a5)
-; RV32IXQCCMP-FP-NEXT:    sw a0, -132(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a0, -144(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-FP-NEXT:    lw a0, 20(a5)
-; RV32IXQCCMP-FP-NEXT:    sw a0, -136(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a0, -148(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-FP-NEXT:    lw a0, 24(a5)
-; RV32IXQCCMP-FP-NEXT:    sw a0, -140(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a0, -152(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-FP-NEXT:    lw t5, 28(a5)
 ; RV32IXQCCMP-FP-NEXT:    lw t6, 32(a5)
 ; RV32IXQCCMP-FP-NEXT:    lw s2, 36(a5)
@@ -2570,36 +2578,36 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV32IXQCCMP-FP-NEXT:    sw s2, 36(a5)
 ; RV32IXQCCMP-FP-NEXT:    sw t6, 32(a5)
 ; RV32IXQCCMP-FP-NEXT:    sw t5, 28(a5)
-; RV32IXQCCMP-FP-NEXT:    lw a0, -140(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a0, -152(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-FP-NEXT:    sw a0, 24(a5)
-; RV32IXQCCMP-FP-NEXT:    lw a0, -136(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a0, -148(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-FP-NEXT:    sw a0, 20(a5)
-; RV32IXQCCMP-FP-NEXT:    lw a0, -132(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a0, -144(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-FP-NEXT:    sw a0, 16(a5)
-; RV32IXQCCMP-FP-NEXT:    lw a0, -128(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a0, -140(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-FP-NEXT:    sw a0, %lo(var_test_irq+12)(t1)
-; RV32IXQCCMP-FP-NEXT:    lw a0, -124(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a0, -136(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-FP-NEXT:    sw a0, %lo(var_test_irq+8)(t1)
-; RV32IXQCCMP-FP-NEXT:    lw a0, -120(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a0, -132(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-FP-NEXT:    sw a0, %lo(var_test_irq+4)(t1)
-; RV32IXQCCMP-FP-NEXT:    lw a0, -116(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a0, -128(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-FP-NEXT:    sw a0, %lo(var_test_irq)(t1)
-; RV32IXQCCMP-FP-NEXT:    .cfi_def_cfa sp, 144
-; RV32IXQCCMP-FP-NEXT:    lw t0, 88(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw t1, 84(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw t2, 80(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw a0, 76(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw a1, 72(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw a2, 68(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw a3, 64(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw a4, 60(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw a5, 56(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw a6, 52(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw a7, 48(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw t3, 44(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw t4, 40(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw t5, 36(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT:    lw t6, 32(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    .cfi_def_cfa sp, 160
+; RV32IXQCCMP-FP-NEXT:    lw t0, 92(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw t1, 88(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw t2, 84(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a0, 80(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a1, 76(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a2, 72(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a3, 68(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a4, 64(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a5, 60(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a6, 56(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a7, 52(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw t3, 48(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw t4, 44(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw t5, 40(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw t6, 36(sp) # 4-byte Folded Reload
 ; RV32IXQCCMP-FP-NEXT:    .cfi_restore t0
 ; RV32IXQCCMP-FP-NEXT:    .cfi_restore t1
 ; RV32IXQCCMP-FP-NEXT:    .cfi_restore t2
@@ -2615,7 +2623,7 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV32IXQCCMP-FP-NEXT:    .cfi_restore t4
 ; RV32IXQCCMP-FP-NEXT:    .cfi_restore t5
 ; RV32IXQCCMP-FP-NEXT:    .cfi_restore t6
-; RV32IXQCCMP-FP-NEXT:    addi sp, sp, 32
+; RV32IXQCCMP-FP-NEXT:    addi sp, sp, 48
 ; RV32IXQCCMP-FP-NEXT:    .cfi_def_cfa_offset 112
 ; RV32IXQCCMP-FP-NEXT:    qc.cm.pop {ra, s0-s11}, 112
 ; RV32IXQCCMP-FP-NEXT:    .cfi_restore ra
@@ -2653,53 +2661,53 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV64IXQCCMP-FP-NEXT:    .cfi_offset s11, -104
 ; RV64IXQCCMP-FP-NEXT:    addi sp, sp, -128
 ; RV64IXQCCMP-FP-NEXT:    .cfi_def_cfa_offset 288
-; RV64IXQCCMP-FP-NEXT:    sd t0, 176(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT:    sd t1, 168(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT:    sd t2, 160(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT:    sd a0, 152(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT:    sd a1, 144(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT:    sd a2, 136(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT:    sd a3, 128(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT:    sd a4, 120(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT:    sd a5, 112(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT:    sd a6, 104(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT:    sd a7, 96(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT:    sd t3, 88(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT:    sd t4, 80(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT:    sd t5, 72(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT:    sd t6, 64(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT:    .cfi_offset t0, -112
-; RV64IXQCCMP-FP-NEXT:    .cfi_offset t1, -120
-; RV64IXQCCMP-FP-NEXT:    .cfi_offset t2, -128
-; RV64IXQCCMP-FP-NEXT:    .cfi_offset a0, -136
-; RV64IXQCCMP-FP-NEXT:    .cfi_offset a1, -144
-; RV64IXQCCMP-FP-NEXT:    .cfi_offset a2, -152
-; RV64IXQCCMP-FP-NEXT:    .cfi_offset a3, -160
-; RV64IXQCCMP-FP-NEXT:    .cfi_offset a4, -168
-; RV64IXQCCMP-FP-NEXT:    .cfi_offset a5, -176
-; RV64IXQCCMP-FP-NEXT:    .cfi_offset a6, -184
-; RV64IXQCCMP-FP-NEXT:    .cfi_offset a7, -192
-; RV64IXQCCMP-FP-NEXT:    .cfi_offset t3, -200
-; RV64IXQCCMP-FP-NEXT:    .cfi_offset t4, -208
-; RV64IXQCCMP-FP-NEXT:    .cfi_offset t5, -216
-; RV64IXQCCMP-FP-NEXT:    .cfi_offset t6, -224
+; RV64IXQCCMP-FP-NEXT:    sd t0, 168(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT:    sd t1, 160(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT:    sd t2, 152(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT:    sd a0, 144(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT:    sd a1, 136(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT:    sd a2, 128(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT:    sd a3, 120(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT:    sd a4, 112(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT:    sd a5, 104(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT:    sd a6, 96(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT:    sd a7, 88(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT:    sd t3, 80(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT:    sd t4, 72(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT:    sd t5, 64(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT:    sd t6, 56(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT:    .cfi_offset t0, -120
+; RV64IXQCCMP-FP-NEXT:    .cfi_offset t1, -128
+; RV64IXQCCMP-FP-NEXT:    .cfi_offset t2, -136
+; RV64IXQCCMP-FP-NEXT:    .cfi_offset a0, -144
+; RV64IXQCCMP-FP-NEXT:    .cfi_offset a1, -152
+; RV64IXQCCMP-FP-NEXT:    .cfi_offset a2, -160
+; RV64IXQCCMP-FP-NEXT:    .cfi_offset a3, -168
+; RV64IXQCCMP-FP-NEXT:    .cfi_offset a4, -176
+; RV64IXQCCMP-FP-NEXT:    .cfi_offset a5, -184
+; RV64IXQCCMP-FP-NEXT:    .cfi_offset a6, -192
+; RV64IXQCCMP-FP-NEXT:    .cfi_offset a7, -200
+; RV64IXQCCMP-FP-NEXT:    .cfi_offset t3, -208
+; RV64IXQCCMP-FP-NEXT:    .cfi_offset t4, -216
+; RV64IXQCCMP-FP-NEXT:    .cfi_offset t5, -224
+; RV64IXQCCMP-FP-NEXT:    .cfi_offset t6, -232
 ; RV64IXQCCMP-FP-NEXT:    .cfi_def_cfa s0, 0
 ; RV64IXQCCMP-FP-NEXT:    lui t1, %hi(var_test_irq)
 ; RV64IXQCCMP-FP-NEXT:    lw a0, %lo(var_test_irq)(t1)
-; RV64IXQCCMP-FP-NEXT:    sd a0, -232(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT:    lw a0, %lo(var_test_irq+4)(t1)
 ; RV64IXQCCMP-FP-NEXT:    sd a0, -240(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT:    lw a0, %lo(var_test_irq+8)(t1)
+; RV64IXQCCMP-FP-NEXT:    lw a0, %lo(var_test_irq+4)(t1)
 ; RV64IXQCCMP-FP-NEXT:    sd a0, -248(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT:    lw a0, %lo(var_test_irq+12)(t1)
+; RV64IXQCCMP-FP-NEXT:    lw a0, %lo(var_test_irq+8)(t1)
 ; RV64IXQCCMP-FP-NEXT:    sd a0, -256(s0) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT:    lw a0, %lo(var_test_irq+12)(t1)
+; RV64IXQCCMP-FP-NEXT:    sd a0, -264(s0) # 8-byte Folded Spill
 ; RV64IXQCCMP-FP-NEXT:    addi a5, t1, %lo(var_test_irq)
 ; RV64IXQCCMP-FP-NEXT:    lw a0, 16(a5)
-; RV64IXQCCMP-FP-NEXT:    sd a0, -264(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT:    lw a0, 20(a5)
 ; RV64IXQCCMP-FP-NEXT:    sd a0, -272(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT:    lw a0, 24(a5)
+; RV64IXQCCMP-FP-NEXT:    lw a0, 20(a5)
 ; RV64IXQCCMP-FP-NEXT:    sd a0, -280(s0) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT:    lw a0, 24(a5)
+; RV64IXQCCMP-FP-NEXT:    sd a0, -288(s0) # 8-byte Folded Spill
 ; RV64IXQCCMP-FP-NEXT:    lw t5, 28(a5)
 ; RV64IXQCCMP-FP-NEXT:    lw t6, 32(a5)
 ; RV64IXQCCMP-FP-NEXT:    lw s2, 36(a5)
@@ -2750,36 +2758,36 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV64IXQCCMP-FP-NEXT:    sw s2, 36(a5)
 ; RV64IXQCCMP-FP-NEXT:    sw t6, 32(a5)
 ; RV64IXQCCMP-FP-NEXT:    sw t5, 28(a5)
-; RV64IXQCCMP-FP-NEXT:    ld a0, -280(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld a0, -288(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-FP-NEXT:    sw a0, 24(a5)
-; RV64IXQCCMP-FP-NEXT:    ld a0, -272(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld a0, -280(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-FP-NEXT:    sw a0, 20(a5)
-; RV64IXQCCMP-FP-NEXT:    ld a0, -264(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld a0, -272(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-FP-NEXT:    sw a0, 16(a5)
-; RV64IXQCCMP-FP-NEXT:    ld a0, -256(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld a0, -264(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-FP-NEXT:    sw a0, %lo(var_test_irq+12)(t1)
-; RV64IXQCCMP-FP-NEXT:    ld a0, -248(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld a0, -256(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-FP-NEXT:    sw a0, %lo(var_test_irq+8)(t1)
-; RV64IXQCCMP-FP-NEXT:    ld a0, -240(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld a0, -248(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-FP-NEXT:    sw a0, %lo(var_test_irq+4)(t1)
-; RV64IXQCCMP-FP-NEXT:    ld a0, -232(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld a0, -240(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-FP-NEXT:    sw a0, %lo(var_test_irq)(t1)
 ; RV64IXQCCMP-FP-NEXT:    .cfi_def_cfa sp, 288
-; RV64IXQCCMP-FP-NEXT:    ld t0, 176(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT:    ld t1, 168(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT:    ld t2, 160(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT:    ld a0, 152(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT:    ld a1, 144(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT:    ld a2, 136(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT:    ld a3, 128(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT:    ld a4, 120(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT:    ld a5, 112(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT:    ld a6, 104(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT:    ld a7, 96(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT:    ld t3, 88(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT:    ld t4, 80(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT:    ld t5, 72(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT:    ld t6, 64(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld t0, 168(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld t1, 160(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld t2, 152(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld a0, 144(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld a1, 136(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld a2, 128(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld a3, 120(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld a4, 112(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld a5, 104(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld a6, 96(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld a7, 88(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld t3, 80(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld t4, 72(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld t5, 64(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld t6, 56(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-FP-NEXT:    .cfi_restore t0
 ; RV64IXQCCMP-FP-NEXT:    .cfi_restore t1
 ; RV64IXQCCMP-FP-NEXT:    .cfi_restore t2
@@ -2831,52 +2839,52 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV32IXQCCMP-SR-NEXT:    .cfi_offset s9, -44
 ; RV32IXQCCMP-SR-NEXT:    .cfi_offset s10, -48
 ; RV32IXQCCMP-SR-NEXT:    .cfi_offset s11, -52
-; RV32IXQCCMP-SR-NEXT:    addi sp, sp, -32
-; RV32IXQCCMP-SR-NEXT:    .cfi_def_cfa_offset 144
-; RV32IXQCCMP-SR-NEXT:    sw t0, 88(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw t1, 84(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw t2, 80(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw a0, 76(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw a1, 72(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw a2, 68(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw a3, 64(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw a4, 60(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw a5, 56(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw a6, 52(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw a7, 48(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw t3, 44(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw t4, 40(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw t5, 36(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    sw t6, 32(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset t0, -56
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset t1, -60
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset t2, -64
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset a0, -68
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset a1, -72
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset a2, -76
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset a3, -80
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset a4, -84
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset a5, -88
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset a6, -92
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset a7, -96
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset t3, -100
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset t4, -104
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset t5, -108
-; RV32IXQCCMP-SR-NEXT:    .cfi_offset t6, -112
+; RV32IXQCCMP-SR-NEXT:    addi sp, sp, -48
+; RV32IXQCCMP-SR-NEXT:    .cfi_def_cfa_offset 160
+; RV32IXQCCMP-SR-NEXT:    sw t0, 92(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw t1, 88(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw t2, 84(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a0, 80(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a1, 76(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a2, 72(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a3, 68(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a4, 64(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a5, 60(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a6, 56(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a7, 52(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw t3, 48(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw t4, 44(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw t5, 40(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw t6, 36(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset t0, -68
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset t1, -72
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset t2, -76
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset a0, -80
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset a1, -84
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset a2, -88
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset a3, -92
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset a4, -96
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset a5, -100
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset a6, -104
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset a7, -108
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset t3, -112
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset t4, -116
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset t5, -120
+; RV32IXQCCMP-SR-NEXT:    .cfi_offset t6, -124
 ; RV32IXQCCMP-SR-NEXT:    lui t0, %hi(var_test_irq)
 ; RV32IXQCCMP-SR-NEXT:    lw a0, %lo(var_test_irq)(t0)
-; RV32IXQCCMP-SR-NEXT:    sw a0, 28(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a0, 32(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-SR-NEXT:    lw a0, %lo(var_test_irq+4)(t0)
-; RV32IXQCCMP-SR-NEXT:    sw a0, 24(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a0, 28(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-SR-NEXT:    lw a0, %lo(var_test_irq+8)(t0)
-; RV32IXQCCMP-SR-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a0, 24(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-SR-NEXT:    lw a0, %lo(var_test_irq+12)(t0)
-; RV32IXQCCMP-SR-NEXT:    sw a0, 16(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-SR-NEXT:    addi a5, t0, %lo(var_test_irq)
 ; RV32IXQCCMP-SR-NEXT:    lw a0, 16(a5)
-; RV32IXQCCMP-SR-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a0, 16(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-SR-NEXT:    lw a0, 20(a5)
-; RV32IXQCCMP-SR-NEXT:    sw a0, 8(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-SR-NEXT:    lw t4, 24(a5)
 ; RV32IXQCCMP-SR-NEXT:    lw t5, 28(a5)
 ; RV32IXQCCMP-SR-NEXT:    lw t6, 32(a5)
@@ -2929,33 +2937,33 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV32IXQCCMP-SR-NEXT:    sw t6, 32(a5)
 ; RV32IXQCCMP-SR-NEXT:    sw t5, 28(a5)
 ; RV32IXQCCMP-SR-NEXT:    sw t4, 24(a5)
-; RV32IXQCCMP-SR-NEXT:    lw a0, 8(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    sw a0, 20(a5)
 ; RV32IXQCCMP-SR-NEXT:    lw a0, 12(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    sw a0, 16(a5)
+; RV32IXQCCMP-SR-NEXT:    sw a0, 20(a5)
 ; RV32IXQCCMP-SR-NEXT:    lw a0, 16(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
+; RV32IXQCCMP-SR-NEXT:    sw a0, 16(a5)
 ; RV32IXQCCMP-SR-NEXT:    lw a0, 20(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
+; RV32IXQCCMP-SR-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
 ; RV32IXQCCMP-SR-NEXT:    lw a0, 24(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
+; RV32IXQCCMP-SR-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
 ; RV32IXQCCMP-SR-NEXT:    lw a0, 28(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
+; RV32IXQCCMP-SR-NEXT:    lw a0, 32(sp) # 4-byte Folded Reload
 ; RV32IXQCCMP-SR-NEXT:    sw a0, %lo(var_test_irq)(t0)
-; RV32IXQCCMP-SR-NEXT:    lw t0, 88(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw t1, 84(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw t2, 80(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw a0, 76(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw a1, 72(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw a2, 68(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw a3, 64(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw a4, 60(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw a5, 56(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw a6, 52(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw a7, 48(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw t3, 44(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw t4, 40(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw t5, 36(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    lw t6, 32(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw t0, 92(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw t1, 88(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw t2, 84(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw a0, 80(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw a1, 76(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw a2, 72(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw a3, 68(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw a4, 64(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw a5, 60(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw a6, 56(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw a7, 52(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw t3, 48(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw t4, 44(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw t5, 40(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    lw t6, 36(sp) # 4-byte Folded Reload
 ; RV32IXQCCMP-SR-NEXT:    .cfi_restore t0
 ; RV32IXQCCMP-SR-NEXT:    .cfi_restore t1
 ; RV32IXQCCMP-SR-NEXT:    .cfi_restore t2
@@ -2971,7 +2979,7 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV32IXQCCMP-SR-NEXT:    .cfi_restore t4
 ; RV32IXQCCMP-SR-NEXT:    .cfi_restore t5
 ; RV32IXQCCMP-SR-NEXT:    .cfi_restore t6
-; RV32IXQCCMP-SR-NEXT:    addi sp, sp, 32
+; RV32IXQCCMP-SR-NEXT:    addi sp, sp, 48
 ; RV32IXQCCMP-SR-NEXT:    .cfi_def_cfa_offset 112
 ; RV32IXQCCMP-SR-NEXT:    qc.cm.pop {ra, s0-s11}, 112
 ; RV32IXQCCMP-SR-NEXT:    .cfi_restore ra
@@ -3007,52 +3015,52 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV64IXQCCMP-SR-NEXT:    .cfi_offset s9, -88
 ; RV64IXQCCMP-SR-NEXT:    .cfi_offset s10, -96
 ; RV64IXQCCMP-SR-NEXT:    .cfi_offset s11, -104
-; RV64IXQCCMP-SR-NEXT:    addi sp, sp, -112
-; RV64IXQCCMP-SR-NEXT:    .cfi_def_cfa_offset 272
-; RV64IXQCCMP-SR-NEXT:    sd t0, 160(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd t1, 152(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd t2, 144(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd a0, 136(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd a1, 128(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd a2, 120(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd a3, 112(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd a4, 104(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd a5, 96(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd a6, 88(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd a7, 80(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd t3, 72(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd t4, 64(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd t5, 56(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    sd t6, 48(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset t0, -112
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset t1, -120
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset t2, -128
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset a0, -136
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset a1, -144
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset a2, -152
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset a3, -160
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset a4, -168
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset a5, -176
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset a6, -184
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset a7, -192
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset t3, -200
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset t4, -208
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset t5, -216
-; RV64IXQCCMP-SR-NEXT:    .cfi_offset t6, -224
+; RV64IXQCCMP-SR-NEXT:    addi sp, sp, -128
+; RV64IXQCCMP-SR-NEXT:    .cfi_def_cfa_offset 288
+; RV64IXQCCMP-SR-NEXT:    sd t0, 168(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd t1, 160(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd t2, 152(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd a0, 144(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd a1, 136(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd a2, 128(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd a3, 120(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd a4, 112(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd a5, 104(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd a6, 96(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd a7, 88(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd t3, 80(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd t4, 72(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd t5, 64(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd t6, 56(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset t0, -120
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset t1, -128
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset t2, -136
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset a0, -144
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset a1, -152
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset a2, -160
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset a3, -168
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset a4, -176
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset a5, -184
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset a6, -192
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset a7, -200
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset t3, -208
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset t4, -216
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset t5, -224
+; RV64IXQCCMP-SR-NEXT:    .cfi_offset t6, -232
 ; RV64IXQCCMP-SR-NEXT:    lui t0, %hi(var_test_irq)
 ; RV64IXQCCMP-SR-NEXT:    lw a0, %lo(var_test_irq)(t0)
-; RV64IXQCCMP-SR-NEXT:    sd a0, 40(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd a0, 48(sp) # 8-byte Folded Spill
 ; RV64IXQCCMP-SR-NEXT:    lw a0, %lo(var_test_irq+4)(t0)
-; RV64IXQCCMP-SR-NEXT:    sd a0, 32(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd a0, 40(sp) # 8-byte Folded Spill
 ; RV64IXQCCMP-SR-NEXT:    lw a0, %lo(var_test_irq+8)(t0)
-; RV64IXQCCMP-SR-NEXT:    sd a0, 24(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd a0, 32(sp) # 8-byte Folded Spill
 ; RV64IXQCCMP-SR-NEXT:    lw a0, %lo(var_test_irq+12)(t0)
-; RV64IXQCCMP-SR-NEXT:    sd a0, 16(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd a0, 24(sp) # 8-byte Folded Spill
 ; RV64IXQCCMP-SR-NEXT:    addi a5, t0, %lo(var_test_irq)
 ; RV64IXQCCMP-SR-NEXT:    lw a0, 16(a5)
-; RV64IXQCCMP-SR-NEXT:    sd a0, 8(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd a0, 16(sp) # 8-byte Folded Spill
 ; RV64IXQCCMP-SR-NEXT:    lw a0, 20(a5)
-; RV64IXQCCMP-SR-NEXT:    sd a0, 0(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    sd a0, 8(sp) # 8-byte Folded Spill
 ; RV64IXQCCMP-SR-NEXT:    lw t4, 24(a5)
 ; RV64IXQCCMP-SR-NEXT:    lw t5, 28(a5)
 ; RV64IXQCCMP-SR-NEXT:    lw t6, 32(a5)
@@ -3105,33 +3113,33 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV64IXQCCMP-SR-NEXT:    sw t6, 32(a5)
 ; RV64IXQCCMP-SR-NEXT:    sw t5, 28(a5)
 ; RV64IXQCCMP-SR-NEXT:    sw t4, 24(a5)
-; RV64IXQCCMP-SR-NEXT:    ld a0, 0(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    sw a0, 20(a5)
 ; RV64IXQCCMP-SR-NEXT:    ld a0, 8(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    sw a0, 16(a5)
+; RV64IXQCCMP-SR-NEXT:    sw a0, 20(a5)
 ; RV64IXQCCMP-SR-NEXT:    ld a0, 16(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
+; RV64IXQCCMP-SR-NEXT:    sw a0, 16(a5)
 ; RV64IXQCCMP-SR-NEXT:    ld a0, 24(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
+; RV64IXQCCMP-SR-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
 ; RV64IXQCCMP-SR-NEXT:    ld a0, 32(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
+; RV64IXQCCMP-SR-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
 ; RV64IXQCCMP-SR-NEXT:    ld a0, 40(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
+; RV64IXQCCMP-SR-NEXT:    ld a0, 48(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-SR-NEXT:    sw a0, %lo(var_test_irq)(t0)
-; RV64IXQCCMP-SR-NEXT:    ld t0, 160(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld t1, 152(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld t2, 144(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld a0, 136(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld a1, 128(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld a2, 120(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld a3, 112(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld a4, 104(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld a5, 96(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld a6, 88(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld a7, 80(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld t3, 72(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld t4, 64(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld t5, 56(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT:    ld t6, 48(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld t0, 168(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld t1, 160(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld t2, 152(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld a0, 144(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld a1, 136(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld a2, 128(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld a3, 120(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld a4, 112(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld a5, 104(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld a6, 96(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld a7, 88(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld t3, 80(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld t4, 72(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld t5, 64(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld t6, 56(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-SR-NEXT:    .cfi_restore t0
 ; RV64IXQCCMP-SR-NEXT:    .cfi_restore t1
 ; RV64IXQCCMP-SR-NEXT:    .cfi_restore t2
@@ -3147,7 +3155,7 @@ define void @callee_with_irq() "interrupt"="machine" {
 ; RV64IXQCCMP-SR-NEXT:    .cfi_restore t4
 ; RV64IXQCCMP-SR-NEXT:    .cfi_restore t5
 ; RV64IXQCCMP-SR-NEXT:    .cfi_restore t6
-; RV64IXQCCMP-SR-NEXT:    addi sp, sp, 112
+; RV64IXQCCMP-SR-NEXT:    addi sp, sp, 128
 ; RV64IXQCCMP-SR-NEXT:    .cfi_def_cfa_offset 160
 ; RV64IXQCCMP-SR-NEXT:    qc.cm.pop {ra, s0-s11}, 160
 ; RV64IXQCCMP-SR-NEXT:    .cfi_restore ra
@@ -3173,8 +3181,8 @@ define void @callee_with_irq() "interrupt"="machine" {
 define void @callee_no_irq() {
 ; RV32IXQCCMP-LABEL: callee_no_irq:
 ; RV32IXQCCMP:       # %bb.0:
-; RV32IXQCCMP-NEXT:    qc.cm.push {ra, s0-s11}, -80
-; RV32IXQCCMP-NEXT:    .cfi_def_cfa_offset 80
+; RV32IXQCCMP-NEXT:    qc.cm.push {ra, s0-s11}, -96
+; RV32IXQCCMP-NEXT:    .cfi_def_cfa_offset 96
 ; RV32IXQCCMP-NEXT:    .cfi_offset ra, -4
 ; RV32IXQCCMP-NEXT:    .cfi_offset s0, -8
 ; RV32IXQCCMP-NEXT:    .cfi_offset s1, -12
@@ -3190,18 +3198,18 @@ define void @callee_no_irq() {
 ; RV32IXQCCMP-NEXT:    .cfi_offset s11, -52
 ; RV32IXQCCMP-NEXT:    lui t0, %hi(var_test_irq)
 ; RV32IXQCCMP-NEXT:    lw a0, %lo(var_test_irq)(t0)
-; RV32IXQCCMP-NEXT:    sw a0, 24(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 28(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, %lo(var_test_irq+4)(t0)
-; RV32IXQCCMP-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 24(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, %lo(var_test_irq+8)(t0)
-; RV32IXQCCMP-NEXT:    sw a0, 16(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, %lo(var_test_irq+12)(t0)
-; RV32IXQCCMP-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 16(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    addi a5, t0, %lo(var_test_irq)
 ; RV32IXQCCMP-NEXT:    lw a0, 16(a5)
-; RV32IXQCCMP-NEXT:    sw a0, 8(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw a0, 20(a5)
-; RV32IXQCCMP-NEXT:    sw a0, 4(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT:    sw a0, 8(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-NEXT:    lw t4, 24(a5)
 ; RV32IXQCCMP-NEXT:    lw t5, 28(a5)
 ; RV32IXQCCMP-NEXT:    lw t6, 32(a5)
@@ -3254,19 +3262,19 @@ define void @callee_no_irq() {
 ; RV32IXQCCMP-NEXT:    sw t6, 32(a5)
 ; RV32IXQCCMP-NEXT:    sw t5, 28(a5)
 ; RV32IXQCCMP-NEXT:    sw t4, 24(a5)
-; RV32IXQCCMP-NEXT:    lw a0, 4(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, 20(a5)
 ; RV32IXQCCMP-NEXT:    lw a0, 8(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, 16(a5)
+; RV32IXQCCMP-NEXT:    sw a0, 20(a5)
 ; RV32IXQCCMP-NEXT:    lw a0, 12(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
+; RV32IXQCCMP-NEXT:    sw a0, 16(a5)
 ; RV32IXQCCMP-NEXT:    lw a0, 16(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
+; RV32IXQCCMP-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
 ; RV32IXQCCMP-NEXT:    lw a0, 20(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
+; RV32IXQCCMP-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
 ; RV32IXQCCMP-NEXT:    lw a0, 24(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
+; RV32IXQCCMP-NEXT:    lw a0, 28(sp) # 4-byte Folded Reload
 ; RV32IXQCCMP-NEXT:    sw a0, %lo(var_test_irq)(t0)
-; RV32IXQCCMP-NEXT:    qc.cm.popret {ra, s0-s11}, 80
+; RV32IXQCCMP-NEXT:    qc.cm.popret {ra, s0-s11}, 96
 ;
 ; RV64IXQCCMP-LABEL: callee_no_irq:
 ; RV64IXQCCMP:       # %bb.0:
@@ -3287,18 +3295,18 @@ define void @callee_no_irq() {
 ; RV64IXQCCMP-NEXT:    .cfi_offset s11, -104
 ; RV64IXQCCMP-NEXT:    lui t0, %hi(var_test_irq)
 ; RV64IXQCCMP-NEXT:    lw a0, %lo(var_test_irq)(t0)
-; RV64IXQCCMP-NEXT:    sd a0, 48(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, %lo(var_test_irq+4)(t0)
 ; RV64IXQCCMP-NEXT:    sd a0, 40(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, %lo(var_test_irq+8)(t0)
+; RV64IXQCCMP-NEXT:    lw a0, %lo(var_test_irq+4)(t0)
 ; RV64IXQCCMP-NEXT:    sd a0, 32(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, %lo(var_test_irq+12)(t0)
+; RV64IXQCCMP-NEXT:    lw a0, %lo(var_test_irq+8)(t0)
 ; RV64IXQCCMP-NEXT:    sd a0, 24(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    lw a0, %lo(var_test_irq+12)(t0)
+; RV64IXQCCMP-NEXT:    sd a0, 16(sp) # 8-byte Folded Spill
 ; RV64IXQCCMP-NEXT:    addi a5, t0, %lo(var_test_irq)
 ; RV64IXQCCMP-NEXT:    lw a0, 16(a5)
-; RV64IXQCCMP-NEXT:    sd a0, 16(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT:    lw a0, 20(a5)
 ; RV64IXQCCMP-NEXT:    sd a0, 8(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT:    lw a0, 20(a5)
+; RV64IXQCCMP-NEXT:    sd a0, 0(sp) # 8-byte Folded Spill
 ; RV64IXQCCMP-NEXT:    lw t4, 24(a5)
 ; RV64IXQCCMP-NEXT:    lw t5, 28(a5)
 ; RV64IXQCCMP-NEXT:    lw t6, 32(a5)
@@ -3351,24 +3359,24 @@ define void @callee_no_irq() {
 ; RV64IXQCCMP-NEXT:    sw t6, 32(a5)
 ; RV64IXQCCMP-NEXT:    sw t5, 28(a5)
 ; RV64IXQCCMP-NEXT:    sw t4, 24(a5)
-; RV64IXQCCMP-NEXT:    ld a0, 8(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 0(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, 20(a5)
-; RV64IXQCCMP-NEXT:    ld a0, 16(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 8(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, 16(a5)
-; RV64IXQCCMP-NEXT:    ld a0, 24(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 16(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
-; RV64IXQCCMP-NEXT:    ld a0, 32(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 24(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
-; RV64IXQCCMP-NEXT:    ld a0, 40(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 32(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
-; RV64IXQCCMP-NEXT:    ld a0, 48(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT:    ld a0, 40(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-NEXT:    sw a0, %lo(var_test_irq)(t0)
 ; RV64IXQCCMP-NEXT:    qc.cm.popret {ra, s0-s11}, 160
 ;
 ; RV32IXQCCMP-FP-LABEL: callee_no_irq:
 ; RV32IXQCCMP-FP:       # %bb.0:
-; RV32IXQCCMP-FP-NEXT:    qc.cm.pushfp {ra, s0-s11}, -80
-; RV32IXQCCMP-FP-NEXT:    .cfi_def_cfa_offset 80
+; RV32IXQCCMP-FP-NEXT:    qc.cm.pushfp {ra, s0-s11}, -96
+; RV32IXQCCMP-FP-NEXT:    .cfi_def_cfa_offset 96
 ; RV32IXQCCMP-FP-NEXT:    .cfi_offset ra, -4
 ; RV32IXQCCMP-FP-NEXT:    .cfi_offset s0, -8
 ; RV32IXQCCMP-FP-NEXT:    .cfi_offset s1, -12
@@ -3385,20 +3393,20 @@ define void @callee_no_irq() {
 ; RV32IXQCCMP-FP-NEXT:    .cfi_def_cfa s0, 0
 ; RV32IXQCCMP-FP-NEXT:    lui t1, %hi(var_test_irq)
 ; RV32IXQCCMP-FP-NEXT:    lw a0, %lo(var_test_irq)(t1)
-; RV32IXQCCMP-FP-NEXT:    sw a0, -56(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a0, -68(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-FP-NEXT:    lw a0, %lo(var_test_irq+4)(t1)
-; RV32IXQCCMP-FP-NEXT:    sw a0, -60(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a0, -72(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-FP-NEXT:    lw a0, %lo(var_test_irq+8)(t1)
-; RV32IXQCCMP-FP-NEXT:    sw a0, -64(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a0, -76(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-FP-NEXT:    lw a0, %lo(var_test_irq+12)(t1)
-; RV32IXQCCMP-FP-NEXT:    sw a0, -68(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a0, -80(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-FP-NEXT:    addi a5, t1, %lo(var_test_irq)
 ; RV32IXQCCMP-FP-NEXT:    lw a0, 16(a5)
-; RV32IXQCCMP-FP-NEXT:    sw a0, -72(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a0, -84(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-FP-NEXT:    lw a0, 20(a5)
-; RV32IXQCCMP-FP-NEXT:    sw a0, -76(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a0, -88(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-FP-NEXT:    lw a0, 24(a5)
-; RV32IXQCCMP-FP-NEXT:    sw a0, -80(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT:    sw a0, -92(s0) # 4-byte Folded Spill
 ; RV32IXQCCMP-FP-NEXT:    lw t5, 28(a5)
 ; RV32IXQCCMP-FP-NEXT:    lw t6, 32(a5)
 ; RV32IXQCCMP-FP-NEXT:    lw s2, 36(a5)
@@ -3449,22 +3457,22 @@ define void @callee_no_irq() {
 ; RV32IXQCCMP-FP-NEXT:    sw s2, 36(a5)
 ; RV32IXQCCMP-FP-NEXT:    sw t6, 32(a5)
 ; RV32IXQCCMP-FP-NEXT:    sw t5, 28(a5)
-; RV32IXQCCMP-FP-NEXT:    lw a0, -80(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a0, -92(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-FP-NEXT:    sw a0, 24(a5)
-; RV32IXQCCMP-FP-NEXT:    lw a0, -76(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a0, -88(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-FP-NEXT:    sw a0, 20(a5)
-; RV32IXQCCMP-FP-NEXT:    lw a0, -72(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a0, -84(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-FP-NEXT:    sw a0, 16(a5)
-; RV32IXQCCMP-FP-NEXT:    lw a0, -68(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a0, -80(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-FP-NEXT:    sw a0, %lo(var_test_irq+12)(t1)
-; RV32IXQCCMP-FP-NEXT:    lw a0, -64(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a0, -76(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-FP-NEXT:    sw a0, %lo(var_test_irq+8)(t1)
-; RV32IXQCCMP-FP-NEXT:    lw a0, -60(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a0, -72(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-FP-NEXT:    sw a0, %lo(var_test_irq+4)(t1)
-; RV32IXQCCMP-FP-NEXT:    lw a0, -56(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT:    lw a0, -68(s0) # 4-byte Folded Reload
 ; RV32IXQCCMP-FP-NEXT:    sw a0, %lo(var_test_irq)(t1)
-; RV32IXQCCMP-FP-NEXT:    .cfi_def_cfa sp, 80
-; RV32IXQCCMP-FP-NEXT:    qc.cm.popret {ra, s0-s11}, 80
+; RV32IXQCCMP-FP-NEXT:    .cfi_def_cfa sp, 96
+; RV32IXQCCMP-FP-NEXT:    qc.cm.popret {ra, s0-s11}, 96
 ;
 ; RV64IXQCCMP-FP-LABEL: callee_no_irq:
 ; RV64IXQCCMP-FP:       # %bb.0:
@@ -3483,23 +3491,25 @@ define void @callee_no_irq() {
 ; RV64IXQCCMP-FP-NEXT:    .cfi_offset s9, -88
 ; RV64IXQCCMP-FP-NEXT:    .cfi_offset s10, -96
 ; RV64IXQCCMP-FP-NEXT:    .cfi_offset s11, -104
+; RV64IXQCCMP-FP-NEXT:    addi sp, sp, -16
+; RV64IXQCCMP-FP-NEXT:    .cfi_def_cfa_offset 176
 ; RV64IXQCCMP-FP-NEXT:    .cfi_def_cfa s0, 0
 ; RV64IXQCCMP-FP-NEXT:    lui t1, %hi(var_test_irq)
 ; RV64IXQCCMP-FP-NEXT:    lw a0, %lo(var_test_irq)(t1)
-; RV64IXQCCMP-FP-NEXT:    sd a0, -112(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT:    lw a0, %lo(var_test_irq+4)(t1)
 ; RV64IXQCCMP-FP-NEXT:    sd a0, -120(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT:    lw a0, %lo(var_test_irq+8)(t1)
+; RV64IXQCCMP-FP-NEXT:    lw a0, %lo(var_test_irq+4)(t1)
 ; RV64IXQCCMP-FP-NEXT:    sd a0, -128(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT:    lw a0, %lo(var_test_irq+12)(t1)
+; RV64IXQCCMP-FP-NEXT:    lw a0, %lo(var_test_irq+8)(t1)
 ; RV64IXQCCMP-FP-NEXT:    sd a0, -136(s0) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT:    lw a0, %lo(var_test_irq+12)(t1)
+; RV64IXQCCMP-FP-NEXT:    sd a0, -144(s0) # 8-byte Folded Spill
 ; RV64IXQCCMP-FP-NEXT:    addi a5, t1, %lo(var_test_irq)
 ; RV64IXQCCMP-FP-NEXT:    lw a0, 16(a5)
-; RV64IXQCCMP-FP-NEXT:    sd a0, -144(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT:    lw a0, 20(a5)
 ; RV64IXQCCMP-FP-NEXT:    sd a0, -152(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT:    lw a0, 24(a5)
+; RV64IXQCCMP-FP-NEXT:    lw a0, 20(a5)
 ; RV64IXQCCMP-FP-NEXT:    sd a0, -160(s0) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT:    lw a0, 24(a5)
+; RV64IXQCCMP-FP-NEXT:    sd a0, -168(s0) # 8-byte Folded Spill
 ; RV64IXQCCMP-FP-NEXT:    lw t5, 28(a5)
 ; RV64IXQCCMP-FP-NEXT:    lw t6, 32(a5)
 ; RV64IXQCCMP-FP-NEXT:    lw s2, 36(a5)
@@ -3550,27 +3560,29 @@ define void @callee_no_irq() {
 ; RV64IXQCCMP-FP-NEXT:    sw s2, 36(a5)
 ; RV64IXQCCMP-FP-NEXT:    sw t6, 32(a5)
 ; RV64IXQCCMP-FP-NEXT:    sw t5, 28(a5)
-; RV64IXQCCMP-FP-NEXT:    ld a0, -160(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld a0, -168(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-FP-NEXT:    sw a0, 24(a5)
-; RV64IXQCCMP-FP-NEXT:    ld a0, -152(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld a0, -160(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-FP-NEXT:    sw a0, 20(a5)
-; RV64IXQCCMP-FP-NEXT:    ld a0, -144(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld a0, -152(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-FP-NEXT:    sw a0, 16(a5)
-; RV64IXQCCMP-FP-NEXT:    ld a0, -136(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld a0, -144(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-FP-NEXT:    sw a0, %lo(var_test_irq+12)(t1)
-; RV64IXQCCMP-FP-NEXT:    ld a0, -128(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld a0, -136(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-FP-NEXT:    sw a0, %lo(var_test_irq+8)(t1)
-; RV64IXQCCMP-FP-NEXT:    ld a0, -120(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld a0, -128(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-FP-NEXT:    sw a0, %lo(var_test_irq+4)(t1)
-; RV64IXQCCMP-FP-NEXT:    ld a0, -112(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT:    ld a0, -120(s0) # 8-byte Folded Reload
 ; RV64IXQCCMP-FP-NEXT:    sw a0, %lo(var_test_irq)(t1)
-; RV64IXQCCMP-FP-NEXT:    .cfi_def_cfa sp, 160
+; RV64IXQCCMP-FP-NEXT:    .cfi_def_cfa sp, 176
+; RV64IXQCCMP-FP-NEXT:    addi sp, sp, 16
+; RV64IXQCCMP-FP-NEXT:    .cfi_def_cfa_offset 160
 ; RV64IXQCCMP-FP-NEXT:    qc.cm.popret {ra, s0-s11}, 160
 ;
 ; RV32IXQCCMP-SR-LABEL: callee_no_irq:
 ; RV32IXQCCMP-SR:       # %bb.0:
-; RV32IXQCCMP-SR-NEXT:    qc.cm.push {ra, s0-s11}, -80
-; RV32IXQCCMP-SR-NEXT:    .cfi_def_cfa_offset 80
+; RV32IXQCCMP-SR-NEXT:    qc.cm.push {ra, s0-s11}, -96
+; RV32IXQCCMP-SR-NEXT:    .cfi_def_cfa_offset 96
 ; RV32IXQCCMP-SR-NEXT:    .cfi_offset ra, -4
 ; RV32IXQCCMP-SR-NEXT:    .cfi_offset s0, -8
 ; RV32IXQCCMP-SR-NEXT:    .cfi_offset s1, -12
@@ -3586,18 +3598,18 @@ define void @callee_no_irq() {
 ; RV32IXQCCMP-SR-NEXT:    .cfi_offset s11, -52
 ; RV32IXQCCMP-SR-NEXT:    lui t0, %hi(var_test_irq)
 ; RV32IXQCCMP-SR-NEXT:    lw a0, %lo(var_test_irq)(t0)
-; RV32IXQCCMP-SR-NEXT:    sw a0, 24(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a0, 28(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-SR-NEXT:    lw a0, %lo(var_test_irq+4)(t0)
-; RV32IXQCCMP-SR-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a0, 24(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-SR-NEXT:    lw a0, %lo(var_test_irq+8)(t0)
-; RV32IXQCCMP-SR-NEXT:    sw a0, 16(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a0, 20(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-SR-NEXT:    lw a0, %lo(var_test_irq+12)(t0)
-; RV32IXQCCMP-SR-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a0, 16(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-SR-NEXT:    addi a5, t0, %lo(var_test_irq)
 ; RV32IXQCCMP-SR-NEXT:    lw a0, 16(a5)
-; RV32IXQCCMP-SR-NEXT:    sw a0, 8(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-SR-NEXT:    lw a0, 20(a5)
-; RV32IXQCCMP-SR-NEXT:    sw a0, 4(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT:    sw a0, 8(sp) # 4-byte Folded Spill
 ; RV32IXQCCMP-SR-NEXT:    lw t4, 24(a5)
 ; RV32IXQCCMP-SR-NEXT:    lw t5, 28(a5)
 ; RV32IXQCCMP-SR-NEXT:    lw t6, 32(a5)
@@ -3650,19 +3662,19 @@ define void @callee_no_irq() {
 ; RV32IXQCCMP-SR-NEXT:    sw t6, 32(a5)
 ; RV32IXQCCMP-SR-NEXT:    sw t5, 28(a5)
 ; RV32IXQCCMP-SR-NEXT:    sw t4, 24(a5)
-; RV32IXQCCMP-SR-NEXT:    lw a0, 4(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    sw a0, 20(a5)
 ; RV32IXQCCMP-SR-NEXT:    lw a0, 8(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    sw a0, 16(a5)
+; RV32IXQCCMP-SR-NEXT:    sw a0, 20(a5)
 ; RV32IXQCCMP-SR-NEXT:    lw a0, 12(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
+; RV32IXQCCMP-SR-NEXT:    sw a0, 16(a5)
 ; RV32IXQCCMP-SR-NEXT:    lw a0, 16(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
+; RV32IXQCCMP-SR-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
 ; RV32IXQCCMP-SR-NEXT:    lw a0, 20(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
+; RV32IXQCCMP-SR-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
 ; RV32IXQCCMP-SR-NEXT:    lw a0, 24(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
+; RV32IXQCCMP-SR-NEXT:    lw a0, 28(sp) # 4-byte Folded Reload
 ; RV32IXQCCMP-SR-NEXT:    sw a0, %lo(var_test_irq)(t0)
-; RV32IXQCCMP-SR-NEXT:    qc.cm.popret {ra, s0-s11}, 80
+; RV32IXQCCMP-SR-NEXT:    qc.cm.popret {ra, s0-s11}, 96
 ;
 ; RV64IXQCCMP-SR-LABEL: callee_no_irq:
 ; RV64IXQCCMP-SR:       # %bb.0:
@@ -3683,18 +3695,18 @@ define void @callee_no_irq() {
 ; RV64IXQCCMP-SR-NEXT:    .cfi_offset s11, -104
 ; RV64IXQCCMP-SR-NEXT:    lui t0, %hi(var_test_irq)
 ; RV64IXQCCMP-SR-NEXT:    lw a0, %lo(var_test_irq)(t0)
-; RV64IXQCCMP-SR-NEXT:    sd a0, 48(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    lw a0, %lo(var_test_irq+4)(t0)
 ; RV64IXQCCMP-SR-NEXT:    sd a0, 40(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    lw a0, %lo(var_test_irq+8)(t0)
+; RV64IXQCCMP-SR-NEXT:    lw a0, %lo(var_test_irq+4)(t0)
 ; RV64IXQCCMP-SR-NEXT:    sd a0, 32(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    lw a0, %lo(var_test_irq+12)(t0)
+; RV64IXQCCMP-SR-NEXT:    lw a0, %lo(var_test_irq+8)(t0)
 ; RV64IXQCCMP-SR-NEXT:    sd a0, 24(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    lw a0, %lo(var_test_irq+12)(t0)
+; RV64IXQCCMP-SR-NEXT:    sd a0, 16(sp) # 8-byte Folded Spill
 ; RV64IXQCCMP-SR-NEXT:    addi a5, t0, %lo(var_test_irq)
 ; RV64IXQCCMP-SR-NEXT:    lw a0, 16(a5)
-; RV64IXQCCMP-SR-NEXT:    sd a0, 16(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT:    lw a0, 20(a5)
 ; RV64IXQCCMP-SR-NEXT:    sd a0, 8(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT:    lw a0, 20(a5)
+; RV64IXQCCMP-SR-NEXT:    sd a0, 0(sp) # 8-byte Folded Spill
 ; RV64IXQCCMP-SR-NEXT:    lw t4, 24(a5)
 ; RV64IXQCCMP-SR-NEXT:    lw t5, 28(a5)
 ; RV64IXQCCMP-SR-NEXT:    lw t6, 32(a5)
@@ -3747,17 +3759,17 @@ define void @callee_no_irq() {
 ; RV64IXQCCMP-SR-NEXT:    sw t6, 32(a5)
 ; RV64IXQCCMP-SR-NEXT:    sw t5, 28(a5)
 ; RV64IXQCCMP-SR-NEXT:    sw t4, 24(a5)
-; RV64IXQCCMP-SR-NEXT:    ld a0, 8(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld a0, 0(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-SR-NEXT:    sw a0, 20(a5)
-; RV64IXQCCMP-SR-NEXT:    ld a0, 16(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld a0, 8(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-SR-NEXT:    sw a0, 16(a5)
-; RV64IXQCCMP-SR-NEXT:    ld a0, 24(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld a0, 16(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-SR-NEXT:    sw a0, %lo(var_test_irq+12)(t0)
-; RV64IXQCCMP-SR-NEXT:    ld a0, 32(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld a0, 24(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-SR-NEXT:    sw a0, %lo(var_test_irq+8)(t0)
-; RV64IXQCCMP-SR-NEXT:    ld a0, 40(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld a0, 32(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-SR-NEXT:    sw a0, %lo(var_test_irq+4)(t0)
-; RV64IXQCCMP-SR-NEXT:    ld a0, 48(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT:    ld a0, 40(sp) # 8-byte Folded Reload
 ; RV64IXQCCMP-SR-NEXT:    sw a0, %lo(var_test_irq)(t0)
 ; RV64IXQCCMP-SR-NEXT:    qc.cm.popret {ra, s0-s11}, 160
   %val = load [32 x i32], ptr @var_test_irq
@@ -3771,99 +3783,99 @@ declare ptr @llvm.frameaddress.p0(i32 immarg)
 define i32 @use_fp(i32 %x) {
 ; RV32IXQCCMP-LABEL: use_fp:
 ; RV32IXQCCMP:       # %bb.0: # %entry
-; RV32IXQCCMP-NEXT:    qc.cm.pushfp {ra, s0-s1}, -16
-; RV32IXQCCMP-NEXT:    .cfi_def_cfa_offset 16
+; RV32IXQCCMP-NEXT:    qc.cm.pushfp {ra, s0-s1}, -32
+; RV32IXQCCMP-NEXT:    .cfi_def_cfa_offset 32
 ; RV32IXQCCMP-NEXT:    .cfi_offset ra, -4
 ; RV32IXQCCMP-NEXT:    .cfi_offset s0, -8
 ; RV32IXQCCMP-NEXT:    .cfi_offset s1, -12
 ; RV32IXQCCMP-NEXT:    .cfi_def_cfa s0, 0
 ; RV32IXQCCMP-NEXT:    mv s1, a0
-; RV32IXQCCMP-NEXT:    addi a1, s0, -16
+; RV32IXQCCMP-NEXT:    addi a1, s0, -20
 ; RV32IXQCCMP-NEXT:    mv a0, s0
 ; RV32IXQCCMP-NEXT:    call bar
 ; RV32IXQCCMP-NEXT:    mv a0, s1
-; RV32IXQCCMP-NEXT:    .cfi_def_cfa sp, 16
-; RV32IXQCCMP-NEXT:    qc.cm.popret {ra, s0-s1}, 16
+; RV32IXQCCMP-NEXT:    .cfi_def_cfa sp, 32
+; RV32IXQCCMP-NEXT:    qc.cm.popret {ra, s0-s1}, 32
 ;
 ; RV64IXQCCMP-LABEL: use_fp:
 ; RV64IXQCCMP:       # %bb.0: # %entry
-; RV64IXQCCMP-NEXT:    qc.cm.pushfp {ra, s0-s1}, -32
-; RV64IXQCCMP-NEXT:    .cfi_def_cfa_offset 32
+; RV64IXQCCMP-NEXT:    qc.cm.pushfp {ra, s0-s1}, -48
+; RV64IXQCCMP-NEXT:    .cfi_def_cfa_offset 48
 ; RV64IXQCCMP-NEXT:    .cfi_offset ra, -8
 ; RV64IXQCCMP-NEXT:    .cfi_offset s0, -16
 ; RV64IXQCCMP-NEXT:    .cfi_offset s1, -24
 ; RV64IXQCCMP-NEXT:    .cfi_def_cfa s0, 0
 ; RV64IXQCCMP-NEXT:    mv s1, a0
-; RV64IXQCCMP-NEXT:    addi a1, s0, -28
+; RV64IXQCCMP-NEXT:    addi a1, s0, -36
 ; RV64IXQCCMP-NEXT:    mv a0, s0
 ; RV64IXQCCMP-NEXT:    call bar
 ; RV64IXQCCMP-NEXT:    mv a0, s1
-; RV64IXQCCMP-NEXT:    .cfi_def_cfa sp, 32
-; RV64IXQCCMP-NEXT:    qc.cm.popret {ra, s0-s1}, 32
+; RV64IXQCCMP-NEXT:    .cfi_def_cfa sp, 48
+; RV64IXQCCMP-NEXT:    qc.cm.popret {ra, s0-s1}, 48
 ;
 ; RV32IXQCCMP-FP-LABEL: use_fp:
 ; RV32IXQCCMP-FP:       # %bb.0: # %entry
-; RV32IXQCCMP-FP-NEXT:    qc.cm.pushfp {ra, s0-s1}, -16
-; RV32IXQCCMP-FP-NEXT:    .cfi_def_cfa_offset 16
+; RV32IXQCCMP-FP-NEXT:    qc.cm.pushfp {ra, s0-s1}, -32
+; RV32IXQCCMP-FP-NEXT:    .cfi_def_cfa_offset 32
 ; RV32IXQCCMP-FP-NEXT:    .cfi_offset ra, -4
 ; RV32IXQCCMP-FP-NEXT:    .cfi_offset s0, -8
 ; RV32IXQCCMP-FP-NEXT:    .cfi_offset s1, -12
 ; RV32IXQCCMP-FP-NEXT:    .cfi_def_cfa s0, 0
 ; RV32IXQCCMP-FP-NEXT:    mv s1, a0
-; RV32IXQCCMP-FP-NEXT:    addi a1, s0, -16
+; RV32IXQCCMP-FP-NEXT:    addi a1, s0, -20
 ; RV32IXQCCMP-FP-NEXT:    mv a0, s0
 ; RV32IXQCCMP-FP-NEXT:    call bar
 ; RV32IXQCCMP-FP-NEXT:    mv a0, s1
-; RV32IXQCCMP-FP-NEXT:    .cfi_def_cfa sp, 16
-; RV32IXQCCMP-FP-NEXT:    qc.cm.popret {ra, s0-s1}, 16
+; RV32IXQCCMP-FP-NEXT:    .cfi_def_cfa sp, 32
+; RV32IXQCCMP-FP-NEXT:    qc.cm.popret {ra, s0-s1}, 32
 ;
 ; RV64IXQCCMP-FP-LABEL: use_fp:
 ; RV64IXQCCMP-FP:       # %bb.0: # %entry
-; RV64IXQCCMP-FP-NEXT:    qc.cm.pushfp {ra, s0-s1}, -32
-; RV64IXQCCMP-FP-NEXT:    .cfi_def_cfa_offset 32
+; RV64IXQCCMP-FP-NEXT:    qc.cm.pushfp {ra, s0-s1}, -48
+; RV64IXQCCMP-FP-NEXT:    .cfi_def_cfa_offset 48
 ; RV64IXQCCMP-FP-NEXT:    .cfi_offset ra, -8
 ; RV64IXQCCMP-FP-NEXT:    .cfi_offset s0, -16
 ; RV64IXQCCMP-FP-NEXT:    .cfi_offset s1, -24
 ; RV64IXQCCMP-FP-NEXT:    .cfi_def_cfa s0, 0
 ; RV64IXQCCMP-FP-NEXT:    mv s1, a0
-; RV64IXQCCMP-FP-NEXT:    addi a1, s0, -28
+; RV64IXQCCMP-FP-NEXT:    addi a1, s0, -36
 ; RV64IXQCCMP-FP-NEXT:    mv a0, s0
 ; RV64IXQCCMP-FP-NEXT:    call bar
 ; RV64IXQCCMP-FP-NEXT:    mv a0, s1
-; RV64IXQCCMP-FP-NEXT:    .cfi_def_cfa sp, 32
-; RV64IXQCCMP-FP-NEXT:    qc.cm.popret {ra, s0-s1}, 32
+; RV64IXQCCMP-FP-NEXT:    .cfi_def_cfa sp, 48
+; RV64IXQCCMP-FP-NEXT:    qc.cm.popret {ra, s0-s1}, 48
 ;
 ; RV32IXQCCMP-SR-LABEL: use_fp:
 ; RV32IXQCCMP-SR:       # %bb.0: # %entry
-; RV32IXQCCMP-SR-NEXT:    qc.cm.pushfp {ra, s0-s1}, -16
-; RV32IXQCCMP-SR-NEXT:    .cfi_def_cfa_offset 16
+; RV32IXQCCMP-SR-NEXT:    qc.cm.pushfp {ra, s0-s1}, -32
+; RV32IXQCCMP-SR-NEXT:    .cfi_def_cfa_offset 32
 ; RV32IXQCCMP-SR-NEXT:    .cfi_offset ra, -4
 ; RV32IXQCCMP-SR-NEXT:    .cfi_offset s0, -8
 ; RV32IXQCCMP-SR-NEXT:    .cfi_offset s1, -12
 ; RV32IXQCCMP-SR-NEXT:    .cfi_def_cfa s0, 0
 ; RV32IXQCCMP-SR-NEXT:    mv s1, a0
-; RV32IXQCCMP-SR-NEXT:    addi a1, s0, -16
+; RV32IXQCCMP-SR-NEXT:    addi a1, s0, -20
 ; RV32IXQCCMP-SR-NEXT:    mv a0, s0
 ; RV32IXQCCMP-SR-NEXT:    call bar
 ; RV32IXQCCMP-SR-NEXT:    mv a0, s1
-; RV32IXQCCMP-SR-NEXT:    .cfi_def_cfa sp, 16
-; RV32IXQCCMP-SR-NEXT:    qc.cm.popret {ra, s0-s1}, 16
+; RV32IXQCCMP-SR-NEXT:    .cfi_def_cfa sp, 32
+; RV32IXQCCMP-SR-NEXT:    qc.cm.popret {ra, s0-s1}, 32
 ;
 ; RV64IXQCCMP-SR-LABEL: use_fp:
 ; RV64IXQCCMP-SR:       # %bb.0: # %entry
-; RV64IXQCCMP-SR-NEXT:    qc.cm.pushfp {ra, s0-s1}, -32
-; RV64IXQCCMP-SR-NEXT:    .cfi_def_cfa_offset 32
+; RV64IXQCCMP-SR-NEXT:    qc.cm.pushfp {ra, s0-s1}, -48
+; RV64IXQCCMP-SR-NEXT:    .cfi_def_cfa_offset 48
 ; RV64IXQCCMP-SR-NEXT:    .cfi_offset ra, -8
 ; RV64IXQCCMP-SR-NEXT:    .cfi_offset s0, -16
 ; RV64IXQCCMP-SR-NEXT:    .cfi_offset s1, -24
 ; RV64IXQCCMP-SR-NEXT:    .cfi_def_cfa s0, 0
 ; RV64IXQCCMP-SR-NEXT:    mv s1, a0
-; RV64IXQCCMP-SR-NEXT:    addi a1, s0, -28
+; RV64IXQCCMP-SR-NEXT:    addi a1, s0, -36
 ; RV64IXQCCMP-SR-NEXT:    mv a0, s0
 ; RV64IXQCCMP-SR-NEXT:    call bar
 ; RV64IXQCCMP-SR-NEXT:    mv a0, s1
-; RV64IXQCCMP-SR-NEXT:    .cfi_def_cfa sp, 32
-; RV64IXQCCMP-SR-NEXT:    qc.cm.popret {ra, s0-s1}, 32
+; RV64IXQCCMP-SR-NEXT:    .cfi_def_cfa sp, 48
+; RV64IXQCCMP-SR-NEXT:    qc.cm.popret {ra, s0-s1}, 48
 entry:
   %var = alloca i32, align 4
   %0 = tail call ptr @llvm.frameaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/RISCV/xqccmp-with-float.ll b/llvm/test/CodeGen/RISCV/xqccmp-with-float.ll
index f4f3c31f9fb3a..12d30cbd7a289 100644
--- a/llvm/test/CodeGen/RISCV/xqccmp-with-float.ll
+++ b/llvm/test/CodeGen/RISCV/xqccmp-with-float.ll
@@ -8,31 +8,31 @@ declare void @callee()
 define float @foo(float %arg) {
 ; XQCCMP32-LABEL: foo:
 ; XQCCMP32:       # %bb.0: # %entry
-; XQCCMP32-NEXT:    qc.cm.push {ra}, -16
-; XQCCMP32-NEXT:    .cfi_def_cfa_offset 16
+; XQCCMP32-NEXT:    qc.cm.push {ra}, -32
+; XQCCMP32-NEXT:    .cfi_def_cfa_offset 32
 ; XQCCMP32-NEXT:    .cfi_offset ra, -4
-; XQCCMP32-NEXT:    fsw fs0, 8(sp) # 4-byte Folded Spill
-; XQCCMP32-NEXT:    .cfi_offset fs0, -8
+; XQCCMP32-NEXT:    fsw fs0, 12(sp) # 4-byte Folded Spill
+; XQCCMP32-NEXT:    .cfi_offset fs0, -20
 ; XQCCMP32-NEXT:    fmv.s fs0, fa0
 ; XQCCMP32-NEXT:    call callee
 ; XQCCMP32-NEXT:    fmv.s fa0, fs0
-; XQCCMP32-NEXT:    flw fs0, 8(sp) # 4-byte Folded Reload
+; XQCCMP32-NEXT:    flw fs0, 12(sp) # 4-byte Folded Reload
 ; XQCCMP32-NEXT:    .cfi_restore fs0
-; XQCCMP32-NEXT:    qc.cm.popret {ra}, 16
+; XQCCMP32-NEXT:    qc.cm.popret {ra}, 32
 ;
 ; XQCCMP64-LABEL: foo:
 ; XQCCMP64:       # %bb.0: # %entry
-; XQCCMP64-NEXT:    qc.cm.push {ra}, -16
-; XQCCMP64-NEXT:    .cfi_def_cfa_offset 16
+; XQCCMP64-NEXT:    qc.cm.push {ra}, -32
+; XQCCMP64-NEXT:    .cfi_def_cfa_offset 32
 ; XQCCMP64-NEXT:    .cfi_offset ra, -8
-; XQCCMP64-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
-; XQCCMP64-NEXT:    .cfi_offset fs0, -12
+; XQCCMP64-NEXT:    fsw fs0, 12(sp) # 4-byte Folded Spill
+; XQCCMP64-NEXT:    .cfi_offset fs0, -20
 ; XQCCMP64-NEXT:    fmv.s fs0, fa0
 ; XQCCMP64-NEXT:    call callee
 ; XQCCMP64-NEXT:    fmv.s fa0, fs0
-; XQCCMP64-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; XQCCMP64-NEXT:    flw fs0, 12(sp) # 4-byte Folded Reload
 ; XQCCMP64-NEXT:    .cfi_restore fs0
-; XQCCMP64-NEXT:    qc.cm.popret {ra}, 16
+; XQCCMP64-NEXT:    qc.cm.popret {ra}, 32
 entry:
   call void @callee()
   ret float %arg
@@ -41,20 +41,20 @@ entry:
 define void @foo2(i32 %x, float %y) {
 ; XQCCMP32-LABEL: foo2:
 ; XQCCMP32:       # %bb.0: # %entry
-; XQCCMP32-NEXT:    qc.cm.push {ra, s0}, -16
-; XQCCMP32-NEXT:    .cfi_def_cfa_offset 16
+; XQCCMP32-NEXT:    qc.cm.push {ra, s0}, -32
+; XQCCMP32-NEXT:    .cfi_def_cfa_offset 32
 ; XQCCMP32-NEXT:    .cfi_offset ra, -4
 ; XQCCMP32-NEXT:    .cfi_offset s0, -8
-; XQCCMP32-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
-; XQCCMP32-NEXT:    .cfi_offset fs0, -12
+; XQCCMP32-NEXT:    fsw fs0, 12(sp) # 4-byte Folded Spill
+; XQCCMP32-NEXT:    .cfi_offset fs0, -20
 ; XQCCMP32-NEXT:    fmv.s fs0, fa0
 ; XQCCMP32-NEXT:    mv s0, a0
 ; XQCCMP32-NEXT:    call bar
 ; XQCCMP32-NEXT:    mv a0, s0
 ; XQCCMP32-NEXT:    fmv.s fa0, fs0
-; XQCCMP32-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; XQCCMP32-NEXT:    flw fs0, 12(sp) # 4-byte Folded Reload
 ; XQCCMP32-NEXT:    .cfi_restore fs0
-; XQCCMP32-NEXT:    qc.cm.pop {ra, s0}, 16
+; XQCCMP32-NEXT:    qc.cm.pop {ra, s0}, 32
 ; XQCCMP32-NEXT:    .cfi_restore ra
 ; XQCCMP32-NEXT:    .cfi_restore s0
 ; XQCCMP32-NEXT:    .cfi_def_cfa_offset 0
diff --git a/llvm/test/CodeGen/RISCV/zalasr-offset-folding.ll b/llvm/test/CodeGen/RISCV/zalasr-offset-folding.ll
new file mode 100644
index 0000000000000..78653ba3b78ef
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/zalasr-offset-folding.ll
@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=riscv32 -mattr=+a,+experimental-zalasr | FileCheck %s
+
+; Make sure we don't fold -1920 into the lw instruction because we still
+; need it for the sw.rl.
+
+define i32 @test(ptr %p) {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lui a1, 20
+; CHECK-NEXT:    addi a1, a1, -1920
+; CHECK-NEXT:    add a0, a0, a1
+; CHECK-NEXT:    li a1, 2
+; CHECK-NEXT:    sw.rl a1, (a0)
+; CHECK-NEXT:    lw a0, 0(a0)
+; CHECK-NEXT:    ret
+entry:
+  %gep0 = getelementptr [65536 x i32], ptr %p, i64 0, i32 20000
+  store atomic i32 2, ptr %gep0 seq_cst, align 4
+  %a = load i32, ptr %gep0
+  ret i32 %a
+}
diff --git a/llvm/test/CodeGen/RISCV/zcmp-additional-stack.ll b/llvm/test/CodeGen/RISCV/zcmp-additional-stack.ll
index 61c1de588a6e1..c98b9b80378fd 100644
--- a/llvm/test/CodeGen/RISCV/zcmp-additional-stack.ll
+++ b/llvm/test/CodeGen/RISCV/zcmp-additional-stack.ll
@@ -8,8 +8,8 @@ define ptr @func(ptr %s, i32 %_c, ptr %incdec.ptr, i1 %0, i8 %conv14) #0 {
 ; RV32-NEXT:    .cfi_offset ra, -12
 ; RV32-NEXT:    .cfi_offset s0, -8
 ; RV32-NEXT:    .cfi_offset s1, -4
-; RV32-NEXT:    addi sp, sp, -4
-; RV32-NEXT:    .cfi_def_cfa_offset 20
+; RV32-NEXT:    addi sp, sp, -8
+; RV32-NEXT:    .cfi_def_cfa_offset 24
 ; RV32-NEXT:    sw a4, 4(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    sw a2, 0(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    mv a2, a1
@@ -33,7 +33,7 @@ define ptr @func(ptr %s, i32 %_c, ptr %incdec.ptr, i1 %0, i8 %conv14) #0 {
 ; RV32-NEXT:    lw a0, 4(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    sb a0, 0(s0)
 ; RV32-NEXT:    mv a0, s1
-; RV32-NEXT:    addi sp, sp, 4
+; RV32-NEXT:    addi sp, sp, 8
 ; RV32-NEXT:    .cfi_def_cfa_offset 16
 ; RV32-NEXT:    cm.popret {ra, s0-s1}, 16
 entry:
diff --git a/llvm/test/CodeGen/RISCV/zcmp-with-float.ll b/llvm/test/CodeGen/RISCV/zcmp-with-float.ll
index 638a3af00eec8..d2ecba2fe8d18 100644
--- a/llvm/test/CodeGen/RISCV/zcmp-with-float.ll
+++ b/llvm/test/CodeGen/RISCV/zcmp-with-float.ll
@@ -8,31 +8,31 @@ declare void @callee()
 define float @foo(float %arg) {
 ; RV32-LABEL: foo:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    cm.push {ra}, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
+; RV32-NEXT:    cm.push {ra}, -32
+; RV32-NEXT:    .cfi_def_cfa_offset 32
 ; RV32-NEXT:    .cfi_offset ra, -4
-; RV32-NEXT:    fsw fs0, 8(sp) # 4-byte Folded Spill
-; RV32-NEXT:    .cfi_offset fs0, -8
+; RV32-NEXT:    fsw fs0, 12(sp) # 4-byte Folded Spill
+; RV32-NEXT:    .cfi_offset fs0, -20
 ; RV32-NEXT:    fmv.s fs0, fa0
 ; RV32-NEXT:    call callee
 ; RV32-NEXT:    fmv.s fa0, fs0
-; RV32-NEXT:    flw fs0, 8(sp) # 4-byte Folded Reload
+; RV32-NEXT:    flw fs0, 12(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    .cfi_restore fs0
-; RV32-NEXT:    cm.popret {ra}, 16
+; RV32-NEXT:    cm.popret {ra}, 32
 ;
 ; RV64-LABEL: foo:
 ; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    cm.push {ra}, -16
-; RV64-NEXT:    .cfi_def_cfa_offset 16
+; RV64-NEXT:    cm.push {ra}, -32
+; RV64-NEXT:    .cfi_def_cfa_offset 32
 ; RV64-NEXT:    .cfi_offset ra, -8
-; RV64-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
-; RV64-NEXT:    .cfi_offset fs0, -12
+; RV64-NEXT:    fsw fs0, 12(sp) # 4-byte Folded Spill
+; RV64-NEXT:    .cfi_offset fs0, -20
 ; RV64-NEXT:    fmv.s fs0, fa0
 ; RV64-NEXT:    call callee
 ; RV64-NEXT:    fmv.s fa0, fs0
-; RV64-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV64-NEXT:    flw fs0, 12(sp) # 4-byte Folded Reload
 ; RV64-NEXT:    .cfi_restore fs0
-; RV64-NEXT:    cm.popret {ra}, 16
+; RV64-NEXT:    cm.popret {ra}, 32
 entry:
   call void @callee()
   ret float %arg
@@ -41,20 +41,20 @@ entry:
 define void @foo2(i32 %x, float %y) {
 ; RV32-LABEL: foo2:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    cm.push {ra, s0}, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
+; RV32-NEXT:    cm.push {ra, s0}, -32
+; RV32-NEXT:    .cfi_def_cfa_offset 32
 ; RV32-NEXT:    .cfi_offset ra, -8
 ; RV32-NEXT:    .cfi_offset s0, -4
-; RV32-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
-; RV32-NEXT:    .cfi_offset fs0, -12
+; RV32-NEXT:    fsw fs0, 12(sp) # 4-byte Folded Spill
+; RV32-NEXT:    .cfi_offset fs0, -20
 ; RV32-NEXT:    fmv.s fs0, fa0
 ; RV32-NEXT:    mv s0, a0
 ; RV32-NEXT:    call bar
 ; RV32-NEXT:    mv a0, s0
 ; RV32-NEXT:    fmv.s fa0, fs0
-; RV32-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32-NEXT:    flw fs0, 12(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    .cfi_restore fs0
-; RV32-NEXT:    cm.pop {ra, s0}, 16
+; RV32-NEXT:    cm.pop {ra, s0}, 32
 ; RV32-NEXT:    .cfi_restore ra
 ; RV32-NEXT:    .cfi_restore s0
 ; RV32-NEXT:    .cfi_def_cfa_offset 0
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroup_matrix_multiply_accumulate/subgroup_matrix_multiply_accumulate_generic.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroup_matrix_multiply_accumulate/subgroup_matrix_multiply_accumulate_generic.ll
new file mode 100644
index 0000000000000..0cd6992936eeb
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroup_matrix_multiply_accumulate/subgroup_matrix_multiply_accumulate_generic.ll
@@ -0,0 +1,229 @@
+; Adapted from Khronos Translator: subgroup_matrix_multiply_accumulate_generic.ll
+
+; generated with mma.cl:
+; #pragma OPENCL EXTENSION cl_khr_fp16 : enable
+; 
+; // all combinations of parameter types
+; int  __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, int  Matrix_A, int8 Matrix_B, int  Matrix_C, int Operands);
+; int2 __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, int2 Matrix_A, int8 Matrix_B, int2 Matrix_C, int Operands);
+; int4 __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, int4 Matrix_A, int8 Matrix_B, int4 Matrix_C, int Operands);
+; int8 __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, int8 Matrix_A, int8 Matrix_B, int8 Matrix_C, int Operands);
+; 
+; float  __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, int  Matrix_A, int8 Matrix_B, float  Matrix_C, int Operands);
+; float2 __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, int2 Matrix_A, int8 Matrix_B, float2 Matrix_C, int Operands);
+; float4 __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, int4 Matrix_A, int8 Matrix_B, float4 Matrix_C, int Operands);
+; float8 __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, int8 Matrix_A, int8 Matrix_B, float8 Matrix_C, int Operands);
+; 
+; int  __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, short  Matrix_A, int8 Matrix_B, int  Matrix_C, int Operands);
+; int2 __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, short2 Matrix_A, int8 Matrix_B, int2 Matrix_C, int Operands);
+; int4 __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, short4 Matrix_A, int8 Matrix_B, int4 Matrix_C, int Operands);
+; int8 __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, short8 Matrix_A, int8 Matrix_B, int8 Matrix_C, int Operands);
+; 
+; float  __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, short  Matrix_A, int8 Matrix_B, float  Matrix_C, int Operands);
+; float2 __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, short2 Matrix_A, int8 Matrix_B, float2 Matrix_C, int Operands);
+; float4 __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, short4 Matrix_A, int8 Matrix_B, float4 Matrix_C, int Operands);
+; float8 __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, short8 Matrix_A, int8 Matrix_B, float8 Matrix_C, int Operands);
+; 
+; half  __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, short  Matrix_A, int8 Matrix_B, half  Matrix_C, int Operands);
+; half2 __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, short2 Matrix_A, int8 Matrix_B, half2 Matrix_C, int Operands);
+; half4 __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, short4 Matrix_A, int8 Matrix_B, half4 Matrix_C, int Operands);
+; half8 __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, short8 Matrix_A, int8 Matrix_B, half8 Matrix_C, int Operands);
+; 
+; short  __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, short  Matrix_A, int8 Matrix_B, short  Matrix_C, int Operands);
+; short2 __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, short2 Matrix_A, int8 Matrix_B, short2 Matrix_C, int Operands);
+; short4 __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, short4 Matrix_A, int8 Matrix_B, short4 Matrix_C, int Operands);
+; short8 __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, short8 Matrix_A, int8 Matrix_B, short8 Matrix_C, int Operands);
+; 
+; float  __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, float  Matrix_A, float8 Matrix_B, float  Matrix_C, int Operands);
+; float2 __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, float2 Matrix_A, float8 Matrix_B, float2 Matrix_C, int Operands);
+; float4 __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, float4 Matrix_A, float8 Matrix_B, float4 Matrix_C, int Operands);
+; float8 __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, float8 Matrix_A, float8 Matrix_B, float8 Matrix_C, int Operands);
+; 
+; // no operands
+; float4 __spirv_SubgroupMatrixMultiplyAccumulateINTEL(int K_Dim, short4 Matrix_A, int8 Matrix_B, float4 Matrix_C);
+; 
+; void foo(int iM, int2 iM2, int4 iM4, int8 iM8,
+;          short sM, short2 sM2, short4 sM4, short8 sM8,
+;          float fM, float2 fM2, float4 fM4, float8 fM8,
+;          half hM, half2 hM2, half4 hM4, half8 hM8) {
+;     const int i = 42;
+;     int D = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, iM, iM8, iM, 0xA);
+;     int2 D2 = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, iM2, iM8, iM2, 0xA);
+;     int4 D4 = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, iM4, iM8, iM4, 0xA);
+;     int8 D8 = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, iM8, iM8, iM8, 0xA);
+; 
+;     float fD = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, iM, iM8, fM, 0xA);
+;     float2 fD2 = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, iM2, iM8, fM2, 0xA);
+;     float4 fD4 = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, iM4, iM8, fM4, 0xA);
+;     float8 fD8 = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, iM8, iM8, fM8, 0xA);
+; 
+;     int sD = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, sM, iM8, iM, 0xA);
+;     int2 sD2 = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, sM2, iM8, iM2, 0xA);
+;     int4 sD4 = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, sM4, iM8, iM4, 0xA);
+;     int8 sD8 = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, sM8, iM8, iM8, 0xA);
+; 
+;     float sfD = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, sM, iM8, fM, 0xA);
+;     float2 sfD2 = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, sM2, iM8, fM2, 0xA);
+;     float4 sfD4 = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, sM4, iM8, fM4, 0xA);
+;     float8 sfD8 = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, sM8, iM8, fM8, 0xA);
+; 
+;     half hD = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, sM, iM8, hM, 0xA);
+;     half2 hD2 = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, sM2, iM8, hM2, 0xA);
+;     half4 hD4 = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, sM4, iM8, hM4, 0xA);
+;     half8 hD8 = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, sM8, iM8, hM8, 0xA);
+; 
+;     short ssD = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, sM, iM8, sM, 0xA);
+;     short2 ssD2 = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, sM2, iM8, sM2, 0xA);
+;     short4 ssD4 = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, sM4, iM8, sM4, 0xA);
+;     short8 ssD8 = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, sM8, iM8, sM8, 0xA);
+; 
+;     float ffD = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, fM, fM8, fM, 0xA);
+;     float2 ffD2 = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, fM2, fM8, fM2, 0xA);
+;     float4 ffD4 = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, fM4, fM8, fM4, 0xA);
+;     float8 ffD8 = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, fM8, fM8, fM8, 0xA);
+; 
+;     float4 noOpD4 = __spirv_SubgroupMatrixMultiplyAccumulateINTEL(i, sM4, iM8, fM4);
+; }
+; clang -cc1 -cl-std=clc++2021 -triple spir64-unknown-unknown -emit-llvm -finclude-default-header mma.cl -o tmp.ll
+
+; RUN: not llc -O0 -mtriple=spirv32-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+; CHECK-ERROR: requires the following SPIR-V extension: SPV_INTEL_subgroup_matrix_multiply_accumulate
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_subgroup_matrix_multiply_accumulate %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_subgroup_matrix_multiply_accumulate %s -o - -filetype=obj | spirv-val %}
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_subgroup_matrix_multiply_accumulate %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_subgroup_matrix_multiply_accumulate %s -o - -filetype=obj | spirv-val %}
+
+; CHECK: OpCapability SubgroupMatrixMultiplyAccumulateINTEL
+; CHECK: OpExtension "SPV_INTEL_subgroup_matrix_multiply_accumulate"
+; CHECK-DAG: %[[#Int32Ty:]] = OpTypeInt 32 0
+; CHECK-DAG: %[[#Int16Ty:]] = OpTypeInt 16 0
+; CHECK-DAG: %[[#Const42:]] = OpConstant %[[#Int32Ty]] 42
+; CHECK-DAG: %[[#VoidTy:]] = OpTypeVoid
+; CHECK-DAG: %[[#Vec2Int32Ty:]] = OpTypeVector %[[#Int32Ty]] 2
+; CHECK-DAG: %[[#Vec4Int32Ty:]] = OpTypeVector %[[#Int32Ty]] 4
+; CHECK-DAG: %[[#Vec8Int32Ty:]] = OpTypeVector %[[#Int32Ty]] 8
+; CHECK-DAG: %[[#Vec2Int16Ty:]] = OpTypeVector %[[#Int16Ty]] 2
+; CHECK-DAG: %[[#Vec4Int16Ty:]] = OpTypeVector %[[#Int16Ty]] 4
+; CHECK-DAG: %[[#Vec8Int16Ty:]] = OpTypeVector %[[#Int16Ty]] 8
+; CHECK-DAG: %[[#FloatTy:]] = OpTypeFloat 32
+; CHECK-DAG: %[[#Vec2FloatTy:]] = OpTypeVector %[[#FloatTy]] 2
+; CHECK-DAG: %[[#Vec4FloatTy:]] = OpTypeVector %[[#FloatTy]] 4
+; CHECK-DAG: %[[#Vec8FloatTy:]] = OpTypeVector %[[#FloatTy]] 8
+; CHECK-DAG: %[[#HalfTy:]] = OpTypeFloat 16
+; CHECK-DAG: %[[#Vec2HalfTy:]] = OpTypeVector %[[#HalfTy]] 2
+; CHECK-DAG: %[[#Vec4HalfTy:]] = OpTypeVector %[[#HalfTy]] 4
+; CHECK-DAG: %[[#Vec8HalfTy:]] = OpTypeVector %[[#HalfTy]] 8
+; CHECK: %[[#iM:]] = OpFunctionParameter %[[#Int32Ty]]
+; CHECK: %[[#iM2:]] = OpFunctionParameter %[[#Vec2Int32Ty]]
+; CHECK: %[[#iM4:]] = OpFunctionParameter %[[#Vec4Int32Ty]]
+; CHECK: %[[#iM8:]] = OpFunctionParameter %[[#Vec8Int32Ty]]
+; CHECK: %[[#sM:]] = OpFunctionParameter %[[#Int16Ty]]
+; CHECK: %[[#sM2:]] = OpFunctionParameter %[[#Vec2Int16Ty]]
+; CHECK: %[[#sM4:]] = OpFunctionParameter %[[#Vec4Int16Ty]]
+; CHECK: %[[#sM8:]] = OpFunctionParameter %[[#Vec8Int16Ty]]
+; CHECK: %[[#fM:]] = OpFunctionParameter %[[#FloatTy]]
+; CHECK: %[[#fM2:]]  = OpFunctionParameter %[[#Vec2FloatTy]]
+; CHECK: %[[#fM4:]] = OpFunctionParameter %[[#Vec4FloatTy]]
+; CHECK: %[[#fM8:]] = OpFunctionParameter %[[#Vec8FloatTy]]
+; CHECK: %[[#hM:]] = OpFunctionParameter %[[#HalfTy]]
+; CHECK: %[[#hM2:]] = OpFunctionParameter %[[#Vec2HalfTy]]
+; CHECK: %[[#hM4:]] = OpFunctionParameter %[[#Vec4HalfTy]]
+; CHECK: %[[#hM8:]] = OpFunctionParameter %[[#Vec8HalfTy]]
+; CHECK: %[[#]] = OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Int32Ty]] %[[#Const42]] %[[#iM]] %[[#iM8]] %[[#iM]] 10 
+; CHECK: %[[#]] = OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec2Int32Ty]] %[[#Const42]] %[[#iM2]] %[[#iM8]] %[[#iM2]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec4Int32Ty]] %[[#Const42]] %[[#iM4]] %[[#iM8]] %[[#iM4]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec8Int32Ty]] %[[#Const42]] %[[#iM8]] %[[#iM8]] %[[#iM8]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#FloatTy]] %[[#Const42]] %[[#iM]] %[[#iM8]] %[[#fM]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec2FloatTy]] %[[#Const42]] %[[#iM2]] %[[#iM8]] %[[#fM2]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec4FloatTy]] %[[#Const42]] %[[#iM4]] %[[#iM8]] %[[#fM4]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec8FloatTy]] %[[#Const42]] %[[#iM8]] %[[#iM8]] %[[#fM8]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Int32Ty]] %[[#Const42]] %[[#sM]] %[[#iM8]] %[[#iM]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec2Int32Ty]] %[[#Const42]] %[[#sM2]] %[[#iM8]] %[[#iM2]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec4Int32Ty]] %[[#Const42]] %[[#sM4]] %[[#iM8]] %[[#iM4]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec8Int32Ty]] %[[#Const42]] %[[#sM8]] %[[#iM8]] %[[#iM8]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#FloatTy]] %[[#Const42]] %[[#sM]] %[[#iM8]] %[[#fM]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec2FloatTy]] %[[#Const42]] %[[#sM2]] %[[#iM8]] %[[#fM2]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec4FloatTy]] %[[#Const42]] %[[#sM4]] %[[#iM8]] %[[#fM4]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec8FloatTy]] %[[#Const42]] %[[#sM8]] %[[#iM8]] %[[#fM8]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#HalfTy]] %[[#Const42]] %[[#sM]] %[[#iM8]] %[[#hM]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec2HalfTy]] %[[#Const42]] %[[#sM2]] %[[#iM8]] %[[#hM2]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec4HalfTy]] %[[#Const42]] %[[#sM4]] %[[#iM8]] %[[#hM4]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec8HalfTy]] %[[#Const42]] %[[#sM8]] %[[#iM8]] %[[#hM8]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Int16Ty]] %[[#Const42]] %[[#sM]] %[[#iM8]] %[[#sM]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec2Int16Ty]] %[[#Const42]] %[[#sM2]] %[[#iM8]] %[[#sM2]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec4Int16Ty]] %[[#Const42]] %[[#sM4]] %[[#iM8]] %[[#sM4]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec8Int16Ty]] %[[#Const42]] %[[#sM8]] %[[#iM8]] %[[#sM8]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#FloatTy]] %[[#Const42]] %[[#fM]] %[[#fM8]] %[[#fM]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec2FloatTy]] %[[#Const42]] %[[#fM2]] %[[#fM8]] %[[#fM2]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec4FloatTy]] %[[#Const42]] %[[#fM4]] %[[#fM8]] %[[#fM4]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec8FloatTy]] %[[#Const42]] %[[#fM8]] %[[#fM8]] %[[#fM8]] 10 
+; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec4FloatTy]] %[[#Const42]] %[[#sM4]] %[[#iM8]] %[[#fM4]] 
+
+define spir_func void @foo(i32 %iM, <2 x i32> %iM2, <4 x i32> %iM4, <8 x i32> %iM8,
+                           i16 signext %sM, <2 x i16> %sM2, <4 x i16> %sM4, <8 x i16> %sM8,
+                           float %fM, <2 x float> %fM2, <4 x float> %fM4, <8 x float> %fM8,
+                           half %hM, <2 x half> %hM2, <4 x half> %hM4, <8 x half> %hM8) {
+entry:
+  %call = call spir_func i32 @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiiDv8_iii(i32 42, i32 %iM, <8 x i32> %iM8, i32 %iM, i32 10)
+  %call1 = call spir_func <2 x i32> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv2_iDv8_iS_i(i32 42, <2 x i32> %iM2, <8 x i32> %iM8, <2 x i32> %iM2, i32 10)
+  %call2 = call spir_func <4 x i32> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv4_iDv8_iS_i(i32 42, <4 x i32> %iM4, <8 x i32> %iM8, <4 x i32> %iM4, i32 10)
+  %call3 = call spir_func <8 x i32> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv8_iS_S_i(i32 42, <8 x i32> %iM8, <8 x i32> %iM8, <8 x i32> %iM8, i32 10)
+  %call4 = call spir_func float @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiiDv8_ifi(i32 42, i32 %iM, <8 x i32> %iM8, float %fM, i32 10)
+  %call5 = call spir_func <2 x float> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv2_iDv8_iDv2_fi(i32 42, <2 x i32> %iM2, <8 x i32> %iM8, <2 x float> %fM2, i32 10)
+  %call6 = call spir_func <4 x float> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv4_iDv8_iDv4_fi(i32 42, <4 x i32> %iM4, <8 x i32> %iM8, <4 x float> %fM4, i32 10)
+  %call7 = call spir_func <8 x float> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv8_iS_Dv8_fi(i32 42, <8 x i32> %iM8, <8 x i32> %iM8, <8 x float> %fM8, i32 10)
+  %call8 = call spir_func i32 @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELisDv8_iii(i32 42, i16 signext %sM, <8 x i32> %iM8, i32 %iM, i32 10)
+  %call9 = call spir_func <2 x i32> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv2_sDv8_iDv2_ii(i32 42, <2 x i16> %sM2, <8 x i32> %iM8, <2 x i32> %iM2, i32 10)
+  %call10 = call spir_func <4 x i32> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv4_sDv8_iDv4_ii(i32 42, <4 x i16> %sM4, <8 x i32> %iM8, <4 x i32> %iM4, i32 10)
+  %call11 = call spir_func <8 x i32> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv8_sDv8_iS0_i(i32 42, <8 x i16> %sM8, <8 x i32> %iM8, <8 x i32> %iM8, i32 10)
+  %call12 = call spir_func float @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELisDv8_ifi(i32 42, i16 signext %sM, <8 x i32> %iM8, float %fM, i32 10)
+  %call13 = call spir_func <2 x float> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv2_sDv8_iDv2_fi(i32 42, <2 x i16> %sM2, <8 x i32> %iM8, <2 x float> %fM2, i32 10)
+  %call14 = call spir_func <4 x float> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv4_sDv8_iDv4_fi(i32 42, <4 x i16> %sM4, <8 x i32> %iM8, <4 x float> %fM4, i32 10)
+  %call15 = call spir_func <8 x float> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv8_sDv8_iDv8_fi(i32 42, <8 x i16> %sM8, <8 x i32> %iM8, <8 x float> %fM8, i32 10)
+  %call16 = call spir_func half @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELisDv8_iDhi(i32 42, i16 signext %sM, <8 x i32> %iM8, half %hM, i32 10)
+  %call17 = call spir_func <2 x half> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv2_sDv8_iDv2_Dhi(i32 42, <2 x i16> %sM2, <8 x i32> %iM8, <2 x half> %hM2, i32 10)
+  %call18 = call spir_func <4 x half> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv4_sDv8_iDv4_Dhi(i32 42, <4 x i16> %sM4, <8 x i32> %iM8, <4 x half> %hM4, i32 10)
+  %call19 = call spir_func <8 x half> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv8_sDv8_iDv8_Dhi(i32 42, <8 x i16> %sM8, <8 x i32> %iM8, <8 x half> %hM8, i32 10)
+  %call20 = call spir_func signext i16 @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELisDv8_isi(i32 42, i16 signext %sM, <8 x i32> %iM8, i16 signext %sM, i32 10)
+  %call21 = call spir_func <2 x i16> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv2_sDv8_iS_i(i32 42, <2 x i16> %sM2, <8 x i32> %iM8, <2 x i16> %sM2, i32 10)
+  %call22 = call spir_func <4 x i16> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv4_sDv8_iS_i(i32 42, <4 x i16> %sM4, <8 x i32> %iM8, <4 x i16> %sM4, i32 10)
+  %call23 = call spir_func <8 x i16> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv8_sDv8_iS_i(i32 42, <8 x i16> %sM8, <8 x i32> %iM8, <8 x i16> %sM8, i32 10)
+  %call24 = call spir_func float @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELifDv8_ffi(i32 42, float %fM, <8 x float> %fM8, float %fM, i32 10)
+  %call25 = call spir_func <2 x float> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv2_fDv8_fS_i(i32 42, <2 x float> %fM2, <8 x float> %fM8, <2 x float> %fM2, i32 10)
+  %call26 = call spir_func <4 x float> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv4_fDv8_fS_i(i32 42, <4 x float> %fM4, <8 x float> %fM8, <4 x float> %fM4, i32 10)
+  %call27 = call spir_func <8 x float> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv8_fS_S_i(i32 42, <8 x float> %fM8, <8 x float> %fM8, <8 x float> %fM8, i32 10)
+  %call28 = call spir_func <4 x float> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv4_sDv8_iDv4_f(i32 42, <4 x i16> %sM4, <8 x i32> %iM8, <4 x float> %fM4)
+  ret void
+}
+
+declare spir_func i32 @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiiDv8_iii(i32, i32, <8 x i32>, i32, i32)
+declare spir_func <2 x i32> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv2_iDv8_iS_i(i32, <2 x i32>, <8 x i32>, <2 x i32>, i32)
+declare spir_func <4 x i32> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv4_iDv8_iS_i(i32, <4 x i32>, <8 x i32>, <4 x i32>, i32)
+declare spir_func <8 x i32> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv8_iS_S_i(i32, <8 x i32>, <8 x i32>, <8 x i32>, i32)
+declare spir_func float @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiiDv8_ifi(i32, i32, <8 x i32>, float, i32)
+declare spir_func <2 x float> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv2_iDv8_iDv2_fi(i32, <2 x i32>, <8 x i32>, <2 x float>, i32)
+declare spir_func <4 x float> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv4_iDv8_iDv4_fi(i32, <4 x i32>, <8 x i32>, <4 x float>, i32)
+declare spir_func <8 x float> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv8_iS_Dv8_fi(i32, <8 x i32>, <8 x i32>, <8 x float>, i32)
+declare spir_func i32 @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELisDv8_iii(i32, i16 signext, <8 x i32>, i32, i32)
+declare spir_func <2 x i32> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv2_sDv8_iDv2_ii(i32, <2 x i16>, <8 x i32>, <2 x i32>, i32)
+declare spir_func <4 x i32> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv4_sDv8_iDv4_ii(i32, <4 x i16>, <8 x i32>, <4 x i32>, i32)
+declare spir_func <8 x i32> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv8_sDv8_iS0_i(i32, <8 x i16>, <8 x i32>, <8 x i32>, i32)
+declare spir_func float @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELisDv8_ifi(i32, i16 signext, <8 x i32>, float, i32)
+declare spir_func <2 x float> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv2_sDv8_iDv2_fi(i32, <2 x i16>, <8 x i32>, <2 x float>, i32)
+declare spir_func <4 x float> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv4_sDv8_iDv4_fi(i32, <4 x i16>, <8 x i32>, <4 x float>, i32)
+declare spir_func <8 x float> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv8_sDv8_iDv8_fi(i32, <8 x i16>, <8 x i32>, <8 x float>, i32)
+declare spir_func half @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELisDv8_iDhi(i32, i16 signext, <8 x i32>, half, i32)
+declare spir_func <2 x half> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv2_sDv8_iDv2_Dhi(i32, <2 x i16>, <8 x i32>, <2 x half>, i32)
+declare spir_func <4 x half> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv4_sDv8_iDv4_Dhi(i32, <4 x i16>, <8 x i32>, <4 x half>, i32)
+declare spir_func <8 x half> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv8_sDv8_iDv8_Dhi(i32, <8 x i16>, <8 x i32>, <8 x half>, i32)
+declare spir_func signext i16 @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELisDv8_isi(i32, i16 signext, <8 x i32>, i16 signext, i32)
+declare spir_func <2 x i16> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv2_sDv8_iS_i(i32, <2 x i16>, <8 x i32>, <2 x i16>, i32)
+declare spir_func <4 x i16> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv4_sDv8_iS_i(i32, <4 x i16>, <8 x i32>, <4 x i16>, i32)
+declare spir_func <8 x i16> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv8_sDv8_iS_i(i32, <8 x i16>, <8 x i32>, <8 x i16>, i32)
+declare spir_func float @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELifDv8_ffi(i32, float, <8 x float>, float, i32)
+declare spir_func <2 x float> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv2_fDv8_fS_i(i32, <2 x float>, <8 x float>, <2 x float>, i32)
+declare spir_func <4 x float> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv4_fDv8_fS_i(i32, <4 x float>, <8 x float>, <4 x float>, i32)
+declare spir_func <8 x float> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv8_fS_S_i(i32, <8 x float>, <8 x float>, <8 x float>, i32)
+declare spir_func <4 x float> @_Z45__spirv_SubgroupMatrixMultiplyAccumulateINTELiDv4_sDv8_iDv4_f(i32, <4 x i16>, <8 x i32>, <4 x float>)
diff --git a/llvm/test/CodeGen/SystemZ/fp-abs-01.ll b/llvm/test/CodeGen/SystemZ/fp-abs-01.ll
index 0cfdefe3bd61b..fe573f1e3587e 100644
--- a/llvm/test/CodeGen/SystemZ/fp-abs-01.ll
+++ b/llvm/test/CodeGen/SystemZ/fp-abs-01.ll
@@ -7,10 +7,9 @@
 declare half @llvm.fabs.f16(half %f)
 define half @f0(half %f) {
 ; CHECK-LABEL: f0:
-; CHECK:      brasl %r14, __extendhfsf2@PLT
+; CHECK:      # %bb.0:
 ; CHECK-NEXT: lpdfr %f0, %f0
-; CHECK-NEXT: brasl %r14, __truncsfhf2@PLT
-; CHECK: br %r14
+; CHECK-NEXT: br %r14
   %res = call half @llvm.fabs.f16(half %f)
   ret half %res
 }
diff --git a/llvm/test/CodeGen/SystemZ/fp-abs-02.ll b/llvm/test/CodeGen/SystemZ/fp-abs-02.ll
index 4266a893e8a3b..752609ef6d00d 100644
--- a/llvm/test/CodeGen/SystemZ/fp-abs-02.ll
+++ b/llvm/test/CodeGen/SystemZ/fp-abs-02.ll
@@ -3,6 +3,18 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
 
+; Test f16.
+declare half @llvm.fabs.f16(half %f)
+define half @f0(half %f) {
+; CHECK-LABEL: f0:
+; CHECK:      # %bb.0:
+; CHECK-NEXT: lndfr %f0, %f0
+; CHECK-NEXT: br %r14
+  %abs = call half @llvm.fabs.f16(half %f)
+  %res = fneg half %abs
+  ret half %res
+}
+
 ; Test f32.
 declare float @llvm.fabs.f32(float %f)
 define float @f1(float %f) {
diff --git a/llvm/test/CodeGen/SystemZ/fp-abs-03.ll b/llvm/test/CodeGen/SystemZ/fp-abs-03.ll
index 29f2d06e75ff9..029ae2309cab9 100644
--- a/llvm/test/CodeGen/SystemZ/fp-abs-03.ll
+++ b/llvm/test/CodeGen/SystemZ/fp-abs-03.ll
@@ -6,10 +6,9 @@
 declare half @llvm.fabs.f16(half %f)
 define half @f0(half %f) {
 ; CHECK-LABEL: f0:
-; CHECK:      brasl %r14, __extendhfsf2@PLT
+; CHECK:      # %bb.0:
 ; CHECK-NEXT: lpdfr %f0, %f0
-; CHECK-NEXT: brasl %r14, __truncsfhf2@PLT
-; CHECK: br %r14
+; CHECK-NEXT: br %r14
   %res = call half @llvm.fabs.f16(half %f)
   ret half %res
 }
diff --git a/llvm/test/CodeGen/SystemZ/fp-abs-04.ll b/llvm/test/CodeGen/SystemZ/fp-abs-04.ll
index afaf3f6d22ac8..fbb43b69371f3 100644
--- a/llvm/test/CodeGen/SystemZ/fp-abs-04.ll
+++ b/llvm/test/CodeGen/SystemZ/fp-abs-04.ll
@@ -6,13 +6,9 @@
 declare half @llvm.fabs.f16(half %f)
 define half @f0(half %f) {
 ; CHECK-LABEL: f0:
-; CHECK:      brasl   %r14, __extendhfsf2@PLT
-; CHECK-NEXT: lpdfr   %f0, %f0
-; CHECK-NEXT: brasl   %r14, __truncsfhf2@PLT
-; CHECK-NEXT: brasl   %r14, __extendhfsf2@PLT
-; CHECK-NEXT: lcdfr   %f0, %f0
-; CHECK-NEXT: brasl   %r14, __truncsfhf2@PLT
-; CHECK: br %r14
+; CHECK:      # %bb.0:
+; CHECK-NEXT: lndfr %f0, %f0
+; CHECK-NEXT: br %r14
   %abs = call half @llvm.fabs.f16(half %f)
   %res = fneg half %abs
   ret half %res
diff --git a/llvm/test/CodeGen/SystemZ/fp-copysign-01.ll b/llvm/test/CodeGen/SystemZ/fp-copysign-01.ll
index d2b6488008e6b..eee97b265a6af 100644
--- a/llvm/test/CodeGen/SystemZ/fp-copysign-01.ll
+++ b/llvm/test/CodeGen/SystemZ/fp-copysign-01.ll
@@ -1,4 +1,4 @@
-; Test copysign operations.
+; Test copysign libcalls.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
diff --git a/llvm/test/CodeGen/SystemZ/fp-copysign-02.ll b/llvm/test/CodeGen/SystemZ/fp-copysign-02.ll
index 178568ebb3bf9..86a4f21a6b594 100644
--- a/llvm/test/CodeGen/SystemZ/fp-copysign-02.ll
+++ b/llvm/test/CodeGen/SystemZ/fp-copysign-02.ll
@@ -1,4 +1,4 @@
-; Test f128 copysign operations on z14.
+; Test f128 copysign libcalls on z14.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
 
diff --git a/llvm/test/CodeGen/SystemZ/fp-copysign-03.ll b/llvm/test/CodeGen/SystemZ/fp-copysign-03.ll
index 909519e8ace55..c2c5889a689e4 100644
--- a/llvm/test/CodeGen/SystemZ/fp-copysign-03.ll
+++ b/llvm/test/CodeGen/SystemZ/fp-copysign-03.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z16 \
 ; RUN:   | FileCheck %s --check-prefixes=CHECK,Z16
 ;
-; Test copysign intrinsics with half.
+; Test copysign intrinsics.
 
 declare half @llvm.copysign.f16(half, half)
 declare float @llvm.copysign.f32(float, float)
@@ -43,53 +43,25 @@ define half @f2(half %a, double %b) {
 }
 
 ; Test copysign with an f16 result and f128 sign argument.
-; TODO: Let the DAGCombiner remove the fp_round.
 define half @f3(half %a, fp128 %b) {
 ; Z10-LABEL: f3:
 ; Z10:       # %bb.0:
-; Z10-NEXT:    stmg %r14, %r15, 112(%r15)
-; Z10-NEXT:    .cfi_offset %r14, -48
-; Z10-NEXT:    .cfi_offset %r15, -40
-; Z10-NEXT:    aghi %r15, -184
-; Z10-NEXT:    .cfi_def_cfa_offset 344
-; Z10-NEXT:    std %f8, 176(%r15) # 8-byte Spill
-; Z10-NEXT:    .cfi_offset %f8, -168
 ; Z10-NEXT:    ld %f1, 0(%r2)
 ; Z10-NEXT:    ld %f3, 8(%r2)
-; Z10-NEXT:    ler %f8, %f0
-; Z10-NEXT:    la %r2, 160(%r15)
-; Z10-NEXT:    std %f1, 160(%r15)
-; Z10-NEXT:    std %f3, 168(%r15)
-; Z10-NEXT:    brasl %r14, __trunctfhf2@PLT
-; Z10-NEXT:    cpsdr %f0, %f0, %f8
-; Z10-NEXT:    ld %f8, 176(%r15) # 8-byte Reload
-; Z10-NEXT:    lmg %r14, %r15, 296(%r15)
+; Z10-NEXT:    cpsdr %f0, %f1, %f0
 ; Z10-NEXT:    br %r14
 ;
 ; Z16-LABEL: f3:
 ; Z16:       # %bb.0:
-; Z16-NEXT:    stmg %r14, %r15, 112(%r15)
-; Z16-NEXT:    .cfi_offset %r14, -48
-; Z16-NEXT:    .cfi_offset %r15, -40
-; Z16-NEXT:    aghi %r15, -184
-; Z16-NEXT:    .cfi_def_cfa_offset 344
-; Z16-NEXT:    std %f8, 176(%r15) # 8-byte Spill
-; Z16-NEXT:    .cfi_offset %f8, -168
-; Z16-NEXT:    ldr %f8, %f0
-; Z16-NEXT:    vl %v0, 0(%r2), 3
-; Z16-NEXT:    la %r2, 160(%r15)
-; Z16-NEXT:    vst %v0, 160(%r15), 3
-; Z16-NEXT:    brasl %r14, __trunctfhf2@PLT
-; Z16-NEXT:    cpsdr %f0, %f0, %f8
-; Z16-NEXT:    ld %f8, 176(%r15) # 8-byte Reload
-; Z16-NEXT:    lmg %r14, %r15, 296(%r15)
+; Z16-NEXT:    vl %v1, 0(%r2), 3
+; Z16-NEXT:    cpsdr %f0, %f1, %f0
 ; Z16-NEXT:    br %r14
   %bh = fptrunc fp128 %b to half
   %res = call half @llvm.copysign.f16(half %a, half %bh)
   ret half %res
 }
 
-; Test copysign with an f32 result and half sign argument.
+; Test copysign with an f32 result and f16 sign argument.
 define float @f4(float %a, half %b) {
 ; CHECK-LABEL: f4:
 ; CHECK:       # %bb.0:
@@ -100,20 +72,100 @@ define float @f4(float %a, half %b) {
   ret float %res
 }
 
-; Test copysign with an f64 result and half sign argument.
-define double @f5(double %a, half %b) {
+; Test copysign with an f32 result and f32 sign argument.
+define float @f5(float %a, float %b) {
 ; CHECK-LABEL: f5:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    cpsdr %f0, %f2, %f0
+; CHECK-NEXT:    br %r14
+  %res = call float @llvm.copysign.f32(float %a, float %b)
+  ret float %res
+}
+
+; Test copysign with an f32 result and f64 sign argument.
+define float @f6(float %a, double %b) {
+; CHECK-LABEL: f6:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cpsdr %f0, %f2, %f0
+; CHECK-NEXT:    br %r14
+  %bf = fptrunc double %b to float
+  %res = call float @llvm.copysign.f32(float %a, float %bf)
+  ret float %res
+}
+
+; Test copysign with an f32 result and f128 sign argument.
+define float @f7(float %a, fp128 %b) {
+; Z10-LABEL: f7:
+; Z10:       # %bb.0:
+; Z10-NEXT:    ld %f1, 0(%r2)
+; Z10-NEXT:    ld %f3, 8(%r2)
+; Z10-NEXT:    cpsdr %f0, %f1, %f0
+; Z10-NEXT:    br %r14
+;
+; Z16-LABEL: f7:
+; Z16:       # %bb.0:
+; Z16-NEXT:    vl %v1, 0(%r2), 3
+; Z16-NEXT:    cpsdr %f0, %f1, %f0
+; Z16-NEXT:    br %r14
+  %bf = fptrunc fp128 %b to float
+  %res = call float @llvm.copysign.f32(float %a, float %bf)
+  ret float %res
+}
+
+; Test copysign with an f64 result and f16 sign argument.
+define double @f8(double %a, half %b) {
+; CHECK-LABEL: f8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cpsdr %f0, %f2, %f0
 ; CHECK-NEXT:    br %r14
   %bd = fpext half %b to double
   %res = call double @llvm.copysign.f64(double %a, double %bd)
   ret double %res
 }
 
-; Test copysign with an f128 result and half sign argument.
-define fp128 @f6(fp128 %a, half %b) {
-; Z10-LABEL: f6:
+; Test copysign with an f64 result and f32 sign argument.
+define double @f9(double %a, float %b) {
+; CHECK-LABEL: f9:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cpsdr %f0, %f2, %f0
+; CHECK-NEXT:    br %r14
+  %bd = fpext float %b to double
+  %res = call double @llvm.copysign.f64(double %a, double %bd)
+  ret double %res
+}
+
+; Test copysign with an f64 result and f64 sign argument.
+define double @f10(double %a, double %b) {
+; CHECK-LABEL: f10:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cpsdr %f0, %f2, %f0
+; CHECK-NEXT:    br %r14
+  %res = call double @llvm.copysign.f64(double %a, double %b)
+  ret double %res
+}
+
+; Test copysign with an f64 result and f128 sign argument.
+define double @f11(double %a, fp128 %b) {
+; Z10-LABEL: f11:
+; Z10:       # %bb.0:
+; Z10-NEXT:    ld %f1, 0(%r2)
+; Z10-NEXT:    ld %f3, 8(%r2)
+; Z10-NEXT:    cpsdr %f0, %f1, %f0
+; Z10-NEXT:    br %r14
+;
+; Z16-LABEL: f11:
+; Z16:       # %bb.0:
+; Z16-NEXT:    vl %v1, 0(%r2), 3
+; Z16-NEXT:    cpsdr %f0, %f1, %f0
+; Z16-NEXT:    br %r14
+  %bd = fptrunc fp128 %b to double
+  %res = call double @llvm.copysign.f64(double %a, double %bd)
+  ret double %res
+}
+
+; Test copysign with an f128 result and f16 sign argument.
+define fp128 @f12(fp128 %a, half %b) {
+; Z10-LABEL: f12:
 ; Z10:       # %bb.0:
 ; Z10-NEXT:    ld %f1, 0(%r3)
 ; Z10-NEXT:    ld %f3, 8(%r3)
@@ -122,24 +174,117 @@ define fp128 @f6(fp128 %a, half %b) {
 ; Z10-NEXT:    std %f3, 8(%r2)
 ; Z10-NEXT:    br %r14
 ;
-; Z16-LABEL: f6:
+; Z16-LABEL: f12:
 ; Z16:       # %bb.0:
 ; Z16-NEXT:    aghi %r15, -168
 ; Z16-NEXT:    .cfi_def_cfa_offset 328
 ; Z16-NEXT:    vl %v1, 0(%r3), 3
 ; Z16-NEXT:    vsteh %v0, 164(%r15), 0
 ; Z16-NEXT:    tm 164(%r15), 128
-; Z16-NEXT:    je .LBB6_2
+; Z16-NEXT:    je .LBB12_2
 ; Z16-NEXT:  # %bb.1:
 ; Z16-NEXT:    wflnxb %v0, %v1
-; Z16-NEXT:    j .LBB6_3
-; Z16-NEXT:  .LBB6_2:
+; Z16-NEXT:    j .LBB12_3
+; Z16-NEXT:  .LBB12_2:
 ; Z16-NEXT:    wflpxb %v0, %v1
-; Z16-NEXT:  .LBB6_3:
+; Z16-NEXT:  .LBB12_3:
 ; Z16-NEXT:    vst %v0, 0(%r2), 3
 ; Z16-NEXT:    aghi %r15, 168
 ; Z16-NEXT:    br %r14
-  %bd = fpext half %b to fp128
-  %res = call fp128 @llvm.copysign.f128(fp128 %a, fp128 %bd)
+  %b128 = fpext half %b to fp128
+  %res = call fp128 @llvm.copysign.f128(fp128 %a, fp128 %b128)
+  ret fp128 %res
+}
+
+; Test copysign with an f128 result and f32 sign argument.
+define fp128 @f13(fp128 %a, float %b) {
+; Z10-LABEL: f13:
+; Z10:       # %bb.0:
+; Z10-NEXT:    ld %f1, 0(%r3)
+; Z10-NEXT:    ld %f3, 8(%r3)
+; Z10-NEXT:    cpsdr %f1, %f0, %f1
+; Z10-NEXT:    std %f1, 0(%r2)
+; Z10-NEXT:    std %f3, 8(%r2)
+; Z10-NEXT:    br %r14
+;
+; Z16-LABEL: f13:
+; Z16:       # %bb.0:
+; Z16-NEXT:    vl %v1, 0(%r3), 3
+; Z16-NEXT:    vlgvf %r0, %v0, 0
+; Z16-NEXT:    tmlh %r0, 32768
+; Z16-NEXT:    je .LBB13_2
+; Z16-NEXT:  # %bb.1:
+; Z16-NEXT:    wflnxb %v0, %v1
+; Z16-NEXT:    vst %v0, 0(%r2), 3
+; Z16-NEXT:    br %r14
+; Z16-NEXT:  .LBB13_2:
+; Z16-NEXT:    wflpxb %v0, %v1
+; Z16-NEXT:    vst %v0, 0(%r2), 3
+; Z16-NEXT:    br %r14
+  %b128 = fpext float %b to fp128
+  %res = call fp128 @llvm.copysign.f128(fp128 %a, fp128 %b128)
+  ret fp128 %res
+}
+
+; Test copysign with an f128 result and f64 sign argument.
+define fp128 @f14(fp128 %a, double %b) {
+; Z10-LABEL: f14:
+; Z10:       # %bb.0:
+; Z10-NEXT:    ld %f1, 0(%r3)
+; Z10-NEXT:    ld %f3, 8(%r3)
+; Z10-NEXT:    cpsdr %f1, %f0, %f1
+; Z10-NEXT:    std %f1, 0(%r2)
+; Z10-NEXT:    std %f3, 8(%r2)
+; Z10-NEXT:    br %r14
+;
+; Z16-LABEL: f14:
+; Z16:       # %bb.0:
+; Z16-NEXT:    vl %v1, 0(%r3), 3
+; Z16-NEXT:    lgdr %r0, %f0
+; Z16-NEXT:    tmhh %r0, 32768
+; Z16-NEXT:    je .LBB14_2
+; Z16-NEXT:  # %bb.1:
+; Z16-NEXT:    wflnxb %v0, %v1
+; Z16-NEXT:    vst %v0, 0(%r2), 3
+; Z16-NEXT:    br %r14
+; Z16-NEXT:  .LBB14_2:
+; Z16-NEXT:    wflpxb %v0, %v1
+; Z16-NEXT:    vst %v0, 0(%r2), 3
+; Z16-NEXT:    br %r14
+  %b128 = fpext double %b to fp128
+  %res = call fp128 @llvm.copysign.f128(fp128 %a, fp128 %b128)
+  ret fp128 %res
+}
+
+; Test copysign with an f128 result and f128 sign argument.
+define fp128 @f15(fp128 %a, fp128 %b) {
+; Z10-LABEL: f15:
+; Z10:       # %bb.0:
+; Z10-NEXT:    ld %f0, 0(%r3)
+; Z10-NEXT:    ld %f2, 8(%r3)
+; Z10-NEXT:    ld %f1, 0(%r4)
+; Z10-NEXT:    ld %f3, 8(%r4)
+; Z10-NEXT:    cpsdr %f0, %f1, %f0
+; Z10-NEXT:    std %f0, 0(%r2)
+; Z10-NEXT:    std %f2, 8(%r2)
+; Z10-NEXT:    br %r14
+;
+; Z16-LABEL: f15:
+; Z16:       # %bb.0:
+; Z16-NEXT:    larl %r1, .LCPI15_0
+; Z16-NEXT:    vl %v1, 0(%r4), 3
+; Z16-NEXT:    vl %v2, 0(%r1), 3
+; Z16-NEXT:    vl %v0, 0(%r3), 3
+; Z16-NEXT:    vtm %v1, %v2
+; Z16-NEXT:    je .LBB15_2
+; Z16-NEXT:  # %bb.1:
+; Z16-NEXT:    wflnxb %v0, %v0
+; Z16-NEXT:    vst %v0, 0(%r2), 3
+; Z16-NEXT:    br %r14
+; Z16-NEXT:  .LBB15_2:
+; Z16-NEXT:    wflpxb %v0, %v0
+; Z16-NEXT:    vst %v0, 0(%r2), 3
+; Z16-NEXT:    br %r14
+  %res = call fp128 @llvm.copysign.f128(fp128 %a, fp128 %b)
   ret fp128 %res
 }
diff --git a/llvm/test/CodeGen/SystemZ/fp-mul-08.ll b/llvm/test/CodeGen/SystemZ/fp-mul-08.ll
index 2b18abec8d555..e739bddd4f18f 100644
--- a/llvm/test/CodeGen/SystemZ/fp-mul-08.ll
+++ b/llvm/test/CodeGen/SystemZ/fp-mul-08.ll
@@ -8,13 +8,12 @@ declare float @llvm.fma.f32(float %f1, float %f2, float %f3)
 
 define half @f0(half %f1, half %f2, half %acc) {
 ; CHECK-LABEL: f0:
-; CHECK: brasl %r14, __extendhfsf2@PLT
-; CHECK: lcdfr %f0, %f0
-; CHECK: brasl %r14, __truncsfhf2@PLT
+; CHECK-NOT: brasl
+; CHECK: lcdfr %f{{[0-9]+}}, %f4
 ; CHECK: brasl %r14, __extendhfsf2@PLT
 ; CHECK: brasl %r14, __extendhfsf2@PLT
 ; CHECK: brasl %r14, __extendhfsf2@PLT
-; CHECK-SCALAR: maebr %f0, %f9, %f8
+; CHECK-SCALAR: maebr %f0, %f8, %f10
 ; CHECK-VECTOR: wfmasb %f0, %f0, %f8, %f10
 ; CHECK: brasl %r14, __truncsfhf2@PLT
 ; CHECK: br %r14
diff --git a/llvm/test/CodeGen/SystemZ/fp-mul-10.ll b/llvm/test/CodeGen/SystemZ/fp-mul-10.ll
index 1ecf52fbde354..8f2cd23112cd0 100644
--- a/llvm/test/CodeGen/SystemZ/fp-mul-10.ll
+++ b/llvm/test/CodeGen/SystemZ/fp-mul-10.ll
@@ -30,10 +30,10 @@ define half @f3_half(half %f1, half %f2, half %acc) {
 ; CHECK: brasl %r14, __extendhfsf2@PLT
 ; CHECK: wfmasb %f0, %f0, %f8, %f10
 ; CHECK: brasl %r14, __truncsfhf2@PLT
-; CHECK: brasl %r14, __extendhfsf2@PLT
-; CHECK: lcdfr %f0, %f0
-; CHECK: brasl %r14, __truncsfhf2@PLT
-; CHECK: br %r14
+; CHECK-NOT: brasl
+; CHECK:      lcdfr %f0, %f0
+; CHECK-NEXT: lmg
+; CHECK-NEXT: br %r14
   %res = call half @llvm.fma.f16 (half %f1, half %f2, half %acc)
   %negres = fneg half %res
   ret half %negres
@@ -50,18 +50,17 @@ define float @f3(float %f1, float %f2, float %acc) {
 
 define half @f4_half(half %f1, half %f2, half %acc) {
 ; CHECK-LABEL: f4_half:
-; CHECK: brasl %r14, __extendhfsf2@PLT
-; CHECK: lcdfr %f0, %f0
-; CHECK: brasl %r14, __truncsfhf2@PLT
+; CHECK-NOT: brasl
+; CHECK: lcdfr %f0, %f4
 ; CHECK: brasl %r14, __extendhfsf2@PLT
 ; CHECK: brasl %r14, __extendhfsf2@PLT
 ; CHECK: brasl %r14, __extendhfsf2@PLT
 ; CHECK: wfmasb %f0, %f0, %f8, %f10
 ; CHECK: brasl %r14, __truncsfhf2@PLT
-; CHECK: brasl %r14, __extendhfsf2@PLT
-; CHECK: lcdfr %f0, %f0
-; CHECK: brasl %r14, __truncsfhf2@PLT
-; CHECK: br %r14
+; CHECK-NOT: brasl
+; CHECK:      lcdfr %f0, %f0
+; CHECK-NEXT: lmg
+; CHECK-NEXT: br %r14
   %negacc = fneg half %acc
   %res = call half @llvm.fma.f16 (half %f1, half %f2, half %negacc)
   %negres = fneg half %res
diff --git a/llvm/test/CodeGen/SystemZ/fp-neg-01.ll b/llvm/test/CodeGen/SystemZ/fp-neg-01.ll
index a8fe8d5da7c8a..0e19d9647178f 100644
--- a/llvm/test/CodeGen/SystemZ/fp-neg-01.ll
+++ b/llvm/test/CodeGen/SystemZ/fp-neg-01.ll
@@ -6,10 +6,9 @@
 ; Test f16.
 define half @f0(half %f) {
 ; CHECK-LABEL: f0:
-; CHECK: brasl %r14, __extendhfsf2@PLT
-; CHECK: lcdfr %f0, %f0
-; CHECK: brasl %r14, __truncsfhf2@PLT
-; CHECK: br %r14
+; CHECK:      # %bb.0:
+; CHECK-NEXT: lcdfr %f0, %f0
+; CHECK-NEXT: br %r14
   %res = fneg half %f
   ret half %res
 }
diff --git a/llvm/test/CodeGen/SystemZ/fp-neg-02.ll b/llvm/test/CodeGen/SystemZ/fp-neg-02.ll
index 848c4740d8540..d0802878f8f8b 100644
--- a/llvm/test/CodeGen/SystemZ/fp-neg-02.ll
+++ b/llvm/test/CodeGen/SystemZ/fp-neg-02.ll
@@ -5,10 +5,9 @@
 ; Test f16.
 define half @f0(half %f) {
 ; CHECK-LABEL: f0:
-; CHECK: brasl %r14, __extendhfsf2@PLT
-; CHECK: lcdfr %f0, %f0
-; CHECK: brasl %r14, __truncsfhf2@PLT
-; CHECK: br %r14
+; CHECK:      # %bb.0:
+; CHECK-NEXT: lcdfr %f0, %f0
+; CHECK-NEXT: br %r14
   %res = fneg half %f
   ret half %res
 }
diff --git a/llvm/test/CodeGen/Thumb2/mve-ctpop.ll b/llvm/test/CodeGen/Thumb2/mve-ctpop.ll
index 724bd4f7963b8..341163c6f9bd0 100644
--- a/llvm/test/CodeGen/Thumb2/mve-ctpop.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-ctpop.ll
@@ -1,5 +1,4 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; NOTE: Assertions have been autoenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
 
 define arm_aapcs_vfpcc <2 x i64> @ctpop_2i64_t(<2 x i64> %src){
diff --git a/llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll b/llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
index a84424bf7dea9..b3bf464b529d0 100644
--- a/llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
+++ b/llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
@@ -2283,8 +2283,8 @@ define <4 x i64> @test_masked_z_8xi64_to_4xi64_perm_mask7(<8 x i64> %vec, <4 x i
 define <2 x i64> @test_8xi64_to_2xi64_perm_mask0(<8 x i64> %vec) {
 ; CHECK-LABEL: test_8xi64_to_2xi64_perm_mask0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vpermpd {{.*#+}} zmm0 = zmm0[3,0,2,3,7,4,6,7]
-; CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 killed $zmm0
+; CHECK-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[3,0,2,3]
+; CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 killed $ymm0
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
   %res = shufflevector <8 x i64> %vec, <8 x i64> undef, <2 x i32> <i32 3, i32 0>
@@ -2293,9 +2293,9 @@ define <2 x i64> @test_8xi64_to_2xi64_perm_mask0(<8 x i64> %vec) {
 define <2 x i64> @test_masked_8xi64_to_2xi64_perm_mask0(<8 x i64> %vec, <2 x i64> %vec2, <2 x i64> %mask) {
 ; CHECK-LABEL: test_masked_8xi64_to_2xi64_perm_mask0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    # kill: def $xmm1 killed $xmm1 def $zmm1
+; CHECK-NEXT:    # kill: def $xmm1 killed $xmm1 def $ymm1
 ; CHECK-NEXT:    vptestnmq %xmm2, %xmm2, %k1
-; CHECK-NEXT:    vpermq {{.*#+}} zmm1 {%k1} = zmm0[3,0,2,3,7,4,6,7]
+; CHECK-NEXT:    vpermq {{.*#+}} ymm1 {%k1} = ymm0[3,0,2,3]
 ; CHECK-NEXT:    vmovdqa %xmm1, %xmm0
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
@@ -2308,8 +2308,8 @@ define <2 x i64> @test_masked_z_8xi64_to_2xi64_perm_mask0(<8 x i64> %vec, <2 x i
 ; CHECK-LABEL: test_masked_z_8xi64_to_2xi64_perm_mask0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vptestnmq %xmm1, %xmm1, %k1
-; CHECK-NEXT:    vpermq {{.*#+}} zmm0 {%k1} {z} = zmm0[3,0,2,3,7,4,6,7]
-; CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 killed $zmm0
+; CHECK-NEXT:    vpermq {{.*#+}} ymm0 {%k1} {z} = ymm0[3,0,2,3]
+; CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 killed $ymm0
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
   %shuf = shufflevector <8 x i64> %vec, <8 x i64> undef, <2 x i32> <i32 3, i32 0>
diff --git a/llvm/test/CodeGen/X86/build-vector-128.ll b/llvm/test/CodeGen/X86/build-vector-128.ll
index 30f55a1d41922..e2db8d4241420 100644
--- a/llvm/test/CodeGen/X86/build-vector-128.ll
+++ b/llvm/test/CodeGen/X86/build-vector-128.ll
@@ -410,6 +410,631 @@ define <16 x i8> @test_buildvector_v16i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4,
   ret <16 x i8> %ins15
 }
 
+; build vectors of repeated elements
+
+define <4 x float> @test_buildvector_4f32_2_var(float %a0, float %a1) {
+; SSE2-32-LABEL: test_buildvector_4f32_2_var:
+; SSE2-32:       # %bb.0:
+; SSE2-32-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2-32-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE2-32-NEXT:    unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; SSE2-32-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; SSE2-32-NEXT:    movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-32-NEXT:    retl
+;
+; SSE2-64-LABEL: test_buildvector_4f32_2_var:
+; SSE2-64:       # %bb.0:
+; SSE2-64-NEXT:    movaps %xmm1, %xmm2
+; SSE2-64-NEXT:    unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
+; SSE2-64-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-64-NEXT:    movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; SSE2-64-NEXT:    retq
+;
+; SSE41-32-LABEL: test_buildvector_4f32_2_var:
+; SSE41-32:       # %bb.0:
+; SSE41-32-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; SSE41-32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
+; SSE41-32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
+; SSE41-32-NEXT:    retl
+;
+; SSE41-64-LABEL: test_buildvector_4f32_2_var:
+; SSE41-64:       # %bb.0:
+; SSE41-64-NEXT:    movaps %xmm0, %xmm2
+; SSE41-64-NEXT:    insertps {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[2,3]
+; SSE41-64-NEXT:    insertps {{.*#+}} xmm2 = xmm2[0,1],xmm1[0],xmm2[3]
+; SSE41-64-NEXT:    insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm0[0]
+; SSE41-64-NEXT:    movaps %xmm2, %xmm0
+; SSE41-64-NEXT:    retq
+;
+; AVX-32-LABEL: test_buildvector_4f32_2_var:
+; AVX-32:       # %bb.0:
+; AVX-32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
+; AVX-32-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
+; AVX-32-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
+; AVX-32-NEXT:    retl
+;
+; AVX-64-LABEL: test_buildvector_4f32_2_var:
+; AVX-64:       # %bb.0:
+; AVX-64-NEXT:    vinsertps {{.*#+}} xmm2 = xmm0[0],xmm1[0],xmm0[2,3]
+; AVX-64-NEXT:    vinsertps {{.*#+}} xmm1 = xmm2[0,1],xmm1[0],xmm2[3]
+; AVX-64-NEXT:    vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
+; AVX-64-NEXT:    retq
+  %v0 = insertelement <4 x float> poison, float %a0, i32 0
+  %v1 = insertelement <4 x float> %v0, float %a1, i32 1
+  %v2 = insertelement <4 x float> %v1, float %a1, i32 2
+  %v3 = insertelement <4 x float> %v2, float %a0, i32 3
+  ret <4 x float> %v3
+}
+
+define <4 x float> @test_buildvector_4f32_2_load(ptr %p0, ptr %p1) {
+; SSE2-32-LABEL: test_buildvector_4f32_2_load:
+; SSE2-32:       # %bb.0:
+; SSE2-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SSE2-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; SSE2-32-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2-32-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE2-32-NEXT:    movaps %xmm1, %xmm2
+; SSE2-32-NEXT:    unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
+; SSE2-32-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-32-NEXT:    movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; SSE2-32-NEXT:    retl
+;
+; SSE2-64-LABEL: test_buildvector_4f32_2_load:
+; SSE2-64:       # %bb.0:
+; SSE2-64-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2-64-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE2-64-NEXT:    movaps %xmm1, %xmm2
+; SSE2-64-NEXT:    unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
+; SSE2-64-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-64-NEXT:    movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; SSE2-64-NEXT:    retq
+;
+; SSE41-32-LABEL: test_buildvector_4f32_2_load:
+; SSE41-32:       # %bb.0:
+; SSE41-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SSE41-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; SSE41-32-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE41-32-NEXT:    movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; SSE41-32-NEXT:    movaps %xmm2, %xmm0
+; SSE41-32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
+; SSE41-32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
+; SSE41-32-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm2[0]
+; SSE41-32-NEXT:    retl
+;
+; SSE41-64-LABEL: test_buildvector_4f32_2_load:
+; SSE41-64:       # %bb.0:
+; SSE41-64-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE41-64-NEXT:    movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; SSE41-64-NEXT:    movaps %xmm2, %xmm0
+; SSE41-64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
+; SSE41-64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
+; SSE41-64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm2[0]
+; SSE41-64-NEXT:    retq
+;
+; AVX-32-LABEL: test_buildvector_4f32_2_load:
+; AVX-32:       # %bb.0:
+; AVX-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; AVX-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; AVX-32-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; AVX-32-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; AVX-32-NEXT:    vinsertps {{.*#+}} xmm2 = xmm1[0],xmm0[0],xmm1[2,3]
+; AVX-32-NEXT:    vinsertps {{.*#+}} xmm0 = xmm2[0,1],xmm0[0],xmm2[3]
+; AVX-32-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
+; AVX-32-NEXT:    retl
+;
+; AVX-64-LABEL: test_buildvector_4f32_2_load:
+; AVX-64:       # %bb.0:
+; AVX-64-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; AVX-64-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; AVX-64-NEXT:    vinsertps {{.*#+}} xmm2 = xmm1[0],xmm0[0],xmm1[2,3]
+; AVX-64-NEXT:    vinsertps {{.*#+}} xmm0 = xmm2[0,1],xmm0[0],xmm2[3]
+; AVX-64-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
+; AVX-64-NEXT:    retq
+  %a0 = load float, ptr %p0
+  %a1 = load float, ptr %p1
+  %v0 = insertelement <4 x float> poison, float %a0, i32 0
+  %v1 = insertelement <4 x float> %v0, float %a1, i32 1
+  %v2 = insertelement <4 x float> %v1, float %a1, i32 2
+  %v3 = insertelement <4 x float> %v2, float %a0, i32 3
+  ret <4 x float> %v3
+}
+
+define <8 x i16> @test_buildvector_8i16_2_var(i16 %a0, i16 %a1) {
+; SSE2-32-LABEL: test_buildvector_8i16_2_var:
+; SSE2-32:       # %bb.0:
+; SSE2-32-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE2-32-NEXT:    movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2-32-NEXT:    pshuflw {{.*#+}} xmm2 = xmm0[0,0,0,0,4,5,6,7]
+; SSE2-32-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; SSE2-32-NEXT:    movdqa %xmm2, %xmm1
+; SSE2-32-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; SSE2-32-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSE2-32-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-32-NEXT:    retl
+;
+; SSE2-64-LABEL: test_buildvector_8i16_2_var:
+; SSE2-64:       # %bb.0:
+; SSE2-64-NEXT:    movd %esi, %xmm1
+; SSE2-64-NEXT:    movd %edi, %xmm0
+; SSE2-64-NEXT:    pshuflw {{.*#+}} xmm2 = xmm0[0,0,0,0,4,5,6,7]
+; SSE2-64-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; SSE2-64-NEXT:    movdqa %xmm2, %xmm1
+; SSE2-64-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; SSE2-64-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSE2-64-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-64-NEXT:    retq
+;
+; SSE41-32-LABEL: test_buildvector_8i16_2_var:
+; SSE41-32:       # %bb.0:
+; SSE41-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SSE41-32-NEXT:    movd %eax, %xmm0
+; SSE41-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; SSE41-32-NEXT:    pinsrw $1, %ecx, %xmm0
+; SSE41-32-NEXT:    pinsrw $2, %eax, %xmm0
+; SSE41-32-NEXT:    pinsrw $3, %eax, %xmm0
+; SSE41-32-NEXT:    pinsrw $4, %eax, %xmm0
+; SSE41-32-NEXT:    pinsrw $5, %eax, %xmm0
+; SSE41-32-NEXT:    pinsrw $6, %eax, %xmm0
+; SSE41-32-NEXT:    pinsrw $7, %ecx, %xmm0
+; SSE41-32-NEXT:    retl
+;
+; SSE41-64-LABEL: test_buildvector_8i16_2_var:
+; SSE41-64:       # %bb.0:
+; SSE41-64-NEXT:    movd %edi, %xmm0
+; SSE41-64-NEXT:    pinsrw $1, %esi, %xmm0
+; SSE41-64-NEXT:    pinsrw $2, %edi, %xmm0
+; SSE41-64-NEXT:    pinsrw $3, %edi, %xmm0
+; SSE41-64-NEXT:    pinsrw $4, %edi, %xmm0
+; SSE41-64-NEXT:    pinsrw $5, %edi, %xmm0
+; SSE41-64-NEXT:    pinsrw $6, %edi, %xmm0
+; SSE41-64-NEXT:    pinsrw $7, %esi, %xmm0
+; SSE41-64-NEXT:    retq
+;
+; AVX-32-LABEL: test_buildvector_8i16_2_var:
+; AVX-32:       # %bb.0:
+; AVX-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; AVX-32-NEXT:    vmovd %eax, %xmm0
+; AVX-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; AVX-32-NEXT:    vpinsrw $1, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrw $2, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrw $3, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrw $4, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrw $5, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrw $6, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrw $7, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT:    retl
+;
+; AVX-64-LABEL: test_buildvector_8i16_2_var:
+; AVX-64:       # %bb.0:
+; AVX-64-NEXT:    vmovd %edi, %xmm0
+; AVX-64-NEXT:    vpinsrw $1, %esi, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrw $2, %edi, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrw $3, %edi, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrw $4, %edi, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrw $5, %edi, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrw $6, %edi, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrw $7, %esi, %xmm0, %xmm0
+; AVX-64-NEXT:    retq
+  %v0 = insertelement <8 x i16> poison, i16 %a0, i32 0
+  %v1 = insertelement <8 x i16> %v0, i16 %a1, i32 1
+  %v2 = insertelement <8 x i16> %v1, i16 %a0, i32 2
+  %v3 = insertelement <8 x i16> %v2, i16 %a0, i32 3
+  %v4 = insertelement <8 x i16> %v3, i16 %a0, i32 4
+  %v5 = insertelement <8 x i16> %v4, i16 %a0, i32 5
+  %v6 = insertelement <8 x i16> %v5, i16 %a0, i32 6
+  %v7 = insertelement <8 x i16> %v6, i16 %a1, i32 7
+  ret <8 x i16> %v7
+}
+
+define <8 x i16> @test_buildvector_8i16_2_load(ptr %p0, ptr %p1) {
+; SSE2-32-LABEL: test_buildvector_8i16_2_load:
+; SSE2-32:       # %bb.0:
+; SSE2-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SSE2-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; SSE2-32-NEXT:    movzwl (%ecx), %ecx
+; SSE2-32-NEXT:    movd %ecx, %xmm1
+; SSE2-32-NEXT:    movzwl (%eax), %eax
+; SSE2-32-NEXT:    movd %eax, %xmm0
+; SSE2-32-NEXT:    pshuflw {{.*#+}} xmm2 = xmm0[0,0,0,0,4,5,6,7]
+; SSE2-32-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; SSE2-32-NEXT:    movdqa %xmm2, %xmm1
+; SSE2-32-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; SSE2-32-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSE2-32-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-32-NEXT:    retl
+;
+; SSE2-64-LABEL: test_buildvector_8i16_2_load:
+; SSE2-64:       # %bb.0:
+; SSE2-64-NEXT:    movzwl (%rsi), %eax
+; SSE2-64-NEXT:    movd %eax, %xmm1
+; SSE2-64-NEXT:    movzwl (%rdi), %eax
+; SSE2-64-NEXT:    movd %eax, %xmm0
+; SSE2-64-NEXT:    pshuflw {{.*#+}} xmm2 = xmm0[0,0,0,0,4,5,6,7]
+; SSE2-64-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; SSE2-64-NEXT:    movdqa %xmm2, %xmm1
+; SSE2-64-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; SSE2-64-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSE2-64-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-64-NEXT:    retq
+;
+; SSE41-32-LABEL: test_buildvector_8i16_2_load:
+; SSE41-32:       # %bb.0:
+; SSE41-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; SSE41-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SSE41-32-NEXT:    movzwl (%eax), %eax
+; SSE41-32-NEXT:    movzwl (%ecx), %ecx
+; SSE41-32-NEXT:    movd %ecx, %xmm0
+; SSE41-32-NEXT:    pinsrw $1, %eax, %xmm0
+; SSE41-32-NEXT:    pinsrw $2, %ecx, %xmm0
+; SSE41-32-NEXT:    pinsrw $3, %ecx, %xmm0
+; SSE41-32-NEXT:    pinsrw $4, %ecx, %xmm0
+; SSE41-32-NEXT:    pinsrw $5, %ecx, %xmm0
+; SSE41-32-NEXT:    pinsrw $6, %ecx, %xmm0
+; SSE41-32-NEXT:    pinsrw $7, %eax, %xmm0
+; SSE41-32-NEXT:    retl
+;
+; SSE41-64-LABEL: test_buildvector_8i16_2_load:
+; SSE41-64:       # %bb.0:
+; SSE41-64-NEXT:    movzwl (%rsi), %eax
+; SSE41-64-NEXT:    movzwl (%rdi), %ecx
+; SSE41-64-NEXT:    movd %ecx, %xmm0
+; SSE41-64-NEXT:    pinsrw $1, %eax, %xmm0
+; SSE41-64-NEXT:    pinsrw $2, %ecx, %xmm0
+; SSE41-64-NEXT:    pinsrw $3, %ecx, %xmm0
+; SSE41-64-NEXT:    pinsrw $4, %ecx, %xmm0
+; SSE41-64-NEXT:    pinsrw $5, %ecx, %xmm0
+; SSE41-64-NEXT:    pinsrw $6, %ecx, %xmm0
+; SSE41-64-NEXT:    pinsrw $7, %eax, %xmm0
+; SSE41-64-NEXT:    retq
+;
+; AVX-32-LABEL: test_buildvector_8i16_2_load:
+; AVX-32:       # %bb.0:
+; AVX-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; AVX-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; AVX-32-NEXT:    movzwl (%ecx), %ecx
+; AVX-32-NEXT:    movzwl (%eax), %eax
+; AVX-32-NEXT:    vmovd %eax, %xmm0
+; AVX-32-NEXT:    vpinsrw $1, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrw $2, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrw $3, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrw $4, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrw $5, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrw $6, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrw $7, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT:    retl
+;
+; AVX-64-LABEL: test_buildvector_8i16_2_load:
+; AVX-64:       # %bb.0:
+; AVX-64-NEXT:    movzwl (%rsi), %eax
+; AVX-64-NEXT:    movzwl (%rdi), %ecx
+; AVX-64-NEXT:    vmovd %ecx, %xmm0
+; AVX-64-NEXT:    vpinsrw $1, %eax, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrw $2, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrw $3, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrw $4, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrw $5, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrw $6, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrw $7, %eax, %xmm0, %xmm0
+; AVX-64-NEXT:    retq
+  %a0 = load i16, ptr %p0
+  %a1 = load i16, ptr %p1
+  %v0 = insertelement <8 x i16> poison, i16 %a0, i32 0
+  %v1 = insertelement <8 x i16> %v0, i16 %a1, i32 1
+  %v2 = insertelement <8 x i16> %v1, i16 %a0, i32 2
+  %v3 = insertelement <8 x i16> %v2, i16 %a0, i32 3
+  %v4 = insertelement <8 x i16> %v3, i16 %a0, i32 4
+  %v5 = insertelement <8 x i16> %v4, i16 %a0, i32 5
+  %v6 = insertelement <8 x i16> %v5, i16 %a0, i32 6
+  %v7 = insertelement <8 x i16> %v6, i16 %a1, i32 7
+  ret <8 x i16> %v7
+}
+
+define <16 x i8> @test_buildvector_16i8_2_var(i8 %a0, i8 %a1) {
+; SSE2-32-LABEL: test_buildvector_16i8_2_var:
+; SSE2-32:       # %bb.0:
+; SSE2-32-NEXT:    movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2-32-NEXT:    movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; SSE2-32-NEXT:    movdqa %xmm2, %xmm1
+; SSE2-32-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
+; SSE2-32-NEXT:    movdqa %xmm0, %xmm3
+; SSE2-32-NEXT:    punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]
+; SSE2-32-NEXT:    movdqa %xmm1, %xmm4
+; SSE2-32-NEXT:    punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3]
+; SSE2-32-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; SSE2-32-NEXT:    punpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; SSE2-32-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
+; SSE2-32-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1]
+; SSE2-32-NEXT:    movdqa %xmm3, %xmm2
+; SSE2-32-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
+; SSE2-32-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]
+; SSE2-32-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSE2-32-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-32-NEXT:    retl
+;
+; SSE2-64-LABEL: test_buildvector_16i8_2_var:
+; SSE2-64:       # %bb.0:
+; SSE2-64-NEXT:    movd %edi, %xmm0
+; SSE2-64-NEXT:    movd %esi, %xmm1
+; SSE2-64-NEXT:    movdqa %xmm1, %xmm2
+; SSE2-64-NEXT:    punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
+; SSE2-64-NEXT:    movdqa %xmm0, %xmm3
+; SSE2-64-NEXT:    punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]
+; SSE2-64-NEXT:    movdqa %xmm2, %xmm4
+; SSE2-64-NEXT:    punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3]
+; SSE2-64-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; SSE2-64-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; SSE2-64-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]
+; SSE2-64-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
+; SSE2-64-NEXT:    movdqa %xmm3, %xmm1
+; SSE2-64-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
+; SSE2-64-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]
+; SSE2-64-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-64-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; SSE2-64-NEXT:    retq
+;
+; SSE41-32-LABEL: test_buildvector_16i8_2_var:
+; SSE41-32:       # %bb.0:
+; SSE41-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SSE41-32-NEXT:    movd %eax, %xmm0
+; SSE41-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; SSE41-32-NEXT:    pinsrb $1, %ecx, %xmm0
+; SSE41-32-NEXT:    pinsrb $2, %eax, %xmm0
+; SSE41-32-NEXT:    pinsrb $3, %eax, %xmm0
+; SSE41-32-NEXT:    pinsrb $4, %eax, %xmm0
+; SSE41-32-NEXT:    pinsrb $5, %eax, %xmm0
+; SSE41-32-NEXT:    pinsrb $6, %eax, %xmm0
+; SSE41-32-NEXT:    pinsrb $7, %ecx, %xmm0
+; SSE41-32-NEXT:    pinsrb $8, %ecx, %xmm0
+; SSE41-32-NEXT:    pinsrb $9, %eax, %xmm0
+; SSE41-32-NEXT:    pinsrb $10, %ecx, %xmm0
+; SSE41-32-NEXT:    pinsrb $11, %ecx, %xmm0
+; SSE41-32-NEXT:    pinsrb $12, %ecx, %xmm0
+; SSE41-32-NEXT:    pinsrb $13, %eax, %xmm0
+; SSE41-32-NEXT:    pinsrb $14, %eax, %xmm0
+; SSE41-32-NEXT:    pinsrb $15, %eax, %xmm0
+; SSE41-32-NEXT:    retl
+;
+; SSE41-64-LABEL: test_buildvector_16i8_2_var:
+; SSE41-64:       # %bb.0:
+; SSE41-64-NEXT:    movd %edi, %xmm0
+; SSE41-64-NEXT:    pinsrb $1, %esi, %xmm0
+; SSE41-64-NEXT:    pinsrb $2, %edi, %xmm0
+; SSE41-64-NEXT:    pinsrb $3, %edi, %xmm0
+; SSE41-64-NEXT:    pinsrb $4, %edi, %xmm0
+; SSE41-64-NEXT:    pinsrb $5, %edi, %xmm0
+; SSE41-64-NEXT:    pinsrb $6, %edi, %xmm0
+; SSE41-64-NEXT:    pinsrb $7, %esi, %xmm0
+; SSE41-64-NEXT:    pinsrb $8, %esi, %xmm0
+; SSE41-64-NEXT:    pinsrb $9, %edi, %xmm0
+; SSE41-64-NEXT:    pinsrb $10, %esi, %xmm0
+; SSE41-64-NEXT:    pinsrb $11, %esi, %xmm0
+; SSE41-64-NEXT:    pinsrb $12, %esi, %xmm0
+; SSE41-64-NEXT:    pinsrb $13, %edi, %xmm0
+; SSE41-64-NEXT:    pinsrb $14, %edi, %xmm0
+; SSE41-64-NEXT:    pinsrb $15, %edi, %xmm0
+; SSE41-64-NEXT:    retq
+;
+; AVX-32-LABEL: test_buildvector_16i8_2_var:
+; AVX-32:       # %bb.0:
+; AVX-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; AVX-32-NEXT:    vmovd %eax, %xmm0
+; AVX-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; AVX-32-NEXT:    vpinsrb $1, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $2, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $3, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $4, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $5, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $6, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $7, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $8, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $9, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $10, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $11, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $12, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $13, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $14, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $15, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    retl
+;
+; AVX-64-LABEL: test_buildvector_16i8_2_var:
+; AVX-64:       # %bb.0:
+; AVX-64-NEXT:    vmovd %edi, %xmm0
+; AVX-64-NEXT:    vpinsrb $1, %esi, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $2, %edi, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $3, %edi, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $4, %edi, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $5, %edi, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $6, %edi, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $7, %esi, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $8, %esi, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $9, %edi, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $10, %esi, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $11, %esi, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $12, %esi, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $13, %edi, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $14, %edi, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $15, %edi, %xmm0, %xmm0
+; AVX-64-NEXT:    retq
+  %v0 = insertelement <16 x i8> poison, i8 %a0, i8 0
+  %v1 = insertelement <16 x i8> %v0, i8 %a1, i8 1
+  %v2 = insertelement <16 x i8> %v1, i8 %a0, i8 2
+  %v3 = insertelement <16 x i8> %v2, i8 %a0, i8 3
+  %v4 = insertelement <16 x i8> %v3, i8 %a0, i8 4
+  %v5 = insertelement <16 x i8> %v4, i8 %a0, i8 5
+  %v6 = insertelement <16 x i8> %v5, i8 %a0, i8 6
+  %v7 = insertelement <16 x i8> %v6, i8 %a1, i8 7
+  %v8 = insertelement <16 x i8> %v7, i8 %a1, i8 8
+  %v9 = insertelement <16 x i8> %v8, i8 %a0, i8 9
+  %v10 = insertelement <16 x i8> %v9, i8 %a1, i8 10
+  %v11 = insertelement <16 x i8> %v10, i8 %a1, i8 11
+  %v12 = insertelement <16 x i8> %v11, i8 %a1, i8 12
+  %v13 = insertelement <16 x i8> %v12, i8 %a0, i8 13
+  %v14 = insertelement <16 x i8> %v13, i8 %a0, i8 14
+  %v15 = insertelement <16 x i8> %v14, i8 %a0, i8 15
+  ret <16 x i8> %v15
+}
+
+define <16 x i8> @test_buildvector_16i8_2_load(ptr %p0, ptr %p1) {
+; SSE2-32-LABEL: test_buildvector_16i8_2_load:
+; SSE2-32:       # %bb.0:
+; SSE2-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SSE2-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; SSE2-32-NEXT:    movzbl (%ecx), %ecx
+; SSE2-32-NEXT:    movd %ecx, %xmm0
+; SSE2-32-NEXT:    movzbl (%eax), %eax
+; SSE2-32-NEXT:    movd %eax, %xmm2
+; SSE2-32-NEXT:    movdqa %xmm2, %xmm1
+; SSE2-32-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
+; SSE2-32-NEXT:    movdqa %xmm0, %xmm3
+; SSE2-32-NEXT:    punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]
+; SSE2-32-NEXT:    movdqa %xmm1, %xmm4
+; SSE2-32-NEXT:    punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3]
+; SSE2-32-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; SSE2-32-NEXT:    punpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; SSE2-32-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
+; SSE2-32-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1]
+; SSE2-32-NEXT:    movdqa %xmm3, %xmm2
+; SSE2-32-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
+; SSE2-32-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]
+; SSE2-32-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSE2-32-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-32-NEXT:    retl
+;
+; SSE2-64-LABEL: test_buildvector_16i8_2_load:
+; SSE2-64:       # %bb.0:
+; SSE2-64-NEXT:    movzbl (%rdi), %eax
+; SSE2-64-NEXT:    movd %eax, %xmm0
+; SSE2-64-NEXT:    movzbl (%rsi), %eax
+; SSE2-64-NEXT:    movd %eax, %xmm1
+; SSE2-64-NEXT:    movdqa %xmm1, %xmm2
+; SSE2-64-NEXT:    punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
+; SSE2-64-NEXT:    movdqa %xmm0, %xmm3
+; SSE2-64-NEXT:    punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]
+; SSE2-64-NEXT:    movdqa %xmm2, %xmm4
+; SSE2-64-NEXT:    punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3]
+; SSE2-64-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; SSE2-64-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; SSE2-64-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]
+; SSE2-64-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
+; SSE2-64-NEXT:    movdqa %xmm3, %xmm1
+; SSE2-64-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
+; SSE2-64-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]
+; SSE2-64-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-64-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; SSE2-64-NEXT:    retq
+;
+; SSE41-32-LABEL: test_buildvector_16i8_2_load:
+; SSE41-32:       # %bb.0:
+; SSE41-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SSE41-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; SSE41-32-NEXT:    movzbl (%ecx), %ecx
+; SSE41-32-NEXT:    movzbl (%eax), %eax
+; SSE41-32-NEXT:    movd %eax, %xmm0
+; SSE41-32-NEXT:    pinsrb $1, %ecx, %xmm0
+; SSE41-32-NEXT:    pinsrb $2, %eax, %xmm0
+; SSE41-32-NEXT:    pinsrb $3, %eax, %xmm0
+; SSE41-32-NEXT:    pinsrb $4, %eax, %xmm0
+; SSE41-32-NEXT:    pinsrb $5, %eax, %xmm0
+; SSE41-32-NEXT:    pinsrb $6, %eax, %xmm0
+; SSE41-32-NEXT:    pinsrb $7, %ecx, %xmm0
+; SSE41-32-NEXT:    pinsrb $8, %ecx, %xmm0
+; SSE41-32-NEXT:    pinsrb $9, %eax, %xmm0
+; SSE41-32-NEXT:    pinsrb $10, %ecx, %xmm0
+; SSE41-32-NEXT:    pinsrb $11, %ecx, %xmm0
+; SSE41-32-NEXT:    pinsrb $12, %ecx, %xmm0
+; SSE41-32-NEXT:    pinsrb $13, %eax, %xmm0
+; SSE41-32-NEXT:    pinsrb $14, %eax, %xmm0
+; SSE41-32-NEXT:    pinsrb $15, %eax, %xmm0
+; SSE41-32-NEXT:    retl
+;
+; SSE41-64-LABEL: test_buildvector_16i8_2_load:
+; SSE41-64:       # %bb.0:
+; SSE41-64-NEXT:    movzbl (%rsi), %ecx
+; SSE41-64-NEXT:    movzbl (%rdi), %eax
+; SSE41-64-NEXT:    movd %eax, %xmm0
+; SSE41-64-NEXT:    pinsrb $1, %ecx, %xmm0
+; SSE41-64-NEXT:    pinsrb $2, %eax, %xmm0
+; SSE41-64-NEXT:    pinsrb $3, %eax, %xmm0
+; SSE41-64-NEXT:    pinsrb $4, %eax, %xmm0
+; SSE41-64-NEXT:    pinsrb $5, %eax, %xmm0
+; SSE41-64-NEXT:    pinsrb $6, %eax, %xmm0
+; SSE41-64-NEXT:    pinsrb $7, %ecx, %xmm0
+; SSE41-64-NEXT:    pinsrb $8, %ecx, %xmm0
+; SSE41-64-NEXT:    pinsrb $9, %eax, %xmm0
+; SSE41-64-NEXT:    pinsrb $10, %ecx, %xmm0
+; SSE41-64-NEXT:    pinsrb $11, %ecx, %xmm0
+; SSE41-64-NEXT:    pinsrb $12, %ecx, %xmm0
+; SSE41-64-NEXT:    pinsrb $13, %eax, %xmm0
+; SSE41-64-NEXT:    pinsrb $14, %eax, %xmm0
+; SSE41-64-NEXT:    pinsrb $15, %eax, %xmm0
+; SSE41-64-NEXT:    retq
+;
+; AVX-32-LABEL: test_buildvector_16i8_2_load:
+; AVX-32:       # %bb.0:
+; AVX-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; AVX-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; AVX-32-NEXT:    movzbl (%ecx), %ecx
+; AVX-32-NEXT:    movzbl (%eax), %eax
+; AVX-32-NEXT:    vmovd %eax, %xmm0
+; AVX-32-NEXT:    vpinsrb $1, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $2, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $3, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $4, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $5, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $6, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $7, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $8, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $9, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $10, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $11, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $12, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $13, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $14, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    vpinsrb $15, %eax, %xmm0, %xmm0
+; AVX-32-NEXT:    retl
+;
+; AVX-64-LABEL: test_buildvector_16i8_2_load:
+; AVX-64:       # %bb.0:
+; AVX-64-NEXT:    movzbl (%rsi), %eax
+; AVX-64-NEXT:    movzbl (%rdi), %ecx
+; AVX-64-NEXT:    vmovd %ecx, %xmm0
+; AVX-64-NEXT:    vpinsrb $1, %eax, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $2, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $3, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $4, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $5, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $6, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $7, %eax, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $8, %eax, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $9, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $10, %eax, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $11, %eax, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $12, %eax, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $13, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $14, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT:    vpinsrb $15, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT:    retq
+  %a0 = load i8, ptr %p0
+  %a1 = load i8, ptr %p1
+  %v0 = insertelement <16 x i8> poison, i8 %a0, i8 0
+  %v1 = insertelement <16 x i8> %v0, i8 %a1, i8 1
+  %v2 = insertelement <16 x i8> %v1, i8 %a0, i8 2
+  %v3 = insertelement <16 x i8> %v2, i8 %a0, i8 3
+  %v4 = insertelement <16 x i8> %v3, i8 %a0, i8 4
+  %v5 = insertelement <16 x i8> %v4, i8 %a0, i8 5
+  %v6 = insertelement <16 x i8> %v5, i8 %a0, i8 6
+  %v7 = insertelement <16 x i8> %v6, i8 %a1, i8 7
+  %v8 = insertelement <16 x i8> %v7, i8 %a1, i8 8
+  %v9 = insertelement <16 x i8> %v8, i8 %a0, i8 9
+  %v10 = insertelement <16 x i8> %v9, i8 %a1, i8 10
+  %v11 = insertelement <16 x i8> %v10, i8 %a1, i8 11
+  %v12 = insertelement <16 x i8> %v11, i8 %a1, i8 12
+  %v13 = insertelement <16 x i8> %v12, i8 %a0, i8 13
+  %v14 = insertelement <16 x i8> %v13, i8 %a0, i8 14
+  %v15 = insertelement <16 x i8> %v14, i8 %a0, i8 15
+  ret <16 x i8> %v15
+}
+
 ; PR30780
 
 define <4 x i32> @test_buildvector_v4i32_splat_sext_i8(i8 %in) {
diff --git a/llvm/test/CodeGen/X86/build-vector-256.ll b/llvm/test/CodeGen/X86/build-vector-256.ll
index d2d7a194c7012..6c1cbfb4014b6 100644
--- a/llvm/test/CodeGen/X86/build-vector-256.ll
+++ b/llvm/test/CodeGen/X86/build-vector-256.ll
@@ -412,6 +412,353 @@ define <32 x i8> @test_buildvector_v32i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4,
   ret <32 x i8> %ins31
 }
 
+; build vectors of repeated elements
+
+define <4 x double> @test_buildvector_4f64_2_var(double %a0, double %a1) {
+; AVX-32-LABEL: test_buildvector_4f64_2_var:
+; AVX-32:       # %bb.0:
+; AVX-32-NEXT:    vmovups {{[0-9]+}}(%esp), %xmm0
+; AVX-32-NEXT:    vmovsd {{.*#+}} xmm1 = mem[0],zero
+; AVX-32-NEXT:    vmovhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1]
+; AVX-32-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX-32-NEXT:    retl
+;
+; AVX-64-LABEL: test_buildvector_4f64_2_var:
+; AVX-64:       # %bb.0:
+; AVX-64-NEXT:    vmovlhps {{.*#+}} xmm2 = xmm1[0],xmm0[0]
+; AVX-64-NEXT:    vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX-64-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX-64-NEXT:    retq
+  %v0 = insertelement <4 x double> poison, double %a0, i32 0
+  %v1 = insertelement <4 x double> %v0, double %a1, i32 1
+  %v2 = insertelement <4 x double> %v1, double %a1, i32 2
+  %v3 = insertelement <4 x double> %v2, double %a0, i32 3
+  ret <4 x double> %v3
+}
+
+define <4 x double> @test_buildvector_4f64_2_load(ptr %p0, ptr %p1) {
+; AVX-32-LABEL: test_buildvector_4f64_2_load:
+; AVX-32:       # %bb.0:
+; AVX-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; AVX-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; AVX-32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
+; AVX-32-NEXT:    vmovsd {{.*#+}} xmm1 = mem[0],zero
+; AVX-32-NEXT:    vmovlhps {{.*#+}} xmm2 = xmm1[0],xmm0[0]
+; AVX-32-NEXT:    vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX-32-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX-32-NEXT:    retl
+;
+; AVX-64-LABEL: test_buildvector_4f64_2_load:
+; AVX-64:       # %bb.0:
+; AVX-64-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
+; AVX-64-NEXT:    vmovsd {{.*#+}} xmm1 = mem[0],zero
+; AVX-64-NEXT:    vmovlhps {{.*#+}} xmm2 = xmm1[0],xmm0[0]
+; AVX-64-NEXT:    vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX-64-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX-64-NEXT:    retq
+  %a0 = load double, ptr %p0
+  %a1 = load double, ptr %p1
+  %v0 = insertelement <4 x double> poison, double %a0, i32 0
+  %v1 = insertelement <4 x double> %v0, double %a1, i32 1
+  %v2 = insertelement <4 x double> %v1, double %a1, i32 2
+  %v3 = insertelement <4 x double> %v2, double %a0, i32 3
+  ret <4 x double> %v3
+}
+
+define <8 x float> @test_buildvector_8f32_2_var(float %a0, float %a1) {
+; AVX-32-LABEL: test_buildvector_8f32_2_var:
+; AVX-32:       # %bb.0:
+; AVX-32-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; AVX-32-NEXT:    vbroadcastss {{[0-9]+}}(%esp), %xmm1
+; AVX-32-NEXT:    vinsertps {{.*#+}} xmm2 = xmm1[0,1,2],xmm0[0]
+; AVX-32-NEXT:    vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3]
+; AVX-32-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX-32-NEXT:    retl
+;
+; AVX1-64-LABEL: test_buildvector_8f32_2_var:
+; AVX1-64:       # %bb.0:
+; AVX1-64-NEXT:    vshufps {{.*#+}} xmm2 = xmm0[0,0,0,3]
+; AVX1-64-NEXT:    vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm1[0]
+; AVX1-64-NEXT:    vinsertps {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[2,3]
+; AVX1-64-NEXT:    vshufps {{.*#+}} xmm0 = xmm1[0,1],xmm0[0,0]
+; AVX1-64-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-64-NEXT:    retq
+;
+; AVX2-64-LABEL: test_buildvector_8f32_2_var:
+; AVX2-64:       # %bb.0:
+; AVX2-64-NEXT:    vbroadcastss %xmm0, %xmm0
+; AVX2-64-NEXT:    vinsertps {{.*#+}} xmm2 = xmm0[0,1,2],xmm1[0]
+; AVX2-64-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
+; AVX2-64-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX2-64-NEXT:    retq
+  %v0 = insertelement <8 x float> poison, float %a0, i32 0
+  %v1 = insertelement <8 x float> %v0, float %a1, i32 1
+  %v2 = insertelement <8 x float> %v1, float %a0, i32 2
+  %v3 = insertelement <8 x float> %v2, float %a0, i32 3
+  %v4 = insertelement <8 x float> %v3, float %a0, i32 4
+  %v5 = insertelement <8 x float> %v4, float %a0, i32 5
+  %v6 = insertelement <8 x float> %v5, float %a0, i32 6
+  %v7 = insertelement <8 x float> %v6, float %a1, i32 7
+  ret <8 x float> %v7
+}
+
+define <8 x float> @test_buildvector_8f32_2_load(ptr %p0, ptr %p1) {
+; AVX-32-LABEL: test_buildvector_8f32_2_load:
+; AVX-32:       # %bb.0:
+; AVX-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; AVX-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; AVX-32-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; AVX-32-NEXT:    vbroadcastss (%eax), %xmm1
+; AVX-32-NEXT:    vinsertps {{.*#+}} xmm2 = xmm1[0,1,2],xmm0[0]
+; AVX-32-NEXT:    vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3]
+; AVX-32-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX-32-NEXT:    retl
+;
+; AVX-64-LABEL: test_buildvector_8f32_2_load:
+; AVX-64:       # %bb.0:
+; AVX-64-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; AVX-64-NEXT:    vbroadcastss (%rdi), %xmm1
+; AVX-64-NEXT:    vinsertps {{.*#+}} xmm2 = xmm1[0,1,2],xmm0[0]
+; AVX-64-NEXT:    vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3]
+; AVX-64-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX-64-NEXT:    retq
+  %a0 = load float, ptr %p0
+  %a1 = load float, ptr %p1
+  %v0 = insertelement <8 x float> poison, float %a0, i32 0
+  %v1 = insertelement <8 x float> %v0, float %a1, i32 1
+  %v2 = insertelement <8 x float> %v1, float %a0, i32 2
+  %v3 = insertelement <8 x float> %v2, float %a0, i32 3
+  %v4 = insertelement <8 x float> %v3, float %a0, i32 4
+  %v5 = insertelement <8 x float> %v4, float %a0, i32 5
+  %v6 = insertelement <8 x float> %v5, float %a0, i32 6
+  %v7 = insertelement <8 x float> %v6, float %a1, i32 7
+  ret <8 x float> %v7
+}
+
+define <16 x i16> @test_buildvector_16i16_2_var(i16 %a0, i16 %a1) {
+; AVX1-32-LABEL: test_buildvector_16i16_2_var:
+; AVX1-32:       # %bb.0:
+; AVX1-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; AVX1-32-NEXT:    vmovd %eax, %xmm0
+; AVX1-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; AVX1-32-NEXT:    vpinsrw $1, %ecx, %xmm0, %xmm0
+; AVX1-32-NEXT:    vpinsrw $2, %eax, %xmm0, %xmm0
+; AVX1-32-NEXT:    vpinsrw $3, %eax, %xmm0, %xmm0
+; AVX1-32-NEXT:    vpinsrw $4, %eax, %xmm0, %xmm0
+; AVX1-32-NEXT:    vpinsrw $5, %ecx, %xmm0, %xmm0
+; AVX1-32-NEXT:    vpinsrw $6, %ecx, %xmm0, %xmm0
+; AVX1-32-NEXT:    vpinsrw $7, %ecx, %xmm0, %xmm0
+; AVX1-32-NEXT:    vmovd %ecx, %xmm1
+; AVX1-32-NEXT:    vpinsrw $1, %eax, %xmm1, %xmm1
+; AVX1-32-NEXT:    vpinsrw $2, %ecx, %xmm1, %xmm1
+; AVX1-32-NEXT:    vpinsrw $3, %ecx, %xmm1, %xmm1
+; AVX1-32-NEXT:    vpinsrw $4, %ecx, %xmm1, %xmm1
+; AVX1-32-NEXT:    vpinsrw $5, %ecx, %xmm1, %xmm1
+; AVX1-32-NEXT:    vpinsrw $6, %ecx, %xmm1, %xmm1
+; AVX1-32-NEXT:    vpinsrw $7, %eax, %xmm1, %xmm1
+; AVX1-32-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-32-NEXT:    retl
+;
+; AVX1-64-LABEL: test_buildvector_16i16_2_var:
+; AVX1-64:       # %bb.0:
+; AVX1-64-NEXT:    vmovd %esi, %xmm0
+; AVX1-64-NEXT:    vpinsrw $1, %edi, %xmm0, %xmm0
+; AVX1-64-NEXT:    vpinsrw $2, %esi, %xmm0, %xmm0
+; AVX1-64-NEXT:    vpinsrw $3, %esi, %xmm0, %xmm0
+; AVX1-64-NEXT:    vpinsrw $4, %esi, %xmm0, %xmm0
+; AVX1-64-NEXT:    vpinsrw $5, %edi, %xmm0, %xmm0
+; AVX1-64-NEXT:    vpinsrw $6, %edi, %xmm0, %xmm0
+; AVX1-64-NEXT:    vpinsrw $7, %edi, %xmm0, %xmm0
+; AVX1-64-NEXT:    vmovd %edi, %xmm1
+; AVX1-64-NEXT:    vpinsrw $1, %esi, %xmm1, %xmm1
+; AVX1-64-NEXT:    vpinsrw $2, %edi, %xmm1, %xmm1
+; AVX1-64-NEXT:    vpinsrw $3, %edi, %xmm1, %xmm1
+; AVX1-64-NEXT:    vpinsrw $4, %edi, %xmm1, %xmm1
+; AVX1-64-NEXT:    vpinsrw $5, %edi, %xmm1, %xmm1
+; AVX1-64-NEXT:    vpinsrw $6, %edi, %xmm1, %xmm1
+; AVX1-64-NEXT:    vpinsrw $7, %esi, %xmm1, %xmm1
+; AVX1-64-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-64-NEXT:    retq
+;
+; AVX2-32-LABEL: test_buildvector_16i16_2_var:
+; AVX2-32:       # %bb.0:
+; AVX2-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; AVX2-32-NEXT:    vmovd %eax, %xmm0
+; AVX2-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; AVX2-32-NEXT:    vpinsrw $1, %ecx, %xmm0, %xmm0
+; AVX2-32-NEXT:    vpinsrw $2, %eax, %xmm0, %xmm0
+; AVX2-32-NEXT:    vpinsrw $3, %eax, %xmm0, %xmm0
+; AVX2-32-NEXT:    vpinsrw $4, %eax, %xmm0, %xmm0
+; AVX2-32-NEXT:    vpinsrw $5, %ecx, %xmm0, %xmm0
+; AVX2-32-NEXT:    vpinsrw $6, %ecx, %xmm0, %xmm0
+; AVX2-32-NEXT:    vpinsrw $7, %ecx, %xmm0, %xmm0
+; AVX2-32-NEXT:    vmovd %ecx, %xmm1
+; AVX2-32-NEXT:    vpinsrw $1, %eax, %xmm1, %xmm1
+; AVX2-32-NEXT:    vpinsrw $2, %ecx, %xmm1, %xmm1
+; AVX2-32-NEXT:    vpinsrw $3, %ecx, %xmm1, %xmm1
+; AVX2-32-NEXT:    vpinsrw $4, %ecx, %xmm1, %xmm1
+; AVX2-32-NEXT:    vpinsrw $5, %ecx, %xmm1, %xmm1
+; AVX2-32-NEXT:    vpinsrw $6, %ecx, %xmm1, %xmm1
+; AVX2-32-NEXT:    vpinsrw $7, %eax, %xmm1, %xmm1
+; AVX2-32-NEXT:    vinserti128 $1, %xmm0, %ymm1, %ymm0
+; AVX2-32-NEXT:    retl
+;
+; AVX2-64-LABEL: test_buildvector_16i16_2_var:
+; AVX2-64:       # %bb.0:
+; AVX2-64-NEXT:    vmovd %esi, %xmm0
+; AVX2-64-NEXT:    vpinsrw $1, %edi, %xmm0, %xmm0
+; AVX2-64-NEXT:    vpinsrw $2, %esi, %xmm0, %xmm0
+; AVX2-64-NEXT:    vpinsrw $3, %esi, %xmm0, %xmm0
+; AVX2-64-NEXT:    vpinsrw $4, %esi, %xmm0, %xmm0
+; AVX2-64-NEXT:    vpinsrw $5, %edi, %xmm0, %xmm0
+; AVX2-64-NEXT:    vpinsrw $6, %edi, %xmm0, %xmm0
+; AVX2-64-NEXT:    vpinsrw $7, %edi, %xmm0, %xmm0
+; AVX2-64-NEXT:    vmovd %edi, %xmm1
+; AVX2-64-NEXT:    vpinsrw $1, %esi, %xmm1, %xmm1
+; AVX2-64-NEXT:    vpinsrw $2, %edi, %xmm1, %xmm1
+; AVX2-64-NEXT:    vpinsrw $3, %edi, %xmm1, %xmm1
+; AVX2-64-NEXT:    vpinsrw $4, %edi, %xmm1, %xmm1
+; AVX2-64-NEXT:    vpinsrw $5, %edi, %xmm1, %xmm1
+; AVX2-64-NEXT:    vpinsrw $6, %edi, %xmm1, %xmm1
+; AVX2-64-NEXT:    vpinsrw $7, %esi, %xmm1, %xmm1
+; AVX2-64-NEXT:    vinserti128 $1, %xmm0, %ymm1, %ymm0
+; AVX2-64-NEXT:    retq
+  %v0 = insertelement <16 x i16> poison, i16 %a0, i16 0
+  %v1 = insertelement <16 x i16> %v0, i16 %a1, i16 1
+  %v2 = insertelement <16 x i16> %v1, i16 %a0, i16 2
+  %v3 = insertelement <16 x i16> %v2, i16 %a0, i16 3
+  %v4 = insertelement <16 x i16> %v3, i16 %a0, i16 4
+  %v5 = insertelement <16 x i16> %v4, i16 %a0, i16 5
+  %v6 = insertelement <16 x i16> %v5, i16 %a0, i16 6
+  %v7 = insertelement <16 x i16> %v6, i16 %a1, i16 7
+  %v8 = insertelement <16 x i16> %v7, i16 %a1, i16 8
+  %v9 = insertelement <16 x i16> %v8, i16 %a0, i16 9
+  %v10 = insertelement <16 x i16> %v9, i16 %a1, i16 10
+  %v11 = insertelement <16 x i16> %v10, i16 %a1, i16 11
+  %v12 = insertelement <16 x i16> %v11, i16 %a1, i16 12
+  %v13 = insertelement <16 x i16> %v12, i16 %a0, i16 13
+  %v14 = insertelement <16 x i16> %v13, i16 %a0, i16 14
+  %v15 = insertelement <16 x i16> %v14, i16 %a0, i16 15
+  ret <16 x i16> %v15
+}
+
+define <16 x i16> @test_buildvector_16i16_2_load(ptr %p0, ptr %p1) {
+; AVX1-32-LABEL: test_buildvector_16i16_2_load:
+; AVX1-32:       # %bb.0:
+; AVX1-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; AVX1-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; AVX1-32-NEXT:    movzwl (%eax), %eax
+; AVX1-32-NEXT:    movzwl (%ecx), %ecx
+; AVX1-32-NEXT:    vmovd %ecx, %xmm0
+; AVX1-32-NEXT:    vpinsrw $1, %eax, %xmm0, %xmm0
+; AVX1-32-NEXT:    vpinsrw $2, %ecx, %xmm0, %xmm0
+; AVX1-32-NEXT:    vpinsrw $3, %ecx, %xmm0, %xmm0
+; AVX1-32-NEXT:    vpinsrw $4, %ecx, %xmm0, %xmm0
+; AVX1-32-NEXT:    vpinsrw $5, %eax, %xmm0, %xmm0
+; AVX1-32-NEXT:    vpinsrw $6, %eax, %xmm0, %xmm0
+; AVX1-32-NEXT:    vpinsrw $7, %eax, %xmm0, %xmm0
+; AVX1-32-NEXT:    vmovd %eax, %xmm1
+; AVX1-32-NEXT:    vpinsrw $1, %ecx, %xmm1, %xmm1
+; AVX1-32-NEXT:    vpinsrw $2, %eax, %xmm1, %xmm1
+; AVX1-32-NEXT:    vpinsrw $3, %eax, %xmm1, %xmm1
+; AVX1-32-NEXT:    vpinsrw $4, %eax, %xmm1, %xmm1
+; AVX1-32-NEXT:    vpinsrw $5, %eax, %xmm1, %xmm1
+; AVX1-32-NEXT:    vpinsrw $6, %eax, %xmm1, %xmm1
+; AVX1-32-NEXT:    vpinsrw $7, %ecx, %xmm1, %xmm1
+; AVX1-32-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-32-NEXT:    retl
+;
+; AVX1-64-LABEL: test_buildvector_16i16_2_load:
+; AVX1-64:       # %bb.0:
+; AVX1-64-NEXT:    movzwl (%rdi), %eax
+; AVX1-64-NEXT:    movzwl (%rsi), %ecx
+; AVX1-64-NEXT:    vmovd %ecx, %xmm0
+; AVX1-64-NEXT:    vpinsrw $1, %eax, %xmm0, %xmm0
+; AVX1-64-NEXT:    vpinsrw $2, %ecx, %xmm0, %xmm0
+; AVX1-64-NEXT:    vpinsrw $3, %ecx, %xmm0, %xmm0
+; AVX1-64-NEXT:    vpinsrw $4, %ecx, %xmm0, %xmm0
+; AVX1-64-NEXT:    vpinsrw $5, %eax, %xmm0, %xmm0
+; AVX1-64-NEXT:    vpinsrw $6, %eax, %xmm0, %xmm0
+; AVX1-64-NEXT:    vpinsrw $7, %eax, %xmm0, %xmm0
+; AVX1-64-NEXT:    vmovd %eax, %xmm1
+; AVX1-64-NEXT:    vpinsrw $1, %ecx, %xmm1, %xmm1
+; AVX1-64-NEXT:    vpinsrw $2, %eax, %xmm1, %xmm1
+; AVX1-64-NEXT:    vpinsrw $3, %eax, %xmm1, %xmm1
+; AVX1-64-NEXT:    vpinsrw $4, %eax, %xmm1, %xmm1
+; AVX1-64-NEXT:    vpinsrw $5, %eax, %xmm1, %xmm1
+; AVX1-64-NEXT:    vpinsrw $6, %eax, %xmm1, %xmm1
+; AVX1-64-NEXT:    vpinsrw $7, %ecx, %xmm1, %xmm1
+; AVX1-64-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-64-NEXT:    retq
+;
+; AVX2-32-LABEL: test_buildvector_16i16_2_load:
+; AVX2-32:       # %bb.0:
+; AVX2-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; AVX2-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; AVX2-32-NEXT:    movzwl (%eax), %eax
+; AVX2-32-NEXT:    movzwl (%ecx), %ecx
+; AVX2-32-NEXT:    vmovd %ecx, %xmm0
+; AVX2-32-NEXT:    vpinsrw $1, %eax, %xmm0, %xmm0
+; AVX2-32-NEXT:    vpinsrw $2, %ecx, %xmm0, %xmm0
+; AVX2-32-NEXT:    vpinsrw $3, %ecx, %xmm0, %xmm0
+; AVX2-32-NEXT:    vpinsrw $4, %ecx, %xmm0, %xmm0
+; AVX2-32-NEXT:    vpinsrw $5, %eax, %xmm0, %xmm0
+; AVX2-32-NEXT:    vpinsrw $6, %eax, %xmm0, %xmm0
+; AVX2-32-NEXT:    vpinsrw $7, %eax, %xmm0, %xmm0
+; AVX2-32-NEXT:    vmovd %eax, %xmm1
+; AVX2-32-NEXT:    vpinsrw $1, %ecx, %xmm1, %xmm1
+; AVX2-32-NEXT:    vpinsrw $2, %eax, %xmm1, %xmm1
+; AVX2-32-NEXT:    vpinsrw $3, %eax, %xmm1, %xmm1
+; AVX2-32-NEXT:    vpinsrw $4, %eax, %xmm1, %xmm1
+; AVX2-32-NEXT:    vpinsrw $5, %eax, %xmm1, %xmm1
+; AVX2-32-NEXT:    vpinsrw $6, %eax, %xmm1, %xmm1
+; AVX2-32-NEXT:    vpinsrw $7, %ecx, %xmm1, %xmm1
+; AVX2-32-NEXT:    vinserti128 $1, %xmm0, %ymm1, %ymm0
+; AVX2-32-NEXT:    retl
+;
+; AVX2-64-LABEL: test_buildvector_16i16_2_load:
+; AVX2-64:       # %bb.0:
+; AVX2-64-NEXT:    movzwl (%rdi), %eax
+; AVX2-64-NEXT:    movzwl (%rsi), %ecx
+; AVX2-64-NEXT:    vmovd %ecx, %xmm0
+; AVX2-64-NEXT:    vpinsrw $1, %eax, %xmm0, %xmm0
+; AVX2-64-NEXT:    vpinsrw $2, %ecx, %xmm0, %xmm0
+; AVX2-64-NEXT:    vpinsrw $3, %ecx, %xmm0, %xmm0
+; AVX2-64-NEXT:    vpinsrw $4, %ecx, %xmm0, %xmm0
+; AVX2-64-NEXT:    vpinsrw $5, %eax, %xmm0, %xmm0
+; AVX2-64-NEXT:    vpinsrw $6, %eax, %xmm0, %xmm0
+; AVX2-64-NEXT:    vpinsrw $7, %eax, %xmm0, %xmm0
+; AVX2-64-NEXT:    vmovd %eax, %xmm1
+; AVX2-64-NEXT:    vpinsrw $1, %ecx, %xmm1, %xmm1
+; AVX2-64-NEXT:    vpinsrw $2, %eax, %xmm1, %xmm1
+; AVX2-64-NEXT:    vpinsrw $3, %eax, %xmm1, %xmm1
+; AVX2-64-NEXT:    vpinsrw $4, %eax, %xmm1, %xmm1
+; AVX2-64-NEXT:    vpinsrw $5, %eax, %xmm1, %xmm1
+; AVX2-64-NEXT:    vpinsrw $6, %eax, %xmm1, %xmm1
+; AVX2-64-NEXT:    vpinsrw $7, %ecx, %xmm1, %xmm1
+; AVX2-64-NEXT:    vinserti128 $1, %xmm0, %ymm1, %ymm0
+; AVX2-64-NEXT:    retq
+  %a0 = load i16, ptr %p0
+  %a1 = load i16, ptr %p1
+  %v0 = insertelement <16 x i16> poison, i16 %a0, i16 0
+  %v1 = insertelement <16 x i16> %v0, i16 %a1, i16 1
+  %v2 = insertelement <16 x i16> %v1, i16 %a0, i16 2
+  %v3 = insertelement <16 x i16> %v2, i16 %a0, i16 3
+  %v4 = insertelement <16 x i16> %v3, i16 %a0, i16 4
+  %v5 = insertelement <16 x i16> %v4, i16 %a0, i16 5
+  %v6 = insertelement <16 x i16> %v5, i16 %a0, i16 6
+  %v7 = insertelement <16 x i16> %v6, i16 %a1, i16 7
+  %v8 = insertelement <16 x i16> %v7, i16 %a1, i16 8
+  %v9 = insertelement <16 x i16> %v8, i16 %a0, i16 9
+  %v10 = insertelement <16 x i16> %v9, i16 %a1, i16 10
+  %v11 = insertelement <16 x i16> %v10, i16 %a1, i16 11
+  %v12 = insertelement <16 x i16> %v11, i16 %a1, i16 12
+  %v13 = insertelement <16 x i16> %v12, i16 %a0, i16 13
+  %v14 = insertelement <16 x i16> %v13, i16 %a0, i16 14
+  %v15 = insertelement <16 x i16> %v14, i16 %a0, i16 15
+  ret <16 x i16> %v15
+}
+
 ; PR30780
 
 define <8 x i32> @test_buildvector_v8i32_splat_sext_i8(i8 %in) {
@@ -485,3 +832,4 @@ define <8 x i32> @test_buildvector_v8i32_splat_zext_i8(i8 %in) {
   %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
   ret <8 x i32> %splat
 }
+
diff --git a/llvm/test/CodeGen/X86/build-vector-512.ll b/llvm/test/CodeGen/X86/build-vector-512.ll
index ac33ac96db416..5d38f087aa1b3 100644
--- a/llvm/test/CodeGen/X86/build-vector-512.ll
+++ b/llvm/test/CodeGen/X86/build-vector-512.ll
@@ -476,3 +476,164 @@ define <64 x i8> @test_buildvector_v64i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4,
   %ins63 = insertelement <64 x i8> %ins62, i8 %a63, i32 63
   ret <64 x i8> %ins63
 }
+
+; build vectors of repeated elements
+
+define <8 x double> @test_buildvector_8f64_2_var(double %a0, double %a1) {
+; AVX-32-LABEL: test_buildvector_8f64_2_var:
+; AVX-32:       # %bb.0:
+; AVX-32-NEXT:    vmovddup {{.*#+}} xmm0 = mem[0,0]
+; AVX-32-NEXT:    vmovups {{[0-9]+}}(%esp), %xmm1
+; AVX-32-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm2
+; AVX-32-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX-32-NEXT:    vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
+; AVX-32-NEXT:    retl
+;
+; AVX-64-LABEL: test_buildvector_8f64_2_var:
+; AVX-64:       # %bb.0:
+; AVX-64-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0]
+; AVX-64-NEXT:    vmovlhps {{.*#+}} xmm1 = xmm0[0],xmm1[0]
+; AVX-64-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm2
+; AVX-64-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX-64-NEXT:    vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
+; AVX-64-NEXT:    retq
+  %v0 = insertelement <8 x double> poison, double %a0, i32 0
+  %v1 = insertelement <8 x double> %v0, double %a1, i32 1
+  %v2 = insertelement <8 x double> %v1, double %a0, i32 2
+  %v3 = insertelement <8 x double> %v2, double %a0, i32 3
+  %v4 = insertelement <8 x double> %v3, double %a0, i32 4
+  %v5 = insertelement <8 x double> %v4, double %a0, i32 5
+  %v6 = insertelement <8 x double> %v5, double %a0, i32 6
+  %v7 = insertelement <8 x double> %v6, double %a1, i32 7
+  ret <8 x double> %v7
+}
+
+define <8 x double> @test_buildvector_8f64_2_load(ptr %p0, ptr %p1) {
+; AVX-32-LABEL: test_buildvector_8f64_2_load:
+; AVX-32:       # %bb.0:
+; AVX-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; AVX-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; AVX-32-NEXT:    vmovddup {{.*#+}} xmm0 = mem[0,0]
+; AVX-32-NEXT:    vmovhps {{.*#+}} xmm1 = xmm0[0,1],mem[0,1]
+; AVX-32-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm2
+; AVX-32-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX-32-NEXT:    vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
+; AVX-32-NEXT:    retl
+;
+; AVX-64-LABEL: test_buildvector_8f64_2_load:
+; AVX-64:       # %bb.0:
+; AVX-64-NEXT:    vmovddup {{.*#+}} xmm0 = mem[0,0]
+; AVX-64-NEXT:    vmovhps {{.*#+}} xmm1 = xmm0[0,1],mem[0,1]
+; AVX-64-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm2
+; AVX-64-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX-64-NEXT:    vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
+; AVX-64-NEXT:    retq
+  %a0 = load double, ptr %p0
+  %a1 = load double, ptr %p1
+  %v0 = insertelement <8 x double> poison, double %a0, i32 0
+  %v1 = insertelement <8 x double> %v0, double %a1, i32 1
+  %v2 = insertelement <8 x double> %v1, double %a0, i32 2
+  %v3 = insertelement <8 x double> %v2, double %a0, i32 3
+  %v4 = insertelement <8 x double> %v3, double %a0, i32 4
+  %v5 = insertelement <8 x double> %v4, double %a0, i32 5
+  %v6 = insertelement <8 x double> %v5, double %a0, i32 6
+  %v7 = insertelement <8 x double> %v6, double %a1, i32 7
+  ret <8 x double> %v7
+}
+
+define <16 x float> @test_buildvector_16f32_2_var(float %a0, float %a1) {
+; AVX-32-LABEL: test_buildvector_16f32_2_var:
+; AVX-32:       # %bb.0:
+; AVX-32-NEXT:    vbroadcastss {{[0-9]+}}(%esp), %xmm0
+; AVX-32-NEXT:    vpmovsxbd {{.*#+}} xmm1 = [0,17,0,0]
+; AVX-32-NEXT:    vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; AVX-32-NEXT:    vpermi2ps %zmm0, %zmm2, %zmm1
+; AVX-32-NEXT:    vblendps {{.*#+}} xmm3 = xmm2[0],xmm0[1,2,3]
+; AVX-32-NEXT:    vinsertf128 $1, %xmm3, %ymm1, %ymm1
+; AVX-32-NEXT:    vinsertps {{.*#+}} xmm3 = xmm0[0,1,2],xmm2[0]
+; AVX-32-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3]
+; AVX-32-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
+; AVX-32-NEXT:    vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
+; AVX-32-NEXT:    retl
+;
+; AVX-64-LABEL: test_buildvector_16f32_2_var:
+; AVX-64:       # %bb.0:
+; AVX-64-NEXT:    # kill: def $xmm1 killed $xmm1 def $zmm1
+; AVX-64-NEXT:    vpmovsxbd {{.*#+}} xmm2 = [0,16,0,0]
+; AVX-64-NEXT:    vbroadcastss %xmm0, %xmm0
+; AVX-64-NEXT:    vpermi2ps %zmm1, %zmm0, %zmm2
+; AVX-64-NEXT:    vinsertps {{.*#+}} xmm3 = xmm0[0,1,2],xmm1[0]
+; AVX-64-NEXT:    vinsertf128 $1, %xmm3, %ymm2, %ymm2
+; AVX-64-NEXT:    vpmovsxbd {{.*#+}} ymm3 = [0,16,0,0,0,17,18,19]
+; AVX-64-NEXT:    vpermi2ps %zmm0, %zmm1, %zmm3
+; AVX-64-NEXT:    vinsertf64x4 $1, %ymm3, %zmm2, %zmm0
+; AVX-64-NEXT:    retq
+  %v0 = insertelement <16 x float> poison, float %a0, i32 0
+  %v1 = insertelement <16 x float> %v0, float %a1, i32 1
+  %v2 = insertelement <16 x float> %v1, float %a0, i32 2
+  %v3 = insertelement <16 x float> %v2, float %a0, i32 3
+  %v4 = insertelement <16 x float> %v3, float %a0, i32 4
+  %v5 = insertelement <16 x float> %v4, float %a0, i32 5
+  %v6 = insertelement <16 x float> %v5, float %a0, i32 6
+  %v7 = insertelement <16 x float> %v6, float %a1, i32 7
+  %v8 = insertelement <16 x float> %v7, float %a1, i32 8
+  %v9 = insertelement <16 x float> %v8, float %a0, i32 9
+  %v10 = insertelement <16 x float> %v9, float %a1, i32 10
+  %v11 = insertelement <16 x float> %v10, float %a1, i32 11
+  %v12 = insertelement <16 x float> %v11, float %a1, i32 12
+  %v13 = insertelement <16 x float> %v12, float %a0, i32 13
+  %v14 = insertelement <16 x float> %v13, float %a0, i32 14
+  %v15 = insertelement <16 x float> %v14, float %a0, i32 15
+  ret <16 x float> %v15
+}
+
+define <16 x float> @test_buildvector_16f32_2_load(ptr %p0, ptr %p1) {
+; AVX-32-LABEL: test_buildvector_16f32_2_load:
+; AVX-32:       # %bb.0:
+; AVX-32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; AVX-32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; AVX-32-NEXT:    vpmovsxbd {{.*#+}} xmm0 = [0,17,0,0]
+; AVX-32-NEXT:    vbroadcastss (%ecx), %xmm1
+; AVX-32-NEXT:    vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; AVX-32-NEXT:    vpermi2ps %zmm1, %zmm2, %zmm0
+; AVX-32-NEXT:    vblendps {{.*#+}} xmm3 = xmm2[0],xmm1[1,2,3]
+; AVX-32-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
+; AVX-32-NEXT:    vinsertps {{.*#+}} xmm3 = xmm1[0,1,2],xmm2[0]
+; AVX-32-NEXT:    vinsertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[2,3]
+; AVX-32-NEXT:    vinsertf128 $1, %xmm3, %ymm1, %ymm1
+; AVX-32-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
+; AVX-32-NEXT:    retl
+;
+; AVX-64-LABEL: test_buildvector_16f32_2_load:
+; AVX-64:       # %bb.0:
+; AVX-64-NEXT:    vpmovsxbd {{.*#+}} xmm0 = [0,17,0,0]
+; AVX-64-NEXT:    vbroadcastss (%rdi), %xmm1
+; AVX-64-NEXT:    vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; AVX-64-NEXT:    vpermi2ps %zmm1, %zmm2, %zmm0
+; AVX-64-NEXT:    vblendps {{.*#+}} xmm3 = xmm2[0],xmm1[1,2,3]
+; AVX-64-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
+; AVX-64-NEXT:    vinsertps {{.*#+}} xmm3 = xmm1[0,1,2],xmm2[0]
+; AVX-64-NEXT:    vinsertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[2,3]
+; AVX-64-NEXT:    vinsertf128 $1, %xmm3, %ymm1, %ymm1
+; AVX-64-NEXT:    vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
+; AVX-64-NEXT:    retq
+  %a0 = load float, ptr %p0
+  %a1 = load float, ptr %p1
+  %v0 = insertelement <16 x float> poison, float %a0, i32 0
+  %v1 = insertelement <16 x float> %v0, float %a1, i32 1
+  %v2 = insertelement <16 x float> %v1, float %a0, i32 2
+  %v3 = insertelement <16 x float> %v2, float %a0, i32 3
+  %v4 = insertelement <16 x float> %v3, float %a0, i32 4
+  %v5 = insertelement <16 x float> %v4, float %a0, i32 5
+  %v6 = insertelement <16 x float> %v5, float %a0, i32 6
+  %v7 = insertelement <16 x float> %v6, float %a1, i32 7
+  %v8 = insertelement <16 x float> %v7, float %a1, i32 8
+  %v9 = insertelement <16 x float> %v8, float %a0, i32 9
+  %v10 = insertelement <16 x float> %v9, float %a1, i32 10
+  %v11 = insertelement <16 x float> %v10, float %a1, i32 11
+  %v12 = insertelement <16 x float> %v11, float %a1, i32 12
+  %v13 = insertelement <16 x float> %v12, float %a0, i32 13
+  %v14 = insertelement <16 x float> %v13, float %a0, i32 14
+  %v15 = insertelement <16 x float> %v14, float %a0, i32 15
+  ret <16 x float> %v15
+}
diff --git a/llvm/test/CodeGen/X86/buildvec-widen-dotproduct.ll b/llvm/test/CodeGen/X86/buildvec-widen-dotproduct.ll
new file mode 100644
index 0000000000000..8c85dfa09fd2d
--- /dev/null
+++ b/llvm/test/CodeGen/X86/buildvec-widen-dotproduct.ll
@@ -0,0 +1,587 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64   | FileCheck %s --check-prefixes=SSE2
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE4
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX,AVX2
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX,AVX512
+
+define i32 @dot_ext_v8i8_v8i32(ptr %a, i64 %a_stride, ptr %b) nounwind {
+; SSE2-LABEL: dot_ext_v8i8_v8i32:
+; SSE2:       # %bb.0: # %entry
+; SSE2-NEXT:    pushq %r14
+; SSE2-NEXT:    pushq %rbx
+; SSE2-NEXT:    movzbl (%rdi), %eax
+; SSE2-NEXT:    movzbl (%rdi,%rsi), %ecx
+; SSE2-NEXT:    movzbl (%rdi,%rsi,2), %r8d
+; SSE2-NEXT:    leaq (%rsi,%rsi,2), %r9
+; SSE2-NEXT:    movzbl (%rdi,%r9), %r10d
+; SSE2-NEXT:    movzbl (%rdi,%rsi,4), %r11d
+; SSE2-NEXT:    leaq (%rsi,%rsi,4), %rbx
+; SSE2-NEXT:    movzbl (%rdi,%rbx), %ebx
+; SSE2-NEXT:    movzbl (%rdi,%r9,2), %r9d
+; SSE2-NEXT:    leaq (,%rsi,8), %r14
+; SSE2-NEXT:    subq %rsi, %r14
+; SSE2-NEXT:    movzbl (%rdi,%r14), %esi
+; SSE2-NEXT:    shll $16, %ecx
+; SSE2-NEXT:    orl %eax, %ecx
+; SSE2-NEXT:    movd %ecx, %xmm0
+; SSE2-NEXT:    pinsrw $2, %r8d, %xmm0
+; SSE2-NEXT:    pinsrw $3, %r10d, %xmm0
+; SSE2-NEXT:    pinsrw $4, %r11d, %xmm0
+; SSE2-NEXT:    pinsrw $5, %ebx, %xmm0
+; SSE2-NEXT:    pinsrw $6, %r9d, %xmm0
+; SSE2-NEXT:    pinsrw $7, %esi, %xmm0
+; SSE2-NEXT:    movdqu (%rdx), %xmm1
+; SSE2-NEXT:    pmaddwd %xmm1, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; SSE2-NEXT:    paddd %xmm0, %xmm1
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
+; SSE2-NEXT:    paddd %xmm1, %xmm0
+; SSE2-NEXT:    movd %xmm0, %eax
+; SSE2-NEXT:    popq %rbx
+; SSE2-NEXT:    popq %r14
+; SSE2-NEXT:    retq
+;
+; SSE4-LABEL: dot_ext_v8i8_v8i32:
+; SSE4:       # %bb.0: # %entry
+; SSE4-NEXT:    leaq (%rsi,%rsi,4), %rax
+; SSE4-NEXT:    leaq (%rsi,%rsi,2), %rcx
+; SSE4-NEXT:    leaq (,%rsi,8), %r8
+; SSE4-NEXT:    movzbl (%rdi), %r9d
+; SSE4-NEXT:    movd %r9d, %xmm0
+; SSE4-NEXT:    pinsrb $1, (%rdi,%rsi), %xmm0
+; SSE4-NEXT:    pinsrb $2, (%rdi,%rsi,2), %xmm0
+; SSE4-NEXT:    pinsrb $3, (%rdi,%rcx), %xmm0
+; SSE4-NEXT:    pinsrb $4, (%rdi,%rsi,4), %xmm0
+; SSE4-NEXT:    pinsrb $5, (%rdi,%rax), %xmm0
+; SSE4-NEXT:    pinsrb $6, (%rdi,%rcx,2), %xmm0
+; SSE4-NEXT:    subq %rsi, %r8
+; SSE4-NEXT:    pinsrb $7, (%rdi,%r8), %xmm0
+; SSE4-NEXT:    movdqu (%rdx), %xmm1
+; SSE4-NEXT:    pmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; SSE4-NEXT:    pmaddwd %xmm1, %xmm0
+; SSE4-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; SSE4-NEXT:    paddd %xmm0, %xmm1
+; SSE4-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
+; SSE4-NEXT:    paddd %xmm1, %xmm0
+; SSE4-NEXT:    movd %xmm0, %eax
+; SSE4-NEXT:    retq
+;
+; AVX2-LABEL: dot_ext_v8i8_v8i32:
+; AVX2:       # %bb.0: # %entry
+; AVX2-NEXT:    leaq (%rsi,%rsi,4), %rax
+; AVX2-NEXT:    leaq (%rsi,%rsi,2), %rcx
+; AVX2-NEXT:    leaq (,%rsi,8), %r8
+; AVX2-NEXT:    subq %rsi, %r8
+; AVX2-NEXT:    movzbl (%rdi), %r9d
+; AVX2-NEXT:    vmovd %r9d, %xmm0
+; AVX2-NEXT:    vpinsrb $1, (%rdi,%rsi), %xmm0, %xmm0
+; AVX2-NEXT:    vpinsrb $2, (%rdi,%rsi,2), %xmm0, %xmm0
+; AVX2-NEXT:    vpinsrb $3, (%rdi,%rcx), %xmm0, %xmm0
+; AVX2-NEXT:    vpinsrb $4, (%rdi,%rsi,4), %xmm0, %xmm0
+; AVX2-NEXT:    vpinsrb $5, (%rdi,%rax), %xmm0, %xmm0
+; AVX2-NEXT:    vpinsrb $6, (%rdi,%rcx,2), %xmm0, %xmm0
+; AVX2-NEXT:    vpinsrb $7, (%rdi,%r8), %xmm0, %xmm0
+; AVX2-NEXT:    vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; AVX2-NEXT:    vpmaddwd (%rdx), %xmm0, %xmm0
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; AVX2-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; AVX2-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
+; AVX2-NEXT:    vmovd %xmm0, %eax
+; AVX2-NEXT:    retq
+;
+; AVX512-LABEL: dot_ext_v8i8_v8i32:
+; AVX512:       # %bb.0: # %entry
+; AVX512-NEXT:    leaq (%rsi,%rsi,4), %rax
+; AVX512-NEXT:    leaq (%rsi,%rsi,2), %rcx
+; AVX512-NEXT:    leaq (,%rsi,8), %r8
+; AVX512-NEXT:    movzbl (%rdi), %r9d
+; AVX512-NEXT:    vmovd %r9d, %xmm0
+; AVX512-NEXT:    vpinsrb $1, (%rdi,%rsi), %xmm0, %xmm0
+; AVX512-NEXT:    vpinsrb $2, (%rdi,%rsi,2), %xmm0, %xmm0
+; AVX512-NEXT:    vpinsrb $3, (%rdi,%rcx), %xmm0, %xmm0
+; AVX512-NEXT:    vpinsrb $4, (%rdi,%rsi,4), %xmm0, %xmm0
+; AVX512-NEXT:    vpinsrb $5, (%rdi,%rax), %xmm0, %xmm0
+; AVX512-NEXT:    vpinsrb $6, (%rdi,%rcx,2), %xmm0, %xmm0
+; AVX512-NEXT:    subq %rsi, %r8
+; AVX512-NEXT:    vpinsrb $7, (%rdi,%r8), %xmm0, %xmm0
+; AVX512-NEXT:    vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; AVX512-NEXT:    vpmaddwd (%rdx), %xmm0, %xmm0
+; AVX512-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; AVX512-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
+; AVX512-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; AVX512-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
+; AVX512-NEXT:    vmovd %xmm0, %eax
+; AVX512-NEXT:    retq
+entry:
+  %var0 = load i8, ptr %a, align 1
+  %arrayidx.1 = getelementptr inbounds i8, ptr %a, i64 %a_stride
+  %var1 = load i8, ptr %arrayidx.1, align 1
+  %mul.2 = shl nsw i64 %a_stride, 1
+  %arrayidx.2 = getelementptr inbounds i8, ptr %a, i64 %mul.2
+  %var2 = load i8, ptr %arrayidx.2, align 1
+  %mul.3 = mul nsw i64 %a_stride, 3
+  %arrayidx.3 = getelementptr inbounds i8, ptr %a, i64 %mul.3
+  %var3 = load i8, ptr %arrayidx.3, align 1
+  %mul.4 = shl nsw i64 %a_stride, 2
+  %arrayidx.4 = getelementptr inbounds i8, ptr %a, i64 %mul.4
+  %var4 = load i8, ptr %arrayidx.4, align 1
+  %mul.5 = mul nsw i64 %a_stride, 5
+  %arrayidx.5 = getelementptr inbounds i8, ptr %a, i64 %mul.5
+  %var5 = load i8, ptr %arrayidx.5, align 1
+  %mul.6 = mul nsw i64 %a_stride, 6
+  %arrayidx.6 = getelementptr inbounds i8, ptr %a, i64 %mul.6
+  %var6 = load i8, ptr %arrayidx.6, align 1
+  %mul.7 = mul nsw i64 %a_stride, 7
+  %arrayidx.7 = getelementptr inbounds i8, ptr %a, i64 %mul.7
+  %var7 = load i8, ptr %arrayidx.7, align 1
+  %var8 = insertelement <8 x i8> poison, i8 %var0, i64 0
+  %var9 = insertelement <8 x i8> %var8, i8 %var1, i64 1
+  %var10 = insertelement <8 x i8> %var9, i8 %var2, i64 2
+  %var11 = insertelement <8 x i8> %var10, i8 %var3, i64 3
+  %var12 = insertelement <8 x i8> %var11, i8 %var4, i64 4
+  %var13 = insertelement <8 x i8> %var12, i8 %var5, i64 5
+  %var14 = insertelement <8 x i8> %var13, i8 %var6, i64 6
+  %var15 = insertelement <8 x i8> %var14, i8 %var7, i64 7
+  %var16 = zext <8 x i8> %var15 to <8 x i32>
+  %var17 = load <8 x i16>, ptr %b, align 2
+  %var18 = sext <8 x i16> %var17 to <8 x i32>
+  %var19 = mul nsw <8 x i32> %var18, %var16
+  %var20 = tail call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %var19)
+  ret i32 %var20
+}
+
+define i32 @dot_ext_v4i8_v4i32(ptr %a, i64 %a_stride, ptr %b) nounwind {
+; SSE2-LABEL: dot_ext_v4i8_v4i32:
+; SSE2:       # %bb.0: # %entry
+; SSE2-NEXT:    movzbl (%rdi), %eax
+; SSE2-NEXT:    movzbl (%rdi,%rsi), %ecx
+; SSE2-NEXT:    movzbl (%rdi,%rsi,2), %r8d
+; SSE2-NEXT:    leaq (%rsi,%rsi,2), %rsi
+; SSE2-NEXT:    movd %eax, %xmm0
+; SSE2-NEXT:    pinsrw $2, %ecx, %xmm0
+; SSE2-NEXT:    pinsrw $4, %r8d, %xmm0
+; SSE2-NEXT:    movzbl (%rdi,%rsi), %eax
+; SSE2-NEXT:    pinsrw $6, %eax, %xmm0
+; SSE2-NEXT:    movq {{.*#+}} xmm1 = mem[0],zero
+; SSE2-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3]
+; SSE2-NEXT:    pmaddwd %xmm0, %xmm1
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; SSE2-NEXT:    paddd %xmm1, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; SSE2-NEXT:    paddd %xmm0, %xmm1
+; SSE2-NEXT:    movd %xmm1, %eax
+; SSE2-NEXT:    retq
+;
+; SSE4-LABEL: dot_ext_v4i8_v4i32:
+; SSE4:       # %bb.0: # %entry
+; SSE4-NEXT:    leaq (%rsi,%rsi,2), %rax
+; SSE4-NEXT:    movzbl (%rdi), %ecx
+; SSE4-NEXT:    movd %ecx, %xmm0
+; SSE4-NEXT:    pinsrb $1, (%rdi,%rsi), %xmm0
+; SSE4-NEXT:    pinsrb $2, (%rdi,%rsi,2), %xmm0
+; SSE4-NEXT:    pinsrb $3, (%rdi,%rax), %xmm0
+; SSE4-NEXT:    pmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
+; SSE4-NEXT:    pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
+; SSE4-NEXT:    pmaddwd %xmm0, %xmm1
+; SSE4-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; SSE4-NEXT:    paddd %xmm1, %xmm0
+; SSE4-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; SSE4-NEXT:    paddd %xmm0, %xmm1
+; SSE4-NEXT:    movd %xmm1, %eax
+; SSE4-NEXT:    retq
+;
+; AVX-LABEL: dot_ext_v4i8_v4i32:
+; AVX:       # %bb.0: # %entry
+; AVX-NEXT:    movzbl (%rdi), %eax
+; AVX-NEXT:    vmovd %eax, %xmm0
+; AVX-NEXT:    vpinsrb $1, (%rdi,%rsi), %xmm0, %xmm0
+; AVX-NEXT:    vpinsrb $2, (%rdi,%rsi,2), %xmm0, %xmm0
+; AVX-NEXT:    leaq (%rsi,%rsi,2), %rax
+; AVX-NEXT:    vpinsrb $3, (%rdi,%rax), %xmm0, %xmm0
+; AVX-NEXT:    vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
+; AVX-NEXT:    vpmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
+; AVX-NEXT:    vpmaddwd %xmm0, %xmm1, %xmm0
+; AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; AVX-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; AVX-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vmovd %xmm0, %eax
+; AVX-NEXT:    retq
+entry:
+  %var0 = load i8, ptr %a, align 1
+  %arrayidx.1 = getelementptr inbounds i8, ptr %a, i64 %a_stride
+  %var1 = load i8, ptr %arrayidx.1, align 1
+  %mul.2 = shl nsw i64 %a_stride, 1
+  %arrayidx.2 = getelementptr inbounds i8, ptr %a, i64 %mul.2
+  %var2 = load i8, ptr %arrayidx.2, align 1
+  %mul.3 = mul nsw i64 %a_stride, 3
+  %arrayidx.3 = getelementptr inbounds i8, ptr %a, i64 %mul.3
+  %var3 = load i8, ptr %arrayidx.3, align 1
+  %var8 = insertelement <4 x i8> poison, i8 %var0, i64 0
+  %var9 = insertelement <4 x i8> %var8, i8 %var1, i64 1
+  %var10 = insertelement <4 x i8> %var9, i8 %var2, i64 2
+  %var11 = insertelement <4 x i8> %var10, i8 %var3, i64 3
+  %var16 = zext <4 x i8> %var11 to <4 x i32>
+  %var17 = load <4 x i16>, ptr %b, align 2
+  %var18 = sext <4 x i16> %var17 to <4 x i32>
+  %var19 = mul nsw <4 x i32> %var18, %var16
+  %var20 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %var19)
+  ret i32 %var20
+}
+
+define i32 @dot_ext_v2i8_v2i32(ptr %a, i64 %a_stride, ptr %b) nounwind {
+; SSE2-LABEL: dot_ext_v2i8_v2i32:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    movzbl (%rdi), %eax
+; SSE2-NEXT:    movzbl (%rdi,%rsi), %ecx
+; SSE2-NEXT:    movd %eax, %xmm0
+; SSE2-NEXT:    pinsrw $2, %ecx, %xmm0
+; SSE2-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE2-NEXT:    pshuflw {{.*#+}} xmm1 = xmm1[0,1,1,3,4,5,6,7]
+; SSE2-NEXT:    pmaddwd %xmm0, %xmm1
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
+; SSE2-NEXT:    paddd %xmm1, %xmm0
+; SSE2-NEXT:    movd %xmm0, %eax
+; SSE2-NEXT:    retq
+;
+; SSE4-LABEL: dot_ext_v2i8_v2i32:
+; SSE4:       # %bb.0:
+; SSE4-NEXT:    movzbl (%rdi), %eax
+; SSE4-NEXT:    movd %eax, %xmm0
+; SSE4-NEXT:    pinsrb $4, (%rdi,%rsi), %xmm0
+; SSE4-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE4-NEXT:    pmovzxwd {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
+; SSE4-NEXT:    pmaddwd %xmm0, %xmm1
+; SSE4-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
+; SSE4-NEXT:    paddd %xmm1, %xmm0
+; SSE4-NEXT:    movd %xmm0, %eax
+; SSE4-NEXT:    retq
+;
+; AVX-LABEL: dot_ext_v2i8_v2i32:
+; AVX:       # %bb.0:
+; AVX-NEXT:    movzbl (%rdi), %eax
+; AVX-NEXT:    vmovd %eax, %xmm0
+; AVX-NEXT:    vpinsrb $4, (%rdi,%rsi), %xmm0, %xmm0
+; AVX-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; AVX-NEXT:    vpmovzxwd {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
+; AVX-NEXT:    vpmaddwd %xmm0, %xmm1, %xmm0
+; AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; AVX-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vmovd %xmm0, %eax
+; AVX-NEXT:    retq
+  %var0 = load i8, ptr %a, align 1
+  %arrayidx.1 = getelementptr inbounds i8, ptr %a, i64 %a_stride
+  %var1 = load i8, ptr %arrayidx.1, align 1
+  %var8 = insertelement <2 x i8> poison, i8 %var0, i64 0
+  %var9 = insertelement <2 x i8> %var8, i8 %var1, i64 1
+  %var16 = zext <2 x i8> %var9 to <2 x i32>
+  %var17 = load <2 x i16>, ptr %b, align 2
+  %var18 = sext <2 x i16> %var17 to <2 x i32>
+  %var19 = mul nsw <2 x i32> %var18, %var16
+  %var20 = tail call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> %var19)
+  ret i32 %var20
+}
+
+define i64 @dot_ext_v2i8_v2i64(ptr %a, i64 %a_stride, ptr %b) nounwind {
+; SSE2-LABEL: dot_ext_v2i8_v2i64:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    movzbl (%rdi), %eax
+; SSE2-NEXT:    movzbl (%rdi,%rsi), %ecx
+; SSE2-NEXT:    movd %eax, %xmm0
+; SSE2-NEXT:    pinsrw $4, %ecx, %xmm0
+; SSE2-NEXT:    movzwl (%rdx), %eax
+; SSE2-NEXT:    movd %eax, %xmm1
+; SSE2-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; SSE2-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,1,1,3]
+; SSE2-NEXT:    pxor %xmm2, %xmm2
+; SSE2-NEXT:    pcmpgtd %xmm1, %xmm2
+; SSE2-NEXT:    psrad $24, %xmm1
+; SSE2-NEXT:    pmuludq %xmm0, %xmm1
+; SSE2-NEXT:    pmuludq %xmm0, %xmm2
+; SSE2-NEXT:    psllq $32, %xmm2
+; SSE2-NEXT:    paddq %xmm1, %xmm2
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm2[2,3,2,3]
+; SSE2-NEXT:    paddq %xmm2, %xmm0
+; SSE2-NEXT:    movq %xmm0, %rax
+; SSE2-NEXT:    retq
+;
+; SSE4-LABEL: dot_ext_v2i8_v2i64:
+; SSE4:       # %bb.0:
+; SSE4-NEXT:    movzbl (%rdi), %eax
+; SSE4-NEXT:    movd %eax, %xmm0
+; SSE4-NEXT:    pinsrb $1, (%rdi,%rsi), %xmm0
+; SSE4-NEXT:    pmovzxbq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero
+; SSE4-NEXT:    pmovsxbq (%rdx), %xmm1
+; SSE4-NEXT:    pmuldq %xmm0, %xmm1
+; SSE4-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; SSE4-NEXT:    paddq %xmm1, %xmm0
+; SSE4-NEXT:    movq %xmm0, %rax
+; SSE4-NEXT:    retq
+;
+; AVX-LABEL: dot_ext_v2i8_v2i64:
+; AVX:       # %bb.0:
+; AVX-NEXT:    movzbl (%rdi), %eax
+; AVX-NEXT:    vmovd %eax, %xmm0
+; AVX-NEXT:    vpinsrb $1, (%rdi,%rsi), %xmm0, %xmm0
+; AVX-NEXT:    vpmovzxbq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero
+; AVX-NEXT:    vpmovsxbq (%rdx), %xmm1
+; AVX-NEXT:    vpmuldq %xmm0, %xmm1, %xmm0
+; AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; AVX-NEXT:    vpaddq %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vmovq %xmm0, %rax
+; AVX-NEXT:    retq
+  %var0 = load i8, ptr %a, align 1
+  %arrayidx.1 = getelementptr inbounds i8, ptr %a, i64 %a_stride
+  %var1 = load i8, ptr %arrayidx.1, align 1
+  %var8 = insertelement <2 x i8> poison, i8 %var0, i64 0
+  %var9 = insertelement <2 x i8> %var8, i8 %var1, i64 1
+  %var16 = zext <2 x i8> %var9 to <2 x i64>
+  %var17 = load <2 x i8>, ptr %b, align 2
+  %var18 = sext <2 x i8> %var17 to <2 x i64>
+  %var19 = mul nsw <2 x i64> %var18, %var16
+  %var20 = tail call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %var19)
+  ret i64 %var20
+}
+
+define i32 @dot_ext_v4i16_v4i32(ptr %a, i64 %a_stride, ptr %b) nounwind {
+; SSE2-LABEL: dot_ext_v4i16_v4i32:
+; SSE2:       # %bb.0: # %entry
+; SSE2-NEXT:    movzwl (%rdi), %eax
+; SSE2-NEXT:    movd %eax, %xmm0
+; SSE2-NEXT:    pinsrw $2, (%rdi,%rsi), %xmm0
+; SSE2-NEXT:    pinsrw $4, (%rdi,%rsi,2), %xmm0
+; SSE2-NEXT:    leaq (%rsi,%rsi,2), %rax
+; SSE2-NEXT:    movdqa %xmm0, %xmm1
+; SSE2-NEXT:    pinsrw $6, (%rdi,%rax), %xmm1
+; SSE2-NEXT:    movq {{.*#+}} xmm2 = mem[0],zero
+; SSE2-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3]
+; SSE2-NEXT:    psrad $16, %xmm2
+; SSE2-NEXT:    pmuludq %xmm2, %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
+; SSE2-NEXT:    pmuludq %xmm1, %xmm2
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; SSE2-NEXT:    paddd %xmm0, %xmm1
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
+; SSE2-NEXT:    paddd %xmm1, %xmm0
+; SSE2-NEXT:    movd %xmm0, %eax
+; SSE2-NEXT:    retq
+;
+; SSE4-LABEL: dot_ext_v4i16_v4i32:
+; SSE4:       # %bb.0: # %entry
+; SSE4-NEXT:    leaq (%rsi,%rsi,2), %rax
+; SSE4-NEXT:    movzwl (%rdi), %ecx
+; SSE4-NEXT:    movd %ecx, %xmm0
+; SSE4-NEXT:    pinsrw $1, (%rdi,%rsi), %xmm0
+; SSE4-NEXT:    pinsrw $2, (%rdi,%rsi,2), %xmm0
+; SSE4-NEXT:    pinsrw $3, (%rdi,%rax), %xmm0
+; SSE4-NEXT:    pmovsxwd (%rdx), %xmm1
+; SSE4-NEXT:    pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
+; SSE4-NEXT:    pmulld %xmm0, %xmm1
+; SSE4-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; SSE4-NEXT:    paddd %xmm1, %xmm0
+; SSE4-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; SSE4-NEXT:    paddd %xmm0, %xmm1
+; SSE4-NEXT:    movd %xmm1, %eax
+; SSE4-NEXT:    retq
+;
+; AVX2-LABEL: dot_ext_v4i16_v4i32:
+; AVX2:       # %bb.0: # %entry
+; AVX2-NEXT:    leaq (%rsi,%rsi,2), %rax
+; AVX2-NEXT:    movzwl (%rdi), %ecx
+; AVX2-NEXT:    vmovd %ecx, %xmm0
+; AVX2-NEXT:    vpinsrw $1, (%rdi,%rsi), %xmm0, %xmm0
+; AVX2-NEXT:    vpinsrw $2, (%rdi,%rsi,2), %xmm0, %xmm0
+; AVX2-NEXT:    vpinsrw $3, (%rdi,%rax), %xmm0, %xmm0
+; AVX2-NEXT:    vpmovsxwd (%rdx), %xmm1
+; AVX2-NEXT:    vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
+; AVX2-NEXT:    vpmulld %xmm0, %xmm1, %xmm0
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; AVX2-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; AVX2-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
+; AVX2-NEXT:    vmovd %xmm0, %eax
+; AVX2-NEXT:    retq
+;
+; AVX512-LABEL: dot_ext_v4i16_v4i32:
+; AVX512:       # %bb.0: # %entry
+; AVX512-NEXT:    leaq (%rsi,%rsi,2), %rax
+; AVX512-NEXT:    movzwl (%rdi), %ecx
+; AVX512-NEXT:    vmovd %ecx, %xmm0
+; AVX512-NEXT:    vpinsrw $1, (%rdi,%rsi), %xmm0, %xmm0
+; AVX512-NEXT:    vpinsrw $2, (%rdi,%rsi,2), %xmm0, %xmm0
+; AVX512-NEXT:    vpinsrw $3, (%rdi,%rax), %xmm0, %xmm0
+; AVX512-NEXT:    vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
+; AVX512-NEXT:    vpmovsxwd (%rdx), %xmm1
+; AVX512-NEXT:    vpmulld %xmm0, %xmm1, %xmm0
+; AVX512-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; AVX512-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
+; AVX512-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; AVX512-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
+; AVX512-NEXT:    vmovd %xmm0, %eax
+; AVX512-NEXT:    retq
+entry:
+  %var0 = load i16, ptr %a, align 1
+  %arrayidx.1 = getelementptr inbounds i8, ptr %a, i64 %a_stride
+  %var1 = load i16, ptr %arrayidx.1, align 1
+  %mul.2 = shl nsw i64 %a_stride, 1
+  %arrayidx.2 = getelementptr inbounds i8, ptr %a, i64 %mul.2
+  %var2 = load i16, ptr %arrayidx.2, align 1
+  %mul.3 = mul nsw i64 %a_stride, 3
+  %arrayidx.3 = getelementptr inbounds i8, ptr %a, i64 %mul.3
+  %var3 = load i16, ptr %arrayidx.3, align 1
+  %var8 = insertelement <4 x i16> poison, i16 %var0, i64 0
+  %var9 = insertelement <4 x i16> %var8, i16 %var1, i64 1
+  %var10 = insertelement <4 x i16> %var9, i16 %var2, i64 2
+  %var11 = insertelement <4 x i16> %var10, i16 %var3, i64 3
+  %var16 = zext <4 x i16> %var11 to <4 x i32>
+  %var17 = load <4 x i16>, ptr %b, align 2
+  %var18 = sext <4 x i16> %var17 to <4 x i32>
+  %var19 = mul nsw <4 x i32> %var18, %var16
+  %var20 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %var19)
+  ret i32 %var20
+}
+
+define i32 @dot_ext_v2i16_v2i32(ptr %a, i64 %a_stride, ptr %b) nounwind {
+; SSE2-LABEL: dot_ext_v2i16_v2i32:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    movzwl (%rdi), %eax
+; SSE2-NEXT:    movd %eax, %xmm0
+; SSE2-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE2-NEXT:    pshuflw {{.*#+}} xmm1 = xmm1[0,0,2,1,4,5,6,7]
+; SSE2-NEXT:    psrad $16, %xmm1
+; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
+; SSE2-NEXT:    pmuludq %xmm0, %xmm1
+; SSE2-NEXT:    pinsrw $2, (%rdi,%rsi), %xmm0
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; SSE2-NEXT:    pmuludq %xmm0, %xmm2
+; SSE2-NEXT:    paddd %xmm2, %xmm1
+; SSE2-NEXT:    movd %xmm1, %eax
+; SSE2-NEXT:    retq
+;
+; SSE4-LABEL: dot_ext_v2i16_v2i32:
+; SSE4:       # %bb.0:
+; SSE4-NEXT:    movzwl (%rdi), %eax
+; SSE4-NEXT:    movd %eax, %xmm0
+; SSE4-NEXT:    pinsrw $1, (%rdi,%rsi), %xmm0
+; SSE4-NEXT:    pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
+; SSE4-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE4-NEXT:    pmovsxwd %xmm1, %xmm1
+; SSE4-NEXT:    pmulld %xmm0, %xmm1
+; SSE4-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
+; SSE4-NEXT:    paddd %xmm1, %xmm0
+; SSE4-NEXT:    movd %xmm0, %eax
+; SSE4-NEXT:    retq
+;
+; AVX-LABEL: dot_ext_v2i16_v2i32:
+; AVX:       # %bb.0:
+; AVX-NEXT:    movzwl (%rdi), %eax
+; AVX-NEXT:    vmovd %eax, %xmm0
+; AVX-NEXT:    vpinsrw $1, (%rdi,%rsi), %xmm0, %xmm0
+; AVX-NEXT:    vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
+; AVX-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; AVX-NEXT:    vpmovsxwd %xmm1, %xmm1
+; AVX-NEXT:    vpmulld %xmm0, %xmm1, %xmm0
+; AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; AVX-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vmovd %xmm0, %eax
+; AVX-NEXT:    retq
+  %var0 = load i16, ptr %a, align 1
+  %arrayidx.1 = getelementptr inbounds i8, ptr %a, i64 %a_stride
+  %var1 = load i16, ptr %arrayidx.1, align 1
+  %var8 = insertelement <2 x i16> poison, i16 %var0, i64 0
+  %var9 = insertelement <2 x i16> %var8, i16 %var1, i64 1
+  %var16 = zext <2 x i16> %var9 to <2 x i32>
+  %var17 = load <2 x i16>, ptr %b, align 2
+  %var18 = sext <2 x i16> %var17 to <2 x i32>
+  %var19 = mul nsw <2 x i32> %var18, %var16
+  %var20 = tail call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> %var19)
+  ret i32 %var20
+}
+
+define i64 @dot_ext_v2i32_v2i64(ptr %a, i64 %a_stride, ptr %b) nounwind {
+; SSE2-LABEL: dot_ext_v2i32_v2i64:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; SSE2-NEXT:    pxor %xmm0, %xmm0
+; SSE2-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; SSE2-NEXT:    movq {{.*#+}} xmm2 = mem[0],zero
+; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[0,1,1,3]
+; SSE2-NEXT:    pcmpgtd %xmm2, %xmm0
+; SSE2-NEXT:    pmuludq %xmm1, %xmm0
+; SSE2-NEXT:    psllq $32, %xmm0
+; SSE2-NEXT:    pmuludq %xmm2, %xmm1
+; SSE2-NEXT:    paddq %xmm0, %xmm1
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; SSE2-NEXT:    paddq %xmm1, %xmm0
+; SSE2-NEXT:    movq %xmm0, %rax
+; SSE2-NEXT:    retq
+;
+; SSE4-LABEL: dot_ext_v2i32_v2i64:
+; SSE4:       # %bb.0:
+; SSE4-NEXT:    movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE4-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE4-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; SSE4-NEXT:    pmovsxdq (%rdx), %xmm0
+; SSE4-NEXT:    movdqa %xmm0, %xmm2
+; SSE4-NEXT:    pmuludq %xmm1, %xmm2
+; SSE4-NEXT:    psrlq $32, %xmm0
+; SSE4-NEXT:    pmuludq %xmm1, %xmm0
+; SSE4-NEXT:    psllq $32, %xmm0
+; SSE4-NEXT:    paddq %xmm2, %xmm0
+; SSE4-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; SSE4-NEXT:    paddq %xmm0, %xmm1
+; SSE4-NEXT:    movq %xmm1, %rax
+; SSE4-NEXT:    retq
+;
+; AVX2-LABEL: dot_ext_v2i32_v2i64:
+; AVX2:       # %bb.0:
+; AVX2-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; AVX2-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; AVX2-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
+; AVX2-NEXT:    vpmovsxdq (%rdx), %xmm1
+; AVX2-NEXT:    vpmuludq %xmm0, %xmm1, %xmm2
+; AVX2-NEXT:    vpsrlq $32, %xmm1, %xmm1
+; AVX2-NEXT:    vpmuludq %xmm0, %xmm1, %xmm0
+; AVX2-NEXT:    vpsllq $32, %xmm0, %xmm0
+; AVX2-NEXT:    vpaddq %xmm0, %xmm2, %xmm0
+; AVX2-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; AVX2-NEXT:    vpaddq %xmm1, %xmm0, %xmm0
+; AVX2-NEXT:    vmovq %xmm0, %rax
+; AVX2-NEXT:    retq
+;
+; AVX512-LABEL: dot_ext_v2i32_v2i64:
+; AVX512:       # %bb.0:
+; AVX512-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; AVX512-NEXT:    vpinsrd $1, (%rdi,%rsi), %xmm0, %xmm0
+; AVX512-NEXT:    vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
+; AVX512-NEXT:    vpmovsxdq (%rdx), %xmm1
+; AVX512-NEXT:    vpmullq %xmm0, %xmm1, %xmm0
+; AVX512-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; AVX512-NEXT:    vpaddq %xmm1, %xmm0, %xmm0
+; AVX512-NEXT:    vmovq %xmm0, %rax
+; AVX512-NEXT:    retq
+  %var0 = load i32, ptr %a, align 1
+  %arrayidx.1 = getelementptr inbounds i8, ptr %a, i64 %a_stride
+  %var1 = load i32, ptr %arrayidx.1, align 1
+  %var8 = insertelement <2 x i32> poison, i32 %var0, i64 0
+  %var9 = insertelement <2 x i32> %var8, i32 %var1, i64 1
+  %var16 = zext <2 x i32> %var9 to <2 x i64>
+  %var17 = load <2 x i32>, ptr %b, align 2
+  %var18 = sext <2 x i32> %var17 to <2 x i64>
+  %var19 = mul nsw <2 x i64> %var18, %var16
+  %var20 = tail call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %var19)
+  ret i64 %var20
+}
+
+declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
+declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
+declare i32 @llvm.vector.reduce.add.v2i32(<2 x i32>)
+declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64>)
diff --git a/llvm/test/CodeGen/X86/extractelement-load.ll b/llvm/test/CodeGen/X86/extractelement-load.ll
index 022b25a241533..ce68eebd5b752 100644
--- a/llvm/test/CodeGen/X86/extractelement-load.ll
+++ b/llvm/test/CodeGen/X86/extractelement-load.ll
@@ -528,3 +528,73 @@ define i32 @main() nounwind {
   %r = add i32 %e1, %e2
   ret i32 %r
 }
+
+; A test for incorrect combine for single value extraction from VBROADCAST_LOAD.
+; Wrong combine makes the second call (%t8) use the stored result in the
+; previous instructions instead of %t4.
+declare <2 x float> @ccosf(<2 x float>)
+define dso_local <2 x float> @multiuse_of_single_value_from_vbroadcast_load(ptr %p, ptr %arr) nounwind {
+; X86-SSE2-LABEL: multiuse_of_single_value_from_vbroadcast_load:
+; X86-SSE2:       # %bb.0:
+; X86-SSE2-NEXT:    pushl %esi
+; X86-SSE2-NEXT:    subl $16, %esp
+; X86-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; X86-SSE2-NEXT:    movups 24(%esi), %xmm0
+; X86-SSE2-NEXT:    movups %xmm0, (%esp) # 16-byte Spill
+; X86-SSE2-NEXT:    movhps %xmm0, (%eax)
+; X86-SSE2-NEXT:    movaps 32(%esi), %xmm0
+; X86-SSE2-NEXT:    calll ccosf@PLT
+; X86-SSE2-NEXT:    movlps %xmm0, 32(%esi)
+; X86-SSE2-NEXT:    movups (%esp), %xmm0 # 16-byte Reload
+; X86-SSE2-NEXT:    movhlps {{.*#+}} xmm0 = xmm0[1,1]
+; X86-SSE2-NEXT:    calll ccosf@PLT
+; X86-SSE2-NEXT:    addl $16, %esp
+; X86-SSE2-NEXT:    popl %esi
+; X86-SSE2-NEXT:    retl
+;
+; X64-SSSE3-LABEL: multiuse_of_single_value_from_vbroadcast_load:
+; X64-SSSE3:       # %bb.0:
+; X64-SSSE3-NEXT:    pushq %rbx
+; X64-SSSE3-NEXT:    subq $16, %rsp
+; X64-SSSE3-NEXT:    movq %rsi, %rbx
+; X64-SSSE3-NEXT:    movddup {{.*#+}} xmm0 = mem[0,0]
+; X64-SSSE3-NEXT:    movapd %xmm0, (%rsp) # 16-byte Spill
+; X64-SSSE3-NEXT:    movlpd %xmm0, (%rdi)
+; X64-SSSE3-NEXT:    movaps 32(%rsi), %xmm0
+; X64-SSSE3-NEXT:    callq ccosf@PLT
+; X64-SSSE3-NEXT:    movlps %xmm0, 32(%rbx)
+; X64-SSSE3-NEXT:    movaps (%rsp), %xmm0 # 16-byte Reload
+; X64-SSSE3-NEXT:    callq ccosf@PLT
+; X64-SSSE3-NEXT:    addq $16, %rsp
+; X64-SSSE3-NEXT:    popq %rbx
+; X64-SSSE3-NEXT:    retq
+;
+; X64-AVX-LABEL: multiuse_of_single_value_from_vbroadcast_load:
+; X64-AVX:       # %bb.0:
+; X64-AVX-NEXT:    pushq %rbx
+; X64-AVX-NEXT:    subq $16, %rsp
+; X64-AVX-NEXT:    movq %rsi, %rbx
+; X64-AVX-NEXT:    vmovddup {{.*#+}} xmm0 = mem[0,0]
+; X64-AVX-NEXT:    vmovaps %xmm0, (%rsp) # 16-byte Spill
+; X64-AVX-NEXT:    vmovlps %xmm0, (%rdi)
+; X64-AVX-NEXT:    vmovaps 32(%rsi), %xmm0
+; X64-AVX-NEXT:    callq ccosf@PLT
+; X64-AVX-NEXT:    vmovlps %xmm0, 32(%rbx)
+; X64-AVX-NEXT:    vmovaps (%rsp), %xmm0 # 16-byte Reload
+; X64-AVX-NEXT:    callq ccosf@PLT
+; X64-AVX-NEXT:    addq $16, %rsp
+; X64-AVX-NEXT:    popq %rbx
+; X64-AVX-NEXT:    retq
+  %p1 = getelementptr [5 x <2 x float>], ptr %arr, i64 0, i64 3
+  %p2 = getelementptr inbounds [5 x <2 x float>], ptr %arr, i64 0, i64 4, i32 0
+  %t3 = load <4 x float>, ptr %p1, align 8
+  %t4 = shufflevector <4 x float> %t3, <4 x float> poison, <2 x i32> <i32 2, i32 3>
+  store <2 x float> %t4, ptr %p, align 16
+  %t5 = load <4 x float>, ptr %p2, align 32
+  %t6 = shufflevector <4 x float> %t5, <4 x float> poison, <2 x i32> <i32 0, i32 1>
+  %t7 = call <2 x float> @ccosf(<2 x float> %t6)
+  store <2 x float> %t7, ptr %p2, align 32
+  %t8 = call <2 x float> @ccosf(<2 x float> %t4)
+  ret <2 x float> %t8
+}
diff --git a/llvm/test/CodeGen/X86/ispow2.ll b/llvm/test/CodeGen/X86/ispow2.ll
index 649d257b28d76..badfd1af940ca 100644
--- a/llvm/test/CodeGen/X86/ispow2.ll
+++ b/llvm/test/CodeGen/X86/ispow2.ll
@@ -72,11 +72,11 @@ define <4 x i1> @is_pow2_non_zero_4xv64(<4 x i64> %xin) {
 ; CHECK-NOBMI-NEXT:    pcmpeqd %xmm2, %xmm2
 ; CHECK-NOBMI-NEXT:    movdqa %xmm1, %xmm3
 ; CHECK-NOBMI-NEXT:    paddq %xmm2, %xmm3
+; CHECK-NOBMI-NEXT:    paddq %xmm0, %xmm2
+; CHECK-NOBMI-NEXT:    pand %xmm2, %xmm0
 ; CHECK-NOBMI-NEXT:    pand %xmm1, %xmm3
 ; CHECK-NOBMI-NEXT:    pxor %xmm1, %xmm1
 ; CHECK-NOBMI-NEXT:    pcmpeqd %xmm1, %xmm3
-; CHECK-NOBMI-NEXT:    paddq %xmm0, %xmm2
-; CHECK-NOBMI-NEXT:    pand %xmm2, %xmm0
 ; CHECK-NOBMI-NEXT:    pcmpeqd %xmm1, %xmm0
 ; CHECK-NOBMI-NEXT:    movdqa %xmm0, %xmm1
 ; CHECK-NOBMI-NEXT:    shufps {{.*#+}} xmm1 = xmm1[1,3],xmm3[1,3]
@@ -122,12 +122,12 @@ define <4 x i1> @neither_pow2_non_zero_4xv64(<4 x i64> %xin) {
 ; CHECK-NOBMI-NEXT:    pcmpeqd %xmm2, %xmm2
 ; CHECK-NOBMI-NEXT:    movdqa %xmm1, %xmm3
 ; CHECK-NOBMI-NEXT:    paddq %xmm2, %xmm3
-; CHECK-NOBMI-NEXT:    pand %xmm1, %xmm3
-; CHECK-NOBMI-NEXT:    pxor %xmm1, %xmm1
-; CHECK-NOBMI-NEXT:    pcmpeqd %xmm1, %xmm3
 ; CHECK-NOBMI-NEXT:    movdqa %xmm0, %xmm4
 ; CHECK-NOBMI-NEXT:    paddq %xmm2, %xmm4
 ; CHECK-NOBMI-NEXT:    pand %xmm4, %xmm0
+; CHECK-NOBMI-NEXT:    pand %xmm1, %xmm3
+; CHECK-NOBMI-NEXT:    pxor %xmm1, %xmm1
+; CHECK-NOBMI-NEXT:    pcmpeqd %xmm1, %xmm3
 ; CHECK-NOBMI-NEXT:    pcmpeqd %xmm1, %xmm0
 ; CHECK-NOBMI-NEXT:    movdqa %xmm0, %xmm1
 ; CHECK-NOBMI-NEXT:    shufps {{.*#+}} xmm1 = xmm1[1,3],xmm3[1,3]
@@ -170,27 +170,27 @@ define <4 x i1> @neither_pow2_non_zero_4xv64_x_maybe_z(<4 x i64> %x) {
 ; CHECK-NOBMI-LABEL: neither_pow2_non_zero_4xv64_x_maybe_z:
 ; CHECK-NOBMI:       # %bb.0:
 ; CHECK-NOBMI-NEXT:    pcmpeqd %xmm2, %xmm2
-; CHECK-NOBMI-NEXT:    movdqa %xmm1, %xmm3
+; CHECK-NOBMI-NEXT:    movdqa %xmm0, %xmm3
 ; CHECK-NOBMI-NEXT:    paddq %xmm2, %xmm3
-; CHECK-NOBMI-NEXT:    movdqa {{.*#+}} xmm4 = [9223372039002259456,9223372039002259456]
-; CHECK-NOBMI-NEXT:    pxor %xmm4, %xmm3
-; CHECK-NOBMI-NEXT:    pxor %xmm3, %xmm1
-; CHECK-NOBMI-NEXT:    movdqa %xmm1, %xmm5
+; CHECK-NOBMI-NEXT:    movdqa %xmm1, %xmm4
+; CHECK-NOBMI-NEXT:    paddq %xmm2, %xmm4
+; CHECK-NOBMI-NEXT:    movdqa {{.*#+}} xmm5 = [9223372039002259456,9223372039002259456]
+; CHECK-NOBMI-NEXT:    pxor %xmm5, %xmm4
+; CHECK-NOBMI-NEXT:    pxor %xmm4, %xmm1
+; CHECK-NOBMI-NEXT:    movdqa %xmm1, %xmm6
+; CHECK-NOBMI-NEXT:    pcmpgtd %xmm4, %xmm6
+; CHECK-NOBMI-NEXT:    pxor %xmm5, %xmm3
+; CHECK-NOBMI-NEXT:    pxor %xmm3, %xmm0
+; CHECK-NOBMI-NEXT:    movdqa %xmm0, %xmm5
 ; CHECK-NOBMI-NEXT:    pcmpgtd %xmm3, %xmm5
-; CHECK-NOBMI-NEXT:    movdqa %xmm0, %xmm6
-; CHECK-NOBMI-NEXT:    paddq %xmm2, %xmm6
-; CHECK-NOBMI-NEXT:    pxor %xmm4, %xmm6
-; CHECK-NOBMI-NEXT:    pxor %xmm6, %xmm0
-; CHECK-NOBMI-NEXT:    movdqa %xmm0, %xmm4
-; CHECK-NOBMI-NEXT:    pcmpgtd %xmm6, %xmm4
-; CHECK-NOBMI-NEXT:    movdqa %xmm4, %xmm7
-; CHECK-NOBMI-NEXT:    shufps {{.*#+}} xmm7 = xmm7[0,2],xmm5[0,2]
-; CHECK-NOBMI-NEXT:    pcmpeqd %xmm3, %xmm1
-; CHECK-NOBMI-NEXT:    pcmpeqd %xmm6, %xmm0
+; CHECK-NOBMI-NEXT:    movdqa %xmm5, %xmm7
+; CHECK-NOBMI-NEXT:    shufps {{.*#+}} xmm7 = xmm7[0,2],xmm6[0,2]
+; CHECK-NOBMI-NEXT:    pcmpeqd %xmm4, %xmm1
+; CHECK-NOBMI-NEXT:    pcmpeqd %xmm3, %xmm0
 ; CHECK-NOBMI-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[1,3]
 ; CHECK-NOBMI-NEXT:    andps %xmm7, %xmm0
-; CHECK-NOBMI-NEXT:    shufps {{.*#+}} xmm4 = xmm4[1,3],xmm5[1,3]
-; CHECK-NOBMI-NEXT:    orps %xmm4, %xmm0
+; CHECK-NOBMI-NEXT:    shufps {{.*#+}} xmm5 = xmm5[1,3],xmm6[1,3]
+; CHECK-NOBMI-NEXT:    orps %xmm5, %xmm0
 ; CHECK-NOBMI-NEXT:    xorps %xmm2, %xmm0
 ; CHECK-NOBMI-NEXT:    retq
 ;
diff --git a/llvm/test/CodeGen/X86/pr40891.ll b/llvm/test/CodeGen/X86/pr40891.ll
index 24f644683c286..8ff0846e953cd 100644
--- a/llvm/test/CodeGen/X86/pr40891.ll
+++ b/llvm/test/CodeGen/X86/pr40891.ll
@@ -1,17 +1,29 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx2 | FileCheck %s
+; RUN: llc < %s -mtriple=i686-- -mattr=avx2 | FileCheck %s --check-prefixes=X86
+; RUN: llc < %s -mtriple=x86_64-- -mattr=avx2 | FileCheck %s --check-prefixes=X64
 
 ; Make sure this sequence doesn't hang in DAG combine.
 
 define <8 x i32> @foo(<8 x i64> %x, <4 x i64> %y) {
-; CHECK-LABEL: foo:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vandps %ymm2, %ymm0, %ymm0
-; CHECK-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1
-; CHECK-NEXT:    vperm2f128 {{.*#+}} ymm2 = ymm0[2,3],ymm1[2,3]
-; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; CHECK-NEXT:    vshufps {{.*#+}} ymm0 = ymm0[0,2],ymm2[0,2],ymm0[4,6],ymm2[4,6]
-; CHECK-NEXT:    retl
+; X86-LABEL: foo:
+; X86:       # %bb.0:
+; X86-NEXT:    vandps %ymm2, %ymm0, %ymm0
+; X86-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1
+; X86-NEXT:    vperm2f128 {{.*#+}} ymm2 = ymm0[2,3],ymm1[2,3]
+; X86-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; X86-NEXT:    vshufps {{.*#+}} ymm0 = ymm0[0,2],ymm2[0,2],ymm0[4,6],ymm2[4,6]
+; X86-NEXT:    retl
+;
+; X64-LABEL: foo:
+; X64:       # %bb.0:
+; X64-NEXT:    vandps %ymm2, %ymm0, %ymm0
+; X64-NEXT:    vextractf128 $1, %ymm0, %xmm2
+; X64-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[0,2]
+; X64-NEXT:    vextractf128 $1, %ymm1, %xmm2
+; X64-NEXT:    vshufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2]
+; X64-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; X64-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; X64-NEXT:    retq
   %a = shufflevector <4 x i64> %y, <4 x i64> <i64 12345, i64 67890, i64 13579, i64 24680>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   %b = and <8 x i64> %x, %a
   %c = trunc <8 x i64> %b to <8 x i32>
diff --git a/llvm/test/CodeGen/X86/pr94829.ll b/llvm/test/CodeGen/X86/pr94829.ll
new file mode 100644
index 0000000000000..b858c636cebd8
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr94829.ll
@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=x86_64 -o - %s | FileCheck %s
+
+define i64 @test(i64 %x, i64 %y, i64 %a, i64 %b) {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    testq %rsi, %rsi
+; CHECK-NEXT:    jg .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    movq %rcx, %rax
+; CHECK-NEXT:    leaq -1(%rdi), %rcx
+; CHECK-NEXT:    andq %rdi, %rcx
+; CHECK-NEXT:    jne .LBB0_2
+; CHECK-NEXT:  # %bb.3: # %if.end
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB0_2: # %if.then
+; CHECK-NEXT:    movq %rdx, %rax
+; CHECK-NEXT:    retq
+entry:
+  %ctpop = call i64 @llvm.ctpop.i64(i64 %x)
+  %cmp1 = icmp ugt i64 %ctpop, 1
+  %cmp2 = icmp sgt i64 %y, 0
+  %cmp = or i1 %cmp2, %cmp1
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+  br label %if.end
+
+if.end:
+  %res = phi i64 [ %a, %if.then ], [ %b, %entry ]
+  ret i64 %res
+}
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll b/llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
index 93a84e30412d6..c8b95cd71c5d1 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
@@ -84,7 +84,7 @@ define void @load_i64_stride3_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
 ;
 ; AVX512-LABEL: load_i64_stride3_vf2:
 ; AVX512:       # %bb.0:
-; AVX512-NEXT:    vpermpd {{.*#+}} zmm0 = mem[0,3,2,3,4,7,6,7]
+; AVX512-NEXT:    vpermpd {{.*#+}} ymm0 = mem[0,3,2,3]
 ; AVX512-NEXT:    vmovdqa 32(%rdi), %xmm1
 ; AVX512-NEXT:    vpalignr {{.*#+}} xmm2 = mem[8,9,10,11,12,13,14,15],xmm1[0,1,2,3,4,5,6,7]
 ; AVX512-NEXT:    vpblendd {{.*#+}} xmm1 = mem[0,1],xmm1[2,3]
@@ -97,9 +97,8 @@ define void @load_i64_stride3_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
 ; AVX512-FCP-LABEL: load_i64_stride3_vf2:
 ; AVX512-FCP:       # %bb.0:
 ; AVX512-FCP-NEXT:    vpmovsxbq {{.*#+}} xmm0 = [1,4]
-; AVX512-FCP-NEXT:    vmovaps (%rdi), %zmm1
-; AVX512-FCP-NEXT:    vpermpd %zmm1, %zmm0, %zmm0
-; AVX512-FCP-NEXT:    vpermpd {{.*#+}} zmm1 = zmm1[0,3,2,3,4,7,6,7]
+; AVX512-FCP-NEXT:    vpermpd (%rdi), %zmm0, %zmm0
+; AVX512-FCP-NEXT:    vpermpd {{.*#+}} ymm1 = mem[0,3,2,3]
 ; AVX512-FCP-NEXT:    vmovaps 16(%rdi), %xmm2
 ; AVX512-FCP-NEXT:    vblendps {{.*#+}} xmm2 = xmm2[0,1],mem[2,3]
 ; AVX512-FCP-NEXT:    vmovaps %xmm1, (%rsi)
@@ -110,7 +109,7 @@ define void @load_i64_stride3_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
 ;
 ; AVX512DQ-LABEL: load_i64_stride3_vf2:
 ; AVX512DQ:       # %bb.0:
-; AVX512DQ-NEXT:    vpermpd {{.*#+}} zmm0 = mem[0,3,2,3,4,7,6,7]
+; AVX512DQ-NEXT:    vpermpd {{.*#+}} ymm0 = mem[0,3,2,3]
 ; AVX512DQ-NEXT:    vmovdqa 32(%rdi), %xmm1
 ; AVX512DQ-NEXT:    vpalignr {{.*#+}} xmm2 = mem[8,9,10,11,12,13,14,15],xmm1[0,1,2,3,4,5,6,7]
 ; AVX512DQ-NEXT:    vpblendd {{.*#+}} xmm1 = mem[0,1],xmm1[2,3]
@@ -123,9 +122,8 @@ define void @load_i64_stride3_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
 ; AVX512DQ-FCP-LABEL: load_i64_stride3_vf2:
 ; AVX512DQ-FCP:       # %bb.0:
 ; AVX512DQ-FCP-NEXT:    vpmovsxbq {{.*#+}} xmm0 = [1,4]
-; AVX512DQ-FCP-NEXT:    vmovaps (%rdi), %zmm1
-; AVX512DQ-FCP-NEXT:    vpermpd %zmm1, %zmm0, %zmm0
-; AVX512DQ-FCP-NEXT:    vpermpd {{.*#+}} zmm1 = zmm1[0,3,2,3,4,7,6,7]
+; AVX512DQ-FCP-NEXT:    vpermpd (%rdi), %zmm0, %zmm0
+; AVX512DQ-FCP-NEXT:    vpermpd {{.*#+}} ymm1 = mem[0,3,2,3]
 ; AVX512DQ-FCP-NEXT:    vmovaps 16(%rdi), %xmm2
 ; AVX512DQ-FCP-NEXT:    vblendps {{.*#+}} xmm2 = xmm2[0,1],mem[2,3]
 ; AVX512DQ-FCP-NEXT:    vmovaps %xmm1, (%rsi)
@@ -136,7 +134,7 @@ define void @load_i64_stride3_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
 ;
 ; AVX512BW-LABEL: load_i64_stride3_vf2:
 ; AVX512BW:       # %bb.0:
-; AVX512BW-NEXT:    vpermpd {{.*#+}} zmm0 = mem[0,3,2,3,4,7,6,7]
+; AVX512BW-NEXT:    vpermpd {{.*#+}} ymm0 = mem[0,3,2,3]
 ; AVX512BW-NEXT:    vmovdqa 32(%rdi), %xmm1
 ; AVX512BW-NEXT:    vpalignr {{.*#+}} xmm2 = mem[8,9,10,11,12,13,14,15],xmm1[0,1,2,3,4,5,6,7]
 ; AVX512BW-NEXT:    vpblendd {{.*#+}} xmm1 = mem[0,1],xmm1[2,3]
@@ -149,9 +147,8 @@ define void @load_i64_stride3_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
 ; AVX512BW-FCP-LABEL: load_i64_stride3_vf2:
 ; AVX512BW-FCP:       # %bb.0:
 ; AVX512BW-FCP-NEXT:    vpmovsxbq {{.*#+}} xmm0 = [1,4]
-; AVX512BW-FCP-NEXT:    vmovaps (%rdi), %zmm1
-; AVX512BW-FCP-NEXT:    vpermpd %zmm1, %zmm0, %zmm0
-; AVX512BW-FCP-NEXT:    vpermpd {{.*#+}} zmm1 = zmm1[0,3,2,3,4,7,6,7]
+; AVX512BW-FCP-NEXT:    vpermpd (%rdi), %zmm0, %zmm0
+; AVX512BW-FCP-NEXT:    vpermpd {{.*#+}} ymm1 = mem[0,3,2,3]
 ; AVX512BW-FCP-NEXT:    vmovaps 16(%rdi), %xmm2
 ; AVX512BW-FCP-NEXT:    vblendps {{.*#+}} xmm2 = xmm2[0,1],mem[2,3]
 ; AVX512BW-FCP-NEXT:    vmovaps %xmm1, (%rsi)
@@ -162,7 +159,7 @@ define void @load_i64_stride3_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
 ;
 ; AVX512DQ-BW-LABEL: load_i64_stride3_vf2:
 ; AVX512DQ-BW:       # %bb.0:
-; AVX512DQ-BW-NEXT:    vpermpd {{.*#+}} zmm0 = mem[0,3,2,3,4,7,6,7]
+; AVX512DQ-BW-NEXT:    vpermpd {{.*#+}} ymm0 = mem[0,3,2,3]
 ; AVX512DQ-BW-NEXT:    vmovdqa 32(%rdi), %xmm1
 ; AVX512DQ-BW-NEXT:    vpalignr {{.*#+}} xmm2 = mem[8,9,10,11,12,13,14,15],xmm1[0,1,2,3,4,5,6,7]
 ; AVX512DQ-BW-NEXT:    vpblendd {{.*#+}} xmm1 = mem[0,1],xmm1[2,3]
@@ -175,9 +172,8 @@ define void @load_i64_stride3_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
 ; AVX512DQ-BW-FCP-LABEL: load_i64_stride3_vf2:
 ; AVX512DQ-BW-FCP:       # %bb.0:
 ; AVX512DQ-BW-FCP-NEXT:    vpmovsxbq {{.*#+}} xmm0 = [1,4]
-; AVX512DQ-BW-FCP-NEXT:    vmovaps (%rdi), %zmm1
-; AVX512DQ-BW-FCP-NEXT:    vpermpd %zmm1, %zmm0, %zmm0
-; AVX512DQ-BW-FCP-NEXT:    vpermpd {{.*#+}} zmm1 = zmm1[0,3,2,3,4,7,6,7]
+; AVX512DQ-BW-FCP-NEXT:    vpermpd (%rdi), %zmm0, %zmm0
+; AVX512DQ-BW-FCP-NEXT:    vpermpd {{.*#+}} ymm1 = mem[0,3,2,3]
 ; AVX512DQ-BW-FCP-NEXT:    vmovaps 16(%rdi), %xmm2
 ; AVX512DQ-BW-FCP-NEXT:    vblendps {{.*#+}} xmm2 = xmm2[0,1],mem[2,3]
 ; AVX512DQ-BW-FCP-NEXT:    vmovaps %xmm1, (%rsi)
diff --git a/llvm/test/CodeGen/X86/vector-popcnt-128.ll b/llvm/test/CodeGen/X86/vector-popcnt-128.ll
index 741d70a369022..c1d30b6d5a995 100644
--- a/llvm/test/CodeGen/X86/vector-popcnt-128.ll
+++ b/llvm/test/CodeGen/X86/vector-popcnt-128.ll
@@ -803,11 +803,10 @@ define <2 x i64> @eq_1_v2i64(<2 x i64> %0) {
 ; BITALG-LABEL: eq_1_v2i64:
 ; BITALG:       # %bb.0:
 ; BITALG-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
-; BITALG-NEXT:    vpaddq %xmm1, %xmm0, %xmm1
-; BITALG-NEXT:    vpxor %xmm1, %xmm0, %xmm0
-; BITALG-NEXT:    vpminuq %xmm1, %xmm0, %xmm1
-; BITALG-NEXT:    vpcmpeqq %xmm1, %xmm0, %xmm0
-; BITALG-NEXT:    vpternlogq {{.*#+}} xmm0 = ~xmm0
+; BITALG-NEXT:    vpaddq %xmm1, %xmm0, %xmm2
+; BITALG-NEXT:    vpxor %xmm2, %xmm0, %xmm0
+; BITALG-NEXT:    vpcmpnleuq %xmm2, %xmm0, %k1
+; BITALG-NEXT:    vmovdqa64 %xmm1, %xmm0 {%k1} {z}
 ; BITALG-NEXT:    retq
   %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
   %3 = icmp eq <2 x i64> %2, <i64 1, i64 1>
@@ -883,10 +882,10 @@ define <2 x i64> @ne_1_v2i64(<2 x i64> %0) {
 ; BITALG-LABEL: ne_1_v2i64:
 ; BITALG:       # %bb.0:
 ; BITALG-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
-; BITALG-NEXT:    vpaddq %xmm1, %xmm0, %xmm1
-; BITALG-NEXT:    vpxor %xmm1, %xmm0, %xmm0
-; BITALG-NEXT:    vpminuq %xmm1, %xmm0, %xmm1
-; BITALG-NEXT:    vpcmpeqq %xmm1, %xmm0, %xmm0
+; BITALG-NEXT:    vpaddq %xmm1, %xmm0, %xmm2
+; BITALG-NEXT:    vpxor %xmm2, %xmm0, %xmm0
+; BITALG-NEXT:    vpcmpleuq %xmm2, %xmm0, %k1
+; BITALG-NEXT:    vmovdqa64 %xmm1, %xmm0 {%k1} {z}
 ; BITALG-NEXT:    retq
   %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
   %3 = icmp ne <2 x i64> %2, <i64 1, i64 1>
@@ -982,11 +981,10 @@ define <4 x i32> @eq_1_v4i32(<4 x i32> %0) {
 ; BITALG-LABEL: eq_1_v4i32:
 ; BITALG:       # %bb.0:
 ; BITALG-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
-; BITALG-NEXT:    vpaddd %xmm1, %xmm0, %xmm1
-; BITALG-NEXT:    vpxor %xmm1, %xmm0, %xmm0
-; BITALG-NEXT:    vpminud %xmm1, %xmm0, %xmm1
-; BITALG-NEXT:    vpcmpeqd %xmm1, %xmm0, %xmm0
-; BITALG-NEXT:    vpternlogq {{.*#+}} xmm0 = ~xmm0
+; BITALG-NEXT:    vpaddd %xmm1, %xmm0, %xmm2
+; BITALG-NEXT:    vpxor %xmm2, %xmm0, %xmm0
+; BITALG-NEXT:    vpcmpnleud %xmm2, %xmm0, %k1
+; BITALG-NEXT:    vmovdqa32 %xmm1, %xmm0 {%k1} {z}
 ; BITALG-NEXT:    retq
   %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
   %3 = icmp eq <4 x i32> %2, <i32 1, i32 1, i32 1, i32 1>
@@ -1085,10 +1083,10 @@ define <4 x i32> @ne_1_v4i32(<4 x i32> %0) {
 ; BITALG-LABEL: ne_1_v4i32:
 ; BITALG:       # %bb.0:
 ; BITALG-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
-; BITALG-NEXT:    vpaddd %xmm1, %xmm0, %xmm1
-; BITALG-NEXT:    vpxor %xmm1, %xmm0, %xmm0
-; BITALG-NEXT:    vpminud %xmm1, %xmm0, %xmm1
-; BITALG-NEXT:    vpcmpeqd %xmm1, %xmm0, %xmm0
+; BITALG-NEXT:    vpaddd %xmm1, %xmm0, %xmm2
+; BITALG-NEXT:    vpxor %xmm2, %xmm0, %xmm0
+; BITALG-NEXT:    vpcmpleud %xmm2, %xmm0, %k1
+; BITALG-NEXT:    vmovdqa32 %xmm1, %xmm0 {%k1} {z}
 ; BITALG-NEXT:    retq
   %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
   %3 = icmp ne <4 x i32> %2, <i32 1, i32 1, i32 1, i32 1>
diff --git a/llvm/test/CodeGen/X86/vector-popcnt-256-ult-ugt.ll b/llvm/test/CodeGen/X86/vector-popcnt-256-ult-ugt.ll
index f72ad6d70522f..487f9a5d326cf 100644
--- a/llvm/test/CodeGen/X86/vector-popcnt-256-ult-ugt.ll
+++ b/llvm/test/CodeGen/X86/vector-popcnt-256-ult-ugt.ll
@@ -10,18 +10,18 @@
 define <32 x i8> @ugt_1_v32i8(<32 x i8> %0) {
 ; AVX1-LABEL: ugt_1_v32i8:
 ; AVX1:       # %bb.0:
-; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; AVX1-NEXT:    vpaddb %xmm2, %xmm1, %xmm3
-; AVX1-NEXT:    vpand %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpxor %xmm3, %xmm3, %xmm3
-; AVX1-NEXT:    vpcmpeqb %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpxor %xmm2, %xmm1, %xmm1
-; AVX1-NEXT:    vpaddb %xmm2, %xmm0, %xmm4
-; AVX1-NEXT:    vpand %xmm4, %xmm0, %xmm0
-; AVX1-NEXT:    vpcmpeqb %xmm3, %xmm0, %xmm0
-; AVX1-NEXT:    vpxor %xmm2, %xmm0, %xmm0
-; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vpaddb %xmm1, %xmm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpaddb %xmm1, %xmm3, %xmm4
+; AVX1-NEXT:    vpand %xmm4, %xmm3, %xmm3
+; AVX1-NEXT:    vpxor %xmm4, %xmm4, %xmm4
+; AVX1-NEXT:    vpcmpeqb %xmm4, %xmm3, %xmm3
+; AVX1-NEXT:    vpxor %xmm1, %xmm3, %xmm3
+; AVX1-NEXT:    vpand %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vpcmpeqb %xmm4, %xmm0, %xmm0
+; AVX1-NEXT:    vpxor %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: ugt_1_v32i8:
@@ -76,13 +76,13 @@ define <32 x i8> @ugt_1_v32i8(<32 x i8> %0) {
 define <32 x i8> @ult_2_v32i8(<32 x i8> %0) {
 ; AVX1-LABEL: ult_2_v32i8:
 ; AVX1:       # %bb.0:
-; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; AVX1-NEXT:    vpaddb %xmm2, %xmm1, %xmm3
-; AVX1-NEXT:    vpand %xmm3, %xmm1, %xmm1
+; AVX1-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vpaddb %xmm1, %xmm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpaddb %xmm1, %xmm3, %xmm1
+; AVX1-NEXT:    vpand %xmm1, %xmm3, %xmm1
 ; AVX1-NEXT:    vpxor %xmm3, %xmm3, %xmm3
 ; AVX1-NEXT:    vpcmpeqb %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpaddb %xmm2, %xmm0, %xmm2
 ; AVX1-NEXT:    vpand %xmm2, %xmm0, %xmm0
 ; AVX1-NEXT:    vpcmpeqb %xmm3, %xmm0, %xmm0
 ; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
@@ -1003,18 +1003,18 @@ define <32 x i8> @ult_7_v32i8(<32 x i8> %0) {
 define <16 x i16> @ugt_1_v16i16(<16 x i16> %0) {
 ; AVX1-LABEL: ugt_1_v16i16:
 ; AVX1:       # %bb.0:
-; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; AVX1-NEXT:    vpaddw %xmm2, %xmm1, %xmm3
-; AVX1-NEXT:    vpand %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpxor %xmm3, %xmm3, %xmm3
-; AVX1-NEXT:    vpcmpeqw %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpxor %xmm2, %xmm1, %xmm1
-; AVX1-NEXT:    vpaddw %xmm2, %xmm0, %xmm4
-; AVX1-NEXT:    vpand %xmm4, %xmm0, %xmm0
-; AVX1-NEXT:    vpcmpeqw %xmm3, %xmm0, %xmm0
-; AVX1-NEXT:    vpxor %xmm2, %xmm0, %xmm0
-; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vpaddw %xmm1, %xmm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpaddw %xmm1, %xmm3, %xmm4
+; AVX1-NEXT:    vpand %xmm4, %xmm3, %xmm3
+; AVX1-NEXT:    vpxor %xmm4, %xmm4, %xmm4
+; AVX1-NEXT:    vpcmpeqw %xmm4, %xmm3, %xmm3
+; AVX1-NEXT:    vpxor %xmm1, %xmm3, %xmm3
+; AVX1-NEXT:    vpand %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vpcmpeqw %xmm4, %xmm0, %xmm0
+; AVX1-NEXT:    vpxor %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: ugt_1_v16i16:
@@ -1069,13 +1069,13 @@ define <16 x i16> @ugt_1_v16i16(<16 x i16> %0) {
 define <16 x i16> @ult_2_v16i16(<16 x i16> %0) {
 ; AVX1-LABEL: ult_2_v16i16:
 ; AVX1:       # %bb.0:
-; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; AVX1-NEXT:    vpaddw %xmm2, %xmm1, %xmm3
-; AVX1-NEXT:    vpand %xmm3, %xmm1, %xmm1
+; AVX1-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vpaddw %xmm1, %xmm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpaddw %xmm1, %xmm3, %xmm1
+; AVX1-NEXT:    vpand %xmm1, %xmm3, %xmm1
 ; AVX1-NEXT:    vpxor %xmm3, %xmm3, %xmm3
 ; AVX1-NEXT:    vpcmpeqw %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpaddw %xmm2, %xmm0, %xmm2
 ; AVX1-NEXT:    vpand %xmm2, %xmm0, %xmm0
 ; AVX1-NEXT:    vpcmpeqw %xmm3, %xmm0, %xmm0
 ; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
@@ -3302,18 +3302,18 @@ define <16 x i16> @ult_15_v16i16(<16 x i16> %0) {
 define <8 x i32> @ugt_1_v8i32(<8 x i32> %0) {
 ; AVX1-LABEL: ugt_1_v8i32:
 ; AVX1:       # %bb.0:
-; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; AVX1-NEXT:    vpaddd %xmm2, %xmm1, %xmm3
-; AVX1-NEXT:    vpand %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpxor %xmm3, %xmm3, %xmm3
-; AVX1-NEXT:    vpcmpeqd %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpxor %xmm2, %xmm1, %xmm1
-; AVX1-NEXT:    vpaddd %xmm2, %xmm0, %xmm4
-; AVX1-NEXT:    vpand %xmm4, %xmm0, %xmm0
-; AVX1-NEXT:    vpcmpeqd %xmm3, %xmm0, %xmm0
-; AVX1-NEXT:    vpxor %xmm2, %xmm0, %xmm0
-; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vpaddd %xmm1, %xmm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpaddd %xmm1, %xmm3, %xmm4
+; AVX1-NEXT:    vpand %xmm4, %xmm3, %xmm3
+; AVX1-NEXT:    vpxor %xmm4, %xmm4, %xmm4
+; AVX1-NEXT:    vpcmpeqd %xmm4, %xmm3, %xmm3
+; AVX1-NEXT:    vpxor %xmm1, %xmm3, %xmm3
+; AVX1-NEXT:    vpand %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vpcmpeqd %xmm4, %xmm0, %xmm0
+; AVX1-NEXT:    vpxor %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: ugt_1_v8i32:
@@ -3370,13 +3370,13 @@ define <8 x i32> @ugt_1_v8i32(<8 x i32> %0) {
 define <8 x i32> @ult_2_v8i32(<8 x i32> %0) {
 ; AVX1-LABEL: ult_2_v8i32:
 ; AVX1:       # %bb.0:
-; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; AVX1-NEXT:    vpaddd %xmm2, %xmm1, %xmm3
-; AVX1-NEXT:    vpand %xmm3, %xmm1, %xmm1
+; AVX1-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vpaddd %xmm1, %xmm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpaddd %xmm1, %xmm3, %xmm1
+; AVX1-NEXT:    vpand %xmm1, %xmm3, %xmm1
 ; AVX1-NEXT:    vpxor %xmm3, %xmm3, %xmm3
 ; AVX1-NEXT:    vpcmpeqd %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpaddd %xmm2, %xmm0, %xmm2
 ; AVX1-NEXT:    vpand %xmm2, %xmm0, %xmm0
 ; AVX1-NEXT:    vpcmpeqd %xmm3, %xmm0, %xmm0
 ; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
@@ -9377,18 +9377,18 @@ define <8 x i32> @ult_31_v8i32(<8 x i32> %0) {
 define <4 x i64> @ugt_1_v4i64(<4 x i64> %0) {
 ; AVX1-LABEL: ugt_1_v4i64:
 ; AVX1:       # %bb.0:
-; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; AVX1-NEXT:    vpaddq %xmm2, %xmm1, %xmm3
-; AVX1-NEXT:    vpand %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpxor %xmm3, %xmm3, %xmm3
-; AVX1-NEXT:    vpcmpeqq %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpxor %xmm2, %xmm1, %xmm1
-; AVX1-NEXT:    vpaddq %xmm2, %xmm0, %xmm4
-; AVX1-NEXT:    vpand %xmm4, %xmm0, %xmm0
-; AVX1-NEXT:    vpcmpeqq %xmm3, %xmm0, %xmm0
-; AVX1-NEXT:    vpxor %xmm2, %xmm0, %xmm0
-; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vpaddq %xmm1, %xmm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpaddq %xmm1, %xmm3, %xmm4
+; AVX1-NEXT:    vpand %xmm4, %xmm3, %xmm3
+; AVX1-NEXT:    vpxor %xmm4, %xmm4, %xmm4
+; AVX1-NEXT:    vpcmpeqq %xmm4, %xmm3, %xmm3
+; AVX1-NEXT:    vpxor %xmm1, %xmm3, %xmm3
+; AVX1-NEXT:    vpand %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vpcmpeqq %xmm4, %xmm0, %xmm0
+; AVX1-NEXT:    vpxor %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: ugt_1_v4i64:
@@ -9445,13 +9445,13 @@ define <4 x i64> @ugt_1_v4i64(<4 x i64> %0) {
 define <4 x i64> @ult_2_v4i64(<4 x i64> %0) {
 ; AVX1-LABEL: ult_2_v4i64:
 ; AVX1:       # %bb.0:
-; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; AVX1-NEXT:    vpaddq %xmm2, %xmm1, %xmm3
-; AVX1-NEXT:    vpand %xmm3, %xmm1, %xmm1
+; AVX1-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vpaddq %xmm1, %xmm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpaddq %xmm1, %xmm3, %xmm1
+; AVX1-NEXT:    vpand %xmm1, %xmm3, %xmm1
 ; AVX1-NEXT:    vpxor %xmm3, %xmm3, %xmm3
 ; AVX1-NEXT:    vpcmpeqq %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpaddq %xmm2, %xmm0, %xmm2
 ; AVX1-NEXT:    vpand %xmm2, %xmm0, %xmm0
 ; AVX1-NEXT:    vpcmpeqq %xmm3, %xmm0, %xmm0
 ; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
diff --git a/llvm/test/CodeGen/X86/vector-popcnt-256.ll b/llvm/test/CodeGen/X86/vector-popcnt-256.ll
index 701b9622089db..7fb60b987d95d 100644
--- a/llvm/test/CodeGen/X86/vector-popcnt-256.ll
+++ b/llvm/test/CodeGen/X86/vector-popcnt-256.ll
@@ -507,15 +507,15 @@ define <32 x i8> @foldv32i8() nounwind {
 define <4 x i64> @eq_1_v4i64(<4 x i64> %0) {
 ; AVX1-LABEL: eq_1_v4i64:
 ; AVX1:       # %bb.0:
-; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; AVX1-NEXT:    vpaddq %xmm2, %xmm1, %xmm3
+; AVX1-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vpaddq %xmm1, %xmm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpaddq %xmm1, %xmm3, %xmm1
 ; AVX1-NEXT:    vmovddup {{.*#+}} xmm4 = [9223372036854775808,9223372036854775808]
 ; AVX1-NEXT:    # xmm4 = mem[0,0]
-; AVX1-NEXT:    vpxor %xmm4, %xmm3, %xmm3
-; AVX1-NEXT:    vpxor %xmm1, %xmm3, %xmm1
-; AVX1-NEXT:    vpcmpgtq %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpaddq %xmm2, %xmm0, %xmm2
+; AVX1-NEXT:    vpxor %xmm4, %xmm1, %xmm1
+; AVX1-NEXT:    vpxor %xmm3, %xmm1, %xmm3
+; AVX1-NEXT:    vpcmpgtq %xmm1, %xmm3, %xmm1
 ; AVX1-NEXT:    vpxor %xmm4, %xmm2, %xmm2
 ; AVX1-NEXT:    vpxor %xmm0, %xmm2, %xmm0
 ; AVX1-NEXT:    vpcmpgtq %xmm2, %xmm0, %xmm0
@@ -534,12 +534,12 @@ define <4 x i64> @eq_1_v4i64(<4 x i64> %0) {
 ;
 ; XOP-LABEL: eq_1_v4i64:
 ; XOP:       # %bb.0:
-; XOP-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; XOP-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; XOP-NEXT:    vpaddq %xmm2, %xmm1, %xmm3
-; XOP-NEXT:    vpxor %xmm3, %xmm1, %xmm1
-; XOP-NEXT:    vpcomgtuq %xmm3, %xmm1, %xmm1
-; XOP-NEXT:    vpaddq %xmm2, %xmm0, %xmm2
+; XOP-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; XOP-NEXT:    vpaddq %xmm1, %xmm0, %xmm2
+; XOP-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; XOP-NEXT:    vpaddq %xmm1, %xmm3, %xmm1
+; XOP-NEXT:    vpxor %xmm1, %xmm3, %xmm3
+; XOP-NEXT:    vpcomgtuq %xmm1, %xmm3, %xmm1
 ; XOP-NEXT:    vpxor %xmm2, %xmm0, %xmm0
 ; XOP-NEXT:    vpcomgtuq %xmm2, %xmm0, %xmm0
 ; XOP-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
@@ -574,11 +574,10 @@ define <4 x i64> @eq_1_v4i64(<4 x i64> %0) {
 ; BITALG-LABEL: eq_1_v4i64:
 ; BITALG:       # %bb.0:
 ; BITALG-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1
-; BITALG-NEXT:    vpaddq %ymm1, %ymm0, %ymm1
-; BITALG-NEXT:    vpxor %ymm1, %ymm0, %ymm0
-; BITALG-NEXT:    vpminuq %ymm1, %ymm0, %ymm1
-; BITALG-NEXT:    vpcmpeqq %ymm1, %ymm0, %ymm0
-; BITALG-NEXT:    vpternlogq {{.*#+}} ymm0 = ~ymm0
+; BITALG-NEXT:    vpaddq %ymm1, %ymm0, %ymm2
+; BITALG-NEXT:    vpxor %ymm2, %ymm0, %ymm0
+; BITALG-NEXT:    vpcmpnleuq %ymm2, %ymm0, %k1
+; BITALG-NEXT:    vmovdqa64 %ymm1, %ymm0 {%k1} {z}
 ; BITALG-NEXT:    retq
   %2 = tail call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %0)
   %3 = icmp eq <4 x i64> %2, <i64 1, i64 1, i64 1, i64 1>
@@ -589,21 +588,21 @@ define <4 x i64> @eq_1_v4i64(<4 x i64> %0) {
 define <4 x i64> @ne_1_v4i64(<4 x i64> %0) {
 ; AVX1-LABEL: ne_1_v4i64:
 ; AVX1:       # %bb.0:
-; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; AVX1-NEXT:    vpaddq %xmm2, %xmm1, %xmm3
-; AVX1-NEXT:    vmovddup {{.*#+}} xmm4 = [9223372036854775808,9223372036854775808]
-; AVX1-NEXT:    # xmm4 = mem[0,0]
-; AVX1-NEXT:    vpxor %xmm4, %xmm3, %xmm3
-; AVX1-NEXT:    vpxor %xmm1, %xmm3, %xmm1
-; AVX1-NEXT:    vpcmpgtq %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpxor %xmm2, %xmm1, %xmm1
-; AVX1-NEXT:    vpaddq %xmm2, %xmm0, %xmm3
-; AVX1-NEXT:    vpxor %xmm4, %xmm3, %xmm3
-; AVX1-NEXT:    vpxor %xmm0, %xmm3, %xmm0
-; AVX1-NEXT:    vpcmpgtq %xmm3, %xmm0, %xmm0
-; AVX1-NEXT:    vpxor %xmm2, %xmm0, %xmm0
-; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vpaddq %xmm1, %xmm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpaddq %xmm1, %xmm3, %xmm4
+; AVX1-NEXT:    vmovddup {{.*#+}} xmm5 = [9223372036854775808,9223372036854775808]
+; AVX1-NEXT:    # xmm5 = mem[0,0]
+; AVX1-NEXT:    vpxor %xmm5, %xmm4, %xmm4
+; AVX1-NEXT:    vpxor %xmm3, %xmm4, %xmm3
+; AVX1-NEXT:    vpcmpgtq %xmm4, %xmm3, %xmm3
+; AVX1-NEXT:    vpxor %xmm1, %xmm3, %xmm3
+; AVX1-NEXT:    vpxor %xmm5, %xmm2, %xmm2
+; AVX1-NEXT:    vpxor %xmm0, %xmm2, %xmm0
+; AVX1-NEXT:    vpcmpgtq %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vpxor %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: ne_1_v4i64:
@@ -619,12 +618,12 @@ define <4 x i64> @ne_1_v4i64(<4 x i64> %0) {
 ;
 ; XOP-LABEL: ne_1_v4i64:
 ; XOP:       # %bb.0:
-; XOP-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; XOP-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; XOP-NEXT:    vpaddq %xmm2, %xmm1, %xmm3
-; XOP-NEXT:    vpxor %xmm3, %xmm1, %xmm1
-; XOP-NEXT:    vpcomleuq %xmm3, %xmm1, %xmm1
-; XOP-NEXT:    vpaddq %xmm2, %xmm0, %xmm2
+; XOP-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; XOP-NEXT:    vpaddq %xmm1, %xmm0, %xmm2
+; XOP-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; XOP-NEXT:    vpaddq %xmm1, %xmm3, %xmm1
+; XOP-NEXT:    vpxor %xmm1, %xmm3, %xmm3
+; XOP-NEXT:    vpcomleuq %xmm1, %xmm3, %xmm1
 ; XOP-NEXT:    vpxor %xmm2, %xmm0, %xmm0
 ; XOP-NEXT:    vpcomleuq %xmm2, %xmm0, %xmm0
 ; XOP-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
@@ -660,10 +659,10 @@ define <4 x i64> @ne_1_v4i64(<4 x i64> %0) {
 ; BITALG-LABEL: ne_1_v4i64:
 ; BITALG:       # %bb.0:
 ; BITALG-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1
-; BITALG-NEXT:    vpaddq %ymm1, %ymm0, %ymm1
-; BITALG-NEXT:    vpxor %ymm1, %ymm0, %ymm0
-; BITALG-NEXT:    vpminuq %ymm1, %ymm0, %ymm1
-; BITALG-NEXT:    vpcmpeqq %ymm1, %ymm0, %ymm0
+; BITALG-NEXT:    vpaddq %ymm1, %ymm0, %ymm2
+; BITALG-NEXT:    vpxor %ymm2, %ymm0, %ymm0
+; BITALG-NEXT:    vpcmpleuq %ymm2, %ymm0, %k1
+; BITALG-NEXT:    vmovdqa64 %ymm1, %ymm0 {%k1} {z}
 ; BITALG-NEXT:    retq
   %2 = tail call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %0)
   %3 = icmp ne <4 x i64> %2, <i64 1, i64 1, i64 1, i64 1>
@@ -674,19 +673,19 @@ define <4 x i64> @ne_1_v4i64(<4 x i64> %0) {
 define <8 x i32> @eq_1_v8i32(<8 x i32> %0) {
 ; AVX1-LABEL: eq_1_v8i32:
 ; AVX1:       # %bb.0:
-; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; AVX1-NEXT:    vpaddd %xmm2, %xmm1, %xmm3
-; AVX1-NEXT:    vpxor %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpminud %xmm3, %xmm1, %xmm3
-; AVX1-NEXT:    vpcmpeqd %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpxor %xmm2, %xmm1, %xmm1
-; AVX1-NEXT:    vpaddd %xmm2, %xmm0, %xmm3
-; AVX1-NEXT:    vpxor %xmm3, %xmm0, %xmm0
-; AVX1-NEXT:    vpminud %xmm3, %xmm0, %xmm3
-; AVX1-NEXT:    vpcmpeqd %xmm3, %xmm0, %xmm0
+; AVX1-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vpaddd %xmm1, %xmm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpaddd %xmm1, %xmm3, %xmm4
+; AVX1-NEXT:    vpxor %xmm4, %xmm3, %xmm3
+; AVX1-NEXT:    vpminud %xmm4, %xmm3, %xmm4
+; AVX1-NEXT:    vpcmpeqd %xmm4, %xmm3, %xmm3
+; AVX1-NEXT:    vpxor %xmm1, %xmm3, %xmm3
 ; AVX1-NEXT:    vpxor %xmm2, %xmm0, %xmm0
-; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    vpminud %xmm2, %xmm0, %xmm2
+; AVX1-NEXT:    vpcmpeqd %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vpxor %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: eq_1_v8i32:
@@ -701,12 +700,12 @@ define <8 x i32> @eq_1_v8i32(<8 x i32> %0) {
 ;
 ; XOP-LABEL: eq_1_v8i32:
 ; XOP:       # %bb.0:
-; XOP-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; XOP-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; XOP-NEXT:    vpaddd %xmm2, %xmm1, %xmm3
-; XOP-NEXT:    vpxor %xmm3, %xmm1, %xmm1
-; XOP-NEXT:    vpcomgtud %xmm3, %xmm1, %xmm1
-; XOP-NEXT:    vpaddd %xmm2, %xmm0, %xmm2
+; XOP-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; XOP-NEXT:    vpaddd %xmm1, %xmm0, %xmm2
+; XOP-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; XOP-NEXT:    vpaddd %xmm1, %xmm3, %xmm1
+; XOP-NEXT:    vpxor %xmm1, %xmm3, %xmm3
+; XOP-NEXT:    vpcomgtud %xmm1, %xmm3, %xmm1
 ; XOP-NEXT:    vpxor %xmm2, %xmm0, %xmm0
 ; XOP-NEXT:    vpcomgtud %xmm2, %xmm0, %xmm0
 ; XOP-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
@@ -741,11 +740,10 @@ define <8 x i32> @eq_1_v8i32(<8 x i32> %0) {
 ; BITALG-LABEL: eq_1_v8i32:
 ; BITALG:       # %bb.0:
 ; BITALG-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1
-; BITALG-NEXT:    vpaddd %ymm1, %ymm0, %ymm1
-; BITALG-NEXT:    vpxor %ymm1, %ymm0, %ymm0
-; BITALG-NEXT:    vpminud %ymm1, %ymm0, %ymm1
-; BITALG-NEXT:    vpcmpeqd %ymm1, %ymm0, %ymm0
-; BITALG-NEXT:    vpternlogq {{.*#+}} ymm0 = ~ymm0
+; BITALG-NEXT:    vpaddd %ymm1, %ymm0, %ymm2
+; BITALG-NEXT:    vpxor %ymm2, %ymm0, %ymm0
+; BITALG-NEXT:    vpcmpnleud %ymm2, %ymm0, %k1
+; BITALG-NEXT:    vmovdqa32 %ymm1, %ymm0 {%k1} {z}
 ; BITALG-NEXT:    retq
   %2 = tail call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> %0)
   %3 = icmp eq <8 x i32> %2, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -756,13 +754,13 @@ define <8 x i32> @eq_1_v8i32(<8 x i32> %0) {
 define <8 x i32> @ne_1_v8i32(<8 x i32> %0) {
 ; AVX1-LABEL: ne_1_v8i32:
 ; AVX1:       # %bb.0:
-; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; AVX1-NEXT:    vpaddd %xmm2, %xmm1, %xmm3
-; AVX1-NEXT:    vpxor %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpminud %xmm3, %xmm1, %xmm3
-; AVX1-NEXT:    vpcmpeqd %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpaddd %xmm2, %xmm0, %xmm2
+; AVX1-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vpaddd %xmm1, %xmm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpaddd %xmm1, %xmm3, %xmm1
+; AVX1-NEXT:    vpxor %xmm1, %xmm3, %xmm3
+; AVX1-NEXT:    vpminud %xmm1, %xmm3, %xmm1
+; AVX1-NEXT:    vpcmpeqd %xmm1, %xmm3, %xmm1
 ; AVX1-NEXT:    vpxor %xmm2, %xmm0, %xmm0
 ; AVX1-NEXT:    vpminud %xmm2, %xmm0, %xmm2
 ; AVX1-NEXT:    vpcmpeqd %xmm2, %xmm0, %xmm0
@@ -780,12 +778,12 @@ define <8 x i32> @ne_1_v8i32(<8 x i32> %0) {
 ;
 ; XOP-LABEL: ne_1_v8i32:
 ; XOP:       # %bb.0:
-; XOP-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; XOP-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; XOP-NEXT:    vpaddd %xmm2, %xmm1, %xmm3
-; XOP-NEXT:    vpxor %xmm3, %xmm1, %xmm1
-; XOP-NEXT:    vpcomleud %xmm3, %xmm1, %xmm1
-; XOP-NEXT:    vpaddd %xmm2, %xmm0, %xmm2
+; XOP-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; XOP-NEXT:    vpaddd %xmm1, %xmm0, %xmm2
+; XOP-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; XOP-NEXT:    vpaddd %xmm1, %xmm3, %xmm1
+; XOP-NEXT:    vpxor %xmm1, %xmm3, %xmm3
+; XOP-NEXT:    vpcomleud %xmm1, %xmm3, %xmm1
 ; XOP-NEXT:    vpxor %xmm2, %xmm0, %xmm0
 ; XOP-NEXT:    vpcomleud %xmm2, %xmm0, %xmm0
 ; XOP-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
@@ -821,10 +819,10 @@ define <8 x i32> @ne_1_v8i32(<8 x i32> %0) {
 ; BITALG-LABEL: ne_1_v8i32:
 ; BITALG:       # %bb.0:
 ; BITALG-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1
-; BITALG-NEXT:    vpaddd %ymm1, %ymm0, %ymm1
-; BITALG-NEXT:    vpxor %ymm1, %ymm0, %ymm0
-; BITALG-NEXT:    vpminud %ymm1, %ymm0, %ymm1
-; BITALG-NEXT:    vpcmpeqd %ymm1, %ymm0, %ymm0
+; BITALG-NEXT:    vpaddd %ymm1, %ymm0, %ymm2
+; BITALG-NEXT:    vpxor %ymm2, %ymm0, %ymm0
+; BITALG-NEXT:    vpcmpleud %ymm2, %ymm0, %k1
+; BITALG-NEXT:    vmovdqa32 %ymm1, %ymm0 {%k1} {z}
 ; BITALG-NEXT:    retq
   %2 = tail call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> %0)
   %3 = icmp ne <8 x i32> %2, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -835,19 +833,19 @@ define <8 x i32> @ne_1_v8i32(<8 x i32> %0) {
 define <16 x i16> @eq_1_v16i16(<16 x i16> %0) {
 ; AVX1-LABEL: eq_1_v16i16:
 ; AVX1:       # %bb.0:
-; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; AVX1-NEXT:    vpaddw %xmm2, %xmm1, %xmm3
-; AVX1-NEXT:    vpxor %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpminuw %xmm3, %xmm1, %xmm3
-; AVX1-NEXT:    vpcmpeqw %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpxor %xmm2, %xmm1, %xmm1
-; AVX1-NEXT:    vpaddw %xmm2, %xmm0, %xmm3
-; AVX1-NEXT:    vpxor %xmm3, %xmm0, %xmm0
-; AVX1-NEXT:    vpminuw %xmm3, %xmm0, %xmm3
-; AVX1-NEXT:    vpcmpeqw %xmm3, %xmm0, %xmm0
+; AVX1-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vpaddw %xmm1, %xmm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpaddw %xmm1, %xmm3, %xmm4
+; AVX1-NEXT:    vpxor %xmm4, %xmm3, %xmm3
+; AVX1-NEXT:    vpminuw %xmm4, %xmm3, %xmm4
+; AVX1-NEXT:    vpcmpeqw %xmm4, %xmm3, %xmm3
+; AVX1-NEXT:    vpxor %xmm1, %xmm3, %xmm3
 ; AVX1-NEXT:    vpxor %xmm2, %xmm0, %xmm0
-; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    vpminuw %xmm2, %xmm0, %xmm2
+; AVX1-NEXT:    vpcmpeqw %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vpxor %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: eq_1_v16i16:
@@ -862,12 +860,12 @@ define <16 x i16> @eq_1_v16i16(<16 x i16> %0) {
 ;
 ; XOP-LABEL: eq_1_v16i16:
 ; XOP:       # %bb.0:
-; XOP-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; XOP-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; XOP-NEXT:    vpaddw %xmm2, %xmm1, %xmm3
-; XOP-NEXT:    vpxor %xmm3, %xmm1, %xmm1
-; XOP-NEXT:    vpcomgtuw %xmm3, %xmm1, %xmm1
-; XOP-NEXT:    vpaddw %xmm2, %xmm0, %xmm2
+; XOP-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; XOP-NEXT:    vpaddw %xmm1, %xmm0, %xmm2
+; XOP-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; XOP-NEXT:    vpaddw %xmm1, %xmm3, %xmm1
+; XOP-NEXT:    vpxor %xmm1, %xmm3, %xmm3
+; XOP-NEXT:    vpcomgtuw %xmm1, %xmm3, %xmm1
 ; XOP-NEXT:    vpxor %xmm2, %xmm0, %xmm0
 ; XOP-NEXT:    vpcomgtuw %xmm2, %xmm0, %xmm0
 ; XOP-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
@@ -915,13 +913,13 @@ define <16 x i16> @eq_1_v16i16(<16 x i16> %0) {
 define <16 x i16> @ne_1_v16i16(<16 x i16> %0) {
 ; AVX1-LABEL: ne_1_v16i16:
 ; AVX1:       # %bb.0:
-; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; AVX1-NEXT:    vpaddw %xmm2, %xmm1, %xmm3
-; AVX1-NEXT:    vpxor %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpminuw %xmm3, %xmm1, %xmm3
-; AVX1-NEXT:    vpcmpeqw %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpaddw %xmm2, %xmm0, %xmm2
+; AVX1-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vpaddw %xmm1, %xmm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpaddw %xmm1, %xmm3, %xmm1
+; AVX1-NEXT:    vpxor %xmm1, %xmm3, %xmm3
+; AVX1-NEXT:    vpminuw %xmm1, %xmm3, %xmm1
+; AVX1-NEXT:    vpcmpeqw %xmm1, %xmm3, %xmm1
 ; AVX1-NEXT:    vpxor %xmm2, %xmm0, %xmm0
 ; AVX1-NEXT:    vpminuw %xmm2, %xmm0, %xmm2
 ; AVX1-NEXT:    vpcmpeqw %xmm2, %xmm0, %xmm0
@@ -939,12 +937,12 @@ define <16 x i16> @ne_1_v16i16(<16 x i16> %0) {
 ;
 ; XOP-LABEL: ne_1_v16i16:
 ; XOP:       # %bb.0:
-; XOP-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; XOP-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; XOP-NEXT:    vpaddw %xmm2, %xmm1, %xmm3
-; XOP-NEXT:    vpxor %xmm3, %xmm1, %xmm1
-; XOP-NEXT:    vpcomleuw %xmm3, %xmm1, %xmm1
-; XOP-NEXT:    vpaddw %xmm2, %xmm0, %xmm2
+; XOP-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; XOP-NEXT:    vpaddw %xmm1, %xmm0, %xmm2
+; XOP-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; XOP-NEXT:    vpaddw %xmm1, %xmm3, %xmm1
+; XOP-NEXT:    vpxor %xmm1, %xmm3, %xmm3
+; XOP-NEXT:    vpcomleuw %xmm1, %xmm3, %xmm1
 ; XOP-NEXT:    vpxor %xmm2, %xmm0, %xmm0
 ; XOP-NEXT:    vpcomleuw %xmm2, %xmm0, %xmm0
 ; XOP-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
@@ -992,19 +990,19 @@ define <16 x i16> @ne_1_v16i16(<16 x i16> %0) {
 define <32 x i8> @eq_1_v32i8(<32 x i8> %0) {
 ; AVX1-LABEL: eq_1_v32i8:
 ; AVX1:       # %bb.0:
-; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; AVX1-NEXT:    vpaddb %xmm2, %xmm1, %xmm3
-; AVX1-NEXT:    vpxor %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpminub %xmm3, %xmm1, %xmm3
-; AVX1-NEXT:    vpcmpeqb %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpxor %xmm2, %xmm1, %xmm1
-; AVX1-NEXT:    vpaddb %xmm2, %xmm0, %xmm3
-; AVX1-NEXT:    vpxor %xmm3, %xmm0, %xmm0
-; AVX1-NEXT:    vpminub %xmm3, %xmm0, %xmm3
-; AVX1-NEXT:    vpcmpeqb %xmm3, %xmm0, %xmm0
+; AVX1-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vpaddb %xmm1, %xmm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpaddb %xmm1, %xmm3, %xmm4
+; AVX1-NEXT:    vpxor %xmm4, %xmm3, %xmm3
+; AVX1-NEXT:    vpminub %xmm4, %xmm3, %xmm4
+; AVX1-NEXT:    vpcmpeqb %xmm4, %xmm3, %xmm3
+; AVX1-NEXT:    vpxor %xmm1, %xmm3, %xmm3
 ; AVX1-NEXT:    vpxor %xmm2, %xmm0, %xmm0
-; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT:    vpminub %xmm2, %xmm0, %xmm2
+; AVX1-NEXT:    vpcmpeqb %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vpxor %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: eq_1_v32i8:
@@ -1019,12 +1017,12 @@ define <32 x i8> @eq_1_v32i8(<32 x i8> %0) {
 ;
 ; XOP-LABEL: eq_1_v32i8:
 ; XOP:       # %bb.0:
-; XOP-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; XOP-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; XOP-NEXT:    vpaddb %xmm2, %xmm1, %xmm3
-; XOP-NEXT:    vpxor %xmm3, %xmm1, %xmm1
-; XOP-NEXT:    vpcomgtub %xmm3, %xmm1, %xmm1
-; XOP-NEXT:    vpaddb %xmm2, %xmm0, %xmm2
+; XOP-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; XOP-NEXT:    vpaddb %xmm1, %xmm0, %xmm2
+; XOP-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; XOP-NEXT:    vpaddb %xmm1, %xmm3, %xmm1
+; XOP-NEXT:    vpxor %xmm1, %xmm3, %xmm3
+; XOP-NEXT:    vpcomgtub %xmm1, %xmm3, %xmm1
 ; XOP-NEXT:    vpxor %xmm2, %xmm0, %xmm0
 ; XOP-NEXT:    vpcomgtub %xmm2, %xmm0, %xmm0
 ; XOP-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
@@ -1072,13 +1070,13 @@ define <32 x i8> @eq_1_v32i8(<32 x i8> %0) {
 define <32 x i8> @ne_1_v32i8(<32 x i8> %0) {
 ; AVX1-LABEL: ne_1_v32i8:
 ; AVX1:       # %bb.0:
-; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; AVX1-NEXT:    vpaddb %xmm2, %xmm1, %xmm3
-; AVX1-NEXT:    vpxor %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpminub %xmm3, %xmm1, %xmm3
-; AVX1-NEXT:    vpcmpeqb %xmm3, %xmm1, %xmm1
-; AVX1-NEXT:    vpaddb %xmm2, %xmm0, %xmm2
+; AVX1-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; AVX1-NEXT:    vpaddb %xmm1, %xmm0, %xmm2
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT:    vpaddb %xmm1, %xmm3, %xmm1
+; AVX1-NEXT:    vpxor %xmm1, %xmm3, %xmm3
+; AVX1-NEXT:    vpminub %xmm1, %xmm3, %xmm1
+; AVX1-NEXT:    vpcmpeqb %xmm1, %xmm3, %xmm1
 ; AVX1-NEXT:    vpxor %xmm2, %xmm0, %xmm0
 ; AVX1-NEXT:    vpminub %xmm2, %xmm0, %xmm2
 ; AVX1-NEXT:    vpcmpeqb %xmm2, %xmm0, %xmm0
@@ -1096,12 +1094,12 @@ define <32 x i8> @ne_1_v32i8(<32 x i8> %0) {
 ;
 ; XOP-LABEL: ne_1_v32i8:
 ; XOP:       # %bb.0:
-; XOP-NEXT:    vextractf128 $1, %ymm0, %xmm1
-; XOP-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; XOP-NEXT:    vpaddb %xmm2, %xmm1, %xmm3
-; XOP-NEXT:    vpxor %xmm3, %xmm1, %xmm1
-; XOP-NEXT:    vpcomleub %xmm3, %xmm1, %xmm1
-; XOP-NEXT:    vpaddb %xmm2, %xmm0, %xmm2
+; XOP-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; XOP-NEXT:    vpaddb %xmm1, %xmm0, %xmm2
+; XOP-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; XOP-NEXT:    vpaddb %xmm1, %xmm3, %xmm1
+; XOP-NEXT:    vpxor %xmm1, %xmm3, %xmm3
+; XOP-NEXT:    vpcomleub %xmm1, %xmm3, %xmm1
 ; XOP-NEXT:    vpxor %xmm2, %xmm0, %xmm0
 ; XOP-NEXT:    vpcomleub %xmm2, %xmm0, %xmm0
 ; XOP-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
diff --git a/llvm/test/CodeGen/X86/vector-popcnt-512-ult-ugt.ll b/llvm/test/CodeGen/X86/vector-popcnt-512-ult-ugt.ll
index 828c97de3a079..1618a647a4062 100644
--- a/llvm/test/CodeGen/X86/vector-popcnt-512-ult-ugt.ll
+++ b/llvm/test/CodeGen/X86/vector-popcnt-512-ult-ugt.ll
@@ -9,13 +9,13 @@
 define <64 x i8> @ugt_1_v64i8(<64 x i8> %0) {
 ; AVX512F-LABEL: ugt_1_v64i8:
 ; AVX512F:       # %bb.0:
-; AVX512F-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
-; AVX512F-NEXT:    vpcmpeqd %ymm2, %ymm2, %ymm2
-; AVX512F-NEXT:    vpaddb %ymm2, %ymm1, %ymm3
-; AVX512F-NEXT:    vpand %ymm3, %ymm1, %ymm1
+; AVX512F-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512F-NEXT:    vpaddb %ymm1, %ymm0, %ymm2
+; AVX512F-NEXT:    vextracti64x4 $1, %zmm0, %ymm3
+; AVX512F-NEXT:    vpaddb %ymm1, %ymm3, %ymm1
+; AVX512F-NEXT:    vpand %ymm1, %ymm3, %ymm1
 ; AVX512F-NEXT:    vpxor %xmm3, %xmm3, %xmm3
 ; AVX512F-NEXT:    vpcmpeqb %ymm3, %ymm1, %ymm1
-; AVX512F-NEXT:    vpaddb %ymm2, %ymm0, %ymm2
 ; AVX512F-NEXT:    vpand %ymm2, %ymm0, %ymm0
 ; AVX512F-NEXT:    vpcmpeqb %ymm3, %ymm0, %ymm0
 ; AVX512F-NEXT:    vinserti64x4 $1, %ymm1, %zmm0, %zmm0
@@ -32,13 +32,13 @@ define <64 x i8> @ugt_1_v64i8(<64 x i8> %0) {
 ;
 ; AVX512VPOPCNTDQ-NOBW-LABEL: ugt_1_v64i8:
 ; AVX512VPOPCNTDQ-NOBW:       # %bb.0:
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqd %ymm2, %ymm2, %ymm2
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddb %ymm2, %ymm1, %ymm3
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpand %ymm3, %ymm1, %ymm1
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddb %ymm1, %ymm0, %ymm2
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vextracti64x4 $1, %zmm0, %ymm3
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddb %ymm1, %ymm3, %ymm1
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpand %ymm1, %ymm3, %ymm1
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpxor %xmm3, %xmm3, %xmm3
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqb %ymm3, %ymm1, %ymm1
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddb %ymm2, %ymm0, %ymm2
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpand %ymm2, %ymm0, %ymm0
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqb %ymm3, %ymm0, %ymm0
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vinserti64x4 $1, %ymm1, %zmm0, %zmm0
@@ -68,13 +68,13 @@ define <64 x i8> @ugt_1_v64i8(<64 x i8> %0) {
 define <64 x i8> @ult_2_v64i8(<64 x i8> %0) {
 ; AVX512F-LABEL: ult_2_v64i8:
 ; AVX512F:       # %bb.0:
-; AVX512F-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
-; AVX512F-NEXT:    vpcmpeqd %ymm2, %ymm2, %ymm2
-; AVX512F-NEXT:    vpaddb %ymm2, %ymm1, %ymm3
-; AVX512F-NEXT:    vpand %ymm3, %ymm1, %ymm1
+; AVX512F-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512F-NEXT:    vpaddb %ymm1, %ymm0, %ymm2
+; AVX512F-NEXT:    vextracti64x4 $1, %zmm0, %ymm3
+; AVX512F-NEXT:    vpaddb %ymm1, %ymm3, %ymm1
+; AVX512F-NEXT:    vpand %ymm1, %ymm3, %ymm1
 ; AVX512F-NEXT:    vpxor %xmm3, %xmm3, %xmm3
 ; AVX512F-NEXT:    vpcmpeqb %ymm3, %ymm1, %ymm1
-; AVX512F-NEXT:    vpaddb %ymm2, %ymm0, %ymm2
 ; AVX512F-NEXT:    vpand %ymm2, %ymm0, %ymm0
 ; AVX512F-NEXT:    vpcmpeqb %ymm3, %ymm0, %ymm0
 ; AVX512F-NEXT:    vinserti64x4 $1, %ymm1, %zmm0, %zmm0
@@ -90,13 +90,13 @@ define <64 x i8> @ult_2_v64i8(<64 x i8> %0) {
 ;
 ; AVX512VPOPCNTDQ-NOBW-LABEL: ult_2_v64i8:
 ; AVX512VPOPCNTDQ-NOBW:       # %bb.0:
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqd %ymm2, %ymm2, %ymm2
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddb %ymm2, %ymm1, %ymm3
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpand %ymm3, %ymm1, %ymm1
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddb %ymm1, %ymm0, %ymm2
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vextracti64x4 $1, %zmm0, %ymm3
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddb %ymm1, %ymm3, %ymm1
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpand %ymm1, %ymm3, %ymm1
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpxor %xmm3, %xmm3, %xmm3
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqb %ymm3, %ymm1, %ymm1
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddb %ymm2, %ymm0, %ymm2
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpand %ymm2, %ymm0, %ymm0
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqb %ymm3, %ymm0, %ymm0
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vinserti64x4 $1, %ymm1, %zmm0, %zmm0
@@ -1035,13 +1035,13 @@ define <64 x i8> @ult_7_v64i8(<64 x i8> %0) {
 define <32 x i16> @ugt_1_v32i16(<32 x i16> %0) {
 ; AVX512F-LABEL: ugt_1_v32i16:
 ; AVX512F:       # %bb.0:
-; AVX512F-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
-; AVX512F-NEXT:    vpcmpeqd %ymm2, %ymm2, %ymm2
-; AVX512F-NEXT:    vpaddw %ymm2, %ymm1, %ymm3
-; AVX512F-NEXT:    vpand %ymm3, %ymm1, %ymm1
+; AVX512F-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512F-NEXT:    vpaddw %ymm1, %ymm0, %ymm2
+; AVX512F-NEXT:    vextracti64x4 $1, %zmm0, %ymm3
+; AVX512F-NEXT:    vpaddw %ymm1, %ymm3, %ymm1
+; AVX512F-NEXT:    vpand %ymm1, %ymm3, %ymm1
 ; AVX512F-NEXT:    vpxor %xmm3, %xmm3, %xmm3
 ; AVX512F-NEXT:    vpcmpeqw %ymm3, %ymm1, %ymm1
-; AVX512F-NEXT:    vpaddw %ymm2, %ymm0, %ymm2
 ; AVX512F-NEXT:    vpand %ymm2, %ymm0, %ymm0
 ; AVX512F-NEXT:    vpcmpeqw %ymm3, %ymm0, %ymm0
 ; AVX512F-NEXT:    vinserti64x4 $1, %ymm1, %zmm0, %zmm0
@@ -1058,13 +1058,13 @@ define <32 x i16> @ugt_1_v32i16(<32 x i16> %0) {
 ;
 ; AVX512VPOPCNTDQ-NOBW-LABEL: ugt_1_v32i16:
 ; AVX512VPOPCNTDQ-NOBW:       # %bb.0:
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqd %ymm2, %ymm2, %ymm2
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddw %ymm2, %ymm1, %ymm3
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpand %ymm3, %ymm1, %ymm1
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddw %ymm1, %ymm0, %ymm2
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vextracti64x4 $1, %zmm0, %ymm3
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddw %ymm1, %ymm3, %ymm1
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpand %ymm1, %ymm3, %ymm1
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpxor %xmm3, %xmm3, %xmm3
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqw %ymm3, %ymm1, %ymm1
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddw %ymm2, %ymm0, %ymm2
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpand %ymm2, %ymm0, %ymm0
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqw %ymm3, %ymm0, %ymm0
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vinserti64x4 $1, %ymm1, %zmm0, %zmm0
@@ -1094,13 +1094,13 @@ define <32 x i16> @ugt_1_v32i16(<32 x i16> %0) {
 define <32 x i16> @ult_2_v32i16(<32 x i16> %0) {
 ; AVX512F-LABEL: ult_2_v32i16:
 ; AVX512F:       # %bb.0:
-; AVX512F-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
-; AVX512F-NEXT:    vpcmpeqd %ymm2, %ymm2, %ymm2
-; AVX512F-NEXT:    vpaddw %ymm2, %ymm1, %ymm3
-; AVX512F-NEXT:    vpand %ymm3, %ymm1, %ymm1
+; AVX512F-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512F-NEXT:    vpaddw %ymm1, %ymm0, %ymm2
+; AVX512F-NEXT:    vextracti64x4 $1, %zmm0, %ymm3
+; AVX512F-NEXT:    vpaddw %ymm1, %ymm3, %ymm1
+; AVX512F-NEXT:    vpand %ymm1, %ymm3, %ymm1
 ; AVX512F-NEXT:    vpxor %xmm3, %xmm3, %xmm3
 ; AVX512F-NEXT:    vpcmpeqw %ymm3, %ymm1, %ymm1
-; AVX512F-NEXT:    vpaddw %ymm2, %ymm0, %ymm2
 ; AVX512F-NEXT:    vpand %ymm2, %ymm0, %ymm0
 ; AVX512F-NEXT:    vpcmpeqw %ymm3, %ymm0, %ymm0
 ; AVX512F-NEXT:    vinserti64x4 $1, %ymm1, %zmm0, %zmm0
@@ -1116,13 +1116,13 @@ define <32 x i16> @ult_2_v32i16(<32 x i16> %0) {
 ;
 ; AVX512VPOPCNTDQ-NOBW-LABEL: ult_2_v32i16:
 ; AVX512VPOPCNTDQ-NOBW:       # %bb.0:
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqd %ymm2, %ymm2, %ymm2
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddw %ymm2, %ymm1, %ymm3
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpand %ymm3, %ymm1, %ymm1
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddw %ymm1, %ymm0, %ymm2
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vextracti64x4 $1, %zmm0, %ymm3
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddw %ymm1, %ymm3, %ymm1
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpand %ymm1, %ymm3, %ymm1
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpxor %xmm3, %xmm3, %xmm3
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqw %ymm3, %ymm1, %ymm1
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddw %ymm2, %ymm0, %ymm2
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpand %ymm2, %ymm0, %ymm0
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqw %ymm3, %ymm0, %ymm0
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vinserti64x4 $1, %ymm1, %zmm0, %zmm0
diff --git a/llvm/test/CodeGen/X86/vector-popcnt-512.ll b/llvm/test/CodeGen/X86/vector-popcnt-512.ll
index 0a5f16a0f635f..f470a2be8aee8 100644
--- a/llvm/test/CodeGen/X86/vector-popcnt-512.ll
+++ b/llvm/test/CodeGen/X86/vector-popcnt-512.ll
@@ -451,13 +451,13 @@ define <16 x i32> @ne_1_v16i32(<16 x i32> %0) {
 define <32 x i16> @eq_1_v32i16(<32 x i16> %0) {
 ; AVX512F-LABEL: eq_1_v32i16:
 ; AVX512F:       # %bb.0:
-; AVX512F-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
-; AVX512F-NEXT:    vpcmpeqd %ymm2, %ymm2, %ymm2
-; AVX512F-NEXT:    vpaddw %ymm2, %ymm1, %ymm3
-; AVX512F-NEXT:    vpxor %ymm3, %ymm1, %ymm1
-; AVX512F-NEXT:    vpminuw %ymm3, %ymm1, %ymm3
-; AVX512F-NEXT:    vpcmpeqw %ymm3, %ymm1, %ymm1
-; AVX512F-NEXT:    vpaddw %ymm2, %ymm0, %ymm2
+; AVX512F-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512F-NEXT:    vpaddw %ymm1, %ymm0, %ymm2
+; AVX512F-NEXT:    vextracti64x4 $1, %zmm0, %ymm3
+; AVX512F-NEXT:    vpaddw %ymm1, %ymm3, %ymm1
+; AVX512F-NEXT:    vpxor %ymm1, %ymm3, %ymm3
+; AVX512F-NEXT:    vpminuw %ymm1, %ymm3, %ymm1
+; AVX512F-NEXT:    vpcmpeqw %ymm1, %ymm3, %ymm1
 ; AVX512F-NEXT:    vpxor %ymm2, %ymm0, %ymm0
 ; AVX512F-NEXT:    vpminuw %ymm2, %ymm0, %ymm2
 ; AVX512F-NEXT:    vpcmpeqw %ymm2, %ymm0, %ymm0
@@ -476,13 +476,13 @@ define <32 x i16> @eq_1_v32i16(<32 x i16> %0) {
 ;
 ; AVX512VPOPCNTDQ-NOBW-LABEL: eq_1_v32i16:
 ; AVX512VPOPCNTDQ-NOBW:       # %bb.0:
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqd %ymm2, %ymm2, %ymm2
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddw %ymm2, %ymm1, %ymm3
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpxor %ymm3, %ymm1, %ymm1
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpminuw %ymm3, %ymm1, %ymm3
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqw %ymm3, %ymm1, %ymm1
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddw %ymm2, %ymm0, %ymm2
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddw %ymm1, %ymm0, %ymm2
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vextracti64x4 $1, %zmm0, %ymm3
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddw %ymm1, %ymm3, %ymm1
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpxor %ymm1, %ymm3, %ymm3
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpminuw %ymm1, %ymm3, %ymm1
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqw %ymm1, %ymm3, %ymm1
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpxor %ymm2, %ymm0, %ymm0
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpminuw %ymm2, %ymm0, %ymm2
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqw %ymm2, %ymm0, %ymm0
@@ -514,13 +514,13 @@ define <32 x i16> @eq_1_v32i16(<32 x i16> %0) {
 define <32 x i16> @ne_1_v32i16(<32 x i16> %0) {
 ; AVX512F-LABEL: ne_1_v32i16:
 ; AVX512F:       # %bb.0:
-; AVX512F-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
-; AVX512F-NEXT:    vpcmpeqd %ymm2, %ymm2, %ymm2
-; AVX512F-NEXT:    vpaddw %ymm2, %ymm1, %ymm3
-; AVX512F-NEXT:    vpxor %ymm3, %ymm1, %ymm1
-; AVX512F-NEXT:    vpminuw %ymm3, %ymm1, %ymm3
-; AVX512F-NEXT:    vpcmpeqw %ymm3, %ymm1, %ymm1
-; AVX512F-NEXT:    vpaddw %ymm2, %ymm0, %ymm2
+; AVX512F-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512F-NEXT:    vpaddw %ymm1, %ymm0, %ymm2
+; AVX512F-NEXT:    vextracti64x4 $1, %zmm0, %ymm3
+; AVX512F-NEXT:    vpaddw %ymm1, %ymm3, %ymm1
+; AVX512F-NEXT:    vpxor %ymm1, %ymm3, %ymm3
+; AVX512F-NEXT:    vpminuw %ymm1, %ymm3, %ymm1
+; AVX512F-NEXT:    vpcmpeqw %ymm1, %ymm3, %ymm1
 ; AVX512F-NEXT:    vpxor %ymm2, %ymm0, %ymm0
 ; AVX512F-NEXT:    vpminuw %ymm2, %ymm0, %ymm2
 ; AVX512F-NEXT:    vpcmpeqw %ymm2, %ymm0, %ymm0
@@ -538,13 +538,13 @@ define <32 x i16> @ne_1_v32i16(<32 x i16> %0) {
 ;
 ; AVX512VPOPCNTDQ-NOBW-LABEL: ne_1_v32i16:
 ; AVX512VPOPCNTDQ-NOBW:       # %bb.0:
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqd %ymm2, %ymm2, %ymm2
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddw %ymm2, %ymm1, %ymm3
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpxor %ymm3, %ymm1, %ymm1
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpminuw %ymm3, %ymm1, %ymm3
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqw %ymm3, %ymm1, %ymm1
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddw %ymm2, %ymm0, %ymm2
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddw %ymm1, %ymm0, %ymm2
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vextracti64x4 $1, %zmm0, %ymm3
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddw %ymm1, %ymm3, %ymm1
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpxor %ymm1, %ymm3, %ymm3
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpminuw %ymm1, %ymm3, %ymm1
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqw %ymm1, %ymm3, %ymm1
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpxor %ymm2, %ymm0, %ymm0
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpminuw %ymm2, %ymm0, %ymm2
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqw %ymm2, %ymm0, %ymm0
@@ -575,13 +575,13 @@ define <32 x i16> @ne_1_v32i16(<32 x i16> %0) {
 define <64 x i8> @eq_1_v64i8(<64 x i8> %0) {
 ; AVX512F-LABEL: eq_1_v64i8:
 ; AVX512F:       # %bb.0:
-; AVX512F-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
-; AVX512F-NEXT:    vpcmpeqd %ymm2, %ymm2, %ymm2
-; AVX512F-NEXT:    vpaddb %ymm2, %ymm1, %ymm3
-; AVX512F-NEXT:    vpxor %ymm3, %ymm1, %ymm1
-; AVX512F-NEXT:    vpminub %ymm3, %ymm1, %ymm3
-; AVX512F-NEXT:    vpcmpeqb %ymm3, %ymm1, %ymm1
-; AVX512F-NEXT:    vpaddb %ymm2, %ymm0, %ymm2
+; AVX512F-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512F-NEXT:    vpaddb %ymm1, %ymm0, %ymm2
+; AVX512F-NEXT:    vextracti64x4 $1, %zmm0, %ymm3
+; AVX512F-NEXT:    vpaddb %ymm1, %ymm3, %ymm1
+; AVX512F-NEXT:    vpxor %ymm1, %ymm3, %ymm3
+; AVX512F-NEXT:    vpminub %ymm1, %ymm3, %ymm1
+; AVX512F-NEXT:    vpcmpeqb %ymm1, %ymm3, %ymm1
 ; AVX512F-NEXT:    vpxor %ymm2, %ymm0, %ymm0
 ; AVX512F-NEXT:    vpminub %ymm2, %ymm0, %ymm2
 ; AVX512F-NEXT:    vpcmpeqb %ymm2, %ymm0, %ymm0
@@ -600,13 +600,13 @@ define <64 x i8> @eq_1_v64i8(<64 x i8> %0) {
 ;
 ; AVX512VPOPCNTDQ-NOBW-LABEL: eq_1_v64i8:
 ; AVX512VPOPCNTDQ-NOBW:       # %bb.0:
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqd %ymm2, %ymm2, %ymm2
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddb %ymm2, %ymm1, %ymm3
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpxor %ymm3, %ymm1, %ymm1
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpminub %ymm3, %ymm1, %ymm3
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqb %ymm3, %ymm1, %ymm1
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddb %ymm2, %ymm0, %ymm2
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddb %ymm1, %ymm0, %ymm2
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vextracti64x4 $1, %zmm0, %ymm3
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddb %ymm1, %ymm3, %ymm1
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpxor %ymm1, %ymm3, %ymm3
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpminub %ymm1, %ymm3, %ymm1
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqb %ymm1, %ymm3, %ymm1
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpxor %ymm2, %ymm0, %ymm0
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpminub %ymm2, %ymm0, %ymm2
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqb %ymm2, %ymm0, %ymm0
@@ -638,13 +638,13 @@ define <64 x i8> @eq_1_v64i8(<64 x i8> %0) {
 define <64 x i8> @ne_1_v64i8(<64 x i8> %0) {
 ; AVX512F-LABEL: ne_1_v64i8:
 ; AVX512F:       # %bb.0:
-; AVX512F-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
-; AVX512F-NEXT:    vpcmpeqd %ymm2, %ymm2, %ymm2
-; AVX512F-NEXT:    vpaddb %ymm2, %ymm1, %ymm3
-; AVX512F-NEXT:    vpxor %ymm3, %ymm1, %ymm1
-; AVX512F-NEXT:    vpminub %ymm3, %ymm1, %ymm3
-; AVX512F-NEXT:    vpcmpeqb %ymm3, %ymm1, %ymm1
-; AVX512F-NEXT:    vpaddb %ymm2, %ymm0, %ymm2
+; AVX512F-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512F-NEXT:    vpaddb %ymm1, %ymm0, %ymm2
+; AVX512F-NEXT:    vextracti64x4 $1, %zmm0, %ymm3
+; AVX512F-NEXT:    vpaddb %ymm1, %ymm3, %ymm1
+; AVX512F-NEXT:    vpxor %ymm1, %ymm3, %ymm3
+; AVX512F-NEXT:    vpminub %ymm1, %ymm3, %ymm1
+; AVX512F-NEXT:    vpcmpeqb %ymm1, %ymm3, %ymm1
 ; AVX512F-NEXT:    vpxor %ymm2, %ymm0, %ymm0
 ; AVX512F-NEXT:    vpminub %ymm2, %ymm0, %ymm2
 ; AVX512F-NEXT:    vpcmpeqb %ymm2, %ymm0, %ymm0
@@ -662,13 +662,13 @@ define <64 x i8> @ne_1_v64i8(<64 x i8> %0) {
 ;
 ; AVX512VPOPCNTDQ-NOBW-LABEL: ne_1_v64i8:
 ; AVX512VPOPCNTDQ-NOBW:       # %bb.0:
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqd %ymm2, %ymm2, %ymm2
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddb %ymm2, %ymm1, %ymm3
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpxor %ymm3, %ymm1, %ymm1
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpminub %ymm3, %ymm1, %ymm3
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqb %ymm3, %ymm1, %ymm1
-; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddb %ymm2, %ymm0, %ymm2
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddb %ymm1, %ymm0, %ymm2
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vextracti64x4 $1, %zmm0, %ymm3
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpaddb %ymm1, %ymm3, %ymm1
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpxor %ymm1, %ymm3, %ymm3
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpminub %ymm1, %ymm3, %ymm1
+; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqb %ymm1, %ymm3, %ymm1
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpxor %ymm2, %ymm0, %ymm0
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpminub %ymm2, %ymm0, %ymm2
 ; AVX512VPOPCNTDQ-NOBW-NEXT:    vpcmpeqb %ymm2, %ymm0, %ymm0
diff --git a/llvm/test/CodeGen/X86/vector-trunc.ll b/llvm/test/CodeGen/X86/vector-trunc.ll
index 732cc445ddcd8..2e2bf33192b42 100644
--- a/llvm/test/CodeGen/X86/vector-trunc.ll
+++ b/llvm/test/CodeGen/X86/vector-trunc.ll
@@ -215,7 +215,7 @@ entry:
   ret <8 x i16> %0
 }
 
-define void @trunc8i64_8i8(<8 x i64> %a) {
+define void @trunc8i64_8i8(<8 x i64> %a, ptr %b) {
 ; SSE2-SSSE3-LABEL: trunc8i64_8i8:
 ; SSE2-SSSE3:       # %bb.0: # %entry
 ; SSE2-SSSE3-NEXT:    movdqa {{.*#+}} xmm4 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
@@ -227,7 +227,7 @@ define void @trunc8i64_8i8(<8 x i64> %a) {
 ; SSE2-SSSE3-NEXT:    packuswb %xmm1, %xmm0
 ; SSE2-SSSE3-NEXT:    packuswb %xmm2, %xmm0
 ; SSE2-SSSE3-NEXT:    packuswb %xmm0, %xmm0
-; SSE2-SSSE3-NEXT:    movq %xmm0, (%rax)
+; SSE2-SSSE3-NEXT:    movq %xmm0, (%rdi)
 ; SSE2-SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: trunc8i64_8i8:
@@ -241,7 +241,7 @@ define void @trunc8i64_8i8(<8 x i64> %a) {
 ; SSE41-NEXT:    packusdw %xmm1, %xmm0
 ; SSE41-NEXT:    packusdw %xmm2, %xmm0
 ; SSE41-NEXT:    packuswb %xmm0, %xmm0
-; SSE41-NEXT:    movq %xmm0, (%rax)
+; SSE41-NEXT:    movq %xmm0, (%rdi)
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: trunc8i64_8i8:
@@ -255,7 +255,7 @@ define void @trunc8i64_8i8(<8 x i64> %a) {
 ; AVX1-NEXT:    vpackusdw %xmm2, %xmm0, %xmm0
 ; AVX1-NEXT:    vpackusdw %xmm1, %xmm0, %xmm0
 ; AVX1-NEXT:    vpackuswb %xmm0, %xmm0, %xmm0
-; AVX1-NEXT:    vmovq %xmm0, (%rax)
+; AVX1-NEXT:    vmovq %xmm0, (%rdi)
 ; AVX1-NEXT:    vzeroupper
 ; AVX1-NEXT:    retq
 ;
@@ -269,18 +269,18 @@ define void @trunc8i64_8i8(<8 x i64> %a) {
 ; AVX2-NEXT:    vpackusdw %xmm1, %xmm0, %xmm0
 ; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
 ; AVX2-NEXT:    vpackuswb %xmm0, %xmm0, %xmm0
-; AVX2-NEXT:    vmovq %xmm0, (%rax)
+; AVX2-NEXT:    vmovq %xmm0, (%rdi)
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: trunc8i64_8i8:
 ; AVX512:       # %bb.0: # %entry
-; AVX512-NEXT:    vpmovqb %zmm0, (%rax)
+; AVX512-NEXT:    vpmovqb %zmm0, (%rdi)
 ; AVX512-NEXT:    vzeroupper
 ; AVX512-NEXT:    retq
 entry:
   %0 = trunc <8 x i64> %a to <8 x i8>
-  store <8 x i8> %0, ptr undef, align 4
+  store <8 x i8> %0, ptr %b, align 4
   ret void
 }
 
@@ -492,7 +492,7 @@ entry:
   ret <8 x i16> %1
 }
 
-define void @trunc8i32_8i8(<8 x i32> %a) {
+define void @trunc8i32_8i8(<8 x i32> %a, ptr %b) {
 ; SSE2-SSSE3-LABEL: trunc8i32_8i8:
 ; SSE2-SSSE3:       # %bb.0: # %entry
 ; SSE2-SSSE3-NEXT:    movdqa {{.*#+}} xmm2 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
@@ -500,7 +500,7 @@ define void @trunc8i32_8i8(<8 x i32> %a) {
 ; SSE2-SSSE3-NEXT:    pand %xmm2, %xmm0
 ; SSE2-SSSE3-NEXT:    packuswb %xmm1, %xmm0
 ; SSE2-SSSE3-NEXT:    packuswb %xmm0, %xmm0
-; SSE2-SSSE3-NEXT:    movq %xmm0, (%rax)
+; SSE2-SSSE3-NEXT:    movq %xmm0, (%rdi)
 ; SSE2-SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: trunc8i32_8i8:
@@ -510,7 +510,7 @@ define void @trunc8i32_8i8(<8 x i32> %a) {
 ; SSE41-NEXT:    pand %xmm2, %xmm0
 ; SSE41-NEXT:    packusdw %xmm1, %xmm0
 ; SSE41-NEXT:    packuswb %xmm0, %xmm0
-; SSE41-NEXT:    movq %xmm0, (%rax)
+; SSE41-NEXT:    movq %xmm0, (%rdi)
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: trunc8i32_8i8:
@@ -520,7 +520,7 @@ define void @trunc8i32_8i8(<8 x i32> %a) {
 ; AVX1-NEXT:    vpshufb %xmm2, %xmm1, %xmm1
 ; AVX1-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
 ; AVX1-NEXT:    vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; AVX1-NEXT:    vmovq %xmm0, (%rax)
+; AVX1-NEXT:    vmovq %xmm0, (%rdi)
 ; AVX1-NEXT:    vzeroupper
 ; AVX1-NEXT:    retq
 ;
@@ -531,7 +531,7 @@ define void @trunc8i32_8i8(<8 x i32> %a) {
 ; AVX2-NEXT:    vpshufb %xmm2, %xmm1, %xmm1
 ; AVX2-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
 ; AVX2-NEXT:    vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; AVX2-NEXT:    vmovq %xmm0, (%rax)
+; AVX2-NEXT:    vmovq %xmm0, (%rdi)
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
 ;
@@ -539,13 +539,13 @@ define void @trunc8i32_8i8(<8 x i32> %a) {
 ; AVX512F:       # %bb.0: # %entry
 ; AVX512F-NEXT:    # kill: def $ymm0 killed $ymm0 def $zmm0
 ; AVX512F-NEXT:    vpmovdb %zmm0, %xmm0
-; AVX512F-NEXT:    vmovq %xmm0, (%rax)
+; AVX512F-NEXT:    vmovq %xmm0, (%rdi)
 ; AVX512F-NEXT:    vzeroupper
 ; AVX512F-NEXT:    retq
 ;
 ; AVX512VL-LABEL: trunc8i32_8i8:
 ; AVX512VL:       # %bb.0: # %entry
-; AVX512VL-NEXT:    vpmovdb %ymm0, (%rax)
+; AVX512VL-NEXT:    vpmovdb %ymm0, (%rdi)
 ; AVX512VL-NEXT:    vzeroupper
 ; AVX512VL-NEXT:    retq
 ;
@@ -553,22 +553,22 @@ define void @trunc8i32_8i8(<8 x i32> %a) {
 ; AVX512BW:       # %bb.0: # %entry
 ; AVX512BW-NEXT:    # kill: def $ymm0 killed $ymm0 def $zmm0
 ; AVX512BW-NEXT:    vpmovdb %zmm0, %xmm0
-; AVX512BW-NEXT:    vmovq %xmm0, (%rax)
+; AVX512BW-NEXT:    vmovq %xmm0, (%rdi)
 ; AVX512BW-NEXT:    vzeroupper
 ; AVX512BW-NEXT:    retq
 ;
 ; AVX512BWVL-LABEL: trunc8i32_8i8:
 ; AVX512BWVL:       # %bb.0: # %entry
-; AVX512BWVL-NEXT:    vpmovdb %ymm0, (%rax)
+; AVX512BWVL-NEXT:    vpmovdb %ymm0, (%rdi)
 ; AVX512BWVL-NEXT:    vzeroupper
 ; AVX512BWVL-NEXT:    retq
 entry:
   %0 = trunc <8 x i32> %a to <8 x i8>
-  store <8 x i8> %0, ptr undef, align 4
+  store <8 x i8> %0, ptr %b, align 4
   ret void
 }
 
-define void @trunc16i32_16i16(<16 x i32> %a) {
+define void @trunc16i32_16i16(<16 x i32> %a, ptr %b) {
 ; SSE2-LABEL: trunc16i32_16i16:
 ; SSE2:       # %bb.0: # %entry
 ; SSE2-NEXT:    pslld $16, %xmm1
@@ -581,8 +581,8 @@ define void @trunc16i32_16i16(<16 x i32> %a) {
 ; SSE2-NEXT:    pslld $16, %xmm2
 ; SSE2-NEXT:    psrad $16, %xmm2
 ; SSE2-NEXT:    packssdw %xmm3, %xmm2
-; SSE2-NEXT:    movdqu %xmm2, (%rax)
-; SSE2-NEXT:    movdqu %xmm0, (%rax)
+; SSE2-NEXT:    movdqu %xmm2, 16(%rdi)
+; SSE2-NEXT:    movdqu %xmm0, (%rdi)
 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: trunc16i32_16i16:
@@ -594,8 +594,8 @@ define void @trunc16i32_16i16(<16 x i32> %a) {
 ; SSSE3-NEXT:    pshufb %xmm4, %xmm3
 ; SSSE3-NEXT:    pshufb %xmm4, %xmm2
 ; SSSE3-NEXT:    punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
-; SSSE3-NEXT:    movdqu %xmm2, (%rax)
-; SSSE3-NEXT:    movdqu %xmm0, (%rax)
+; SSSE3-NEXT:    movdqu %xmm2, 16(%rdi)
+; SSSE3-NEXT:    movdqu %xmm0, (%rdi)
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: trunc16i32_16i16:
@@ -607,8 +607,8 @@ define void @trunc16i32_16i16(<16 x i32> %a) {
 ; SSE41-NEXT:    pblendw {{.*#+}} xmm3 = xmm3[0],xmm4[1],xmm3[2],xmm4[3],xmm3[4],xmm4[5],xmm3[6],xmm4[7]
 ; SSE41-NEXT:    pblendw {{.*#+}} xmm2 = xmm2[0],xmm4[1],xmm2[2],xmm4[3],xmm2[4],xmm4[5],xmm2[6],xmm4[7]
 ; SSE41-NEXT:    packusdw %xmm3, %xmm2
-; SSE41-NEXT:    movdqu %xmm2, (%rax)
-; SSE41-NEXT:    movdqu %xmm0, (%rax)
+; SSE41-NEXT:    movdqu %xmm2, 16(%rdi)
+; SSE41-NEXT:    movdqu %xmm0, (%rdi)
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: trunc16i32_16i16:
@@ -620,8 +620,8 @@ define void @trunc16i32_16i16(<16 x i32> %a) {
 ; AVX1-NEXT:    vandps %ymm2, %ymm1, %ymm1
 ; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
 ; AVX1-NEXT:    vpackusdw %xmm2, %xmm1, %xmm1
-; AVX1-NEXT:    vmovdqu %xmm1, (%rax)
-; AVX1-NEXT:    vmovdqu %xmm0, (%rax)
+; AVX1-NEXT:    vmovdqu %xmm1, 16(%rdi)
+; AVX1-NEXT:    vmovdqu %xmm0, (%rdi)
 ; AVX1-NEXT:    vzeroupper
 ; AVX1-NEXT:    retq
 ;
@@ -632,22 +632,22 @@ define void @trunc16i32_16i16(<16 x i32> %a) {
 ; AVX2-NEXT:    vpblendw {{.*#+}} ymm0 = ymm0[0],ymm2[1],ymm0[2],ymm2[3],ymm0[4],ymm2[5],ymm0[6],ymm2[7],ymm0[8],ymm2[9],ymm0[10],ymm2[11],ymm0[12],ymm2[13],ymm0[14],ymm2[15]
 ; AVX2-NEXT:    vpackusdw %ymm1, %ymm0, %ymm0
 ; AVX2-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3]
-; AVX2-NEXT:    vmovdqu %ymm0, (%rax)
+; AVX2-NEXT:    vmovdqu %ymm0, (%rdi)
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: trunc16i32_16i16:
 ; AVX512:       # %bb.0: # %entry
-; AVX512-NEXT:    vpmovdw %zmm0, (%rax)
+; AVX512-NEXT:    vpmovdw %zmm0, (%rdi)
 ; AVX512-NEXT:    vzeroupper
 ; AVX512-NEXT:    retq
 entry:
   %0 = trunc <16 x i32> %a to <16 x i16>
-  store <16 x i16> %0, ptr undef, align 4
+  store <16 x i16> %0, ptr %b, align 4
   ret void
 }
 
-define void @trunc16i32_16i16_ashr(<16 x i32> %a) {
+define void @trunc16i32_16i16_ashr(<16 x i32> %a, ptr %b) {
 ; SSE2-SSSE3-LABEL: trunc16i32_16i16_ashr:
 ; SSE2-SSSE3:       # %bb.0: # %entry
 ; SSE2-SSSE3-NEXT:    psrad $16, %xmm1
@@ -656,8 +656,8 @@ define void @trunc16i32_16i16_ashr(<16 x i32> %a) {
 ; SSE2-SSSE3-NEXT:    psrad $16, %xmm3
 ; SSE2-SSSE3-NEXT:    psrad $16, %xmm2
 ; SSE2-SSSE3-NEXT:    packssdw %xmm3, %xmm2
-; SSE2-SSSE3-NEXT:    movdqu %xmm2, (%rax)
-; SSE2-SSSE3-NEXT:    movdqu %xmm0, (%rax)
+; SSE2-SSSE3-NEXT:    movdqu %xmm2, 16(%rdi)
+; SSE2-SSSE3-NEXT:    movdqu %xmm0, (%rdi)
 ; SSE2-SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: trunc16i32_16i16_ashr:
@@ -668,8 +668,8 @@ define void @trunc16i32_16i16_ashr(<16 x i32> %a) {
 ; SSE41-NEXT:    psrld $16, %xmm1
 ; SSE41-NEXT:    psrld $16, %xmm0
 ; SSE41-NEXT:    packusdw %xmm1, %xmm0
-; SSE41-NEXT:    movdqu %xmm2, (%rax)
-; SSE41-NEXT:    movdqu %xmm0, (%rax)
+; SSE41-NEXT:    movdqu %xmm2, 16(%rdi)
+; SSE41-NEXT:    movdqu %xmm0, (%rdi)
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: trunc16i32_16i16_ashr:
@@ -682,8 +682,8 @@ define void @trunc16i32_16i16_ashr(<16 x i32> %a) {
 ; AVX1-NEXT:    vpsrld $16, %xmm2, %xmm2
 ; AVX1-NEXT:    vpsrld $16, %xmm0, %xmm0
 ; AVX1-NEXT:    vpackusdw %xmm2, %xmm0, %xmm0
-; AVX1-NEXT:    vmovdqu %xmm1, (%rax)
-; AVX1-NEXT:    vmovdqu %xmm0, (%rax)
+; AVX1-NEXT:    vmovdqu %xmm1, 16(%rdi)
+; AVX1-NEXT:    vmovdqu %xmm0, (%rdi)
 ; AVX1-NEXT:    vzeroupper
 ; AVX1-NEXT:    retq
 ;
@@ -693,24 +693,24 @@ define void @trunc16i32_16i16_ashr(<16 x i32> %a) {
 ; AVX2-NEXT:    vpsrld $16, %ymm0, %ymm0
 ; AVX2-NEXT:    vpackusdw %ymm1, %ymm0, %ymm0
 ; AVX2-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3]
-; AVX2-NEXT:    vmovdqu %ymm0, (%rax)
+; AVX2-NEXT:    vmovdqu %ymm0, (%rdi)
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: trunc16i32_16i16_ashr:
 ; AVX512:       # %bb.0: # %entry
 ; AVX512-NEXT:    vpsrld $16, %zmm0, %zmm0
-; AVX512-NEXT:    vpmovdw %zmm0, (%rax)
+; AVX512-NEXT:    vpmovdw %zmm0, (%rdi)
 ; AVX512-NEXT:    vzeroupper
 ; AVX512-NEXT:    retq
 entry:
   %0 = ashr <16 x i32> %a, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
   %1 = trunc <16 x i32> %0 to <16 x i16>
-  store <16 x i16> %1, ptr undef, align 4
+  store <16 x i16> %1, ptr %b, align 4
   ret void
 }
 
-define void @trunc16i32_16i16_lshr(<16 x i32> %a) {
+define void @trunc16i32_16i16_lshr(<16 x i32> %a, ptr %b) {
 ; SSE2-SSSE3-LABEL: trunc16i32_16i16_lshr:
 ; SSE2-SSSE3:       # %bb.0: # %entry
 ; SSE2-SSSE3-NEXT:    psrad $16, %xmm1
@@ -719,8 +719,8 @@ define void @trunc16i32_16i16_lshr(<16 x i32> %a) {
 ; SSE2-SSSE3-NEXT:    psrad $16, %xmm3
 ; SSE2-SSSE3-NEXT:    psrad $16, %xmm2
 ; SSE2-SSSE3-NEXT:    packssdw %xmm3, %xmm2
-; SSE2-SSSE3-NEXT:    movdqu %xmm2, (%rax)
-; SSE2-SSSE3-NEXT:    movdqu %xmm0, (%rax)
+; SSE2-SSSE3-NEXT:    movdqu %xmm2, 16(%rdi)
+; SSE2-SSSE3-NEXT:    movdqu %xmm0, (%rdi)
 ; SSE2-SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: trunc16i32_16i16_lshr:
@@ -731,8 +731,8 @@ define void @trunc16i32_16i16_lshr(<16 x i32> %a) {
 ; SSE41-NEXT:    psrld $16, %xmm1
 ; SSE41-NEXT:    psrld $16, %xmm0
 ; SSE41-NEXT:    packusdw %xmm1, %xmm0
-; SSE41-NEXT:    movdqu %xmm2, (%rax)
-; SSE41-NEXT:    movdqu %xmm0, (%rax)
+; SSE41-NEXT:    movdqu %xmm2, 16(%rdi)
+; SSE41-NEXT:    movdqu %xmm0, (%rdi)
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: trunc16i32_16i16_lshr:
@@ -745,8 +745,8 @@ define void @trunc16i32_16i16_lshr(<16 x i32> %a) {
 ; AVX1-NEXT:    vpsrld $16, %xmm2, %xmm2
 ; AVX1-NEXT:    vpsrld $16, %xmm0, %xmm0
 ; AVX1-NEXT:    vpackusdw %xmm2, %xmm0, %xmm0
-; AVX1-NEXT:    vmovdqu %xmm1, (%rax)
-; AVX1-NEXT:    vmovdqu %xmm0, (%rax)
+; AVX1-NEXT:    vmovdqu %xmm1, 16(%rdi)
+; AVX1-NEXT:    vmovdqu %xmm0, (%rdi)
 ; AVX1-NEXT:    vzeroupper
 ; AVX1-NEXT:    retq
 ;
@@ -756,24 +756,24 @@ define void @trunc16i32_16i16_lshr(<16 x i32> %a) {
 ; AVX2-NEXT:    vpsrld $16, %ymm0, %ymm0
 ; AVX2-NEXT:    vpackusdw %ymm1, %ymm0, %ymm0
 ; AVX2-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3]
-; AVX2-NEXT:    vmovdqu %ymm0, (%rax)
+; AVX2-NEXT:    vmovdqu %ymm0, (%rdi)
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: trunc16i32_16i16_lshr:
 ; AVX512:       # %bb.0: # %entry
 ; AVX512-NEXT:    vpsrld $16, %zmm0, %zmm0
-; AVX512-NEXT:    vpmovdw %zmm0, (%rax)
+; AVX512-NEXT:    vpmovdw %zmm0, (%rdi)
 ; AVX512-NEXT:    vzeroupper
 ; AVX512-NEXT:    retq
 entry:
   %0 = lshr <16 x i32> %a, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
   %1 = trunc <16 x i32> %0 to <16 x i16>
-  store <16 x i16> %1, ptr undef, align 4
+  store <16 x i16> %1, ptr %b, align 4
   ret void
 }
 
-define void @trunc16i32_16i8(<16 x i32> %a) {
+define void @trunc16i32_16i8(<16 x i32> %a, ptr %b) {
 ; SSE2-SSSE3-LABEL: trunc16i32_16i8:
 ; SSE2-SSSE3:       # %bb.0: # %entry
 ; SSE2-SSSE3-NEXT:    movdqa {{.*#+}} xmm4 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
@@ -784,7 +784,7 @@ define void @trunc16i32_16i8(<16 x i32> %a) {
 ; SSE2-SSSE3-NEXT:    pand %xmm4, %xmm0
 ; SSE2-SSSE3-NEXT:    packuswb %xmm1, %xmm0
 ; SSE2-SSSE3-NEXT:    packuswb %xmm2, %xmm0
-; SSE2-SSSE3-NEXT:    movdqu %xmm0, (%rax)
+; SSE2-SSSE3-NEXT:    movdqu %xmm0, (%rdi)
 ; SSE2-SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: trunc16i32_16i8:
@@ -797,7 +797,7 @@ define void @trunc16i32_16i8(<16 x i32> %a) {
 ; SSE41-NEXT:    pand %xmm4, %xmm0
 ; SSE41-NEXT:    packusdw %xmm1, %xmm0
 ; SSE41-NEXT:    packuswb %xmm2, %xmm0
-; SSE41-NEXT:    movdqu %xmm0, (%rax)
+; SSE41-NEXT:    movdqu %xmm0, (%rdi)
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: trunc16i32_16i8:
@@ -810,7 +810,7 @@ define void @trunc16i32_16i8(<16 x i32> %a) {
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
 ; AVX1-NEXT:    vpackusdw %xmm2, %xmm0, %xmm0
 ; AVX1-NEXT:    vpackuswb %xmm1, %xmm0, %xmm0
-; AVX1-NEXT:    vmovdqu %xmm0, (%rax)
+; AVX1-NEXT:    vmovdqu %xmm0, (%rdi)
 ; AVX1-NEXT:    vzeroupper
 ; AVX1-NEXT:    retq
 ;
@@ -823,22 +823,22 @@ define void @trunc16i32_16i8(<16 x i32> %a) {
 ; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
 ; AVX2-NEXT:    vpackuswb %xmm1, %xmm0, %xmm0
 ; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
-; AVX2-NEXT:    vmovdqu %xmm0, (%rax)
+; AVX2-NEXT:    vmovdqu %xmm0, (%rdi)
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: trunc16i32_16i8:
 ; AVX512:       # %bb.0: # %entry
-; AVX512-NEXT:    vpmovdb %zmm0, (%rax)
+; AVX512-NEXT:    vpmovdb %zmm0, (%rdi)
 ; AVX512-NEXT:    vzeroupper
 ; AVX512-NEXT:    retq
 entry:
   %0 = trunc <16 x i32> %a to <16 x i8>
-  store <16 x i8> %0, ptr undef, align 4
+  store <16 x i8> %0, ptr %b, align 4
   ret void
 }
 
-define void @trunc16i32_16i8_ashr(<16 x i32> %a) {
+define void @trunc16i32_16i8_ashr(<16 x i32> %a, ptr %b) {
 ; SSE2-SSSE3-LABEL: trunc16i32_16i8_ashr:
 ; SSE2-SSSE3:       # %bb.0: # %entry
 ; SSE2-SSSE3-NEXT:    psrld $24, %xmm1
@@ -848,7 +848,7 @@ define void @trunc16i32_16i8_ashr(<16 x i32> %a) {
 ; SSE2-SSSE3-NEXT:    psrld $24, %xmm2
 ; SSE2-SSSE3-NEXT:    packuswb %xmm3, %xmm2
 ; SSE2-SSSE3-NEXT:    packuswb %xmm2, %xmm0
-; SSE2-SSSE3-NEXT:    movdqu %xmm0, (%rax)
+; SSE2-SSSE3-NEXT:    movdqu %xmm0, (%rdi)
 ; SSE2-SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: trunc16i32_16i8_ashr:
@@ -860,7 +860,7 @@ define void @trunc16i32_16i8_ashr(<16 x i32> %a) {
 ; SSE41-NEXT:    psrld $24, %xmm2
 ; SSE41-NEXT:    packusdw %xmm3, %xmm2
 ; SSE41-NEXT:    packuswb %xmm2, %xmm0
-; SSE41-NEXT:    movdqu %xmm0, (%rax)
+; SSE41-NEXT:    movdqu %xmm0, (%rdi)
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: trunc16i32_16i8_ashr:
@@ -874,7 +874,7 @@ define void @trunc16i32_16i8_ashr(<16 x i32> %a) {
 ; AVX1-NEXT:    vpsrld $24, %xmm1, %xmm1
 ; AVX1-NEXT:    vpackusdw %xmm2, %xmm1, %xmm1
 ; AVX1-NEXT:    vpackuswb %xmm1, %xmm0, %xmm0
-; AVX1-NEXT:    vmovdqu %xmm0, (%rax)
+; AVX1-NEXT:    vmovdqu %xmm0, (%rdi)
 ; AVX1-NEXT:    vzeroupper
 ; AVX1-NEXT:    retq
 ;
@@ -886,24 +886,24 @@ define void @trunc16i32_16i8_ashr(<16 x i32> %a) {
 ; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
 ; AVX2-NEXT:    vpackuswb %xmm1, %xmm0, %xmm0
 ; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
-; AVX2-NEXT:    vmovdqu %xmm0, (%rax)
+; AVX2-NEXT:    vmovdqu %xmm0, (%rdi)
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: trunc16i32_16i8_ashr:
 ; AVX512:       # %bb.0: # %entry
 ; AVX512-NEXT:    vpsrld $24, %zmm0, %zmm0
-; AVX512-NEXT:    vpmovdb %zmm0, (%rax)
+; AVX512-NEXT:    vpmovdb %zmm0, (%rdi)
 ; AVX512-NEXT:    vzeroupper
 ; AVX512-NEXT:    retq
 entry:
   %0 = ashr <16 x i32> %a, <i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24>
   %1 = trunc <16 x i32> %0 to <16 x i8>
-  store <16 x i8> %1, ptr undef, align 4
+  store <16 x i8> %1, ptr %b, align 4
   ret void
 }
 
-define void @trunc16i32_16i8_lshr(<16 x i32> %a) {
+define void @trunc16i32_16i8_lshr(<16 x i32> %a, ptr %b) {
 ; SSE2-SSSE3-LABEL: trunc16i32_16i8_lshr:
 ; SSE2-SSSE3:       # %bb.0: # %entry
 ; SSE2-SSSE3-NEXT:    psrld $24, %xmm1
@@ -913,7 +913,7 @@ define void @trunc16i32_16i8_lshr(<16 x i32> %a) {
 ; SSE2-SSSE3-NEXT:    psrld $24, %xmm2
 ; SSE2-SSSE3-NEXT:    packuswb %xmm3, %xmm2
 ; SSE2-SSSE3-NEXT:    packuswb %xmm2, %xmm0
-; SSE2-SSSE3-NEXT:    movdqu %xmm0, (%rax)
+; SSE2-SSSE3-NEXT:    movdqu %xmm0, (%rdi)
 ; SSE2-SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: trunc16i32_16i8_lshr:
@@ -925,7 +925,7 @@ define void @trunc16i32_16i8_lshr(<16 x i32> %a) {
 ; SSE41-NEXT:    psrld $24, %xmm2
 ; SSE41-NEXT:    packusdw %xmm3, %xmm2
 ; SSE41-NEXT:    packuswb %xmm2, %xmm0
-; SSE41-NEXT:    movdqu %xmm0, (%rax)
+; SSE41-NEXT:    movdqu %xmm0, (%rdi)
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: trunc16i32_16i8_lshr:
@@ -939,7 +939,7 @@ define void @trunc16i32_16i8_lshr(<16 x i32> %a) {
 ; AVX1-NEXT:    vpsrld $24, %xmm1, %xmm1
 ; AVX1-NEXT:    vpackusdw %xmm2, %xmm1, %xmm1
 ; AVX1-NEXT:    vpackuswb %xmm1, %xmm0, %xmm0
-; AVX1-NEXT:    vmovdqu %xmm0, (%rax)
+; AVX1-NEXT:    vmovdqu %xmm0, (%rdi)
 ; AVX1-NEXT:    vzeroupper
 ; AVX1-NEXT:    retq
 ;
@@ -951,32 +951,32 @@ define void @trunc16i32_16i8_lshr(<16 x i32> %a) {
 ; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
 ; AVX2-NEXT:    vpackuswb %xmm1, %xmm0, %xmm0
 ; AVX2-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
-; AVX2-NEXT:    vmovdqu %xmm0, (%rax)
+; AVX2-NEXT:    vmovdqu %xmm0, (%rdi)
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: trunc16i32_16i8_lshr:
 ; AVX512:       # %bb.0: # %entry
 ; AVX512-NEXT:    vpsrld $24, %zmm0, %zmm0
-; AVX512-NEXT:    vpmovdb %zmm0, (%rax)
+; AVX512-NEXT:    vpmovdb %zmm0, (%rdi)
 ; AVX512-NEXT:    vzeroupper
 ; AVX512-NEXT:    retq
 entry:
   %0 = lshr <16 x i32> %a, <i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24>
   %1 = trunc <16 x i32> %0 to <16 x i8>
-  store <16 x i8> %1, ptr undef, align 4
+  store <16 x i8> %1, ptr %b, align 4
   ret void
 }
 
 ;PR25684
-define void @trunc16i16_16i8(<16 x i16> %a) {
+define void @trunc16i16_16i8(<16 x i16> %a, ptr %b) {
 ; SSE2-SSSE3-LABEL: trunc16i16_16i8:
 ; SSE2-SSSE3:       # %bb.0: # %entry
 ; SSE2-SSSE3-NEXT:    movdqa {{.*#+}} xmm2 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0]
 ; SSE2-SSSE3-NEXT:    pand %xmm2, %xmm1
 ; SSE2-SSSE3-NEXT:    pand %xmm2, %xmm0
 ; SSE2-SSSE3-NEXT:    packuswb %xmm1, %xmm0
-; SSE2-SSSE3-NEXT:    movdqu %xmm0, (%rax)
+; SSE2-SSSE3-NEXT:    movdqu %xmm0, (%rdi)
 ; SSE2-SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: trunc16i16_16i8:
@@ -985,7 +985,7 @@ define void @trunc16i16_16i8(<16 x i16> %a) {
 ; SSE41-NEXT:    pand %xmm2, %xmm1
 ; SSE41-NEXT:    pand %xmm2, %xmm0
 ; SSE41-NEXT:    packuswb %xmm1, %xmm0
-; SSE41-NEXT:    movdqu %xmm0, (%rax)
+; SSE41-NEXT:    movdqu %xmm0, (%rdi)
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: trunc16i16_16i8:
@@ -993,7 +993,7 @@ define void @trunc16i16_16i8(<16 x i16> %a) {
 ; AVX1-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
 ; AVX1-NEXT:    vpackuswb %xmm1, %xmm0, %xmm0
-; AVX1-NEXT:    vmovdqu %xmm0, (%rax)
+; AVX1-NEXT:    vmovdqu %xmm0, (%rdi)
 ; AVX1-NEXT:    vzeroupper
 ; AVX1-NEXT:    retq
 ;
@@ -1002,21 +1002,21 @@ define void @trunc16i16_16i8(<16 x i16> %a) {
 ; AVX2-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
 ; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
 ; AVX2-NEXT:    vpackuswb %xmm1, %xmm0, %xmm0
-; AVX2-NEXT:    vmovdqu %xmm0, (%rax)
+; AVX2-NEXT:    vmovdqu %xmm0, (%rdi)
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
 ;
 ; AVX512F-LABEL: trunc16i16_16i8:
 ; AVX512F:       # %bb.0: # %entry
 ; AVX512F-NEXT:    vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
-; AVX512F-NEXT:    vpmovdb %zmm0, (%rax)
+; AVX512F-NEXT:    vpmovdb %zmm0, (%rdi)
 ; AVX512F-NEXT:    vzeroupper
 ; AVX512F-NEXT:    retq
 ;
 ; AVX512VL-LABEL: trunc16i16_16i8:
 ; AVX512VL:       # %bb.0: # %entry
 ; AVX512VL-NEXT:    vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
-; AVX512VL-NEXT:    vpmovdb %zmm0, (%rax)
+; AVX512VL-NEXT:    vpmovdb %zmm0, (%rdi)
 ; AVX512VL-NEXT:    vzeroupper
 ; AVX512VL-NEXT:    retq
 ;
@@ -1024,28 +1024,28 @@ define void @trunc16i16_16i8(<16 x i16> %a) {
 ; AVX512BW:       # %bb.0: # %entry
 ; AVX512BW-NEXT:    # kill: def $ymm0 killed $ymm0 def $zmm0
 ; AVX512BW-NEXT:    vpmovwb %zmm0, %ymm0
-; AVX512BW-NEXT:    vmovdqu %xmm0, (%rax)
+; AVX512BW-NEXT:    vmovdqu %xmm0, (%rdi)
 ; AVX512BW-NEXT:    vzeroupper
 ; AVX512BW-NEXT:    retq
 ;
 ; AVX512BWVL-LABEL: trunc16i16_16i8:
 ; AVX512BWVL:       # %bb.0: # %entry
-; AVX512BWVL-NEXT:    vpmovwb %ymm0, (%rax)
+; AVX512BWVL-NEXT:    vpmovwb %ymm0, (%rdi)
 ; AVX512BWVL-NEXT:    vzeroupper
 ; AVX512BWVL-NEXT:    retq
 entry:
   %0 = trunc <16 x i16> %a to <16 x i8>
-  store <16 x i8> %0, ptr undef, align 4
+  store <16 x i8> %0, ptr %b, align 4
   ret void
 }
 
-define void @trunc16i16_16i8_ashr(<16 x i16> %a) {
+define void @trunc16i16_16i8_ashr(<16 x i16> %a, ptr %b) {
 ; SSE-LABEL: trunc16i16_16i8_ashr:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    psrlw $8, %xmm1
 ; SSE-NEXT:    psrlw $8, %xmm0
 ; SSE-NEXT:    packuswb %xmm1, %xmm0
-; SSE-NEXT:    movdqu %xmm0, (%rax)
+; SSE-NEXT:    movdqu %xmm0, (%rdi)
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: trunc16i16_16i8_ashr:
@@ -1054,7 +1054,7 @@ define void @trunc16i16_16i8_ashr(<16 x i16> %a) {
 ; AVX1-NEXT:    vpsrlw $8, %xmm1, %xmm1
 ; AVX1-NEXT:    vpsrlw $8, %xmm0, %xmm0
 ; AVX1-NEXT:    vpackuswb %xmm1, %xmm0, %xmm0
-; AVX1-NEXT:    vmovdqu %xmm0, (%rax)
+; AVX1-NEXT:    vmovdqu %xmm0, (%rdi)
 ; AVX1-NEXT:    vzeroupper
 ; AVX1-NEXT:    retq
 ;
@@ -1063,7 +1063,7 @@ define void @trunc16i16_16i8_ashr(<16 x i16> %a) {
 ; AVX2-NEXT:    vpsrlw $8, %ymm0, %ymm0
 ; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
 ; AVX2-NEXT:    vpackuswb %xmm1, %xmm0, %xmm0
-; AVX2-NEXT:    vmovdqu %xmm0, (%rax)
+; AVX2-NEXT:    vmovdqu %xmm0, (%rdi)
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
 ;
@@ -1071,7 +1071,7 @@ define void @trunc16i16_16i8_ashr(<16 x i16> %a) {
 ; AVX512F:       # %bb.0: # %entry
 ; AVX512F-NEXT:    vpsrlw $8, %ymm0, %ymm0
 ; AVX512F-NEXT:    vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
-; AVX512F-NEXT:    vpmovdb %zmm0, (%rax)
+; AVX512F-NEXT:    vpmovdb %zmm0, (%rdi)
 ; AVX512F-NEXT:    vzeroupper
 ; AVX512F-NEXT:    retq
 ;
@@ -1079,7 +1079,7 @@ define void @trunc16i16_16i8_ashr(<16 x i16> %a) {
 ; AVX512VL:       # %bb.0: # %entry
 ; AVX512VL-NEXT:    vpsrlw $8, %ymm0, %ymm0
 ; AVX512VL-NEXT:    vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
-; AVX512VL-NEXT:    vpmovdb %zmm0, (%rax)
+; AVX512VL-NEXT:    vpmovdb %zmm0, (%rdi)
 ; AVX512VL-NEXT:    vzeroupper
 ; AVX512VL-NEXT:    retq
 ;
@@ -1087,30 +1087,30 @@ define void @trunc16i16_16i8_ashr(<16 x i16> %a) {
 ; AVX512BW:       # %bb.0: # %entry
 ; AVX512BW-NEXT:    vpsrlw $8, %ymm0, %ymm0
 ; AVX512BW-NEXT:    vpmovwb %zmm0, %ymm0
-; AVX512BW-NEXT:    vmovdqu %xmm0, (%rax)
+; AVX512BW-NEXT:    vmovdqu %xmm0, (%rdi)
 ; AVX512BW-NEXT:    vzeroupper
 ; AVX512BW-NEXT:    retq
 ;
 ; AVX512BWVL-LABEL: trunc16i16_16i8_ashr:
 ; AVX512BWVL:       # %bb.0: # %entry
 ; AVX512BWVL-NEXT:    vpsrlw $8, %ymm0, %ymm0
-; AVX512BWVL-NEXT:    vpmovwb %ymm0, (%rax)
+; AVX512BWVL-NEXT:    vpmovwb %ymm0, (%rdi)
 ; AVX512BWVL-NEXT:    vzeroupper
 ; AVX512BWVL-NEXT:    retq
 entry:
   %0 = ashr <16 x i16> %a, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
   %1 = trunc <16 x i16> %0 to <16 x i8>
-  store <16 x i8> %1, ptr undef, align 4
+  store <16 x i8> %1, ptr %b, align 4
   ret void
 }
 
-define void @trunc16i16_16i8_lshr(<16 x i16> %a) {
+define void @trunc16i16_16i8_lshr(<16 x i16> %a, ptr %b) {
 ; SSE-LABEL: trunc16i16_16i8_lshr:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    psrlw $8, %xmm1
 ; SSE-NEXT:    psrlw $8, %xmm0
 ; SSE-NEXT:    packuswb %xmm1, %xmm0
-; SSE-NEXT:    movdqu %xmm0, (%rax)
+; SSE-NEXT:    movdqu %xmm0, (%rdi)
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: trunc16i16_16i8_lshr:
@@ -1119,7 +1119,7 @@ define void @trunc16i16_16i8_lshr(<16 x i16> %a) {
 ; AVX1-NEXT:    vpsrlw $8, %xmm1, %xmm1
 ; AVX1-NEXT:    vpsrlw $8, %xmm0, %xmm0
 ; AVX1-NEXT:    vpackuswb %xmm1, %xmm0, %xmm0
-; AVX1-NEXT:    vmovdqu %xmm0, (%rax)
+; AVX1-NEXT:    vmovdqu %xmm0, (%rdi)
 ; AVX1-NEXT:    vzeroupper
 ; AVX1-NEXT:    retq
 ;
@@ -1128,7 +1128,7 @@ define void @trunc16i16_16i8_lshr(<16 x i16> %a) {
 ; AVX2-NEXT:    vpsrlw $8, %ymm0, %ymm0
 ; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
 ; AVX2-NEXT:    vpackuswb %xmm1, %xmm0, %xmm0
-; AVX2-NEXT:    vmovdqu %xmm0, (%rax)
+; AVX2-NEXT:    vmovdqu %xmm0, (%rdi)
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
 ;
@@ -1136,7 +1136,7 @@ define void @trunc16i16_16i8_lshr(<16 x i16> %a) {
 ; AVX512F:       # %bb.0: # %entry
 ; AVX512F-NEXT:    vpsrlw $8, %ymm0, %ymm0
 ; AVX512F-NEXT:    vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
-; AVX512F-NEXT:    vpmovdb %zmm0, (%rax)
+; AVX512F-NEXT:    vpmovdb %zmm0, (%rdi)
 ; AVX512F-NEXT:    vzeroupper
 ; AVX512F-NEXT:    retq
 ;
@@ -1144,7 +1144,7 @@ define void @trunc16i16_16i8_lshr(<16 x i16> %a) {
 ; AVX512VL:       # %bb.0: # %entry
 ; AVX512VL-NEXT:    vpsrlw $8, %ymm0, %ymm0
 ; AVX512VL-NEXT:    vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
-; AVX512VL-NEXT:    vpmovdb %zmm0, (%rax)
+; AVX512VL-NEXT:    vpmovdb %zmm0, (%rdi)
 ; AVX512VL-NEXT:    vzeroupper
 ; AVX512VL-NEXT:    retq
 ;
@@ -1152,24 +1152,24 @@ define void @trunc16i16_16i8_lshr(<16 x i16> %a) {
 ; AVX512BW:       # %bb.0: # %entry
 ; AVX512BW-NEXT:    vpsrlw $8, %ymm0, %ymm0
 ; AVX512BW-NEXT:    vpmovwb %zmm0, %ymm0
-; AVX512BW-NEXT:    vmovdqu %xmm0, (%rax)
+; AVX512BW-NEXT:    vmovdqu %xmm0, (%rdi)
 ; AVX512BW-NEXT:    vzeroupper
 ; AVX512BW-NEXT:    retq
 ;
 ; AVX512BWVL-LABEL: trunc16i16_16i8_lshr:
 ; AVX512BWVL:       # %bb.0: # %entry
 ; AVX512BWVL-NEXT:    vpsrlw $8, %ymm0, %ymm0
-; AVX512BWVL-NEXT:    vpmovwb %ymm0, (%rax)
+; AVX512BWVL-NEXT:    vpmovwb %ymm0, (%rdi)
 ; AVX512BWVL-NEXT:    vzeroupper
 ; AVX512BWVL-NEXT:    retq
 entry:
   %0 = lshr <16 x i16> %a, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
   %1 = trunc <16 x i16> %0 to <16 x i8>
-  store <16 x i8> %1, ptr undef, align 4
+  store <16 x i8> %1, ptr %b, align 4
   ret void
 }
 
-define void @trunc32i16_32i8(<32 x i16> %a) {
+define void @trunc32i16_32i8(<32 x i16> %a, ptr %b) {
 ; SSE2-SSSE3-LABEL: trunc32i16_32i8:
 ; SSE2-SSSE3:       # %bb.0: # %entry
 ; SSE2-SSSE3-NEXT:    movdqa {{.*#+}} xmm4 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0]
@@ -1179,8 +1179,8 @@ define void @trunc32i16_32i8(<32 x i16> %a) {
 ; SSE2-SSSE3-NEXT:    pand %xmm4, %xmm3
 ; SSE2-SSSE3-NEXT:    pand %xmm4, %xmm2
 ; SSE2-SSSE3-NEXT:    packuswb %xmm3, %xmm2
-; SSE2-SSSE3-NEXT:    movdqu %xmm2, (%rax)
-; SSE2-SSSE3-NEXT:    movdqu %xmm0, (%rax)
+; SSE2-SSSE3-NEXT:    movdqu %xmm2, 16(%rdi)
+; SSE2-SSSE3-NEXT:    movdqu %xmm0, (%rdi)
 ; SSE2-SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: trunc32i16_32i8:
@@ -1192,8 +1192,8 @@ define void @trunc32i16_32i8(<32 x i16> %a) {
 ; SSE41-NEXT:    pand %xmm4, %xmm3
 ; SSE41-NEXT:    pand %xmm4, %xmm2
 ; SSE41-NEXT:    packuswb %xmm3, %xmm2
-; SSE41-NEXT:    movdqu %xmm2, (%rax)
-; SSE41-NEXT:    movdqu %xmm0, (%rax)
+; SSE41-NEXT:    movdqu %xmm2, 16(%rdi)
+; SSE41-NEXT:    movdqu %xmm0, (%rdi)
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: trunc32i16_32i8:
@@ -1205,8 +1205,8 @@ define void @trunc32i16_32i8(<32 x i16> %a) {
 ; AVX1-NEXT:    vandps %ymm2, %ymm1, %ymm1
 ; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
 ; AVX1-NEXT:    vpackuswb %xmm2, %xmm1, %xmm1
-; AVX1-NEXT:    vmovdqu %xmm1, (%rax)
-; AVX1-NEXT:    vmovdqu %xmm0, (%rax)
+; AVX1-NEXT:    vmovdqu %xmm1, 16(%rdi)
+; AVX1-NEXT:    vmovdqu %xmm0, (%rdi)
 ; AVX1-NEXT:    vzeroupper
 ; AVX1-NEXT:    retq
 ;
@@ -1217,7 +1217,7 @@ define void @trunc32i16_32i8(<32 x i16> %a) {
 ; AVX2-NEXT:    vpand %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpackuswb %ymm1, %ymm0, %ymm0
 ; AVX2-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3]
-; AVX2-NEXT:    vmovdqu %ymm0, (%rax)
+; AVX2-NEXT:    vmovdqu %ymm0, (%rdi)
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
 ;
@@ -1225,9 +1225,9 @@ define void @trunc32i16_32i8(<32 x i16> %a) {
 ; AVX512F:       # %bb.0: # %entry
 ; AVX512F-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
 ; AVX512F-NEXT:    vpmovzxwd {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero
-; AVX512F-NEXT:    vpmovdb %zmm1, (%rax)
+; AVX512F-NEXT:    vpmovdb %zmm1, 16(%rdi)
 ; AVX512F-NEXT:    vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
-; AVX512F-NEXT:    vpmovdb %zmm0, (%rax)
+; AVX512F-NEXT:    vpmovdb %zmm0, (%rdi)
 ; AVX512F-NEXT:    vzeroupper
 ; AVX512F-NEXT:    retq
 ;
@@ -1235,26 +1235,26 @@ define void @trunc32i16_32i8(<32 x i16> %a) {
 ; AVX512VL:       # %bb.0: # %entry
 ; AVX512VL-NEXT:    vextracti64x4 $1, %zmm0, %ymm1
 ; AVX512VL-NEXT:    vpmovzxwd {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero
-; AVX512VL-NEXT:    vpmovdb %zmm1, (%rax)
+; AVX512VL-NEXT:    vpmovdb %zmm1, 16(%rdi)
 ; AVX512VL-NEXT:    vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
-; AVX512VL-NEXT:    vpmovdb %zmm0, (%rax)
+; AVX512VL-NEXT:    vpmovdb %zmm0, (%rdi)
 ; AVX512VL-NEXT:    vzeroupper
 ; AVX512VL-NEXT:    retq
 ;
 ; AVX512BW-LABEL: trunc32i16_32i8:
 ; AVX512BW:       # %bb.0: # %entry
-; AVX512BW-NEXT:    vpmovwb %zmm0, (%rax)
+; AVX512BW-NEXT:    vpmovwb %zmm0, (%rdi)
 ; AVX512BW-NEXT:    vzeroupper
 ; AVX512BW-NEXT:    retq
 ;
 ; AVX512BWVL-LABEL: trunc32i16_32i8:
 ; AVX512BWVL:       # %bb.0: # %entry
-; AVX512BWVL-NEXT:    vpmovwb %zmm0, (%rax)
+; AVX512BWVL-NEXT:    vpmovwb %zmm0, (%rdi)
 ; AVX512BWVL-NEXT:    vzeroupper
 ; AVX512BWVL-NEXT:    retq
 entry:
   %0 = trunc <32 x i16> %a to <32 x i8>
-  store <32 x i8> %0, ptr undef, align 4
+  store <32 x i8> %0, ptr %b, align 4
   ret void
 }
 
diff --git a/llvm/test/DebugInfo/Generic/inline-scopes.ll b/llvm/test/DebugInfo/Generic/inline-scopes.ll
index 8e7543eb16e69..45ecdd0594f64 100644
--- a/llvm/test/DebugInfo/Generic/inline-scopes.ll
+++ b/llvm/test/DebugInfo/Generic/inline-scopes.ll
@@ -20,16 +20,29 @@
 ; }
 
 ; Ensure that lexical_blocks within inlined_subroutines are preserved/emitted.
+; CHECK:      DW_TAG_subprogram
+; CHECK-NEXT: DW_AT_linkage_name ("_Z2f1v")
+; CHECK:      [[ADDR1:0x[0-9a-f]+]]: DW_TAG_lexical_block
+; CHECK:      DW_TAG_subprogram
+; CHECK-NEXT: DW_AT_linkage_name ("_Z2f2v")
+; CHECK:      [[ADDR2:0x[0-9a-f]+]]: DW_TAG_lexical_block
 ; CHECK: DW_TAG_inlined_subroutine
 ; CHECK-NOT: DW_TAG
 ; CHECK-NOT: NULL
-; CHECK: DW_TAG_lexical_block
+; CHECK:      DW_TAG_lexical_block
+; CHECK-NOT: {{DW_TAG|NULL}}
+; CHECK:      DW_AT_abstract_origin ([[ADDR1]]
 ; CHECK-NOT: DW_TAG
 ; CHECK-NOT: NULL
 ; CHECK: DW_TAG_variable
 ; Ensure that file changes don't interfere with creating inlined subroutines.
 ; (see the line directive inside 'f2' in thesource)
 ; CHECK: DW_TAG_inlined_subroutine
+; CHECK-NOT: {{DW_TAG|NULL}}
+; CHECK:      DW_TAG_lexical_block
+; CHECK-NOT: {{DW_TAG|NULL}}
+; CHECK:      DW_AT_abstract_origin ([[ADDR2]]
+; CHECK-NOT: {{DW_TAG|NULL}}
 ; CHECK:   DW_TAG_variable
 ; CHECK-NOT: DW_TAG
 ; CHECK:     DW_AT_abstract_origin
diff --git a/llvm/test/DebugInfo/Generic/lexical-block-abstract-origin.ll b/llvm/test/DebugInfo/Generic/lexical-block-abstract-origin.ll
new file mode 100644
index 0000000000000..cbe2b818fba38
--- /dev/null
+++ b/llvm/test/DebugInfo/Generic/lexical-block-abstract-origin.ll
@@ -0,0 +1,56 @@
+; RUN: %llc_dwarf -filetype=obj -O0 %s -o - | llvm-dwarfdump -debug-info - | FileCheck %s
+
+; Check that DW_AT_abstract_origin is generated for concrete lexical block.
+
+; Generated from:
+; inline __attribute__((always_inline)) int foo(int x) {
+;   {
+;     int y = x + 5;
+;     return y - 10;
+;   }
+; }
+;
+; int bar(int x) {
+;   int y = foo(7);
+;   return y + 8;
+; }
+
+; CHECK:      DW_TAG_subprogram
+; CHECK-NEXT:   DW_AT_name  ("foo")
+; CHECK-NOT:    {{DW_TAG|NULL}}
+; CHECK:        [[LB:.*]]: DW_TAG_lexical_block
+
+; CHECK:        DW_TAG_inlined_subroutine
+; CHECK-NEXT:     DW_AT_abstract_origin {{.*}} "foo"
+; CHECK-NOT:      {{DW_TAG|NULL}}
+; CHECK:          DW_TAG_lexical_block
+; CHECK-NOT:        {{DW_TAG|NULL}}
+; CHECK:            DW_AT_abstract_origin {{.*}}[[LB]]
+
+target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
+target triple = "arm64-apple-macosx15.0.0"
+
+define i32 @bar() !dbg !9 {
+entry:
+  %y.i = alloca i32, align 4
+    #dbg_declare(ptr %y.i, !22, !DIExpression(), !24)
+  store i32 0, ptr %y.i, align 4, !dbg !24
+  %1 = load i32, ptr %y.i, align 4
+  ret i32 %1
+}
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!3}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, emissionKind: FullDebug)
+!1 = !DIFile(filename: "test.c", directory: "")
+!3 = !{i32 2, !"Debug Info Version", i32 3}
+!9 = distinct !DISubprogram(name: "bar", scope: !1, file: !1, line: 8, type: !10, spFlags: DISPFlagDefinition, unit: !0)
+!10 = !DISubroutineType(types: !13)
+!12 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
+!13 = !{}
+!19 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 1, type: !10, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !0)
+!21 = distinct !DILocation(line: 9, column: 11, scope: !9)
+!22 = !DILocalVariable(name: "y", scope: !23, file: !1, line: 3, type: !12)
+!23 = distinct !DILexicalBlock(scope: !19, file: !1, line: 2, column: 3)
+!24 = !DILocation(line: 3, column: 9, scope: !23, inlinedAt: !21)
diff --git a/llvm/test/DebugInfo/NVPTX/debug-info.ll b/llvm/test/DebugInfo/NVPTX/debug-info.ll
index fa2925af37971..1fc945b364c93 100644
--- a/llvm/test/DebugInfo/NVPTX/debug-info.ll
+++ b/llvm/test/DebugInfo/NVPTX/debug-info.ll
@@ -20,7 +20,7 @@
 ; CHECK: )
 ; CHECK: {
 ; CHECK-DAG: .reg .pred      %p<2>;
-; CHECK-DAG: .reg .f32       %f<5>;
+; CHECK-DAG: .reg .b32       %f<5>;
 ; CHECK-DAG: .reg .b32       %r<6>;
 ; CHECK-DAG: .reg .b64       %rd<8>;
 ; CHECK: .loc [[DEBUG_INFO_CU:[0-9]+]] 5 0
diff --git a/llvm/test/DebugInfo/X86/lexical-block-file-inline.ll b/llvm/test/DebugInfo/X86/lexical-block-file-inline.ll
index 15d0785bde93d..e8136f8eea965 100644
--- a/llvm/test/DebugInfo/X86/lexical-block-file-inline.ll
+++ b/llvm/test/DebugInfo/X86/lexical-block-file-inline.ll
@@ -28,9 +28,11 @@
 ; CHECK:    DW_TAG_subprogram
 ; CHECK-NOT: {{DW_TAG|NULL}}
 ; CHECK:      DW_AT_abstract_origin {{.*}} {[[Offset_bar:0x[0-9abcdef]+]]}
-; CHECK-NOT: {{DW_TAG|NULL}}
+; CHECK-NOT:  {{DW_TAG|NULL}}
 ; CHECK:      DW_TAG_lexical_block
-; CHECK-NOT: {{DW_TAG|NULL}}
+; CHECK-NOT:    {{DW_TAG|NULL}}
+; CHECK:        DW_AT_abstract_origin {{.*}}[[Offset_lb:0x[0-9a-f]+]]
+; CHECK-NOT:    {{DW_TAG|NULL}}
 ; CHECK:        DW_TAG_variable
 
 ;; Abstract "bar" function
@@ -40,7 +42,7 @@
 ; CHECK-NOT: {{DW_TAG|NULL}}
 ; CHECK:      DW_AT_inline
 ; CHECK-NOT: {{DW_TAG|NULL}}
-; CHECK:      DW_TAG_lexical_block
+; CHECK:      [[Offset_lb]]: DW_TAG_lexical_block
 ; CHECK-NOT: {{DW_TAG|NULL}}
 ; CHECK:        DW_TAG_variable
 ; CHECK-NOT: {{DW_TAG|NULL}}
@@ -56,8 +58,10 @@
 ; CHECK-NEXT:   DW_AT_abstract_origin {{.*}} {[[Offset_bar]]}
 ; CHECK-NOT: {{DW_TAG|NULL}}
 ; CHECK:        DW_TAG_lexical_block
-; CHECK-NOT: {{DW_TAG|NULL}}
-; CHECK:          DW_TAG_variable
+; CHECK-NOT:      {{DW_TAG|NULL}}
+; CHECK:          DW_AT_abstract_origin {{.*}}[[Offset_lb]]
+; CHECK-NOT:    {{DW_TAG|NULL}}
+; CHECK:        DW_TAG_variable
 
 ; Function Attrs: alwaysinline nounwind
 define i32 @_Z3barv() #0 !dbg !4 {
diff --git a/llvm/test/DebugInfo/X86/missing-abstract-variable.ll b/llvm/test/DebugInfo/X86/missing-abstract-variable.ll
index 572dca2c2cb6c..21363805aff2f 100644
--- a/llvm/test/DebugInfo/X86/missing-abstract-variable.ll
+++ b/llvm/test/DebugInfo/X86/missing-abstract-variable.ll
@@ -37,7 +37,7 @@
 ; CHECK-NOT: DW_TAG
 ; CHECK:     DW_AT_name ("b")
 ; CHECK-NOT: {{DW_TAG|NULL}}
-; CHECK:       DW_TAG_lexical_block
+; CHECK:       [[LB_DECL:.*]]: DW_TAG_lexical_block
 ; CHECK-NOT: {{DW_TAG|NULL}}
 ; CHECK:   DW_TAG_variable
 ; CHECK-NOT: DW_TAG
@@ -82,7 +82,9 @@
 
 ; CHECK-NOT: {{DW_TAG|NULL}}
 ; CHECK:     DW_TAG_lexical_block
-; CHECK-NOT: {{DW_TAG|NULL}}
+; CHECK-NOT:   {{DW_TAG|NULL}}
+; CHECK:       DW_AT_abstract_origin {{.*}}[[LB_DECL]]
+; CHECK-NOT:   {{DW_TAG|NULL}}
 ; CHECK:       DW_TAG_variable
 ; CHECK-NOT: DW_TAG
 ; CHECK:         DW_AT_abstract_origin {{.*}} "s"
diff --git a/llvm/test/Instrumentation/ThreadSanitizer/capture.ll b/llvm/test/Instrumentation/ThreadSanitizer/capture.ll
index 9cd5d77f4753e..e1b9e03b88446 100644
--- a/llvm/test/Instrumentation/ThreadSanitizer/capture.ll
+++ b/llvm/test/Instrumentation/ThreadSanitizer/capture.ll
@@ -47,6 +47,21 @@ entry:
 ; CHECK: __tsan_write
 ; CHECK: ret void
 
+define void @captured3() nounwind uwtable sanitize_thread {
+entry:
+  %stkobj = alloca [2 x i32], align 8
+  ; escapes due to store into global
+  store ptr %stkobj, ptr @sink, align 8
+  ; derived is captured as its base object is captured
+  %derived = getelementptr inbounds i32, ptr %stkobj, i64 1
+  store i32 42, ptr %derived, align 4
+  ret void
+}
+; CHECK-LABEL: define void @captured3
+; CHECK: __tsan_write
+; CHECK: __tsan_write
+; CHECK: ret void
+
 define void @notcaptured0() nounwind uwtable sanitize_thread {
 entry:
   %ptr = alloca i32, align 4
diff --git a/llvm/test/Transforms/CodeGenPrepare/unfold-pow2-test-vec.ll b/llvm/test/Transforms/CodeGenPrepare/unfold-pow2-test-vec.ll
new file mode 100644
index 0000000000000..9e4a10d9eb864
--- /dev/null
+++ b/llvm/test/Transforms/CodeGenPrepare/unfold-pow2-test-vec.ll
@@ -0,0 +1,85 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -p 'require<profile-summary>,function(codegenprepare)' -S %s \
+; RUN:   | FileCheck %s --check-prefix=SLOW
+; RUN: opt -p 'require<profile-summary>,function(codegenprepare)' -S --mattr=+zvbb %s \
+; RUN:   | FileCheck %s --check-prefix=FAST
+; REQUIRES: riscv-registered-target
+
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
+target triple = "riscv64"
+
+define <4 x i1> @test_ult_2(<4 x i64> %x) {
+; SLOW-LABEL: define <4 x i1> @test_ult_2(
+; SLOW-SAME: <4 x i64> [[X:%.*]]) {
+; SLOW-NEXT:    [[TMP0:%.*]] = add <4 x i64> [[X]], splat (i64 -1)
+; SLOW-NEXT:    [[TMP1:%.*]] = and <4 x i64> [[X]], [[TMP0]]
+; SLOW-NEXT:    [[CMP1:%.*]] = icmp eq <4 x i64> [[TMP1]], zeroinitializer
+; SLOW-NEXT:    ret <4 x i1> [[CMP1]]
+;
+; FAST-LABEL: define <4 x i1> @test_ult_2(
+; FAST-SAME: <4 x i64> [[X:%.*]]) #[[ATTR0:[0-9]+]] {
+; FAST-NEXT:    [[CTPOP:%.*]] = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> [[X]])
+; FAST-NEXT:    [[CMP1:%.*]] = icmp ult <4 x i64> [[CTPOP]], splat (i64 2)
+; FAST-NEXT:    ret <4 x i1> [[CMP1]]
+;
+  %ctpop = call <4 x i64> @llvm.ctpop(<4 x i64> %x)
+  %cmp = icmp ult <4 x i64> %ctpop, splat (i64 2)
+  ret <4 x i1> %cmp
+}
+
+define <4 x i1> @test_ugt_1(<4 x i64> %x) {
+; SLOW-LABEL: define <4 x i1> @test_ugt_1(
+; SLOW-SAME: <4 x i64> [[X:%.*]]) {
+; SLOW-NEXT:    [[TMP0:%.*]] = add <4 x i64> [[X]], splat (i64 -1)
+; SLOW-NEXT:    [[TMP1:%.*]] = and <4 x i64> [[X]], [[TMP0]]
+; SLOW-NEXT:    [[CMP1:%.*]] = icmp ne <4 x i64> [[TMP1]], zeroinitializer
+; SLOW-NEXT:    ret <4 x i1> [[CMP1]]
+;
+; FAST-LABEL: define <4 x i1> @test_ugt_1(
+; FAST-SAME: <4 x i64> [[X:%.*]]) #[[ATTR0]] {
+; FAST-NEXT:    [[CTPOP:%.*]] = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> [[X]])
+; FAST-NEXT:    [[CMP1:%.*]] = icmp ugt <4 x i64> [[CTPOP]], splat (i64 1)
+; FAST-NEXT:    ret <4 x i1> [[CMP1]]
+;
+  %ctpop = call <4 x i64> @llvm.ctpop(<4 x i64> %x)
+  %cmp = icmp ugt <4 x i64> %ctpop, splat (i64 1)
+  ret <4 x i1> %cmp
+}
+
+define <4 x i1> @test_eq_1(<4 x i64> %x) {
+; SLOW-LABEL: define <4 x i1> @test_eq_1(
+; SLOW-SAME: <4 x i64> [[X:%.*]]) {
+; SLOW-NEXT:    [[TMP0:%.*]] = add <4 x i64> [[X]], splat (i64 -1)
+; SLOW-NEXT:    [[TMP1:%.*]] = xor <4 x i64> [[X]], [[TMP0]]
+; SLOW-NEXT:    [[TMP2:%.*]] = icmp ugt <4 x i64> [[TMP1]], [[TMP0]]
+; SLOW-NEXT:    ret <4 x i1> [[TMP2]]
+;
+; FAST-LABEL: define <4 x i1> @test_eq_1(
+; FAST-SAME: <4 x i64> [[X:%.*]]) #[[ATTR0]] {
+; FAST-NEXT:    [[CTPOP:%.*]] = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> [[X]])
+; FAST-NEXT:    [[CMP1:%.*]] = icmp eq <4 x i64> [[CTPOP]], splat (i64 1)
+; FAST-NEXT:    ret <4 x i1> [[CMP1]]
+;
+  %ctpop = call <4 x i64> @llvm.ctpop(<4 x i64> %x)
+  %cmp = icmp eq <4 x i64> %ctpop, splat (i64 1)
+  ret <4 x i1> %cmp
+}
+
+define <4 x i1> @test_ne_1(<4 x i64> %x) {
+; SLOW-LABEL: define <4 x i1> @test_ne_1(
+; SLOW-SAME: <4 x i64> [[X:%.*]]) {
+; SLOW-NEXT:    [[TMP0:%.*]] = add <4 x i64> [[X]], splat (i64 -1)
+; SLOW-NEXT:    [[TMP1:%.*]] = xor <4 x i64> [[X]], [[TMP0]]
+; SLOW-NEXT:    [[TMP2:%.*]] = icmp ule <4 x i64> [[TMP1]], [[TMP0]]
+; SLOW-NEXT:    ret <4 x i1> [[TMP2]]
+;
+; FAST-LABEL: define <4 x i1> @test_ne_1(
+; FAST-SAME: <4 x i64> [[X:%.*]]) #[[ATTR0]] {
+; FAST-NEXT:    [[CTPOP:%.*]] = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> [[X]])
+; FAST-NEXT:    [[CMP1:%.*]] = icmp ne <4 x i64> [[CTPOP]], splat (i64 1)
+; FAST-NEXT:    ret <4 x i1> [[CMP1]]
+;
+  %ctpop = call <4 x i64> @llvm.ctpop(<4 x i64> %x)
+  %cmp = icmp ne <4 x i64> %ctpop, splat (i64 1)
+  ret <4 x i1> %cmp
+}
diff --git a/llvm/test/Transforms/CodeGenPrepare/unfold-pow2-test.ll b/llvm/test/Transforms/CodeGenPrepare/unfold-pow2-test.ll
new file mode 100644
index 0000000000000..f5a4f913e6c06
--- /dev/null
+++ b/llvm/test/Transforms/CodeGenPrepare/unfold-pow2-test.ll
@@ -0,0 +1,123 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -p 'require<profile-summary>,function(codegenprepare)' -S %s \
+; RUN:   | FileCheck %s --check-prefix=SLOW
+; RUN: opt -p 'require<profile-summary>,function(codegenprepare)' -S --mattr=+zbb %s \
+; RUN:   | FileCheck %s --check-prefix=FAST
+; REQUIRES: riscv-registered-target
+
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
+target triple = "riscv64"
+
+define i1 @test_ult_2(i64 %x) {
+; SLOW-LABEL: define i1 @test_ult_2(
+; SLOW-SAME: i64 [[X:%.*]]) {
+; SLOW-NEXT:    [[TMP0:%.*]] = add i64 [[X]], -1
+; SLOW-NEXT:    [[TMP1:%.*]] = and i64 [[X]], [[TMP0]]
+; SLOW-NEXT:    [[CMP1:%.*]] = icmp eq i64 [[TMP1]], 0
+; SLOW-NEXT:    ret i1 [[CMP1]]
+;
+; FAST-LABEL: define i1 @test_ult_2(
+; FAST-SAME: i64 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
+; FAST-NEXT:    [[CTPOP:%.*]] = call i64 @llvm.ctpop.i64(i64 [[X]])
+; FAST-NEXT:    [[CMP1:%.*]] = icmp ult i64 [[CTPOP]], 2
+; FAST-NEXT:    ret i1 [[CMP1]]
+;
+  %ctpop = call i64 @llvm.ctpop(i64 %x)
+  %cmp = icmp ult i64 %ctpop, 2
+  ret i1 %cmp
+}
+
+define i1 @test_ugt_1(i64 %x) {
+; SLOW-LABEL: define i1 @test_ugt_1(
+; SLOW-SAME: i64 [[X:%.*]]) {
+; SLOW-NEXT:    [[TMP0:%.*]] = add i64 [[X]], -1
+; SLOW-NEXT:    [[TMP1:%.*]] = and i64 [[X]], [[TMP0]]
+; SLOW-NEXT:    [[CMP1:%.*]] = icmp ne i64 [[TMP1]], 0
+; SLOW-NEXT:    ret i1 [[CMP1]]
+;
+; FAST-LABEL: define i1 @test_ugt_1(
+; FAST-SAME: i64 [[X:%.*]]) #[[ATTR0]] {
+; FAST-NEXT:    [[CTPOP:%.*]] = call i64 @llvm.ctpop.i64(i64 [[X]])
+; FAST-NEXT:    [[CMP1:%.*]] = icmp ugt i64 [[CTPOP]], 1
+; FAST-NEXT:    ret i1 [[CMP1]]
+;
+  %ctpop = call i64 @llvm.ctpop(i64 %x)
+  %cmp = icmp ugt i64 %ctpop, 1
+  ret i1 %cmp
+}
+
+define i1 @test_eq_1_nz(i64 %x) {
+; SLOW-LABEL: define i1 @test_eq_1_nz(
+; SLOW-SAME: i64 [[X:%.*]]) {
+; SLOW-NEXT:    [[TMP0:%.*]] = add i64 [[X]], -1
+; SLOW-NEXT:    [[TMP1:%.*]] = and i64 [[X]], [[TMP0]]
+; SLOW-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 0
+; SLOW-NEXT:    ret i1 [[TMP2]]
+;
+; FAST-LABEL: define i1 @test_eq_1_nz(
+; FAST-SAME: i64 [[X:%.*]]) #[[ATTR0]] {
+; FAST-NEXT:    [[CTPOP:%.*]] = call range(i64 1, 33) i64 @llvm.ctpop.i64(i64 [[X]])
+; FAST-NEXT:    [[CMP1:%.*]] = icmp ult i64 [[CTPOP]], 2
+; FAST-NEXT:    ret i1 [[CMP1]]
+;
+  %ctpop = call range(i64 1, 33) i64 @llvm.ctpop(i64 %x)
+  %cmp = icmp eq i64 %ctpop, 1
+  ret i1 %cmp
+}
+
+define i1 @test_ne_1_nz(i64 %x) {
+; SLOW-LABEL: define i1 @test_ne_1_nz(
+; SLOW-SAME: i64 [[X:%.*]]) {
+; SLOW-NEXT:    [[TMP0:%.*]] = add i64 [[X]], -1
+; SLOW-NEXT:    [[TMP1:%.*]] = and i64 [[X]], [[TMP0]]
+; SLOW-NEXT:    [[TMP2:%.*]] = icmp ne i64 [[TMP1]], 0
+; SLOW-NEXT:    ret i1 [[TMP2]]
+;
+; FAST-LABEL: define i1 @test_ne_1_nz(
+; FAST-SAME: i64 [[X:%.*]]) #[[ATTR0]] {
+; FAST-NEXT:    [[CTPOP:%.*]] = call range(i64 1, 33) i64 @llvm.ctpop.i64(i64 [[X]])
+; FAST-NEXT:    [[CMP1:%.*]] = icmp ugt i64 [[CTPOP]], 1
+; FAST-NEXT:    ret i1 [[CMP1]]
+;
+  %ctpop = call range(i64 1, 33) i64 @llvm.ctpop(i64 %x)
+  %cmp = icmp ne i64 %ctpop, 1
+  ret i1 %cmp
+}
+
+define i1 @test_eq_1(i64 %x) {
+; SLOW-LABEL: define i1 @test_eq_1(
+; SLOW-SAME: i64 [[X:%.*]]) {
+; SLOW-NEXT:    [[TMP0:%.*]] = add i64 [[X]], -1
+; SLOW-NEXT:    [[TMP1:%.*]] = xor i64 [[X]], [[TMP0]]
+; SLOW-NEXT:    [[TMP2:%.*]] = icmp ugt i64 [[TMP1]], [[TMP0]]
+; SLOW-NEXT:    ret i1 [[TMP2]]
+;
+; FAST-LABEL: define i1 @test_eq_1(
+; FAST-SAME: i64 [[X:%.*]]) #[[ATTR0]] {
+; FAST-NEXT:    [[CTPOP:%.*]] = call i64 @llvm.ctpop.i64(i64 [[X]])
+; FAST-NEXT:    [[CMP1:%.*]] = icmp eq i64 [[CTPOP]], 1
+; FAST-NEXT:    ret i1 [[CMP1]]
+;
+  %ctpop = call i64 @llvm.ctpop(i64 %x)
+  %cmp = icmp eq i64 %ctpop, 1
+  ret i1 %cmp
+}
+
+define i1 @test_ne_1(i64 %x) {
+; SLOW-LABEL: define i1 @test_ne_1(
+; SLOW-SAME: i64 [[X:%.*]]) {
+; SLOW-NEXT:    [[TMP0:%.*]] = add i64 [[X]], -1
+; SLOW-NEXT:    [[TMP1:%.*]] = xor i64 [[X]], [[TMP0]]
+; SLOW-NEXT:    [[TMP2:%.*]] = icmp ule i64 [[TMP1]], [[TMP0]]
+; SLOW-NEXT:    ret i1 [[TMP2]]
+;
+; FAST-LABEL: define i1 @test_ne_1(
+; FAST-SAME: i64 [[X:%.*]]) #[[ATTR0]] {
+; FAST-NEXT:    [[CTPOP:%.*]] = call i64 @llvm.ctpop.i64(i64 [[X]])
+; FAST-NEXT:    [[CMP1:%.*]] = icmp ne i64 [[CTPOP]], 1
+; FAST-NEXT:    ret i1 [[CMP1]]
+;
+  %ctpop = call i64 @llvm.ctpop(i64 %x)
+  %cmp = icmp ne i64 %ctpop, 1
+  ret i1 %cmp
+}
diff --git a/llvm/test/Transforms/FunctionAttrs/initializes.ll b/llvm/test/Transforms/FunctionAttrs/initializes.ll
index 861c61d683ae0..937595b5e9b74 100644
--- a/llvm/test/Transforms/FunctionAttrs/initializes.ll
+++ b/llvm/test/Transforms/FunctionAttrs/initializes.ll
@@ -635,3 +635,17 @@ define void @memset_offset_1_size_0(ptr %dst, ptr %src) {
   call void @llvm.memmove.p0.p0.i64(ptr %dst.1, ptr %src, i64 0, i1 false)
   ret void
 }
+
+; We should bail if the range overflows a singed 64-bit int.
+define void @range_overflows_signed_64_bit_int(ptr %arg) {
+; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: write)
+; CHECK-LABEL: define void @range_overflows_signed_64_bit_int(
+; CHECK-SAME: ptr writeonly captures(none) [[ARG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[GETELEMENTPTR:%.*]] = getelementptr i8, ptr [[ARG]], i64 9223372036854775804
+; CHECK-NEXT:    store i32 0, ptr [[GETELEMENTPTR]], align 4
+; CHECK-NEXT:    ret void
+;
+  %getelementptr = getelementptr i8, ptr %arg, i64 9223372036854775804
+  store i32 0, ptr %getelementptr
+  ret void
+}
diff --git a/llvm/test/Transforms/GlobalOpt/X86/preserve-dbgloc-of-load-store-to-bool.ll b/llvm/test/Transforms/GlobalOpt/X86/preserve-dbgloc-of-load-store-to-bool.ll
new file mode 100644
index 0000000000000..6d2fb50eb3378
--- /dev/null
+++ b/llvm/test/Transforms/GlobalOpt/X86/preserve-dbgloc-of-load-store-to-bool.ll
@@ -0,0 +1,99 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt < %s -p=globalopt -S | FileCheck %s
+
+;; Test that when we are able to simplify uses of global variables with loads of
+;; newly generated bool values, we transfer debuglocs over correctly.
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+@global = internal global i32 0
+@global.1 = internal unnamed_addr global ptr null, align 8
+
+define void @ham() !dbg !7 {
+; CHECK-LABEL: define void @ham(
+; CHECK-SAME: ) local_unnamed_addr !dbg [[DBG4:![0-9]+]] {
+; CHECK-NEXT:  [[BB:.*:]]
+; CHECK-NEXT:    [[LOAD_B:%.*]] = load i1, ptr @global, align 1, !dbg [[DBG6:![0-9]+]]
+; CHECK-NEXT:    [[LOAD_B1:%.*]] = load i1, ptr @global, align 1, !dbg [[DBG6]]
+; CHECK-NEXT:    [[LOAD:%.*]] = zext i1 [[LOAD_B1]] to i32, !dbg [[DBG6]]
+; CHECK-NEXT:    store i1 [[LOAD_B]], ptr @global, align 1
+; CHECK-NEXT:    ret void
+;
+bb:
+  %load = load i32, ptr @global, align 4, !dbg !4
+  store i32 %load, ptr @global, align 4
+  ret void
+}
+
+define void @hoge() {
+; CHECK-LABEL: define void @hoge() local_unnamed_addr {
+; CHECK-NEXT:  [[BB:.*:]]
+; CHECK-NEXT:    store i1 true, ptr @global, align 1
+; CHECK-NEXT:    ret void
+;
+bb:
+  store i32 1, ptr @global, align 4
+  ret void
+}
+
+define void @bar() !dbg !13 {
+; CHECK-LABEL: define void @bar(
+; CHECK-SAME: ) local_unnamed_addr !dbg [[DBG8:![0-9]+]] {
+; CHECK-NEXT:  [[ENTRY:.*:]]
+; CHECK-NEXT:    store i1 true, ptr @global.1.init, align 1, !dbg [[DBG9:![0-9]+]]
+; CHECK-NEXT:    ret void
+;
+entry:
+  %call = tail call noalias nonnull dereferenceable(48) ptr @_Znwm(i64 48)
+  store ptr %call, ptr @global.1, align 8, !dbg !14
+  ret void
+}
+
+define void @pluto() !dbg !10 {
+; CHECK-LABEL: define void @pluto(
+; CHECK-SAME: ) local_unnamed_addr !dbg [[DBG10:![0-9]+]] {
+; CHECK-NEXT:  [[ENTRY:.*:]]
+; CHECK-NEXT:    [[GLOBAL_1_INIT_VAL:%.*]] = load i1, ptr @global.1.init, align 1, !dbg [[DBG11:![0-9]+]]
+; CHECK-NEXT:    [[NOTINIT:%.*]] = xor i1 [[GLOBAL_1_INIT_VAL]], true, !dbg [[DBG12:![0-9]+]]
+; CHECK-NEXT:    unreachable
+;
+entry:
+  %0 = load ptr, ptr @global.1, align 8, !dbg !11
+  %.not = icmp eq ptr %0, null, !dbg !12
+  unreachable
+}
+
+declare ptr @_Znwm(i64)
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!3}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang version 20.0.0git", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !2, globals: !2, splitDebugInlining: false, nameTableKind: None)
+!1 = !DIFile(filename: "preserve-load-dbgloc.c", directory: "/tmp")
+!2 = !{}
+!3 = !{i32 2, !"Debug Info Version", i32 3}
+!4 = !DILocation(line: 10, column: 1, scope: !5)
+!5 = distinct !DILexicalBlock(scope: !7, file: !6, line: 1524, column: 3)
+!6 = !DIFile(filename: "preserve-load-dbgloc.c", directory: "/tmp")
+!7 = distinct !DISubprogram(name: "ham", scope: !6, file: !6, line: 10, type: !8, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !2)
+!8 = distinct !DISubroutineType(types: !2)
+!10 = distinct !DISubprogram(name: "pluto", scope: !6, file: !6, line: 20, type: !8, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !2)
+!11 = !DILocation(line: 20, column: 2, scope: !10)
+!12 = !DILocation(line: 21, column: 3, scope: !10)
+!13 = distinct !DISubprogram(name: "bar", scope: !6, file: !6, line: 230, type: !8, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !2)
+!14 = !DILocation(line: 11, column: 4, scope: !13)
+;.
+; CHECK: [[META0:![0-9]+]] = distinct !DICompileUnit(language: DW_LANG_C11, file: [[META1:![0-9]+]], producer: "{{.*}}clang version {{.*}}", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: [[META2:![0-9]+]], retainedTypes: [[META2]], globals: [[META2]], splitDebugInlining: false, nameTableKind: None)
+; CHECK: [[META1]] = !DIFile(filename: "preserve-load-dbgloc.c", directory: {{.*}})
+; CHECK: [[META2]] = !{}
+; CHECK: [[DBG4]] = distinct !DISubprogram(name: "ham", scope: [[META1]], file: [[META1]], line: 10, type: [[META5:![0-9]+]], flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: [[META0]], retainedNodes: [[META2]])
+; CHECK: [[META5]] = distinct !DISubroutineType(types: [[META2]])
+; CHECK: [[DBG6]] = !DILocation(line: 10, column: 1, scope: [[META7:![0-9]+]])
+; CHECK: [[META7]] = distinct !DILexicalBlock(scope: [[DBG4]], file: [[META1]], line: 1524, column: 3)
+; CHECK: [[DBG8]] = distinct !DISubprogram(name: "bar", scope: [[META1]], file: [[META1]], line: 230, type: [[META5]], flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: [[META0]], retainedNodes: [[META2]])
+; CHECK: [[DBG9]] = !DILocation(line: 11, column: 4, scope: [[DBG8]])
+; CHECK: [[DBG10]] = distinct !DISubprogram(name: "pluto", scope: [[META1]], file: [[META1]], line: 20, type: [[META5]], flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: [[META0]], retainedNodes: [[META2]])
+; CHECK: [[DBG11]] = !DILocation(line: 20, column: 2, scope: [[DBG10]])
+; CHECK: [[DBG12]] = !DILocation(line: 21, column: 3, scope: [[DBG10]])
+;.
diff --git a/llvm/test/Transforms/GlobalOpt/malloc-promote-atomic.ll b/llvm/test/Transforms/GlobalOpt/malloc-promote-atomic.ll
new file mode 100644
index 0000000000000..0ecdf095efdd8
--- /dev/null
+++ b/llvm/test/Transforms/GlobalOpt/malloc-promote-atomic.ll
@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -passes=globalopt -S < %s | FileCheck %s
+
+@g = internal global ptr null, align 8
+
+define void @init() {
+; CHECK-LABEL: define void @init() local_unnamed_addr {
+; CHECK-NEXT:    [[ALLOC:%.*]] = call ptr @malloc(i64 48)
+; CHECK-NEXT:    store atomic ptr [[ALLOC]], ptr @g seq_cst, align 8
+; CHECK-NEXT:    ret void
+;
+  %alloc = call ptr @malloc(i64 48)
+  store atomic ptr %alloc, ptr @g seq_cst, align 8
+  ret void
+}
+
+define i1 @check() {
+; CHECK-LABEL: define i1 @check() local_unnamed_addr {
+; CHECK-NEXT:    [[VAL:%.*]] = load atomic ptr, ptr @g seq_cst, align 8
+; CHECK-NEXT:    [[CMP:%.*]] = icmp eq ptr [[VAL]], null
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %val = load atomic ptr, ptr @g seq_cst, align 8
+  %cmp = icmp eq ptr %val, null
+  ret i1 %cmp
+}
+
+declare ptr @malloc(i64) allockind("alloc,uninitialized") allocsize(0)
diff --git a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-binop.ll b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-binop.ll
index 7da55a199df28..85fc02cb10e14 100644
--- a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-binop.ll
+++ b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-binop.ll
@@ -16,9 +16,20 @@ define <vscale x 4 x i32> @commute_constant_to_rhs(<vscale x 4 x i1> %pg, <vscal
   ret <vscale x 4 x i32> %r
 }
 
+; Operation is not commutative.
+define <vscale x 4 x i32> @cannot_commute_constant_to_rhs_1(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @cannot_commute_constant_to_rhs_1(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[A:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 303), <vscale x 4 x i32> [[A]])
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 303), <vscale x 4 x i32> %a)
+  ret <vscale x 4 x i32> %r
+}
+
 ; Inactive lanes are important, which make the operation non-commutative.
-define <vscale x 4 x i32> @cannot_commute_constant_to_rhs(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) #0 {
-; CHECK-LABEL: define <vscale x 4 x i32> @cannot_commute_constant_to_rhs(
+define <vscale x 4 x i32> @cannot_commute_constant_to_rhs_2(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @cannot_commute_constant_to_rhs_2(
 ; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[A:%.*]]) #[[ATTR0]] {
 ; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 303), <vscale x 4 x i32> [[A]])
 ; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
@@ -96,6 +107,106 @@ define <vscale x 4 x i32> @constant_mul_u_after_striping_inactive_lanes(<vscale
 ; enable simplification. Given the simplications themselves are common code, it
 ; is assumed they are already well tested elsewhere.
 
+define <vscale x 4 x i32> @constant_add(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @constant_add(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @constant_add_u(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @constant_add_u(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.add.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.add.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @constant_and(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @constant_and(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 14))
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 14))
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @constant_and_u(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @constant_and_u(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.and.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 14))
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.and.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 14))
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @constant_eor(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @constant_eor(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @constant_eor_u(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @constant_eor_u(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x float> @constant_fadd(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x float> @constant_fadd(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fadd.nxv4f32(<vscale x 4 x i1> [[PG]], <vscale x 4 x float> splat (float 7.000000e+00), <vscale x 4 x float> splat (float 6.000000e+00))
+; CHECK-NEXT:    ret <vscale x 4 x float> [[R]]
+;
+  %r = call <vscale x 4 x float> @llvm.aarch64.sve.fadd.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> splat (float 7.0), <vscale x 4 x float> splat (float 6.0))
+  ret <vscale x 4 x float> %r
+}
+
+define <vscale x 4 x float> @constant_fadd_u(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x float> @constant_fadd_u(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fadd.u.nxv4f32(<vscale x 4 x i1> [[PG]], <vscale x 4 x float> splat (float 7.000000e+00), <vscale x 4 x float> splat (float 6.000000e+00))
+; CHECK-NEXT:    ret <vscale x 4 x float> [[R]]
+;
+  %r = call <vscale x 4 x float> @llvm.aarch64.sve.fadd.u.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> splat (float 7.0), <vscale x 4 x float> splat (float 6.0))
+  ret <vscale x 4 x float> %r
+}
+
+define <vscale x 4 x float> @constant_fdiv(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x float> @constant_fdiv(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fdiv.nxv4f32(<vscale x 4 x i1> [[PG]], <vscale x 4 x float> splat (float 1.200000e+01), <vscale x 4 x float> splat (float 6.000000e+00))
+; CHECK-NEXT:    ret <vscale x 4 x float> [[R]]
+;
+  %r = call <vscale x 4 x float> @llvm.aarch64.sve.fdiv.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> splat (float 12.0), <vscale x 4 x float> splat (float 6.0))
+  ret <vscale x 4 x float> %r
+}
+
+define <vscale x 4 x float> @constant_fdiv_u(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x float> @constant_fdiv_u(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fdiv.u.nxv4f32(<vscale x 4 x i1> [[PG]], <vscale x 4 x float> splat (float 7.000000e+00), <vscale x 4 x float> splat (float 6.000000e+00))
+; CHECK-NEXT:    ret <vscale x 4 x float> [[R]]
+;
+  %r = call <vscale x 4 x float> @llvm.aarch64.sve.fdiv.u.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> splat (float 7.0), <vscale x 4 x float> splat (float 6.0))
+  ret <vscale x 4 x float> %r
+}
+
 define <vscale x 4 x float> @constant_fmul(<vscale x 4 x i1> %pg) #0 {
 ; CHECK-LABEL: define <vscale x 4 x float> @constant_fmul(
 ; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
@@ -115,6 +226,26 @@ define <vscale x 4 x float> @constant_fmul_u(<vscale x 4 x i1> %pg) #0 {
   ret <vscale x 4 x float> %r
 }
 
+define <vscale x 4 x float> @constant_fsub(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x float> @constant_fsub(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1> [[PG]], <vscale x 4 x float> splat (float 7.000000e+00), <vscale x 4 x float> splat (float 6.000000e+00))
+; CHECK-NEXT:    ret <vscale x 4 x float> [[R]]
+;
+  %r = call <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> splat (float 7.0), <vscale x 4 x float> splat (float 6.0))
+  ret <vscale x 4 x float> %r
+}
+
+define <vscale x 4 x float> @constant_fsub_u(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x float> @constant_fsub_u(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fsub.u.nxv4f32(<vscale x 4 x i1> [[PG]], <vscale x 4 x float> splat (float 7.000000e+00), <vscale x 4 x float> splat (float 6.000000e+00))
+; CHECK-NEXT:    ret <vscale x 4 x float> [[R]]
+;
+  %r = call <vscale x 4 x float> @llvm.aarch64.sve.fsub.u.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> splat (float 7.0), <vscale x 4 x float> splat (float 6.0))
+  ret <vscale x 4 x float> %r
+}
+
 define <vscale x 4 x i32> @constant_mul(<vscale x 4 x i1> %pg) #0 {
 ; CHECK-LABEL: define <vscale x 4 x i32> @constant_mul(
 ; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
@@ -134,13 +265,179 @@ define <vscale x 4 x i32> @constant_mul_u(<vscale x 4 x i1> %pg) #0 {
   ret <vscale x 4 x i32> %r
 }
 
+define <vscale x 4 x i32> @constant_orr(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @constant_orr(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 13), <vscale x 4 x i32> splat (i32 3))
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 13), <vscale x 4 x i32> splat (i32 3))
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @constant_orr_u(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @constant_orr_u(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 13), <vscale x 4 x i32> splat (i32 3))
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 13), <vscale x 4 x i32> splat (i32 3))
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @constant_sdiv(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @constant_sdiv(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -7), <vscale x 4 x i32> splat (i32 3))
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 -7), <vscale x 4 x i32> splat (i32 3))
+  ret <vscale x 4 x i32> %r
+}
+
+; The intrinsic's IR equivalent does not support divide-by-zero.
+define <vscale x 4 x i32> @constant_sdiv_by_zero(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @constant_sdiv_by_zero(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -7), <vscale x 4 x i32> zeroinitializer)
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 -7), <vscale x 4 x i32> splat (i32 0))
+  ret <vscale x 4 x i32> %r
+}
+
+; The intrinsic's IR equivalent does not support overflow.
+define <vscale x 4 x i32> @constant_sdiv_with_overflow(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @constant_sdiv_with_overflow(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -2147483648), <vscale x 4 x i32> splat (i32 -1))
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 -2147483648), <vscale x 4 x i32> splat (i32 -1))
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @constant_sdiv_u(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @constant_sdiv_u(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -7), <vscale x 4 x i32> splat (i32 -3))
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 -7), <vscale x 4 x i32> splat (i32 -3))
+  ret <vscale x 4 x i32> %r
+}
+
+; The intrinsic's IR equivalent does not support divide-by-zero.
+define <vscale x 4 x i32> @constant_sdiv_u_by_zero(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @constant_sdiv_u_by_zero(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -7), <vscale x 4 x i32> zeroinitializer)
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 -7), <vscale x 4 x i32> splat (i32 0))
+  ret <vscale x 4 x i32> %r
+}
+
+; The intrinsic's IR equivalent does not support overflow.
+define <vscale x 4 x i32> @constant_sdiv_u_with_overflow(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @constant_sdiv_u_with_overflow(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -2147483648), <vscale x 4 x i32> splat (i32 -1))
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 -2147483648), <vscale x 4 x i32> splat (i32 -1))
+  ret <vscale x 4 x i32> %r
+}
+define <vscale x 4 x i32> @constant_sub(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @constant_sub(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @constant_sub_u(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @constant_sub_u(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @constant_udiv(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @constant_udiv(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
+  ret <vscale x 4 x i32> %r
+}
+
+; The intrinsic's IR equivalent does not support divide-by-zero.
+define <vscale x 4 x i32> @constant_udiv_by_zero(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @constant_udiv_by_zero(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> zeroinitializer)
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 0))
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @constant_udiv_u(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @constant_udiv_u(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 9), <vscale x 4 x i32> splat (i32 3))
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 9), <vscale x 4 x i32> splat (i32 3))
+  ret <vscale x 4 x i32> %r
+}
 
-; repeat only the constant fold tests for fmul(.u)
+; The intrinsic's IR equivalent does not support divide-by-zero.
+define <vscale x 4 x i32> @constant_udiv_u_by_zero(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @constant_udiv_u_by_zero(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 9), <vscale x 4 x i32> zeroinitializer)
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 9), <vscale x 4 x i32> splat (i32 0))
+  ret <vscale x 4 x i32> %r
+}
 
 declare <vscale x 4 x i32> @llvm.aarch64.sve.dup.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
+declare <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
+declare <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
+declare <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
 declare <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
+declare <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
+declare <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
+declare <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
+declare <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
 
+declare <vscale x 4 x i32> @llvm.aarch64.sve.add.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
+declare <vscale x 4 x i32> @llvm.aarch64.sve.and.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
+declare <vscale x 4 x i32> @llvm.aarch64.sve.eor.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
 declare <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
+declare <vscale x 4 x i32> @llvm.aarch64.sve.orr.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
+declare <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
+declare <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
+declare <vscale x 4 x i32> @llvm.aarch64.sve.udiv.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
+
+declare <vscale x 4 x float> @llvm.aarch64.sve.fadd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
+declare <vscale x 4 x float> @llvm.aarch64.sve.fdiv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
+declare <vscale x 4 x float> @llvm.aarch64.sve.fmul.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
+declare <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
+
+declare <vscale x 4 x float> @llvm.aarch64.sve.fadd.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
+declare <vscale x 4 x float> @llvm.aarch64.sve.fdiv.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
+declare <vscale x 4 x float> @llvm.aarch64.sve.fmul.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
+declare <vscale x 4 x float> @llvm.aarch64.sve.fsub.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
 
 attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-shift.ll b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-shift.ll
new file mode 100644
index 0000000000000..400dc0dc8f8ee
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-shift.ll
@@ -0,0 +1,353 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -S -passes=instcombine < %s | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+define <vscale x 16 x i8> @constant_asr_i8_shift_by_0(<vscale x 16 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 16 x i8> @constant_asr_i8_shift_by_0(
+; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 7), <vscale x 16 x i8> zeroinitializer)
+; CHECK-NEXT:    ret <vscale x 16 x i8> [[R]]
+;
+  %r = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 7), <vscale x 16 x i8> splat (i8 0))
+  ret <vscale x 16 x i8> %r
+}
+
+define <vscale x 16 x i8> @constant_asr_i8_shift_by_1(<vscale x 16 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 16 x i8> @constant_asr_i8_shift_by_1(
+; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 -63), <vscale x 16 x i8> splat (i8 1))
+; CHECK-NEXT:    ret <vscale x 16 x i8> [[R]]
+;
+  %r = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 193), <vscale x 16 x i8> splat (i8 1))
+  ret <vscale x 16 x i8> %r
+}
+
+; data = 0x80
+define <vscale x 16 x i8> @constant_asr_i8_shift_by_7(<vscale x 16 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 16 x i8> @constant_asr_i8_shift_by_7(
+; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 -128), <vscale x 16 x i8> splat (i8 7))
+; CHECK-NEXT:    ret <vscale x 16 x i8> [[R]]
+;
+  %r = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 128), <vscale x 16 x i8> splat (i8 7))
+  ret <vscale x 16 x i8> %r
+}
+
+; The intrinsic's IR equivalent only supports shift amounts in the range 0-7.
+; data = 0x80
+define <vscale x 16 x i8> @constant_asr_i8_shift_by_8(<vscale x 16 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 16 x i8> @constant_asr_i8_shift_by_8(
+; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 -128), <vscale x 16 x i8> splat (i8 8))
+; CHECK-NEXT:    ret <vscale x 16 x i8> [[R]]
+;
+  %r = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 128), <vscale x 16 x i8> splat (i8 8))
+  ret <vscale x 16 x i8> %r
+}
+
+; data = 0x8000
+define <vscale x 8 x i16> @constant_asr_i16_shift_by_15(<vscale x 8 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 8 x i16> @constant_asr_i16_shift_by_15(
+; CHECK-SAME: <vscale x 8 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> [[PG]], <vscale x 8 x i16> splat (i16 -32768), <vscale x 8 x i16> splat (i16 15))
+; CHECK-NEXT:    ret <vscale x 8 x i16> [[R]]
+;
+  %r = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> splat (i16 32768), <vscale x 8 x i16> splat (i16 15))
+  ret <vscale x 8 x i16> %r
+}
+
+; The intrinsic's IR equivalent only supports shift amounts in the range 0-15.
+; data = 0x8000
+define <vscale x 8 x i16> @constant_asr_i16_shift_by_16(<vscale x 8 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 8 x i16> @constant_asr_i16_shift_by_16(
+; CHECK-SAME: <vscale x 8 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> [[PG]], <vscale x 8 x i16> splat (i16 -32768), <vscale x 8 x i16> splat (i16 16))
+; CHECK-NEXT:    ret <vscale x 8 x i16> [[R]]
+;
+  %r = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> splat (i16 32768), <vscale x 8 x i16> splat (i16 16))
+  ret <vscale x 8 x i16> %r
+}
+
+; data = 0x800000000
+define <vscale x 4 x i32> @constant_asr_i32_shift_by_31(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @constant_asr_i32_shift_by_31(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -2147483648), <vscale x 4 x i32> splat (i32 31))
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 2147483648), <vscale x 4 x i32> splat (i32 31))
+  ret <vscale x 4 x i32> %r
+}
+
+; The intrinsic's IR equivalent only supports shift amounts in the range 0-31.
+; data = 0x80000000
+define <vscale x 4 x i32> @constant_asr_i32_shift_by_32(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @constant_asr_i32_shift_by_32(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -2147483648), <vscale x 4 x i32> splat (i32 32))
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 2147483648), <vscale x 4 x i32> splat (i32 32))
+  ret <vscale x 4 x i32> %r
+}
+
+; data = 0x8000000000000000
+define <vscale x 2 x i64> @constant_asr_i64_shift_by_63(<vscale x 2 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 2 x i64> @constant_asr_i64_shift_by_63(
+; CHECK-SAME: <vscale x 2 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> [[PG]], <vscale x 2 x i64> splat (i64 -9223372036854775808), <vscale x 2 x i64> splat (i64 63))
+; CHECK-NEXT:    ret <vscale x 2 x i64> [[R]]
+;
+  %r = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> splat (i64 9223372036854775808), <vscale x 2 x i64> splat (i64 63))
+  ret <vscale x 2 x i64> %r
+}
+
+; The intrinsic's IR equivalent only supports shift amounts in the range 0-63.
+; data = 0x8000000000000000
+define <vscale x 2 x i64> @constant_asr_i64_shift_by_64(<vscale x 2 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 2 x i64> @constant_asr_i64_shift_by_64(
+; CHECK-SAME: <vscale x 2 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> [[PG]], <vscale x 2 x i64> splat (i64 -9223372036854775808), <vscale x 2 x i64> splat (i64 64))
+; CHECK-NEXT:    ret <vscale x 2 x i64> [[R]]
+;
+  %r = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> splat (i64 9223372036854775808), <vscale x 2 x i64> splat (i64 64))
+  ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 16 x i8> @constant_lsl_i8_shift_by_0(<vscale x 16 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 16 x i8> @constant_lsl_i8_shift_by_0(
+; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 7), <vscale x 16 x i8> zeroinitializer)
+; CHECK-NEXT:    ret <vscale x 16 x i8> [[R]]
+;
+  %r = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 7), <vscale x 16 x i8> splat (i8 0))
+  ret <vscale x 16 x i8> %r
+}
+
+define <vscale x 16 x i8> @constant_lsl_i8_shift_by_1(<vscale x 16 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 16 x i8> @constant_lsl_i8_shift_by_1(
+; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 -63), <vscale x 16 x i8> splat (i8 1))
+; CHECK-NEXT:    ret <vscale x 16 x i8> [[R]]
+;
+  %r = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 193), <vscale x 16 x i8> splat (i8 1))
+  ret <vscale x 16 x i8> %r
+}
+
+; result = 0x80
+define <vscale x 16 x i8> @constant_lsl_i8_shift_by_7(<vscale x 16 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 16 x i8> @constant_lsl_i8_shift_by_7(
+; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 1), <vscale x 16 x i8> splat (i8 7))
+; CHECK-NEXT:    ret <vscale x 16 x i8> [[R]]
+;
+  %r = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 1), <vscale x 16 x i8> splat (i8 7))
+  ret <vscale x 16 x i8> %r
+}
+
+; The intrinsic's IR equivalent only supports shift amounts in the range 0-7.
+define <vscale x 16 x i8> @constant_lsl_i8_shift_by_8(<vscale x 16 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 16 x i8> @constant_lsl_i8_shift_by_8(
+; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 1), <vscale x 16 x i8> splat (i8 8))
+; CHECK-NEXT:    ret <vscale x 16 x i8> [[R]]
+;
+  %r = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 1), <vscale x 16 x i8> splat (i8 8))
+  ret <vscale x 16 x i8> %r
+}
+
+; result = 0x8000
+define <vscale x 8 x i16> @constant_lsl_i16_shift_by_15(<vscale x 8 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 8 x i16> @constant_lsl_i16_shift_by_15(
+; CHECK-SAME: <vscale x 8 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> [[PG]], <vscale x 8 x i16> splat (i16 1), <vscale x 8 x i16> splat (i16 15))
+; CHECK-NEXT:    ret <vscale x 8 x i16> [[R]]
+;
+  %r = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> splat (i16 1), <vscale x 8 x i16> splat (i16 15))
+  ret <vscale x 8 x i16> %r
+}
+
+; The intrinsic's IR equivalent only supports shift amounts in the range 0-15.
+define <vscale x 8 x i16> @constant_lsl_i16_shift_by_16(<vscale x 8 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 8 x i16> @constant_lsl_i16_shift_by_16(
+; CHECK-SAME: <vscale x 8 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> [[PG]], <vscale x 8 x i16> splat (i16 1), <vscale x 8 x i16> splat (i16 16))
+; CHECK-NEXT:    ret <vscale x 8 x i16> [[R]]
+;
+  %r = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> splat (i16 1), <vscale x 8 x i16> splat (i16 16))
+  ret <vscale x 8 x i16> %r
+}
+
+; result = 0x800000000
+define <vscale x 4 x i32> @constant_lsl_i32_shift_by_31(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @constant_lsl_i32_shift_by_31(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 1), <vscale x 4 x i32> splat (i32 31))
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 1), <vscale x 4 x i32> splat (i32 31))
+  ret <vscale x 4 x i32> %r
+}
+
+; The intrinsic's IR equivalent only supports shift amounts in the range 0-31.
+define <vscale x 4 x i32> @constant_lsl_i32_shift_by_32(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @constant_lsl_i32_shift_by_32(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 1), <vscale x 4 x i32> splat (i32 32))
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 1), <vscale x 4 x i32> splat (i32 32))
+  ret <vscale x 4 x i32> %r
+}
+
+; result = 0x8000000000000000
+define <vscale x 2 x i64> @constant_lsl_i64_shift_by_63(<vscale x 2 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 2 x i64> @constant_lsl_i64_shift_by_63(
+; CHECK-SAME: <vscale x 2 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> [[PG]], <vscale x 2 x i64> splat (i64 1), <vscale x 2 x i64> splat (i64 63))
+; CHECK-NEXT:    ret <vscale x 2 x i64> [[R]]
+;
+  %r = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> splat (i64 1), <vscale x 2 x i64> splat (i64 63))
+  ret <vscale x 2 x i64> %r
+}
+
+; The intrinsic's IR equivalent only supports shift amounts in the range 0-63.
+define <vscale x 2 x i64> @constant_lsl_i64_shift_by_64(<vscale x 2 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 2 x i64> @constant_lsl_i64_shift_by_64(
+; CHECK-SAME: <vscale x 2 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> [[PG]], <vscale x 2 x i64> splat (i64 1), <vscale x 2 x i64> splat (i64 64))
+; CHECK-NEXT:    ret <vscale x 2 x i64> [[R]]
+;
+  %r = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> splat (i64 1), <vscale x 2 x i64> splat (i64 64))
+  ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 16 x i8> @constant_lsr_i8_shift_by_0(<vscale x 16 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 16 x i8> @constant_lsr_i8_shift_by_0(
+; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 7), <vscale x 16 x i8> zeroinitializer)
+; CHECK-NEXT:    ret <vscale x 16 x i8> [[R]]
+;
+  %r = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 7), <vscale x 16 x i8> splat (i8 0))
+  ret <vscale x 16 x i8> %r
+}
+
+define <vscale x 16 x i8> @constant_lsr_i8_shift_by_1(<vscale x 16 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 16 x i8> @constant_lsr_i8_shift_by_1(
+; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 -63), <vscale x 16 x i8> splat (i8 1))
+; CHECK-NEXT:    ret <vscale x 16 x i8> [[R]]
+;
+  %r = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 193), <vscale x 16 x i8> splat (i8 1))
+  ret <vscale x 16 x i8> %r
+}
+
+; data = 0x80
+define <vscale x 16 x i8> @constant_lsr_i8_shift_by_7(<vscale x 16 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 16 x i8> @constant_lsr_i8_shift_by_7(
+; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 -128), <vscale x 16 x i8> splat (i8 7))
+; CHECK-NEXT:    ret <vscale x 16 x i8> [[R]]
+;
+  %r = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 128), <vscale x 16 x i8> splat (i8 7))
+  ret <vscale x 16 x i8> %r
+}
+
+; The intrinsic's IR equivalent only supports shift amounts in the range 0-7.
+; data = 0x80
+define <vscale x 16 x i8> @constant_lsr_i8_shift_by_8(<vscale x 16 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 16 x i8> @constant_lsr_i8_shift_by_8(
+; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 -128), <vscale x 16 x i8> splat (i8 8))
+; CHECK-NEXT:    ret <vscale x 16 x i8> [[R]]
+;
+  %r = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 128), <vscale x 16 x i8> splat (i8 8))
+  ret <vscale x 16 x i8> %r
+}
+
+; data = 0x8000
+define <vscale x 8 x i16> @constant_lsr_i16_shift_by_15(<vscale x 8 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 8 x i16> @constant_lsr_i16_shift_by_15(
+; CHECK-SAME: <vscale x 8 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> [[PG]], <vscale x 8 x i16> splat (i16 -32768), <vscale x 8 x i16> splat (i16 15))
+; CHECK-NEXT:    ret <vscale x 8 x i16> [[R]]
+;
+  %r = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> splat (i16 32768), <vscale x 8 x i16> splat (i16 15))
+  ret <vscale x 8 x i16> %r
+}
+
+; The intrinsic's IR equivalent only supports shift amounts in the range 0-15.
+; data = 0x8000
+define <vscale x 8 x i16> @constant_lsr_i16_shift_by_16(<vscale x 8 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 8 x i16> @constant_lsr_i16_shift_by_16(
+; CHECK-SAME: <vscale x 8 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> [[PG]], <vscale x 8 x i16> splat (i16 -32768), <vscale x 8 x i16> splat (i16 16))
+; CHECK-NEXT:    ret <vscale x 8 x i16> [[R]]
+;
+  %r = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> splat (i16 32768), <vscale x 8 x i16> splat (i16 16))
+  ret <vscale x 8 x i16> %r
+}
+
+; data = 0x800000000
+define <vscale x 4 x i32> @constant_lsr_i32_shift_by_31(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @constant_lsr_i32_shift_by_31(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -2147483648), <vscale x 4 x i32> splat (i32 31))
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 2147483648), <vscale x 4 x i32> splat (i32 31))
+  ret <vscale x 4 x i32> %r
+}
+
+; The intrinsic's IR equivalent only supports shift amounts in the range 0-31.
+; data = 0x80000000
+define <vscale x 4 x i32> @constant_lsr_i32_shift_by_32(<vscale x 4 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 4 x i32> @constant_lsr_i32_shift_by_32(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -2147483648), <vscale x 4 x i32> splat (i32 32))
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 2147483648), <vscale x 4 x i32> splat (i32 32))
+  ret <vscale x 4 x i32> %r
+}
+
+; data = 0x8000000000000000
+define <vscale x 2 x i64> @constant_lsr_i64_shift_by_63(<vscale x 2 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 2 x i64> @constant_lsr_i64_shift_by_63(
+; CHECK-SAME: <vscale x 2 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> [[PG]], <vscale x 2 x i64> splat (i64 -9223372036854775808), <vscale x 2 x i64> splat (i64 63))
+; CHECK-NEXT:    ret <vscale x 2 x i64> [[R]]
+;
+  %r = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> splat (i64 9223372036854775808), <vscale x 2 x i64> splat (i64 63))
+  ret <vscale x 2 x i64> %r
+}
+
+; The intrinsic's IR equivalent only supports shift amounts in the range 0-63.
+; data = 0x8000000000000000
+define <vscale x 2 x i64> @constant_lsr_i64_shift_by_64(<vscale x 2 x i1> %pg) #0 {
+; CHECK-LABEL: define <vscale x 2 x i64> @constant_lsr_i64_shift_by_64(
+; CHECK-SAME: <vscale x 2 x i1> [[PG:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> [[PG]], <vscale x 2 x i64> splat (i64 -9223372036854775808), <vscale x 2 x i64> splat (i64 64))
+; CHECK-NEXT:    ret <vscale x 2 x i64> [[R]]
+;
+  %r = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> splat (i64 9223372036854775808), <vscale x 2 x i64> splat (i64 64))
+  ret <vscale x 2 x i64> %r
+}
+
+declare <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
+declare <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
+declare <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
+declare <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
+
+declare <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
+declare <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
+declare <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
+declare <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
+
+declare <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
+declare <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
+declare <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
+declare <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
+
+attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/Transforms/InstCombine/and-fcmp.ll b/llvm/test/Transforms/InstCombine/and-fcmp.ll
index c7bbc8ab56f9a..ec1b6ad2ea168 100644
--- a/llvm/test/Transforms/InstCombine/and-fcmp.ll
+++ b/llvm/test/Transforms/InstCombine/and-fcmp.ll
@@ -4990,6 +4990,34 @@ define i1 @clang_builtin_isnormal_inf_check_copysign(half %x, half %y) {
   ret i1 %and
 }
 
+define i1 @clang_builtin_isnormal_inf_check_copysign_logical_select(half %x, half %y) {
+; CHECK-LABEL: @clang_builtin_isnormal_inf_check_copysign_logical_select(
+; CHECK-NEXT:    [[COPYSIGN_X:%.*]] = call half @llvm.copysign.f16(half [[X:%.*]], half [[Y:%.*]])
+; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
+; CHECK-NEXT:    [[CMP:%.*]] = fcmp ueq half [[COPYSIGN_X]], 0xH7C00
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[ORD]], i1 [[CMP]], i1 false
+; CHECK-NEXT:    ret i1 [[AND]]
+;
+  %copysign.x = call half @llvm.copysign.f16(half %x, half %y)
+  %ord = fcmp ord half %x, 0.0
+  %cmp = fcmp uge half %copysign.x, 0xH7C00
+  %and = select i1 %ord, i1 %cmp, i1 false
+  ret i1 %and
+}
+
+define i1 @clang_builtin_isnormal_inf_check_fabs_nnan_logical_select(half %x) {
+; CHECK-LABEL: @clang_builtin_isnormal_inf_check_fabs_nnan_logical_select(
+; CHECK-NEXT:    [[COPYSIGN_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
+; CHECK-NEXT:    [[AND:%.*]] = fcmp oeq half [[COPYSIGN_X]], 0xH7C00
+; CHECK-NEXT:    ret i1 [[AND]]
+;
+  %copysign.x = call nnan half @llvm.fabs.f16(half %x)
+  %ord = fcmp ord half %x, 0.0
+  %cmp = fcmp uge half %copysign.x, 0xH7C00
+  %and = select i1 %ord, i1 %cmp, i1 false
+  ret i1 %and
+}
+
 define i1 @isnormal_logical_select_0(half %x) {
 ; CHECK-LABEL: @isnormal_logical_select_0(
 ; CHECK-NEXT:    [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
diff --git a/llvm/test/Transforms/InstCombine/clamp-to-minmax.ll b/llvm/test/Transforms/InstCombine/clamp-to-minmax.ll
index 478d437847127..b557c0dbe2629 100644
--- a/llvm/test/Transforms/InstCombine/clamp-to-minmax.ll
+++ b/llvm/test/Transforms/InstCombine/clamp-to-minmax.ll
@@ -83,7 +83,7 @@ define float @clamp_float_fast_unordered_strict_maxmin(float %x) {
 ; (X <= C1) ? C1 : MIN(X, C2)
 define float @clamp_float_fast_unordered_nonstrict_maxmin(float %x) {
 ; CHECK-LABEL: @clamp_float_fast_unordered_nonstrict_maxmin(
-; CHECK-NEXT:    [[MIN:%.*]] = call fast float @llvm.minnum.f32(float [[X:%.*]], float 2.550000e+02) 
+; CHECK-NEXT:    [[MIN:%.*]] = call fast float @llvm.minnum.f32(float [[X:%.*]], float 2.550000e+02)
 ; CHECK-NEXT:    [[CMP1:%.*]] = fcmp fast ule float [[X]], 1.000000e+00
 ; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMP1]], float 1.000000e+00, float [[MIN]]
 ; CHECK-NEXT:    ret float [[R]]
@@ -98,7 +98,7 @@ define float @clamp_float_fast_unordered_nonstrict_maxmin(float %x) {
 ; (X > C1) ? C1 : MAX(X, C2)
 define float @clamp_float_fast_unordered_strict_minmax(float %x) {
 ; CHECK-LABEL: @clamp_float_fast_unordered_strict_minmax(
-; CHECK-NEXT:    [[MAX:%.*]] = call fast float @llvm.maxnum.f32(float [[X:%.*]], float 1.000000e+00) 
+; CHECK-NEXT:    [[MAX:%.*]] = call fast float @llvm.maxnum.f32(float [[X:%.*]], float 1.000000e+00)
 ; CHECK-NEXT:    [[CMP1:%.*]] = fcmp fast ugt float [[X]], 2.550000e+02
 ; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMP1]], float 2.550000e+02, float [[MAX]]
 ; CHECK-NEXT:    ret float [[R]]
@@ -113,7 +113,7 @@ define float @clamp_float_fast_unordered_strict_minmax(float %x) {
 ; (X >= C1) ? C1 : MAX(X, C2)
 define float @clamp_float_fast_unordered_nonstrict_minmax(float %x) {
 ; CHECK-LABEL: @clamp_float_fast_unordered_nonstrict_minmax(
-; CHECK-NEXT:    [[MAX:%.*]] = call fast float @llvm.maxnum.f32(float [[X:%.*]], float 1.000000e+00) 
+; CHECK-NEXT:    [[MAX:%.*]] = call fast float @llvm.maxnum.f32(float [[X:%.*]], float 1.000000e+00)
 ; CHECK-NEXT:    [[CMP1:%.*]] = fcmp fast uge float [[X]], 2.550000e+02
 ; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMP1]], float 2.550000e+02, float [[MAX]]
 ; CHECK-NEXT:    ret float [[R]]
@@ -147,7 +147,7 @@ define float @clamp_test_1(float %x) {
 ; Like @clamp_test_1 but HighConst < LowConst
 define float @clamp_negative_wrong_const(float %x) {
 ; CHECK-LABEL: @clamp_negative_wrong_const(
-; CHECK-NEXT:    [[INNER_SEL:%.*]] = call fast float @llvm.minnum.f32(float [[X:%.*]], float 2.550000e+02) 
+; CHECK-NEXT:    [[INNER_SEL:%.*]] = call fast float @llvm.minnum.f32(float [[X:%.*]], float 2.550000e+02)
 ; CHECK-NEXT:    [[OUTER_CMP:%.*]] = fcmp fast ugt float [[X]], 5.120000e+02
 ; CHECK-NEXT:    [[R:%.*]] = select i1 [[OUTER_CMP]], float [[INNER_SEL]], float 5.120000e+02
 ; CHECK-NEXT:    ret float [[R]]
@@ -162,7 +162,7 @@ define float @clamp_negative_wrong_const(float %x) {
 ; Like @clamp_test_1 but both are min
 define float @clamp_negative_same_op(float %x) {
 ; CHECK-LABEL: @clamp_negative_same_op(
-; CHECK-NEXT:    [[INNER_SEL:%.*]] = call fast float @llvm.minnum.f32(float [[X:%.*]], float 2.550000e+02) 
+; CHECK-NEXT:    [[INNER_SEL:%.*]] = call fast float @llvm.minnum.f32(float [[X:%.*]], float 2.550000e+02)
 ; CHECK-NEXT:    [[OUTER_CMP:%.*]] = fcmp fast ult float [[X]], 1.000000e+00
 ; CHECK-NEXT:    [[R:%.*]] = select i1 [[OUTER_CMP]], float [[INNER_SEL]], float 1.000000e+00
 ; CHECK-NEXT:    ret float [[R]]
@@ -500,9 +500,9 @@ define float @ui64_clamp_and_cast_to_float(i64 %x) {
 
 define float @mixed_clamp_to_float_1(i32 %x) {
 ; CHECK-LABEL: @mixed_clamp_to_float_1(
-; CHECK-NEXT:    [[SI_MIN:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 255)
-; CHECK-NEXT:    [[R1:%.*]] = call i32 @llvm.smax.i32(i32 [[SI_MIN]], i32 1)
-; CHECK-NEXT:    [[R:%.*]] = uitofp nneg i32 [[R1]] to float
+; CHECK-NEXT:    [[R1:%.*]] = call i32 @llvm.smax.i32(i32 [[SI_MIN:%.*]], i32 1)
+; CHECK-NEXT:    [[R2:%.*]] = call i32 @llvm.smin.i32(i32 [[R1]], i32 255)
+; CHECK-NEXT:    [[R:%.*]] = uitofp nneg i32 [[R2]] to float
 ; CHECK-NEXT:    ret float [[R]]
 ;
   %si_min_cmp = icmp sgt i32 %x, 255
@@ -535,9 +535,9 @@ define i32 @mixed_clamp_to_i32_1(float %x) {
 
 define float @mixed_clamp_to_float_2(i32 %x) {
 ; CHECK-LABEL: @mixed_clamp_to_float_2(
-; CHECK-NEXT:    [[SI_MIN:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 255)
-; CHECK-NEXT:    [[R1:%.*]] = call i32 @llvm.smax.i32(i32 [[SI_MIN]], i32 1)
-; CHECK-NEXT:    [[R:%.*]] = uitofp nneg i32 [[R1]] to float
+; CHECK-NEXT:    [[R1:%.*]] = call i32 @llvm.smax.i32(i32 [[SI_MIN:%.*]], i32 1)
+; CHECK-NEXT:    [[R2:%.*]] = call i32 @llvm.smin.i32(i32 [[R1]], i32 255)
+; CHECK-NEXT:    [[R:%.*]] = uitofp nneg i32 [[R2]] to float
 ; CHECK-NEXT:    ret float [[R]]
 ;
   %si_min_cmp = icmp sgt i32 %x, 255
@@ -568,9 +568,9 @@ define i32 @mixed_clamp_to_i32_2(float %x) {
 
 define <2 x float> @mixed_clamp_to_float_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @mixed_clamp_to_float_vec(
-; CHECK-NEXT:    [[SI_MIN:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[X:%.*]], <2 x i32> splat (i32 255))
-; CHECK-NEXT:    [[R1:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[SI_MIN]], <2 x i32> splat (i32 1))
-; CHECK-NEXT:    [[R:%.*]] = uitofp nneg <2 x i32> [[R1]] to <2 x float>
+; CHECK-NEXT:    [[R1:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[SI_MIN:%.*]], <2 x i32> splat (i32 1))
+; CHECK-NEXT:    [[R2:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[R1]], <2 x i32> splat (i32 255))
+; CHECK-NEXT:    [[R:%.*]] = uitofp nneg <2 x i32> [[R2]] to <2 x float>
 ; CHECK-NEXT:    ret <2 x float> [[R]]
 ;
   %si_min_cmp = icmp sgt <2 x i32> %x, <i32 255, i32 255>
diff --git a/llvm/test/Transforms/InstCombine/icmp.ll b/llvm/test/Transforms/InstCombine/icmp.ll
index 6e1486660b24d..f5df8573d6304 100644
--- a/llvm/test/Transforms/InstCombine/icmp.ll
+++ b/llvm/test/Transforms/InstCombine/icmp.ll
@@ -2954,6 +2954,99 @@ define i1 @or1_eq1(i32 %x) {
   ret i1 %t1
 }
 
+define <2 x i1> @or1_eq1_vec(<2 x i32> %x) {
+; CHECK-LABEL: @or1_eq1_vec(
+; CHECK-NEXT:    [[T1:%.*]] = icmp ult <2 x i32> [[X:%.*]], splat (i32 2)
+; CHECK-NEXT:    ret <2 x i1> [[T1]]
+;
+  %t0 = or <2 x i32> %x, splat (i32 1)
+  %t1 = icmp eq <2 x i32> %t0, splat (i32 1)
+  ret <2 x i1> %t1
+}
+
+define <2 x i1> @or_eq_vec_nonsplat(<2 x i32> %x) {
+; CHECK-LABEL: @or_eq_vec_nonsplat(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], <i32 -2, i32 -3>
+; CHECK-NEXT:    [[T1:%.*]] = icmp eq <2 x i32> [[TMP1]], zeroinitializer
+; CHECK-NEXT:    ret <2 x i1> [[T1]]
+;
+  %t0 = or <2 x i32> %x, <i32 1, i32 2>
+  %t1 = icmp eq <2 x i32> %t0, <i32 1, i32 2>
+  ret <2 x i1> %t1
+}
+
+define void @or_eq_vec_multiple_nonsplat(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z, ptr %ptr0, ptr %ptr1, ptr %ptr2) {
+; CHECK-LABEL: @or_eq_vec_multiple_nonsplat(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], <i32 -2, i32 -3>
+; CHECK-NEXT:    [[CMP0:%.*]] = icmp eq <2 x i32> [[TMP1]], zeroinitializer
+; CHECK-NEXT:    store <2 x i1> [[CMP0]], ptr [[PTR0:%.*]], align 1
+; CHECK-NEXT:    [[TMP2:%.*]] = and <2 x i32> [[Y:%.*]], <i32 -2, i32 -3>
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq <2 x i32> [[TMP2]], zeroinitializer
+; CHECK-NEXT:    store <2 x i1> [[CMP1]], ptr [[PTR1:%.*]], align 1
+; CHECK-NEXT:    [[TMP3:%.*]] = and <2 x i32> [[Z:%.*]], <i32 -2, i32 -3>
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp eq <2 x i32> [[TMP3]], zeroinitializer
+; CHECK-NEXT:    store <2 x i1> [[CMP2]], ptr [[PTR2:%.*]], align 1
+; CHECK-NEXT:    ret void
+;
+  %t0 = or <2 x i32> %x, <i32 1, i32 2>
+  %cmp0 = icmp eq <2 x i32> %t0, <i32 1, i32 2>
+  store <2 x i1> %cmp0, ptr %ptr0
+
+  %t1 = or <2 x i32> %y, <i32 1, i32 2>
+  %cmp1 = icmp eq <2 x i32> %t1, <i32 1, i32 2>
+  store <2 x i1> %cmp1, ptr %ptr1
+
+  %t2 = or <2 x i32> %z, <i32 1, i32 2>
+  %cmp2 = icmp eq <2 x i32> %t2, <i32 1, i32 2>
+  store <2 x i1> %cmp2, ptr %ptr2
+  ret void
+}
+
+; Make sure use count of 1 doesn't matter
+define i1 @or1_eq1_multiple(i32 %x, i32 %y, i32 %z, ptr %ptr0, ptr %ptr1) {
+; CHECK-LABEL: @or1_eq1_multiple(
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ult i32 [[X:%.*]], 2
+; CHECK-NEXT:    store i1 [[CMP1]], ptr [[PTR:%.*]], align 1
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp ult i32 [[Y:%.*]], 2
+; CHECK-NEXT:    store i1 [[CMP2]], ptr [[PTR1:%.*]], align 1
+; CHECK-NEXT:    [[CMP3:%.*]] = icmp ult i32 [[Z:%.*]], 2
+; CHECK-NEXT:    ret i1 [[CMP3]]
+;
+  %t0 = or i32 %x, 1
+  %cmp0 = icmp eq i32 %t0, 1
+  store i1 %cmp0, ptr %ptr0
+
+  %t1 = or i32 %y, 1
+  %cmp1 = icmp eq i32 %t1, 1
+  store i1 %cmp1, ptr %ptr1
+
+  %t2 = or i32 %z, 1
+  %cmp2 = icmp eq i32 %t2, 1
+  ret i1 %cmp2
+}
+
+define <2 x i1> @or1_eq1_multiple_vec(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z, ptr %ptr0, ptr %ptr1) {
+; CHECK-LABEL: @or1_eq1_multiple_vec(
+; CHECK-NEXT:    [[CMP0:%.*]] = icmp ult <2 x i32> [[X:%.*]], splat (i32 2)
+; CHECK-NEXT:    store <2 x i1> [[CMP0]], ptr [[PTR0:%.*]], align 1
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ult <2 x i32> [[Y:%.*]], splat (i32 2)
+; CHECK-NEXT:    store <2 x i1> [[CMP1]], ptr [[PTR1:%.*]], align 1
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp ult <2 x i32> [[Z:%.*]], splat (i32 2)
+; CHECK-NEXT:    ret <2 x i1> [[CMP2]]
+;
+  %t0 = or <2 x i32> %x, splat (i32 1)
+  %cmp0 = icmp eq <2 x i32> %t0, splat (i32 1)
+  store <2 x i1> %cmp0, ptr %ptr0
+
+  %t1 = or <2 x i32> %y, splat (i32 1)
+  %cmp1 = icmp eq <2 x i32> %t1, splat (i32 1)
+  store <2 x i1> %cmp1, ptr %ptr1
+
+  %t2 = or <2 x i32> %z, splat (i32 1)
+  %cmp2 = icmp eq <2 x i32> %t2, splat (i32 1)
+  ret <2 x i1> %cmp2
+}
+
 ; X | C == C --> X <=u C (when C+1 is PowerOf2).
 
 define <2 x i1> @or3_eq3_vec(<2 x i8> %x) {
diff --git a/llvm/test/Transforms/InstCombine/max-min-canonicalize.ll b/llvm/test/Transforms/InstCombine/max-min-canonicalize.ll
new file mode 100644
index 0000000000000..d438c07cf2fbe
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/max-min-canonicalize.ll
@@ -0,0 +1,367 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+
+; smax(smin(X, MinC), MaxC) -> smin(smax(X, MaxC), MinC)
+; umax(umin(X, MinC), MaxC) -> umin(smax(X, MaxC), MinC)
+
+
+define i16 @smax_smin(i16 %x) {
+; CHECK-LABEL: define i16 @smax_smin(
+; CHECK-SAME: i16 [[X:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = call i16 @llvm.smax.i16(i16 [[X]], i16 -1)
+; CHECK-NEXT:    [[MAX:%.*]] = call i16 @llvm.smin.i16(i16 [[TMP1]], i16 255)
+; CHECK-NEXT:    ret i16 [[MAX]]
+;
+  %min = call i16 @llvm.smin.i16(i16 %x, i16 255)
+  %max = call i16 @llvm.smax.i16(i16 %min, i16 -1)
+  ret i16 %max
+}
+
+define i16 @umax_umin(i16 %x) {
+; CHECK-LABEL: define i16 @umax_umin(
+; CHECK-SAME: i16 [[X:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = call i16 @llvm.umax.i16(i16 [[X]], i16 63)
+; CHECK-NEXT:    [[MAX:%.*]] = call i16 @llvm.umin.i16(i16 [[TMP1]], i16 255)
+; CHECK-NEXT:    ret i16 [[MAX]]
+;
+  %min = call i16 @llvm.umin.i16(i16 %x, i16 255)
+  %max = call i16 @llvm.umax.i16(i16 %min, i16 63)
+  ret i16 %max
+}
+
+define i16 @smax_smin_commute0(i16 %x) {
+; CHECK-LABEL: define i16 @smax_smin_commute0(
+; CHECK-SAME: i16 [[X:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = call i16 @llvm.smax.i16(i16 [[X]], i16 -128)
+; CHECK-NEXT:    [[MAX:%.*]] = call i16 @llvm.smin.i16(i16 [[TMP1]], i16 127)
+; CHECK-NEXT:    ret i16 [[MAX]]
+;
+  %min = call i16 @llvm.smin.i16(i16 %x, i16 127)
+  %max = call i16 @llvm.smax.i16(i16 %min, i16 -128)
+  ret i16 %max
+}
+
+define i16 @umax_umin_commute0(i16 %x) {
+; CHECK-LABEL: define i16 @umax_umin_commute0(
+; CHECK-SAME: i16 [[X:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = call i16 @llvm.umax.i16(i16 [[X]], i16 127)
+; CHECK-NEXT:    [[MAX:%.*]] = call i16 @llvm.umin.i16(i16 [[TMP1]], i16 255)
+; CHECK-NEXT:    ret i16 [[MAX]]
+;
+  %min = call i16 @llvm.umin.i16(i16 %x, i16 255)
+  %max = call i16 @llvm.umax.i16(i16 %min, i16 127)
+  ret i16 %max
+}
+
+define i16 @smax_smin_commute1(i16 %x) {
+; CHECK-LABEL: define i16 @smax_smin_commute1(
+; CHECK-SAME: i16 [[X:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = call i16 @llvm.smax.i16(i16 [[X]], i16 -128)
+; CHECK-NEXT:    [[MAX:%.*]] = call i16 @llvm.smin.i16(i16 [[TMP1]], i16 127)
+; CHECK-NEXT:    ret i16 [[MAX]]
+;
+  %min = call i16 @llvm.smin.i16(i16 127, i16 %x)
+  %max = call i16 @llvm.smax.i16(i16 %min, i16 -128)
+  ret i16 %max
+}
+
+define i16 @umax_umin_commute1(i16 %x) {
+; CHECK-LABEL: define i16 @umax_umin_commute1(
+; CHECK-SAME: i16 [[X:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = call i16 @llvm.umax.i16(i16 [[X]], i16 127)
+; CHECK-NEXT:    [[MAX:%.*]] = call i16 @llvm.umin.i16(i16 [[TMP1]], i16 255)
+; CHECK-NEXT:    ret i16 [[MAX]]
+;
+  %min = call i16 @llvm.umin.i16(i16 255, i16 %x)
+  %max = call i16 @llvm.umax.i16(i16 %min, i16 127)
+  ret i16 %max
+}
+
+define i16 @smax_smin_commute2(i16 %x) {
+; CHECK-LABEL: define i16 @smax_smin_commute2(
+; CHECK-SAME: i16 [[X:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = call i16 @llvm.smax.i16(i16 [[X]], i16 -128)
+; CHECK-NEXT:    [[MAX:%.*]] = call i16 @llvm.smin.i16(i16 [[TMP1]], i16 127)
+; CHECK-NEXT:    ret i16 [[MAX]]
+;
+  %min = call i16 @llvm.smin.i16(i16 %x, i16 127)
+  %max = call i16 @llvm.smax.i16(i16 -128, i16 %min)
+  ret i16 %max
+}
+
+define i16 @umax_umin_commute2(i16 %x) {
+; CHECK-LABEL: define i16 @umax_umin_commute2(
+; CHECK-SAME: i16 [[X:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = call i16 @llvm.umax.i16(i16 [[X]], i16 127)
+; CHECK-NEXT:    [[MAX:%.*]] = call i16 @llvm.umin.i16(i16 [[TMP1]], i16 255)
+; CHECK-NEXT:    ret i16 [[MAX]]
+;
+  %min = call i16 @llvm.umin.i16(i16 %x, i16 255)
+  %max = call i16 @llvm.umax.i16(i16 127, i16 %min)
+  ret i16 %max
+}
+
+define i16 @smax_smin_commute3(i16 %x) {
+; CHECK-LABEL: define i16 @smax_smin_commute3(
+; CHECK-SAME: i16 [[X:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = call i16 @llvm.smax.i16(i16 [[X]], i16 -128)
+; CHECK-NEXT:    [[MAX:%.*]] = call i16 @llvm.smin.i16(i16 [[TMP1]], i16 127)
+; CHECK-NEXT:    ret i16 [[MAX]]
+;
+  %min = call i16 @llvm.smin.i16(i16 %x, i16 127)
+  %max = call i16 @llvm.smax.i16(i16 %min, i16 -128)
+  ret i16 %max
+}
+
+define i16 @umax_umin_commute3(i16 %x) {
+; CHECK-LABEL: define i16 @umax_umin_commute3(
+; CHECK-SAME: i16 [[X:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = call i16 @llvm.umax.i16(i16 [[X]], i16 127)
+; CHECK-NEXT:    [[MAX:%.*]] = call i16 @llvm.umin.i16(i16 [[TMP1]], i16 255)
+; CHECK-NEXT:    ret i16 [[MAX]]
+;
+  %min = call i16 @llvm.umin.i16(i16 %x, i16 255)
+  %max = call i16 @llvm.umax.i16(i16 %min, i16 127)
+  ret i16 %max
+}
+
+define <2 x i16> @smax_smin_v2i16(<2 x i16> %x) {
+; CHECK-LABEL: define <2 x i16> @smax_smin_v2i16(
+; CHECK-SAME: <2 x i16> [[X:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i16> @llvm.smax.v2i16(<2 x i16> [[X]], <2 x i16> splat (i16 -128))
+; CHECK-NEXT:    [[MAX:%.*]] = call <2 x i16> @llvm.smin.v2i16(<2 x i16> [[TMP1]], <2 x i16> splat (i16 127))
+; CHECK-NEXT:    ret <2 x i16> [[MAX]]
+;
+  %min = call <2 x i16> @llvm.smin.v2i16(<2 x i16> %x, <2 x i16> splat (i16 127))
+  %max = call <2 x i16> @llvm.smax.v2i16(<2 x i16> %min, <2 x i16> splat (i16 -128))
+  ret <2 x i16> %max
+}
+
+define <2 x i16> @umax_umin_v2i16(<2 x i16> %x) {
+; CHECK-LABEL: define <2 x i16> @umax_umin_v2i16(
+; CHECK-SAME: <2 x i16> [[X:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i16> @llvm.umax.v2i16(<2 x i16> [[X]], <2 x i16> splat (i16 127))
+; CHECK-NEXT:    [[MAX:%.*]] = call <2 x i16> @llvm.umin.v2i16(<2 x i16> [[TMP1]], <2 x i16> splat (i16 255))
+; CHECK-NEXT:    ret <2 x i16> [[MAX]]
+;
+  %min = call <2 x i16> @llvm.umin.v2i16(<2 x i16> %x, <2 x i16> splat (i16 255))
+  %max = call <2 x i16> @llvm.umax.v2i16(<2 x i16> %min, <2 x i16> splat (i16 127))
+  ret <2 x i16> %max
+}
+
+define <2 x i8> @smax_smin_v2i16_nonsplat_1(<2 x i8> %a) {
+; CHECK-LABEL: define <2 x i8> @smax_smin_v2i16_nonsplat_1(
+; CHECK-SAME: <2 x i8> [[A:%.*]]) {
+; CHECK-NEXT:    [[MIN:%.*]] = call <2 x i8> @llvm.smin.v2i8(<2 x i8> [[A]], <2 x i8> <i8 20, i8 10>)
+; CHECK-NEXT:    [[MAX:%.*]] = call <2 x i8> @llvm.smax.v2i8(<2 x i8> [[MIN]], <2 x i8> <i8 10, i8 0>)
+; CHECK-NEXT:    ret <2 x i8> [[MAX]]
+;
+  %min = call <2 x i8> @llvm.smin(<2 x i8> %a, <2 x i8> <i8 20, i8 10>)
+  %max = call <2 x i8> @llvm.smax(<2 x i8> %min, <2 x i8> <i8 10, i8 0>)
+  ret <2 x i8> %max
+}
+
+define <2 x i16> @umax_umin_v2i16_nonsplat_1(<2 x i16> %a) {
+; CHECK-LABEL: define <2 x i16> @umax_umin_v2i16_nonsplat_1(
+; CHECK-SAME: <2 x i16> [[A:%.*]]) {
+; CHECK-NEXT:    [[MIN:%.*]] = call <2 x i16> @llvm.umin.v2i16(<2 x i16> [[A]], <2 x i16> <i16 20, i16 10>)
+; CHECK-NEXT:    [[MAX:%.*]] = call <2 x i16> @llvm.umax.v2i16(<2 x i16> [[MIN]], <2 x i16> <i16 10, i16 1>)
+; CHECK-NEXT:    ret <2 x i16> [[MAX]]
+;
+  %min = call <2 x i16> @llvm.umin(<2 x i16> %a, <2 x i16> <i16 20, i16 10>)
+  %max = call <2 x i16> @llvm.umax(<2 x i16> %min, <2 x i16> <i16 10, i16 1>)
+  ret <2 x i16> %max
+}
+
+define <2 x i8> @smax_smin_v2i16_nonsplat_2(<2 x i8> %a) {
+; CHECK-LABEL: define <2 x i8> @smax_smin_v2i16_nonsplat_2(
+; CHECK-SAME: <2 x i8> [[A:%.*]]) {
+; CHECK-NEXT:    [[MIN:%.*]] = call <2 x i8> @llvm.smin.v2i8(<2 x i8> [[A]], <2 x i8> <i8 0, i8 10>)
+; CHECK-NEXT:    [[MAX:%.*]] = call <2 x i8> @llvm.smax.v2i8(<2 x i8> [[MIN]], <2 x i8> <i8 10, i8 0>)
+; CHECK-NEXT:    ret <2 x i8> [[MAX]]
+;
+  %min = call <2 x i8> @llvm.smin(<2 x i8> %a, <2 x i8> <i8 0, i8 10>)
+  %max = call <2 x i8> @llvm.smax(<2 x i8> %min, <2 x i8> <i8 10, i8 0>)
+  ret <2 x i8> %max
+}
+
+define <2 x i16> @umax_umin_v2i16_nonsplat_2(<2 x i16> %a) {
+; CHECK-LABEL: define <2 x i16> @umax_umin_v2i16_nonsplat_2(
+; CHECK-SAME: <2 x i16> [[A:%.*]]) {
+; CHECK-NEXT:    [[MIN:%.*]] = call <2 x i16> @llvm.umin.v2i16(<2 x i16> [[A]], <2 x i16> <i16 1, i16 10>)
+; CHECK-NEXT:    [[MAX:%.*]] = call <2 x i16> @llvm.umax.v2i16(<2 x i16> [[MIN]], <2 x i16> <i16 10, i16 1>)
+; CHECK-NEXT:    ret <2 x i16> [[MAX]]
+;
+  %min = call <2 x i16> @llvm.umin(<2 x i16> %a, <2 x i16> <i16 1, i16 10>)
+  %max = call <2 x i16> @llvm.umax(<2 x i16> %min, <2 x i16> <i16 10, i16 1>)
+  ret <2 x i16> %max
+}
+
+declare void @use(i16)
+
+define i16 @smax_smin_used(i16 %x) {
+; CHECK-LABEL: define i16 @smax_smin_used(
+; CHECK-SAME: i16 [[X:%.*]]) {
+; CHECK-NEXT:    [[MIN:%.*]] = call i16 @llvm.smin.i16(i16 [[X]], i16 127)
+; CHECK-NEXT:    [[MAX:%.*]] = call i16 @llvm.smax.i16(i16 [[MIN]], i16 -128)
+; CHECK-NEXT:    call void @use(i16 [[MIN]])
+; CHECK-NEXT:    ret i16 [[MAX]]
+;
+  %min = call i16 @llvm.smin.i16(i16 %x, i16 127)
+  %max = call i16 @llvm.smax.i16(i16 %min, i16 -128)
+  call void @use(i16 %min)
+  ret i16 %max
+}
+
+define i16 @umax_umin_used(i16 %x) {
+; CHECK-LABEL: define i16 @umax_umin_used(
+; CHECK-SAME: i16 [[X:%.*]]) {
+; CHECK-NEXT:    [[MIN:%.*]] = call i16 @llvm.umin.i16(i16 [[X]], i16 255)
+; CHECK-NEXT:    [[MAX:%.*]] = call i16 @llvm.umax.i16(i16 [[MIN]], i16 127)
+; CHECK-NEXT:    call void @use(i16 [[MIN]])
+; CHECK-NEXT:    ret i16 [[MAX]]
+;
+  %min = call i16 @llvm.umin.i16(i16 %x, i16 255)
+  %max = call i16 @llvm.umax.i16(i16 %min, i16 127)
+  call void @use(i16 %min)
+  ret i16 %max
+}
+
+
+define i16 @smax_smin_i16_limits(i16 %x) {
+; CHECK-LABEL: define i16 @smax_smin_i16_limits(
+; CHECK-SAME: i16 [[X:%.*]]) {
+; CHECK-NEXT:    ret i16 [[X]]
+;
+  %min = call i16 @llvm.smin.i16(i16 %x, i16 32767)
+  %max = call i16 @llvm.smax.i16(i16 %min, i16 -32768)
+  ret i16 %max
+}
+
+define i16 @umax_umin_i16_limits(i16 %x) {
+; CHECK-LABEL: define i16 @umax_umin_i16_limits(
+; CHECK-SAME: i16 [[X:%.*]]) {
+; CHECK-NEXT:    ret i16 [[X]]
+;
+  %min = call i16 @llvm.umin.i16(i16 %x, i16 65535)
+  %max = call i16 @llvm.umax.i16(i16 %min, i16 0)
+  ret i16 %max
+}
+
+define i16 @min_smax_smin_nested(i16 %x) {
+; CHECK-LABEL: define i16 @min_smax_smin_nested(
+; CHECK-SAME: i16 [[X:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = call i16 @llvm.smax.i16(i16 [[X]], i16 -128)
+; CHECK-NEXT:    [[MIN2:%.*]] = call i16 @llvm.smin.i16(i16 [[TMP1]], i16 127)
+; CHECK-NEXT:    ret i16 [[MIN2]]
+;
+  %min1 = call i16 @llvm.smin.i16(i16 %x, i16 255)
+  %max = call i16 @llvm.smax.i16(i16 %min1, i16 -128)
+  %min2 = call i16 @llvm.smin.i16(i16 %max, i16 127)
+  ret i16 %min2
+}
+
+define i16 @umax_umin_nested(i16 %x) {
+; CHECK-LABEL: define i16 @umax_umin_nested(
+; CHECK-SAME: i16 [[X:%.*]]) {
+; CHECK-NEXT:    [[MAX:%.*]] = call i16 @llvm.umax.i16(i16 [[X]], i16 63)
+; CHECK-NEXT:    [[MIN2:%.*]] = call i16 @llvm.umin.i16(i16 [[MAX]], i16 127)
+; CHECK-NEXT:    ret i16 [[MIN2]]
+;
+  %min1 = call i16 @llvm.umin.i16(i16 %x, i16 255)
+  %max = call i16 @llvm.umax.i16(i16 %min1, i16 63)
+  %min2 = call i16 @llvm.umin.i16(i16 %max, i16 127)
+  ret i16 %min2
+}
+
+define i16 @smax_smin_cmax_sgt_cmin(i16 %x) {
+; CHECK-LABEL: define i16 @smax_smin_cmax_sgt_cmin(
+; CHECK-SAME: i16 [[X:%.*]]) {
+; CHECK-NEXT:    ret i16 127
+;
+  %min = call i16 @llvm.smin.i16(i16 %x, i16 126)
+  %max = call i16 @llvm.smax.i16(i16 %min, i16 127)
+  ret i16 %max
+}
+
+define i16 @umax_umin_cmax_ugt_cmin(i16 %x) {
+; CHECK-LABEL: define i16 @umax_umin_cmax_ugt_cmin(
+; CHECK-SAME: i16 [[X:%.*]]) {
+; CHECK-NEXT:    ret i16 127
+;
+  %min = call i16 @llvm.umin.i16(i16 %x, i16 126)
+  %max = call i16 @llvm.umax.i16(i16 %min, i16 127)
+  ret i16 %max
+}
+
+define i16 @smax_smin_variables(i16 %x, i16 %y, i16 %z) {
+; CHECK-LABEL: define i16 @smax_smin_variables(
+; CHECK-SAME: i16 [[X:%.*]], i16 [[Y:%.*]], i16 [[Z:%.*]]) {
+; CHECK-NEXT:    [[MIN:%.*]] = call i16 @llvm.smin.i16(i16 [[X]], i16 [[Y]])
+; CHECK-NEXT:    [[MAX:%.*]] = call i16 @llvm.smax.i16(i16 [[MIN]], i16 [[Z]])
+; CHECK-NEXT:    ret i16 [[MAX]]
+;
+  %min = call i16 @llvm.smin.i16(i16 %x, i16 %y)
+  %max = call i16 @llvm.smax.i16(i16 %min, i16 %z)
+  ret i16 %max
+}
+
+define i16 @umax_umin_variables(i16 %x, i16 %y, i16 %z) {
+; CHECK-LABEL: define i16 @umax_umin_variables(
+; CHECK-SAME: i16 [[X:%.*]], i16 [[Y:%.*]], i16 [[Z:%.*]]) {
+; CHECK-NEXT:    [[MIN:%.*]] = call i16 @llvm.umin.i16(i16 [[X]], i16 [[Y]])
+; CHECK-NEXT:    [[MAX:%.*]] = call i16 @llvm.umax.i16(i16 [[MIN]], i16 [[Z]])
+; CHECK-NEXT:    ret i16 [[MAX]]
+;
+  %min = call i16 @llvm.umin.i16(i16 %x, i16 %y)
+  %max = call i16 @llvm.umax.i16(i16 %min, i16 %z)
+  ret i16 %max
+}
+
+define i16 @smin_smax(i16 %x) {
+; CHECK-LABEL: define i16 @smin_smax(
+; CHECK-SAME: i16 [[X:%.*]]) {
+; CHECK-NEXT:    [[MAX:%.*]] = call i16 @llvm.smax.i16(i16 [[X]], i16 -128)
+; CHECK-NEXT:    [[MIN:%.*]] = call i16 @llvm.smin.i16(i16 [[MAX]], i16 127)
+; CHECK-NEXT:    ret i16 [[MIN]]
+;
+  %max = call i16 @llvm.smax.i16(i16 %x, i16 -128)
+  %min = call i16 @llvm.smin.i16(i16 %max, i16 127)
+  ret i16 %min
+}
+
+define i16 @umin_umax(i16 %x) {
+; CHECK-LABEL: define i16 @umin_umax(
+; CHECK-SAME: i16 [[X:%.*]]) {
+; CHECK-NEXT:    [[MAX:%.*]] = call i16 @llvm.umax.i16(i16 [[X]], i16 127)
+; CHECK-NEXT:    [[MIN:%.*]] = call i16 @llvm.umin.i16(i16 [[MAX]], i16 255)
+; CHECK-NEXT:    ret i16 [[MIN]]
+;
+  %max = call i16 @llvm.umax.i16(i16 %x, i16 127)
+  %min = call i16 @llvm.umin.i16(i16 %max, i16 255)
+  ret i16 %min
+}
+
+define i16 @smin_umax(i16 %x) {
+; CHECK-LABEL: define i16 @smin_umax(
+; CHECK-SAME: i16 [[X:%.*]]) {
+; CHECK-NEXT:    [[MAX:%.*]] = call i16 @llvm.umax.i16(i16 [[X]], i16 127)
+; CHECK-NEXT:    [[MIN:%.*]] = call i16 @llvm.smin.i16(i16 [[MAX]], i16 255)
+; CHECK-NEXT:    ret i16 [[MIN]]
+;
+  %max = call i16 @llvm.umax.i16(i16 %x, i16 127)
+  %min = call i16 @llvm.smin.i16(i16 %max, i16 255)
+  ret i16 %min
+}
+
+define i16 @umin_smax(i16 %x) {
+; CHECK-LABEL: define i16 @umin_smax(
+; CHECK-SAME: i16 [[X:%.*]]) {
+; CHECK-NEXT:    [[MAX:%.*]] = call i16 @llvm.smax.i16(i16 [[X]], i16 -128)
+; CHECK-NEXT:    [[MIN:%.*]] = call i16 @llvm.umin.i16(i16 [[MAX]], i16 127)
+; CHECK-NEXT:    ret i16 [[MIN]]
+;
+  %max = call i16 @llvm.smax.i16(i16 %x, i16 -128)
+  %min = call i16 @llvm.umin.i16(i16 %max, i16 127)
+  ret i16 %min
+}
diff --git a/llvm/test/Transforms/InstCombine/max_known_bits.ll b/llvm/test/Transforms/InstCombine/max_known_bits.ll
index 3eb53b32efecc..162abf0efb7cc 100644
--- a/llvm/test/Transforms/InstCombine/max_known_bits.ll
+++ b/llvm/test/Transforms/InstCombine/max_known_bits.ll
@@ -35,9 +35,9 @@ define i16 @min_max_clamp(i16 %x) {
 ; Same as above with min/max reversed.
 define i16 @min_max_clamp_2(i16 %x) {
 ; CHECK-LABEL: @min_max_clamp_2(
-; CHECK-NEXT:    [[B:%.*]] = call i16 @llvm.smin.i16(i16 [[X:%.*]], i16 2047)
-; CHECK-NEXT:    [[D:%.*]] = call i16 @llvm.smax.i16(i16 [[B]], i16 -2048)
-; CHECK-NEXT:    [[E:%.*]] = add nsw i16 [[D]], 1
+; CHECK-NEXT:    [[D:%.*]] = call i16 @llvm.smax.i16(i16 [[B:%.*]], i16 -2048)
+; CHECK-NEXT:    [[D1:%.*]] = call i16 @llvm.smin.i16(i16 [[D]], i16 2047)
+; CHECK-NEXT:    [[E:%.*]] = add nsw i16 [[D1]], 1
 ; CHECK-NEXT:    ret i16 [[E]]
 ;
   %a = icmp slt i16 %x, 2047
@@ -71,9 +71,9 @@ define i32 @min_max_clamp_3(i16 %x) {
 ; Same as above with min/max order reversed
 define i32 @min_max_clamp_4(i16 %x) {
 ; CHECK-LABEL: @min_max_clamp_4(
-; CHECK-NEXT:    [[B:%.*]] = call i16 @llvm.smin.i16(i16 [[X:%.*]], i16 2047)
-; CHECK-NEXT:    [[D:%.*]] = call i16 @llvm.smax.i16(i16 [[B]], i16 -2048)
-; CHECK-NEXT:    [[TMP1:%.*]] = sext i16 [[D]] to i32
+; CHECK-NEXT:    [[D:%.*]] = call i16 @llvm.smax.i16(i16 [[B:%.*]], i16 -2048)
+; CHECK-NEXT:    [[D1:%.*]] = call i16 @llvm.smin.i16(i16 [[D]], i16 2047)
+; CHECK-NEXT:    [[TMP1:%.*]] = sext i16 [[D1]] to i32
 ; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %a = icmp slt i16 %x, 2047
@@ -106,9 +106,9 @@ define i16 @min_max_clamp_intrinsic(i16 %x) {
 
 define i16 @min_max_clamp_intrinsic_2(i16 %x) {
 ; CHECK-LABEL: @min_max_clamp_intrinsic_2(
-; CHECK-NEXT:    [[A:%.*]] = call i16 @llvm.smin.i16(i16 [[X:%.*]], i16 2047)
-; CHECK-NEXT:    [[B:%.*]] = call i16 @llvm.smax.i16(i16 [[A]], i16 -2048)
-; CHECK-NEXT:    [[C:%.*]] = add nsw i16 [[B]], 1
+; CHECK-NEXT:    [[B:%.*]] = call i16 @llvm.smax.i16(i16 [[A:%.*]], i16 -2048)
+; CHECK-NEXT:    [[B1:%.*]] = call i16 @llvm.smin.i16(i16 [[B]], i16 2047)
+; CHECK-NEXT:    [[C:%.*]] = add nsw i16 [[B1]], 1
 ; CHECK-NEXT:    ret i16 [[C]]
 ;
   %a = call i16 @llvm.smin.i16(i16 %x, i16 2047)
@@ -134,9 +134,9 @@ define i32 @min_max_clamp_intrinsic_3(i16 %x) {
 
 define i32 @min_max_clamp_intrinsic_4(i16 %x) {
 ; CHECK-LABEL: @min_max_clamp_intrinsic_4(
-; CHECK-NEXT:    [[A:%.*]] = call i16 @llvm.smin.i16(i16 [[X:%.*]], i16 2047)
-; CHECK-NEXT:    [[B:%.*]] = call i16 @llvm.smax.i16(i16 [[A]], i16 -2048)
-; CHECK-NEXT:    [[TMP1:%.*]] = sext i16 [[B]] to i32
+; CHECK-NEXT:    [[B:%.*]] = call i16 @llvm.smax.i16(i16 [[A:%.*]], i16 -2048)
+; CHECK-NEXT:    [[B1:%.*]] = call i16 @llvm.smin.i16(i16 [[B]], i16 2047)
+; CHECK-NEXT:    [[TMP1:%.*]] = sext i16 [[B1]] to i32
 ; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %a = call i16 @llvm.smin.i16(i16 %x, i16 2047)
diff --git a/llvm/test/Transforms/InstCombine/minmax-fold.ll b/llvm/test/Transforms/InstCombine/minmax-fold.ll
index 4d66e261c649c..cd376b74fb36c 100644
--- a/llvm/test/Transforms/InstCombine/minmax-fold.ll
+++ b/llvm/test/Transforms/InstCombine/minmax-fold.ll
@@ -346,9 +346,9 @@ define i32 @test75(i32 %x) {
 
 define i32 @clamp_signed1(i32 %x) {
 ; CHECK-LABEL: @clamp_signed1(
-; CHECK-NEXT:    [[MIN:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 255)
-; CHECK-NEXT:    [[R:%.*]] = call i32 @llvm.smax.i32(i32 [[MIN]], i32 15)
-; CHECK-NEXT:    ret i32 [[R]]
+; CHECK-NEXT:    [[R:%.*]] = call i32 @llvm.smax.i32(i32 [[MIN:%.*]], i32 15)
+; CHECK-NEXT:    [[R1:%.*]] = call i32 @llvm.smin.i32(i32 [[R]], i32 255)
+; CHECK-NEXT:    ret i32 [[R1]]
 ;
   %cmp2 = icmp slt i32 %x, 255
   %min = select i1 %cmp2, i32 %x, i32 255
@@ -376,9 +376,9 @@ define i32 @clamp_signed2(i32 %x) {
 
 define i32 @clamp_signed3(i32 %x) {
 ; CHECK-LABEL: @clamp_signed3(
-; CHECK-NEXT:    [[MIN:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 255)
-; CHECK-NEXT:    [[R:%.*]] = call i32 @llvm.smax.i32(i32 [[MIN]], i32 15)
-; CHECK-NEXT:    ret i32 [[R]]
+; CHECK-NEXT:    [[R:%.*]] = call i32 @llvm.smax.i32(i32 [[MIN:%.*]], i32 15)
+; CHECK-NEXT:    [[R1:%.*]] = call i32 @llvm.smin.i32(i32 [[R]], i32 255)
+; CHECK-NEXT:    ret i32 [[R1]]
 ;
   %cmp2 = icmp slt i32 %x, 255
   %min = select i1 %cmp2, i32 %x, i32 255
@@ -406,9 +406,9 @@ define i32 @clamp_signed4(i32 %x) {
 
 define i32 @clamp_unsigned1(i32 %x) {
 ; CHECK-LABEL: @clamp_unsigned1(
-; CHECK-NEXT:    [[MIN:%.*]] = call i32 @llvm.umin.i32(i32 [[X:%.*]], i32 255)
-; CHECK-NEXT:    [[R:%.*]] = call i32 @llvm.umax.i32(i32 [[MIN]], i32 15)
-; CHECK-NEXT:    ret i32 [[R]]
+; CHECK-NEXT:    [[R:%.*]] = call i32 @llvm.umax.i32(i32 [[MIN:%.*]], i32 15)
+; CHECK-NEXT:    [[R1:%.*]] = call i32 @llvm.umin.i32(i32 [[R]], i32 255)
+; CHECK-NEXT:    ret i32 [[R1]]
 ;
   %cmp2 = icmp ult i32 %x, 255
   %min = select i1 %cmp2, i32 %x, i32 255
@@ -436,9 +436,9 @@ define i32 @clamp_unsigned2(i32 %x) {
 
 define i32 @clamp_unsigned3(i32 %x) {
 ; CHECK-LABEL: @clamp_unsigned3(
-; CHECK-NEXT:    [[MIN:%.*]] = call i32 @llvm.umin.i32(i32 [[X:%.*]], i32 255)
-; CHECK-NEXT:    [[R:%.*]] = call i32 @llvm.umax.i32(i32 [[MIN]], i32 15)
-; CHECK-NEXT:    ret i32 [[R]]
+; CHECK-NEXT:    [[R:%.*]] = call i32 @llvm.umax.i32(i32 [[MIN:%.*]], i32 15)
+; CHECK-NEXT:    [[R1:%.*]] = call i32 @llvm.umin.i32(i32 [[R]], i32 255)
+; CHECK-NEXT:    ret i32 [[R1]]
 ;
   %cmp2 = icmp ult i32 %x, 255
   %min = select i1 %cmp2, i32 %x, i32 255
@@ -467,9 +467,9 @@ define i32 @clamp_unsigned4(i32 %x) {
 ; (icmp sgt smin(PositiveA, B) 0) -> (icmp sgt B 0)
 define i32 @clamp_check_for_no_infinite_loop1(i32 %i) {
 ; CHECK-LABEL: @clamp_check_for_no_infinite_loop1(
-; CHECK-NEXT:    [[SEL1:%.*]] = call i32 @llvm.smin.i32(i32 [[I:%.*]], i32 255)
-; CHECK-NEXT:    [[RES:%.*]] = call i32 @llvm.smax.i32(i32 [[SEL1]], i32 0)
-; CHECK-NEXT:    ret i32 [[RES]]
+; CHECK-NEXT:    [[RES:%.*]] = call i32 @llvm.smax.i32(i32 [[SEL1:%.*]], i32 0)
+; CHECK-NEXT:    [[RES1:%.*]] = call i32 @llvm.smin.i32(i32 [[RES]], i32 255)
+; CHECK-NEXT:    ret i32 [[RES1]]
 ;
   %cmp1 = icmp slt i32 %i, 255
   %sel1 = select i1 %cmp1, i32 %i, i32 255
@@ -1429,8 +1429,8 @@ define i8 @PR46271(<2 x i8> %x) {
 define i32 @twoway_clamp_lt(i32 %num) {
 ; CHECK-LABEL: @twoway_clamp_lt(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = icmp sgt i32 [[NUM:%.*]], 13767
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP0]], i32 13768, i32 13767
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp slt i32 [[NUM:%.*]], 13768
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP0]], i32 13767, i32 13768
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
 entry:
diff --git a/llvm/test/Transforms/InstCombine/minmax-intrinsics.ll b/llvm/test/Transforms/InstCombine/minmax-intrinsics.ll
index 0b7127f82b612..9a8608da9fd5b 100644
--- a/llvm/test/Transforms/InstCombine/minmax-intrinsics.ll
+++ b/llvm/test/Transforms/InstCombine/minmax-intrinsics.ll
@@ -774,8 +774,8 @@ define i8 @clamp_two_vals_smax_smin(i8 %x) {
 
 define <3 x i8> @clamp_two_vals_smin_smax(<3 x i8> %x) {
 ; CHECK-LABEL: @clamp_two_vals_smin_smax(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt <3 x i8> [[X:%.*]], splat (i8 41)
-; CHECK-NEXT:    [[R:%.*]] = select <3 x i1> [[TMP1]], <3 x i8> splat (i8 42), <3 x i8> splat (i8 41)
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <3 x i8> [[X:%.*]], splat (i8 42)
+; CHECK-NEXT:    [[R:%.*]] = select <3 x i1> [[TMP1]], <3 x i8> splat (i8 41), <3 x i8> splat (i8 42)
 ; CHECK-NEXT:    ret <3 x i8> [[R]]
 ;
   %m = call <3 x i8> @llvm.smin.v3i8(<3 x i8> %x, <3 x i8> <i8 42, i8 42, i8 42>)
@@ -796,8 +796,8 @@ define i8 @clamp_two_vals_umax_umin(i8 %x) {
 
 define i8 @clamp_two_vals_umin_umax(i8 %x) {
 ; CHECK-LABEL: @clamp_two_vals_umin_umax(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i8 [[X:%.*]], 41
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP1]], i8 42, i8 41
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i8 [[X:%.*]], 42
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP1]], i8 41, i8 42
 ; CHECK-NEXT:    ret i8 [[R]]
 ;
   %m = call i8 @llvm.umin.i8(i8 %x, i8 42)
@@ -2192,9 +2192,9 @@ define i8 @umin_umin_reassoc_constants(i8 %x) {
 
 define i8 @smin_smax_reassoc_constants(i8 %x) {
 ; CHECK-LABEL: @smin_smax_reassoc_constants(
-; CHECK-NEXT:    [[M1:%.*]] = call i8 @llvm.smin.i8(i8 [[X:%.*]], i8 97)
-; CHECK-NEXT:    [[M2:%.*]] = call i8 @llvm.smax.i8(i8 [[M1]], i8 -3)
-; CHECK-NEXT:    ret i8 [[M2]]
+; CHECK-NEXT:    [[M2:%.*]] = call i8 @llvm.smax.i8(i8 [[M1:%.*]], i8 -3)
+; CHECK-NEXT:    [[M3:%.*]] = call i8 @llvm.smin.i8(i8 [[M2]], i8 97)
+; CHECK-NEXT:    ret i8 [[M3]]
 ;
   %m1 = call i8 @llvm.smin.i8(i8 %x, i8 97)
   %m2 = call i8 @llvm.smax.i8(i8 %m1, i8 -3)
diff --git a/llvm/test/Transforms/InstCombine/sadd_sat.ll b/llvm/test/Transforms/InstCombine/sadd_sat.ll
index d27e7aa28d62c..6afb77d975b8c 100644
--- a/llvm/test/Transforms/InstCombine/sadd_sat.ll
+++ b/llvm/test/Transforms/InstCombine/sadd_sat.ll
@@ -77,8 +77,8 @@ define i32 @smul_sat32(i32 %a, i32 %b) {
 ; CHECK-NEXT:    [[CONV:%.*]] = sext i32 [[A:%.*]] to i64
 ; CHECK-NEXT:    [[CONV1:%.*]] = sext i32 [[B:%.*]] to i64
 ; CHECK-NEXT:    [[ADD:%.*]] = mul nsw i64 [[CONV1]], [[CONV]]
-; CHECK-NEXT:    [[SPEC_STORE_SELECT:%.*]] = call i64 @llvm.smin.i64(i64 [[ADD]], i64 2147483647)
-; CHECK-NEXT:    [[SPEC_STORE_SELECT8:%.*]] = call i64 @llvm.smax.i64(i64 [[SPEC_STORE_SELECT]], i64 -2147483648)
+; CHECK-NEXT:    [[TMP0:%.*]] = call i64 @llvm.smax.i64(i64 [[ADD]], i64 -2147483648)
+; CHECK-NEXT:    [[SPEC_STORE_SELECT8:%.*]] = call i64 @llvm.smin.i64(i64 [[TMP0]], i64 2147483647)
 ; CHECK-NEXT:    [[CONV7:%.*]] = trunc nsw i64 [[SPEC_STORE_SELECT8]] to i32
 ; CHECK-NEXT:    ret i32 [[CONV7]]
 ;
@@ -100,8 +100,8 @@ define i32 @smul_sat32_mm(i32 %a, i32 %b) {
 ; CHECK-NEXT:    [[CONV:%.*]] = sext i32 [[A:%.*]] to i64
 ; CHECK-NEXT:    [[CONV1:%.*]] = sext i32 [[B:%.*]] to i64
 ; CHECK-NEXT:    [[ADD:%.*]] = mul nsw i64 [[CONV1]], [[CONV]]
-; CHECK-NEXT:    [[SPEC_STORE_SELECT:%.*]] = call i64 @llvm.smin.i64(i64 [[ADD]], i64 2147483647)
-; CHECK-NEXT:    [[SPEC_STORE_SELECT8:%.*]] = call i64 @llvm.smax.i64(i64 [[SPEC_STORE_SELECT]], i64 -2147483648)
+; CHECK-NEXT:    [[TMP0:%.*]] = call i64 @llvm.smax.i64(i64 [[ADD]], i64 -2147483648)
+; CHECK-NEXT:    [[SPEC_STORE_SELECT8:%.*]] = call i64 @llvm.smin.i64(i64 [[TMP0]], i64 2147483647)
 ; CHECK-NEXT:    [[CONV7:%.*]] = trunc nsw i64 [[SPEC_STORE_SELECT8]] to i32
 ; CHECK-NEXT:    ret i32 [[CONV7]]
 ;
@@ -293,8 +293,8 @@ define signext i4 @sadd_sat4(i4 signext %a, i4 signext %b) {
 ; CHECK-NEXT:    [[CONV:%.*]] = sext i4 [[A:%.*]] to i32
 ; CHECK-NEXT:    [[CONV1:%.*]] = sext i4 [[B:%.*]] to i32
 ; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV1]], [[CONV]]
-; CHECK-NEXT:    [[SPEC_STORE_SELECT:%.*]] = call i32 @llvm.smin.i32(i32 [[ADD]], i32 7)
-; CHECK-NEXT:    [[SPEC_STORE_SELECT10:%.*]] = call i32 @llvm.smax.i32(i32 [[SPEC_STORE_SELECT]], i32 -8)
+; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @llvm.smax.i32(i32 [[ADD]], i32 -8)
+; CHECK-NEXT:    [[SPEC_STORE_SELECT10:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP0]], i32 7)
 ; CHECK-NEXT:    [[CONV9:%.*]] = trunc nsw i32 [[SPEC_STORE_SELECT10]] to i4
 ; CHECK-NEXT:    ret i4 [[CONV9]]
 ;
@@ -316,8 +316,8 @@ define signext i4 @ssub_sat4(i4 signext %a, i4 signext %b) {
 ; CHECK-NEXT:    [[CONV:%.*]] = sext i4 [[A:%.*]] to i32
 ; CHECK-NEXT:    [[CONV1:%.*]] = sext i4 [[B:%.*]] to i32
 ; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 [[CONV]], [[CONV1]]
-; CHECK-NEXT:    [[SPEC_STORE_SELECT:%.*]] = call i32 @llvm.smin.i32(i32 [[SUB]], i32 7)
-; CHECK-NEXT:    [[SPEC_STORE_SELECT10:%.*]] = call i32 @llvm.smax.i32(i32 [[SPEC_STORE_SELECT]], i32 -8)
+; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @llvm.smax.i32(i32 [[SUB]], i32 -8)
+; CHECK-NEXT:    [[SPEC_STORE_SELECT10:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP0]], i32 7)
 ; CHECK-NEXT:    [[CONV9:%.*]] = trunc nsw i32 [[SPEC_STORE_SELECT10]] to i4
 ; CHECK-NEXT:    ret i4 [[CONV9]]
 ;
@@ -405,8 +405,8 @@ define <4 x i32> @sadd_satv4i4(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: @sadd_satv4i4(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[ADD:%.*]] = add <4 x i32> [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[SPEC_STORE_SELECT:%.*]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[ADD]], <4 x i32> splat (i32 15))
-; CHECK-NEXT:    [[SPEC_STORE_SELECT8:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[SPEC_STORE_SELECT]], <4 x i32> splat (i32 -16))
+; CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[ADD]], <4 x i32> splat (i32 -16))
+; CHECK-NEXT:    [[SPEC_STORE_SELECT8:%.*]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[TMP0]], <4 x i32> splat (i32 15))
 ; CHECK-NEXT:    ret <4 x i32> [[SPEC_STORE_SELECT8]]
 ;
 entry:
@@ -422,8 +422,8 @@ define <4 x i32> @ssub_satv4i4(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: @ssub_satv4i4(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[ADD:%.*]] = sub <4 x i32> [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[SPEC_STORE_SELECT:%.*]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[ADD]], <4 x i32> splat (i32 15))
-; CHECK-NEXT:    [[SPEC_STORE_SELECT8:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[SPEC_STORE_SELECT]], <4 x i32> splat (i32 -16))
+; CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[ADD]], <4 x i32> splat (i32 -16))
+; CHECK-NEXT:    [[SPEC_STORE_SELECT8:%.*]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[TMP0]], <4 x i32> splat (i32 15))
 ; CHECK-NEXT:    ret <4 x i32> [[SPEC_STORE_SELECT8]]
 ;
 entry:
@@ -511,8 +511,8 @@ define i32 @sadd_sat32_extrause_3(i32 %a, i32 %b) {
 ; CHECK-NEXT:    [[CONV:%.*]] = sext i32 [[A:%.*]] to i64
 ; CHECK-NEXT:    [[CONV1:%.*]] = sext i32 [[B:%.*]] to i64
 ; CHECK-NEXT:    [[ADD:%.*]] = add nsw i64 [[CONV1]], [[CONV]]
-; CHECK-NEXT:    [[SPEC_STORE_SELECT:%.*]] = call i64 @llvm.smin.i64(i64 [[ADD]], i64 2147483647)
-; CHECK-NEXT:    [[SPEC_STORE_SELECT8:%.*]] = call i64 @llvm.smax.i64(i64 [[SPEC_STORE_SELECT]], i64 -2147483648)
+; CHECK-NEXT:    [[TMP0:%.*]] = call i64 @llvm.smax.i64(i64 [[ADD]], i64 -2147483648)
+; CHECK-NEXT:    [[SPEC_STORE_SELECT8:%.*]] = call i64 @llvm.smin.i64(i64 [[TMP0]], i64 2147483647)
 ; CHECK-NEXT:    [[CONV7:%.*]] = trunc nsw i64 [[SPEC_STORE_SELECT8]] to i32
 ; CHECK-NEXT:    call void @use64(i64 [[ADD]])
 ; CHECK-NEXT:    ret i32 [[CONV7]]
@@ -536,8 +536,8 @@ define i32 @sadd_sat32_extrause_3_mm(i32 %a, i32 %b) {
 ; CHECK-NEXT:    [[CONV:%.*]] = sext i32 [[A:%.*]] to i64
 ; CHECK-NEXT:    [[CONV1:%.*]] = sext i32 [[B:%.*]] to i64
 ; CHECK-NEXT:    [[ADD:%.*]] = add nsw i64 [[CONV1]], [[CONV]]
-; CHECK-NEXT:    [[SPEC_STORE_SELECT:%.*]] = call i64 @llvm.smin.i64(i64 [[ADD]], i64 2147483647)
-; CHECK-NEXT:    [[SPEC_STORE_SELECT8:%.*]] = call i64 @llvm.smax.i64(i64 [[SPEC_STORE_SELECT]], i64 -2147483648)
+; CHECK-NEXT:    [[TMP0:%.*]] = call i64 @llvm.smax.i64(i64 [[ADD]], i64 -2147483648)
+; CHECK-NEXT:    [[SPEC_STORE_SELECT8:%.*]] = call i64 @llvm.smin.i64(i64 [[TMP0]], i64 2147483647)
 ; CHECK-NEXT:    [[CONV7:%.*]] = trunc nsw i64 [[SPEC_STORE_SELECT8]] to i32
 ; CHECK-NEXT:    call void @use64(i64 [[ADD]])
 ; CHECK-NEXT:    ret i32 [[CONV7]]
@@ -559,8 +559,8 @@ define i32 @sadd_sat32_trunc(i32 %a, i32 %b) {
 ; CHECK-NEXT:    [[CONV:%.*]] = sext i32 [[A:%.*]] to i64
 ; CHECK-NEXT:    [[CONV1:%.*]] = sext i32 [[B:%.*]] to i64
 ; CHECK-NEXT:    [[ADD:%.*]] = add nsw i64 [[CONV1]], [[CONV]]
-; CHECK-NEXT:    [[SPEC_STORE_SELECT:%.*]] = call i64 @llvm.smin.i64(i64 [[ADD]], i64 32767)
-; CHECK-NEXT:    [[SPEC_STORE_SELECT8:%.*]] = call i64 @llvm.smax.i64(i64 [[SPEC_STORE_SELECT]], i64 -32768)
+; CHECK-NEXT:    [[TMP0:%.*]] = call i64 @llvm.smax.i64(i64 [[ADD]], i64 -32768)
+; CHECK-NEXT:    [[SPEC_STORE_SELECT8:%.*]] = call i64 @llvm.smin.i64(i64 [[TMP0]], i64 32767)
 ; CHECK-NEXT:    [[CONV7:%.*]] = trunc nsw i64 [[SPEC_STORE_SELECT8]] to i32
 ; CHECK-NEXT:    ret i32 [[CONV7]]
 ;
@@ -601,8 +601,8 @@ define i8 @sadd_sat8_ext8(i8 %a, i16 %b) {
 ; CHECK-NEXT:    [[CONV:%.*]] = sext i8 [[A:%.*]] to i32
 ; CHECK-NEXT:    [[CONV1:%.*]] = sext i16 [[B:%.*]] to i32
 ; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV1]], [[CONV]]
-; CHECK-NEXT:    [[SPEC_STORE_SELECT:%.*]] = call i32 @llvm.smin.i32(i32 [[ADD]], i32 127)
-; CHECK-NEXT:    [[SPEC_STORE_SELECT8:%.*]] = call i32 @llvm.smax.i32(i32 [[SPEC_STORE_SELECT]], i32 -128)
+; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @llvm.smax.i32(i32 [[ADD]], i32 -128)
+; CHECK-NEXT:    [[SPEC_STORE_SELECT8:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP0]], i32 127)
 ; CHECK-NEXT:    [[CONV7:%.*]] = trunc nsw i32 [[SPEC_STORE_SELECT8]] to i8
 ; CHECK-NEXT:    ret i8 [[CONV7]]
 ;
diff --git a/llvm/test/Transforms/InstCombine/select-min-max.ll b/llvm/test/Transforms/InstCombine/select-min-max.ll
index 0430fcd5ad370..99906620f8df2 100644
--- a/llvm/test/Transforms/InstCombine/select-min-max.ll
+++ b/llvm/test/Transforms/InstCombine/select-min-max.ll
@@ -216,8 +216,8 @@ define i32 @smax_smin(i32 %x) {
 
 define i32 @smin_smax(i32 %x) {
 ; CHECK-LABEL: @smin_smax(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], -2
-; CHECK-NEXT:    [[S:%.*]] = select i1 [[TMP1]], i32 -1, i32 -2
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], -1
+; CHECK-NEXT:    [[S:%.*]] = select i1 [[TMP1]], i32 -2, i32 -1
 ; CHECK-NEXT:    ret i32 [[S]]
 ;
   %m = call i32 @llvm.smin.i32(i32 %x, i32 -1)
@@ -240,8 +240,8 @@ define i8 @umax_umin(i8 %x) {
 
 define i8 @umin_umax(i8 %x) {
 ; CHECK-LABEL: @umin_umax(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i8 [[X:%.*]], 126
-; CHECK-NEXT:    [[S:%.*]] = select i1 [[TMP1]], i8 127, i8 126
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i8 [[X:%.*]], 127
+; CHECK-NEXT:    [[S:%.*]] = select i1 [[TMP1]], i8 126, i8 127
 ; CHECK-NEXT:    ret i8 [[S]]
 ;
   %m = call i8 @llvm.umin.i8(i8 %x, i8 127)
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll b/llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll
index 585c2df08f7d6..42a51bc7be30a 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll
@@ -1000,22 +1000,25 @@ define void @test_widen_exp_v2(ptr noalias %p2, ptr noalias %p, i64 %n) #5 {
 ; TFA_INTERLEAVE-NEXT:    [[ACTIVE_LANE_MASK:%.*]] = phi i1 [ [[ACTIVE_LANE_MASK_ENTRY]], %[[ENTRY]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], %[[PRED_STORE_CONTINUE5]] ]
 ; TFA_INTERLEAVE-NEXT:    [[ACTIVE_LANE_MASK2:%.*]] = phi i1 [ [[ACTIVE_LANE_MASK_ENTRY1]], %[[ENTRY]] ], [ [[ACTIVE_LANE_MASK_NEXT6:%.*]], %[[PRED_STORE_CONTINUE5]] ]
 ; TFA_INTERLEAVE-NEXT:    [[TMP4:%.*]] = load double, ptr [[P2]], align 8
-; TFA_INTERLEAVE-NEXT:    br i1 [[ACTIVE_LANE_MASK]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
-; TFA_INTERLEAVE:       [[PRED_STORE_IF]]:
 ; TFA_INTERLEAVE-NEXT:    [[TMP5:%.*]] = tail call double @llvm.exp.f64(double [[TMP4]]) #[[ATTR7:[0-9]+]]
-; TFA_INTERLEAVE-NEXT:    [[TMP6:%.*]] = fcmp ogt double [[TMP5]], 0.000000e+00
-; TFA_INTERLEAVE-NEXT:    [[TMP7:%.*]] = xor i1 [[TMP6]], true
-; TFA_INTERLEAVE-NEXT:    [[TMP24:%.*]] = select i1 [[TMP7]], double 1.000000e+00, double 0.000000e+00
-; TFA_INTERLEAVE-NEXT:    store double [[TMP24]], ptr [[P]], align 8
-; TFA_INTERLEAVE-NEXT:    br label %[[PRED_STORE_CONTINUE]]
-; TFA_INTERLEAVE:       [[PRED_STORE_CONTINUE]]:
-; TFA_INTERLEAVE-NEXT:    br i1 [[ACTIVE_LANE_MASK2]], label %[[PRED_STORE_IF4:.*]], label %[[PRED_STORE_CONTINUE5]]
-; TFA_INTERLEAVE:       [[PRED_STORE_IF4]]:
 ; TFA_INTERLEAVE-NEXT:    [[TMP8:%.*]] = tail call double @llvm.exp.f64(double [[TMP4]]) #[[ATTR7]]
+; TFA_INTERLEAVE-NEXT:    [[TMP6:%.*]] = fcmp ogt double [[TMP5]], 0.000000e+00
 ; TFA_INTERLEAVE-NEXT:    [[TMP9:%.*]] = fcmp ogt double [[TMP8]], 0.000000e+00
-; TFA_INTERLEAVE-NEXT:    [[TMP10:%.*]] = xor i1 [[TMP9]], true
+; TFA_INTERLEAVE-NEXT:    [[TMP18:%.*]] = xor i1 [[TMP6]], true
+; TFA_INTERLEAVE-NEXT:    [[TMP20:%.*]] = xor i1 [[TMP9]], true
+; TFA_INTERLEAVE-NEXT:    [[TMP10:%.*]] = select i1 [[ACTIVE_LANE_MASK]], i1 [[TMP18]], i1 false
+; TFA_INTERLEAVE-NEXT:    [[TMP21:%.*]] = select i1 [[ACTIVE_LANE_MASK2]], i1 [[TMP20]], i1 false
 ; TFA_INTERLEAVE-NEXT:    [[TMP26:%.*]] = select i1 [[TMP10]], double 1.000000e+00, double 0.000000e+00
-; TFA_INTERLEAVE-NEXT:    store double [[TMP26]], ptr [[P]], align 8
+; TFA_INTERLEAVE-NEXT:    [[PREDPHI3:%.*]] = select i1 [[TMP21]], double 1.000000e+00, double 0.000000e+00
+; TFA_INTERLEAVE-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[ACTIVE_LANE_MASK2]], double [[PREDPHI3]], double [[TMP26]]
+; TFA_INTERLEAVE-NEXT:    [[TMP13:%.*]] = xor i1 [[ACTIVE_LANE_MASK]], true
+; TFA_INTERLEAVE-NEXT:    [[TMP14:%.*]] = xor i1 [[ACTIVE_LANE_MASK2]], true
+; TFA_INTERLEAVE-NEXT:    [[TMP15:%.*]] = xor i1 [[TMP13]], true
+; TFA_INTERLEAVE-NEXT:    [[TMP16:%.*]] = xor i1 [[TMP14]], true
+; TFA_INTERLEAVE-NEXT:    [[TMP17:%.*]] = or i1 [[TMP15]], [[TMP16]]
+; TFA_INTERLEAVE-NEXT:    br i1 [[TMP17]], label %[[BB18:.*]], label %[[PRED_STORE_CONTINUE5]]
+; TFA_INTERLEAVE:       [[BB18]]:
+; TFA_INTERLEAVE-NEXT:    store double [[SPEC_SELECT]], ptr [[P]], align 8
 ; TFA_INTERLEAVE-NEXT:    br label %[[PRED_STORE_CONTINUE5]]
 ; TFA_INTERLEAVE:       [[PRED_STORE_CONTINUE5]]:
 ; TFA_INTERLEAVE-NEXT:    [[TMP27]] = add i64 [[INDEX]], 2
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-no-dotprod.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-no-dotprod.ll
index 2d60762ff36ba..09d09e2f0569c 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-no-dotprod.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-no-dotprod.ll
@@ -63,3 +63,59 @@ for.body:                                         ; preds = %for.body, %entry
 for.exit:                        ; preds = %for.body
   ret i32 %add
 }
+
+; Test to ensure that we don't crash when evaluating an extend from a type
+; that is not a factor of the target type.
+define i40 @partial_reduce_not_known_factor(i32 %a, i32 %b, i16 %N) {
+; CHECK-LABEL: define i40 @partial_reduce_not_known_factor(
+; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i16 [[N:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:  [[ENTRY:.*]]:
+; CHECK-NEXT:    [[SMAX:%.*]] = call i16 @llvm.smax.i16(i16 [[N]], i16 0)
+; CHECK-NEXT:    [[TMP0:%.*]] = zext nneg i16 [[SMAX]] to i32
+; CHECK-NEXT:    [[TMP1:%.*]] = add nuw nsw i32 [[TMP0]], 1
+; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP1]], 4
+; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK:       [[VECTOR_PH]]:
+; CHECK-NEXT:    [[N_MOD_VF:%.*]] = urem i32 [[TMP1]], 4
+; CHECK-NEXT:    [[N_VEC:%.*]] = sub i32 [[TMP1]], [[N_MOD_VF]]
+; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i32> poison, i32 [[B]], i64 0
+; CHECK-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i32> [[BROADCAST_SPLATINSERT]], <2 x i32> poison, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <2 x i32> poison, i32 [[A]], i64 0
+; CHECK-NEXT:    [[BROADCAST_SPLAT2:%.*]] = shufflevector <2 x i32> [[BROADCAST_SPLATINSERT1]], <2 x i32> poison, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = trunc i32 [[N_VEC]] to i16
+; CHECK-NEXT:    [[TMP3:%.*]] = sext <2 x i32> [[BROADCAST_SPLAT2]] to <2 x i40>
+; CHECK-NEXT:    [[TMP4:%.*]] = sext <2 x i32> [[BROADCAST_SPLAT]] to <2 x i40>
+; CHECK-NEXT:    [[TMP5:%.*]] = or <2 x i40> [[TMP4]], [[TMP3]]
+; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]
+; CHECK:       [[VECTOR_BODY]]:
+; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi <2 x i40> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[VEC_PHI3:%.*]] = phi <2 x i40> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP8:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[TMP6]] = or <2 x i40> [[VEC_PHI]], [[TMP5]]
+; CHECK-NEXT:    [[TMP8]] = or <2 x i40> [[VEC_PHI3]], [[TMP5]]
+; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
+; CHECK-NEXT:    [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT:    br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK:       [[MIDDLE_BLOCK]]:
+; CHECK-NEXT:    [[BIN_RDX:%.*]] = or <2 x i40> [[TMP8]], [[TMP6]]
+; CHECK-NEXT:    [[TMP9:%.*]] = call i40 @llvm.vector.reduce.or.v2i40(<2 x i40> [[BIN_RDX]])
+; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i32 [[TMP1]], [[N_VEC]]
+; CHECK-NEXT:    br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+entry:
+  br label %for.body
+
+for.body:
+  %red = phi i40 [ 0, %entry ], [ %1, %for.body ]
+  %iv = phi i16 [ 0, %entry ], [ %iv.next, %for.body ]
+  %resize = sext i32 %a to i40
+  %resize4 = sext i32 %b to i40
+  %0 = or i40 %resize4, %resize
+  %1 = or i40 %red, %0
+  %iv.next = add i16 %iv, 1
+  %cmp = icmp slt i16 %iv, %N
+  br i1 %cmp, label %for.body, label %exit
+
+exit:
+  %result.lcssa = phi i40 [ %1, %for.body ]
+  ret i40 %result.lcssa
+}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
index 56cea996f3d80..9257e45c809e9 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
@@ -753,6 +753,48 @@ for.exit:
   ret void
 }
 
+; The histogram operation generates vectors. This example used to crash
+; due to a missing entry in a switch statement.
+define void @histogram_generates_vectors_crash(ptr %data_array, ptr noalias %indices) {
+; CHECK-LABEL: define void @histogram_generates_vectors_crash(
+; CHECK-SAME: ptr [[DATA_ARRAY:%.*]], ptr noalias [[INDICES:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label [[FOR_BODY:%.*]]
+; CHECK:       for.body:
+; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT:    [[GEP_INDICES:%.*]] = getelementptr [1048576 x i32], ptr [[INDICES]], i64 [[IV]]
+; CHECK-NEXT:    [[L_IDX:%.*]] = load i32, ptr [[GEP_INDICES]], align 4
+; CHECK-NEXT:    [[IDXPROM5:%.*]] = sext i32 [[L_IDX]] to i64
+; CHECK-NEXT:    [[GEP_BUCKET:%.*]] = getelementptr [1048576 x i32], ptr [[DATA_ARRAY]], i64 [[IDXPROM5]]
+; CHECK-NEXT:    [[L_BUCKET:%.*]] = load i32, ptr [[GEP_BUCKET]], align 4
+; CHECK-NEXT:    [[INC:%.*]] = add i32 [[L_BUCKET]], 1
+; CHECK-NEXT:    store i32 [[INC]], ptr [[GEP_BUCKET]], align 4
+; CHECK-NEXT:    [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT:    [[EXITCOND:%.*]] = icmp eq i64 [[IV]], 1
+; CHECK-NEXT:    br i1 [[EXITCOND]], label [[FOR_EXIT:%.*]], label [[FOR_BODY]]
+; CHECK:       for.exit:
+; CHECK-NEXT:    ret void
+;
+entry:
+  br label %for.body
+
+for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %gep.indices = getelementptr [1048576 x i32], ptr %indices, i64 %iv
+  %l.idx = load i32, ptr %gep.indices, align 4
+  %idxprom5 = sext i32 %l.idx to i64
+  %gep.bucket = getelementptr [1048576 x i32], ptr %data_array, i64 %idxprom5
+  %l.bucket = load i32, ptr %gep.bucket, align 4
+  %inc = add i32 %l.bucket, 1
+  store i32 %inc, ptr %gep.bucket, align 4
+  %iv.next = add i64 %iv, 1
+  %exitcond = icmp eq i64 %iv, 1
+  br i1 %exitcond, label %for.exit, label %for.body
+
+for.exit:
+  ret void
+}
+
 attributes #0 = { "target-features"="+sve2" vscale_range(1,16) }
 
 !0 = distinct !{!0, !1}
diff --git a/llvm/test/Transforms/LoopVectorize/X86/pr51366-sunk-instruction-used-outside-of-loop.ll b/llvm/test/Transforms/LoopVectorize/X86/pr51366-sunk-instruction-used-outside-of-loop.ll
index c91ead00a950d..644f10b617eb7 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/pr51366-sunk-instruction-used-outside-of-loop.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/pr51366-sunk-instruction-used-outside-of-loop.ll
@@ -8,13 +8,13 @@ define ptr @test(ptr noalias %src, ptr noalias %dst) {
 ; CHECK-NEXT:    [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 0, i64 1>, %vector.ph ], [ [[VEC_IND_NEXT:%.*]], [[PRED_LOAD_CONTINUE2]] ]
 ; CHECK-NEXT:    [[TMP0:%.*]] = add i64 [[INDEX]], 0
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i64 [[INDEX]], 1
-; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[SRC:%.*]], i64 [[TMP1]]
+; CHECK-NEXT:    [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[SRC:%.*]], i64 [[TMP0]]
+; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[TMP1]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq <2 x i64> [[VEC_IND]], zeroinitializer
 ; CHECK-NEXT:    [[TMP4:%.*]] = xor <2 x i1> [[TMP3]], splat (i1 true)
 ; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <2 x i1> [[TMP4]], i32 0
 ; CHECK-NEXT:    br i1 [[TMP5]], label [[PRED_LOAD_IF:%.*]], label [[PRED_LOAD_CONTINUE:%.*]]
 ; CHECK:       pred.load.if:
-; CHECK-NEXT:    [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[TMP0]]
 ; CHECK-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
 ; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <2 x i32> poison, i32 [[TMP7]], i32 0
 ; CHECK-NEXT:    br label [[PRED_LOAD_CONTINUE]]
diff --git a/llvm/test/Transforms/LoopVectorize/X86/small-size.ll b/llvm/test/Transforms/LoopVectorize/X86/small-size.ll
index 6424fb5565a63..5917b300b4820 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/small-size.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/small-size.ll
@@ -258,6 +258,8 @@ define void @example2(i32 %n, i32 %x) optsize {
 
 ; Loop has no primary induction as its integer IV has step -1 starting at
 ; unknown N, but can still be vectorized.
+; Note: Most scalar pointer induction GEPs could be sunk into the conditional
+;       blocks.
 define void @example3(i32 %n, ptr noalias nocapture %p, ptr noalias nocapture %q) optsize {
 ; CHECK-LABEL: @example3(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i32 [[N:%.*]], 0
@@ -275,7 +277,19 @@ define void @example3(i32 %n, ptr noalias nocapture %p, ptr noalias nocapture %q
 ; CHECK:       vector.body:
 ; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE16:%.*]] ]
 ; CHECK-NEXT:    [[OFFSET_IDX:%.*]] = shl i64 [[INDEX]], 2
+; CHECK-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 [[OFFSET_IDX]]
+; CHECK-NEXT:    [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[TMP11]], i64 4
+; CHECK-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[P]], i64 [[OFFSET_IDX]]
+; CHECK-NEXT:    [[NEXT_GEP4:%.*]] = getelementptr i8, ptr [[TMP12]], i64 8
+; CHECK-NEXT:    [[TMP15:%.*]] = getelementptr i8, ptr [[P]], i64 [[OFFSET_IDX]]
+; CHECK-NEXT:    [[NEXT_GEP5:%.*]] = getelementptr i8, ptr [[TMP15]], i64 12
 ; CHECK-NEXT:    [[OFFSET_IDX6:%.*]] = shl i64 [[INDEX]], 2
+; CHECK-NEXT:    [[TMP16:%.*]] = getelementptr i8, ptr [[Q:%.*]], i64 [[OFFSET_IDX6]]
+; CHECK-NEXT:    [[NEXT_GEP8:%.*]] = getelementptr i8, ptr [[TMP16]], i64 4
+; CHECK-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[Q]], i64 [[OFFSET_IDX6]]
+; CHECK-NEXT:    [[NEXT_GEP9:%.*]] = getelementptr i8, ptr [[TMP7]], i64 8
+; CHECK-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[Q]], i64 [[OFFSET_IDX6]]
+; CHECK-NEXT:    [[NEXT_GEP10:%.*]] = getelementptr i8, ptr [[TMP8]], i64 12
 ; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[INDEX]], i64 0
 ; CHECK-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer
 ; CHECK-NEXT:    [[VEC_IV:%.*]] = or disjoint <4 x i64> [[BROADCAST_SPLAT]], <i64 0, i64 1, i64 2, i64 3>
@@ -283,8 +297,8 @@ define void @example3(i32 %n, ptr noalias nocapture %p, ptr noalias nocapture %q
 ; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x i1> [[TMP3]], i64 0
 ; CHECK-NEXT:    br i1 [[TMP4]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]
 ; CHECK:       pred.store.if:
-; CHECK-NEXT:    [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 [[OFFSET_IDX]]
-; CHECK-NEXT:    [[NEXT_GEP7:%.*]] = getelementptr i8, ptr [[Q:%.*]], i64 [[OFFSET_IDX6]]
+; CHECK-NEXT:    [[NEXT_GEP7:%.*]] = getelementptr i8, ptr [[Q]], i64 [[OFFSET_IDX6]]
+; CHECK-NEXT:    [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[P]], i64 [[OFFSET_IDX]]
 ; CHECK-NEXT:    [[TMP5:%.*]] = load i32, ptr [[NEXT_GEP7]], align 16
 ; CHECK-NEXT:    store i32 [[TMP5]], ptr [[NEXT_GEP]], align 16
 ; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE]]
@@ -292,10 +306,6 @@ define void @example3(i32 %n, ptr noalias nocapture %p, ptr noalias nocapture %q
 ; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <4 x i1> [[TMP3]], i64 1
 ; CHECK-NEXT:    br i1 [[TMP6]], label [[PRED_STORE_IF11:%.*]], label [[PRED_STORE_CONTINUE12:%.*]]
 ; CHECK:       pred.store.if11:
-; CHECK-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[P]], i64 [[OFFSET_IDX]]
-; CHECK-NEXT:    [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[TMP7]], i64 4
-; CHECK-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[Q]], i64 [[OFFSET_IDX6]]
-; CHECK-NEXT:    [[NEXT_GEP8:%.*]] = getelementptr i8, ptr [[TMP8]], i64 4
 ; CHECK-NEXT:    [[TMP9:%.*]] = load i32, ptr [[NEXT_GEP8]], align 16
 ; CHECK-NEXT:    store i32 [[TMP9]], ptr [[NEXT_GEP3]], align 16
 ; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE12]]
@@ -303,10 +313,6 @@ define void @example3(i32 %n, ptr noalias nocapture %p, ptr noalias nocapture %q
 ; CHECK-NEXT:    [[TMP10:%.*]] = extractelement <4 x i1> [[TMP3]], i64 2
 ; CHECK-NEXT:    br i1 [[TMP10]], label [[PRED_STORE_IF13:%.*]], label [[PRED_STORE_CONTINUE14:%.*]]
 ; CHECK:       pred.store.if13:
-; CHECK-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[P]], i64 [[OFFSET_IDX]]
-; CHECK-NEXT:    [[NEXT_GEP4:%.*]] = getelementptr i8, ptr [[TMP11]], i64 8
-; CHECK-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[Q]], i64 [[OFFSET_IDX6]]
-; CHECK-NEXT:    [[NEXT_GEP9:%.*]] = getelementptr i8, ptr [[TMP12]], i64 8
 ; CHECK-NEXT:    [[TMP13:%.*]] = load i32, ptr [[NEXT_GEP9]], align 16
 ; CHECK-NEXT:    store i32 [[TMP13]], ptr [[NEXT_GEP4]], align 16
 ; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE14]]
@@ -314,10 +320,6 @@ define void @example3(i32 %n, ptr noalias nocapture %p, ptr noalias nocapture %q
 ; CHECK-NEXT:    [[TMP14:%.*]] = extractelement <4 x i1> [[TMP3]], i64 3
 ; CHECK-NEXT:    br i1 [[TMP14]], label [[PRED_STORE_IF15:%.*]], label [[PRED_STORE_CONTINUE16]]
 ; CHECK:       pred.store.if15:
-; CHECK-NEXT:    [[TMP15:%.*]] = getelementptr i8, ptr [[P]], i64 [[OFFSET_IDX]]
-; CHECK-NEXT:    [[NEXT_GEP5:%.*]] = getelementptr i8, ptr [[TMP15]], i64 12
-; CHECK-NEXT:    [[TMP16:%.*]] = getelementptr i8, ptr [[Q]], i64 [[OFFSET_IDX6]]
-; CHECK-NEXT:    [[NEXT_GEP10:%.*]] = getelementptr i8, ptr [[TMP16]], i64 12
 ; CHECK-NEXT:    [[TMP17:%.*]] = load i32, ptr [[NEXT_GEP10]], align 16
 ; CHECK-NEXT:    store i32 [[TMP17]], ptr [[NEXT_GEP5]], align 16
 ; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE16]]
@@ -445,6 +447,8 @@ define void @example23b(ptr noalias nocapture %src, ptr noalias nocapture %dst)
 }
 
 ; We CAN vectorize this example by folding the tail it entails.
+; Note: Most scalar pointer induction GEPs could be sunk into the conditional
+;       blocks.
 define void @example23c(ptr noalias nocapture %src, ptr noalias nocapture %dst) optsize {
 ; CHECK-LABEL: @example23c(
 ; CHECK-NEXT:    br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
@@ -453,7 +457,19 @@ define void @example23c(ptr noalias nocapture %src, ptr noalias nocapture %dst)
 ; CHECK:       vector.body:
 ; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE15:%.*]] ]
 ; CHECK-NEXT:    [[OFFSET_IDX:%.*]] = shl i64 [[INDEX]], 1
+; CHECK-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[SRC:%.*]], i64 [[OFFSET_IDX]]
+; CHECK-NEXT:    [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[TMP7]], i64 2
+; CHECK-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[OFFSET_IDX]]
+; CHECK-NEXT:    [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[TMP8]], i64 4
+; CHECK-NEXT:    [[TMP13:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[OFFSET_IDX]]
+; CHECK-NEXT:    [[NEXT_GEP4:%.*]] = getelementptr i8, ptr [[TMP13]], i64 6
 ; CHECK-NEXT:    [[OFFSET_IDX5:%.*]] = shl i64 [[INDEX]], 2
+; CHECK-NEXT:    [[TMP14:%.*]] = getelementptr i8, ptr [[DST:%.*]], i64 [[OFFSET_IDX5]]
+; CHECK-NEXT:    [[NEXT_GEP7:%.*]] = getelementptr i8, ptr [[TMP14]], i64 4
+; CHECK-NEXT:    [[TMP19:%.*]] = getelementptr i8, ptr [[DST]], i64 [[OFFSET_IDX5]]
+; CHECK-NEXT:    [[NEXT_GEP8:%.*]] = getelementptr i8, ptr [[TMP19]], i64 8
+; CHECK-NEXT:    [[TMP20:%.*]] = getelementptr i8, ptr [[DST]], i64 [[OFFSET_IDX5]]
+; CHECK-NEXT:    [[NEXT_GEP9:%.*]] = getelementptr i8, ptr [[TMP20]], i64 12
 ; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[INDEX]], i64 0
 ; CHECK-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer
 ; CHECK-NEXT:    [[VEC_IV:%.*]] = or disjoint <4 x i64> [[BROADCAST_SPLAT]], <i64 0, i64 1, i64 2, i64 3>
@@ -461,8 +477,8 @@ define void @example23c(ptr noalias nocapture %src, ptr noalias nocapture %dst)
 ; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i1> [[TMP1]], i64 0
 ; CHECK-NEXT:    br i1 [[TMP2]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]
 ; CHECK:       pred.store.if:
-; CHECK-NEXT:    [[NEXT_GEP6:%.*]] = getelementptr i8, ptr [[DST:%.*]], i64 [[OFFSET_IDX5]]
-; CHECK-NEXT:    [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[SRC:%.*]], i64 [[OFFSET_IDX]]
+; CHECK-NEXT:    [[NEXT_GEP6:%.*]] = getelementptr i8, ptr [[DST]], i64 [[OFFSET_IDX5]]
+; CHECK-NEXT:    [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[OFFSET_IDX]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = load i16, ptr [[NEXT_GEP]], align 2
 ; CHECK-NEXT:    [[TMP4:%.*]] = zext i16 [[TMP3]] to i32
 ; CHECK-NEXT:    [[TMP5:%.*]] = shl nuw nsw i32 [[TMP4]], 7
@@ -472,10 +488,6 @@ define void @example23c(ptr noalias nocapture %src, ptr noalias nocapture %dst)
 ; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <4 x i1> [[TMP1]], i64 1
 ; CHECK-NEXT:    br i1 [[TMP6]], label [[PRED_STORE_IF9:%.*]], label [[PRED_STORE_CONTINUE10:%.*]]
 ; CHECK:       pred.store.if9:
-; CHECK-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[DST]], i64 [[OFFSET_IDX5]]
-; CHECK-NEXT:    [[NEXT_GEP7:%.*]] = getelementptr i8, ptr [[TMP7]], i64 4
-; CHECK-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[OFFSET_IDX]]
-; CHECK-NEXT:    [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[TMP8]], i64 2
 ; CHECK-NEXT:    [[TMP9:%.*]] = load i16, ptr [[NEXT_GEP2]], align 2
 ; CHECK-NEXT:    [[TMP10:%.*]] = zext i16 [[TMP9]] to i32
 ; CHECK-NEXT:    [[TMP11:%.*]] = shl nuw nsw i32 [[TMP10]], 7
@@ -485,10 +497,6 @@ define void @example23c(ptr noalias nocapture %src, ptr noalias nocapture %dst)
 ; CHECK-NEXT:    [[TMP12:%.*]] = extractelement <4 x i1> [[TMP1]], i64 2
 ; CHECK-NEXT:    br i1 [[TMP12]], label [[PRED_STORE_IF12:%.*]], label [[PRED_STORE_CONTINUE12:%.*]]
 ; CHECK:       pred.store.if11:
-; CHECK-NEXT:    [[TMP13:%.*]] = getelementptr i8, ptr [[DST]], i64 [[OFFSET_IDX5]]
-; CHECK-NEXT:    [[NEXT_GEP8:%.*]] = getelementptr i8, ptr [[TMP13]], i64 8
-; CHECK-NEXT:    [[TMP14:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[OFFSET_IDX]]
-; CHECK-NEXT:    [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[TMP14]], i64 4
 ; CHECK-NEXT:    [[TMP15:%.*]] = load i16, ptr [[NEXT_GEP3]], align 2
 ; CHECK-NEXT:    [[TMP16:%.*]] = zext i16 [[TMP15]] to i32
 ; CHECK-NEXT:    [[TMP17:%.*]] = shl nuw nsw i32 [[TMP16]], 7
@@ -498,10 +506,6 @@ define void @example23c(ptr noalias nocapture %src, ptr noalias nocapture %dst)
 ; CHECK-NEXT:    [[TMP18:%.*]] = extractelement <4 x i1> [[TMP1]], i64 3
 ; CHECK-NEXT:    br i1 [[TMP18]], label [[PRED_STORE_IF13:%.*]], label [[PRED_STORE_CONTINUE15]]
 ; CHECK:       pred.store.if13:
-; CHECK-NEXT:    [[TMP19:%.*]] = getelementptr i8, ptr [[DST]], i64 [[OFFSET_IDX5]]
-; CHECK-NEXT:    [[NEXT_GEP9:%.*]] = getelementptr i8, ptr [[TMP19]], i64 12
-; CHECK-NEXT:    [[TMP20:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[OFFSET_IDX]]
-; CHECK-NEXT:    [[NEXT_GEP4:%.*]] = getelementptr i8, ptr [[TMP20]], i64 6
 ; CHECK-NEXT:    [[TMP21:%.*]] = load i16, ptr [[NEXT_GEP4]], align 2
 ; CHECK-NEXT:    [[TMP22:%.*]] = zext i16 [[TMP21]] to i32
 ; CHECK-NEXT:    [[TMP23:%.*]] = shl nuw nsw i32 [[TMP22]], 7
diff --git a/llvm/test/Transforms/LoopVectorize/pointer-induction.ll b/llvm/test/Transforms/LoopVectorize/pointer-induction.ll
index 06b6a2b29c01e..d7dc68b082f29 100644
--- a/llvm/test/Transforms/LoopVectorize/pointer-induction.ll
+++ b/llvm/test/Transforms/LoopVectorize/pointer-induction.ll
@@ -3,7 +3,8 @@
 ; RUN: opt < %s -passes=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -lv-strided-pointer-ivs=true -S | FileCheck --check-prefixes=CHECK,STRIDED %s
 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
 
-
+; Note: Most scalar pointer induction GEPs could be sunk into the conditional
+;       blocks.
 ; Function Attrs: nofree norecurse nounwind
 define void @a(ptr readnone %b) {
 ; CHECK-LABEL: @a(
@@ -25,7 +26,13 @@ define void @a(ptr readnone %b) {
 ; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE10:%.*]] ]
 ; CHECK-NEXT:    [[OFFSET_IDX:%.*]] = sub i64 0, [[INDEX]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], 0
+; CHECK-NEXT:    [[TMP11:%.*]] = add i64 [[OFFSET_IDX]], -1
+; CHECK-NEXT:    [[TMP14:%.*]] = add i64 [[OFFSET_IDX]], -2
+; CHECK-NEXT:    [[TMP17:%.*]] = add i64 [[OFFSET_IDX]], -3
 ; CHECK-NEXT:    [[NEXT_GEP:%.*]] = getelementptr i8, ptr null, i64 [[TMP2]]
+; CHECK-NEXT:    [[NEXT_GEP2:%.*]] = getelementptr i8, ptr null, i64 [[TMP11]]
+; CHECK-NEXT:    [[NEXT_GEP3:%.*]] = getelementptr i8, ptr null, i64 [[TMP14]]
+; CHECK-NEXT:    [[NEXT_GEP4:%.*]] = getelementptr i8, ptr null, i64 [[TMP17]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[NEXT_GEP]], i64 -1
 ; CHECK-NEXT:    [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[TMP3]], i32 0
 ; CHECK-NEXT:    [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[TMP4]], i32 -3
@@ -43,8 +50,6 @@ define void @a(ptr readnone %b) {
 ; CHECK-NEXT:    [[TMP10:%.*]] = extractelement <4 x i1> [[TMP7]], i32 1
 ; CHECK-NEXT:    br i1 [[TMP10]], label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6:%.*]]
 ; CHECK:       pred.store.if5:
-; CHECK-NEXT:    [[TMP11:%.*]] = add i64 [[OFFSET_IDX]], -1
-; CHECK-NEXT:    [[NEXT_GEP2:%.*]] = getelementptr i8, ptr null, i64 [[TMP11]]
 ; CHECK-NEXT:    [[TMP12:%.*]] = getelementptr inbounds i8, ptr [[NEXT_GEP2]], i64 -1
 ; CHECK-NEXT:    store i8 95, ptr [[TMP12]], align 1
 ; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE6]]
@@ -52,8 +57,6 @@ define void @a(ptr readnone %b) {
 ; CHECK-NEXT:    [[TMP13:%.*]] = extractelement <4 x i1> [[TMP7]], i32 2
 ; CHECK-NEXT:    br i1 [[TMP13]], label [[PRED_STORE_IF7:%.*]], label [[PRED_STORE_CONTINUE8:%.*]]
 ; CHECK:       pred.store.if7:
-; CHECK-NEXT:    [[TMP14:%.*]] = add i64 [[OFFSET_IDX]], -2
-; CHECK-NEXT:    [[NEXT_GEP3:%.*]] = getelementptr i8, ptr null, i64 [[TMP14]]
 ; CHECK-NEXT:    [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[NEXT_GEP3]], i64 -1
 ; CHECK-NEXT:    store i8 95, ptr [[TMP15]], align 1
 ; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE8]]
@@ -61,8 +64,6 @@ define void @a(ptr readnone %b) {
 ; CHECK-NEXT:    [[TMP16:%.*]] = extractelement <4 x i1> [[TMP7]], i32 3
 ; CHECK-NEXT:    br i1 [[TMP16]], label [[PRED_STORE_IF9:%.*]], label [[PRED_STORE_CONTINUE10]]
 ; CHECK:       pred.store.if9:
-; CHECK-NEXT:    [[TMP17:%.*]] = add i64 [[OFFSET_IDX]], -3
-; CHECK-NEXT:    [[NEXT_GEP4:%.*]] = getelementptr i8, ptr null, i64 [[TMP17]]
 ; CHECK-NEXT:    [[TMP18:%.*]] = getelementptr inbounds i8, ptr [[NEXT_GEP4]], i64 -1
 ; CHECK-NEXT:    store i8 95, ptr [[TMP18]], align 1
 ; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE10]]
diff --git a/llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll b/llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
index caa5969bbc365..13d5be1b94d15 100644
--- a/llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
+++ b/llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
@@ -82,6 +82,8 @@ for.body:
   br i1 %exitcond, label %for.cond.cleanup, label %for.body
 }
 
+; Note: Most scalar pointer induction GEPs could be sunk into the conditional
+;       blocks.
 define void @VF1-VPWidenCanonicalIVRecipeExe(ptr %ptr1) {
 ; CHECK-LABEL: @VF1-VPWidenCanonicalIVRecipeExe(
 ; CHECK-NEXT:  entry:
@@ -92,6 +94,13 @@ define void @VF1-VPWidenCanonicalIVRecipeExe(ptr %ptr1) {
 ; CHECK:       vector.body:
 ; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE12:%.*]] ]
 ; CHECK-NEXT:    [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 8
+; CHECK-NEXT:    [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 8
+; CHECK-NEXT:    [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 16
+; CHECK-NEXT:    [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 24
+; CHECK-NEXT:    [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[PTR1]], i64 [[OFFSET_IDX]]
+; CHECK-NEXT:    [[NEXT_GEP1:%.*]] = getelementptr i8, ptr [[PTR1]], i64 [[TMP4]]
+; CHECK-NEXT:    [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[PTR1]], i64 [[TMP5]]
+; CHECK-NEXT:    [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[PTR1]], i64 [[TMP6]]
 ; CHECK-NEXT:    [[VEC_IV:%.*]] = add i64 [[INDEX]], 0
 ; CHECK-NEXT:    [[VEC_IV4:%.*]] = add i64 [[INDEX]], 1
 ; CHECK-NEXT:    [[VEC_IV5:%.*]] = add i64 [[INDEX]], 2
@@ -102,28 +111,21 @@ define void @VF1-VPWidenCanonicalIVRecipeExe(ptr %ptr1) {
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp ule i64 [[VEC_IV6]], 14
 ; CHECK-NEXT:    br i1 [[TMP0]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]
 ; CHECK:       pred.store.if:
-; CHECK-NEXT:    [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[PTR1]], i64 [[OFFSET_IDX]]
 ; CHECK-NEXT:    store double 0.000000e+00, ptr [[NEXT_GEP]], align 8
 ; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE]]
 ; CHECK:       pred.store.continue:
 ; CHECK-NEXT:    br i1 [[TMP1]], label [[PRED_STORE_IF7:%.*]], label [[PRED_STORE_CONTINUE8:%.*]]
 ; CHECK:       pred.store.if7:
-; CHECK-NEXT:    [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 8
-; CHECK-NEXT:    [[NEXT_GEP1:%.*]] = getelementptr i8, ptr [[PTR1]], i64 [[TMP5]]
 ; CHECK-NEXT:    store double 0.000000e+00, ptr [[NEXT_GEP1]], align 8
 ; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE8]]
 ; CHECK:       pred.store.continue8:
 ; CHECK-NEXT:    br i1 [[TMP2]], label [[PRED_STORE_IF9:%.*]], label [[PRED_STORE_CONTINUE10:%.*]]
 ; CHECK:       pred.store.if9:
-; CHECK-NEXT:    [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 16
-; CHECK-NEXT:    [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[PTR1]], i64 [[TMP6]]
 ; CHECK-NEXT:    store double 0.000000e+00, ptr [[NEXT_GEP2]], align 8
 ; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE10]]
 ; CHECK:       pred.store.continue10:
 ; CHECK-NEXT:    br i1 [[TMP3]], label [[PRED_STORE_IF11:%.*]], label [[PRED_STORE_CONTINUE12]]
 ; CHECK:       pred.store.if11:
-; CHECK-NEXT:    [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 24
-; CHECK-NEXT:    [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[PTR1]], i64 [[TMP7]]
 ; CHECK-NEXT:    store double 0.000000e+00, ptr [[NEXT_GEP3]], align 8
 ; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE12]]
 ; CHECK:       pred.store.continue12:
diff --git a/llvm/test/Transforms/PGOProfile/memprof-dump-matched-alloc-site.ll b/llvm/test/Transforms/PGOProfile/memprof-dump-matched-alloc-site.ll
new file mode 100644
index 0000000000000..b9126ac9a457f
--- /dev/null
+++ b/llvm/test/Transforms/PGOProfile/memprof-dump-matched-alloc-site.ll
@@ -0,0 +1,78 @@
+; Tests that the compiler dumps an allocation site with multiple inlined frames.
+;
+; The test case is generated from:
+;
+; // main
+; // |
+; // f1 (noinline)
+; // |
+; // f2
+; // |
+; // f3
+; // |
+; // new
+;
+; char *f1() { return new char[3]; }
+; char *f2() { return f1(); }
+; __attribute__((noinline)) char *f3() { return f2(); }
+;
+; int main() {
+;   f3();
+;   return 0;
+; }
+;
+; Here we expect to match the allocation site to encompass 3 frames.
+
+; REQUIRES: x86_64-linux
+; RUN: split-file %s %t
+; RUN: llvm-profdata merge %t/memprof-dump-matched-alloc-site.yaml -o %t/memprof-dump-matched-alloc-site.memprofdata
+; RUN: opt < %t/memprof-dump-matched-alloc-site.ll -passes='memprof-use<profile-filename=%t/memprof-dump-matched-alloc-site.memprofdata>' -memprof-print-match-info -S 2>&1 | FileCheck %s
+
+;--- memprof-dump-matched-alloc-site.yaml
+---
+HeapProfileRecords:
+  - GUID:            _Z2f3v
+    AllocSites:
+      - Callstack:
+          - { Function: _ZL2f1v, LineOffset: 0, Column: 35, IsInlineFrame: true }
+          - { Function: _ZL2f2v, LineOffset: 0, Column: 35, IsInlineFrame: true }
+          - { Function: _Z2f3v, LineOffset: 0, Column: 47, IsInlineFrame: false }
+          - { Function: main, LineOffset: 1, Column: 3, IsInlineFrame: false }
+        MemInfoBlock:
+          AllocCount:      1
+          TotalSize:       3
+          TotalLifetime:   0
+          TotalLifetimeAccessDensity: 0
+    CallSites:
+      # Kept empty here because this section is irrelevant for this test.
+...
+;--- memprof-dump-matched-alloc-site.ll
+; CHECK: MemProf notcold context with id 12978026349401156968 has total profiled size 3 is matched with 3 frames
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define ptr @_Z2f3v() {
+entry:
+  %call.i.i = call ptr @_Znam(i64 0), !dbg !3
+  ret ptr null
+}
+
+declare ptr @_Znam(i64)
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!2}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1)
+!1 = !DIFile(filename: "memprof-dump-matched-alloc-site.cc", directory: "/")
+!2 = !{i32 2, !"Debug Info Version", i32 3}
+!3 = !DILocation(line: 1, column: 35, scope: !4, inlinedAt: !7)
+!4 = distinct !DISubprogram(name: "f1", linkageName: "_ZL2f1v", scope: !1, file: !1, line: 1, type: !5, scopeLine: 1, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagLocalToUnit | DISPFlagDefinition | DISPFlagOptimized, unit: !0)
+!5 = !DISubroutineType(types: !6)
+!6 = !{}
+!7 = distinct !DILocation(line: 2, column: 35, scope: !8, inlinedAt: !9)
+!8 = distinct !DISubprogram(name: "f2", linkageName: "_ZL2f2v", scope: !1, file: !1, line: 2, type: !5, scopeLine: 2, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagLocalToUnit | DISPFlagDefinition | DISPFlagOptimized, unit: !0)
+!9 = distinct !DILocation(line: 3, column: 47, scope: !10)
+!10 = distinct !DISubprogram(name: "f3", linkageName: "_Z2f3v", scope: !1, file: !1, line: 3, type: !5, scopeLine: 3, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0)
+!11 = !DILocation(line: 6, column: 3, scope: !12)
+!12 = distinct !DISubprogram(name: "main", scope: !1, file: !1, line: 5, type: !5, scopeLine: 5, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0)
diff --git a/llvm/test/Transforms/PGOProfile/memprof-dump-matched-call-sites.ll b/llvm/test/Transforms/PGOProfile/memprof-dump-matched-call-sites.ll
index 6fe0e5cd497ec..fa99116b820f9 100644
--- a/llvm/test/Transforms/PGOProfile/memprof-dump-matched-call-sites.ll
+++ b/llvm/test/Transforms/PGOProfile/memprof-dump-matched-call-sites.ll
@@ -71,7 +71,7 @@ HeapProfileRecords:
     CallSites:       []
 ...
 ;--- memprof-dump-matched-call-site.ll
-; CHECK: MemProf notcold context with id 3894143216621363392 has total profiled size 4 is matched
+; CHECK: MemProf notcold context with id 3894143216621363392 has total profiled size 4 is matched with 1 frames
 ; CHECK: MemProf callsite match for inline call stack 4745611964195289084 10616861955219347331
 ; CHECK: MemProf callsite match for inline call stack 5401059281181789382
 
diff --git a/llvm/test/Transforms/PGOProfile/memprof.ll b/llvm/test/Transforms/PGOProfile/memprof.ll
index 5a958de5f7f8d..73226df861ea5 100644
--- a/llvm/test/Transforms/PGOProfile/memprof.ll
+++ b/llvm/test/Transforms/PGOProfile/memprof.ll
@@ -93,14 +93,14 @@
 ;; notcold again.
 ; RUN: opt < %s -passes='memprof-use<profile-filename=%t.memprofdata>' -pgo-warn-missing-function -S -memprof-min-ave-lifetime-access-density-hot-threshold=0 2>&1 | FileCheck %s --check-prefixes=MEMPROF,ALL
 
-; MEMPROFMATCHINFO: MemProf notcold context with id 1093248920606587996 has total profiled size 10 is matched
-; MEMPROFMATCHINFO: MemProf notcold context with id 5725971306423925017 has total profiled size 10 is matched
-; MEMPROFMATCHINFO: MemProf notcold context with id 6792096022461663180 has total profiled size 10 is matched
-; MEMPROFMATCHINFO: MemProf cold context with id 8525406123785421946 has total profiled size 10 is matched
-; MEMPROFMATCHINFO: MemProf cold context with id 11714230664165068698 has total profiled size 10 is matched
-; MEMPROFMATCHINFO: MemProf cold context with id 15737101490731057601 has total profiled size 10 is matched
-; MEMPROFMATCHINFO: MemProf cold context with id 16342802530253093571 has total profiled size 10 is matched
-; MEMPROFMATCHINFO: MemProf cold context with id 18254812774972004394 has total profiled size 10 is matched
+; MEMPROFMATCHINFO: MemProf notcold context with id 1093248920606587996 has total profiled size 10 is matched with 1 frames
+; MEMPROFMATCHINFO: MemProf notcold context with id 5725971306423925017 has total profiled size 10 is matched with 1 frames
+; MEMPROFMATCHINFO: MemProf notcold context with id 6792096022461663180 has total profiled size 10 is matched with 1 frames
+; MEMPROFMATCHINFO: MemProf cold context with id 8525406123785421946 has total profiled size 10 is matched with 1 frames
+; MEMPROFMATCHINFO: MemProf cold context with id 11714230664165068698 has total profiled size 10 is matched with 1 frames
+; MEMPROFMATCHINFO: MemProf cold context with id 15737101490731057601 has total profiled size 10 is matched with 1 frames
+; MEMPROFMATCHINFO: MemProf cold context with id 16342802530253093571 has total profiled size 10 is matched with 1 frames
+; MEMPROFMATCHINFO: MemProf cold context with id 18254812774972004394 has total profiled size 10 is matched with 1 frames
 ; MEMPROFMATCHINFO: MemProf callsite match for inline call stack 748269490701775343
 ; MEMPROFMATCHINFO: MemProf callsite match for inline call stack 1544787832369987002
 ; MEMPROFMATCHINFO: MemProf callsite match for inline call stack 2061451396820446691
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/blendv-select.ll b/llvm/test/Transforms/PhaseOrdering/X86/blendv-select.ll
index 444e256f9854b..22e4239009dd2 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/blendv-select.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/blendv-select.ll
@@ -473,6 +473,65 @@ define <8 x i64> @x86_pblendvb_v64i8_v32i8(<8 x i64> %a, <8 x i64> %b, <8 x i64>
   ret <8 x i64> %res
 }
 
+define <2 x i64> @PR66513(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i64> %src) {
+; CHECK-LABEL: @PR66513(
+; CHECK-NEXT:    [[I:%.*]] = bitcast <2 x i64> [[A:%.*]] to <4 x i32>
+; CHECK-NEXT:    [[CMP_I23:%.*]] = icmp sgt <4 x i32> [[I]], zeroinitializer
+; CHECK-NEXT:    [[SEXT_I24:%.*]] = sext <4 x i1> [[CMP_I23]] to <4 x i32>
+; CHECK-NEXT:    [[I1:%.*]] = bitcast <4 x i32> [[SEXT_I24]] to <2 x i64>
+; CHECK-NEXT:    [[I2:%.*]] = bitcast <2 x i64> [[B:%.*]] to <4 x i32>
+; CHECK-NEXT:    [[CMP_I21:%.*]] = icmp sgt <4 x i32> [[I2]], zeroinitializer
+; CHECK-NEXT:    [[SEXT_I22:%.*]] = sext <4 x i1> [[CMP_I21]] to <4 x i32>
+; CHECK-NEXT:    [[I3:%.*]] = bitcast <4 x i32> [[SEXT_I22]] to <2 x i64>
+; CHECK-NEXT:    [[I4:%.*]] = bitcast <2 x i64> [[C:%.*]] to <4 x i32>
+; CHECK-NEXT:    [[CMP_I:%.*]] = icmp sgt <4 x i32> [[I4]], zeroinitializer
+; CHECK-NEXT:    [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i32>
+; CHECK-NEXT:    [[I5:%.*]] = bitcast <4 x i32> [[SEXT_I]] to <2 x i64>
+; CHECK-NEXT:    [[AND_I27:%.*]] = and <2 x i64> [[I3]], [[I1]]
+; CHECK-NEXT:    [[XOR_I:%.*]] = xor <2 x i64> [[AND_I27]], [[I5]]
+; CHECK-NEXT:    [[AND_I26:%.*]] = and <2 x i64> [[XOR_I]], [[I1]]
+; CHECK-NEXT:    [[AND_I25:%.*]] = and <2 x i64> [[XOR_I]], [[I3]]
+; CHECK-NEXT:    [[AND_I:%.*]] = and <2 x i64> [[AND_I27]], [[SRC:%.*]]
+; CHECK-NEXT:    [[I6:%.*]] = bitcast <2 x i64> [[AND_I]] to <16 x i8>
+; CHECK-NEXT:    [[I7:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
+; CHECK-NEXT:    [[I8:%.*]] = bitcast <2 x i64> [[AND_I26]] to <16 x i8>
+; CHECK-NEXT:    [[I9:%.*]] = tail call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> [[I6]], <16 x i8> [[I7]], <16 x i8> [[I8]])
+; CHECK-NEXT:    [[I12:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>
+; CHECK-NEXT:    [[I13:%.*]] = bitcast <2 x i64> [[AND_I25]] to <16 x i8>
+; CHECK-NEXT:    [[I14:%.*]] = tail call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> [[I9]], <16 x i8> [[I12]], <16 x i8> [[I13]])
+; CHECK-NEXT:    [[I15:%.*]] = bitcast <16 x i8> [[I14]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[I15]]
+;
+  %i = bitcast <2 x i64> %a to <4 x i32>
+  %cmp.i23 = icmp sgt <4 x i32> %i, zeroinitializer
+  %sext.i24 = sext <4 x i1> %cmp.i23 to <4 x i32>
+  %i1 = bitcast <4 x i32> %sext.i24 to <2 x i64>
+  %i2 = bitcast <2 x i64> %b to <4 x i32>
+  %cmp.i21 = icmp sgt <4 x i32> %i2, zeroinitializer
+  %sext.i22 = sext <4 x i1> %cmp.i21 to <4 x i32>
+  %i3 = bitcast <4 x i32> %sext.i22 to <2 x i64>
+  %i4 = bitcast <2 x i64> %c to <4 x i32>
+  %cmp.i = icmp sgt <4 x i32> %i4, zeroinitializer
+  %sext.i = sext <4 x i1> %cmp.i to <4 x i32>
+  %i5 = bitcast <4 x i32> %sext.i to <2 x i64>
+  %and.i27 = and <2 x i64> %i1, %i3
+  %xor.i = xor <2 x i64> %and.i27, %i5
+  %and.i26 = and <2 x i64> %xor.i, %i1
+  %and.i25 = and <2 x i64> %xor.i, %i3
+  %and.i = and <2 x i64> %src, %and.i27
+  %i6 = bitcast <2 x i64> %and.i to <16 x i8>
+  %i7 = bitcast <2 x i64> %a to <16 x i8>
+  %i8 = bitcast <2 x i64> %and.i26 to <16 x i8>
+  %i9 = call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> %i6, <16 x i8> %i7, <16 x i8> %i8)
+  %i10 = bitcast <16 x i8> %i9 to <2 x i64>
+  %i11 = bitcast <2 x i64> %i10 to <16 x i8>
+  %i12 = bitcast <2 x i64> %b to <16 x i8>
+  %i13 = bitcast <2 x i64> %and.i25 to <16 x i8>
+  %i14 = call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> %i11, <16 x i8> %i12, <16 x i8> %i13)
+  %i15 = bitcast <16 x i8> %i14 to <2 x i64>
+  ret <2 x i64> %i15
+}
+
 ;
 ; Negative Tests
 ;
diff --git a/llvm/test/Transforms/Reassociate/canonicalize-made-change.ll b/llvm/test/Transforms/Reassociate/canonicalize-made-change.ll
new file mode 100644
index 0000000000000..64f1ede9a9ac4
--- /dev/null
+++ b/llvm/test/Transforms/Reassociate/canonicalize-made-change.ll
@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -passes="print<demanded-bits>,reassociate,bdce" -S < %s | FileCheck %s
+
+; We want to verify that demanded-bits analysis is invalidated when
+; reassociate is canonicalizing expressions (e.g. putting the constant on the
+; RHS of an OR).
+;
+; Printing demanded-bits will make sure a demanded-bits analysis is cached.
+; Then we run reassociate, followed by bdce. When not invalidating demanded-bits
+; while doing reassociation of the OR, we got this kind of error:
+;
+;   Running pass: BDCEPass on foo (4 instructions)
+;   While deleting: i1 %cmp1
+;   Use still stuck around after Def is destroyed:  %or = or i1 %cmp1, true
+;   UNREACHABLE executed at ../lib/IR/Value.cpp:102!
+;
+; Check that we get the expected result without failing on assert/unreachable.
+
+define i1 @foo(i1 %c) {
+; CHECK-LABEL: define i1 @foo(
+; CHECK-SAME: i1 [[C:%.*]]) {
+; CHECK-NEXT:  [[ENTRY:.*:]]
+; CHECK-NEXT:    [[OR:%.*]] = or i1 false, true
+; CHECK-NEXT:    [[AND:%.*]] = and i1 [[OR]], [[C]]
+; CHECK-NEXT:    ret i1 [[AND]]
+;
+entry:
+  %cmp = icmp ne i16 0, 1
+  %or = or i1 true, %cmp
+  %and = and i1 %c, %or
+  ret i1 %and
+}
diff --git a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll
index 422e5d8215502..2a5b678e91fd8 100644
--- a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll
+++ b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/preserve-inbounds.ll
@@ -1,5 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -passes=separate-const-offset-from-gep -S | FileCheck %s
+; RUN: opt < %s -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -passes=separate-const-offset-from-gep -S | FileCheck %s
+
+; gfx1200 is particularly interesting since it allows negative immediate offsets
+; in flat instructions, so the transformation is applied in more cases.
 
 ; The inbounds flags cannot be preserved here: If the pointers point to the
 ; beginning of an object and %i is 1, the intermediate GEPs are out of bounds.
@@ -16,3 +19,524 @@ entry:
   %arrayidx = getelementptr inbounds i32, ptr %p, i64 %idx
   ret ptr %arrayidx
 }
+
+; All indices must be non-negative, so inbounds can be preserved.
+define ptr @must_be_inbounds(ptr %p, i32 %i) {
+; CHECK-LABEL: @must_be_inbounds(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[I_PROM:%.*]] = zext i32 [[I:%.*]] to i64
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[P:%.*]], i64 [[I_PROM]]
+; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 4
+; CHECK-NEXT:    ret ptr [[ARRAYIDX2]]
+;
+entry:
+  %i.prom = zext i32 %i to i64
+  %idx = add nsw i64 %i.prom, 1
+  %arrayidx = getelementptr inbounds i32, ptr %p, i64 %idx
+  ret ptr %arrayidx
+}
+
+; idx must be non-negative -> preserve inbounds
+define ptr @sign_bit_clear(ptr %p, i64 %i) {
+; CHECK-LABEL: @sign_bit_clear(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[IDX:%.*]] = and i64 [[I:%.*]], 9223372036854775807
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[P:%.*]], i64 [[IDX]]
+; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 4
+; CHECK-NEXT:    ret ptr [[ARRAYIDX]]
+;
+entry:
+  %idx = and i64 %i, u0x7fffffffffffffff
+  %idx.add = add i64 %idx, 1
+  %arrayidx = getelementptr inbounds i32, ptr %p, i64 %idx.add
+  ret ptr %arrayidx
+}
+
+; idx may be negative -> don't preserve inbounds
+define ptr @sign_bit_not_clear(ptr %p, i64 %i) {
+; CHECK-LABEL: @sign_bit_not_clear(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[IDX:%.*]] = and i64 [[I:%.*]], -256
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr i32, ptr [[P:%.*]], i64 [[IDX]]
+; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr i8, ptr [[TMP0]], i64 4
+; CHECK-NEXT:    ret ptr [[ARRAYIDX2]]
+;
+entry:
+  %idx = and i64 %i, u0xffffffffffffff00
+  %idx.add = add i64 %idx, 1
+  %arrayidx = getelementptr inbounds i32, ptr %p, i64 %idx.add
+  ret ptr %arrayidx
+}
+
+; idx may be 0 or very negative -> don't preserve inbounds
+define ptr @only_sign_bit_not_clear(ptr %p, i64 %i) {
+; CHECK-LABEL: @only_sign_bit_not_clear(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[IDX:%.*]] = and i64 [[I:%.*]], -9223372036854775808
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr i32, ptr [[P:%.*]], i64 [[IDX]]
+; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr i8, ptr [[TMP0]], i64 4
+; CHECK-NEXT:    ret ptr [[ARRAYIDX2]]
+;
+entry:
+  %idx = and i64 %i, u0x8000000000000000
+  %idx.add = add i64 %idx, 1
+  %arrayidx = getelementptr inbounds i32, ptr %p, i64 %idx.add
+  ret ptr %arrayidx
+}
+
+; all indices non-negative -> preserve inbounds
+define ptr @multi_level_nonnegative(ptr %p, i64 %idx1, i64 %idx2) {
+; CHECK-LABEL: @multi_level_nonnegative(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[MASKED_IDX1:%.*]] = and i64 [[IDX1:%.*]], 255
+; CHECK-NEXT:    [[MASKED_IDX2:%.*]] = and i64 [[IDX2:%.*]], 65535
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [10 x [20 x i32]], ptr [[P:%.*]], i64 0, i64 [[MASKED_IDX1]], i64 [[MASKED_IDX2]]
+; CHECK-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 180
+; CHECK-NEXT:    ret ptr [[ARRAYIDX3]]
+;
+entry:
+  %masked.idx1 = and i64 %idx1, u0xff
+  %masked.idx2 = and i64 %idx2, u0xffff
+  %idx1.add = add i64 %masked.idx1, 2
+  %idx2.add = add i64 %masked.idx2, 5
+  %arrayidx = getelementptr inbounds [10 x [20 x i32]], ptr %p, i64 0, i64 %idx1.add, i64 %idx2.add
+  ret ptr %arrayidx
+}
+
+; It doesn't matter that %idx2.add might be negative, the indices in the resulting GEPs are all non-negative -> preserve inbounds
+define ptr @multi_level_mixed_okay(ptr %p, i64 %idx1, i64 %idx2) {
+; CHECK-LABEL: @multi_level_mixed_okay(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[MASKED_IDX1:%.*]] = and i64 [[IDX1:%.*]], 255
+; CHECK-NEXT:    [[MASKED_IDX2:%.*]] = and i64 [[IDX2:%.*]], 65535
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [10 x [20 x i32]], ptr [[P:%.*]], i64 0, i64 [[MASKED_IDX1]], i64 [[MASKED_IDX2]]
+; CHECK-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 156
+; CHECK-NEXT:    ret ptr [[ARRAYIDX3]]
+;
+entry:
+  %masked.idx1 = and i64 %idx1, u0xff
+  %masked.idx2 = and i64 %idx2, u0xffff
+  %idx1.add = add i64 %masked.idx1, 2
+  %idx2.add = add i64 %masked.idx2, -1
+  %arrayidx = getelementptr inbounds [10 x [20 x i32]], ptr %p, i64 0, i64 %idx1.add, i64 %idx2.add
+  ret ptr %arrayidx
+}
+
+; One index may be negative -> don't preserve inbounds
+define ptr @multi_level_mixed_not_okay(ptr %p, i64 %idx1, i64 %idx2) {
+; CHECK-LABEL: @multi_level_mixed_not_okay(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[MASKED_IDX1:%.*]] = and i64 [[IDX1:%.*]], -256
+; CHECK-NEXT:    [[MASKED_IDX2:%.*]] = and i64 [[IDX2:%.*]], 65535
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr [10 x [20 x i32]], ptr [[P:%.*]], i64 0, i64 [[MASKED_IDX1]], i64 [[MASKED_IDX2]]
+; CHECK-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 156
+; CHECK-NEXT:    ret ptr [[ARRAYIDX3]]
+;
+entry:
+  %masked.idx1 = and i64 %idx1, u0xffffffffffffff00
+  %masked.idx2 = and i64 %idx2, u0xffff
+  %idx1.add = add i64 %masked.idx1, 2
+  %idx2.add = add i64 %masked.idx2, -1
+  %arrayidx = getelementptr inbounds [10 x [20 x i32]], ptr %p, i64 0, i64 %idx1.add, i64 %idx2.add
+  ret ptr %arrayidx
+}
+
+
+define ptr @nuw_implies_nuw(ptr %p, i64 %i) {
+; CHECK-LABEL: @nuw_implies_nuw(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr nuw i32, ptr [[P:%.*]], i64 [[I:%.*]]
+; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr nuw i8, ptr [[TMP0]], i64 4
+; CHECK-NEXT:    ret ptr [[ARRAYIDX2]]
+;
+entry:
+  %idx = add nuw i64 %i, 1
+  %arrayidx = getelementptr nuw i32, ptr %p, i64 %idx
+  ret ptr %arrayidx
+}
+
+define ptr @nuw_implies_nuw_negative(ptr %p, i64 %i) {
+; CHECK-LABEL: @nuw_implies_nuw_negative(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr nuw i32, ptr [[P:%.*]], i64 [[I:%.*]]
+; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr nuw i8, ptr [[TMP0]], i64 -64
+; CHECK-NEXT:    ret ptr [[ARRAYIDX2]]
+;
+entry:
+  %idx = add nuw i64 %i, -16
+  %arrayidx = getelementptr nuw i32, ptr %p, i64 %idx
+  ret ptr %arrayidx
+}
+
+define ptr @nuw_inbounds_implies_nuw_inbounds(ptr %p, i64 %i) {
+; CHECK-LABEL: @nuw_inbounds_implies_nuw_inbounds(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw i32, ptr [[P:%.*]], i64 [[I:%.*]]
+; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 4
+; CHECK-NEXT:    ret ptr [[ARRAYIDX2]]
+;
+entry:
+  %idx = add nuw i64 %i, 1
+  %arrayidx = getelementptr inbounds nuw i32, ptr %p, i64 %idx
+  ret ptr %arrayidx
+}
+
+; This is poison anyway, so we can preserve the flags.
+define ptr @nuw_inbounds_implies_nuw_inbounds_negative(ptr %p, i64 %i) {
+; CHECK-LABEL: @nuw_inbounds_implies_nuw_inbounds_negative(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw i32, ptr [[P:%.*]], i64 [[I:%.*]]
+; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 -64
+; CHECK-NEXT:    ret ptr [[ARRAYIDX2]]
+;
+entry:
+  %idx = add nuw i64 %i, -16
+  %arrayidx = getelementptr inbounds nuw i32, ptr %p, i64 %idx
+  ret ptr %arrayidx
+}
+
+define ptr @nuw_nusw_implies_nuw_nusw(ptr %p, i64 %i) {
+; CHECK-LABEL: @nuw_nusw_implies_nuw_nusw(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr nusw nuw i32, ptr [[P:%.*]], i64 [[I:%.*]]
+; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr nusw nuw i8, ptr [[TMP0]], i64 4
+; CHECK-NEXT:    ret ptr [[ARRAYIDX2]]
+;
+entry:
+  %idx = add nuw i64 %i, 1
+  %arrayidx = getelementptr nusw nuw i32, ptr %p, i64 %idx
+  ret ptr %arrayidx
+}
+
+; Also poison.
+define ptr @nuw_implies_nuw_nusw_negative(ptr %p, i64 %i) {
+; CHECK-LABEL: @nuw_implies_nuw_nusw_negative(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr nusw nuw i32, ptr [[P:%.*]], i64 [[I:%.*]]
+; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr nusw nuw i8, ptr [[TMP0]], i64 -64
+; CHECK-NEXT:    ret ptr [[ARRAYIDX2]]
+;
+entry:
+  %idx = add nuw i64 %i, -16
+  %arrayidx = getelementptr nusw nuw i32, ptr %p, i64 %idx
+  ret ptr %arrayidx
+}
+
+
+define ptr @nuw_inbounds_implies_nuw_inbounds_ordisjoint(ptr %p, i64 %i) {
+; CHECK-LABEL: @nuw_inbounds_implies_nuw_inbounds_ordisjoint(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw i32, ptr [[P:%.*]], i64 [[I:%.*]]
+; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 4
+; CHECK-NEXT:    ret ptr [[ARRAYIDX2]]
+;
+entry:
+  %idx = or disjoint i64 %i, 1
+  %arrayidx = getelementptr inbounds nuw i32, ptr %p, i64 %idx
+  ret ptr %arrayidx
+}
+
+; This is poison anyway, so we can do the transformation.
+define ptr @nuw_inbounds_implies_nuw_inbounds_ordisjoint_negative(ptr %p, i64 %i) {
+; CHECK-LABEL: @nuw_inbounds_implies_nuw_inbounds_ordisjoint_negative(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw i32, ptr [[P:%.*]], i64 [[I:%.*]]
+; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 -64
+; CHECK-NEXT:    ret ptr [[ARRAYIDX2]]
+;
+entry:
+  %idx = or disjoint i64 %i, -16
+  %arrayidx = getelementptr inbounds nuw i32, ptr %p, i64 %idx
+  ret ptr %arrayidx
+}
+
+; Check that nothing happens for non-disjoint ors
+define ptr @or_no_disjoint(ptr %p, i64 %i) {
+; CHECK-LABEL: @or_no_disjoint(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[IDX:%.*]] = or i64 [[I:%.*]], 1
+; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds nuw i32, ptr [[P:%.*]], i64 [[IDX]]
+; CHECK-NEXT:    ret ptr [[ARRAYIDX]]
+;
+entry:
+  %idx = or i64 %i, 1
+  %arrayidx = getelementptr inbounds nuw i32, ptr %p, i64 %idx
+  ret ptr %arrayidx
+}
+
+define ptr @no_nuw_inbounds_for_sub(ptr %p, i64 %i) {
+; CHECK-LABEL: @no_nuw_inbounds_for_sub(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr i32, ptr [[P:%.*]], i64 [[I:%.*]]
+; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr i8, ptr [[TMP0]], i64 -4
+; CHECK-NEXT:    ret ptr [[ARRAYIDX2]]
+;
+entry:
+  %idx = sub nuw i64 %i, 1
+  %arrayidx = getelementptr inbounds nuw i32, ptr %p, i64 %idx
+  ret ptr %arrayidx
+}
+
+define ptr @no_nuw_inbounds_for_sub_negative(ptr %p, i64 %i) {
+; CHECK-LABEL: @no_nuw_inbounds_for_sub_negative(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr i32, ptr [[P:%.*]], i64 [[I:%.*]]
+; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr i8, ptr [[TMP0]], i64 64
+; CHECK-NEXT:    ret ptr [[ARRAYIDX2]]
+;
+entry:
+  %idx = sub nuw i64 %i, -16
+  %arrayidx = getelementptr inbounds nuw i32, ptr %p, i64 %idx
+  ret ptr %arrayidx
+}
+
+; Can't preserved nuw and other flags here as distributing the trunc towards the
+; leaves can introduce new wraps.
+define ptr @nuw_inbounds_trunc(ptr %p, i128 %i) {
+; CHECK-LABEL: @nuw_inbounds_trunc(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = trunc i128 [[I:%.*]] to i64
+; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr i32, ptr [[P:%.*]], i64 [[TMP0]]
+; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr i8, ptr [[TMP1]], i64 4
+; CHECK-NEXT:    ret ptr [[ARRAYIDX2]]
+;
+entry:
+  %idx = add nuw i128 %i, 1
+  %idx.conv = trunc i128 %idx to i64
+  %arrayidx = getelementptr inbounds nuw i32, ptr %p, i64 %idx.conv
+  ret ptr %arrayidx
+}
+
+; trunc nuw is not a problem.
+define ptr @nuw_inbounds_implies_nuw_inbounds_trunc_nuw(ptr %p, i128 %i) {
+; CHECK-LABEL: @nuw_inbounds_implies_nuw_inbounds_trunc_nuw(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = trunc nuw i128 [[I:%.*]] to i64
+; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw i32, ptr [[P:%.*]], i64 [[TMP0]]
+; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP1]], i64 4
+; CHECK-NEXT:    ret ptr [[ARRAYIDX2]]
+;
+entry:
+  %idx = add nuw i128 %i, 1
+  %idx.conv = trunc nuw i128 %idx to i64
+  %arrayidx = getelementptr inbounds nuw i32, ptr %p, i64 %idx.conv
+  ret ptr %arrayidx
+}
+
+define ptr @nuw_inbounds_implies_nuw_inbounds_sext(ptr %p, i32 %i) {
+; CHECK-LABEL: @nuw_inbounds_implies_nuw_inbounds_sext(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = sext i32 [[I:%.*]] to i64
+; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw i32, ptr [[P:%.*]], i64 [[TMP0]]
+; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP1]], i64 4
+; CHECK-NEXT:    ret ptr [[ARRAYIDX2]]
+;
+entry:
+  %idx = add nuw i32 %i, 1
+  %idx.conv = sext i32 %idx to i64
+  %arrayidx = getelementptr inbounds nuw i32, ptr %p, i64 %idx.conv
+  ret ptr %arrayidx
+}
+
+define ptr @nuw_inbounds_implies_nuw_inbounds_zext(ptr %p, i32 %i) {
+; CHECK-LABEL: @nuw_inbounds_implies_nuw_inbounds_zext(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = zext i32 [[I:%.*]] to i64
+; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw i32, ptr [[P:%.*]], i64 [[TMP0]]
+; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP1]], i64 4
+; CHECK-NEXT:    ret ptr [[ARRAYIDX2]]
+;
+entry:
+  %idx = add nuw i32 %i, 1
+  %idx.conv = zext i32 %idx to i64
+  %arrayidx = getelementptr inbounds nuw i32, ptr %p, i64 %idx.conv
+  ret ptr %arrayidx
+}
+
+define ptr @nuw_inbounds_implies_nuw_inbounds_zext_negative(ptr %p, i8 %i) {
+; CHECK-LABEL: @nuw_inbounds_implies_nuw_inbounds_zext_negative(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[IDX_CONV:%.*]] = zext i8 [[I:%.*]] to i64
+; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds nuw i32, ptr [[P:%.*]], i64 [[IDX_CONV]]
+; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw i8, ptr [[ARRAYIDX]], i64 960
+; CHECK-NEXT:    ret ptr [[ARRAYIDX2]]
+;
+entry:
+  %idx = add nuw i8 %i, -16
+  %idx.conv = zext i8 %idx to i64
+  %arrayidx = getelementptr inbounds nuw i32, ptr %p, i64 %idx.conv
+  ret ptr %arrayidx
+}
+
+
+; This test and the following ones mask most bits of %v off to facilitate
+; validation with alive2 while still allowing interesting values.
+define ptr @nuw_inbounds_implies_nuw_inbounds_nested(ptr %p, i64 %i, i64 %v) {
+; CHECK-LABEL: @nuw_inbounds_implies_nuw_inbounds_nested(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[V_MASKED:%.*]] = and i64 [[V:%.*]], -1152921488500719601
+; CHECK-NEXT:    [[IDX22:%.*]] = add i64 [[I:%.*]], [[V_MASKED]]
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw i32, ptr [[P:%.*]], i64 [[IDX22]]
+; CHECK-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 4
+; CHECK-NEXT:    ret ptr [[ARRAYIDX3]]
+;
+entry:
+  %v.masked = and i64 %v, u0xf0000003c000000f
+  %idx1 = add nuw i64 %i, 1
+  %idx2 = add nuw i64 %idx1, %v.masked
+  %arrayidx = getelementptr inbounds nuw i32, ptr %p, i64 %idx2
+  ret ptr %arrayidx
+}
+
+define ptr @nuw_inbounds_implies_nuw_inbounds_nested_negative(ptr %p, i64 %i, i64 %v) {
+; CHECK-LABEL: @nuw_inbounds_implies_nuw_inbounds_nested_negative(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[V:%.*]] = and i64 [[V1:%.*]], -1152921488500719601
+; CHECK-NEXT:    [[IDX22:%.*]] = add i64 [[I:%.*]], [[V]]
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw i32, ptr [[P:%.*]], i64 [[IDX22]]
+; CHECK-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 -64
+; CHECK-NEXT:    ret ptr [[ARRAYIDX3]]
+;
+entry:
+  %v.masked = and i64 %v, u0xf0000003c000000f
+  %idx1 = add nuw i64 %i, -16
+  %idx2 = add nuw i64 %idx1, %v.masked
+  %arrayidx = getelementptr inbounds nuw i32, ptr %p, i64 %idx2
+  ret ptr %arrayidx
+}
+
+define ptr @nuw_implies_nuw_nested(ptr %p, i64 %i, i64 %v) {
+; CHECK-LABEL: @nuw_implies_nuw_nested(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[V:%.*]] = and i64 [[V1:%.*]], -1152921488500719601
+; CHECK-NEXT:    [[IDX22:%.*]] = add i64 [[I:%.*]], [[V]]
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr nuw i32, ptr [[P:%.*]], i64 [[IDX22]]
+; CHECK-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr nuw i8, ptr [[TMP0]], i64 4
+; CHECK-NEXT:    ret ptr [[ARRAYIDX3]]
+;
+entry:
+  %v.masked = and i64 %v, u0xf0000003c000000f
+  %idx1 = add nuw i64 %i, 1
+  %idx2 = add nuw i64 %idx1, %v.masked
+  %arrayidx = getelementptr nuw i32, ptr %p, i64 %idx2
+  ret ptr %arrayidx
+}
+
+define ptr @nuw_implies_nuw_nested_negative(ptr %p, i64 %i, i64 %v) {
+; CHECK-LABEL: @nuw_implies_nuw_nested_negative(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[V:%.*]] = and i64 [[V1:%.*]], -1152921488500719601
+; CHECK-NEXT:    [[IDX22:%.*]] = add i64 [[I:%.*]], [[V]]
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr nuw i32, ptr [[P:%.*]], i64 [[IDX22]]
+; CHECK-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr nuw i8, ptr [[TMP0]], i64 -64
+; CHECK-NEXT:    ret ptr [[ARRAYIDX3]]
+;
+entry:
+  %v.masked = and i64 %v, u0xf0000003c000000f
+  %idx1 = add nuw i64 %i, -16
+  %idx2 = add nuw i64 %idx1, %v.masked
+  %arrayidx = getelementptr nuw i32, ptr %p, i64 %idx2
+  ret ptr %arrayidx
+}
+
+define ptr @nuw_nusw_implies_nuw_nusw_nested(ptr %p, i64 %i, i64 %v) {
+; CHECK-LABEL: @nuw_nusw_implies_nuw_nusw_nested(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[V:%.*]] = and i64 [[V1:%.*]], -1152921488500719601
+; CHECK-NEXT:    [[IDX22:%.*]] = add i64 [[I:%.*]], [[V]]
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr nusw nuw i32, ptr [[P:%.*]], i64 [[IDX22]]
+; CHECK-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr nusw nuw i8, ptr [[TMP0]], i64 4
+; CHECK-NEXT:    ret ptr [[ARRAYIDX3]]
+;
+entry:
+  %v.masked = and i64 %v, u0xf0000003c000000f
+  %idx1 = add nuw i64 %i, 1
+  %idx2 = add nuw i64 %idx1, %v.masked
+  %arrayidx = getelementptr nusw nuw i32, ptr %p, i64 %idx2
+  ret ptr %arrayidx
+}
+
+define ptr @nuw_nusw_implies_nuw_nusw_nested_negative(ptr %p, i64 %i, i64 %v) {
+; CHECK-LABEL: @nuw_nusw_implies_nuw_nusw_nested_negative(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[V:%.*]] = and i64 [[V1:%.*]], -1152921488500719601
+; CHECK-NEXT:    [[IDX22:%.*]] = add i64 [[I:%.*]], [[V]]
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr nusw nuw i32, ptr [[P:%.*]], i64 [[IDX22]]
+; CHECK-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr nusw nuw i8, ptr [[TMP0]], i64 -64
+; CHECK-NEXT:    ret ptr [[ARRAYIDX3]]
+;
+entry:
+  %v.masked = and i64 %v, u0xf0000003c000000f
+  %idx1 = add nuw i64 %i, -16
+  %idx2 = add nuw i64 %idx1, %v.masked
+  %arrayidx = getelementptr nusw nuw i32, ptr %p, i64 %idx2
+  ret ptr %arrayidx
+}
+
+
+; Neither inbounds nor nuw can be preserved.
+define ptr @nuw_inbounds_nested_not_all_nuw(ptr %p, i64 %i, i64 %v) {
+; CHECK-LABEL: @nuw_inbounds_nested_not_all_nuw(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[V:%.*]] = and i64 [[V1:%.*]], -1152921488500719601
+; CHECK-NEXT:    [[IDX22:%.*]] = add i64 [[I:%.*]], [[V]]
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr i32, ptr [[P:%.*]], i64 [[IDX22]]
+; CHECK-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr i8, ptr [[TMP0]], i64 4
+; CHECK-NEXT:    ret ptr [[ARRAYIDX3]]
+;
+entry:
+  %v.masked = and i64 %v, u0xf0000003c000000f
+  %idx1 = add nuw i64 %i, 1
+  %idx2 = add i64 %idx1, %v.masked
+  %arrayidx = getelementptr inbounds nuw i32, ptr %p, i64 %idx2
+  ret ptr %arrayidx
+}
+
+
+define ptr @nuw_inbounds_implies_nuw_inbounds_multilevel(ptr %src, i64 %i1, i64 %i2) {
+; CHECK-LABEL: @nuw_inbounds_implies_nuw_inbounds_multilevel(
+; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [4 x i32], ptr [[SRC:%.*]], i64 [[I1:%.*]], i64 [[I2:%.*]]
+; CHECK-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP1]], i64 24
+; CHECK-NEXT:    ret ptr [[ARRAYIDX3]]
+;
+  %idx1 = add nuw i64 %i1, 1
+  %idx2 = add nuw i64 2, %i2
+  %arrayidx = getelementptr inbounds nuw [4 x i32], ptr %src, i64 %idx1, i64 %idx2
+  ret ptr %arrayidx
+}
+
+; Neither inbounds nor nuw can be preserved.
+define ptr @nuw_inbounds_multilevel_not_all_nuw(ptr %src, i64 %i1, i64 %i2) {
+; CHECK-LABEL: @nuw_inbounds_multilevel_not_all_nuw(
+; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr [4 x i32], ptr [[SRC:%.*]], i64 [[I1:%.*]], i64 [[I2:%.*]]
+; CHECK-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr i8, ptr [[TMP1]], i64 24
+; CHECK-NEXT:    ret ptr [[ARRAYIDX3]]
+;
+  %idx1 = add nuw i64 %i1, 1
+  %idx2 = add i64 2, %i2
+  %arrayidx = getelementptr inbounds nuw [4 x i32], ptr %src, i64 %idx1, i64 %idx2
+  ret ptr %arrayidx
+}
+
+; Missing information about non-extracted indices does not matter.
+define ptr @nuw_inbounds_implies_nuw_inbounds_multilevel_one_unfolded(ptr %src, i64 %i1, i64 %v) {
+; CHECK-LABEL: @nuw_inbounds_implies_nuw_inbounds_multilevel_one_unfolded(
+; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [4 x i32], ptr [[SRC:%.*]], i64 [[I1:%.*]], i64 [[V:%.*]]
+; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP1]], i64 16
+; CHECK-NEXT:    ret ptr [[ARRAYIDX2]]
+;
+  %idx1 = add nuw i64 %i1, 1
+  %arrayidx = getelementptr inbounds nuw [4 x i32], ptr %src, i64 %idx1, i64 %v
+  ret ptr %arrayidx
+}
+
+define ptr @nuw_inbounds_implies_nuw_inbounds_multilevel_other_unfolded(ptr %src, i64 %i1, i64 %v) {
+; CHECK-LABEL: @nuw_inbounds_implies_nuw_inbounds_multilevel_other_unfolded(
+; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [4 x i32], ptr [[SRC:%.*]], i64 [[V:%.*]], i64 [[I1:%.*]]
+; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP1]], i64 4
+; CHECK-NEXT:    ret ptr [[ARRAYIDX2]]
+;
+  %idx1 = add nuw i64 %i1, 1
+  %arrayidx = getelementptr inbounds nuw [4 x i32], ptr %src, i64 %v, i64 %idx1
+  ret ptr %arrayidx
+}
diff --git a/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll b/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll
index 9a73feb2c4b5c..4474585bf9b06 100644
--- a/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll
+++ b/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll
@@ -157,19 +157,19 @@ define void @sum_of_array3(i32 %x, i32 %y, ptr nocapture %output) {
 ; IR-NEXT:  .preheader:
 ; IR-NEXT:    [[TMP0:%.*]] = zext i32 [[Y]] to i64
 ; IR-NEXT:    [[TMP1:%.*]] = zext i32 [[X]] to i64
-; IR-NEXT:    [[TMP2:%.*]] = getelementptr [32 x [32 x float]], ptr addrspace(3) @array, i64 0, i64 [[TMP1]], i64 [[TMP0]]
+; IR-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [32 x [32 x float]], ptr addrspace(3) @array, i64 0, i64 [[TMP1]], i64 [[TMP0]]
 ; IR-NEXT:    [[TMP3:%.*]] = addrspacecast ptr addrspace(3) [[TMP2]] to ptr
 ; IR-NEXT:    [[TMP4:%.*]] = load float, ptr [[TMP3]], align 4
 ; IR-NEXT:    [[TMP5:%.*]] = fadd float [[TMP4]], 0.000000e+00
-; IR-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP2]], i64 4
+; IR-NEXT:    [[TMP6:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i64 4
 ; IR-NEXT:    [[TMP7:%.*]] = addrspacecast ptr addrspace(3) [[TMP6]] to ptr
 ; IR-NEXT:    [[TMP8:%.*]] = load float, ptr [[TMP7]], align 4
 ; IR-NEXT:    [[TMP9:%.*]] = fadd float [[TMP5]], [[TMP8]]
-; IR-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP2]], i64 128
+; IR-NEXT:    [[TMP10:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i64 128
 ; IR-NEXT:    [[TMP11:%.*]] = addrspacecast ptr addrspace(3) [[TMP10]] to ptr
 ; IR-NEXT:    [[TMP12:%.*]] = load float, ptr [[TMP11]], align 4
 ; IR-NEXT:    [[TMP13:%.*]] = fadd float [[TMP9]], [[TMP12]]
-; IR-NEXT:    [[TMP14:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP2]], i64 132
+; IR-NEXT:    [[TMP14:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i64 132
 ; IR-NEXT:    [[TMP15:%.*]] = addrspacecast ptr addrspace(3) [[TMP14]] to ptr
 ; IR-NEXT:    [[TMP16:%.*]] = load float, ptr [[TMP15]], align 4
 ; IR-NEXT:    [[TMP17:%.*]] = fadd float [[TMP13]], [[TMP16]]
@@ -224,19 +224,19 @@ define void @sum_of_array4(i32 %x, i32 %y, ptr nocapture %output) {
 ; IR-NEXT:  .preheader:
 ; IR-NEXT:    [[TMP0:%.*]] = zext i32 [[Y]] to i64
 ; IR-NEXT:    [[TMP1:%.*]] = zext i32 [[X]] to i64
-; IR-NEXT:    [[TMP2:%.*]] = getelementptr [32 x [32 x float]], ptr addrspace(3) @array, i64 0, i64 [[TMP1]], i64 [[TMP0]]
+; IR-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [32 x [32 x float]], ptr addrspace(3) @array, i64 0, i64 [[TMP1]], i64 [[TMP0]]
 ; IR-NEXT:    [[TMP3:%.*]] = addrspacecast ptr addrspace(3) [[TMP2]] to ptr
 ; IR-NEXT:    [[TMP4:%.*]] = load float, ptr [[TMP3]], align 4
 ; IR-NEXT:    [[TMP5:%.*]] = fadd float [[TMP4]], 0.000000e+00
-; IR-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP2]], i64 4
+; IR-NEXT:    [[TMP6:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i64 4
 ; IR-NEXT:    [[TMP7:%.*]] = addrspacecast ptr addrspace(3) [[TMP6]] to ptr
 ; IR-NEXT:    [[TMP8:%.*]] = load float, ptr [[TMP7]], align 4
 ; IR-NEXT:    [[TMP9:%.*]] = fadd float [[TMP5]], [[TMP8]]
-; IR-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP2]], i64 128
+; IR-NEXT:    [[TMP10:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i64 128
 ; IR-NEXT:    [[TMP11:%.*]] = addrspacecast ptr addrspace(3) [[TMP10]] to ptr
 ; IR-NEXT:    [[TMP12:%.*]] = load float, ptr [[TMP11]], align 4
 ; IR-NEXT:    [[TMP13:%.*]] = fadd float [[TMP9]], [[TMP12]]
-; IR-NEXT:    [[TMP14:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP2]], i64 132
+; IR-NEXT:    [[TMP14:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i64 132
 ; IR-NEXT:    [[TMP15:%.*]] = addrspacecast ptr addrspace(3) [[TMP14]] to ptr
 ; IR-NEXT:    [[TMP16:%.*]] = load float, ptr [[TMP15]], align 4
 ; IR-NEXT:    [[TMP17:%.*]] = fadd float [[TMP13]], [[TMP16]]
diff --git a/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll b/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll
index 77b3434f4f159..da04a6e979425 100644
--- a/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll
+++ b/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll
@@ -372,8 +372,8 @@ define ptr @trunk_explicit(ptr %ptr, i64 %idx) {
 ; CHECK-LABEL: define ptr @trunk_explicit(
 ; CHECK-SAME: ptr [[PTR:%.*]], i64 [[IDX:%.*]]) {
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr [[STRUCT0:%.*]], ptr [[PTR]], i64 0, i32 3, i64 [[IDX]], i32 1
-; CHECK-NEXT:    [[PTR21:%.*]] = getelementptr i8, ptr [[TMP0]], i64 3216
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [[STRUCT0:%.*]], ptr [[PTR]], i64 0, i32 3, i64 [[IDX]], i32 1
+; CHECK-NEXT:    [[PTR21:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 3216
 ; CHECK-NEXT:    ret ptr [[PTR21]]
 ;
 entry:
@@ -389,8 +389,8 @@ define ptr @trunk_long_idx(ptr %ptr, i64 %idx) {
 ; CHECK-LABEL: define ptr @trunk_long_idx(
 ; CHECK-SAME: ptr [[PTR:%.*]], i64 [[IDX:%.*]]) {
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr [[STRUCT0:%.*]], ptr [[PTR]], i64 0, i32 3, i64 [[IDX]], i32 1
-; CHECK-NEXT:    [[PTR21:%.*]] = getelementptr i8, ptr [[TMP0]], i64 3216
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [[STRUCT0:%.*]], ptr [[PTR]], i64 0, i32 3, i64 [[IDX]], i32 1
+; CHECK-NEXT:    [[PTR21:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 3216
 ; CHECK-NEXT:    ret ptr [[PTR21]]
 ;
 entry:
diff --git a/llvm/test/Transforms/VectorCombine/pr132563.ll b/llvm/test/Transforms/VectorCombine/pr132563.ll
new file mode 100644
index 0000000000000..d0f1ebc46780e
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/pr132563.ll
@@ -0,0 +1,30 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -passes=vector-combine -S %s | FileCheck %s
+
+; Ensure canScalarizeAccess handles cases where the index type can't represent all inbounds values
+
+define void @src_1_idx(ptr %q, i8 zeroext %s, i1 %idx) {
+; CHECK-LABEL: @src_1_idx(
+; CHECK-NEXT:    [[LD:%.*]] = load <16 x i8>, ptr [[Q:%.*]], align 16
+; CHECK-NEXT:    [[V1:%.*]] = insertelement <16 x i8> [[LD]], i8 [[S:%.*]], i1 [[IDX:%.*]]
+; CHECK-NEXT:    store <16 x i8> [[V1]], ptr [[Q]], align 16
+; CHECK-NEXT:    ret void
+;
+  %ld = load <16 x i8>, ptr %q
+  %v1 = insertelement <16 x i8> %ld, i8 %s, i1 %idx
+  store <16 x i8> %v1, ptr %q
+  ret void
+}
+
+define void @src_2_idx(ptr %q, i8 zeroext %s, i8 %idx) {
+; CHECK-LABEL: @src_2_idx(
+; CHECK-NEXT:    [[LD:%.*]] = load <256 x i8>, ptr [[Q:%.*]], align 256
+; CHECK-NEXT:    [[V1:%.*]] = insertelement <256 x i8> [[LD]], i8 [[S:%.*]], i8 [[IDX:%.*]]
+; CHECK-NEXT:    store <256 x i8> [[V1]], ptr [[Q]], align 256
+; CHECK-NEXT:    ret void
+;
+  %ld = load <256 x i8>, ptr %q
+  %v1 = insertelement <256 x i8> %ld, i8 %s, i8 %idx
+  store <256 x i8> %v1, ptr %q
+  ret void
+}
diff --git a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/difile_absolute_filenames.ll b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/difile_absolute_filenames.ll
new file mode 100644
index 0000000000000..abce2a85076b2
--- /dev/null
+++ b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/difile_absolute_filenames.ll
@@ -0,0 +1,28 @@
+; RUN: opt < %s -S | FileCheck %s
+
+source_filename = "/llvm-project/foo.c"
+
+define dso_local void @f() !dbg !10 {
+entry:
+  ret void, !dbg !14
+}
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!2, !3, !4, !5, !6, !7, !8}
+!llvm.ident = !{!9}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None)
+!1 = !DIFile(filename: "/llvm-project/foo.c", directory: "/llvm-project")
+!2 = !{i32 7, !"Dwarf Version", i32 5}
+!3 = !{i32 2, !"Debug Info Version", i32 3}
+!4 = !{i32 1, !"wchar_size", i32 4}
+!5 = !{i32 8, !"PIC Level", i32 2}
+!6 = !{i32 7, !"PIE Level", i32 2}
+!7 = !{i32 7, !"uwtable", i32 2}
+!8 = !{i32 7, !"frame-pointer", i32 2}
+!9 = !{!"clang"}
+!10 = distinct !DISubprogram(name: "f", scope: !11, file: !11, line: 1, type: !12, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !0)
+!11 = !DIFile(filename: "foo.c", directory: "/llvm-project")
+!12 = !DISubroutineType(types: !13)
+!13 = !{null}
+!14 = !DILocation(line: 1, column: 11, scope: !10)
diff --git a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/difile_absolute_filenames.ll.expected b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/difile_absolute_filenames.ll.expected
new file mode 100644
index 0000000000000..0718b345846e9
--- /dev/null
+++ b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/difile_absolute_filenames.ll.expected
@@ -0,0 +1,50 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals
+; RUN: opt < %s -S | FileCheck %s
+
+source_filename = "/llvm-project/foo.c"
+
+define dso_local void @f() !dbg !10 {
+; CHECK-LABEL: @f(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret void, !dbg [[DBG14:![0-9]+]]
+;
+entry:
+  ret void, !dbg !14
+}
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!2, !3, !4, !5, !6, !7, !8}
+!llvm.ident = !{!9}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None)
+!1 = !DIFile(filename: "/llvm-project/foo.c", directory: "/llvm-project")
+!2 = !{i32 7, !"Dwarf Version", i32 5}
+!3 = !{i32 2, !"Debug Info Version", i32 3}
+!4 = !{i32 1, !"wchar_size", i32 4}
+!5 = !{i32 8, !"PIC Level", i32 2}
+!6 = !{i32 7, !"PIE Level", i32 2}
+!7 = !{i32 7, !"uwtable", i32 2}
+!8 = !{i32 7, !"frame-pointer", i32 2}
+!9 = !{!"clang"}
+!10 = distinct !DISubprogram(name: "f", scope: !11, file: !11, line: 1, type: !12, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !0)
+!11 = !DIFile(filename: "foo.c", directory: "/llvm-project")
+!12 = !DISubroutineType(types: !13)
+!13 = !{null}
+!14 = !DILocation(line: 1, column: 11, scope: !10)
+;.
+; CHECK: [[META0:![0-9]+]] = distinct !DICompileUnit(language: DW_LANG_C11, file: [[META1:![0-9]+]], producer: "clang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None)
+; CHECK: [[META1]] = !DIFile(filename: "{{.*}}foo.c", directory: {{.*}})
+; CHECK: [[META2:![0-9]+]] = !{i32 7, !"Dwarf Version", i32 5}
+; CHECK: [[META3:![0-9]+]] = !{i32 2, !"Debug Info Version", i32 3}
+; CHECK: [[META4:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
+; CHECK: [[META5:![0-9]+]] = !{i32 8, !"PIC Level", i32 2}
+; CHECK: [[META6:![0-9]+]] = !{i32 7, !"PIE Level", i32 2}
+; CHECK: [[META7:![0-9]+]] = !{i32 7, !"uwtable", i32 2}
+; CHECK: [[META8:![0-9]+]] = !{i32 7, !"frame-pointer", i32 2}
+; CHECK: [[META9:![0-9]+]] = !{!"clang"}
+; CHECK: [[META10:![0-9]+]] = distinct !DISubprogram(name: "f", scope: [[META11:![0-9]+]], file: [[META11]], line: 1, type: [[META12:![0-9]+]], scopeLine: 1, spFlags: DISPFlagDefinition, unit: [[META0]])
+; CHECK: [[META11]] = !DIFile(filename: "{{.*}}foo.c", directory: {{.*}})
+; CHECK: [[META12]] = !DISubroutineType(types: [[META13:![0-9]+]])
+; CHECK: [[META13]] = !{null}
+; CHECK: [[DBG14]] = !DILocation(line: 1, column: 11, scope: [[META10]])
+;.
diff --git a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.globals.expected b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.globals.expected
index 82f1442f30166..02575d4cff11e 100644
--- a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.globals.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.globals.expected
@@ -244,7 +244,7 @@ attributes #2 = { nounwind }
 ; CHECK: attributes #[[ATTR2]] = { nounwind }
 ;.
 ; CHECK: [[META0:![0-9]+]] = distinct !DICompileUnit(language: DW_LANG_C99, file: [[META1:![0-9]+]], producer: "{{.*}}clang version {{.*}}", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: [[META2:![0-9]+]], splitDebugInlining: false, nameTableKind: None)
-; CHECK: [[META1]] = !DIFile(filename: "various_ir_values.c", directory: {{.*}})
+; CHECK: [[META1]] = !DIFile(filename: "{{.*}}various_ir_values.c", directory: {{.*}})
 ; CHECK: [[META2]] = !{}
 ; CHECK: [[META3:![0-9]+]] = !{i32 7, !"Dwarf Version", i32 4}
 ; CHECK: [[META4:![0-9]+]] = !{i32 2, !"Debug Info Version", i32 3}
diff --git a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.transitiveglobals.expected b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.transitiveglobals.expected
index 9addb55bda98d..cd8dac743e2e0 100644
--- a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.transitiveglobals.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.transitiveglobals.expected
@@ -238,7 +238,7 @@ attributes #2 = { nounwind }
 !62 = !DILocation(line: 11, column: 1, scope: !41)
 ;.
 ; CHECK: [[META0:![0-9]+]] = distinct !DICompileUnit(language: DW_LANG_C99, file: [[META1:![0-9]+]], producer: "{{.*}}clang version {{.*}}", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: [[META2:![0-9]+]], splitDebugInlining: false, nameTableKind: None)
-; CHECK: [[META1]] = !DIFile(filename: "various_ir_values.c", directory: {{.*}})
+; CHECK: [[META1]] = !DIFile(filename: "{{.*}}various_ir_values.c", directory: {{.*}})
 ; CHECK: [[META2]] = !{}
 ; CHECK: [[META7:![0-9]+]] = distinct !DISubprogram(name: "foo", scope: [[META1]], file: [[META1]], line: 1, type: [[META8:![0-9]+]], scopeLine: 1, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: [[META0]], retainedNodes: [[META12:![0-9]+]])
 ; CHECK: [[META8]] = !DISubroutineType(types: [[META9:![0-9]+]])
diff --git a/llvm/test/tools/UpdateTestChecks/update_test_checks/difile_absolute_filenames.test b/llvm/test/tools/UpdateTestChecks/update_test_checks/difile_absolute_filenames.test
new file mode 100644
index 0000000000000..cea600d7b787b
--- /dev/null
+++ b/llvm/test/tools/UpdateTestChecks/update_test_checks/difile_absolute_filenames.test
@@ -0,0 +1,7 @@
+## Test that update_test_checks.py is not sensitive to absolute paths in
+## DIFile's filename field.
+# RUN: cp -f %S/Inputs/difile_absolute_filenames.ll %t.ll && %update_test_checks %t.ll --check-globals
+# RUN: diff -u %t.ll %S/Inputs/difile_absolute_filenames.ll.expected
+## Check that running the script again does not change the result:
+# RUN: %update_test_checks %t.ll --check-globals
+# RUN: diff -u %t.ll %S/Inputs/difile_absolute_filenames.ll.expected
diff --git a/llvm/test/tools/dsymutil/ARM/stmt-seq-macho.test b/llvm/test/tools/dsymutil/ARM/stmt-seq-macho.test
index 1e08bc07e14cb..f2fe794e1b484 100644
--- a/llvm/test/tools/dsymutil/ARM/stmt-seq-macho.test
+++ b/llvm/test/tools/dsymutil/ARM/stmt-seq-macho.test
@@ -83,14 +83,17 @@ ld64.lld \
 
 # Convert executable to YAML for the test
 echo "#--- stmt_seq_macho.o.yaml"
-obj2yaml stmt_seq_macho.o
+obj2yaml stmt_seq_macho.o | sed '1a\
+IsLittleEndian: true'
 echo ""
 echo "#--- stmt_seq_macho.exe.yaml"
-obj2yaml stmt_seq_macho.exe
+obj2yaml stmt_seq_macho.exe | sed '1a\
+IsLittleEndian: true'
 
 #--- stmt-seq-macho.yaml
 #--- stmt_seq_macho.o.yaml
 --- !mach-o
+IsLittleEndian: true
 FileHeader:
   magic:           0xFEEDFACF
   cputype:         0x100000C
@@ -1564,6 +1567,7 @@ DWARF:
 
 #--- stmt_seq_macho.exe.yaml
 --- !mach-o
+IsLittleEndian: true
 FileHeader:
   magic:           0xFEEDFACF
   cputype:         0x100000C
diff --git a/llvm/test/tools/llvm-cov/branch-export-lcov-unify-instances.test b/llvm/test/tools/llvm-cov/branch-export-lcov-unify-instances.test
new file mode 100644
index 0000000000000..368024fbe83b8
--- /dev/null
+++ b/llvm/test/tools/llvm-cov/branch-export-lcov-unify-instances.test
@@ -0,0 +1,38 @@
+
+// RUN: llvm-profdata merge %S/Inputs/branch-templates.proftext -o %t.profdata
+// RUN: llvm-cov export --format=lcov --unify-instantiations=true %S/Inputs/branch-templates.o32l -instr-profile %t.profdata | FileCheck %s -check-prefix=UNIFY
+
+// UNIFY-DAG: BRDA:14,0,0,1
+// UNIFY-DAG: BRDA:14,0,1,2
+// UNIFY-DAG: BRDA:30,0,0,1
+// UNIFY-DAG: BRDA:30,0,1,0
+// UNIFY-DAG: BRDA:32,0,0,0
+// UNIFY-DAG: BRDA:32,0,1,1
+// UNIFY-DAG: BRDA:34,0,0,1
+// UNIFY-DAG: BRDA:34,0,1,0
+// UNIFY-NOT: BRDA
+// UNIFY: BRF:8
+// UNIFY: BRH:4
+// UNIFY: LF:17
+// UNIFY: LH:13
+
+// RUN: llvm-profdata merge %S/Inputs/branch-templates.proftext -o %t.profdata
+// RUN: llvm-cov export --format=lcov --unify-instantiations=false %S/Inputs/branch-templates.o32l -instr-profile %t.profdata | FileCheck %s
+
+// CHECK-DAG: BRDA:14,0,0,0
+// CHECK-DAG: BRDA:14,0,1,1
+// CHECK-DAG: BRDA:14,1,2,1
+// CHECK-DAG: BRDA:14,1,3,0
+// CHECK-DAG: BRDA:14,2,4,0
+// CHECK-DAG: BRDA:14,2,5,1
+// CHECK-DAG: BRDA:30,0,0,1
+// CHECK-DAG: BRDA:30,0,1,0
+// CHECK-DAG: BRDA:32,0,0,0
+// CHECK-DAG: BRDA:32,0,1,1
+// CHECK-DAG: BRDA:34,0,0,1
+// CHECK-DAG: BRDA:34,0,1,0
+// CHECK-NOT: BRDA
+// CHECK: BRF:8
+// CHECK: BRH:4
+// CHECK: LF:17
+// CHECK: LH:13
diff --git a/llvm/test/tools/llvm-cov/branch-export-lcov.test b/llvm/test/tools/llvm-cov/branch-export-lcov.test
index fe43dd66de8d0..936ba2576121b 100644
--- a/llvm/test/tools/llvm-cov/branch-export-lcov.test
+++ b/llvm/test/tools/llvm-cov/branch-export-lcov.test
@@ -39,7 +39,7 @@
 
 // Check recursive macro-expansions.
 // RUN: llvm-profdata merge %S/Inputs/branch-macros.proftext -o %t.profdata
-// RUN: llvm-cov export --format=lcov %S/Inputs/branch-macros.o32l -instr-profile %t.profdata | FileCheck %s -check-prefix=MACROS
+// RUN: llvm-cov export --format=lcov --unify-instantiations=false %S/Inputs/branch-macros.o32l -instr-profile %t.profdata | FileCheck %s -check-prefix=MACROS
 // RUN: llvm-cov export --format=lcov --skip-branches %S/Inputs/branch-macros.o32l -instr-profile %t.profdata | FileCheck %s -check-prefix=NOBRANCH
 
 // MACROS-COUNT-4: BRDA:17
@@ -78,3 +78,38 @@
 // NOBRANCH-NOT: BRF
 // NOBRANCH-NOT: BRH
 
+// Check recursive macro-expansions with unify mode.
+// RUN: llvm-profdata merge %S/Inputs/branch-macros.proftext -o %t.profdata
+// RUN: llvm-cov export --format=lcov --unify-instantiations=true %S/Inputs/branch-macros.o32l -instr-profile %t.profdata | FileCheck %s -check-prefix=MACROS2
+
+// MACROS2-COUNT-4: BRDA:17
+// MACROS2-NOT: BRDA:17
+
+// MACROS2-COUNT-4: BRDA:19
+// MACROS2-NOT: BRDA:19
+
+// MACROS2-COUNT-4: BRDA:21
+// MACROS2-NOT: BRDA:21
+
+// MACROS2-COUNT-4: BRDA:23
+// MACROS2-NOT: BRDA:23
+
+// MACROS2-COUNT-4: BRDA:25
+// MACROS2-NOT: BRDA:25
+
+// MACROS2: BRDA:27,0,0,0
+// MACROS2: BRDA:27,0,1,3
+// MACROS2: BRDA:27,1,2,-
+// MACROS2: BRDA:27,1,3,-
+// MACROS2: BRDA:27,2,4,-
+// MACROS2: BRDA:27,2,5,-
+// MACROS2: BRDA:27,3,6,-
+// MACROS2: BRDA:27,3,7,-
+// MACROS2: BRDA:27,4,8,-
+// MACROS2: BRDA:27,4,9,-
+
+// MACROS2-COUNT-10: BRDA:37
+// MACROS2-NOT: BRDA:37
+// MACROS2-NOT: BRDA
+// MACROS2: BRF:40
+// MACROS2: BRH:24
diff --git a/llvm/test/tools/llvm-extract/extract-unnamed-bb.ll b/llvm/test/tools/llvm-extract/extract-unnamed-bb.ll
new file mode 100644
index 0000000000000..bb82cfdee57d9
--- /dev/null
+++ b/llvm/test/tools/llvm-extract/extract-unnamed-bb.ll
@@ -0,0 +1,28 @@
+; RUN: llvm-extract -S --bb "_Z6kernelv.extracted:%5" < %s | FileCheck %s
+
+; CHECK: define dso_local void @_Z6kernelv.extracted.extracted(i64 %0, i64 %1) {
+
+; CHECK       2:
+; CHECK:        %3 = add nuw nsw i64 %0, 1
+; CHECK-NEXT:   %4 = sub nuw nsw i64 %3, %1
+; CHECK-NEXT:   br label %.exitStub
+
+define dso_local void @_Z6kernelv.extracted(i64 %0, ptr %.out) #0 {
+newFuncRoot:
+  br label %1
+
+1:
+  %2 = phi i64 [ 0, %newFuncRoot ], [ %3, %1 ]
+  %3 = add nuw nsw i64 %2, 1
+  %4 = icmp eq i64 %2, %3
+  br i1 %4, label %5, label %1
+
+5:
+  %6 = add nuw nsw i64 %0, 1
+  %7 = sub nuw nsw i64 %6, %3
+  br label %8
+
+8:
+  %9 = add nuw i64 %0, 2
+  ret void
+}
diff --git a/llvm/test/tools/llvm-ml/macro_function.asm b/llvm/test/tools/llvm-ml/macro_function.asm
index c28d7c8c6222c..475c8b52dce79 100644
--- a/llvm/test/tools/llvm-ml/macro_function.asm
+++ b/llvm/test/tools/llvm-ml/macro_function.asm
@@ -103,14 +103,20 @@ expr_recursive_test PROC
   ret
 expr_recursive_test ENDP
 
+expand_as_directive_test @CatStr(P, RO, C)
+; CHECK-LABEL: expand_as_directive_test:
+
+  ret
+expand_as_directive_test ENDP
+
 custom_strcat MACRO arg1, arg2
   EXITM <arg1&arg2>
 ENDM
 
-expand_as_directive_test custom_strcat(P, ROC)
-; CHECK-LABEL: expand_as_directive_test:
+expand_as_directive_custom_test custom_strcat(P, ROC)
+; CHECK-LABEL: expand_as_directive_custom_test:
 
   ret
-expand_as_directive_test ENDP
+expand_as_directive_custom_test ENDP
 
 end
diff --git a/llvm/tools/llvm-cov/CodeCoverage.cpp b/llvm/tools/llvm-cov/CodeCoverage.cpp
index c828e25de4b02..1f2484cd4dda9 100644
--- a/llvm/tools/llvm-cov/CodeCoverage.cpp
+++ b/llvm/tools/llvm-cov/CodeCoverage.cpp
@@ -1283,6 +1283,10 @@ int CodeCoverageTool::doExport(int argc, const char **argv,
                               cl::desc("Don't export branch data (LCOV)"),
                               cl::cat(ExportCategory));
 
+  cl::opt<bool> UnifyInstantiations("unify-instantiations", cl::Optional,
+                                    cl::desc("Unify function instantiations"),
+                                    cl::init(true), cl::cat(ExportCategory));
+
   auto Err = commandLineParser(argc, argv);
   if (Err)
     return Err;
@@ -1290,6 +1294,7 @@ int CodeCoverageTool::doExport(int argc, const char **argv,
   ViewOpts.SkipExpansions = SkipExpansions;
   ViewOpts.SkipFunctions = SkipFunctions;
   ViewOpts.SkipBranches = SkipBranches;
+  ViewOpts.UnifyFunctionInstantiations = UnifyInstantiations;
 
   if (ViewOpts.Format != CoverageViewOptions::OutputFormat::Text &&
       ViewOpts.Format != CoverageViewOptions::OutputFormat::Lcov) {
diff --git a/llvm/tools/llvm-cov/CoverageExporterLcov.cpp b/llvm/tools/llvm-cov/CoverageExporterLcov.cpp
index d6b9367ae4c51..96be9693a7047 100644
--- a/llvm/tools/llvm-cov/CoverageExporterLcov.cpp
+++ b/llvm/tools/llvm-cov/CoverageExporterLcov.cpp
@@ -43,9 +43,29 @@
 #include "CoverageReport.h"
 
 using namespace llvm;
+using namespace coverage;
 
 namespace {
 
+struct NestedCountedRegion : public coverage::CountedRegion {
+  // Contains the path to default and expanded branches.
+  // Size is 1 for default branches and greater 1 for expanded branches.
+  std::vector<LineColPair> NestedPath;
+  // Contains the original index of this element used to keep the original order
+  // in case of equal nested path.
+  unsigned Position;
+  // Indicates whether this item should be ignored at rendering.
+  bool Ignore = false;
+
+  NestedCountedRegion(llvm::coverage::CountedRegion Region,
+                      std::vector<LineColPair> NestedPath, unsigned Position)
+      : llvm::coverage::CountedRegion(std::move(Region)),
+        NestedPath(std::move(NestedPath)), Position(Position) {}
+
+  // Returns the root line of the branch.
+  unsigned getEffectiveLine() const { return NestedPath.front().first; }
+};
+
 void renderFunctionSummary(raw_ostream &OS,
                            const FileCoverageSummary &Summary) {
   OS << "FNF:" << Summary.FunctionCoverage.getNumFunctions() << '\n'
@@ -75,58 +95,114 @@ void renderLineExecutionCounts(raw_ostream &OS,
   }
 }
 
-std::vector<llvm::coverage::CountedRegion>
+std::vector<NestedCountedRegion>
 collectNestedBranches(const coverage::CoverageMapping &Coverage,
                       ArrayRef<llvm::coverage::ExpansionRecord> Expansions,
-                      int ViewDepth = 0, int SrcLine = 0) {
-  std::vector<llvm::coverage::CountedRegion> Branches;
+                      std::vector<LineColPair> &NestedPath,
+                      unsigned &PositionCounter) {
+  std::vector<NestedCountedRegion> Branches;
   for (const auto &Expansion : Expansions) {
     auto ExpansionCoverage = Coverage.getCoverageForExpansion(Expansion);
 
-    // If we're at the top level, set the corresponding source line.
-    if (ViewDepth == 0)
-      SrcLine = Expansion.Region.LineStart;
+    // Track the path to the nested expansions.
+    NestedPath.push_back(Expansion.Region.startLoc());
 
     // Recursively collect branches from nested expansions.
     auto NestedExpansions = ExpansionCoverage.getExpansions();
     auto NestedExBranches = collectNestedBranches(Coverage, NestedExpansions,
-                                                  ViewDepth + 1, SrcLine);
+                                                  NestedPath, PositionCounter);
     append_range(Branches, NestedExBranches);
 
     // Add branches from this level of expansion.
     auto ExBranches = ExpansionCoverage.getBranches();
-    for (auto B : ExBranches)
+    for (auto &B : ExBranches)
       if (B.FileID == Expansion.FileID) {
-        B.LineStart = SrcLine;
-        Branches.push_back(B);
+        Branches.push_back(
+            NestedCountedRegion(B, NestedPath, PositionCounter++));
       }
+
+    NestedPath.pop_back();
   }
 
   return Branches;
 }
 
-bool sortLine(llvm::coverage::CountedRegion I,
-              llvm::coverage::CountedRegion J) {
-  return (I.LineStart < J.LineStart) ||
-         ((I.LineStart == J.LineStart) && (I.ColumnStart < J.ColumnStart));
+void appendNestedCountedRegions(const std::vector<CountedRegion> &Src,
+                                std::vector<NestedCountedRegion> &Dst) {
+  auto Unfolded = make_filter_range(Src, [](auto &Region) {
+    return !Region.TrueFolded || !Region.FalseFolded;
+  });
+  Dst.reserve(Dst.size() + Src.size());
+  unsigned PositionCounter = Dst.size();
+  std::transform(Unfolded.begin(), Unfolded.end(), std::back_inserter(Dst),
+                 [=, &PositionCounter](auto &Region) {
+                   return NestedCountedRegion(Region, {Region.startLoc()},
+                                              PositionCounter++);
+                 });
+}
+
+void appendNestedCountedRegions(const std::vector<NestedCountedRegion> &Src,
+                                std::vector<NestedCountedRegion> &Dst) {
+  auto Unfolded = make_filter_range(Src, [](auto &NestedRegion) {
+    return !NestedRegion.TrueFolded || !NestedRegion.FalseFolded;
+  });
+  Dst.reserve(Dst.size() + Src.size());
+  std::copy(Unfolded.begin(), Unfolded.end(), std::back_inserter(Dst));
+}
+
+bool sortNested(const NestedCountedRegion &I, const NestedCountedRegion &J) {
+  // This sorts each element by line and column.
+  // Implies that all elements are first sorted by getEffectiveLine().
+  // Use original position if NestedPath is equal.
+  return std::tie(I.NestedPath, I.Position) <
+         std::tie(J.NestedPath, J.Position);
+}
+
+void combineInstanceCounts(std::vector<NestedCountedRegion> &Branches) {
+  auto NextBranch = Branches.begin();
+  auto EndBranch = Branches.end();
+
+  while (NextBranch != EndBranch) {
+    auto SumBranch = NextBranch++;
+
+    // Ensure that only branches with the same NestedPath are summed up.
+    while (NextBranch != EndBranch &&
+           SumBranch->NestedPath == NextBranch->NestedPath) {
+      SumBranch->ExecutionCount += NextBranch->ExecutionCount;
+      SumBranch->FalseExecutionCount += NextBranch->FalseExecutionCount;
+      // Mark this branch as ignored.
+      NextBranch->Ignore = true;
+
+      NextBranch++;
+    }
+  }
 }
 
 void renderBranchExecutionCounts(raw_ostream &OS,
                                  const coverage::CoverageMapping &Coverage,
-                                 const coverage::CoverageData &FileCoverage) {
-  std::vector<llvm::coverage::CountedRegion> Branches =
-      FileCoverage.getBranches();
+                                 const coverage::CoverageData &FileCoverage,
+                                 bool UnifyInstances) {
+
+  std::vector<NestedCountedRegion> Branches;
+
+  appendNestedCountedRegions(FileCoverage.getBranches(), Branches);
 
   // Recursively collect branches for all file expansions.
-  std::vector<llvm::coverage::CountedRegion> ExBranches =
-      collectNestedBranches(Coverage, FileCoverage.getExpansions());
+  std::vector<LineColPair> NestedPath;
+  unsigned PositionCounter = 0;
+  std::vector<NestedCountedRegion> ExBranches = collectNestedBranches(
+      Coverage, FileCoverage.getExpansions(), NestedPath, PositionCounter);
 
   // Append Expansion Branches to Source Branches.
-  append_range(Branches, ExBranches);
+  appendNestedCountedRegions(ExBranches, Branches);
 
   // Sort branches based on line number to ensure branches corresponding to the
   // same source line are counted together.
-  llvm::sort(Branches, sortLine);
+  llvm::sort(Branches, sortNested);
+
+  if (UnifyInstances) {
+    combineInstanceCounts(Branches);
+  }
 
   auto NextBranch = Branches.begin();
   auto EndBranch = Branches.end();
@@ -134,12 +210,13 @@ void renderBranchExecutionCounts(raw_ostream &OS,
   // Branches with the same source line are enumerated individually
   // (BranchIndex) as well as based on True/False pairs (PairIndex).
   while (NextBranch != EndBranch) {
-    unsigned CurrentLine = NextBranch->LineStart;
+    unsigned CurrentLine = NextBranch->getEffectiveLine();
     unsigned PairIndex = 0;
     unsigned BranchIndex = 0;
 
-    while (NextBranch != EndBranch && CurrentLine == NextBranch->LineStart) {
-      if (!NextBranch->TrueFolded || !NextBranch->FalseFolded) {
+    while (NextBranch != EndBranch &&
+           CurrentLine == NextBranch->getEffectiveLine()) {
+      if (!NextBranch->Ignore) {
         unsigned BC1 = NextBranch->ExecutionCount;
         unsigned BC2 = NextBranch->FalseExecutionCount;
         bool BranchNotExecuted = (BC1 == 0 && BC2 == 0);
@@ -173,7 +250,7 @@ void renderBranchSummary(raw_ostream &OS, const FileCoverageSummary &Summary) {
 void renderFile(raw_ostream &OS, const coverage::CoverageMapping &Coverage,
                 const std::string &Filename,
                 const FileCoverageSummary &FileReport, bool ExportSummaryOnly,
-                bool SkipFunctions, bool SkipBranches) {
+                bool SkipFunctions, bool SkipBranches, bool UnifyInstances) {
   OS << "SF:" << Filename << '\n';
 
   if (!ExportSummaryOnly && !SkipFunctions) {
@@ -186,7 +263,7 @@ void renderFile(raw_ostream &OS, const coverage::CoverageMapping &Coverage,
     auto FileCoverage = Coverage.getCoverageForFile(Filename);
     renderLineExecutionCounts(OS, FileCoverage);
     if (!SkipBranches)
-      renderBranchExecutionCounts(OS, Coverage, FileCoverage);
+      renderBranchExecutionCounts(OS, Coverage, FileCoverage, UnifyInstances);
   }
   if (!SkipBranches)
     renderBranchSummary(OS, FileReport);
@@ -198,11 +275,11 @@ void renderFile(raw_ostream &OS, const coverage::CoverageMapping &Coverage,
 void renderFiles(raw_ostream &OS, const coverage::CoverageMapping &Coverage,
                  ArrayRef<std::string> SourceFiles,
                  ArrayRef<FileCoverageSummary> FileReports,
-                 bool ExportSummaryOnly, bool SkipFunctions,
-                 bool SkipBranches) {
+                 bool ExportSummaryOnly, bool SkipFunctions, bool SkipBranches,
+                 bool UnifyInstances) {
   for (unsigned I = 0, E = SourceFiles.size(); I < E; ++I)
     renderFile(OS, Coverage, SourceFiles[I], FileReports[I], ExportSummaryOnly,
-               SkipFunctions, SkipBranches);
+               SkipFunctions, SkipBranches, UnifyInstances);
 }
 
 } // end anonymous namespace
@@ -221,5 +298,6 @@ void CoverageExporterLcov::renderRoot(ArrayRef<std::string> SourceFiles) {
   auto FileReports = CoverageReport::prepareFileReports(Coverage, Totals,
                                                         SourceFiles, Options);
   renderFiles(OS, Coverage, SourceFiles, FileReports, Options.ExportSummaryOnly,
-              Options.SkipFunctions, Options.SkipBranches);
+              Options.SkipFunctions, Options.SkipBranches,
+              Options.UnifyFunctionInstantiations);
 }
diff --git a/llvm/tools/llvm-cov/CoverageViewOptions.h b/llvm/tools/llvm-cov/CoverageViewOptions.h
index 81e69c3814e30..1f6ad570f86f2 100644
--- a/llvm/tools/llvm-cov/CoverageViewOptions.h
+++ b/llvm/tools/llvm-cov/CoverageViewOptions.h
@@ -35,6 +35,7 @@ struct CoverageViewOptions {
   bool ShowBranchPercents;
   bool ShowExpandedRegions;
   bool ShowFunctionInstantiations;
+  bool UnifyFunctionInstantiations;
   bool ShowFullFilenames;
   bool ShowBranchSummary;
   bool ShowMCDCSummary;
diff --git a/llvm/tools/llvm-extract/llvm-extract.cpp b/llvm/tools/llvm-extract/llvm-extract.cpp
index 648060acb392c..69636ca018dcb 100644
--- a/llvm/tools/llvm-extract/llvm-extract.cpp
+++ b/llvm/tools/llvm-extract/llvm-extract.cpp
@@ -90,10 +90,13 @@ static cl::list<std::string> ExtractBlocks(
         "Each pair will create a function.\n"
         "If multiple basic blocks are specified in one pair,\n"
         "the first block in the sequence should dominate the rest.\n"
+        "If an unnamed basic block is to be extracted,\n"
+        "'%' should be added before the basic block variable names.\n"
         "eg:\n"
         "  --bb=f:bb1;bb2 will extract one function with both bb1 and bb2;\n"
         "  --bb=f:bb1 --bb=f:bb2 will extract two functions, one with bb1, one "
-        "with bb2."),
+        "with bb2.\n"
+        "  --bb=f:%1 will extract one function with basic block 1;"),
     cl::value_desc("function:bb1[;bb2...]"), cl::cat(ExtractCat));
 
 // ExtractAlias - The alias to extract from the module.
@@ -356,7 +359,7 @@ int main(int argc, char **argv) {
         // The function has been materialized, so add its matching basic blocks
         // to the block extractor list, or fail if a name is not found.
         auto Res = llvm::find_if(*P.first, [&](const BasicBlock &BB) {
-          return BB.getName() == BBName;
+          return BB.getNameOrAsOperand() == BBName;
         });
         if (Res == P.first->end()) {
           errs() << argv[0] << ": function " << P.first->getName()
diff --git a/llvm/unittests/Support/InstructionCostTest.cpp b/llvm/unittests/Support/InstructionCostTest.cpp
index 4e2842d8ada97..efe838897a684 100644
--- a/llvm/unittests/Support/InstructionCostTest.cpp
+++ b/llvm/unittests/Support/InstructionCostTest.cpp
@@ -23,7 +23,7 @@ TEST_F(CostTest, DefaultCtor) {
   InstructionCost DefaultCost;
 
   ASSERT_TRUE(DefaultCost.isValid());
-  EXPECT_EQ(*(DefaultCost.getValue()), 0);
+  EXPECT_EQ(DefaultCost.getValue(), 0);
 }
 
 TEST_F(CostTest, Operators) {
@@ -70,8 +70,7 @@ TEST_F(CostTest, Operators) {
   EXPECT_FALSE(TmpCost.isValid());
 
   // Test value extraction
-  EXPECT_EQ(*(VThree.getValue()), 3);
-  EXPECT_EQ(IThreeA.getValue(), std::nullopt);
+  EXPECT_EQ(VThree.getValue(), 3);
 
   EXPECT_EQ(std::min(VThree, VNegTwo), -2);
   EXPECT_EQ(std::max(VThree, VSix), 6);
diff --git a/llvm/unittests/TargetParser/TripleTest.cpp b/llvm/unittests/TargetParser/TripleTest.cpp
index 61b3637bb48e2..e409a3b6a62c5 100644
--- a/llvm/unittests/TargetParser/TripleTest.cpp
+++ b/llvm/unittests/TargetParser/TripleTest.cpp
@@ -2572,6 +2572,8 @@ TEST(TripleTest, NormalizeWindows) {
   EXPECT_EQ("i686-unknown-windows-gnu", Triple::normalize("i686-mingw32-w64"));
   EXPECT_EQ("i686-pc-windows-cygnus", Triple::normalize("i686-pc-cygwin"));
   EXPECT_EQ("i686-unknown-windows-cygnus", Triple::normalize("i686-cygwin"));
+  EXPECT_EQ("i686-pc-windows-cygnus", Triple::normalize("i686-pc-msys"));
+  EXPECT_EQ("i686-unknown-windows-cygnus", Triple::normalize("i686-msys"));
 
   EXPECT_EQ("x86_64-pc-windows-msvc", Triple::normalize("x86_64-pc-win32"));
   EXPECT_EQ("x86_64-unknown-windows-msvc", Triple::normalize("x86_64-win32"));
@@ -2581,6 +2583,11 @@ TEST(TripleTest, NormalizeWindows) {
             Triple::normalize("x86_64-pc-mingw32-w64"));
   EXPECT_EQ("x86_64-unknown-windows-gnu",
             Triple::normalize("x86_64-mingw32-w64"));
+  EXPECT_EQ("x86_64-pc-windows-cygnus", Triple::normalize("x86_64-pc-cygwin"));
+  EXPECT_EQ("x86_64-unknown-windows-cygnus",
+            Triple::normalize("x86_64-cygwin"));
+  EXPECT_EQ("x86_64-pc-windows-cygnus", Triple::normalize("x86_64-pc-msys"));
+  EXPECT_EQ("x86_64-unknown-windows-cygnus", Triple::normalize("x86_64-msys"));
 
   EXPECT_EQ("i686-pc-windows-elf", Triple::normalize("i686-pc-win32-elf"));
   EXPECT_EQ("i686-unknown-windows-elf", Triple::normalize("i686-win32-elf"));
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index 7f58c4a88c76d..a4fa063ae61cb 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -910,7 +910,7 @@ std::string TreePredicateFn::getPredCode() const {
 
   if (!isLoad() && !isStore() && !isAtomic() && getMemoryVT())
     PrintFatalError(getOrigPatFragRecord()->getRecord()->getLoc(),
-                    "MemoryVT requires IsLoad or IsStore");
+                    "MemoryVT requires IsLoad or IsStore or IsAtomic");
 
   if (!isLoad() && !isStore()) {
     if (isUnindexed())
@@ -937,11 +937,10 @@ std::string TreePredicateFn::getPredCode() const {
     if (isNonExtLoad())
       PrintFatalError(getOrigPatFragRecord()->getRecord()->getLoc(),
                       "IsNonExtLoad requires IsLoad");
-    if (isAnyExtLoad())
-      PrintFatalError(getOrigPatFragRecord()->getRecord()->getLoc(),
-                      "IsAnyExtLoad requires IsLoad");
-
     if (!isAtomic()) {
+      if (isAnyExtLoad())
+        PrintFatalError(getOrigPatFragRecord()->getRecord()->getLoc(),
+                        "IsAnyExtLoad requires IsLoad or IsAtomic");
       if (isSignExtLoad())
         PrintFatalError(getOrigPatFragRecord()->getRecord()->getLoc(),
                         "IsSignExtLoad requires IsLoad or IsAtomic");
@@ -970,8 +969,9 @@ std::string TreePredicateFn::getPredCode() const {
     if (getMemoryVT() == nullptr && !isAtomicOrderingMonotonic() &&
         getAddressSpaces() == nullptr &&
         // FIXME: Should atomic loads be IsLoad, IsAtomic, or both?
-        !isZeroExtLoad() && !isSignExtLoad() && !isAtomicOrderingAcquire() &&
-        !isAtomicOrderingRelease() && !isAtomicOrderingAcquireRelease() &&
+        !isAnyExtLoad() && !isZeroExtLoad() && !isSignExtLoad() &&
+        !isAtomicOrderingAcquire() && !isAtomicOrderingRelease() &&
+        !isAtomicOrderingAcquireRelease() &&
         !isAtomicOrderingSequentiallyConsistent() &&
         !isAtomicOrderingAcquireOrStronger() &&
         !isAtomicOrderingReleaseOrStronger() &&
@@ -1075,9 +1075,22 @@ std::string TreePredicateFn::getPredCode() const {
         "if (isReleaseOrStronger(cast<AtomicSDNode>(N)->getMergedOrdering())) "
         "return false;\n";
 
-  // TODO: Handle atomic sextload/zextload normally when ATOMIC_LOAD is removed.
-  if (isAtomic() && (isZeroExtLoad() || isSignExtLoad()))
-    Code += "return false;\n";
+  if (isAtomic()) {
+    if ((isAnyExtLoad() + isSignExtLoad() + isZeroExtLoad()) > 1)
+      PrintFatalError(getOrigPatFragRecord()->getRecord()->getLoc(),
+                      "IsAnyExtLoad, IsSignExtLoad, and IsZeroExtLoad are "
+                      "mutually exclusive");
+
+    if (isAnyExtLoad())
+      Code += "if (cast<AtomicSDNode>(N)->getExtensionType() != ISD::EXTLOAD) "
+              "return false;\n";
+    if (isSignExtLoad())
+      Code += "if (cast<AtomicSDNode>(N)->getExtensionType() != ISD::SEXTLOAD) "
+              "return false;\n";
+    if (isZeroExtLoad())
+      Code += "if (cast<AtomicSDNode>(N)->getExtensionType() != ISD::ZEXTLOAD) "
+              "return false;\n";
+  }
 
   if (isLoad() || isStore()) {
     StringRef SDNodeName = isLoad() ? "LoadSDNode" : "StoreSDNode";
diff --git a/llvm/utils/TableGen/DecoderEmitter.cpp b/llvm/utils/TableGen/DecoderEmitter.cpp
index ba360333f86e5..415fe13f87547 100644
--- a/llvm/utils/TableGen/DecoderEmitter.cpp
+++ b/llvm/utils/TableGen/DecoderEmitter.cpp
@@ -127,20 +127,32 @@ typedef std::vector<FixupList> FixupScopeList;
 typedef SmallSetVector<CachedHashString, 16> PredicateSet;
 typedef SmallSetVector<CachedHashString, 16> DecoderSet;
 
-struct DecoderTable : public std::vector<uint8_t> {
+class DecoderTable {
+public:
+  DecoderTable() { Data.reserve(16384); }
+
+  void clear() { Data.clear(); }
+  void push_back(uint8_t Item) { Data.push_back(Item); }
+  size_t size() const { return Data.size(); }
+  const uint8_t *data() const { return Data.data(); }
+
+  using const_iterator = std::vector<uint8_t>::const_iterator;
+  const_iterator begin() const { return Data.begin(); }
+  const_iterator end() const { return Data.end(); }
+
   // Insert a ULEB128 encoded value into the table.
   void insertULEB128(uint64_t Value) {
     // Encode and emit the value to filter against.
     uint8_t Buffer[16];
     unsigned Len = encodeULEB128(Value, Buffer);
-    insert(end(), Buffer, Buffer + Len);
+    Data.insert(Data.end(), Buffer, Buffer + Len);
   }
 
   // Insert space for `NumToSkip` and return the position
   // in the table for patching.
   size_t insertNumToSkip() {
-    size_t Size = size();
-    insert(end(), getNumToSkipInBytes(), 0);
+    size_t Size = Data.size();
+    Data.insert(Data.end(), getNumToSkipInBytes(), 0);
     return Size;
   }
 
@@ -156,11 +168,14 @@ struct DecoderTable : public std::vector<uint8_t> {
       PrintFatalError(
           "disassembler decoding table too large, try --large-decoder-table");
 
-    (*this)[FixupIdx] = static_cast<uint8_t>(Delta);
-    (*this)[FixupIdx + 1] = static_cast<uint8_t>(Delta >> 8);
+    Data[FixupIdx] = static_cast<uint8_t>(Delta);
+    Data[FixupIdx + 1] = static_cast<uint8_t>(Delta >> 8);
     if (getNumToSkipInBytes() == 3)
-      (*this)[FixupIdx + 2] = static_cast<uint8_t>(Delta >> 16);
+      Data[FixupIdx + 2] = static_cast<uint8_t>(Delta >> 16);
   }
+
+private:
+  std::vector<uint8_t> Data;
 };
 
 struct DecoderTableInfo {
@@ -2517,7 +2532,6 @@ namespace {
     // decoders to give more opportunities for uniqueing.
     TableInfo.Table.clear();
     TableInfo.FixupStack.clear();
-    TableInfo.Table.reserve(16384);
     TableInfo.FixupStack.emplace_back();
     FC.emitTableEntries(TableInfo);
     // Any NumToSkip fixups in the top level scope can resolve to the
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index ccc4c00fca047..b3bad55ebf278 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -219,6 +219,9 @@ static Error isTrivialOperatorNode(const TreePatternNode &N) {
     if (Predicate.isLoad() && Predicate.getMemoryVT())
       continue;
 
+    if (Predicate.isStore() && Predicate.getMemoryVT())
+      continue;
+
     if (Predicate.isLoad() || Predicate.isStore()) {
       if (Predicate.isUnindexed())
         continue;
@@ -624,7 +627,8 @@ Expected<InstructionMatcher &> GlobalISelEmitter::addBuiltinPredicates(
         0, MemoryVsLLTSizePredicateMatcher::EqualTo, 0);
     return InsnMatcher;
   }
-  if (Predicate.isLoad() && Predicate.isAnyExtLoad()) {
+  if ((Predicate.isLoad() || Predicate.isAtomic()) &&
+      Predicate.isAnyExtLoad()) {
     InsnMatcher.addPredicate<MemoryVsLLTSizePredicateMatcher>(
         0, MemoryVsLLTSizePredicateMatcher::LessThan, 0);
     return InsnMatcher;
diff --git a/llvm/utils/UpdateTestChecks/common.py b/llvm/utils/UpdateTestChecks/common.py
index 274614c2bd272..e747ae3f385a9 100644
--- a/llvm/utils/UpdateTestChecks/common.py
+++ b/llvm/utils/UpdateTestChecks/common.py
@@ -2358,7 +2358,7 @@ def add(var):
         r"(?<=\")(.+ )?(\w+ version )[\d.]+(?:[^\" ]*)(?: \([^)]+\))?",
         r"{{.*}}\2{{.*}}",
     ),  # preface with glob also, to capture optional CLANG_VENDOR
-    (r'(!DIFile\(filename: ".+", directory: )".+"', r"\1{{.*}}"),
+    (r'(!DIFile\(filename: ")(.+/)?([^/]+", directory: )".+"', r"\1{{.*}}\3{{.*}}"),
 ]
 METADATA_FILTERS_RE = [(re.compile(f), r) for (f, r) in METADATA_FILTERS]
 
diff --git a/llvm/utils/gn/secondary/clang/lib/Sema/BUILD.gn b/llvm/utils/gn/secondary/clang/lib/Sema/BUILD.gn
index 43b8979776902..6a431601ca867 100644
--- a/llvm/utils/gn/secondary/clang/lib/Sema/BUILD.gn
+++ b/llvm/utils/gn/secondary/clang/lib/Sema/BUILD.gn
@@ -32,6 +32,7 @@ static_library("Sema") {
     "//clang/lib/Edit",
     "//clang/lib/Lex",
     "//clang/lib/Support",
+    "//llvm/lib/Frontend/OpenACC",
     "//llvm/lib/Frontend/OpenMP",
     "//llvm/lib/MC",
     "//llvm/lib/Support",
diff --git a/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
index 2cc6a0baaae29..22893c949e503 100644
--- a/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
+++ b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
@@ -39,6 +39,7 @@ static_library("Utility") {
     "RegisterContextDarwin_arm.cpp",
     "RegisterContextDarwin_arm64.cpp",
     "RegisterContextDarwin_i386.cpp",
+    "RegisterContextDarwin_riscv32.cpp",
     "RegisterContextDarwin_x86_64.cpp",
     "RegisterContextDummy.cpp",
     "RegisterContextFreeBSD_i386.cpp",
diff --git a/llvm/utils/gn/secondary/lldb/source/Plugins/SymbolFile/DWARF/BUILD.gn b/llvm/utils/gn/secondary/lldb/source/Plugins/SymbolFile/DWARF/BUILD.gn
index 9dd4e7bb063b9..566195efe68a8 100644
--- a/llvm/utils/gn/secondary/lldb/source/Plugins/SymbolFile/DWARF/BUILD.gn
+++ b/llvm/utils/gn/secondary/lldb/source/Plugins/SymbolFile/DWARF/BUILD.gn
@@ -64,6 +64,7 @@ static_library("DWARF") {
     "DebugNamesDWARFIndex.cpp",
     "LogChannelDWARF.cpp",
     "ManualDWARFIndex.cpp",
+    "ManualDWARFIndexSet.cpp",
     "NameToDIE.cpp",
     "SymbolFileDWARF.cpp",
     "SymbolFileDWARFDebugMap.cpp",
diff --git a/llvm/utils/gn/secondary/llvm/lib/ProfileData/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/ProfileData/BUILD.gn
index c6fa142b37664..244688dd00ba5 100644
--- a/llvm/utils/gn/secondary/llvm/lib/ProfileData/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/ProfileData/BUILD.gn
@@ -10,6 +10,7 @@ static_library("ProfileData") {
   ]
   sources = [
     "GCOV.cpp",
+    "IndexedMemProfData.cpp",
     "InstrProf.cpp",
     "InstrProfCorrelator.cpp",
     "InstrProfReader.cpp",
diff --git a/llvm/utils/vim/syntax/llvm.vim b/llvm/utils/vim/syntax/llvm.vim
index fac509c355cb8..e3b8ff8629559 100644
--- a/llvm/utils/vim/syntax/llvm.vim
+++ b/llvm/utils/vim/syntax/llvm.vim
@@ -24,17 +24,17 @@ syn match   llvmType /\<i\d\+\>/
 " much more common for these tokens to be used for boolean constants.
 syn keyword llvmStatement add addrspacecast alloca and arcp ashr atomicrmw
 syn keyword llvmStatement bitcast br catchpad catchswitch catchret call callbr
-syn keyword llvmStatement cleanuppad cleanupret cmpxchg eq exact extractelement
-syn keyword llvmStatement extractvalue fadd fast fcmp fdiv fence fmul fneg fpext
-syn keyword llvmStatement fptosi fptoui fptrunc free freeze frem fsub
-syn keyword llvmStatement getelementptr icmp inbounds indirectbr insertelement
-syn keyword llvmStatement insertvalue inttoptr invoke landingpad load lshr
-syn keyword llvmStatement malloc max min mul nand ne ninf nnan nsw nsz nuw oeq
-syn keyword llvmStatement oge ogt ole olt one or ord phi ptrtoint resume ret
-syn keyword llvmStatement sdiv select sext sge sgt shl shufflevector sitofp
-syn keyword llvmStatement sle slt srem store sub switch trunc udiv ueq uge ugt
-syn keyword llvmStatement uitofp ule ult umax umin une uno unreachable unwind
-syn keyword llvmStatement urem va_arg xchg xor zext
+syn keyword llvmStatement cleanuppad cleanupret cmpxchg disjoint eq exact
+syn keyword llvmStatement extractelement extractvalue fadd fast fcmp fdiv fence
+syn keyword llvmStatement fmul fneg fpext fptosi fptoui fptrunc free freeze
+syn keyword llvmStatement frem fsub getelementptr icmp inbounds indirectbr
+syn keyword llvmStatement insertelement insertvalue inttoptr invoke landingpad
+syn keyword llvmStatement load lshr malloc max min mul nand ne ninf nnan nsw
+syn keyword llvmStatement nsz nuw oeq oge ogt ole olt one or ord phi ptrtoint
+syn keyword llvmStatement resume ret sdiv select sext sge sgt shl shufflevector
+syn keyword llvmStatement sitofp sle slt srem store sub switch trunc udiv ueq
+syn keyword llvmStatement uge ugt uitofp ule ult umax umin une uno unreachable
+syn keyword llvmStatement unwind urem va_arg xchg xor zext
 
 " Debug records.
 syn match llvmStatement /\v#dbg_(assign|declare|label|value)/
diff --git a/mlir/include/mlir/Dialect/GPU/Transforms/Passes.h b/mlir/include/mlir/Dialect/GPU/Transforms/Passes.h
index 5cc65082a7e56..a13ad33df29cd 100644
--- a/mlir/include/mlir/Dialect/GPU/Transforms/Passes.h
+++ b/mlir/include/mlir/Dialect/GPU/Transforms/Passes.h
@@ -13,6 +13,7 @@
 #ifndef MLIR_DIALECT_GPU_TRANSFORMS_PASSES_H_
 #define MLIR_DIALECT_GPU_TRANSFORMS_PASSES_H_
 
+#include "mlir/Dialect/AMDGPU/Utils/Chipset.h"
 #include "mlir/Dialect/GPU/IR/GPUDialect.h"
 #include "mlir/Dialect/GPU/Utils/GPUUtils.h"
 #include "mlir/IR/PatternMatch.h"
@@ -68,6 +69,20 @@ void populateGpuLowerClusteredSubgroupReduceToShufflePatterns(
     RewritePatternSet &patterns, unsigned subgroupSize,
     unsigned shuffleBitwidth = 32, PatternBenefit benefit = 1);
 
+/// Collect a set of patterns to lower `gpu.subgroup_reduce` into `amdgpu.dpp`
+/// ops over scalar types. Assumes that the subgroup has
+/// `subgroupSize` lanes. Applicable only to AMD GPUs.
+void populateGpuLowerSubgroupReduceToDPPPatterns(RewritePatternSet &patterns,
+                                                 unsigned subgroupSize,
+                                                 amdgpu::Chipset chipset,
+                                                 PatternBenefit benefit = 1);
+
+/// Disjoint counterpart of `populateGpuLowerSubgroupReduceToDPPPatterns`
+/// that only matches `gpu.subgroup_reduce` ops with a `cluster_size`.
+void populateGpuLowerClusteredSubgroupReduceToDPPPatterns(
+    RewritePatternSet &patterns, unsigned subgroupSize, amdgpu::Chipset chipset,
+    PatternBenefit benefit = 1);
+
 /// Collect all patterns to rewrite ops within the GPU dialect.
 inline void populateGpuRewritePatterns(RewritePatternSet &patterns) {
   populateGpuAllReducePatterns(patterns);
diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
index 0f195ff82c3ff..f53f95ee9ba49 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
@@ -1332,18 +1332,21 @@ def ModuleFlagAttr
     Represents a single entry of llvm.module.flags metadata
     (llvm::Module::ModuleFlagEntry in LLVM). The first element is a behavior
     flag described by `ModFlagBehaviorAttr`, the second is a string ID
-    and third is the value of the flag (currently only integer constants
-    are supported).
+    and third is the value of the flag. Current supported types of values:
+      - Integer constants
+      - Strings
 
     Example:
     ```mlir
       #llvm.mlir.module_flag<error, "wchar_size", 4>
+      #llvm.mlir.module_flag<error, "probe-stack", "inline-asm">
     ```
   }];
   let parameters = (ins "ModFlagBehavior":$behavior,
                         "StringAttr":$key,
-                        "uint32_t":$value);
+                        "Attribute":$value);
   let assemblyFormat = "`<` $behavior `,` $key `,` $value `>`";
+  let genVerifyDecl = 1;
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/mlir/include/mlir/Dialect/MemRef/Transforms/Passes.h b/mlir/include/mlir/Dialect/MemRef/Transforms/Passes.h
index d7050156862df..748248d45df26 100644
--- a/mlir/include/mlir/Dialect/MemRef/Transforms/Passes.h
+++ b/mlir/include/mlir/Dialect/MemRef/Transforms/Passes.h
@@ -37,6 +37,7 @@ class VectorDialect;
 } // namespace vector
 
 namespace memref {
+
 //===----------------------------------------------------------------------===//
 // Passes
 //===----------------------------------------------------------------------===//
@@ -44,39 +45,6 @@ namespace memref {
 #define GEN_PASS_DECL
 #include "mlir/Dialect/MemRef/Transforms/Passes.h.inc"
 
-/// Creates an instance of the ExpandOps pass that legalizes memref dialect ops
-/// to be convertible to LLVM. For example, `memref.reshape` gets converted to
-/// `memref_reinterpret_cast`.
-std::unique_ptr<Pass> createExpandOpsPass();
-
-/// Creates an operation pass to fold memref aliasing ops into consumer
-/// load/store ops into `patterns`.
-std::unique_ptr<Pass> createFoldMemRefAliasOpsPass();
-
-/// Creates an interprocedural pass to normalize memrefs to have a trivial
-/// (identity) layout map.
-std::unique_ptr<OperationPass<ModuleOp>> createNormalizeMemRefsPass();
-
-/// Creates an operation pass to resolve `memref.dim` operations with values
-/// that are defined by operations that implement the
-/// `ReifyRankedShapedTypeOpInterface`, in terms of shapes of its input
-/// operands.
-std::unique_ptr<Pass> createResolveRankedShapeTypeResultDimsPass();
-
-/// Creates an operation pass to resolve `memref.dim` operations with values
-/// that are defined by operations that implement the
-/// `InferShapedTypeOpInterface` or the `ReifyRankedShapedTypeOpInterface`,
-/// in terms of shapes of its input operands.
-std::unique_ptr<Pass> createResolveShapedTypeResultDimsPass();
-
-/// Creates an operation pass to expand some memref operation into
-/// easier to reason about operations.
-std::unique_ptr<Pass> createExpandStridedMetadataPass();
-
-/// Creates an operation pass to expand `memref.realloc` operations into their
-/// components.
-std::unique_ptr<Pass> createExpandReallocPass(bool emitDeallocs = true);
-
 //===----------------------------------------------------------------------===//
 // Registration
 //===----------------------------------------------------------------------===//
diff --git a/mlir/include/mlir/Dialect/MemRef/Transforms/Passes.td b/mlir/include/mlir/Dialect/MemRef/Transforms/Passes.td
index 651ee05ae1f3c..a46f73350bb3c 100644
--- a/mlir/include/mlir/Dialect/MemRef/Transforms/Passes.td
+++ b/mlir/include/mlir/Dialect/MemRef/Transforms/Passes.td
@@ -11,18 +11,16 @@
 
 include "mlir/Pass/PassBase.td"
 
-def ExpandOps : Pass<"memref-expand"> {
+def ExpandOpsPass : Pass<"memref-expand"> {
   let summary = "Legalize memref operations to be convertible to LLVM.";
-  let constructor = "mlir::memref::createExpandOpsPass()";
 }
 
-def FoldMemRefAliasOps : Pass<"fold-memref-alias-ops"> {
+def FoldMemRefAliasOpsPass : Pass<"fold-memref-alias-ops"> {
   let summary = "Fold memref alias ops into consumer load/store ops";
   let description = [{
     The pass folds loading/storing from/to memref aliasing ops to loading/storing
     from/to the original memref.
   }];
-  let constructor = "mlir::memref::createFoldMemRefAliasOpsPass()";
   let dependentDialects = [
       "affine::AffineDialect", "memref::MemRefDialect", "vector::VectorDialect"
   ];
@@ -44,9 +42,9 @@ def MemRefEmulateWideInt : Pass<"memref-emulate-wide-int"> {
   let dependentDialects = ["vector::VectorDialect"];
 }
 
-def NormalizeMemRefs : Pass<"normalize-memrefs", "ModuleOp"> {
+def NormalizeMemRefsPass : Pass<"normalize-memrefs", "ModuleOp"> {
   let summary = "Normalize memrefs";
-   let description = [{
+  let description = [{
     This pass transforms memref types with a non-trivial
     [layout map](https://mlir.llvm.org/docs/Dialects/Builtin/#affine-map-layout)
     into memref types with an identity layout map, e.g. (i, j) -> (i, j). This
@@ -155,26 +153,23 @@ def NormalizeMemRefs : Pass<"normalize-memrefs", "ModuleOp"> {
   }
   ```
   }];
-  let constructor = "mlir::memref::createNormalizeMemRefsPass()";
   let dependentDialects = ["affine::AffineDialect"];
 }
 
-def ResolveRankedShapeTypeResultDims :
-    Pass<"resolve-ranked-shaped-type-result-dims"> {
+def ResolveRankedShapeTypeResultDimsPass
+    : Pass<"resolve-ranked-shaped-type-result-dims"> {
   let summary = "Resolve memref.dim of result values of ranked shape type";
   let description = [{
     The pass resolves memref.dim of result of operations that
     implement the `ReifyRankedShapedTypeOpInterface` in terms of
     shapes of its operands.
   }];
-  let constructor =
-      "mlir::memref::createResolveRankedShapeTypeResultDimsPass()";
   let dependentDialects = [
     "memref::MemRefDialect", "tensor::TensorDialect"
   ];
 }
 
-def ResolveShapedTypeResultDims : Pass<"resolve-shaped-type-result-dims"> {
+def ResolveShapedTypeResultDimsPass : Pass<"resolve-shaped-type-result-dims"> {
   let summary = "Resolve memref.dim of result values";
   let description = [{
     The pass resolves memref.dim of result of operations that
@@ -182,13 +177,12 @@ def ResolveShapedTypeResultDims : Pass<"resolve-shaped-type-result-dims"> {
     `ReifyRankedShapedTypeOpInterface` in terms of shapes of its
     operands.
   }];
-  let constructor = "mlir::memref::createResolveShapedTypeResultDimsPass()";
   let dependentDialects = [
     "affine::AffineDialect", "memref::MemRefDialect", "tensor::TensorDialect"
   ];
 }
 
-def ExpandStridedMetadata : Pass<"expand-strided-metadata"> {
+def ExpandStridedMetadataPass : Pass<"expand-strided-metadata"> {
   let summary = "Expand memref operations into easier to analyze constructs";
   let description = [{
     The pass expands memref operations that modify the metadata of a memref
@@ -205,13 +199,12 @@ def ExpandStridedMetadata : Pass<"expand-strided-metadata"> {
     - `memref.extract_strided_metadata`
     - `memref.subview`
   }];
-  let constructor = "mlir::memref::createExpandStridedMetadataPass()";
   let dependentDialects = [
       "affine::AffineDialect", "memref::MemRefDialect"
   ];
 }
 
-def ExpandRealloc : Pass<"expand-realloc"> {
+def ExpandReallocPass : Pass<"expand-realloc"> {
   let summary = "Expand memref.realloc operations into its components";
   let description = [{
     The `memref.realloc` operation performs a conditional allocation and copy to
@@ -243,11 +236,10 @@ def ExpandRealloc : Pass<"expand-realloc"> {
     }
     ```
   }];
-  let options = [
-    Option<"emitDeallocs", "emit-deallocs", "bool", /*default=*/"true",
-           "Emit deallocation operations for the original MemRef">,
+  let options = [Option<"emitDeallocs", "emit-deallocs", "bool",
+                        /*default=*/"true",
+                        "Emit deallocation operations for the original MemRef">,
   ];
-  let constructor = "mlir::memref::createExpandReallocPass()";
   let dependentDialects = [
       "arith::ArithDialect", "scf::SCFDialect", "memref::MemRefDialect"
   ];
diff --git a/mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td b/mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
index 275472bc5edd9..5e249e639d837 100644
--- a/mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
+++ b/mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
@@ -2611,11 +2611,11 @@ def OpenACC_InitOp : OpenACC_Op<"init", [AttrSizedOperandSegments]> {
   }];
 
   let arguments = (ins OptionalAttr<TypedArrayAttrBase<OpenACC_DeviceTypeAttr, "Device type attributes">>:$device_types,
-                       Optional<IntOrIndex>:$deviceNumOperand,
+                       Optional<IntOrIndex>:$deviceNum,
                        Optional<I1>:$ifCond);
 
   let assemblyFormat = [{
-    oilist(`device_num` `(` $deviceNumOperand `:` type($deviceNumOperand) `)`
+    oilist(`device_num` `(` $deviceNum `:` type($deviceNum) `)`
       | `if` `(` $ifCond `)`
     ) attr-dict-with-keyword
   }];
@@ -2642,11 +2642,11 @@ def OpenACC_ShutdownOp : OpenACC_Op<"shutdown", [AttrSizedOperandSegments]> {
   }];
 
   let arguments = (ins OptionalAttr<TypedArrayAttrBase<OpenACC_DeviceTypeAttr, "Device type attributes">>:$device_types,
-                       Optional<IntOrIndex>:$deviceNumOperand,
+                       Optional<IntOrIndex>:$deviceNum,
                        Optional<I1>:$ifCond);
 
   let assemblyFormat = [{
-    oilist(`device_num` `(` $deviceNumOperand `:` type($deviceNumOperand) `)`
+    oilist(`device_num` `(` $deviceNum `:` type($deviceNum) `)`
     |`if` `(` $ifCond `)`
     ) attr-dict-with-keyword
   }];
diff --git a/mlir/include/mlir/Dialect/Tosa/IR/TosaUtilOps.td b/mlir/include/mlir/Dialect/Tosa/IR/TosaUtilOps.td
index 3b2ede1b1a1a2..0ab0a62f1cf11 100644
--- a/mlir/include/mlir/Dialect/Tosa/IR/TosaUtilOps.td
+++ b/mlir/include/mlir/Dialect/Tosa/IR/TosaUtilOps.td
@@ -109,9 +109,9 @@ def Tosa_VariableOp : Tosa_Op<"variable", []> {
 }
 
 //===----------------------------------------------------------------------===//
-// Operator: variable.write
+// Operator: variable_write
 //===----------------------------------------------------------------------===//
-def Tosa_VariableWriteOp : Tosa_Op<"variable.write", []> {
+def Tosa_VariableWriteOp : Tosa_Op<"variable_write", []> {
   let summary = "write_buffer operator";
 
   let description = [{
@@ -120,7 +120,7 @@ def Tosa_VariableWriteOp : Tosa_Op<"variable.write", []> {
 
   let arguments = (ins
     SymbolNameAttr:$name,
-    AnyType:$value
+    Tosa_Tensor:$input1
   );
 
   list<Availability> availability = [
@@ -129,14 +129,14 @@ def Tosa_VariableWriteOp : Tosa_Op<"variable.write", []> {
   ];
 
   let assemblyFormat = [{
-    $name attr-dict `,` $value `:` type($value)
+    $name attr-dict `,` $input1 `:` type($input1)
   }];
 }
 
 //===----------------------------------------------------------------------===//
-// Operator: variable.read
+// Operator: variable_read
 //===----------------------------------------------------------------------===//
-def Tosa_VariableReadOp : Tosa_Op<"variable.read", []> {
+def Tosa_VariableReadOp : Tosa_Op<"variable_read", []> {
   let summary = "read_buffer operator";
 
   let description = [{
@@ -148,7 +148,7 @@ def Tosa_VariableReadOp : Tosa_Op<"variable.read", []> {
   );
 
   let results = (outs
-    AnyType:$value
+    Tosa_Tensor:$output1
   );
 
   list<Availability> availability = [
@@ -157,7 +157,7 @@ def Tosa_VariableReadOp : Tosa_Op<"variable.read", []> {
   ];
 
   let assemblyFormat = [{
-    $name attr-dict `:` type($value)
+    $name attr-dict `:` type($output1)
   }];
 }
 
diff --git a/mlir/include/mlir/Dialect/X86Vector/X86Vector.td b/mlir/include/mlir/Dialect/X86Vector/X86Vector.td
index 5be0d92db4630..126fa0e352656 100644
--- a/mlir/include/mlir/Dialect/X86Vector/X86Vector.td
+++ b/mlir/include/mlir/Dialect/X86Vector/X86Vector.td
@@ -83,7 +83,7 @@ def MaskCompressOp : AVX512_Op<"mask.compress", [Pure,
     }
   }];
   let extraClassDeclaration = [{
-    SmallVector<Value> getIntrinsicOperands(::mlir::RewriterBase&);
+    SmallVector<Value> getIntrinsicOperands(::mlir::RewriterBase&, const LLVMTypeConverter&);
   }];
 }
 
@@ -404,8 +404,127 @@ def DotOp : AVX_LowOp<"dot", [Pure,
     }
   }];
   let extraClassDeclaration = [{
-    SmallVector<Value> getIntrinsicOperands(::mlir::RewriterBase&);
+    SmallVector<Value> getIntrinsicOperands(::mlir::RewriterBase&, const LLVMTypeConverter&);
   }];
 }
 
+
+//----------------------------------------------------------------------------//
+// AVX: Convert packed BF16 even-indexed/odd-indexed elements into packed F32
+//----------------------------------------------------------------------------//
+
+def CvtPackedEvenIndexedBF16ToF32Op : AVX_Op<"cvt.packed.even.indexed.bf16_to_f32", [MemoryEffects<[MemRead]>, 
+  DeclareOpInterfaceMethods<OneToOneIntrinsicOpInterface>]> {
+  let summary = "AVX: Convert packed BF16 even-indexed elements into packed F32 Data.";
+  let description = [{
+    #### From the Intel Intrinsics Guide:
+
+    Convert packed BF16 (16-bit) floating-point even-indexed elements stored at
+    memory locations starting at location `__A` to packed single-precision
+    (32-bit) floating-point elements, and store the results in `dst`.
+
+    Example:
+    ```mlir
+    %dst = x86vector.avx.cvt.packed.even.indexed.bf16_to_f32 %a : memref<16xbf16> -> vector<8xf32>
+    ```
+  }];
+  let arguments = (ins AnyMemRef:$a);
+  let results = (outs VectorOfLengthAndType<[4, 8], [F32]>:$dst);
+  let assemblyFormat =
+    "$a  attr-dict`:` type($a)`->` type($dst)";
+
+  let extraClassDefinition = [{
+    std::string $cppClass::getIntrinsicName() {
+      std::string intr = "llvm.x86.vcvtneebf162ps";
+      VectorType vecType = getDst().getType();
+      unsigned elemBitWidth = vecType.getElementTypeBitWidth();
+      unsigned opBitWidth = vecType.getShape()[0] * elemBitWidth;
+      intr += std::to_string(opBitWidth);
+      return intr;
+    }
+  }];
+
+  let extraClassDeclaration = [{
+        SmallVector<Value> getIntrinsicOperands(::mlir::RewriterBase&, const LLVMTypeConverter&);
+  }];
+}
+
+def CvtPackedOddIndexedBF16ToF32Op : AVX_Op<"cvt.packed.odd.indexed.bf16_to_f32", [MemoryEffects<[MemRead]>, 
+  DeclareOpInterfaceMethods<OneToOneIntrinsicOpInterface>]> {
+  let summary = "AVX: Convert packed BF16 odd-indexed elements into packed F32 Data.";
+  let description = [{
+    #### From the Intel Intrinsics Guide:
+
+    Convert packed BF16 (16-bit) floating-point odd-indexed elements stored at
+    memory locations starting at location `__A` to packed single-precision
+    (32-bit) floating-point elements, and store the results in `dst`.
+
+    Example:
+    ```mlir
+    %dst = x86vector.avx.cvt.packed.odd.indexed.bf16_to_f32 %a : memref<16xbf16> -> vector<8xf32>
+    ```
+  }];
+  let arguments = (ins AnyMemRef:$a);
+  let results = (outs VectorOfLengthAndType<[4, 8], [F32]>:$dst);
+  let assemblyFormat =
+    "$a  attr-dict`:` type($a)`->` type($dst)";
+
+  let extraClassDefinition = [{
+    std::string $cppClass::getIntrinsicName() {
+      std::string intr = "llvm.x86.vcvtneobf162ps";
+      VectorType vecType = getDst().getType();
+      unsigned elemBitWidth = vecType.getElementTypeBitWidth();
+      unsigned opBitWidth = vecType.getShape()[0] * elemBitWidth;
+      intr += std::to_string(opBitWidth);
+      return intr;
+    }
+  }];
+
+  let extraClassDeclaration = [{
+        SmallVector<Value> getIntrinsicOperands(::mlir::RewriterBase&, const LLVMTypeConverter&);
+  }];
+}
+
+//----------------------------------------------------------------------------//
+// AVX: Convert BF16 to F32 and broadcast into packed F32
+//----------------------------------------------------------------------------//
+
+def BcstBF16ToPackedF32Op : AVX_Op<"bcst.bf16_to_f32.packed", [MemoryEffects<[MemRead]>,
+  DeclareOpInterfaceMethods<OneToOneIntrinsicOpInterface>]> {
+  let summary = "AVX: Broadcasts BF16 into packed F32 Data.";
+  let description = [{
+    #### From the Intel Intrinsics Guide:
+
+    Convert scalar BF16 (16-bit) floating-point element stored at memory locations
+    starting at location `__A` to a single-precision (32-bit) floating-point,
+    broadcast it to packed single-precision (32-bit) floating-point elements,
+    and store the results in `dst`.
+
+    Example:
+    ```mlir
+    %dst = x86vector.avx.bcst.bf16_to_f32.packed %a : memref<1xbf16> -> vector<8xf32>
+    ```
+  }];
+  let arguments = (ins AnyMemRef:$a);
+  let results = (outs VectorOfLengthAndType<[4, 8], [F32]>:$dst);
+  let assemblyFormat =
+    "$a  attr-dict`:` type($a)`->` type($dst)";
+
+  let extraClassDefinition = [{
+    std::string $cppClass::getIntrinsicName() {
+      std::string intr = "llvm.x86.vbcstnebf162ps";
+      VectorType vecType = getDst().getType();
+      unsigned elemBitWidth = vecType.getElementTypeBitWidth();
+      unsigned opBitWidth = vecType.getShape()[0] * elemBitWidth;
+      intr += std::to_string(opBitWidth);
+      return intr;
+    }
+  }];
+
+    let extraClassDeclaration = [{
+        SmallVector<Value> getIntrinsicOperands(::mlir::RewriterBase&, const LLVMTypeConverter&);
+  }];
+
+}
+
 #endif // X86VECTOR_OPS
diff --git a/mlir/include/mlir/Dialect/X86Vector/X86VectorDialect.h b/mlir/include/mlir/Dialect/X86Vector/X86VectorDialect.h
index 7bcf4c69b0a6c..308adfa5b9021 100644
--- a/mlir/include/mlir/Dialect/X86Vector/X86VectorDialect.h
+++ b/mlir/include/mlir/Dialect/X86Vector/X86VectorDialect.h
@@ -14,6 +14,8 @@
 #define MLIR_DIALECT_X86VECTOR_X86VECTORDIALECT_H_
 
 #include "mlir/Bytecode/BytecodeOpInterface.h"
+#include "mlir/Conversion/LLVMCommon/Pattern.h"
+#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
 #include "mlir/IR/BuiltinTypes.h"
 #include "mlir/IR/Dialect.h"
 #include "mlir/IR/OpDefinition.h"
diff --git a/mlir/include/mlir/Dialect/X86Vector/X86VectorInterfaces.td b/mlir/include/mlir/Dialect/X86Vector/X86VectorInterfaces.td
index 98d5ca70b4a7d..5176f4a447b6e 100644
--- a/mlir/include/mlir/Dialect/X86Vector/X86VectorInterfaces.td
+++ b/mlir/include/mlir/Dialect/X86Vector/X86VectorInterfaces.td
@@ -58,7 +58,7 @@ def OneToOneIntrinsicOpInterface : OpInterface<"OneToOneIntrinsicOp"> {
       }],
       /*retType=*/"SmallVector<Value>",
       /*methodName=*/"getIntrinsicOperands",
-      /*args=*/(ins "::mlir::RewriterBase &":$rewriter),
+      /*args=*/(ins "::mlir::RewriterBase &":$rewriter, "const LLVMTypeConverter &":$typeConverter),
       /*methodBody=*/"",
       /*defaultImplementation=*/"return SmallVector<Value>($_op->getOperands());"
     >,
diff --git a/mlir/include/mlir/Transforms/GreedyPatternRewriteDriver.h b/mlir/include/mlir/Transforms/GreedyPatternRewriteDriver.h
index 110b4f64856eb..45e61b68f5db2 100644
--- a/mlir/include/mlir/Transforms/GreedyPatternRewriteDriver.h
+++ b/mlir/include/mlir/Transforms/GreedyPatternRewriteDriver.h
@@ -49,25 +49,43 @@ class GreedyRewriteConfig {
   /// larger patterns when given an ambiguous pattern set.
   ///
   /// Note: Only applicable when simplifying entire regions.
-  bool useTopDownTraversal = false;
+  bool getUseTopDownTraversal() const { return useTopDownTraversal; }
+  GreedyRewriteConfig &setUseTopDownTraversal(bool use = true) {
+    useTopDownTraversal = use;
+    return *this;
+  }
 
   /// Perform control flow optimizations to the region tree after applying all
   /// patterns.
   ///
   /// Note: Only applicable when simplifying entire regions.
-  GreedySimplifyRegionLevel enableRegionSimplification =
-      GreedySimplifyRegionLevel::Aggressive;
+  GreedySimplifyRegionLevel getRegionSimplificationLevel() const {
+    return regionSimplificationLevel;
+  }
+  GreedyRewriteConfig &
+  setRegionSimplificationLevel(GreedySimplifyRegionLevel level) {
+    regionSimplificationLevel = level;
+    return *this;
+  }
 
   /// This specifies the maximum number of times the rewriter will iterate
   /// between applying patterns and simplifying regions. Use `kNoLimit` to
   /// disable this iteration limit.
   ///
   /// Note: Only applicable when simplifying entire regions.
-  int64_t maxIterations = 10;
+  int64_t getMaxIterations() const { return maxIterations; }
+  GreedyRewriteConfig &setMaxIterations(int64_t iterations) {
+    maxIterations = iterations;
+    return *this;
+  }
 
   /// This specifies the maximum number of rewrites within an iteration. Use
   /// `kNoLimit` to disable this limit.
-  int64_t maxNumRewrites = kNoLimit;
+  int64_t getMaxNumRewrites() const { return maxNumRewrites; }
+  GreedyRewriteConfig &setMaxNumRewrites(int64_t limit) {
+    maxNumRewrites = limit;
+    return *this;
+  }
 
   static constexpr int64_t kNoLimit = -1;
 
@@ -75,7 +93,11 @@ class GreedyRewriteConfig {
   /// specified, the closest enclosing region around the initial list of ops
   /// (or the specified region, depending on which greedy rewrite entry point
   /// is used) is used as a scope.
-  Region *scope = nullptr;
+  Region *getScope() const { return scope; }
+  GreedyRewriteConfig &setScope(Region *scope) {
+    this->scope = scope;
+    return *this;
+  }
 
   /// Strict mode can restrict the ops that are added to the worklist during
   /// the rewrite.
@@ -87,16 +109,44 @@ class GreedyRewriteConfig {
   /// * GreedyRewriteStrictness::ExistingOps: Only pre-existing ops (that were
   ///   were on the worklist at the very beginning) enqueued. All other ops are
   ///   excluded.
-  GreedyRewriteStrictness strictMode = GreedyRewriteStrictness::AnyOp;
+  GreedyRewriteStrictness getStrictness() const { return strictness; }
+  GreedyRewriteConfig &setStrictness(GreedyRewriteStrictness mode) {
+    strictness = mode;
+    return *this;
+  }
 
   /// An optional listener that should be notified about IR modifications.
-  RewriterBase::Listener *listener = nullptr;
+  RewriterBase::Listener *getListener() const { return listener; }
+  GreedyRewriteConfig &setListener(RewriterBase::Listener *listener) {
+    this->listener = listener;
+    return *this;
+  }
 
   /// Whether this should fold while greedily rewriting.
-  bool fold = true;
+  bool isFoldingEnabled() const { return fold; }
+  GreedyRewriteConfig &enableFolding(bool enable = true) {
+    fold = enable;
+    return *this;
+  }
 
   /// If set to "true", constants are CSE'd (even across multiple regions that
   /// are in a parent-ancestor relationship).
+  bool isConstantCSEEnabled() const { return cseConstants; }
+  GreedyRewriteConfig &enableConstantCSE(bool enable = true) {
+    cseConstants = enable;
+    return *this;
+  }
+
+private:
+  Region *scope = nullptr;
+  bool useTopDownTraversal = false;
+  GreedySimplifyRegionLevel regionSimplificationLevel =
+      GreedySimplifyRegionLevel::Aggressive;
+  int64_t maxIterations = 10;
+  int64_t maxNumRewrites = kNoLimit;
+  GreedyRewriteStrictness strictness = GreedyRewriteStrictness::AnyOp;
+  RewriterBase::Listener *listener = nullptr;
+  bool fold = true;
   bool cseConstants = true;
 };
 
@@ -128,14 +178,14 @@ applyPatternsGreedily(Region &region, const FrozenRewritePatternSet &patterns,
                       GreedyRewriteConfig config = GreedyRewriteConfig(),
                       bool *changed = nullptr);
 /// Same as `applyPatternsAndGreedily` above with folding.
-/// FIXME: Remove this once transition to above is complieted.
+/// FIXME: Remove this once transition to above is completed.
 LLVM_DEPRECATED("Use applyPatternsGreedily() instead", "applyPatternsGreedily")
 inline LogicalResult
 applyPatternsAndFoldGreedily(Region &region,
                              const FrozenRewritePatternSet &patterns,
                              GreedyRewriteConfig config = GreedyRewriteConfig(),
                              bool *changed = nullptr) {
-  config.fold = true;
+  config.enableFolding();
   return applyPatternsGreedily(region, patterns, config, changed);
 }
 
@@ -187,7 +237,7 @@ applyPatternsAndFoldGreedily(Operation *op,
                              const FrozenRewritePatternSet &patterns,
                              GreedyRewriteConfig config = GreedyRewriteConfig(),
                              bool *changed = nullptr) {
-  config.fold = true;
+  config.enableFolding();
   return applyPatternsGreedily(op, patterns, config, changed);
 }
 
@@ -233,7 +283,7 @@ applyOpPatternsAndFold(ArrayRef<Operation *> ops,
                        const FrozenRewritePatternSet &patterns,
                        GreedyRewriteConfig config = GreedyRewriteConfig(),
                        bool *changed = nullptr, bool *allErased = nullptr) {
-  config.fold = true;
+  config.enableFolding();
   return applyOpPatternsGreedily(ops, patterns, config, changed, allErased);
 }
 
diff --git a/mlir/include/mlir/Transforms/Passes.td b/mlir/include/mlir/Transforms/Passes.td
index a39ab77fc8fb3..1e89a78912e99 100644
--- a/mlir/include/mlir/Transforms/Passes.td
+++ b/mlir/include/mlir/Transforms/Passes.td
@@ -33,7 +33,7 @@ def Canonicalizer : Pass<"canonicalize"> {
     Option<"topDownProcessingEnabled", "top-down", "bool",
            /*default=*/"true",
            "Seed the worklist in general top-down order">,
-    Option<"enableRegionSimplification", "region-simplify", "mlir::GreedySimplifyRegionLevel",
+    Option<"regionSimplifyLevel", "region-simplify", "mlir::GreedySimplifyRegionLevel",
            /*default=*/"mlir::GreedySimplifyRegionLevel::Normal",
            "Perform control flow optimizations to the region tree",
              [{::llvm::cl::values(
diff --git a/mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp b/mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
index 9ca93ab28daed..95364c26d1a7d 100644
--- a/mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
+++ b/mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
@@ -1490,6 +1490,14 @@ class RescaleConverter : public OpRewritePattern<tosa::RescaleOp> {
             return;
           };
 
+          // pre-process OutputZP as it can be unsigned
+          auto outBitwidth = outputTy.getElementType().getIntOrFloatBitWidth();
+          APInt OZp(outBitwidth, !op.getOutputUnsigned());
+          OZp = static_cast<int64_t>(*maybeOZp);
+          *maybeOZp = op.getOutputUnsigned()
+                          ? static_cast<int64_t>(OZp.getZExtValue())
+                          : OZp.getSExtValue();
+
           auto outputZp = createConstOpFromZpVal<int32_t>(
               op, *maybeOZp, nestedBuilder.getI32Type(), nestedBuilder);
 
diff --git a/mlir/lib/Conversion/TosaToMLProgram/TosaToMLProgram.cpp b/mlir/lib/Conversion/TosaToMLProgram/TosaToMLProgram.cpp
index d134d8cdf485e..310566e692202 100644
--- a/mlir/lib/Conversion/TosaToMLProgram/TosaToMLProgram.cpp
+++ b/mlir/lib/Conversion/TosaToMLProgram/TosaToMLProgram.cpp
@@ -45,7 +45,7 @@ class VariableWriteOpConverter
     auto globalSymbolRef =
         SymbolRefAttr::get(rewriter.getContext(), op.getName());
     auto newVariableWrite = rewriter.create<ml_program::GlobalStoreOp>(
-        op.getLoc(), globalSymbolRef, op.getValue());
+        op.getLoc(), globalSymbolRef, op.getInput1());
     rewriter.replaceOp(op, newVariableWrite);
     return success();
   }
diff --git a/mlir/lib/Dialect/Affine/TransformOps/AffineTransformOps.cpp b/mlir/lib/Dialect/Affine/TransformOps/AffineTransformOps.cpp
index 9f7df7823d997..43d37ee3332ef 100644
--- a/mlir/lib/Dialect/Affine/TransformOps/AffineTransformOps.cpp
+++ b/mlir/lib/Dialect/Affine/TransformOps/AffineTransformOps.cpp
@@ -127,12 +127,13 @@ SimplifyBoundedAffineOpsOp::apply(transform::TransformRewriter &rewriter,
   patterns.insert<SimplifyAffineMinMaxOp<AffineMinOp>,
                   SimplifyAffineMinMaxOp<AffineMaxOp>>(getContext(), cstr);
   FrozenRewritePatternSet frozenPatterns(std::move(patterns));
-  GreedyRewriteConfig config;
-  config.listener =
-      static_cast<RewriterBase::Listener *>(rewriter.getListener());
-  config.strictMode = GreedyRewriteStrictness::ExistingAndNewOps;
   // Apply the simplification pattern to a fixpoint.
-  if (failed(applyOpPatternsGreedily(targets, frozenPatterns, config))) {
+  if (failed(applyOpPatternsGreedily(
+          targets, frozenPatterns,
+          GreedyRewriteConfig()
+              .setListener(
+                  static_cast<RewriterBase::Listener *>(rewriter.getListener()))
+              .setStrictness(GreedyRewriteStrictness::ExistingAndNewOps)))) {
     auto diag = emitDefiniteFailure()
                 << "affine.min/max simplification did not converge";
     return diag;
diff --git a/mlir/lib/Dialect/Affine/Transforms/AffineDataCopyGeneration.cpp b/mlir/lib/Dialect/Affine/Transforms/AffineDataCopyGeneration.cpp
index 4d30213cc6ec2..62c1857e4b1da 100644
--- a/mlir/lib/Dialect/Affine/Transforms/AffineDataCopyGeneration.cpp
+++ b/mlir/lib/Dialect/Affine/Transforms/AffineDataCopyGeneration.cpp
@@ -237,7 +237,8 @@ void AffineDataCopyGeneration::runOnOperation() {
   AffineLoadOp::getCanonicalizationPatterns(patterns, &getContext());
   AffineStoreOp::getCanonicalizationPatterns(patterns, &getContext());
   FrozenRewritePatternSet frozenPatterns(std::move(patterns));
-  GreedyRewriteConfig config;
-  config.strictMode = GreedyRewriteStrictness::ExistingAndNewOps;
-  (void)applyOpPatternsGreedily(copyOps, frozenPatterns, config);
+  (void)applyOpPatternsGreedily(
+      copyOps, frozenPatterns,
+      GreedyRewriteConfig().setStrictness(
+          GreedyRewriteStrictness::ExistingAndNewOps));
 }
diff --git a/mlir/lib/Dialect/Affine/Transforms/SimplifyAffineStructures.cpp b/mlir/lib/Dialect/Affine/Transforms/SimplifyAffineStructures.cpp
index 31711ade3153b..9e9096c2e3186 100644
--- a/mlir/lib/Dialect/Affine/Transforms/SimplifyAffineStructures.cpp
+++ b/mlir/lib/Dialect/Affine/Transforms/SimplifyAffineStructures.cpp
@@ -109,7 +109,8 @@ void SimplifyAffineStructures::runOnOperation() {
     if (isa<AffineForOp, AffineIfOp, AffineApplyOp>(op))
       opsToSimplify.push_back(op);
   });
-  GreedyRewriteConfig config;
-  config.strictMode = GreedyRewriteStrictness::ExistingAndNewOps;
-  (void)applyOpPatternsGreedily(opsToSimplify, frozenPatterns, config);
+  (void)applyOpPatternsGreedily(
+      opsToSimplify, frozenPatterns,
+      GreedyRewriteConfig().setStrictness(
+          GreedyRewriteStrictness::ExistingAndNewOps));
 }
diff --git a/mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp b/mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
index dd539ff685653..0d4ba3940c48e 100644
--- a/mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
+++ b/mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
@@ -315,11 +315,12 @@ LogicalResult mlir::affine::affineForOpBodySkew(AffineForOp forOp,
         // Simplify/canonicalize the affine.for.
         RewritePatternSet patterns(res.getContext());
         AffineForOp::getCanonicalizationPatterns(patterns, res.getContext());
-        GreedyRewriteConfig config;
-        config.strictMode = GreedyRewriteStrictness::ExistingOps;
         bool erased;
-        (void)applyOpPatternsGreedily(res.getOperation(), std::move(patterns),
-                                      config, /*changed=*/nullptr, &erased);
+        (void)applyOpPatternsGreedily(
+            res.getOperation(), std::move(patterns),
+            GreedyRewriteConfig().setStrictness(
+                GreedyRewriteStrictness::ExistingAndNewOps),
+            /*changed=*/nullptr, &erased);
         if (!erased && !prologue)
           prologue = res;
         if (!erased)
diff --git a/mlir/lib/Dialect/Affine/Utils/Utils.cpp b/mlir/lib/Dialect/Affine/Utils/Utils.cpp
index 2925aa918cb1c..11798b99fa879 100644
--- a/mlir/lib/Dialect/Affine/Utils/Utils.cpp
+++ b/mlir/lib/Dialect/Affine/Utils/Utils.cpp
@@ -426,11 +426,11 @@ LogicalResult mlir::affine::hoistAffineIfOp(AffineIfOp ifOp, bool *folded) {
   RewritePatternSet patterns(ifOp.getContext());
   AffineIfOp::getCanonicalizationPatterns(patterns, ifOp.getContext());
   FrozenRewritePatternSet frozenPatterns(std::move(patterns));
-  GreedyRewriteConfig config;
-  config.strictMode = GreedyRewriteStrictness::ExistingOps;
   bool erased;
-  (void)applyOpPatternsGreedily(ifOp.getOperation(), frozenPatterns, config,
-                                /*changed=*/nullptr, &erased);
+  (void)applyOpPatternsGreedily(
+      ifOp.getOperation(), frozenPatterns,
+      GreedyRewriteConfig().setStrictness(GreedyRewriteStrictness::ExistingOps),
+      /*changed=*/nullptr, &erased);
   if (erased) {
     if (folded)
       *folded = true;
diff --git a/mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp b/mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp
index 602d80a45993e..f2f93883eb2b7 100644
--- a/mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp
+++ b/mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp
@@ -494,10 +494,9 @@ struct IntRangeOptimizationsPass final
     RewritePatternSet patterns(ctx);
     populateIntRangeOptimizationsPatterns(patterns, solver);
 
-    GreedyRewriteConfig config;
-    config.listener = &listener;
-
-    if (failed(applyPatternsGreedily(op, std::move(patterns), config)))
+    if (failed(applyPatternsGreedily(
+            op, std::move(patterns),
+            GreedyRewriteConfig().setListener(&listener))))
       signalPassFailure();
   }
 };
@@ -520,13 +519,12 @@ struct IntRangeNarrowingPass final
     RewritePatternSet patterns(ctx);
     populateIntRangeNarrowingPatterns(patterns, solver, bitwidthsSupported);
 
-    GreedyRewriteConfig config;
     // We specifically need bottom-up traversal as cmpi pattern needs range
     // data, attached to its original argument values.
-    config.useTopDownTraversal = false;
-    config.listener = &listener;
-
-    if (failed(applyPatternsGreedily(op, std::move(patterns), config)))
+    if (failed(applyPatternsGreedily(
+            op, std::move(patterns),
+            GreedyRewriteConfig().setUseTopDownTraversal(false).setListener(
+                &listener))))
       signalPassFailure();
   }
 };
diff --git a/mlir/lib/Dialect/Bufferization/Pipelines/BufferizationPipelines.cpp b/mlir/lib/Dialect/Bufferization/Pipelines/BufferizationPipelines.cpp
index b184265f464d1..d82e3a46dbff2 100644
--- a/mlir/lib/Dialect/Bufferization/Pipelines/BufferizationPipelines.cpp
+++ b/mlir/lib/Dialect/Bufferization/Pipelines/BufferizationPipelines.cpp
@@ -20,7 +20,9 @@
 
 void mlir::bufferization::buildBufferDeallocationPipeline(
     OpPassManager &pm, const BufferDeallocationPipelineOptions &options) {
-  pm.addPass(memref::createExpandReallocPass(/*emitDeallocs=*/false));
+  memref::ExpandReallocPassOptions expandAllocPassOptions{
+      /*emitDeallocs=*/false};
+  pm.addPass(memref::createExpandReallocPass(expandAllocPassOptions));
   pm.addPass(createCanonicalizerPass());
 
   OwnershipBasedBufferDeallocationPassOptions deallocationOptions{
diff --git a/mlir/lib/Dialect/Bufferization/Transforms/BufferDeallocationSimplification.cpp b/mlir/lib/Dialect/Bufferization/Transforms/BufferDeallocationSimplification.cpp
index 35f86a62ae592..c5fab80ecaa08 100644
--- a/mlir/lib/Dialect/Bufferization/Transforms/BufferDeallocationSimplification.cpp
+++ b/mlir/lib/Dialect/Bufferization/Transforms/BufferDeallocationSimplification.cpp
@@ -463,15 +463,15 @@ struct BufferDeallocationSimplificationPass
                  SplitDeallocWhenNotAliasingAnyOther,
                  RetainedMemrefAliasingAlwaysDeallocatedMemref>(&getContext(),
                                                                 analysis);
+
+    populateDeallocOpCanonicalizationPatterns(patterns, &getContext());
     // We don't want that the block structure changes invalidating the
-    // `BufferOriginAnalysis` so we apply the rewrites witha `Normal` level of
+    // `BufferOriginAnalysis` so we apply the rewrites with `Normal` level of
     // region simplification
-    GreedyRewriteConfig config;
-    config.enableRegionSimplification = GreedySimplifyRegionLevel::Normal;
-    populateDeallocOpCanonicalizationPatterns(patterns, &getContext());
-
-    if (failed(
-            applyPatternsGreedily(getOperation(), std::move(patterns), config)))
+    if (failed(applyPatternsGreedily(
+            getOperation(), std::move(patterns),
+            GreedyRewriteConfig().setRegionSimplificationLevel(
+                GreedySimplifyRegionLevel::Normal))))
       signalPassFailure();
   }
 };
diff --git a/mlir/lib/Dialect/GPU/CMakeLists.txt b/mlir/lib/Dialect/GPU/CMakeLists.txt
index 013311ec027da..be6492a22f34f 100644
--- a/mlir/lib/Dialect/GPU/CMakeLists.txt
+++ b/mlir/lib/Dialect/GPU/CMakeLists.txt
@@ -53,6 +53,7 @@ add_mlir_dialect_library(MLIRGPUTransforms
 
   LINK_LIBS PUBLIC
   MLIRAffineUtils
+  MLIRAMDGPUDialect
   MLIRArithDialect
   MLIRAsyncDialect
   MLIRBufferizationDialect
@@ -70,6 +71,7 @@ add_mlir_dialect_library(MLIRGPUTransforms
   MLIRSideEffectInterfaces
   MLIRSPIRVTarget
   MLIRSupport
+  MLIRROCDLDialect
   MLIRROCDLTarget
   MLIRTransformUtils
   MLIRVectorDialect
diff --git a/mlir/lib/Dialect/GPU/Transforms/SubgroupReduceLowering.cpp b/mlir/lib/Dialect/GPU/Transforms/SubgroupReduceLowering.cpp
index 43eff3eddcc49..74face4291353 100644
--- a/mlir/lib/Dialect/GPU/Transforms/SubgroupReduceLowering.cpp
+++ b/mlir/lib/Dialect/GPU/Transforms/SubgroupReduceLowering.cpp
@@ -10,15 +10,19 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "mlir/Dialect/AMDGPU/IR/AMDGPUDialect.h"
+#include "mlir/Dialect/AMDGPU/Utils/Chipset.h"
 #include "mlir/Dialect/Arith/IR/Arith.h"
 #include "mlir/Dialect/GPU/IR/GPUDialect.h"
 #include "mlir/Dialect/GPU/Transforms/Passes.h"
 #include "mlir/Dialect/GPU/Utils/GPUUtils.h"
+#include "mlir/Dialect/LLVMIR/ROCDLDialect.h"
 #include "mlir/Dialect/Vector/IR/VectorOps.h"
 #include "mlir/IR/BuiltinTypes.h"
 #include "mlir/IR/Location.h"
 #include "mlir/IR/PatternMatch.h"
 #include "mlir/IR/TypeUtilities.h"
+#include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/FormatVariadic.h"
 #include "llvm/Support/MathExtras.h"
 #include <cassert>
@@ -362,6 +366,163 @@ struct VectorSubgroupReduceToShuffles final
   unsigned shuffleBitwidth = 0;
   bool matchClustered = false;
 };
+
+static FailureOr<Value>
+createSubgroupDPPReduction(PatternRewriter &rewriter, gpu::SubgroupReduceOp op,
+                           Value input, gpu::AllReduceOperation mode,
+                           const ClusterInfo &ci, amdgpu::Chipset chipset) {
+  Location loc = op.getLoc();
+  Value dpp;
+  Value res = input;
+  constexpr int allRows = 0xf;
+  constexpr int allBanks = 0xf;
+  const bool boundCtrl = true;
+  if (ci.clusterSize >= 2) {
+    // Perform reduction between all lanes N <-> N+1.
+    dpp = rewriter.create<amdgpu::DPPOp>(
+        loc, res.getType(), res, res, amdgpu::DPPPerm::quad_perm,
+        rewriter.getI32ArrayAttr({1, 0, 3, 2}), allRows, allBanks, boundCtrl);
+    res = vector::makeArithReduction(rewriter, loc,
+                                     gpu::convertReductionKind(mode), res, dpp);
+  }
+
+  if (ci.clusterSize >= 4) {
+    // Perform reduction between all lanes N <-> N+2.
+    dpp = rewriter.create<amdgpu::DPPOp>(
+        loc, res.getType(), res, res, amdgpu::DPPPerm::quad_perm,
+        rewriter.getI32ArrayAttr({2, 3, 0, 1}), allRows, allBanks, boundCtrl);
+    res = vector::makeArithReduction(rewriter, loc,
+                                     gpu::convertReductionKind(mode), res, dpp);
+  }
+  if (ci.clusterSize >= 8) {
+    // Perform reduction between all lanes N <-> 7-N,
+    // e.g lane[0] <-> lane[7], lane[1] <-> lane[6]..., lane[3] <-> lane[4].
+    dpp = rewriter.create<amdgpu::DPPOp>(
+        loc, res.getType(), res, res, amdgpu::DPPPerm::row_half_mirror,
+        rewriter.getUnitAttr(), allRows, allBanks, boundCtrl);
+    res = vector::makeArithReduction(rewriter, loc,
+                                     gpu::convertReductionKind(mode), res, dpp);
+  }
+  if (ci.clusterSize >= 16) {
+    // Perform reduction between all lanes N <-> 15-N,
+    // e.g lane[0] <-> lane[15], lane[1] <-> lane[14]..., lane[7] <-> lane[8].
+    dpp = rewriter.create<amdgpu::DPPOp>(
+        loc, res.getType(), res, res, amdgpu::DPPPerm::row_mirror,
+        rewriter.getUnitAttr(), allRows, allBanks, boundCtrl);
+    res = vector::makeArithReduction(rewriter, loc,
+                                     gpu::convertReductionKind(mode), res, dpp);
+  }
+  if (ci.clusterSize >= 32) {
+    if (chipset.majorVersion <= 9) {
+      // Broadcast last value from each row to next row.
+      // Use row mask to avoid polluting rows 1 and 3.
+      dpp = rewriter.create<amdgpu::DPPOp>(
+          loc, res.getType(), res, res, amdgpu::DPPPerm::row_bcast_15,
+          rewriter.getUnitAttr(), 0xa, allBanks,
+          /*bound_ctrl*/ false);
+      res = vector::makeArithReduction(
+          rewriter, loc, gpu::convertReductionKind(mode), res, dpp);
+    } else if (chipset.majorVersion <= 12) {
+      // Use a permute lane to cross rows (row 1 <-> row 0, row 3 <-> row 2).
+      Value uint32Max = rewriter.create<arith::ConstantOp>(
+          loc, rewriter.getI32Type(), rewriter.getI32IntegerAttr(-1));
+      dpp = rewriter.create<ROCDL::PermlaneX16Op>(loc, res.getType(), res, res,
+                                                  uint32Max, uint32Max,
+                                                  /*fi=*/true,
+                                                  /*bound_ctrl=*/false);
+      res = vector::makeArithReduction(
+          rewriter, loc, gpu::convertReductionKind(mode), res, dpp);
+      if (ci.subgroupSize == 32) {
+        Value lane0 = rewriter.create<arith::ConstantOp>(
+            loc, rewriter.getI32Type(), rewriter.getI32IntegerAttr(0));
+        res =
+            rewriter.create<ROCDL::ReadlaneOp>(loc, res.getType(), res, lane0);
+      }
+    } else {
+      return rewriter.notifyMatchFailure(
+          op, "Subgroup reduce lowering to DPP not currently supported for "
+              "this device.");
+    }
+  }
+  if (ci.clusterSize >= 64) {
+    if (chipset.majorVersion <= 9) {
+      // Broadcast 31st lane value to rows 2 and 3.
+      // Use row mask to avoid polluting rows 0 and 1.
+      dpp = rewriter.create<amdgpu::DPPOp>(
+          loc, res.getType(), res, res, amdgpu::DPPPerm::row_bcast_31,
+          rewriter.getUnitAttr(), 0xc, allBanks,
+          /*bound_ctrl*/ false);
+
+    } else if (chipset.majorVersion <= 12) {
+      // Assume reduction across 32 lanes has been done.
+      // Perform final reduction manually by summing values in lane 0 and
+      // lane 32.
+      Value lane0 = rewriter.create<arith::ConstantOp>(
+          loc, rewriter.getI32Type(), rewriter.getI32IntegerAttr(0));
+      Value lane32 = rewriter.create<arith::ConstantOp>(
+          loc, rewriter.getI32Type(), rewriter.getI32IntegerAttr(32));
+      dpp = rewriter.create<ROCDL::ReadlaneOp>(loc, res.getType(), res, lane32);
+      res = rewriter.create<ROCDL::ReadlaneOp>(loc, res.getType(), res, lane0);
+    } else {
+      return rewriter.notifyMatchFailure(
+          op, "Subgroup reduce lowering to DPP not currently supported for "
+              "this device.");
+    }
+    res = vector::makeArithReduction(rewriter, loc,
+                                     gpu::convertReductionKind(mode), res, dpp);
+  }
+  assert(res.getType() == input.getType());
+  return res;
+}
+
+/// Collect a set of patterns to lower `gpu.subgroup_reduce` into `amdgpu.dpp`
+/// ops over scalar types. Assumes that the subgroup has
+/// `subgroupSize` lanes. Applicable only to AMD GPUs.
+struct ScalarSubgroupReduceToDPP final
+    : OpRewritePattern<gpu::SubgroupReduceOp> {
+  ScalarSubgroupReduceToDPP(MLIRContext *ctx, unsigned subgroupSize,
+                            bool matchClustered, amdgpu::Chipset chipset,
+                            PatternBenefit benefit)
+      : OpRewritePattern(ctx, benefit), subgroupSize(subgroupSize),
+        matchClustered(matchClustered), chipset(chipset) {}
+
+  LogicalResult matchAndRewrite(gpu::SubgroupReduceOp op,
+                                PatternRewriter &rewriter) const override {
+    if (op.getClusterSize().has_value() != matchClustered) {
+      return rewriter.notifyMatchFailure(
+          op, llvm::formatv("op is {0}clustered but pattern is configured to "
+                            "only match {1}clustered ops",
+                            matchClustered ? "non-" : "",
+                            matchClustered ? "" : "non-"));
+    }
+    auto ci = getAndValidateClusterInfo(op, subgroupSize);
+    if (failed(ci))
+      return failure();
+
+    if (ci->clusterStride != 1)
+      return rewriter.notifyMatchFailure(
+          op, "Subgroup reductions using DPP are currently only available for "
+              "clusters of contiguous lanes.");
+
+    Type valueTy = op.getType();
+    if (!valueTy.isIntOrFloat())
+      return rewriter.notifyMatchFailure(
+          op, "Value type is not a compatible scalar.");
+
+    FailureOr<Value> dpp = createSubgroupDPPReduction(
+        rewriter, op, op.getValue(), op.getOp(), *ci, chipset);
+    if (failed(dpp))
+      return failure();
+
+    rewriter.replaceOp(op, dpp.value());
+    return success();
+  }
+
+private:
+  unsigned subgroupSize = 0;
+  bool matchClustered = false;
+  amdgpu::Chipset chipset;
+};
 } // namespace
 
 void mlir::populateGpuBreakDownSubgroupReducePatterns(
@@ -372,6 +533,22 @@ void mlir::populateGpuBreakDownSubgroupReducePatterns(
   patterns.add<ScalarizeSingleElementReduce>(patterns.getContext(), benefit);
 }
 
+void mlir::populateGpuLowerSubgroupReduceToDPPPatterns(
+    RewritePatternSet &patterns, unsigned subgroupSize, amdgpu::Chipset chipset,
+    PatternBenefit benefit) {
+  patterns.add<ScalarSubgroupReduceToDPP>(patterns.getContext(), subgroupSize,
+                                          /*matchClustered=*/false, chipset,
+                                          benefit);
+}
+
+void mlir::populateGpuLowerClusteredSubgroupReduceToDPPPatterns(
+    RewritePatternSet &patterns, unsigned subgroupSize, amdgpu::Chipset chipset,
+    PatternBenefit benefit) {
+  patterns.add<ScalarSubgroupReduceToDPP>(patterns.getContext(), subgroupSize,
+                                          /*matchClustered=*/true, chipset,
+                                          benefit);
+}
+
 void mlir::populateGpuLowerSubgroupReduceToShufflePatterns(
     RewritePatternSet &patterns, unsigned subgroupSize,
     unsigned shuffleBitwidth, PatternBenefit benefit) {
diff --git a/mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp b/mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
index e4f9d6f987401..f3ebb8a565ea4 100644
--- a/mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
+++ b/mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
@@ -375,3 +375,13 @@ TargetFeaturesAttr TargetFeaturesAttr::featuresAt(Operation *op) {
   return parentFunction.getOperation()->getAttrOfType<TargetFeaturesAttr>(
       getAttributeName());
 }
+
+LogicalResult
+ModuleFlagAttr::verify(function_ref<InFlightDiagnostic()> emitError,
+                       LLVM::ModFlagBehavior flagBehavior, StringAttr key,
+                       Attribute value) {
+  if (!isa<IntegerAttr, StringAttr>(value))
+    return emitError()
+           << "only integer and string values are currently supported";
+  return success();
+}
diff --git a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
index 0022be84c212e..26c3ef1e8b8bf 100644
--- a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
+++ b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
@@ -1885,11 +1885,40 @@ OpFoldResult LLVM::ExtractValueOp::fold(FoldAdaptor adaptor) {
 
   auto insertValueOp = getContainer().getDefiningOp<InsertValueOp>();
   OpFoldResult result = {};
+  ArrayRef<int64_t> extractPos = getPosition();
+  bool switchedToInsertedValue = false;
   while (insertValueOp) {
-    if (getPosition() == insertValueOp.getPosition())
+    ArrayRef<int64_t> insertPos = insertValueOp.getPosition();
+    auto extractPosSize = extractPos.size();
+    auto insertPosSize = insertPos.size();
+
+    // Case 1: Exact match of positions.
+    if (extractPos == insertPos)
       return insertValueOp.getValue();
-    unsigned min =
-        std::min(getPosition().size(), insertValueOp.getPosition().size());
+
+    // Case 2: Insert position is a prefix of extract position. Continue
+    // traversal with the inserted value. Example:
+    // ```
+    // %0 = llvm.insertvalue %arg1, %undef[0] : !llvm.struct<(i32, i32, i32)>
+    // %1 = llvm.insertvalue %arg2, %0[1] : !llvm.struct<(i32, i32, i32)>
+    // %2 = llvm.insertvalue %arg3, %1[2] : !llvm.struct<(i32, i32, i32)>
+    // %3 = llvm.insertvalue %2, %foo[0]
+    //     : !llvm.struct<(struct<(i32, i32, i32)>, i64)>
+    // %4 = llvm.extractvalue %3[0, 0]
+    //     : !llvm.struct<(struct<(i32, i32, i32)>, i64)>
+    // ```
+    // In the above example, %4 is folded to %arg1.
+    if (extractPosSize > insertPosSize &&
+        extractPos.take_front(insertPosSize) == insertPos) {
+      insertValueOp = insertValueOp.getValue().getDefiningOp<InsertValueOp>();
+      extractPos = extractPos.drop_front(insertPosSize);
+      switchedToInsertedValue = true;
+      continue;
+    }
+
+    // Case 3: Try to continue the traversal with the container value.
+    unsigned min = std::min(extractPosSize, insertPosSize);
+
     // If one is fully prefix of the other, stop propagating back as it will
     // miss dependencies. For instance, %3 should not fold to %f0 in the
     // following example:
@@ -1900,15 +1929,17 @@ OpFoldResult LLVM::ExtractValueOp::fold(FoldAdaptor adaptor) {
     //     !llvm.array<4 x !llvm.array<4 x f32>>
     //   %3 = llvm.extractvalue %2[0, 0] : !llvm.array<4 x !llvm.array<4 x f32>>
     // ```
-    if (getPosition().take_front(min) ==
-        insertValueOp.getPosition().take_front(min))
+    if (extractPos.take_front(min) == insertPos.take_front(min))
       return result;
-
     // If neither a prefix, nor the exact position, we can extract out of the
     // value being inserted into. Moreover, we can try again if that operand
     // is itself an insertvalue expression.
-    getContainerMutable().assign(insertValueOp.getContainer());
-    result = getResult();
+    if (!switchedToInsertedValue) {
+      // Do not swap out the container operand if we decided earlier to
+      // continue the traversal with the inserted value (Case 2).
+      getContainerMutable().assign(insertValueOp.getContainer());
+      result = getResult();
+    }
     insertValueOp = insertValueOp.getContainer().getDefiningOp<InsertValueOp>();
   }
   return result;
diff --git a/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp b/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
index c90ebe4487ca4..b20e6050fb4f8 100644
--- a/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
+++ b/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
@@ -3587,9 +3587,9 @@ transform::VectorizeChildrenAndApplyPatternsOp::applyToOne(
   vector::populateVectorStepLoweringPatterns(patterns);
 
   TrackingListener listener(state, *this);
-  GreedyRewriteConfig config;
-  config.listener = &listener;
-  if (failed(applyPatternsGreedily(target, std::move(patterns), config)))
+  if (failed(
+          applyPatternsGreedily(target, std::move(patterns),
+                                GreedyRewriteConfig().setListener(&listener))))
     return emitDefaultDefiniteFailure(target);
 
   results.push_back(target);
diff --git a/mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp b/mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp
index bf70597d5ddfe..62d016b87d627 100644
--- a/mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp
+++ b/mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp
@@ -2327,10 +2327,9 @@ struct LinalgElementwiseOpFusionPass
     // Add constant folding patterns.
     populateConstantFoldLinalgOperations(patterns, defaultControlFn);
 
-    // Use TopDownTraversal for compile time reasons
-    GreedyRewriteConfig grc;
-    grc.useTopDownTraversal = true;
-    (void)applyPatternsGreedily(op, std::move(patterns), grc);
+    // Use TopDownTraversal for compile time reasons.
+    (void)applyPatternsGreedily(op, std::move(patterns),
+                                GreedyRewriteConfig().setUseTopDownTraversal());
   }
 };
 
diff --git a/mlir/lib/Dialect/MemRef/Transforms/ExpandOps.cpp b/mlir/lib/Dialect/MemRef/Transforms/ExpandOps.cpp
index 83683c7e617bf..020aabd9db6df 100644
--- a/mlir/lib/Dialect/MemRef/Transforms/ExpandOps.cpp
+++ b/mlir/lib/Dialect/MemRef/Transforms/ExpandOps.cpp
@@ -24,7 +24,7 @@
 
 namespace mlir {
 namespace memref {
-#define GEN_PASS_DEF_EXPANDOPS
+#define GEN_PASS_DEF_EXPANDOPSPASS
 #include "mlir/Dialect/MemRef/Transforms/Passes.h.inc"
 } // namespace memref
 } // namespace mlir
@@ -130,7 +130,7 @@ struct MemRefReshapeOpConverter : public OpRewritePattern<memref::ReshapeOp> {
   }
 };
 
-struct ExpandOpsPass : public memref::impl::ExpandOpsBase<ExpandOpsPass> {
+struct ExpandOpsPass : public memref::impl::ExpandOpsPassBase<ExpandOpsPass> {
   void runOnOperation() override {
     MLIRContext &ctx = getContext();
 
@@ -161,7 +161,3 @@ void mlir::memref::populateExpandOpsPatterns(RewritePatternSet &patterns) {
   patterns.add<AtomicRMWOpConverter, MemRefReshapeOpConverter>(
       patterns.getContext());
 }
-
-std::unique_ptr<Pass> mlir::memref::createExpandOpsPass() {
-  return std::make_unique<ExpandOpsPass>();
-}
diff --git a/mlir/lib/Dialect/MemRef/Transforms/ExpandRealloc.cpp b/mlir/lib/Dialect/MemRef/Transforms/ExpandRealloc.cpp
index dcc5eac916d03..7475d442b7b9a 100644
--- a/mlir/lib/Dialect/MemRef/Transforms/ExpandRealloc.cpp
+++ b/mlir/lib/Dialect/MemRef/Transforms/ExpandRealloc.cpp
@@ -16,7 +16,7 @@
 
 namespace mlir {
 namespace memref {
-#define GEN_PASS_DEF_EXPANDREALLOC
+#define GEN_PASS_DEF_EXPANDREALLOCPASS
 #include "mlir/Dialect/MemRef/Transforms/Passes.h.inc"
 } // namespace memref
 } // namespace mlir
@@ -142,11 +142,9 @@ struct ExpandReallocOpPattern : public OpRewritePattern<memref::ReallocOp> {
 };
 
 struct ExpandReallocPass
-    : public memref::impl::ExpandReallocBase<ExpandReallocPass> {
-  ExpandReallocPass(bool emitDeallocs)
-      : memref::impl::ExpandReallocBase<ExpandReallocPass>() {
-    this->emitDeallocs.setValue(emitDeallocs);
-  }
+    : public memref::impl::ExpandReallocPassBase<ExpandReallocPass> {
+  using Base::Base;
+
   void runOnOperation() override {
     MLIRContext &ctx = getContext();
 
@@ -169,7 +167,3 @@ void mlir::memref::populateExpandReallocPatterns(RewritePatternSet &patterns,
                                                  bool emitDeallocs) {
   patterns.add<ExpandReallocOpPattern>(patterns.getContext(), emitDeallocs);
 }
-
-std::unique_ptr<Pass> mlir::memref::createExpandReallocPass(bool emitDeallocs) {
-  return std::make_unique<ExpandReallocPass>(emitDeallocs);
-}
diff --git a/mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp b/mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
index b69cbabe0dde9..2d9372ef1c609 100644
--- a/mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
+++ b/mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
@@ -28,7 +28,7 @@
 
 namespace mlir {
 namespace memref {
-#define GEN_PASS_DEF_EXPANDSTRIDEDMETADATA
+#define GEN_PASS_DEF_EXPANDSTRIDEDMETADATAPASS
 #include "mlir/Dialect/MemRef/Transforms/Passes.h.inc"
 } // namespace memref
 } // namespace mlir
@@ -1213,7 +1213,7 @@ void memref::populateResolveExtractStridedMetadataPatterns(
 namespace {
 
 struct ExpandStridedMetadataPass final
-    : public memref::impl::ExpandStridedMetadataBase<
+    : public memref::impl::ExpandStridedMetadataPassBase<
           ExpandStridedMetadataPass> {
   void runOnOperation() override;
 };
@@ -1225,7 +1225,3 @@ void ExpandStridedMetadataPass::runOnOperation() {
   memref::populateExpandStridedMetadataPatterns(patterns);
   (void)applyPatternsGreedily(getOperation(), std::move(patterns));
 }
-
-std::unique_ptr<Pass> memref::createExpandStridedMetadataPass() {
-  return std::make_unique<ExpandStridedMetadataPass>();
-}
diff --git a/mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp b/mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
index 8e927a60087fc..ec55b9e561914 100644
--- a/mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
+++ b/mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
@@ -35,7 +35,7 @@
 
 namespace mlir {
 namespace memref {
-#define GEN_PASS_DEF_FOLDMEMREFALIASOPS
+#define GEN_PASS_DEF_FOLDMEMREFALIASOPSPASS
 #include "mlir/Dialect/MemRef/Transforms/Passes.h.inc"
 } // namespace memref
 } // namespace mlir
@@ -848,7 +848,7 @@ void memref::populateFoldMemRefAliasOpPatterns(RewritePatternSet &patterns) {
 namespace {
 
 struct FoldMemRefAliasOpsPass final
-    : public memref::impl::FoldMemRefAliasOpsBase<FoldMemRefAliasOpsPass> {
+    : public memref::impl::FoldMemRefAliasOpsPassBase<FoldMemRefAliasOpsPass> {
   void runOnOperation() override;
 };
 
@@ -859,7 +859,3 @@ void FoldMemRefAliasOpsPass::runOnOperation() {
   memref::populateFoldMemRefAliasOpPatterns(patterns);
   (void)applyPatternsGreedily(getOperation(), std::move(patterns));
 }
-
-std::unique_ptr<Pass> memref::createFoldMemRefAliasOpsPass() {
-  return std::make_unique<FoldMemRefAliasOpsPass>();
-}
diff --git a/mlir/lib/Dialect/MemRef/Transforms/NormalizeMemRefs.cpp b/mlir/lib/Dialect/MemRef/Transforms/NormalizeMemRefs.cpp
index 95fed04a7864e..7abd9d17f5aa1 100644
--- a/mlir/lib/Dialect/MemRef/Transforms/NormalizeMemRefs.cpp
+++ b/mlir/lib/Dialect/MemRef/Transforms/NormalizeMemRefs.cpp
@@ -21,7 +21,7 @@
 
 namespace mlir {
 namespace memref {
-#define GEN_PASS_DEF_NORMALIZEMEMREFS
+#define GEN_PASS_DEF_NORMALIZEMEMREFSPASS
 #include "mlir/Dialect/MemRef/Transforms/Passes.h.inc"
 } // namespace memref
 } // namespace mlir
@@ -40,7 +40,7 @@ namespace {
 /// to call a non-normalizable function, we treat that function as
 /// non-normalizable as well. We assume external functions to be normalizable.
 struct NormalizeMemRefs
-    : public memref::impl::NormalizeMemRefsBase<NormalizeMemRefs> {
+    : public memref::impl::NormalizeMemRefsPassBase<NormalizeMemRefs> {
   void runOnOperation() override;
   void normalizeFuncOpMemRefs(func::FuncOp funcOp, ModuleOp moduleOp);
   bool areMemRefsNormalizable(func::FuncOp funcOp);
@@ -53,11 +53,6 @@ struct NormalizeMemRefs
 
 } // namespace
 
-std::unique_ptr<OperationPass<ModuleOp>>
-mlir::memref::createNormalizeMemRefsPass() {
-  return std::make_unique<NormalizeMemRefs>();
-}
-
 void NormalizeMemRefs::runOnOperation() {
   LLVM_DEBUG(llvm::dbgs() << "Normalizing Memrefs...\n");
   ModuleOp moduleOp = getOperation();
diff --git a/mlir/lib/Dialect/MemRef/Transforms/ResolveShapedTypeResultDims.cpp b/mlir/lib/Dialect/MemRef/Transforms/ResolveShapedTypeResultDims.cpp
index dfcbaeb15ae5f..89a3895d06ba5 100644
--- a/mlir/lib/Dialect/MemRef/Transforms/ResolveShapedTypeResultDims.cpp
+++ b/mlir/lib/Dialect/MemRef/Transforms/ResolveShapedTypeResultDims.cpp
@@ -25,8 +25,8 @@
 
 namespace mlir {
 namespace memref {
-#define GEN_PASS_DEF_RESOLVERANKEDSHAPETYPERESULTDIMS
-#define GEN_PASS_DEF_RESOLVESHAPEDTYPERESULTDIMS
+#define GEN_PASS_DEF_RESOLVERANKEDSHAPETYPERESULTDIMSPASS
+#define GEN_PASS_DEF_RESOLVESHAPEDTYPERESULTDIMSPASS
 #include "mlir/Dialect/MemRef/Transforms/Passes.h.inc"
 } // namespace memref
 } // namespace mlir
@@ -164,13 +164,13 @@ struct IterArgsToInitArgs : public OpRewritePattern<tensor::DimOp> {
 
 namespace {
 struct ResolveRankedShapeTypeResultDimsPass final
-    : public memref::impl::ResolveRankedShapeTypeResultDimsBase<
+    : public memref::impl::ResolveRankedShapeTypeResultDimsPassBase<
           ResolveRankedShapeTypeResultDimsPass> {
   void runOnOperation() override;
 };
 
 struct ResolveShapedTypeResultDimsPass final
-    : public memref::impl::ResolveShapedTypeResultDimsBase<
+    : public memref::impl::ResolveShapedTypeResultDimsPassBase<
           ResolveShapedTypeResultDimsPass> {
   void runOnOperation() override;
 };
@@ -206,11 +206,3 @@ void ResolveShapedTypeResultDimsPass::runOnOperation() {
   if (failed(applyPatternsGreedily(getOperation(), std::move(patterns))))
     return signalPassFailure();
 }
-
-std::unique_ptr<Pass> memref::createResolveShapedTypeResultDimsPass() {
-  return std::make_unique<ResolveShapedTypeResultDimsPass>();
-}
-
-std::unique_ptr<Pass> memref::createResolveRankedShapeTypeResultDimsPass() {
-  return std::make_unique<ResolveRankedShapeTypeResultDimsPass>();
-}
diff --git a/mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp b/mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
index 91862d2e17d71..7edf19689d2e1 100644
--- a/mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
+++ b/mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
@@ -1438,10 +1438,10 @@ SliceTrackingListener::insertAndApplyPatterns(ArrayRef<Operation *> ops) {
   if (!patterns)
     return success();
 
-  GreedyRewriteConfig config;
-  config.listener = this;
-  config.strictMode = GreedyRewriteStrictness::ExistingAndNewOps;
-  return applyOpPatternsGreedily(ops, patterns.value(), config);
+  return applyOpPatternsGreedily(
+      ops, patterns.value(),
+      GreedyRewriteConfig().setListener(this).setStrictness(
+          GreedyRewriteStrictness::ExistingAndNewOps));
 }
 
 void SliceTrackingListener::notifyOperationInserted(
diff --git a/mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp b/mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
index 19b9af146f4a4..811f03abb3461 100644
--- a/mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
+++ b/mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
@@ -1353,9 +1353,9 @@ LogicalResult mlir::spirv::unrollVectorsInSignatures(Operation *op) {
   // We only want to apply signature conversion once to the existing func ops.
   // Without specifying strictMode, the greedy pattern rewriter will keep
   // looking for newly created func ops.
-  GreedyRewriteConfig config;
-  config.strictMode = GreedyRewriteStrictness::ExistingOps;
-  return applyPatternsGreedily(op, std::move(patterns), config);
+  return applyPatternsGreedily(op, std::move(patterns),
+                               GreedyRewriteConfig().setStrictness(
+                                   GreedyRewriteStrictness::ExistingOps));
 }
 
 LogicalResult mlir::spirv::unrollVectorsInFuncBodies(Operation *op) {
diff --git a/mlir/lib/Dialect/Tosa/IR/TosaOps.cpp b/mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
index 8b4f6ef0d0980..751ae785bda6f 100644
--- a/mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
+++ b/mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
@@ -428,6 +428,150 @@ static LogicalResult verifyConvOpModes(T op) {
   return success();
 }
 
+//===----------------------------------------------------------------------===//
+// ERROR_IF functions.
+// ERROR_IF is a predicate that must set an error if the condition holds.
+//===----------------------------------------------------------------------===//
+
+template <typename T>
+static LogicalResult verifyConvOpErrorIf(T op) {
+  llvm::ArrayRef<int64_t> padding = op.getPad();
+  if (llvm::any_of(padding, [](int64_t p) { return p < 0; }))
+    return op.emitOpError("expect all padding values to be >= 0, got ")
+           << padding;
+
+  llvm::ArrayRef<int64_t> strides = op.getStride();
+  if (llvm::any_of(strides, [](int64_t s) { return s < 1; }))
+    return op.emitOpError("expect all stride values to be >= 1, got ")
+           << strides;
+
+  llvm::ArrayRef<int64_t> dilations = op.getDilation();
+  if (llvm::any_of(dilations, [](int64_t d) { return d < 1; }))
+    return op.emitOpError("expect all dilation values to be >= 1, got ")
+           << dilations;
+
+  const RankedTensorType outputType =
+      llvm::dyn_cast<RankedTensorType>(op.getOutput().getType());
+  if (!outputType)
+    // Skip following checks if output is not ranked
+    return success();
+
+  const RankedTensorType inputType =
+      llvm::dyn_cast<RankedTensorType>(op.getInput().getType());
+  const RankedTensorType weightType =
+      llvm::dyn_cast<RankedTensorType>(op.getWeight().getType());
+
+  if (inputType && weightType) {
+    const auto verifyOutputSize =
+        [&op](const int64_t inputSize, const int64_t kernelSize,
+              const int64_t outputSize, const int64_t padBefore,
+              const int64_t padAfter, const int64_t stride,
+              const int64_t dilation, const llvm::StringRef dimName,
+              const llvm::StringRef dimAxis,
+              const llvm::StringRef padBeforeName,
+              const llvm::StringRef padAfterName) -> LogicalResult {
+      if (inputSize == ShapedType::kDynamic ||
+          kernelSize == ShapedType::kDynamic)
+        return success();
+
+      // ERROR_IF: O != idiv_check(I - 1 + pa + pb - (K - 1) * d, s) + 1
+
+      const std::optional<int64_t> calculatedOutSizeMinusOne = idivCheck(
+          inputSize - 1 + padBefore + padAfter - (kernelSize - 1) * dilation,
+          stride);
+      if (!calculatedOutSizeMinusOne.has_value())
+        return op.emitOpError("expected input_")
+               << dimName << " - 1 + pad_" << padBeforeName << " + pad_"
+               << padAfterName << " - (kernel_" << dimName
+               << " - 1) * dilation_" << dimAxis
+               << " to be wholly divisible by stride_" << dimAxis << ", got ("
+               << inputSize << " - 1 + " << padBefore << " + " << padAfter
+               << " - (" << kernelSize << " - 1) * " << dilation << ") / "
+               << stride;
+
+      const int64_t calculatedOutSize = calculatedOutSizeMinusOne.value() + 1;
+      if (outputSize != ShapedType::kDynamic && calculatedOutSize != outputSize)
+        return op.emitOpError("calculated output ")
+               << dimName << " did not match expected: "
+               << "calculated=" << calculatedOutSize
+               << ", expected=" << outputSize;
+
+      return success();
+    };
+
+    // input = [_,IH,IW,_], weight = [_,KH,KW,_], output = [_,OH,OW,_]
+    if constexpr (std::is_same<T, tosa::Conv2DOp>::value) {
+      if (failed(verifyOutputSize(
+              inputType.getDimSize(1), weightType.getDimSize(1),
+              outputType.getDimSize(1), padding[0], padding[1], strides[0],
+              dilations[0], "height", "y", "top", "bottom")))
+        return failure();
+
+      if (failed(verifyOutputSize(
+              inputType.getDimSize(2), weightType.getDimSize(2),
+              outputType.getDimSize(2), padding[2], padding[3], strides[1],
+              dilations[1], "width", "x", "left", "right")))
+        return failure();
+    }
+
+    // input = [_,IH,IW,_], weight = [KH,KW,_,_], output = [_,OH,OW,_]
+    if constexpr (std::is_same<T, tosa::DepthwiseConv2DOp>::value) {
+      if (failed(verifyOutputSize(
+              inputType.getDimSize(1), weightType.getDimSize(0),
+              outputType.getDimSize(1), padding[0], padding[1], strides[0],
+              dilations[0], "height", "y", "top", "bottom")))
+        return failure();
+
+      if (failed(verifyOutputSize(
+              inputType.getDimSize(2), weightType.getDimSize(1),
+              outputType.getDimSize(2), padding[2], padding[3], strides[1],
+              dilations[1], "width", "x", "left", "right")))
+        return failure();
+    }
+
+    // input = [_,ID,IH,IW,_], weight = [_,KD,KH,KW,_], output = [_,OD,OH,OW,_]
+    if constexpr (std::is_same<T, tosa::Conv3DOp>::value) {
+      if (failed(verifyOutputSize(
+              inputType.getDimSize(1), weightType.getDimSize(1),
+              outputType.getDimSize(1), padding[0], padding[1], strides[0],
+              dilations[0], "depth", "d", "front", "back")))
+        return failure();
+
+      if (failed(verifyOutputSize(
+              inputType.getDimSize(2), weightType.getDimSize(2),
+              outputType.getDimSize(2), padding[2], padding[3], strides[1],
+              dilations[1], "height", "y", "top", "bottom")))
+        return failure();
+
+      if (failed(verifyOutputSize(
+              inputType.getDimSize(3), weightType.getDimSize(3),
+              outputType.getDimSize(3), padding[4], padding[5], strides[2],
+              dilations[2], "width", "x", "left", "right")))
+        return failure();
+    }
+  }
+
+  const RankedTensorType biasType =
+      llvm::dyn_cast<RankedTensorType>(op.getBias().getType());
+  if (!biasType)
+    // Skip following checks if bias is not ranked
+    return success();
+
+  const int64_t biasChannels = biasType.getDimSize(0);
+  const int64_t outputChannels = outputType.getDimSize(3);
+  if (biasChannels == ShapedType::kDynamic ||
+      outputChannels == ShapedType::kDynamic)
+    // Skip following checks if biasChannels or outputChannels is dynamic dim
+    return success();
+
+  if (biasChannels != outputChannels && biasChannels != 1)
+    return op.emitOpError(
+               "bias channels expected to be equal to output channels (")
+           << outputChannels << ") or 1, got " << biasChannels;
+
+  return success();
+}
+
 // verify that inType and outType have same element types
 template <typename T>
 static LogicalResult verifySameElementTypes(T op, Type inType, Type outType) {
@@ -1178,6 +1322,25 @@ LogicalResult tosa::ConcatOp::verify() {
                  << " on operands 0 and " << operandNum;
       }
     }
+
+    // ERROR_IF(axis_sum != shape[axis]);
+    int64_t axisSum = 0;
+    for (const auto &input : inputList) {
+      const ShapeAdaptor inputShape(input.getType());
+      if (inputShape.isDynamicDim(axis)) {
+        // make axisSum negative to indicate invalid value
+        axisSum = -1;
+        break;
+      }
+      axisSum += inputShape.getDimSize(axis);
+    }
+    const ShapeAdaptor outputShape(outType);
+    if (axisSum >= 0 && outputShape.hasRank() &&
+        !outputShape.isDynamicDim(axis) &&
+        axisSum != outputShape.getDimSize(axis))
+      return emitOpError("requires sum of axis dimensions of input1 "
+                         "equal to output axis dimension, got ")
+             << axisSum << " and " << outputShape.getDimSize(axis);
   }
 
   return success();
@@ -1884,7 +2047,8 @@ static LogicalResult verifyZeroPoint(tosa::RescaleOp op, Value zpVal,
       return op.emitOpError()
              << "expect " << tensorName << "_zp of 0, got " << zp;
     }
-    if (zpElemType.isInteger(16) && tensorUnsigned && zp != 32768) {
+    if (zpElemType.isInteger(16) && tensorUnsigned &&
+        zp != static_cast<int16_t>(32768)) {
       return op.emitOpError() << "expect " << tensorName
                               << "_zp of 0 or 32768 for unsigned int16 "
                               << tensorName << ", got " << zp;
@@ -2586,99 +2750,9 @@ LogicalResult Conv2DOp::inferReturnTypeComponents(
 }
 
 LogicalResult Conv2DOp::verify() {
-  if (verifyConvOp(*this).failed() || verifyConvOpModes(*this).failed())
+  if (verifyConvOp(*this).failed() || verifyConvOpModes(*this).failed() ||
+      verifyConvOpErrorIf(*this).failed())
     return failure();
-
-  llvm::ArrayRef<int64_t> padding = getPad();
-  if (llvm::any_of(padding, [](int64_t p) { return p < 0; }))
-    return emitOpError("expect all padding values to be >= 0, got ") << padding;
-
-  llvm::ArrayRef<int64_t> strides = getStride();
-  if (llvm::any_of(strides, [](int64_t s) { return s < 1; }))
-    return emitOpError("expect all stride values to be >= 1, got ") << strides;
-
-  llvm::ArrayRef<int64_t> dilations = getDilation();
-  if (llvm::any_of(dilations, [](int64_t d) { return d < 1; }))
-    return emitOpError("expect all dilation values to be >= 1, got ")
-           << dilations;
-
-  const RankedTensorType outputType =
-      llvm::dyn_cast<RankedTensorType>(getOutput().getType());
-  if (!outputType)
-    // Skip following checks if output is not ranked
-    return success();
-
-  const RankedTensorType inputType =
-      llvm::dyn_cast<RankedTensorType>(getInput().getType());
-  const RankedTensorType weightType =
-      llvm::dyn_cast<RankedTensorType>(getWeight().getType());
-
-  if (inputType && weightType) {
-    const auto verifyOutputSize =
-        [this](const int64_t inputSize, const int64_t kernelSize,
-               const int64_t outputSize, const int64_t padBefore,
-               const int64_t padAfter, const int64_t stride,
-               const int64_t dilation, const llvm::StringRef dimName,
-               const llvm::StringRef dimAxis,
-               const llvm::StringRef padBeforeName,
-               const llvm::StringRef padAfterName) -> LogicalResult {
-      if (inputSize == ShapedType::kDynamic ||
-          kernelSize == ShapedType::kDynamic)
-        return success();
-
-      const std::optional<int64_t> calculatedOutSizeMinusOne = idivCheck(
-          inputSize - 1 + padBefore + padAfter - (kernelSize - 1) * dilation,
-          stride);
-      if (!calculatedOutSizeMinusOne.has_value())
-        return emitOpError("expected input_")
-               << dimName << " - 1 + pad_" << padBeforeName << " + pad_"
-               << padAfterName << " - (kernel_" << dimName
-               << " - 1) * dilation_" << dimAxis
-               << " to be wholly divisible by stride_" << dimAxis << ", got ("
-               << inputSize << " - 1 + " << padBefore << " + " << padAfter
-               << " - (" << kernelSize << " - 1) * " << dilation << ") / "
-               << stride;
-
-      const int64_t calculatedOutSize = calculatedOutSizeMinusOne.value() + 1;
-      if (outputSize != ShapedType::kDynamic && calculatedOutSize != outputSize)
-        return emitOpError("calculated output ")
-               << dimName << " did not match expected: "
-               << "calculated=" << calculatedOutSize
-               << ", expected=" << outputSize;
-
-      return success();
-    };
-
-    if (failed(verifyOutputSize(
-            inputType.getDimSize(1), weightType.getDimSize(1),
-            outputType.getDimSize(1), padding[0], padding[1], strides[0],
-            dilations[0], "height", "y", "top", "bottom")))
-      return failure();
-
-    if (failed(verifyOutputSize(
-            inputType.getDimSize(2), weightType.getDimSize(2),
-            outputType.getDimSize(2), padding[2], padding[3], strides[1],
-            dilations[1], "width", "x", "left", "right")))
-      return failure();
-  }
-
-  const RankedTensorType biasType =
-      llvm::dyn_cast<RankedTensorType>(getBias().getType());
-  if (!biasType)
-    // Skip following checks if bias is not ranked
-    return success();
-
-  const int64_t biasChannels = biasType.getDimSize(0);
-  const int64_t outputChannels = outputType.getDimSize(3);
-  if (biasChannels == ShapedType::kDynamic ||
-      outputChannels == ShapedType::kDynamic)
-    // Skip following checks if biasChannels or outputChannels is dynamic dim
-    return success();
-
-  if (biasChannels != outputChannels && biasChannels != 1)
-    return emitOpError(
-               "bias channels expected to be equal to output channels (")
-           << outputChannels << ") or 1, got " << biasChannels;
   return success();
 }
 
@@ -2753,7 +2827,8 @@ LogicalResult Conv3DOp::inferReturnTypeComponents(
 }
 
 LogicalResult Conv3DOp::verify() {
-  if (verifyConvOp(*this).failed() || verifyConvOpModes(*this).failed())
+  if (verifyConvOp(*this).failed() || verifyConvOpModes(*this).failed() ||
+      verifyConvOpErrorIf(*this).failed())
     return failure();
   return success();
 }
@@ -2863,7 +2938,8 @@ LogicalResult DepthwiseConv2DOp::inferReturnTypeComponents(
 }
 
 LogicalResult DepthwiseConv2DOp::verify() {
-  if (verifyConvOp(*this).failed() || verifyConvOpModes(*this).failed())
+  if (verifyConvOp(*this).failed() || verifyConvOpModes(*this).failed() ||
+      verifyConvOpErrorIf(*this).failed())
     return failure();
   return success();
 }
diff --git a/mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp b/mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
index 8f62253796175..3938c3731c47f 100644
--- a/mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
+++ b/mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
@@ -226,6 +226,12 @@ LogicalResult ProfileInfoDepot::populateProfileInfo(tosa::VariableOp op) {
   return failure();
 }
 
+template <>
+LogicalResult ProfileInfoDepot::populateProfileInfo(tosa::VariableWriteOp op) {
+  addValue(op.getInput1());
+  return success();
+}
+
 template <>
 LogicalResult ProfileInfoDepot::populateProfileInfo(tosa::IfOp op) {
   addValue(op.getCondition());
@@ -280,6 +286,7 @@ LogicalResult ProfileInfoDepot::populatationDispatch(Operation *op) {
   POPULATE_PROFILE_INFO_CUSTOM(Rescale)
   POPULATE_PROFILE_INFO_CUSTOM(MatMul)
   POPULATE_PROFILE_INFO_CUSTOM(Variable)
+  POPULATE_PROFILE_INFO_CUSTOM(VariableWrite)
   POPULATE_PROFILE_INFO_CUSTOM(If)
   POPULATE_PROFILE_INFO_CUSTOM(While)
 
@@ -334,7 +341,6 @@ LogicalResult ProfileInfoDepot::populatationDispatch(Operation *op) {
   POPULATE_PROFILE_INFO_COMMON(Reverse)
   POPULATE_PROFILE_INFO_COMMON(Identity)
   POPULATE_PROFILE_INFO_COMMON(VariableRead)
-  POPULATE_PROFILE_INFO_COMMON(VariableWrite)
 
   // Type Invariant Extension, a capability extension that is independent
   // of the data type, meaning any compatible type can be used. No type
diff --git a/mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp b/mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
index ef9d27f8df0ad..baa202833e285 100644
--- a/mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
+++ b/mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
@@ -767,7 +767,7 @@ inline bool CompatibleTypes(const mlir::Type &type,
 
 bool TosaValidation::CheckVariable(Operation *op) {
   if (isa<mlir::tosa::VariableOp>(op)) {
-    auto nameAttr = cast<mlir::StringAttr>(op->getAttr("name"));
+    mlir::StringAttr nameAttr = cast<mlir::StringAttr>(op->getAttr("name"));
 
     if (variablesMap.count(nameAttr)) {
       op->emitOpError() << "name has already been declared";
@@ -786,8 +786,7 @@ bool TosaValidation::CheckVariable(Operation *op) {
 bool TosaValidation::CheckVariableReadOrWrite(Operation *op) {
   if (isa<mlir::tosa::VariableReadOp>(op) ||
       isa<mlir::tosa::VariableWriteOp>(op)) {
-    auto nameAttr = cast<mlir::StringAttr>(op->getAttr("name"));
-
+    mlir::StringAttr nameAttr = cast<mlir::StringAttr>(op->getAttr("name"));
     if (!variablesMap.count(nameAttr)) {
       op->emitOpError() << "name has not been declared";
       return false;
diff --git a/mlir/lib/Dialect/Transform/IR/TransformOps.cpp b/mlir/lib/Dialect/Transform/IR/TransformOps.cpp
index 4fe89f3f7fb9e..84d339a985c38 100644
--- a/mlir/lib/Dialect/Transform/IR/TransformOps.cpp
+++ b/mlir/lib/Dialect/Transform/IR/TransformOps.cpp
@@ -394,16 +394,16 @@ DiagnosedSilenceableFailure transform::ApplyPatternsOp::applyToOne(
 
   // Configure the GreedyPatternRewriteDriver.
   GreedyRewriteConfig config;
-  config.listener =
-      static_cast<RewriterBase::Listener *>(rewriter.getListener());
+  config.setListener(
+      static_cast<RewriterBase::Listener *>(rewriter.getListener()));
   FrozenRewritePatternSet frozenPatterns(std::move(patterns));
 
-  config.maxIterations = getMaxIterations() == static_cast<uint64_t>(-1)
-                             ? GreedyRewriteConfig::kNoLimit
-                             : getMaxIterations();
-  config.maxNumRewrites = getMaxNumRewrites() == static_cast<uint64_t>(-1)
+  config.setMaxIterations(getMaxIterations() == static_cast<uint64_t>(-1)
                               ? GreedyRewriteConfig::kNoLimit
-                              : getMaxNumRewrites();
+                              : getMaxIterations());
+  config.setMaxNumRewrites(getMaxNumRewrites() == static_cast<uint64_t>(-1)
+                               ? GreedyRewriteConfig::kNoLimit
+                               : getMaxNumRewrites());
 
   // Apply patterns and CSE repetitively until a fixpoint is reached. If no CSE
   // was requested, apply the greedy pattern rewrite only once. (The greedy
diff --git a/mlir/lib/Dialect/Vector/IR/VectorOps.cpp b/mlir/lib/Dialect/Vector/IR/VectorOps.cpp
index 368259b38b153..df56c68c65cf1 100644
--- a/mlir/lib/Dialect/Vector/IR/VectorOps.cpp
+++ b/mlir/lib/Dialect/Vector/IR/VectorOps.cpp
@@ -151,13 +151,39 @@ static bool isSupportedCombiningKind(CombiningKind combiningKind,
   return false;
 }
 
-AffineMap mlir::vector::getTransferMinorIdentityMap(ShapedType shapedType,
-                                                    VectorType vectorType) {
-  int64_t elementVectorRank = 0;
+/// Returns the number of dimensions of the `shapedType` that participate in the
+/// vector transfer, effectively the rank of the vector dimensions within the
+/// `shapedType`. This is calculated by taking the rank of the `vectorType`
+/// being transferred and subtracting the rank of the `shapedType`'s element
+/// type if it's also a vector.
+///
+/// This is used to determine the number of minor dimensions for identity maps
+/// in vector transfers.
+///
+/// For example, given a transfer operation involving `shapedType` and
+/// `vectorType`:
+///
+///   - shapedType = tensor<10x20xf32>, vectorType = vector<2x4xf32>
+///     - shapedType.getElementType() = f32 (rank 0)
+///     - vectorType.getRank() = 2
+///     - Result = 2 - 0 = 2
+///
+///   - shapedType = tensor<10xvector<20xf32>>, vectorType = vector<20xf32>
+///     - shapedType.getElementType() = vector<20xf32> (rank 1)
+///     - vectorType.getRank() = 1
+///     - Result = 1 - 1 = 0
+static unsigned getRealVectorRank(ShapedType shapedType,
+                                  VectorType vectorType) {
+  unsigned elementVectorRank = 0;
   VectorType elementVectorType =
       llvm::dyn_cast<VectorType>(shapedType.getElementType());
   if (elementVectorType)
     elementVectorRank += elementVectorType.getRank();
+  return vectorType.getRank() - elementVectorRank;
+}
+
+AffineMap mlir::vector::getTransferMinorIdentityMap(ShapedType shapedType,
+                                                    VectorType vectorType) {
   // 0-d transfers are to/from tensor<t>/memref<t> and vector<1xt>.
   // TODO: replace once we have 0-d vectors.
   if (shapedType.getRank() == 0 &&
@@ -166,7 +192,7 @@ AffineMap mlir::vector::getTransferMinorIdentityMap(ShapedType shapedType,
         /*numDims=*/0, /*numSymbols=*/0,
         getAffineConstantExpr(0, shapedType.getContext()));
   return AffineMap::getMinorIdentityMap(
-      shapedType.getRank(), vectorType.getRank() - elementVectorRank,
+      shapedType.getRank(), getRealVectorRank(shapedType, vectorType),
       shapedType.getContext());
 }
 
@@ -2019,8 +2045,9 @@ static Value extractInsertFoldConstantOp(OpType op, AdaptorType adaptor,
     Value position = dynamicPosition[index++];
     if (auto attr = mlir::dyn_cast_if_present<IntegerAttr>(positionAttr)) {
       int64_t value = attr.getInt();
-      // Do not fold if the value is out of bounds.
-      if (value >= 0 && value < vectorShape[i]) {
+      // Do not fold if the value is out of bounds (-1 signifies a poison
+      // value rather than OOB index).
+      if (value >= -1 && value < vectorShape[i]) {
         staticPosition[i] = attr.getInt();
         opChange = true;
         continue;
@@ -4234,6 +4261,10 @@ ParseResult TransferReadOp::parse(OpAsmParser &parser, OperationState &result) {
   Attribute permMapAttr = result.attributes.get(permMapAttrName);
   AffineMap permMap;
   if (!permMapAttr) {
+    if (shapedType.getRank() < getRealVectorRank(shapedType, vectorType))
+      return parser.emitError(typesLoc,
+                              "expected a custom permutation_map when "
+                              "rank(source) != rank(destination)");
     permMap = getTransferMinorIdentityMap(shapedType, vectorType);
     result.attributes.set(permMapAttrName, AffineMapAttr::get(permMap));
   } else {
@@ -4649,6 +4680,10 @@ ParseResult TransferWriteOp::parse(OpAsmParser &parser,
   auto permMapAttr = result.attributes.get(permMapAttrName);
   AffineMap permMap;
   if (!permMapAttr) {
+    if (shapedType.getRank() < getRealVectorRank(shapedType, vectorType))
+      return parser.emitError(typesLoc,
+                              "expected a custom permutation_map when "
+                              "rank(source) != rank(destination)");
     permMap = getTransferMinorIdentityMap(shapedType, vectorType);
     result.attributes.set(permMapAttrName, AffineMapAttr::get(permMap));
   } else {
diff --git a/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp b/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
index 8d4dcb2b27bf9..a560aa1b1e680 100644
--- a/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
+++ b/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
@@ -593,10 +593,19 @@ struct ConvertVectorStore final : OpConversionPattern<vector::StoreOp> {
     auto origElements = valueToStore.getType().getNumElements();
     // Note, per-element-alignment was already verified above.
     bool isDivisibleInSize = origElements % emulatedPerContainerElem == 0;
+    // Do the trailing dim for source and destination match? If yes, then the
+    // corresponding index must be 0.
+    // FIXME: There's no way to tell for dynamic shapes, so we should bail out.
+    // However, that makes some tests fail, so we need to audit first.
+    auto trailingDim = op.getBase().getType().getShape().back();
+    bool trailingDimsMatch =
+        ShapedType::isDynamic(trailingDim) || trailingDim == origElements;
 
     auto stridedMetadata =
         rewriter.create<memref::ExtractStridedMetadataOp>(loc, op.getBase());
 
+    // FIXME: ATM, we do not test cases where offsets, sizes, or strides are
+    // non-zero. As such, this is not needed.
     OpFoldResult linearizedIndices;
     memref::LinearizedMemRefInfo linearizedInfo;
     std::tie(linearizedInfo, linearizedIndices) =
@@ -608,8 +617,9 @@ struct ConvertVectorStore final : OpConversionPattern<vector::StoreOp> {
             getAsOpFoldResult(adaptor.getIndices()));
 
     std::optional<int64_t> foldedNumFrontPadElems =
-        isDivisibleInSize ? 0
-                          : getConstantIntValue(linearizedInfo.intraDataOffset);
+        (isDivisibleInSize && trailingDimsMatch)
+            ? 0
+            : getConstantIntValue(linearizedInfo.intraDataOffset);
 
     if (!foldedNumFrontPadElems) {
       return rewriter.notifyMatchFailure(
@@ -619,15 +629,38 @@ struct ConvertVectorStore final : OpConversionPattern<vector::StoreOp> {
 
     auto memrefBase = cast<MemRefValue>(adaptor.getBase());
 
-    // Conditions when atomic RMWs are not needed:
+    // RMWs are not needed when:
+    //  * no _partial_ stores are required.
+    // A partial store is defined as a store in which only a part of the
+    // container element is overwritten, e.g.
+    //
+    //    Dest before (8 bits)
+    //        +----------+
+    //        | 11000000 |
+    //        +----------+
+    //
+    //    Dest after storing 0xF at offset 4 (in bits)
+    //        +----------+
+    //        | 11001111 |
+    //        +----------+
+    //
+    // At a higher level, this translats to:
     // 1. The source vector size (in bits) is a multiple of byte size.
-    // 2. The address of the store is aligned to the emulated width boundary.
+    // 2. The address of the store is aligned to the container type width
+    //    boundary.
+    //
+    // EXAMPLE 1:
+    //  Requires partial store:
+    //    vector.store %arg0, %0[%c3] : memref<13xi2>, vector<4xi2>
     //
-    // For example, to store a vector<4xi2> to <13xi2> at offset 4, does not
-    // need unaligned emulation because the store address is aligned and the
-    // source is a whole byte.
-    bool emulationRequiresPartialStores =
-        !isDivisibleInSize || *foldedNumFrontPadElems != 0;
+    // EXAMPLE 2:
+    //  Does not require a partial store:
+    //    vector.store %arg0, %0[%c4] : memref<13xi2>, vector<4xi2>
+    //
+    // TODO: Take linearizedInfo.linearizedOffset into account. This is
+    // currently not needed/used/exercised as all our tests set offset to 0.
+    bool emulationRequiresPartialStores = *foldedNumFrontPadElems != 0;
+
     if (!emulationRequiresPartialStores) {
       // Basic case: storing full bytes.
       auto numElements = origElements / emulatedPerContainerElem;
diff --git a/mlir/lib/Dialect/X86Vector/IR/CMakeLists.txt b/mlir/lib/Dialect/X86Vector/IR/CMakeLists.txt
index d24617f037b13..5499d93d5f924 100644
--- a/mlir/lib/Dialect/X86Vector/IR/CMakeLists.txt
+++ b/mlir/lib/Dialect/X86Vector/IR/CMakeLists.txt
@@ -9,6 +9,7 @@ add_mlir_dialect_library(MLIRX86VectorDialect
 
   LINK_LIBS PUBLIC
   MLIRIR
+  MLIRLLVMCommonConversion
   MLIRLLVMDialect
   MLIRSideEffectInterfaces
   )
diff --git a/mlir/lib/Dialect/X86Vector/IR/X86VectorDialect.cpp b/mlir/lib/Dialect/X86Vector/IR/X86VectorDialect.cpp
index 5bb4dcfd60d83..f5e5070c74f8f 100644
--- a/mlir/lib/Dialect/X86Vector/IR/X86VectorDialect.cpp
+++ b/mlir/lib/Dialect/X86Vector/IR/X86VectorDialect.cpp
@@ -31,6 +31,26 @@ void x86vector::X86VectorDialect::initialize() {
       >();
 }
 
+static SmallVector<Value>
+getMemrefBuffPtr(Location loc, ::mlir::TypedValue<::mlir::MemRefType> memrefVal,
+                 RewriterBase &rewriter,
+                 const LLVMTypeConverter &typeConverter) {
+  SmallVector<Value> operands;
+  auto opType = memrefVal.getType();
+
+  Type llvmStructType = typeConverter.convertType(opType);
+  Value llvmStruct =
+      rewriter
+          .create<UnrealizedConversionCastOp>(loc, llvmStructType, memrefVal)
+          .getResult(0);
+  MemRefDescriptor memRefDescriptor(llvmStruct);
+
+  Value ptr = memRefDescriptor.bufferPtr(rewriter, loc, typeConverter, opType);
+  operands.push_back(ptr);
+
+  return operands;
+}
+
 LogicalResult x86vector::MaskCompressOp::verify() {
   if (getSrc() && getConstantSrc())
     return emitError("cannot use both src and constant_src");
@@ -45,8 +65,8 @@ LogicalResult x86vector::MaskCompressOp::verify() {
   return success();
 }
 
-SmallVector<Value>
-x86vector::MaskCompressOp::getIntrinsicOperands(RewriterBase &rewriter) {
+SmallVector<Value> x86vector::MaskCompressOp::getIntrinsicOperands(
+    RewriterBase &rewriter, const LLVMTypeConverter &typeConverter) {
   auto loc = getLoc();
 
   auto opType = getA().getType();
@@ -64,7 +84,8 @@ x86vector::MaskCompressOp::getIntrinsicOperands(RewriterBase &rewriter) {
 }
 
 SmallVector<Value>
-x86vector::DotOp::getIntrinsicOperands(RewriterBase &rewriter) {
+x86vector::DotOp::getIntrinsicOperands(RewriterBase &rewriter,
+                                       const LLVMTypeConverter &typeConverter) {
   SmallVector<Value> operands(getOperands());
   // Dot product of all elements, broadcasted to all elements.
   Value scale =
@@ -74,5 +95,22 @@ x86vector::DotOp::getIntrinsicOperands(RewriterBase &rewriter) {
   return operands;
 }
 
+SmallVector<Value> x86vector::BcstBF16ToPackedF32Op::getIntrinsicOperands(
+    RewriterBase &rewriter, const LLVMTypeConverter &typeConverter) {
+  return getMemrefBuffPtr(getLoc(), getA(), rewriter, typeConverter);
+}
+
+SmallVector<Value>
+x86vector::CvtPackedOddIndexedBF16ToF32Op::getIntrinsicOperands(
+    RewriterBase &rewriter, const LLVMTypeConverter &typeConverter) {
+  return getMemrefBuffPtr(getLoc(), getA(), rewriter, typeConverter);
+}
+
+SmallVector<Value>
+x86vector::CvtPackedEvenIndexedBF16ToF32Op::getIntrinsicOperands(
+    RewriterBase &rewriter, const LLVMTypeConverter &typeConverter) {
+  return getMemrefBuffPtr(getLoc(), getA(), rewriter, typeConverter);
+}
+
 #define GET_OP_CLASSES
 #include "mlir/Dialect/X86Vector/X86Vector.cpp.inc"
diff --git a/mlir/lib/Dialect/X86Vector/Transforms/LegalizeForLLVMExport.cpp b/mlir/lib/Dialect/X86Vector/Transforms/LegalizeForLLVMExport.cpp
index c0c7f61f55f88..d2297554a1012 100644
--- a/mlir/lib/Dialect/X86Vector/Transforms/LegalizeForLLVMExport.cpp
+++ b/mlir/lib/Dialect/X86Vector/Transforms/LegalizeForLLVMExport.cpp
@@ -96,8 +96,8 @@ struct OneToOneIntrinsicOpConversion
   LogicalResult matchAndRewrite(x86vector::OneToOneIntrinsicOp op,
                                 PatternRewriter &rewriter) const override {
     return intrinsicRewrite(op, rewriter.getStringAttr(op.getIntrinsicName()),
-                            op.getIntrinsicOperands(rewriter), typeConverter,
-                            rewriter);
+                            op.getIntrinsicOperands(rewriter, typeConverter),
+                            typeConverter, rewriter);
   }
 
 private:
@@ -114,7 +114,8 @@ void mlir::populateX86VectorLegalizeForLLVMExportPatterns(
 
 void mlir::configureX86VectorLegalizeForExportTarget(
     LLVMConversionTarget &target) {
-  target.addIllegalOp<MaskCompressOp, MaskRndScaleOp, MaskScaleFOp,
-                      Vp2IntersectOp, DotBF16Op, CvtPackedF32ToBF16Op, RsqrtOp,
-                      DotOp>();
+  target.addIllegalOp<
+      MaskCompressOp, MaskRndScaleOp, MaskScaleFOp, Vp2IntersectOp, DotBF16Op,
+      CvtPackedF32ToBF16Op, CvtPackedEvenIndexedBF16ToF32Op,
+      CvtPackedOddIndexedBF16ToF32Op, BcstBF16ToPackedF32Op, RsqrtOp, DotOp>();
 }
diff --git a/mlir/lib/Reducer/ReductionTreePass.cpp b/mlir/lib/Reducer/ReductionTreePass.cpp
index 7292752c712ae..549e4f2bd813b 100644
--- a/mlir/lib/Reducer/ReductionTreePass.cpp
+++ b/mlir/lib/Reducer/ReductionTreePass.cpp
@@ -62,11 +62,11 @@ static void applyPatterns(Region &region,
   // before that transform.
   for (Operation *op : opsInRange) {
     // `applyOpPatternsGreedily` with folding returns whether the op is
-    // convered. Omit it because we don't have expectation this reduction will
+    // converted. Omit it because we don't have expectation this reduction will
     // be success or not.
-    GreedyRewriteConfig config;
-    config.strictMode = GreedyRewriteStrictness::ExistingOps;
-    (void)applyOpPatternsGreedily(op, patterns, config);
+    (void)applyOpPatternsGreedily(op, patterns,
+                                  GreedyRewriteConfig().setStrictness(
+                                      GreedyRewriteStrictness::ExistingOps));
   }
 
   if (eraseOpNotInRange)
diff --git a/mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp b/mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
index 7038b5d73d266..e816a3e218452 100644
--- a/mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
+++ b/mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
@@ -16,6 +16,7 @@
 #include "mlir/Support/LLVM.h"
 #include "mlir/Target/LLVMIR/ModuleTranslation.h"
 
+#include "llvm/ADT/TypeSwitch.h"
 #include "llvm/IR/IRBuilder.h"
 #include "llvm/IR/InlineAsm.h"
 #include "llvm/IR/MDBuilder.h"
@@ -273,10 +274,25 @@ static void convertLinkerOptionsOp(ArrayAttr options,
 static void convertModuleFlagsOp(ArrayAttr flags, llvm::IRBuilderBase &builder,
                                  LLVM::ModuleTranslation &moduleTranslation) {
   llvm::Module *llvmModule = moduleTranslation.getLLVMModule();
-  for (auto flagAttr : flags.getAsRange<ModuleFlagAttr>())
+  for (auto flagAttr : flags.getAsRange<ModuleFlagAttr>()) {
+    llvm::Metadata *valueMetadata =
+        llvm::TypeSwitch<Attribute, llvm::Metadata *>(flagAttr.getValue())
+            .Case<StringAttr>([&](auto strAttr) {
+              return llvm::MDString::get(builder.getContext(),
+                                         strAttr.getValue());
+            })
+            .Case<IntegerAttr>([&](auto intAttr) {
+              return llvm::ConstantAsMetadata::get(llvm::ConstantInt::get(
+                  llvm::Type::getInt32Ty(builder.getContext()),
+                  intAttr.getInt()));
+            })
+            .Default([](auto) { return nullptr; });
+
+    assert(valueMetadata && "expected valid metadata");
     llvmModule->addModuleFlag(
         convertModFlagBehaviorToLLVM(flagAttr.getBehavior()),
-        flagAttr.getKey().getValue(), flagAttr.getValue());
+        flagAttr.getKey().getValue(), valueMetadata);
+  }
 }
 
 static LogicalResult
diff --git a/mlir/lib/Target/LLVMIR/ModuleImport.cpp b/mlir/lib/Target/LLVMIR/ModuleImport.cpp
index df7c8d6ea3579..3f80002c15ebb 100644
--- a/mlir/lib/Target/LLVMIR/ModuleImport.cpp
+++ b/mlir/lib/Target/LLVMIR/ModuleImport.cpp
@@ -525,18 +525,20 @@ LogicalResult ModuleImport::convertModuleFlagsMetadata() {
 
   SmallVector<Attribute> moduleFlags;
   for (const auto [behavior, key, val] : llvmModuleFlags) {
-    // Currently only supports most common: int constant values.
-    auto *constInt = llvm::mdconst::dyn_extract<llvm::ConstantInt>(val);
-    if (!constInt) {
+    Attribute valAttr = nullptr;
+    if (auto *constInt = llvm::mdconst::dyn_extract<llvm::ConstantInt>(val)) {
+      valAttr = builder.getI32IntegerAttr(constInt->getZExtValue());
+    } else if (auto *mdString = dyn_cast<llvm::MDString>(val)) {
+      valAttr = builder.getStringAttr(mdString->getString());
+    } else {
       emitWarning(mlirModule.getLoc())
-          << "unsupported module flag value: " << diagMD(val, llvmModule.get())
-          << ", only constant integer currently supported";
+          << "unsupported module flag value: " << diagMD(val, llvmModule.get());
       continue;
     }
 
     moduleFlags.push_back(builder.getAttr<ModuleFlagAttr>(
         convertModFlagBehaviorFromLLVM(behavior),
-        builder.getStringAttr(key->getString()), constInt->getZExtValue()));
+        builder.getStringAttr(key->getString()), valAttr));
   }
 
   if (!moduleFlags.empty())
diff --git a/mlir/lib/Transforms/Canonicalizer.cpp b/mlir/lib/Transforms/Canonicalizer.cpp
index 7ccd503fb0288..4b0ac28a03713 100644
--- a/mlir/lib/Transforms/Canonicalizer.cpp
+++ b/mlir/lib/Transforms/Canonicalizer.cpp
@@ -32,10 +32,10 @@ struct Canonicalizer : public impl::CanonicalizerBase<Canonicalizer> {
                 ArrayRef<std::string> disabledPatterns,
                 ArrayRef<std::string> enabledPatterns)
       : config(config) {
-    this->topDownProcessingEnabled = config.useTopDownTraversal;
-    this->enableRegionSimplification = config.enableRegionSimplification;
-    this->maxIterations = config.maxIterations;
-    this->maxNumRewrites = config.maxNumRewrites;
+    this->topDownProcessingEnabled = config.getUseTopDownTraversal();
+    this->regionSimplifyLevel = config.getRegionSimplificationLevel();
+    this->maxIterations = config.getMaxIterations();
+    this->maxNumRewrites = config.getMaxNumRewrites();
     this->disabledPatterns = disabledPatterns;
     this->enabledPatterns = enabledPatterns;
   }
@@ -44,10 +44,10 @@ struct Canonicalizer : public impl::CanonicalizerBase<Canonicalizer> {
   /// execution.
   LogicalResult initialize(MLIRContext *context) override {
     // Set the config from possible pass options set in the meantime.
-    config.useTopDownTraversal = topDownProcessingEnabled;
-    config.enableRegionSimplification = enableRegionSimplification;
-    config.maxIterations = maxIterations;
-    config.maxNumRewrites = maxNumRewrites;
+    config.setUseTopDownTraversal(topDownProcessingEnabled);
+    config.setRegionSimplificationLevel(regionSimplifyLevel);
+    config.setMaxIterations(maxIterations);
+    config.setMaxNumRewrites(maxNumRewrites);
 
     RewritePatternSet owningPatterns(context);
     for (auto *dialect : context->getLoadedDialects())
diff --git a/mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp b/mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
index 7c1cfd91f85e6..5a719200e0026 100644
--- a/mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
+++ b/mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
@@ -416,7 +416,8 @@ GreedyPatternRewriteDriver::GreedyPatternRewriteDriver(
       // clang-format off
       , expensiveChecks(
           /*driver=*/this,
-          /*topLevel=*/config.scope ? config.scope->getParentOp() : nullptr)
+          /*topLevel=*/config.getScope() ? config.getScope()->getParentOp()
+                                         : nullptr)
 // clang-format on
 #endif // MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS
 {
@@ -455,8 +456,8 @@ bool GreedyPatternRewriteDriver::processWorklist() {
   bool changed = false;
   int64_t numRewrites = 0;
   while (!worklist.empty() &&
-         (numRewrites < config.maxNumRewrites ||
-          config.maxNumRewrites == GreedyRewriteConfig::kNoLimit)) {
+         (numRewrites < config.getMaxNumRewrites() ||
+          config.getMaxNumRewrites() == GreedyRewriteConfig::kNoLimit)) {
     auto *op = worklist.pop();
 
     LLVM_DEBUG({
@@ -488,7 +489,7 @@ bool GreedyPatternRewriteDriver::processWorklist() {
     // infinite folding loop, as every constant op would be folded to an
     // Attribute and then immediately be rematerialized as a constant op, which
     // is then put on the worklist.
-    if (config.fold && !op->hasTrait<OpTrait::ConstantLike>()) {
+    if (config.isFoldingEnabled() && !op->hasTrait<OpTrait::ConstantLike>()) {
       SmallVector<OpFoldResult> foldResults;
       if (succeeded(op->fold(foldResults))) {
         LLVM_DEBUG(logResultWithLine("success", "operation was folded"));
@@ -574,21 +575,21 @@ bool GreedyPatternRewriteDriver::processWorklist() {
         logger.getOStream() << ")' {\n";
         logger.indent();
       });
-      if (config.listener)
-        config.listener->notifyPatternBegin(pattern, op);
+      if (RewriterBase::Listener *listener = config.getListener())
+        listener->notifyPatternBegin(pattern, op);
       return true;
     };
     function_ref<bool(const Pattern &)> canApply = canApplyCallback;
     auto onFailureCallback = [&](const Pattern &pattern) {
       LLVM_DEBUG(logResult("failure", "pattern failed to match"));
-      if (config.listener)
-        config.listener->notifyPatternEnd(pattern, failure());
+      if (RewriterBase::Listener *listener = config.getListener())
+        listener->notifyPatternEnd(pattern, failure());
     };
     function_ref<void(const Pattern &)> onFailure = onFailureCallback;
     auto onSuccessCallback = [&](const Pattern &pattern) {
       LLVM_DEBUG(logResult("success", "pattern applied successfully"));
-      if (config.listener)
-        config.listener->notifyPatternEnd(pattern, success());
+      if (RewriterBase::Listener *listener = config.getListener())
+        listener->notifyPatternEnd(pattern, success());
       return success();
     };
     function_ref<LogicalResult(const Pattern &)> onSuccess = onSuccessCallback;
@@ -596,7 +597,7 @@ bool GreedyPatternRewriteDriver::processWorklist() {
 #ifdef NDEBUG
     // Optimization: PatternApplicator callbacks are not needed when running in
     // optimized mode and without a listener.
-    if (!config.listener) {
+    if (!config.getListener()) {
       canApply = nullptr;
       onFailure = nullptr;
       onSuccess = nullptr;
@@ -604,8 +605,8 @@ bool GreedyPatternRewriteDriver::processWorklist() {
 #endif // NDEBUG
 
 #if MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS
-    if (config.scope) {
-      expensiveChecks.computeFingerPrints(config.scope->getParentOp());
+    if (config.getScope()) {
+      expensiveChecks.computeFingerPrints(config.getScope()->getParentOp());
     }
     auto clearFingerprints =
         llvm::make_scope_exit([&]() { expensiveChecks.clear(); });
@@ -640,7 +641,7 @@ void GreedyPatternRewriteDriver::addToWorklist(Operation *op) {
   do {
     ancestors.push_back(op);
     region = op->getParentRegion();
-    if (config.scope == region) {
+    if (config.getScope() == region) {
       // Scope (can be `nullptr`) was reached. Stop traveral and enqueue ops.
       for (Operation *op : ancestors)
         addSingleOpToWorklist(op);
@@ -652,20 +653,20 @@ void GreedyPatternRewriteDriver::addToWorklist(Operation *op) {
 }
 
 void GreedyPatternRewriteDriver::addSingleOpToWorklist(Operation *op) {
-  if (config.strictMode == GreedyRewriteStrictness::AnyOp ||
+  if (config.getStrictness() == GreedyRewriteStrictness::AnyOp ||
       strictModeFilteredOps.contains(op))
     worklist.push(op);
 }
 
 void GreedyPatternRewriteDriver::notifyBlockInserted(
     Block *block, Region *previous, Region::iterator previousIt) {
-  if (config.listener)
-    config.listener->notifyBlockInserted(block, previous, previousIt);
+  if (RewriterBase::Listener *listener = config.getListener())
+    listener->notifyBlockInserted(block, previous, previousIt);
 }
 
 void GreedyPatternRewriteDriver::notifyBlockErased(Block *block) {
-  if (config.listener)
-    config.listener->notifyBlockErased(block);
+  if (RewriterBase::Listener *listener = config.getListener())
+    listener->notifyBlockErased(block);
 }
 
 void GreedyPatternRewriteDriver::notifyOperationInserted(
@@ -674,9 +675,9 @@ void GreedyPatternRewriteDriver::notifyOperationInserted(
     logger.startLine() << "** Insert  : '" << op->getName() << "'(" << op
                        << ")\n";
   });
-  if (config.listener)
-    config.listener->notifyOperationInserted(op, previous);
-  if (config.strictMode == GreedyRewriteStrictness::ExistingAndNewOps)
+  if (RewriterBase::Listener *listener = config.getListener())
+    listener->notifyOperationInserted(op, previous);
+  if (config.getStrictness() == GreedyRewriteStrictness::ExistingAndNewOps)
     strictModeFilteredOps.insert(op);
   addToWorklist(op);
 }
@@ -686,8 +687,8 @@ void GreedyPatternRewriteDriver::notifyOperationModified(Operation *op) {
     logger.startLine() << "** Modified: '" << op->getName() << "'(" << op
                        << ")\n";
   });
-  if (config.listener)
-    config.listener->notifyOperationModified(op);
+  if (RewriterBase::Listener *listener = config.getListener())
+    listener->notifyOperationModified(op);
   addToWorklist(op);
 }
 
@@ -736,18 +737,18 @@ void GreedyPatternRewriteDriver::notifyOperationErased(Operation *op) {
   // the part of the IR that is taken into account for the "expensive checks".
   // A greedy pattern rewrite is not allowed to erase the parent op of the scope
   // region, as that would break the worklist handling and the expensive checks.
-  if (config.scope && config.scope->getParentOp() == op)
+  if (Region *scope = config.getScope(); scope->getParentOp() == op)
     llvm_unreachable(
         "scope region must not be erased during greedy pattern rewrite");
 #endif // NDEBUG
 
-  if (config.listener)
-    config.listener->notifyOperationErased(op);
+  if (RewriterBase::Listener *listener = config.getListener())
+    listener->notifyOperationErased(op);
 
   addOperandsToWorklist(op);
   worklist.remove(op);
 
-  if (config.strictMode != GreedyRewriteStrictness::AnyOp)
+  if (config.getStrictness() != GreedyRewriteStrictness::AnyOp)
     strictModeFilteredOps.erase(op);
 }
 
@@ -757,8 +758,8 @@ void GreedyPatternRewriteDriver::notifyOperationReplaced(
     logger.startLine() << "** Replace : '" << op->getName() << "'(" << op
                        << ")\n";
   });
-  if (config.listener)
-    config.listener->notifyOperationReplaced(op, replacement);
+  if (RewriterBase::Listener *listener = config.getListener())
+    listener->notifyOperationReplaced(op, replacement);
 }
 
 void GreedyPatternRewriteDriver::notifyMatchFailure(
@@ -768,8 +769,8 @@ void GreedyPatternRewriteDriver::notifyMatchFailure(
     reasonCallback(diag);
     logger.startLine() << "** Match Failure : " << diag.str() << "\n";
   });
-  if (config.listener)
-    config.listener->notifyMatchFailure(loc, reasonCallback);
+  if (RewriterBase::Listener *listener = config.getListener())
+    listener->notifyMatchFailure(loc, reasonCallback);
 }
 
 //===----------------------------------------------------------------------===//
@@ -800,7 +801,7 @@ RegionPatternRewriteDriver::RegionPatternRewriteDriver(
     const GreedyRewriteConfig &config, Region &region)
     : GreedyPatternRewriteDriver(ctx, patterns, config), region(region) {
   // Populate strict mode ops.
-  if (config.strictMode != GreedyRewriteStrictness::AnyOp) {
+  if (config.getStrictness() != GreedyRewriteStrictness::AnyOp) {
     region.walk([&](Operation *op) { strictModeFilteredOps.insert(op); });
   }
 }
@@ -829,8 +830,8 @@ LogicalResult RegionPatternRewriteDriver::simplify(bool *changed) && {
   MLIRContext *ctx = rewriter.getContext();
   do {
     // Check if the iteration limit was reached.
-    if (++iteration > config.maxIterations &&
-        config.maxIterations != GreedyRewriteConfig::kNoLimit)
+    if (++iteration > config.getMaxIterations() &&
+        config.getMaxIterations() != GreedyRewriteConfig::kNoLimit)
       break;
 
     // New iteration: start with an empty worklist.
@@ -849,16 +850,16 @@ LogicalResult RegionPatternRewriteDriver::simplify(bool *changed) && {
       return false;
     };
 
-    if (!config.useTopDownTraversal) {
+    if (!config.getUseTopDownTraversal()) {
       // Add operations to the worklist in postorder.
       region.walk([&](Operation *op) {
-        if (!config.cseConstants || !insertKnownConstant(op))
+        if (!config.isConstantCSEEnabled() || !insertKnownConstant(op))
           addToWorklist(op);
       });
     } else {
       // Add all nested operations to the worklist in preorder.
       region.walk<WalkOrder::PreOrder>([&](Operation *op) {
-        if (!config.cseConstants || !insertKnownConstant(op)) {
+        if (!config.isConstantCSEEnabled() || !insertKnownConstant(op)) {
           addToWorklist(op);
           return WalkResult::advance();
         }
@@ -875,11 +876,11 @@ LogicalResult RegionPatternRewriteDriver::simplify(bool *changed) && {
 
           // After applying patterns, make sure that the CFG of each of the
           // regions is kept up to date.
-          if (config.enableRegionSimplification !=
+          if (config.getRegionSimplificationLevel() !=
               GreedySimplifyRegionLevel::Disabled) {
             continueRewrites |= succeeded(simplifyRegions(
                 rewriter, region,
-                /*mergeBlocks=*/config.enableRegionSimplification ==
+                /*mergeBlocks=*/config.getRegionSimplificationLevel() ==
                     GreedySimplifyRegionLevel::Aggressive));
           }
         },
@@ -904,11 +905,11 @@ mlir::applyPatternsGreedily(Region &region,
          "patterns can only be applied to operations IsolatedFromAbove");
 
   // Set scope if not specified.
-  if (!config.scope)
-    config.scope = &region;
+  if (!config.getScope())
+    config.setScope(&region);
 
 #if MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS
-  if (failed(verify(config.scope->getParentOp())))
+  if (failed(verify(config.getScope()->getParentOp())))
     llvm::report_fatal_error(
         "greedy pattern rewriter input IR failed to verify");
 #endif // MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS
@@ -919,7 +920,7 @@ mlir::applyPatternsGreedily(Region &region,
   LogicalResult converged = std::move(driver).simplify(changed);
   LLVM_DEBUG(if (failed(converged)) {
     llvm::dbgs() << "The pattern rewrite did not converge after scanning "
-                 << config.maxIterations << " times\n";
+                 << config.getMaxIterations() << " times\n";
   });
   return converged;
 }
@@ -960,7 +961,7 @@ MultiOpPatternRewriteDriver::MultiOpPatternRewriteDriver(
     llvm::SmallDenseSet<Operation *, 4> *survivingOps)
     : GreedyPatternRewriteDriver(ctx, patterns, config),
       survivingOps(survivingOps) {
-  if (config.strictMode != GreedyRewriteStrictness::AnyOp)
+  if (config.getStrictness() != GreedyRewriteStrictness::AnyOp)
     strictModeFilteredOps.insert_range(ops);
 
   if (survivingOps) {
@@ -1024,22 +1025,22 @@ LogicalResult mlir::applyOpPatternsGreedily(
   }
 
   // Determine scope of rewrite.
-  if (!config.scope) {
+  if (!config.getScope()) {
     // Compute scope if none was provided. The scope will remain `nullptr` if
     // there is a top-level op among `ops`.
-    config.scope = findCommonAncestor(ops);
+    config.setScope(findCommonAncestor(ops));
   } else {
     // If a scope was provided, make sure that all ops are in scope.
 #ifndef NDEBUG
     bool allOpsInScope = llvm::all_of(ops, [&](Operation *op) {
-      return static_cast<bool>(config.scope->findAncestorOpInRegion(*op));
+      return static_cast<bool>(config.getScope()->findAncestorOpInRegion(*op));
     });
     assert(allOpsInScope && "ops must be within the specified scope");
 #endif // NDEBUG
   }
 
 #if MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS
-  if (config.scope && failed(verify(config.scope->getParentOp())))
+  if (config.getScope() && failed(verify(config.getScope()->getParentOp())))
     llvm::report_fatal_error(
         "greedy pattern rewriter input IR failed to verify");
 #endif // MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS
@@ -1054,7 +1055,7 @@ LogicalResult mlir::applyOpPatternsGreedily(
     *allErased = surviving.empty();
   LLVM_DEBUG(if (failed(converged)) {
     llvm::dbgs() << "The pattern rewrite did not converge after "
-                 << config.maxNumRewrites << " rewrites";
+                 << config.getMaxNumRewrites() << " rewrites";
   });
   return converged;
 }
diff --git a/mlir/python/mlir/_mlir_libs/_mlir/ir.pyi b/mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
index 1c8080c5d6d2e..6c5f91d757cdc 100644
--- a/mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
+++ b/mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
@@ -45,9 +45,8 @@ from __future__ import annotations
 import abc
 import collections
 from collections.abc import Callable, Sequence
-import io
 from pathlib import Path
-from typing import Any, BinaryIO, ClassVar, TypeVar, overload
+from typing import Any, BinaryIO, ClassVar, Literal, TypeVar, overload
 
 __all__ = [
     "AffineAddExpr",
@@ -196,6 +195,19 @@ class _OperationBase:
         Detaches the operation from its parent block.
         """
     def erase(self) -> None: ...
+
+    @overload
+    def get_asm(
+        binary: Literal[True],
+        large_elements_limit: int | None = None,
+        enable_debug_info: bool = False,
+        pretty_debug_info: bool = False,
+        print_generic_op_form: bool = False,
+        use_local_scope: bool = False,
+        assume_verified: bool = False,
+        skip_regions: bool = False,
+    ) -> bytes: ...
+    @overload
     def get_asm(
         self,
         binary: bool = False,
@@ -206,19 +218,14 @@ class _OperationBase:
         use_local_scope: bool = False,
         assume_verified: bool = False,
         skip_regions: bool = False,
-    ) -> io.BytesIO | io.StringIO:
+    ) -> str:
         """
-        Gets the assembly form of the operation with all options available.
+        Returns the assembly form of the operation.
 
-        Args:
-          binary: Whether to return a bytes (True) or str (False) object. Defaults to
-            False.
-          ... others ...: See the print() method for common keyword arguments for
-            configuring the printout.
-        Returns:
-          Either a bytes or str object, depending on the setting of the 'binary'
-          argument.
+        See the print() method for common keyword arguments for configuring
+        the output.
         """
+
     def move_after(self, other: _OperationBase) -> None:
         """
         Puts self immediately after the other operation in its parent block.
diff --git a/mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir b/mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
index 242772fe5cdcf..a737a8a05bae6 100644
--- a/mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
+++ b/mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
@@ -878,22 +878,22 @@ func.func @depthwise_conv2d_f16_f32_acc(%arg0 : tensor<1x7x5x3xf16>, %arg1 : ten
 // CHECK: #[[$MAP2:.+]] = affine_map<(d0, d1, d2, d3, d4) -> (d0, d1, d2, d3, d4)>
 
 // CHECK-LABEL: @conv3d_f32
-func.func @conv3d_f32(%input: tensor<1x49x48x47x27xf32>, %weights: tensor<28x3x4x5x27xf32>, %bias: tensor<28xf32>) -> () {
-  // CHECK-DAG:  %[[TRANSPOSE:.+]] = linalg.transpose ins(%arg1 : tensor<28x3x4x5x27xf32>) outs(%[[TRANSPOSEDINIT:.+]] : tensor<3x4x5x27x28xf32>) permutation = [1, 2, 3, 4, 0]
-  // CHECK-DAG:  %[[INIT:.+]] = tensor.empty() : tensor<1x47x45x43x28xf32>
+func.func @conv3d_f32(%input: tensor<1x49x48x47x27xf32>, %weights: tensor<43x3x4x5x27xf32>, %bias: tensor<43xf32>) -> () {
+  // CHECK-DAG:  %[[TRANSPOSE:.+]] = linalg.transpose ins(%arg1 : tensor<43x3x4x5x27xf32>) outs(%[[TRANSPOSEDINIT:.+]] : tensor<3x4x5x27x43xf32>) permutation = [1, 2, 3, 4, 0]
+  // CHECK-DAG:  %[[INIT:.+]] = tensor.empty() : tensor<1x47x45x43x43xf32>
   // CHECK:      %[[BROADCAST:.+]] = linalg.generic
   // CHECK-SAME: {indexing_maps = [#[[$MAP1]], #[[$MAP2]]], iterator_types = ["parallel", "parallel", "parallel", "parallel", "parallel"]}
-  // CHECK-SAME: ins(%arg2 : tensor<28xf32>) outs(%[[INIT]] : tensor<1x47x45x43x28xf32>) {
+  // CHECK-SAME: ins(%arg2 : tensor<43xf32>) outs(%[[INIT]] : tensor<1x47x45x43x43xf32>) {
   // CHECK:      ^bb0(%[[IN:.+]]: f32, %[[OUT:.+]]: f32):
   // CHECK:        linalg.yield %[[IN]] : f32
-  // CHECK:      } -> tensor<1x47x45x43x28xf32>
+  // CHECK:      } -> tensor<1x47x45x43x43xf32>
   // CHECK:      linalg.conv_3d_ndhwc_dhwcf
   // CHECK-SAME: {dilations = dense<1> : tensor<3xi64>, strides = dense<1> : tensor<3xi64>}
-  // CHECK-SAME: ins(%arg0, %[[TRANSPOSE]] : tensor<1x49x48x47x27xf32>, tensor<3x4x5x27x28xf32>)
-  // CHECK-SAME: outs(%[[BROADCAST]] : tensor<1x47x45x43x28xf32>) -> tensor<1x47x45x43x28xf32>
+  // CHECK-SAME: ins(%arg0, %[[TRANSPOSE]] : tensor<1x49x48x47x27xf32>, tensor<3x4x5x27x43xf32>)
+  // CHECK-SAME: outs(%[[BROADCAST]] : tensor<1x47x45x43x43xf32>) -> tensor<1x47x45x43x43xf32>
   %input_zp = "tosa.const"() <{values = dense<0.0> : tensor<1xf32>}> : () -> tensor<1xf32>
   %weight_zp = "tosa.const"() <{values = dense<0.0> : tensor<1xf32>}> : () -> tensor<1xf32>
-  %0 = tosa.conv3d %input, %weights, %bias, %input_zp, %weight_zp {acc_type = f32, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>, dilation = array<i64: 1, 1, 1>} : (tensor<1x49x48x47x27xf32>, tensor<28x3x4x5x27xf32>, tensor<28xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x47x45x43x28xf32>
+  %0 = tosa.conv3d %input, %weights, %bias, %input_zp, %weight_zp {acc_type = f32, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>, dilation = array<i64: 1, 1, 1>} : (tensor<1x49x48x47x27xf32>, tensor<43x3x4x5x27xf32>, tensor<43xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x47x45x43x43xf32>
   return
 }
 
@@ -919,40 +919,40 @@ func.func @conv3d_scalar_bias_f32(%input: tensor<1x49x48x47x27xf32>, %weights: t
 // CHECK: #[[$MAP2:.+]] = affine_map<(d0, d1, d2, d3, d4) -> (d0, d1, d2, d3, d4)>
 
 // CHECK-LABEL: @conv3d_i8
-func.func @conv3d_i8(%input: tensor<1x49x48x47x27xi8>, %weights: tensor<28x3x4x5x27xi8>, %bias: tensor<28xi32>) -> () {
-  // CHECK-DAG:  %[[TRANSPOSE:.+]] = linalg.transpose ins(%arg1 : tensor<28x3x4x5x27xi8>) outs(%[[TRANSPOSEDINIT:.+]] : tensor<3x4x5x27x28xi8>) permutation = [1, 2, 3, 4, 0]
-  // CHECK-DAG:  %[[INIT:.+]] = tensor.empty() : tensor<1x47x45x43x28xi32>
+func.func @conv3d_i8(%input: tensor<1x49x48x47x27xi8>, %weights: tensor<43x3x4x5x27xi8>, %bias: tensor<43xi32>) -> () {
+  // CHECK-DAG:  %[[TRANSPOSE:.+]] = linalg.transpose ins(%arg1 : tensor<43x3x4x5x27xi8>) outs(%[[TRANSPOSEDINIT:.+]] : tensor<3x4x5x27x43xi8>) permutation = [1, 2, 3, 4, 0]
+  // CHECK-DAG:  %[[INIT:.+]] = tensor.empty() : tensor<1x47x45x43x43xi32>
   // CHECK:      %[[BROADCAST:.+]] = linalg.generic
   // CHECK-SAME: {indexing_maps = [#[[$MAP1]], #[[$MAP2]]], iterator_types = ["parallel", "parallel", "parallel", "parallel", "parallel"]}
-  // CHECK-SAME: ins(%arg2 : tensor<28xi32>)
-  // CHECK-SAME: outs(%[[INIT]] : tensor<1x47x45x43x28xi32>) {
+  // CHECK-SAME: ins(%arg2 : tensor<43xi32>)
+  // CHECK-SAME: outs(%[[INIT]] : tensor<1x47x45x43x43xi32>) {
   // CHECK:      ^bb0(%[[IN:.+]]: i32, %[[OUT:.+]]: i32):
   // CHECK:        linalg.yield %[[IN]] : i32
-  // CHECK:      } -> tensor<1x47x45x43x28xi32>
+  // CHECK:      } -> tensor<1x47x45x43x43xi32>
   // CHECK:      %[[IZP:.+]] = arith.constant -128 : i32
   // CHECK:      %[[FZP:.+]] = arith.constant 42 : i32
   // CHECK:      linalg.conv_3d_ndhwc_dhwcf_q
   // CHECK-SAME: {dilations = dense<1> : tensor<3xi64>, strides = dense<1> : tensor<3xi64>}
-  // CHECK-SAME: ins(%arg0, %[[TRANSPOSE]], %[[IZP]], %[[FZP]] : tensor<1x49x48x47x27xi8>, tensor<3x4x5x27x28xi8>, i32, i32)
-  // CHECK-SAME: outs(%[[BROADCAST]] : tensor<1x47x45x43x28xi32>) -> tensor<1x47x45x43x28xi32>
+  // CHECK-SAME: ins(%arg0, %[[TRANSPOSE]], %[[IZP]], %[[FZP]] : tensor<1x49x48x47x27xi8>, tensor<3x4x5x27x43xi8>, i32, i32)
+  // CHECK-SAME: outs(%[[BROADCAST]] : tensor<1x47x45x43x43xi32>) -> tensor<1x47x45x43x43xi32>
 
   %input_zp = "tosa.const"() <{values = dense<-128> : tensor<1xi8>}> : () -> tensor<1xi8>
   %weight_zp = "tosa.const"() <{values = dense<42> : tensor<1xi8>}> : () -> tensor<1xi8>
-  %0 = tosa.conv3d %input, %weights, %bias, %input_zp, %weight_zp {acc_type = i32, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>, dilation = array<i64: 1, 1, 1>} : (tensor<1x49x48x47x27xi8>, tensor<28x3x4x5x27xi8>, tensor<28xi32>, tensor<1xi8>, tensor<1xi8>) -> tensor<1x47x45x43x28xi32>
+  %0 = tosa.conv3d %input, %weights, %bias, %input_zp, %weight_zp {acc_type = i32, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>, dilation = array<i64: 1, 1, 1>} : (tensor<1x49x48x47x27xi8>, tensor<43x3x4x5x27xi8>, tensor<43xi32>, tensor<1xi8>, tensor<1xi8>) -> tensor<1x47x45x43x43xi32>
   return
 }
 
 // -----
 
 // CHECK-LABEL: @conv3d_f16_f32_acc
-func.func @conv3d_f16_f32_acc(%input: tensor<1x49x48x47x27xf16>, %weights: tensor<28x3x4x5x27xf16>, %bias: tensor<28xf16>) -> () {
+func.func @conv3d_f16_f32_acc(%input: tensor<1x49x48x47x27xf16>, %weights: tensor<43x3x4x5x27xf16>, %bias: tensor<43xf16>) -> () {
   %input_zp = "tosa.const"() <{values = dense<0.0> : tensor<1xf16>}> : () -> tensor<1xf16>
   %weight_zp = "tosa.const"() <{values = dense<0.0> : tensor<1xf16>}> : () -> tensor<1xf16>
-  // CHECK: linalg.generic {{{.*}}} ins(%{{.*}} : tensor<28xf16>) outs(%{{.*}} : tensor<1x47x45x43x28xf32>)
+  // CHECK: linalg.generic {{{.*}}} ins(%{{.*}} : tensor<43xf16>) outs(%{{.*}} : tensor<1x47x45x43x43xf32>)
   // CHECK: arith.extf %{{.*}} : f16 to f32
-  // CHECK: %[[CONV:.*]] = linalg.conv_3d_ndhwc_dhwcf {{{.*}}} ins(%{{.*}}, %{{.*}} : tensor<1x49x48x47x27xf16>, tensor<3x4x5x27x28xf16>) outs(%{{.*}} : tensor<1x47x45x43x28xf32>) -> tensor<1x47x45x43x28xf32>
-  // CHECK: tosa.cast %[[CONV]] : (tensor<1x47x45x43x28xf32>) -> tensor<1x47x45x43x28xf16>
-  %0 = tosa.conv3d %input, %weights, %bias, %input_zp, %weight_zp {acc_type = f32, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>, dilation = array<i64: 1, 1, 1>} : (tensor<1x49x48x47x27xf16>, tensor<28x3x4x5x27xf16>, tensor<28xf16>, tensor<1xf16>, tensor<1xf16>) -> tensor<1x47x45x43x28xf16>
+  // CHECK: %[[CONV:.*]] = linalg.conv_3d_ndhwc_dhwcf {{{.*}}} ins(%{{.*}}, %{{.*}} : tensor<1x49x48x47x27xf16>, tensor<3x4x5x27x43xf16>) outs(%{{.*}} : tensor<1x47x45x43x43xf32>) -> tensor<1x47x45x43x43xf32>
+  // CHECK: tosa.cast %[[CONV]] : (tensor<1x47x45x43x43xf32>) -> tensor<1x47x45x43x43xf16>
+  %0 = tosa.conv3d %input, %weights, %bias, %input_zp, %weight_zp {acc_type = f32, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>, dilation = array<i64: 1, 1, 1>} : (tensor<1x49x48x47x27xf16>, tensor<43x3x4x5x27xf16>, tensor<43xf16>, tensor<1xf16>, tensor<1xf16>) -> tensor<1x47x45x43x43xf16>
   return
 }
 
diff --git a/mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-pipeline.mlir b/mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-pipeline.mlir
index 731e134ed1a07..37ed5cec00a0d 100644
--- a/mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-pipeline.mlir
+++ b/mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-pipeline.mlir
@@ -6,8 +6,8 @@
 // check that -tosa-validate of stateful ops kick in
 func.func @test_variable_write_shape(%arg0: tensor<1x4x8xi8>) -> () {
   tosa.variable @stored_var = dense<-1> : tensor<2x4x8xi8>
-  // expected-error@+1 {{'tosa.variable.write' op operand type does not equal variable type}}
-  tosa.variable.write @stored_var, %arg0 : tensor<1x4x8xi8>
+  // expected-error@+1 {{'tosa.variable_write' op operand type does not equal variable type}}
+  tosa.variable_write @stored_var, %arg0 : tensor<1x4x8xi8>
   return
 }
 
diff --git a/mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir b/mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
index bcf45e5271aaf..7083d19f4372a 100644
--- a/mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
+++ b/mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
@@ -1161,11 +1161,11 @@ func.func @rescale_i8_unsigned_output(%arg0 : tensor<2xi8>) -> () {
   // CHECK: [[GENERIC:%.+]] = linalg.generic {indexing_maps = [#[[$MAP0]], #[[$MAP0]]], iterator_types = ["parallel"]} ins(%[[ARG0]] : tensor<2xi8>) outs([[INIT]] : tensor<2xi8>)
   // CHECK: ^bb0([[IN:%.+]]: i8, [[UNUSED:%.+]]: i8):
   // CHECK: [[C17:%.+]] = arith.constant 17
-  // CHECK: [[C22:%.+]] = arith.constant 22
+  // CHECK: [[C234:%.+]] = arith.constant 234
   // CHECK-DAG: [[IN32:%.+]] = arith.extsi [[IN]]
   // CHECK-DAG: [[IN_ZEROED:%.+]] = arith.subi [[IN32]], [[C17]]
   // CHECK-DAG: [[SCALED:%.+]] = tosa.apply_scale [[IN_ZEROED]], [[C0]], [[C1]] {rounding_mode = "SINGLE_ROUND"}
-  // CHECK-DAG: [[SCALED_ZEROED:%.+]] = arith.addi [[SCALED]], [[C22]]
+  // CHECK-DAG: [[SCALED_ZEROED:%.+]] = arith.addi [[SCALED]], [[C234]]
   // CHECK-DAG: [[CMIN:%.+]] = arith.constant 0
   // CHECK-DAG: [[CMAX:%.+]] = arith.constant 255
   // CHECK-DAG: [[LOWER:%.+]] = arith.maxsi [[CMIN]], [[SCALED_ZEROED]]
@@ -1175,7 +1175,7 @@ func.func @rescale_i8_unsigned_output(%arg0 : tensor<2xi8>) -> () {
   %multiplier = "tosa.const"() {values = dense<19689> : tensor<1xi16> } : () -> tensor<1xi16>
   %shift = "tosa.const"() {values = dense<15> : tensor<1xi8> } : () -> tensor<1xi8>
   %input_zp = "tosa.const"() {values = dense<17> : tensor<1xi8>} : () -> tensor<1xi8>
-  %output_zp = "tosa.const"() {values = dense<22> : tensor<1xi8>} : () -> tensor<1xi8>
+  %output_zp = "tosa.const"() {values = dense<-22> : tensor<1xi8>} : () -> tensor<1xi8>
   %1 = tosa.rescale %arg0, %multiplier, %shift, %input_zp, %output_zp {scale32 = false, rounding_mode = "SINGLE_ROUND", per_channel = false, input_unsigned = false, output_unsigned = true} : (tensor<2xi8>, tensor<1xi16>, tensor<1xi8>, tensor<1xi8>, tensor<1xi8>) -> tensor<2xi8>
 
   // CHECK: return
diff --git a/mlir/test/Conversion/TosaToMLProgram/tosa-to-mlprogram.mlir b/mlir/test/Conversion/TosaToMLProgram/tosa-to-mlprogram.mlir
index 69b6875987daf..365b05ff084da 100644
--- a/mlir/test/Conversion/TosaToMLProgram/tosa-to-mlprogram.mlir
+++ b/mlir/test/Conversion/TosaToMLProgram/tosa-to-mlprogram.mlir
@@ -5,9 +5,9 @@ module {
   tosa.variable @var_x = dense<7.000000e+00> : tensor<1xf32>
   func.func @test_stateful_ops(%arg0: tensor<1xf32>) -> (tensor<1xf32>) {
     // CHECK: ml_program.global_store @var_x = %arg0 : tensor<1xf32>
-    tosa.variable.write @var_x, %arg0 : tensor<1xf32>
+    tosa.variable_write @var_x, %arg0 : tensor<1xf32>
     // CHECK: %[[LOAD:.+]] = ml_program.global_load @var_x : tensor<1xf32>
-    %0 = tosa.variable.read @var_x : tensor<1xf32>
+    %0 = tosa.variable_read @var_x : tensor<1xf32>
     return %0 : tensor<1xf32>
   }
 }
\ No newline at end of file
diff --git a/mlir/test/Dialect/GPU/subgroup-reduce-lowering.mlir b/mlir/test/Dialect/GPU/subgroup-reduce-lowering.mlir
index 9f2aa1be52fc3..098145ade2ae5 100644
--- a/mlir/test/Dialect/GPU/subgroup-reduce-lowering.mlir
+++ b/mlir/test/Dialect/GPU/subgroup-reduce-lowering.mlir
@@ -6,14 +6,26 @@
 // RUN:   --test-gpu-subgroup-reduce-lowering="expand-to-shuffles" %s \
 // RUN:   | FileCheck %s --check-prefix=CHECK-SHFL
 
+// RUN: mlir-opt --allow-unregistered-dialect \
+// RUN:   --test-gpu-subgroup-reduce-lowering="expand-to-shuffles target=gfx942" %s \
+// RUN:   | FileCheck %s --check-prefix=CHECK-GFX9
+
+// RUN: mlir-opt --allow-unregistered-dialect \
+// RUN:   --test-gpu-subgroup-reduce-lowering="expand-to-shuffles target=gfx1030" %s \
+// RUN:   | FileCheck %s --check-prefix=CHECK-GFX10
+
 // CHECK-SUB:  gpu.module @kernels {
 // CHECK-SHFL: gpu.module @kernels {
+// CHECK-GFX9: gpu.module @kernels {
+// CHECK-GFX10: gpu.module @kernels {
 gpu.module @kernels {
 
   // CHECK-SUB-LABEL:  gpu.func @kernel0(
   // CHECK-SUB-SAME:     %[[ARG0:.+]]: vector<5xf16>)
   //
   // CHECK-SHFL-LABEL: gpu.func @kernel0(
+  // CHECK-GFX9-LABEL: gpu.func @kernel0(
+  // CHECK-GFX10-LABEL: gpu.func @kernel0(
   gpu.func @kernel0(%arg0: vector<5xf16>) kernel {
     // CHECK-SUB: %[[VZ:.+]] = arith.constant dense<0.0{{.*}}> : vector<5xf16>
     // CHECK-SUB: %[[E0:.+]] = vector.extract_strided_slice %[[ARG0]] {offsets = [0], sizes = [2], strides = [1]} : vector<5xf16> to vector<2xf16>
@@ -26,16 +38,26 @@ gpu.module @kernels {
     // CHECK-SUB: %[[R2:.+]] = gpu.subgroup_reduce add %[[E2]] : (f16) -> f16
     // CHECK-SUB: %[[V2:.+]] = vector.insert %[[R2]], %[[V1]] [4] : f16 into vector<5xf16>
     // CHECK-SUB: "test.consume"(%[[V2]]) : (vector<5xf16>) -> ()
+    // CHECK-GFX9-COUNT-6: amdgpu.dpp
+    // CHECK-GFX10-COUNT-4: amdgpu.dpp
+    // CHECK-GFX10: rocdl.permlanex16
+    // CHECK-GFX10-COUNT-2: rocdl.readlane
     %sum0 = gpu.subgroup_reduce add %arg0 : (vector<5xf16>) -> (vector<5xf16>)
     "test.consume"(%sum0) : (vector<5xf16>) -> ()
 
     // CHECK-SUB-COUNT-3: gpu.subgroup_reduce mul {{.+}} uniform
     // CHECK-SUB: "test.consume"
+    // CHECK-GFX9-COUNT-6: amdgpu.dpp
+    // CHECK-GFX10-COUNT-4: amdgpu.dpp
+    // CHECK-GFX10: rocdl.permlanex16
+    // CHECK-GFX10-COUNT-2: rocdl.readlane
     %sum1 = gpu.subgroup_reduce mul %arg0 uniform : (vector<5xf16>) -> (vector<5xf16>)
     "test.consume"(%sum1) : (vector<5xf16>) -> ()
 
     // CHECK-SUB-COUNT-3: gpu.subgroup_reduce mul {{.+}} cluster(size = 4)
     // CHECK-SUB: "test.consume"
+    // CHECK-GFX9-COUNT-2: amdgpu.dpp {{.+}}
+    // CHECK-GFX10-COUNT-2: amdgpu.dpp {{.+}}
     %sum2 = gpu.subgroup_reduce mul %arg0 cluster(size = 4) : (vector<5xf16>) -> (vector<5xf16>)
     "test.consume"(%sum2) : (vector<5xf16>) -> ()
 
@@ -52,27 +74,44 @@ gpu.module @kernels {
   // CHECK-SUB-SAME:     %[[ARG0:.+]]: vector<1xf32>)
   //
   // CHECK-SHFL-LABEL: gpu.func @kernel1(
+  // CHECK-GFX9-LABEL: gpu.func @kernel1(
+  // CHECK-GFX10-LABEL: gpu.func @kernel1(
   gpu.func @kernel1(%arg0: vector<1xf32>) kernel {
     // CHECK-SUB: %[[E0:.+]] = vector.extract %[[ARG0]][0] : f32 from vector<1xf32>
     // CHECK-SUB: %[[R0:.+]] = gpu.subgroup_reduce add %[[E0]] : (f32) -> f32
     // CHECK-SUB: %[[V0:.+]] = vector.broadcast %[[R0]] : f32 to vector<1xf32>
     // CHECK-SUB: "test.consume"(%[[V0]]) : (vector<1xf32>) -> ()
+    // CHECK-GFX9-COUNT-6: amdgpu.dpp
+    // CHECK-GFX10-COUNT-4: amdgpu.dpp
+    // CHECK-GFX10: rocdl.permlanex16
+    // CHECK-GFX10-COUNT-2: rocdl.readlane
     %sum0 = gpu.subgroup_reduce add %arg0 : (vector<1xf32>) -> (vector<1xf32>)
     "test.consume"(%sum0) : (vector<1xf32>) -> ()
 
     // CHECK-SUB: gpu.subgroup_reduce add {{.+}} uniform : (f32) -> f32
     // CHECK-SUB: "test.consume"
+    // CHECK-GFX9-COUNT-6: amdgpu.dpp
+    // CHECK-GFX10-COUNT-4: amdgpu.dpp
+    // CHECK-GFX10: rocdl.permlanex16
+    // CHECK-GFX10-COUNT-2: rocdl.readlane
     %sum1 = gpu.subgroup_reduce add %arg0 uniform : (vector<1xf32>) -> (vector<1xf32>)
     "test.consume"(%sum1) : (vector<1xf32>) -> ()
 
     // Note stride is dropped because it is == 1.
     // CHECK-SUB: gpu.subgroup_reduce add {{.+}} cluster(size = 8) : (f32) -> f32
     // CHECK-SUB: "test.consume"
+    // CHECK-GFX9-COUNT-2: amdgpu.dpp {{.+}} quad_perm
+    // CHECK-GFX9: amdgpu.dpp {{.+}} row_half_mirror
+    // CHECK-GFX10-COUNT-2: amdgpu.dpp {{.+}} quad_perm
+    // CHECK-GFX10: amdgpu.dpp {{.+}} row_half_mirror
     %sum2 = gpu.subgroup_reduce add %arg0 cluster(size = 8, stride = 1) : (vector<1xf32>) -> (vector<1xf32>)
     "test.consume"(%sum2) : (vector<1xf32>) -> ()
 
     // CHECK-SUB: gpu.subgroup_reduce add {{.+}} uniform cluster(size = 8, stride = 4) : (f32) -> f32
     // CHECK-SUB: "test.consume"
+    // CHECK-GFX9-NOT: amdgpu.dpp
+    // CHECK-GFX10-NOT: amdgpu.dpp
+    // CHECK-GFX10-NOT: rocdl.permlanex16
     %sum3 = gpu.subgroup_reduce add %arg0 uniform cluster(size = 8, stride = 4) : (vector<1xf32>) -> (vector<1xf32>)
     "test.consume"(%sum3) : (vector<1xf32>) -> ()
 
@@ -86,6 +125,12 @@ gpu.module @kernels {
   // CHECK-SUB-SAME:     %[[ARG0:.+]]: vector<3xi8>, %[[ARG1:.+]]: vector<4xi8>)
   //
   // CHECK-SHFL-LABEL: gpu.func @kernel2(
+  //
+  // CHECK-GFX9-LABEL: gpu.func @kernel2(
+  // CHECK-GFX9-NOT: amdgpu.dpp
+  //
+  // CHECK-GFX10-LABEL: gpu.func @kernel2(
+  // CHECK-GFX10-NOT: amdgpu.dpp
   gpu.func @kernel2(%arg0: vector<3xi8>, %arg1: vector<4xi8>) kernel {
     // CHECK-SUB: %[[R0:.+]] = gpu.subgroup_reduce add %[[ARG0]] : (vector<3xi8>) -> vector<3xi8>
     // CHECK-SUB: "test.consume"(%[[R0]]) : (vector<3xi8>) -> ()
@@ -103,6 +148,8 @@ gpu.module @kernels {
 
   // CHECK-SHFL-LABEL: gpu.func @kernel3(
   // CHECK-SHFL-SAME:    %[[ARG0:.+]]: i32)
+  // CHECK-GFX9-LABEL: gpu.func @kernel3(
+  // CHECK-GFX10-LABEL: gpu.func @kernel3(
   gpu.func @kernel3(%arg0: i32) kernel {
     // CHECK-SHFL-DAG: %[[C1:.+]] = arith.constant 1 : i32
     // CHECK-SHFL-DAG: %[[C2:.+]] = arith.constant 2 : i32
@@ -122,6 +169,12 @@ gpu.module @kernels {
     // CHECK-SHFL: %[[S4:.+]], %{{.+}} = gpu.shuffle xor %[[A3]], %[[C16]], %[[C32]] : i32
     // CHECK-SHFL: %[[A4:.+]] = arith.addi %[[A3]], %[[S4]] : i32
     // CHECK-SHFL: "test.consume"(%[[A4]]) : (i32) -> ()
+    
+    // CHECK-GFX9-COUNT-6: amdgpu.dpp
+    
+    // CHECK-GFX10-COUNT-4: amdgpu.dpp
+    // CHECK-GFX10: rocdl.permlanex16
+    // CHECK-GFX10-COUNT-2: rocdl.readlane
     %sum0 = gpu.subgroup_reduce add %arg0 : (i32) -> i32
     "test.consume"(%sum0) : (i32) -> ()
 
@@ -131,6 +184,12 @@ gpu.module @kernels {
 
   // CHECK-SHFL-LABEL: gpu.func @kernel3_clustered(
   // CHECK-SHFL-SAME:    %[[ARG0:.+]]: i32)
+  //
+  // CHECK-GFX9-LABEL: gpu.func @kernel3_clustered(
+  // CHECK-GFX9-SAME:    %[[ARG0:.+]]: i32)
+  //
+  // CHECK-GFX10-LABEL: gpu.func @kernel3_clustered(
+  // CHECK-GFX10-SAME:    %[[ARG0:.+]]: i32)
   gpu.func @kernel3_clustered(%arg0: i32) kernel {
     // CHECK-SHFL-DAG: %[[C1:.+]] = arith.constant 1 : i32
     // CHECK-SHFL-DAG: %[[C2:.+]] = arith.constant 2 : i32
@@ -144,6 +203,21 @@ gpu.module @kernels {
     // CHECK-SHFL: %[[S2:.+]], %{{.+}} = gpu.shuffle xor %[[A1]], %[[C4]], %[[C32]] : i32
     // CHECK-SHFL: %[[A2:.+]] = arith.addi %[[A1]], %[[S2]] : i32
     // CHECK-SHFL: "test.consume"(%[[A2]]) : (i32) -> ()
+
+    // CHECK-GFX9: %[[D0:.+]] = amdgpu.dpp %[[ARG0]] %[[ARG0]]  quad_perm([1 : i32, 0 : i32, 3 : i32, 2 : i32]) {bound_ctrl = true} : i32
+    // CHECK-GFX9: %[[A0:.+]] = arith.addi %[[ARG0]], %[[D0]] : i32
+    // CHECK-GFX9: %[[D1:.+]] = amdgpu.dpp %[[A0]] %[[A0]]  quad_perm([2 : i32, 3 : i32, 0 : i32, 1 : i32]) {bound_ctrl = true} : i32
+    // CHECK-GFX9: %[[A1:.+]] = arith.addi %[[A0]], %[[D1]] : i32
+    // CHECK-GFX9: %[[D2:.+]] = amdgpu.dpp %[[A1]] %[[A1]]  row_half_mirror(unit) {bound_ctrl = true} : i32
+    // CHECK-GFX9: %[[A2:.+]] = arith.addi %[[A1]], %[[D2]] : i32
+
+    // CHECK-GFX10: %[[D0:.+]] = amdgpu.dpp %[[ARG0]] %[[ARG0]]  quad_perm([1 : i32, 0 : i32, 3 : i32, 2 : i32]) {bound_ctrl = true} : i32
+    // CHECK-GFX10: %[[A0:.+]] = arith.addi %[[ARG0]], %[[D0]] : i32
+    // CHECK-GFX10: %[[D1:.+]] = amdgpu.dpp %[[A0]] %[[A0]]  quad_perm([2 : i32, 3 : i32, 0 : i32, 1 : i32]) {bound_ctrl = true} : i32
+    // CHECK-GFX10: %[[A1:.+]] = arith.addi %[[A0]], %[[D1]] : i32
+    // CHECK-GFX10: %[[D2:.+]] = amdgpu.dpp %[[A1]] %[[A1]]  row_half_mirror(unit) {bound_ctrl = true} : i32
+    // CHECK-GFX10: %[[A2:.+]] = arith.addi %[[A1]], %[[D2]] : i32
+    // CHECK-GFX10: "test.consume"(%[[A2]]) : (i32) -> ()
     %sum0 = gpu.subgroup_reduce add %arg0 cluster(size = 8) : (i32) -> i32
     "test.consume"(%sum0) : (i32) -> ()
 
@@ -153,6 +227,12 @@ gpu.module @kernels {
 
   // CHECK-SHFL-LABEL: gpu.func @kernel3_clustered_strided(
   // CHECK-SHFL-SAME:    %[[ARG0:.+]]: i32)
+  //
+  // CHECK-GFX9-LABEL: gpu.func @kernel3_clustered_strided(
+  // CHECK-GFX9-NOT: amdgpu.dpp
+  //
+  // CHECK-GFX10-LABEL: gpu.func @kernel3_clustered_strided(
+  // CHECK-GFX10-NOT: amdgpu.dpp
   gpu.func @kernel3_clustered_strided(%arg0: i32) kernel {
     // CHECK-SHFL-DAG: %[[C1:.+]] = arith.constant 4 : i32
     // CHECK-SHFL-DAG: %[[C2:.+]] = arith.constant 8 : i32
@@ -175,6 +255,12 @@ gpu.module @kernels {
 
   // CHECK-SHFL-LABEL: gpu.func @kernel4(
   // CHECK-SHFL-SAME:    %[[ARG0:.+]]: vector<2xf16>)
+  //
+  // CHECK-GFX9-LABEL: gpu.func @kernel4(
+  // CHECK-GFX9-NOT: amdgpu.dpp
+  //
+  // CHECK-GFX10-LABEL: gpu.func @kernel4(
+  // CHECK-GFX10-NOT: amdgpu.dpp
   gpu.func @kernel4(%arg0: vector<2xf16>) kernel {
     // CHECK-SHFL-DAG: %[[C1:.+]] = arith.constant 1 : i32
     // CHECK-SHFL-DAG: %[[C2:.+]] = arith.constant 2 : i32
@@ -211,6 +297,12 @@ gpu.module @kernels {
 
   // CHECK-SHFL-LABEL: gpu.func @kernel4_clustered(
   // CHECK-SHFL-SAME:    %[[ARG0:.+]]: vector<2xf16>)
+  //
+  // CHECK-GFX9-LABEL: gpu.func @kernel4_clustered(
+  // CHECK-GFX9-NOT: amdgpu.dpp
+  //
+  // CHECK-GFX10-LABEL: gpu.func @kernel4_clustered(
+  // CHECK-GFX10-NOT: amdgpu.dpp
   gpu.func @kernel4_clustered(%arg0: vector<2xf16>) kernel {
     // CHECK-SHFL-DAG: %[[C1:.+]] = arith.constant 1 : i32
     // CHECK-SHFL-DAG: %[[C2:.+]] = arith.constant 2 : i32
@@ -226,6 +318,11 @@ gpu.module @kernels {
 
   // CHECK-SHFL-LABEL: gpu.func @kernel5(
   // CHECK-SHFL-SAME:    %[[ARG0:.+]]: i16)
+  //
+  // CHECK-GFX9-LABEL: gpu.func @kernel5(
+  //
+  // CHECK-GFX10-LABEL: gpu.func @kernel5(
+  // CHECK-GFX10-SAME:    %[[ARG0:.+]]: i16)
   gpu.func @kernel5(%arg0: i16) kernel {
     // CHECK-SHFL: %[[E0:.+]] = arith.extui %[[ARG0]] : i16 to i32
     // CHECK-SHFL: %[[S0:.+]], %{{.+}} = gpu.shuffle xor %[[E0]], {{.+}} : i32
@@ -237,6 +334,23 @@ gpu.module @kernels {
     // CHECK-SHFL: arith.trunci {{.+}} : i32 to i16
     // CHECK-SHFL: %[[AL:.+]] = arith.addi {{.+}} : i16
     // CHECK-SHFL: "test.consume"(%[[AL]]) : (i16) -> ()
+    
+    // CHECK-GFX9-COUNT-6: amdgpu.dpp
+
+    // CHECK-GFX10: %[[D0:.+]] = amdgpu.dpp %[[ARG0]] %[[ARG0]]  quad_perm([1 : i32, 0 : i32, 3 : i32, 2 : i32]) {bound_ctrl = true} : i16
+    // CHECK-GFX10: %[[A0:.+]] = arith.addi %[[ARG0]], %[[D0]] : i16
+    // CHECK-GFX10: %[[D1:.+]] = amdgpu.dpp %[[A0]] %[[A0]]  quad_perm([2 : i32, 3 : i32, 0 : i32, 1 : i32]) {bound_ctrl = true} : i16
+    // CHECK-GFX10: %[[A1:.+]] = arith.addi %[[A0]], %[[D1]] : i16
+    // CHECK-GFX10: %[[D2:.+]] = amdgpu.dpp %[[A1]] %[[A1]]  row_half_mirror(unit) {bound_ctrl = true} : i16
+    // CHECK-GFX10: %[[A2:.+]] = arith.addi %[[A1]], %[[D2]] : i16
+    // CHECK-GFX10: %[[D3:.+]] = amdgpu.dpp %[[A2]] %[[A2]]  row_mirror(unit) {bound_ctrl = true} : i16
+    // CHECK-GFX10: %[[A3:.+]] = arith.addi %[[A2]], %[[D3]] : i16
+    // CHECK-GFX10: %[[P0:.+]] = rocdl.permlanex16 %[[A3]], %[[A3]], %c-1_i32, %c-1_i32, true, false : i16, i32
+    // CHECK-GFX10: %[[A4:.+]] = arith.addi %[[A3]], %[[P0]] : i16
+    // CHECK-GFX10: %[[R0:.+]] = rocdl.readlane %[[A4]], %{{.+}} : (i16, i32) -> i16
+    // CHECK-GFX10: %[[R1:.+]] = rocdl.readlane %[[A4]], %{{.+}} : (i16, i32) -> i16
+    // CHECK-GFX10: %[[A5:.+]] = arith.addi %[[R1]], %[[R0]] : i16
+    // CHECK-GFX10: "test.consume"(%[[A5]]) : (i16) -> ()
     %sum0 = gpu.subgroup_reduce add %arg0 : (i16) -> i16
     "test.consume"(%sum0) : (i16) -> ()
 
@@ -246,6 +360,12 @@ gpu.module @kernels {
 
   // CHECK-SHFL-LABEL: gpu.func @kernel5_clustered(
   // CHECK-SHFL-SAME:    %[[ARG0:.+]]: i16)
+  //
+  // CHECK-GFX9-LABEL: gpu.func @kernel5_clustered
+  // CHECK-GFX9-SAME:    %[[ARG0:.+]]: i16)
+  //
+  // CHECK-GFX10-LABEL: gpu.func @kernel5_clustered
+  // CHECK-GFX10-SAME:    %[[ARG0:.+]]: i16)
   gpu.func @kernel5_clustered(%arg0: i16) kernel {
     // CHECK-SHFL: %[[E0:.+]] = arith.extui %[[ARG0]] : i16 to i32
     // CHECK-SHFL: %[[S0:.+]], %{{.+}} = gpu.shuffle xor %[[E0]], {{.+}} : i32
@@ -257,6 +377,26 @@ gpu.module @kernels {
     // CHECK-SHFL: arith.trunci {{.+}} : i32 to i16
     // CHECK-SHFL: %[[AL:.+]] = arith.addi {{.+}} : i16
     // CHECK-SHFL: "test.consume"(%[[AL]]) : (i16) -> ()
+
+    // CHECK-GFX9: %[[VAR0:.+]] = amdgpu.dpp %[[ARG0]] %[[ARG0]]  quad_perm([1 : i32, 0 : i32, 3 : i32, 2 : i32]) {bound_ctrl = true} : i16
+    // CHECK-GFX9: %[[VAR1:.+]] = arith.addi %[[ARG0]], %[[VAR0]] : i16
+    // CHECK-GFX9: %[[VAR2:.+]] = amdgpu.dpp %[[VAR1]] %[[VAR1]]  quad_perm([2 : i32, 3 : i32, 0 : i32, 1 : i32]) {bound_ctrl = true} : i16
+    // CHECK-GFX9: %[[VAR3:.+]] = arith.addi %[[VAR1]], %[[VAR2]] : i16
+    // CHECK-GFX9: %[[VAR4:.+]] = amdgpu.dpp %[[VAR3]] %[[VAR3]]  row_half_mirror(unit) {bound_ctrl = true} : i16
+    // CHECK-GFX9: %[[VAR5:.+]] = arith.addi %[[VAR3]], %[[VAR4]] : i16
+    // CHECK-GFX9: %[[VAR6:.+]] = amdgpu.dpp %[[VAR5]] %[[VAR5]]  row_mirror(unit) {bound_ctrl = true} : i16
+    // CHECK-GFX9: %[[VAR7:.+]] = arith.addi %[[VAR5]], %[[VAR6]] : i16
+    // CHECK-GFX9: "test.consume"(%[[VAR7]]) : (i16) -> ()
+
+    // CHECK-GFX10: %[[VAR0:.+]] = amdgpu.dpp %[[ARG0]] %[[ARG0]]  quad_perm([1 : i32, 0 : i32, 3 : i32, 2 : i32]) {bound_ctrl = true} : i16
+    // CHECK-GFX10: %[[VAR1:.+]] = arith.addi %[[ARG0]], %[[VAR0]] : i16
+    // CHECK-GFX10: %[[VAR2:.+]] = amdgpu.dpp %[[VAR1]] %[[VAR1]]  quad_perm([2 : i32, 3 : i32, 0 : i32, 1 : i32]) {bound_ctrl = true} : i16
+    // CHECK-GFX10: %[[VAR3:.+]] = arith.addi %[[VAR1]], %[[VAR2]] : i16
+    // CHECK-GFX10: %[[VAR4:.+]] = amdgpu.dpp %[[VAR3]] %[[VAR3]]  row_half_mirror(unit) {bound_ctrl = true} : i16
+    // CHECK-GFX10: %[[VAR5:.+]] = arith.addi %[[VAR3]], %[[VAR4]] : i16
+    // CHECK-GFX10: %[[VAR6:.+]] = amdgpu.dpp %[[VAR5]] %[[VAR5]]  row_mirror(unit) {bound_ctrl = true} : i16
+    // CHECK-GFX10: %[[VAR7:.+]] = arith.addi %[[VAR5]], %[[VAR6]] : i16
+    // CHECK-GFX10: "test.consume"(%[[VAR7]]) : (i16) -> ()
     %sum0 = gpu.subgroup_reduce add %arg0 cluster(size = 16) : (i16) -> i16
     "test.consume"(%sum0) : (i16) -> ()
 
@@ -266,6 +406,12 @@ gpu.module @kernels {
 
   // CHECK-SHFL-LABEL: gpu.func @kernel6(
   // CHECK-SHFL-SAME:    %[[ARG0:.+]]: vector<3xi8>)
+  //
+  // CHECK-GFX9-LABEL: gpu.func @kernel6(
+  // CHECK-GFX9-NOT: amdgpu.dpp
+  //
+  // CHECK-GFX10-LABEL: gpu.func @kernel6(
+  // CHECK-GFX10-NOT: amdgpu.dpp
   gpu.func @kernel6(%arg0: vector<3xi8>) kernel {
     // CHECK-SHFL: %[[CZ:.+]] = arith.constant dense<0> : vector<4xi8>
     // CHECK-SHFL: %[[V0:.+]] = vector.insert_strided_slice %[[ARG0]], %[[CZ]] {offsets = [0], strides = [1]} : vector<3xi8> into vector<4xi8>
@@ -289,6 +435,12 @@ gpu.module @kernels {
 
   // CHECK-SHFL-LABEL: gpu.func @kernel_cluster_size_is_subgroup_size(
   // CHECK-SHFL-SAME:    %[[ARG0:.+]]: vector<3xi8>)
+  //
+  // CHECK-GFX9-LABEL: gpu.func @kernel_cluster_size_is_subgroup_size(
+  // CHECK-GFX9-NOT: amdgpu.dpp
+  //
+  // CHECK-GFX10-LABEL: gpu.func @kernel_cluster_size_is_subgroup_size(
+  // CHECK-GFX10-NOT: amdgpu.dpp
   gpu.func @kernel_cluster_size_is_subgroup_size(%arg0: vector<3xi8>) kernel {
     // CHECK-SHFL-COUNT-5: gpu.shuffle xor
     %sum0 = gpu.subgroup_reduce add %arg0 cluster(size = 32) : (vector<3xi8>) -> (vector<3xi8>)
diff --git a/mlir/test/Dialect/LLVMIR/canonicalize.mlir b/mlir/test/Dialect/LLVMIR/canonicalize.mlir
index a793caca064ec..8accf6e263863 100644
--- a/mlir/test/Dialect/LLVMIR/canonicalize.mlir
+++ b/mlir/test/Dialect/LLVMIR/canonicalize.mlir
@@ -57,6 +57,22 @@ llvm.func @fold_extractvalue() -> i32 {
 
 // -----
 
+// CHECK-LABEL: fold_extractvalue(
+//  CHECK-SAME:     %[[arg1:.*]]: i32, %[[arg2:.*]]: i32, %[[arg3:.*]]: i32)
+//  CHECK-NEXT:   llvm.return %[[arg1]] : i32
+llvm.func @fold_extractvalue(%arg1: i32, %arg2: i32, %arg3: i32) -> i32{
+  %3 = llvm.mlir.undef : !llvm.struct<(struct<(i32, i32, i32)>, struct<(i32, i32)>)>
+  %5 = llvm.mlir.undef : !llvm.struct<(i32, i32, i32)>
+  %6 = llvm.insertvalue %arg1, %5[0] : !llvm.struct<(i32, i32, i32)>
+  %7 = llvm.insertvalue %arg1, %6[1] : !llvm.struct<(i32, i32, i32)>
+  %8 = llvm.insertvalue %arg1, %7[2] : !llvm.struct<(i32, i32, i32)>
+  %11 = llvm.insertvalue %8, %3[0] : !llvm.struct<(struct<(i32, i32, i32)>, struct<(i32, i32)>)>
+  %13 = llvm.extractvalue %11[0, 0] : !llvm.struct<(struct<(i32, i32, i32)>, struct<(i32, i32)>)>
+  llvm.return %13 : i32
+}
+
+// -----
+
 // CHECK-LABEL: no_fold_extractvalue
 llvm.func @no_fold_extractvalue(%arr: !llvm.array<4 x f32>) -> f32 {
   %f0 = arith.constant 0.0 : f32
diff --git a/mlir/test/Dialect/LLVMIR/invalid.mlir b/mlir/test/Dialect/LLVMIR/invalid.mlir
index 0cd6b1f20a1bf..a3cd9572933ae 100644
--- a/mlir/test/Dialect/LLVMIR/invalid.mlir
+++ b/mlir/test/Dialect/LLVMIR/invalid.mlir
@@ -1776,9 +1776,10 @@ llvm.mlir.alias external @y5 : i32 {
 // -----
 
 module {
-  // expected-error@+2 {{expected integer value}}
-  // expected-error@+1 {{failed to parse ModuleFlagAttr parameter 'value' which is to be a `uint32_t`}}
-  llvm.module_flags [#llvm.mlir.module_flag<error, "wchar_size", "yolo">]
+  llvm.func @foo()
+
+  // expected-error@below {{only integer and string values are currently supported}}
+  llvm.module_flags [#llvm.mlir.module_flag<error, "yolo", @foo>]
 }
 
 // -----
diff --git a/mlir/test/Dialect/LLVMIR/module-roundtrip.mlir b/mlir/test/Dialect/LLVMIR/module-roundtrip.mlir
index d99a93c1e8565..a94514da9818f 100644
--- a/mlir/test/Dialect/LLVMIR/module-roundtrip.mlir
+++ b/mlir/test/Dialect/LLVMIR/module-roundtrip.mlir
@@ -1,16 +1,18 @@
 // RUN: mlir-opt %s | mlir-opt | FileCheck %s
 
 module {
-  llvm.module_flags [#llvm.mlir.module_flag<error, "wchar_size", 4>,
-                     #llvm.mlir.module_flag<min, "PIC Level", 2>,
-                     #llvm.mlir.module_flag<max, "PIE Level", 2>,
-                     #llvm.mlir.module_flag<max, "uwtable", 2>,
-                     #llvm.mlir.module_flag<max, "frame-pointer", 1>]
+  llvm.module_flags [#llvm.mlir.module_flag<error, "wchar_size", 4 : i32>,
+                     #llvm.mlir.module_flag<min, "PIC Level", 2 : i32>,
+                     #llvm.mlir.module_flag<max, "PIE Level", 2 : i32>,
+                     #llvm.mlir.module_flag<max, "uwtable", 2 : i32>,
+                     #llvm.mlir.module_flag<max, "frame-pointer", 1 : i32>,
+                     #llvm.mlir.module_flag<override, "probe-stack", "inline-asm">]
 }
 
 // CHECK: llvm.module_flags [
-// CHECK-SAME: #llvm.mlir.module_flag<error, "wchar_size", 4>,
-// CHECK-SAME: #llvm.mlir.module_flag<min, "PIC Level", 2>,
-// CHECK-SAME: #llvm.mlir.module_flag<max, "PIE Level", 2>,
-// CHECK-SAME: #llvm.mlir.module_flag<max, "uwtable", 2>,
-// CHECK-SAME: #llvm.mlir.module_flag<max, "frame-pointer", 1>]
+// CHECK-SAME: #llvm.mlir.module_flag<error, "wchar_size", 4 : i32>,
+// CHECK-SAME: #llvm.mlir.module_flag<min, "PIC Level", 2 : i32>,
+// CHECK-SAME: #llvm.mlir.module_flag<max, "PIE Level", 2 : i32>,
+// CHECK-SAME: #llvm.mlir.module_flag<max, "uwtable", 2 : i32>,
+// CHECK-SAME: #llvm.mlir.module_flag<max, "frame-pointer", 1 : i32>,
+// CHECK-SAME: #llvm.mlir.module_flag<override, "probe-stack", "inline-asm">]
diff --git a/mlir/test/Dialect/Tosa/availability.mlir b/mlir/test/Dialect/Tosa/availability.mlir
index 75126a11ac504..7374cfd1145b9 100644
--- a/mlir/test/Dialect/Tosa/availability.mlir
+++ b/mlir/test/Dialect/Tosa/availability.mlir
@@ -38,12 +38,12 @@ func.func @test_conv2d(%arg0: tensor<1x4x4x4xf32>, %arg1: tensor<8x1x1x4xf32>, %
 
 // -----
 // CHECK-LABEL: conv3d
-func.func @test_conv3d(%arg0: tensor<1x4x8x21x17xf32>, %arg1: tensor<34x1x1x1x17xf32>, %arg2: tensor<34xf32>) -> tensor<1x4x8x21x34xf32> {
+func.func @test_conv3d(%arg0: tensor<1x4x8x21x17xf32>, %arg1: tensor<34x1x1x1x17xf32>, %arg2: tensor<21xf32>) -> tensor<1x4x8x21x34xf32> {
   // CHECK: profiles: [ [pro_int, pro_fp] ]
   // CHECK: extensions: [ [int4, int16, fp8e4m3, fp8e5m2, bf16] ]
   %input_zp = "tosa.const"() <{values = dense<0.0> : tensor<1xf32>}> : () -> tensor<1xf32>
   %weight_zp = "tosa.const"() <{values = dense<0.0> : tensor<1xf32>}> : () -> tensor<1xf32>
-  %0 = tosa.conv3d %arg0, %arg1, %arg2, %input_zp, %weight_zp {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>} : (tensor<1x4x8x21x17xf32>, tensor<34x1x1x1x17xf32>, tensor<34xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x4x8x21x34xf32>
+  %0 = tosa.conv3d %arg0, %arg1, %arg2, %input_zp, %weight_zp {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>} : (tensor<1x4x8x21x17xf32>, tensor<34x1x1x1x17xf32>, tensor<21xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x4x8x21x34xf32>
   return %0 : tensor<1x4x8x21x34xf32>
 }
 
diff --git a/mlir/test/Dialect/Tosa/canonicalize.mlir b/mlir/test/Dialect/Tosa/canonicalize.mlir
index d153474593d80..59fd490330691 100644
--- a/mlir/test/Dialect/Tosa/canonicalize.mlir
+++ b/mlir/test/Dialect/Tosa/canonicalize.mlir
@@ -379,19 +379,19 @@ func.func @conv2d_weight_2x2(%arg0: tensor<4x10x10x1xf32>) -> tensor<4x9x9x1xf32
 // -----
 
 // CHECK-LABEL: @depthwise_conv2d_stride_2
-func.func @depthwise_conv2d_stride_2(%arg0: tensor<4x10x10x2xf32>, %arg1: tensor<1x1x2x3xf32>, %arg2: tensor<6xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<4x10x10x6xf32> {
+func.func @depthwise_conv2d_stride_2(%arg0: tensor<4x11x11x2xf32>, %arg1: tensor<1x1x2x3xf32>, %arg2: tensor<6xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<4x6x6x6xf32> {
   // CHECK: tosa.depthwise_conv2d
-  %0 = tosa.depthwise_conv2d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, pad = array<i64: 0, 0, 0, 0>, stride = array<i64: 2, 2>, dilation = array<i64: 1, 1>} : (tensor<4x10x10x2xf32>, tensor<1x1x2x3xf32>, tensor<6xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<4x10x10x6xf32>
-  return %0 : tensor<4x10x10x6xf32>
+  %0 = tosa.depthwise_conv2d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, pad = array<i64: 0, 0, 0, 0>, stride = array<i64: 2, 2>, dilation = array<i64: 1, 1>} : (tensor<4x11x11x2xf32>, tensor<1x1x2x3xf32>, tensor<6xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<4x6x6x6xf32>
+  return %0 : tensor<4x6x6x6xf32>
 }
 
 // -----
 
 // CHECK-LABEL: @depthwise_conv2d_weight_2x2
-func.func @depthwise_conv2d_weight_2x2(%arg0: tensor<4x10x10x2xf32>, %arg1: tensor<2x2x2x3xf32>, %arg2: tensor<6xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<4x10x10x6xf32> {
+func.func @depthwise_conv2d_weight_2x2(%arg0: tensor<4x10x10x2xf32>, %arg1: tensor<2x2x2x3xf32>, %arg2: tensor<6xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<4x9x9x6xf32> {
   // CHECK: tosa.depthwise_conv2d
-  %0 = tosa.depthwise_conv2d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, pad = array<i64: 0, 0, 0, 0>, stride = array<i64: 1, 1>, dilation = array<i64: 1, 1>} : (tensor<4x10x10x2xf32>, tensor<2x2x2x3xf32>, tensor<6xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<4x10x10x6xf32>
-  return %0 : tensor<4x10x10x6xf32>
+  %0 = tosa.depthwise_conv2d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, pad = array<i64: 0, 0, 0, 0>, stride = array<i64: 1, 1>, dilation = array<i64: 1, 1>} : (tensor<4x10x10x2xf32>, tensor<2x2x2x3xf32>, tensor<6xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<4x9x9x6xf32>
+  return %0 : tensor<4x9x9x6xf32>
 }
 
 // -----
diff --git a/mlir/test/Dialect/Tosa/invalid.mlir b/mlir/test/Dialect/Tosa/invalid.mlir
index fc98aa95ed5b3..b147c94fde9b0 100644
--- a/mlir/test/Dialect/Tosa/invalid.mlir
+++ b/mlir/test/Dialect/Tosa/invalid.mlir
@@ -272,37 +272,6 @@ func.func @test_concat(%arg0 : tensor<2x1xf32>, %arg1 : tensor<2x2xf32>) -> tens
 
 // -----
 
-func.func @test_concat_element_type_mismatch(%arg0 : tensor<1x2xf32>, %arg1 : tensor<2x2xf32>) -> tensor<?x?xi8> {
-  // expected-error@+1 {{'tosa.concat' op expect input and output to have same element type, got 'f32' and 'i8'}}
-  %0 = tosa.concat %arg0, %arg1 {axis = 0 : i32} : (tensor<1x2xf32>, tensor<2x2xf32>) -> tensor<?x?xi8>
-  return %0 : tensor<?x?xi8>
-}
-
-// -----
-
-func.func @test_concat_zero_inputs() {
-  // expected-error@+1 {{'tosa.concat' op expect at least one input}}
-  %0 = tosa.concat {axis = 0 : i32} : () -> tensor<*xf32>
-}
-
-// -----
-
-func.func @test_concat_axis_negative(%arg0: tensor<1x2xf32>, %arg1: tensor<2x2xf32>) -> tensor<2x2xf32> {
-  // expected-error@+1 {{'tosa.concat' op expect axis to be within range 0 < axis < rank(input1[firstRankedTensorIdx]), got -1}}
-  %0 = tosa.concat %arg0, %arg1 {axis = -1 : i32} : (tensor<1x2xf32>, tensor<2x2xf32>) -> tensor<2x2xf32>
-  return %0 : tensor<2x2xf32>
-}
-
-// -----
-
-func.func @test_concat_axis_out_of_range(%arg0: tensor<1x2xf32>, %arg1: tensor<2x2xf32>) -> tensor<2x2xf32> {
-  // expected-error@+1 {{'tosa.concat' op expect axis to be within range 0 < axis < rank(input1[firstRankedTensorIdx]), got 3}}
-  %0 = tosa.concat %arg0, %arg1 {axis = 3 : i32} : (tensor<1x2xf32>, tensor<2x2xf32>) -> tensor<2x2xf32>
-  return %0 : tensor<2x2xf32>
-}
-
-// -----
-
 func.func @test_pad_non_const(%arg0: tensor<13x21x3xf32>, %arg1: !tosa.shape<6>) -> tensor<13x21x3xf32> {
   %pad_const = "tosa.const"() {values = dense<3.14> : tensor<1xf32>} : () -> tensor<1xf32>
   // expected-error@+1 {{'tosa.pad' op shape operand is not compile time resolvable}}
@@ -626,8 +595,8 @@ func.func @test_variable_duplicates(%arg0: tensor<2x4x8xi8>) -> () {
 
 func.func @test_variable_read_type(%arg0: tensor<2x4x8xi8>) -> () {
   tosa.variable @stored_var = dense<-1> : tensor<2x4x8xi8>
-  // expected-error@+1 {{'tosa.variable.read' op result type does not equal variable type}}
-  %0 = tosa.variable.read @stored_var : tensor<2x4x8xi16>
+  // expected-error@+1 {{'tosa.variable_read' op illegal: operand/result data types not supported}}
+  %0 = tosa.variable_read @stored_var : tensor<2x4x8xi16>
   return
 }
 
@@ -635,8 +604,8 @@ func.func @test_variable_read_type(%arg0: tensor<2x4x8xi8>) -> () {
 
 func.func @test_variable_read_shape(%arg0: tensor<2x4x8xi8>) -> () {
   tosa.variable @stored_var = dense<-1> : tensor<2x4x8xi8>
-  // expected-error@+1 {{'tosa.variable.read' op result type does not equal variable type}}
-  %0 = tosa.variable.read @stored_var : tensor<1x4x8xi32>
+  // expected-error@+1 {{'tosa.variable_read' op illegal: operand/result data types not supported}}
+  %0 = tosa.variable_read @stored_var : tensor<1x4x8xi32>
   return
 }
 
@@ -644,8 +613,8 @@ func.func @test_variable_read_shape(%arg0: tensor<2x4x8xi8>) -> () {
 
 func.func @test_variable_write_type(%arg0: tensor<2x4x8xi16>) -> () {
   tosa.variable @stored_var = dense<-1> : tensor<2x4x8xi8>
-  // expected-error@+1 {{'tosa.variable.write' op operand type does not equal variable type}}
-  tosa.variable.write @stored_var, %arg0 : tensor<2x4x8xi16>
+  // expected-error@+1 {{'tosa.variable_write' op illegal: operand/result data types not supported}}
+  tosa.variable_write @stored_var, %arg0 : tensor<2x4x8xi16>
   return
 }
 
@@ -653,8 +622,8 @@ func.func @test_variable_write_type(%arg0: tensor<2x4x8xi16>) -> () {
 
 func.func @test_variable_write_shape(%arg0: tensor<1x4x8xi8>) -> () {
   tosa.variable @stored_var = dense<-1> : tensor<2x4x8xi8>
-  // expected-error@+1 {{'tosa.variable.write' op operand type does not equal variable type}}
-  tosa.variable.write @stored_var, %arg0 : tensor<1x4x8xi8>
+  // expected-error@+1 {{'tosa.variable_write' op operand type does not equal variable type}}
+  tosa.variable_write @stored_var, %arg0 : tensor<1x4x8xi8>
   return
 }
 
diff --git a/mlir/test/Dialect/Tosa/invalid_extension.mlir b/mlir/test/Dialect/Tosa/invalid_extension.mlir
index 7386b1ba9df99..c862ae375f33b 100644
--- a/mlir/test/Dialect/Tosa/invalid_extension.mlir
+++ b/mlir/test/Dialect/Tosa/invalid_extension.mlir
@@ -26,9 +26,9 @@ func.func @test_conv2d(%arg0: tensor<1x4x4x4xi8>, %arg1: tensor<8x1x1x4xi4>, %ar
 }
 
 // -----
-func.func @test_conv3d(%arg0: tensor<1x4x8x21x17xi16>, %arg1: tensor<34x1x1x1x17xi8>, %arg2: tensor<34xi48>, %arg3: tensor<1xi16>, %arg4: tensor<1xi8>) -> tensor<1x4x8x21x34xi48> {
+func.func @test_conv3d(%arg0: tensor<1x4x8x21x17xi16>, %arg1: tensor<34x1x1x1x17xi8>, %arg2: tensor<21xi48>, %arg3: tensor<1xi16>, %arg4: tensor<1xi8>) -> tensor<1x4x8x21x34xi48> {
   // expected-error@+1 {{'tosa.conv3d' op illegal: requires [int16] but not enabled in target}}
-  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = i48, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>} : (tensor<1x4x8x21x17xi16>, tensor<34x1x1x1x17xi8>, tensor<34xi48>, tensor<1xi16>, tensor<1xi8>) -> tensor<1x4x8x21x34xi48>
+  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = i48, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>} : (tensor<1x4x8x21x17xi16>, tensor<34x1x1x1x17xi8>, tensor<21xi48>, tensor<1xi16>, tensor<1xi8>) -> tensor<1x4x8x21x34xi48>
   return %0 : tensor<1x4x8x21x34xi48>
 }
 
@@ -313,17 +313,17 @@ func.func @test_identity(%arg0: tensor<13x21x3xi4>) -> tensor<13x21x3xi4> {
 func.func @test_variable_read_type(%arg0: tensor<2x4x8xi8>) -> () {
   // expected-error@+1 {{'tosa.variable' op illegal: requires [variable] but not enabled in target}}
   tosa.variable @stored_var = dense<-1> : tensor<2x4x8xi8>
-  // expected-error@+1 {{'tosa.variable.read' op illegal: requires [variable]}}
-  %0 = tosa.variable.read @stored_var : tensor<2x4x8xi16>
+  // expected-error@+1 {{'tosa.variable_read' op illegal: requires [variable]}}
+  %0 = tosa.variable_read @stored_var : tensor<2x4x8xi8>
   return
 }
 
 // -----
-func.func @test_variable_write_type(%arg0: tensor<2x4x8xi16>) -> () {
+func.func @test_variable_write_type(%arg0: tensor<2x4x8xi8>) -> () {
   // expected-error@+1 {{'tosa.variable' op illegal: requires [variable] but not enabled in target}}
   tosa.variable @stored_var = dense<-1> : tensor<2x4x8xi8>
-  // expected-error@+1 {{'tosa.variable.write' op illegal: requires [variable]}}
-  tosa.variable.write @stored_var, %arg0 : tensor<2x4x8xi16>
+  // expected-error@+1 {{'tosa.variable_write' op illegal: requires [variable]}}
+  tosa.variable_write @stored_var, %arg0 : tensor<2x4x8xi8>
   return
 }
 
@@ -445,10 +445,10 @@ func.func @test_conv2d_non_const_input_zp(%arg0: tensor<1x4x4x4xi8>, %arg1: tens
 
 // -----
 
-func.func @test_conv3d_non_const_weight_zp(%arg0: tensor<1x4x8x21x17xi8>, %arg1: tensor<34x1x1x1x17xi8>, %arg2: tensor<34xi32>, %arg3: tensor<1xi8>) -> tensor<1x4x8x21x34xi32> {
+func.func @test_conv3d_non_const_weight_zp(%arg0: tensor<1x4x8x21x17xi8>, %arg1: tensor<34x1x1x1x17xi8>, %arg2: tensor<21xi32>, %arg3: tensor<1xi8>) -> tensor<1x4x8x21x34xi32> {
   %input_zp = "tosa.const"() {values = dense<0> : tensor<1xi8> } : () -> tensor<1xi8>
   // expected-error@+1 {{'tosa.conv3d' op expected compile time resolvable constant, but got variable value for operand #4}}
-  %0 = tosa.conv3d %arg0, %arg1, %arg2, %input_zp, %arg3 {acc_type = i32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>} : (tensor<1x4x8x21x17xi8>, tensor<34x1x1x1x17xi8>, tensor<34xi32>, tensor<1xi8>, tensor<1xi8>) -> tensor<1x4x8x21x34xi32>
+  %0 = tosa.conv3d %arg0, %arg1, %arg2, %input_zp, %arg3 {acc_type = i32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>} : (tensor<1x4x8x21x17xi8>, tensor<34x1x1x1x17xi8>, tensor<21xi32>, tensor<1xi8>, tensor<1xi8>) -> tensor<1x4x8x21x34xi32>
   return %0 : tensor<1x4x8x21x34xi32>
 }
 
diff --git a/mlir/test/Dialect/Tosa/level_check.mlir b/mlir/test/Dialect/Tosa/level_check.mlir
index b48f614770fcb..5307645324b81 100644
--- a/mlir/test/Dialect/Tosa/level_check.mlir
+++ b/mlir/test/Dialect/Tosa/level_check.mlir
@@ -619,182 +619,182 @@ func.func @test_conv2d_stride_x(%arg0: tensor<1x32x32x8xf32>, %arg1: tensor<16x2
 
 // -----
 
-func.func @test_conv3d_dilation_d(%arg0: tensor<1x1x32x32x8xf32>, %arg1: tensor<16x2x2x2x8xf32>, %arg2: tensor<16xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x1x32x32x16xf32> {
+func.func @test_conv3d_dilation_d(%arg0: tensor<1x1x32x32x8xf32>, %arg1: tensor<16x2x2x2x8xf32>, %arg2: tensor<16xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<*xf32> {
   // expected-error@+1 {{'tosa.conv3d' op failed level check: dilation_d * KD <= MAX_KERNEL}}
   %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 4097, 1, 1>, pad = array<i64: 0, 1, 0, 1, 0, 1>, stride = array<i64: 1, 1, 1>} :
-            (tensor<1x1x32x32x8xf32>, tensor<16x2x2x2x8xf32>, tensor<16xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x1x32x32x16xf32>
-  return %0 : tensor<1x1x32x32x16xf32>
+            (tensor<1x1x32x32x8xf32>, tensor<16x2x2x2x8xf32>, tensor<16xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<*xf32>
+  return %0 : tensor<*xf32>
 }
 
 // -----
 
-func.func @test_conv3d_dilation_y(%arg0: tensor<1x1x32x32x8xf32>, %arg1: tensor<16x2x2x2x8xf32>, %arg2: tensor<16xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x1x32x32x16xf32> {
+func.func @test_conv3d_dilation_y(%arg0: tensor<1x1x32x32x8xf32>, %arg1: tensor<16x2x2x2x8xf32>, %arg2: tensor<16xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<*xf32> {
   // expected-error@+1 {{'tosa.conv3d' op failed level check: dilation_y * KH <= MAX_KERNEL}}
   %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 4097, 1>, pad = array<i64: 0, 1, 0, 1, 0, 1>, stride = array<i64: 1, 1, 1>} :
-            (tensor<1x1x32x32x8xf32>, tensor<16x2x2x2x8xf32>, tensor<16xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x1x32x32x16xf32>
-  return %0 : tensor<1x1x32x32x16xf32>
+            (tensor<1x1x32x32x8xf32>, tensor<16x2x2x2x8xf32>, tensor<16xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<*xf32>
+  return %0 : tensor<*xf32>
 }
 
 // -----
 
-func.func @test_conv3d_dilation_x(%arg0: tensor<1x1x32x32x8xf32>, %arg1: tensor<16x2x2x2x8xf32>, %arg2: tensor<16xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x1x32x32x16xf32> {
+func.func @test_conv3d_dilation_x(%arg0: tensor<1x1x32x32x8xf32>, %arg1: tensor<16x2x2x2x8xf32>, %arg2: tensor<16xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<*xf32> {
   // expected-error@+1 {{'tosa.conv3d' op failed level check: dilation_x * KW <= MAX_KERNEL}}
   %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 4097>, pad = array<i64: 0, 1, 0, 1, 0, 1>, stride = array<i64: 1, 1, 1>} :
-            (tensor<1x1x32x32x8xf32>, tensor<16x2x2x2x8xf32>, tensor<16xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x1x32x32x16xf32>
-  return %0 : tensor<1x1x32x32x16xf32>
+            (tensor<1x1x32x32x8xf32>, tensor<16x2x2x2x8xf32>, tensor<16xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<*xf32>
+  return %0 : tensor<*xf32>
 }
 
 // -----
 
-func.func @test_conv3d_pad_d0(%arg0: tensor<1x1x32x32x8xf32>, %arg1: tensor<16x2x2x2x8xf32>, %arg2: tensor<16xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x1x32x32x16xf32> {
+func.func @test_conv3d_pad_d0(%arg0: tensor<1x1x32x32x8xf32>, %arg1: tensor<16x2x2x2x8xf32>, %arg2: tensor<16xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<*xf32> {
   // expected-error@+1 {{'tosa.conv3d' op failed level check: pad <= MAX_KERNEL}}
   %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 8193, 1, 0, 1, 0, 1>, stride = array<i64: 1, 1, 1>} :
-            (tensor<1x1x32x32x8xf32>, tensor<16x2x2x2x8xf32>, tensor<16xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x1x32x32x16xf32>
-  return %0 : tensor<1x1x32x32x16xf32>
+            (tensor<1x1x32x32x8xf32>, tensor<16x2x2x2x8xf32>, tensor<16xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<*xf32>
+  return %0 : tensor<*xf32>
 }
 
 // -----
 
-func.func @test_conv3d_pad_d1(%arg0: tensor<1x1x32x32x8xf32>, %arg1: tensor<16x2x2x2x8xf32>, %arg2: tensor<16xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x1x32x32x16xf32> {
+func.func @test_conv3d_pad_d1(%arg0: tensor<1x1x32x32x8xf32>, %arg1: tensor<16x2x2x2x8xf32>, %arg2: tensor<16xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<*xf32> {
   // expected-error@+1 {{'tosa.conv3d' op failed level check: pad <= MAX_KERNEL}}
   %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 1, 8193, 0, 1, 0, 1>, stride = array<i64: 1, 1, 1>} :
-            (tensor<1x1x32x32x8xf32>, tensor<16x2x2x2x8xf32>, tensor<16xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x1x32x32x16xf32>
-  return %0 : tensor<1x1x32x32x16xf32>
+            (tensor<1x1x32x32x8xf32>, tensor<16x2x2x2x8xf32>, tensor<16xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<*xf32>
+  return %0 : tensor<*xf32>
 }
 
 // -----
 
-func.func @test_conv3d_pad_top(%arg0: tensor<1x1x32x32x8xf32>, %arg1: tensor<16x2x2x2x8xf32>, %arg2: tensor<16xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x1x32x32x16xf32> {
+func.func @test_conv3d_pad_top(%arg0: tensor<1x1x32x32x8xf32>, %arg1: tensor<16x2x2x2x8xf32>, %arg2: tensor<16xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<*xf32> {
   // expected-error@+1 {{'tosa.conv3d' op failed level check: pad <= MAX_KERNEL}}
   %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 1, 8193, 1, 0, 1>, stride = array<i64: 1, 1, 1>} :
-            (tensor<1x1x32x32x8xf32>, tensor<16x2x2x2x8xf32>, tensor<16xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x1x32x32x16xf32>
-  return %0 : tensor<1x1x32x32x16xf32>
+            (tensor<1x1x32x32x8xf32>, tensor<16x2x2x2x8xf32>, tensor<16xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<*xf32>
+  return %0 : tensor<*xf32>
 }
 
 // -----
 
-func.func @test_conv3d_pad_bottom(%arg0: tensor<1x1x32x32x8xf32>, %arg1: tensor<16x2x2x2x8xf32>, %arg2: tensor<16xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x1x32x32x16xf32> {
+func.func @test_conv3d_pad_bottom(%arg0: tensor<1x1x32x32x8xf32>, %arg1: tensor<16x2x2x2x8xf32>, %arg2: tensor<16xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<*xf32> {
   // expected-error@+1 {{'tosa.conv3d' op failed level check: pad <= MAX_KERNEL}}
   %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 1, 0, 8193, 0, 1>, stride = array<i64: 1, 1, 1>} :
-            (tensor<1x1x32x32x8xf32>, tensor<16x2x2x2x8xf32>, tensor<16xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x1x32x32x16xf32>
-  return %0 : tensor<1x1x32x32x16xf32>
+            (tensor<1x1x32x32x8xf32>, tensor<16x2x2x2x8xf32>, tensor<16xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<*xf32>
+  return %0 : tensor<*xf32>
 }
 
 // -----
 
-func.func @test_conv3d_pad_left(%arg0: tensor<1x1x32x32x8xf32>, %arg1: tensor<16x2x2x2x8xf32>, %arg2: tensor<16xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x1x32x32x16xf32> {
+func.func @test_conv3d_pad_left(%arg0: tensor<1x1x32x32x8xf32>, %arg1: tensor<16x2x2x2x8xf32>, %arg2: tensor<16xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<*xf32> {
   // expected-error@+1 {{'tosa.conv3d' op failed level check: pad <= MAX_KERNEL}}
   %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 1, 0, 1, 8193, 1>, stride = array<i64: 1, 1, 1>} :
-            (tensor<1x1x32x32x8xf32>, tensor<16x2x2x2x8xf32>, tensor<16xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x1x32x32x16xf32>
-  return %0 : tensor<1x1x32x32x16xf32>
+            (tensor<1x1x32x32x8xf32>, tensor<16x2x2x2x8xf32>, tensor<16xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<*xf32>
+  return %0 : tensor<*xf32>
 }
 
 // -----
 
-func.func @test_conv3d_pad_right(%arg0: tensor<1x1x32x32x8xf32>, %arg1: tensor<16x2x2x2x8xf32>, %arg2: tensor<16xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x1x32x32x16xf32> {
+func.func @test_conv3d_pad_right(%arg0: tensor<1x1x32x32x8xf32>, %arg1: tensor<16x2x2x2x8xf32>, %arg2: tensor<16xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<*xf32> {
   // expected-error@+1 {{'tosa.conv3d' op failed level check: pad <= MAX_KERNEL}}
   %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 1, 0, 1, 0, 8193>, stride = array<i64: 1, 1, 1>} :
-            (tensor<1x1x32x32x8xf32>, tensor<16x2x2x2x8xf32>, tensor<16xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x1x32x32x16xf32>
-  return %0 : tensor<1x1x32x32x16xf32>
+            (tensor<1x1x32x32x8xf32>, tensor<16x2x2x2x8xf32>, tensor<16xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<*xf32>
+  return %0 : tensor<*xf32>
 }
 
 // -----
 
-func.func @test_conv3d_stride_d(%arg0: tensor<1x1x32x32x8xf32>, %arg1: tensor<16x2x2x2x8xf32>, %arg2: tensor<16xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x1x32x32x16xf32> {
+func.func @test_conv3d_stride_d(%arg0: tensor<1x1x32x32x8xf32>, %arg1: tensor<16x2x2x2x8xf32>, %arg2: tensor<16xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<*xf32> {
   // expected-error@+1 {{'tosa.conv3d' op failed level check: stride <= MAX_STRIDE}}
   %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 1, 0, 1, 0, 1>, stride = array<i64: 8193, 1, 1>} :
-            (tensor<1x1x32x32x8xf32>, tensor<16x2x2x2x8xf32>, tensor<16xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x1x32x32x16xf32>
-  return %0 : tensor<1x1x32x32x16xf32>
+            (tensor<1x1x32x32x8xf32>, tensor<16x2x2x2x8xf32>, tensor<16xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<*xf32>
+  return %0 : tensor<*xf32>
 }
 
 // -----
 
-func.func @test_conv3d_stride_y(%arg0: tensor<1x1x32x32x8xf32>, %arg1: tensor<16x2x2x2x8xf32>, %arg2: tensor<16xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x1x32x32x16xf32> {
+func.func @test_conv3d_stride_y(%arg0: tensor<1x1x32x32x8xf32>, %arg1: tensor<16x2x2x2x8xf32>, %arg2: tensor<16xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<*xf32> {
   // expected-error@+1 {{'tosa.conv3d' op failed level check: stride <= MAX_STRIDE}}
   %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 1, 0, 1, 0, 1>, stride = array<i64: 1, 8193, 1>} :
-            (tensor<1x1x32x32x8xf32>, tensor<16x2x2x2x8xf32>, tensor<16xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x1x32x32x16xf32>
-  return %0 : tensor<1x1x32x32x16xf32>
+            (tensor<1x1x32x32x8xf32>, tensor<16x2x2x2x8xf32>, tensor<16xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<*xf32>
+  return %0 : tensor<*xf32>
 }
 
 // -----
 
-func.func @test_conv3d_stride_x(%arg0: tensor<1x1x32x32x8xf32>, %arg1: tensor<16x2x2x2x8xf32>, %arg2: tensor<16xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x1x32x32x16xf32> {
+func.func @test_conv3d_stride_x(%arg0: tensor<1x1x32x32x8xf32>, %arg1: tensor<16x2x2x2x8xf32>, %arg2: tensor<16xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<*xf32> {
   // expected-error@+1 {{'tosa.conv3d' op failed level check: stride <= MAX_STRIDE}}
   %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 1, 0, 1, 0, 1>, stride = array<i64: 1, 1, 8193>} :
-            (tensor<1x1x32x32x8xf32>, tensor<16x2x2x2x8xf32>, tensor<16xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x1x32x32x16xf32>
-  return %0 : tensor<1x1x32x32x16xf32>
+            (tensor<1x1x32x32x8xf32>, tensor<16x2x2x2x8xf32>, tensor<16xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<*xf32>
+  return %0 : tensor<*xf32>
 }
 
 // -----
 
-func.func @test_depthwise_conv2d_dilation_y(%arg0: tensor<1x32x32x8xf32>, %arg1: tensor<2x2x8x8xf32>, %arg2: tensor<64xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x32x32x64xf32> {
+func.func @test_depthwise_conv2d_dilation_y(%arg0: tensor<1x32x32x8xf32>, %arg1: tensor<2x2x8x8xf32>, %arg2: tensor<64xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<*xf32> {
   // expected-error@+1 {{'tosa.depthwise_conv2d' op failed level check: dilation_y * KH <= MAX_KERNEL}}
   %0 = tosa.depthwise_conv2d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 4097, 1>, pad = array<i64: 0, 1, 0, 1>, stride = array<i64: 1, 1>} :
-            (tensor<1x32x32x8xf32>, tensor<2x2x8x8xf32>, tensor<64xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x32x32x64xf32>
-  return %0 : tensor<1x32x32x64xf32>
+            (tensor<1x32x32x8xf32>, tensor<2x2x8x8xf32>, tensor<64xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<*xf32>
+  return %0 : tensor<*xf32>
 }
 
 // -----
 
-func.func @test_depthwise_conv2d_dilation_x(%arg0: tensor<1x32x32x8xf32>, %arg1: tensor<2x2x8x8xf32>, %arg2: tensor<64xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x32x32x64xf32> {
+func.func @test_depthwise_conv2d_dilation_x(%arg0: tensor<1x32x32x8xf32>, %arg1: tensor<2x2x8x8xf32>, %arg2: tensor<64xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<*xf32> {
   // expected-error@+1 {{'tosa.depthwise_conv2d' op failed level check: dilation_x * KW <= MAX_KERNEL}}
   %0 = tosa.depthwise_conv2d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 4097>, pad = array<i64: 0, 1, 0, 1>, stride = array<i64: 1, 1>} :
-            (tensor<1x32x32x8xf32>, tensor<2x2x8x8xf32>, tensor<64xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x32x32x64xf32>
-  return %0 : tensor<1x32x32x64xf32>
+            (tensor<1x32x32x8xf32>, tensor<2x2x8x8xf32>, tensor<64xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<*xf32>
+  return %0 : tensor<*xf32>
 }
 
 // -----
 
-func.func @test_depthwise_conv2d_pad_top(%arg0: tensor<1x32x32x8xf32>, %arg1: tensor<2x2x8x8xf32>, %arg2: tensor<64xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x32x32x64xf32> {
+func.func @test_depthwise_conv2d_pad_top(%arg0: tensor<1x32x32x8xf32>, %arg1: tensor<2x2x8x8xf32>, %arg2: tensor<64xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<*xf32> {
   // expected-error@+1 {{'tosa.depthwise_conv2d' op failed level check: pad <= MAX_KERNEL}}
   %0 = tosa.depthwise_conv2d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1>, pad = array<i64: 8193, 1, 0, 1>, stride = array<i64: 1, 1>} :
-            (tensor<1x32x32x8xf32>, tensor<2x2x8x8xf32>, tensor<64xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x32x32x64xf32>
-  return %0 : tensor<1x32x32x64xf32>
+            (tensor<1x32x32x8xf32>, tensor<2x2x8x8xf32>, tensor<64xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<*xf32>
+  return %0 : tensor<*xf32>
 }
 
 // -----
 
-func.func @test_depthwise_conv2d_pad_bottom(%arg0: tensor<1x32x32x8xf32>, %arg1: tensor<2x2x8x8xf32>, %arg2: tensor<64xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x32x32x64xf32> {
+func.func @test_depthwise_conv2d_pad_bottom(%arg0: tensor<1x32x32x8xf32>, %arg1: tensor<2x2x8x8xf32>, %arg2: tensor<64xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<*xf32> {
   // expected-error@+1 {{'tosa.depthwise_conv2d' op failed level check: pad <= MAX_KERNEL}}
   %0 = tosa.depthwise_conv2d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1>, pad = array<i64: 0, 8193, 0, 1>, stride = array<i64: 1, 1>} :
-            (tensor<1x32x32x8xf32>, tensor<2x2x8x8xf32>, tensor<64xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x32x32x64xf32>
-  return %0 : tensor<1x32x32x64xf32>
+            (tensor<1x32x32x8xf32>, tensor<2x2x8x8xf32>, tensor<64xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<*xf32>
+  return %0 : tensor<*xf32>
 }
 
 // -----
 
-func.func @test_depthwise_conv2d_pad_left(%arg0: tensor<1x32x32x8xf32>, %arg1: tensor<2x2x8x8xf32>, %arg2: tensor<64xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x32x32x64xf32> {
+func.func @test_depthwise_conv2d_pad_left(%arg0: tensor<1x32x32x8xf32>, %arg1: tensor<2x2x8x8xf32>, %arg2: tensor<64xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<*xf32> {
   // expected-error@+1 {{'tosa.depthwise_conv2d' op failed level check: pad <= MAX_KERNEL}}
   %0 = tosa.depthwise_conv2d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1>, pad = array<i64: 0, 1, 8193, 1>, stride = array<i64: 1, 1>} :
-            (tensor<1x32x32x8xf32>, tensor<2x2x8x8xf32>, tensor<64xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x32x32x64xf32>
-  return %0 : tensor<1x32x32x64xf32>
+            (tensor<1x32x32x8xf32>, tensor<2x2x8x8xf32>, tensor<64xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<*xf32>
+  return %0 : tensor<*xf32>
 }
 
 // -----
 
-func.func @test_depthwise_conv2d_pad_right(%arg0: tensor<1x32x32x8xf32>, %arg1: tensor<2x2x8x8xf32>, %arg2: tensor<64xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x32x32x64xf32> {
+func.func @test_depthwise_conv2d_pad_right(%arg0: tensor<1x32x32x8xf32>, %arg1: tensor<2x2x8x8xf32>, %arg2: tensor<64xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<*xf32> {
   // expected-error@+1 {{'tosa.depthwise_conv2d' op failed level check: pad <= MAX_KERNEL}}
   %0 = tosa.depthwise_conv2d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1>, pad = array<i64: 0, 1, 0, 8193>, stride = array<i64: 1, 1>} :
-            (tensor<1x32x32x8xf32>, tensor<2x2x8x8xf32>, tensor<64xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x32x32x64xf32>
-  return %0 : tensor<1x32x32x64xf32>
+            (tensor<1x32x32x8xf32>, tensor<2x2x8x8xf32>, tensor<64xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<*xf32>
+  return %0 : tensor<*xf32>
 }
 
 // -----
 
-func.func @test_depthwise_conv2d_stride_y(%arg0: tensor<1x32x32x8xf32>, %arg1: tensor<2x2x8x8xf32>, %arg2: tensor<64xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x32x32x64xf32> {
+func.func @test_depthwise_conv2d_stride_y(%arg0: tensor<1x32x32x8xf32>, %arg1: tensor<2x2x8x8xf32>, %arg2: tensor<64xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<*xf32> {
   // expected-error@+1 {{'tosa.depthwise_conv2d' op failed level check: stride <= MAX_STRIDE}}
   %0 = tosa.depthwise_conv2d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1>, pad = array<i64: 0, 1, 0, 1>, stride = array<i64: 8193, 1>} :
-            (tensor<1x32x32x8xf32>, tensor<2x2x8x8xf32>, tensor<64xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x32x32x64xf32>
-  return %0 : tensor<1x32x32x64xf32>
+            (tensor<1x32x32x8xf32>, tensor<2x2x8x8xf32>, tensor<64xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<*xf32>
+  return %0 : tensor<*xf32>
 }
 
 // -----
 
-func.func @test_depthwise_conv2d_stride_x(%arg0: tensor<1x32x32x8xf32>, %arg1: tensor<2x2x8x8xf32>, %arg2: tensor<64xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x32x32x64xf32> {
+func.func @test_depthwise_conv2d_stride_x(%arg0: tensor<1x32x32x8xf32>, %arg1: tensor<2x2x8x8xf32>, %arg2: tensor<64xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<*xf32> {
   // expected-error@+1 {{'tosa.depthwise_conv2d' op failed level check: stride <= MAX_STRIDE}}
   %0 = tosa.depthwise_conv2d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1>, pad = array<i64: 0, 1, 0, 1>, stride = array<i64: 1, 8193>} :
-            (tensor<1x32x32x8xf32>, tensor<2x2x8x8xf32>, tensor<64xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x32x32x64xf32>
-  return %0 : tensor<1x32x32x64xf32>
+            (tensor<1x32x32x8xf32>, tensor<2x2x8x8xf32>, tensor<64xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<*xf32>
+  return %0 : tensor<*xf32>
 }
 
 // -----
@@ -1089,10 +1089,10 @@ func.func @test_scatter_tensor_size_invalid(%arg0: tensor<13x210000000x3xf32>, %
 
 func.func @test_variable_read_write_tensor_size_invalid() -> () {
   tosa.variable @stored_var = dense<3.14> : tensor<536870912xf32>
-  // expected-error@+1 {{'tosa.variable.read' op failed level check: result tensor size (in bytes) <= (1 << MAX_LOG2_SIZE - 1)}}
-  %0 = tosa.variable.read @stored_var : tensor<536870912xf32>
-  // expected-error@+1 {{'tosa.variable.write' op failed level check: operand tensor size (in bytes) <= (1 << MAX_LOG2_SIZE - 1)}}
-  tosa.variable.write @stored_var, %0 : tensor<536870912xf32>
+  // expected-error@+1 {{'tosa.variable_read' op failed level check: result tensor size (in bytes) <= (1 << MAX_LOG2_SIZE - 1)}}
+  %0 = tosa.variable_read @stored_var : tensor<536870912xf32>
+  // expected-error@+1 {{'tosa.variable_write' op failed level check: operand tensor size (in bytes) <= (1 << MAX_LOG2_SIZE - 1)}}
+  tosa.variable_write @stored_var, %0 : tensor<536870912xf32>
   return
 }
 
@@ -1157,10 +1157,10 @@ func.func @test_cond_if_rank_invalid(%arg0: tensor<1x1x1x1x1x1x1x1xf32>, %arg1:
 func.func @test_variable_read_write_rank_invalid() -> () {
   // expected-error@+1 {{'tosa.variable' op failed level check: attribute rank(shape) <= MAX_RANK}}
   tosa.variable @stored_var = dense<3.14> : tensor<1x1x1x1x1x1x1x1xf32>
-  // expected-error@+1 {{'tosa.variable.read' op failed level check: result rank(shape) <= MAX_RANK}}
-  %0 = tosa.variable.read @stored_var : tensor<1x1x1x1x1x1x1x1xf32>
-  // expected-error@+1 {{'tosa.variable.write' op failed level check: operand rank(shape) <= MAX_RANK}}
-  tosa.variable.write @stored_var, %0 : tensor<1x1x1x1x1x1x1x1xf32>
+  // expected-error@+1 {{'tosa.variable_read' op failed level check: result rank(shape) <= MAX_RANK}}
+  %0 = tosa.variable_read @stored_var : tensor<1x1x1x1x1x1x1x1xf32>
+  // expected-error@+1 {{'tosa.variable_write' op failed level check: operand rank(shape) <= MAX_RANK}}
+  tosa.variable_write @stored_var, %0 : tensor<1x1x1x1x1x1x1x1xf32>
   return
 }
 
diff --git a/mlir/test/Dialect/Tosa/ops.mlir b/mlir/test/Dialect/Tosa/ops.mlir
index b64074e412ed1..c1181825f0c97 100644
--- a/mlir/test/Dialect/Tosa/ops.mlir
+++ b/mlir/test/Dialect/Tosa/ops.mlir
@@ -104,15 +104,15 @@ func.func @test_conv2d_q8xi4(%arg0: tensor<1x11x11x3xi8>) -> tensor<1x1x1x3xi8>
 
 // -----
 // CHECK-LABEL: conv3d
-func.func @test_conv3d(%arg0: tensor<1x4x8x21x17xf32>, %arg1: tensor<34x1x1x1x17xf32>, %arg2: tensor<34xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x4x8x21x34xf32> {
-  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>} : (tensor<1x4x8x21x17xf32>, tensor<34x1x1x1x17xf32>, tensor<34xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x4x8x21x34xf32>
+func.func @test_conv3d(%arg0: tensor<1x4x8x21x17xf32>, %arg1: tensor<34x1x1x1x17xf32>, %arg2: tensor<21xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x4x8x21x34xf32> {
+  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>} : (tensor<1x4x8x21x17xf32>, tensor<34x1x1x1x17xf32>, tensor<21xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x4x8x21x34xf32>
   return %0 : tensor<1x4x8x21x34xf32>
 }
 
 // -----
 // CHECK-LABEL: conv3d_with_local_bound
-func.func @test_conv3d_with_local_bound(%arg0: tensor<1x4x8x21x17xf32>, %arg1: tensor<34x1x1x1x17xf32>, %arg2: tensor<34xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x4x8x21x34xf32> {
-  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>, local_bound = true} : (tensor<1x4x8x21x17xf32>, tensor<34x1x1x1x17xf32>, tensor<34xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x4x8x21x34xf32>
+func.func @test_conv3d_with_local_bound(%arg0: tensor<1x4x8x21x17xf32>, %arg1: tensor<34x1x1x1x17xf32>, %arg2: tensor<21xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x4x8x21x34xf32> {
+  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>, local_bound = true} : (tensor<1x4x8x21x17xf32>, tensor<34x1x1x1x17xf32>, tensor<21xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x4x8x21x34xf32>
   return %0 : tensor<1x4x8x21x34xf32>
 }
 
@@ -823,8 +823,8 @@ func.func @test_conv2d_f8E5M2(%arg0: tensor<1x4x4x4xf8E5M2>, %arg1: tensor<8x1x1
 
 // -----
 // CHECK-LABEL: conv3d_f8E5M2
-func.func @test_conv3d_f8E5M2(%arg0: tensor<1x4x8x21x17xf8E5M2>, %arg1: tensor<34x1x1x1x17xf8E5M2>, %arg2: tensor<34xf16>, %arg3: tensor<1xf8E5M2>, %arg4: tensor<1xf8E5M2>) -> tensor<1x4x8x21x34xf16> {
-  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f16, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>} : (tensor<1x4x8x21x17xf8E5M2>, tensor<34x1x1x1x17xf8E5M2>, tensor<34xf16>, tensor<1xf8E5M2>, tensor<1xf8E5M2>) -> tensor<1x4x8x21x34xf16>
+func.func @test_conv3d_f8E5M2(%arg0: tensor<1x4x8x21x17xf8E5M2>, %arg1: tensor<34x1x1x1x17xf8E5M2>, %arg2: tensor<21xf16>, %arg3: tensor<1xf8E5M2>, %arg4: tensor<1xf8E5M2>) -> tensor<1x4x8x21x34xf16> {
+  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f16, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>} : (tensor<1x4x8x21x17xf8E5M2>, tensor<34x1x1x1x17xf8E5M2>, tensor<21xf16>, tensor<1xf8E5M2>, tensor<1xf8E5M2>) -> tensor<1x4x8x21x34xf16>
   return %0 : tensor<1x4x8x21x34xf16>
 }
 
@@ -968,8 +968,8 @@ func.func @test_conv2d_f8E4M3FN(%arg0: tensor<1x4x4x4xf8E4M3FN>, %arg1: tensor<8
 
 // -----
 // CHECK-LABEL: conv3d_f8E4M3FN
-func.func @test_conv3d_f8E4M3FN(%arg0: tensor<1x4x8x21x17xf8E4M3FN>, %arg1: tensor<34x1x1x1x17xf8E4M3FN>, %arg2: tensor<34xf16>, %arg3: tensor<1xf8E4M3FN>, %arg4: tensor<1xf8E4M3FN>) -> tensor<1x4x8x21x34xf16> {
-  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f16, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>} : (tensor<1x4x8x21x17xf8E4M3FN>, tensor<34x1x1x1x17xf8E4M3FN>, tensor<34xf16>, tensor<1xf8E4M3FN>, tensor<1xf8E4M3FN>) -> tensor<1x4x8x21x34xf16>
+func.func @test_conv3d_f8E4M3FN(%arg0: tensor<1x4x8x21x17xf8E4M3FN>, %arg1: tensor<34x1x1x1x17xf8E4M3FN>, %arg2: tensor<21xf16>, %arg3: tensor<1xf8E4M3FN>, %arg4: tensor<1xf8E4M3FN>) -> tensor<1x4x8x21x34xf16> {
+  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f16, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>} : (tensor<1x4x8x21x17xf8E4M3FN>, tensor<34x1x1x1x17xf8E4M3FN>, tensor<21xf16>, tensor<1xf8E4M3FN>, tensor<1xf8E4M3FN>) -> tensor<1x4x8x21x34xf16>
   return %0 : tensor<1x4x8x21x34xf16>
 }
 
diff --git a/mlir/test/Dialect/Tosa/profile_pro_fp_unsupported.mlir b/mlir/test/Dialect/Tosa/profile_pro_fp_unsupported.mlir
index 72669c62c95ca..efbb9e9d1843f 100644
--- a/mlir/test/Dialect/Tosa/profile_pro_fp_unsupported.mlir
+++ b/mlir/test/Dialect/Tosa/profile_pro_fp_unsupported.mlir
@@ -33,9 +33,9 @@ func.func @test_conv2d(%arg0: tensor<1x4x4x4xf32>, %arg1: tensor<8x1x1x4xf32>, %
 }
 
 // -----
-func.func @test_conv3d(%arg0: tensor<1x4x8x21x17xf16>, %arg1: tensor<34x1x1x1x17xf16>, %arg2: tensor<34xf16>, %arg3: tensor<1xf16>, %arg4: tensor<1xf16>) -> tensor<1x4x8x21x34xf16> {
+func.func @test_conv3d(%arg0: tensor<1x4x8x21x17xf16>, %arg1: tensor<34x1x1x1x17xf16>, %arg2: tensor<21xf16>, %arg3: tensor<1xf16>, %arg4: tensor<1xf16>) -> tensor<1x4x8x21x34xf16> {
   // expected-error@+1 {{'tosa.conv3d' op illegal: requires [pro_fp] but not enabled in target}}
-  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>} : (tensor<1x4x8x21x17xf16>, tensor<34x1x1x1x17xf16>, tensor<34xf16>, tensor<1xf16>, tensor<1xf16>) -> tensor<1x4x8x21x34xf16>
+  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>} : (tensor<1x4x8x21x17xf16>, tensor<34x1x1x1x17xf16>, tensor<21xf16>, tensor<1xf16>, tensor<1xf16>) -> tensor<1x4x8x21x34xf16>
   return %0 : tensor<1x4x8x21x34xf16>
 }
 
diff --git a/mlir/test/Dialect/Tosa/profile_pro_int_unsupported.mlir b/mlir/test/Dialect/Tosa/profile_pro_int_unsupported.mlir
index e98b906377b22..b102eea5699dd 100644
--- a/mlir/test/Dialect/Tosa/profile_pro_int_unsupported.mlir
+++ b/mlir/test/Dialect/Tosa/profile_pro_int_unsupported.mlir
@@ -38,9 +38,9 @@ func.func @test_conv2d(%arg0: tensor<1x4x4x4xi8>, %arg1: tensor<8x1x1x4xi8>, %ar
 }
 
 // -----
-func.func @test_conv3d(%arg0: tensor<1x4x8x21x17xi8>, %arg1: tensor<34x1x1x1x17xi8>, %arg2: tensor<34xi32>, %arg3: tensor<1xi8>, %arg4: tensor<1xi8>) -> tensor<1x4x8x21x34xi32> {
+func.func @test_conv3d(%arg0: tensor<1x4x8x21x17xi8>, %arg1: tensor<34x1x1x1x17xi8>, %arg2: tensor<21xi32>, %arg3: tensor<1xi8>, %arg4: tensor<1xi8>) -> tensor<1x4x8x21x34xi32> {
   // expected-error@+1 {{'tosa.conv3d' op illegal: requires [pro_int] but not enabled in target}}
-  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = i32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>} : (tensor<1x4x8x21x17xi8>, tensor<34x1x1x1x17xi8>, tensor<34xi32>, tensor<1xi8>, tensor<1xi8>) -> tensor<1x4x8x21x34xi32>
+  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = i32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>} : (tensor<1x4x8x21x17xi8>, tensor<34x1x1x1x17xi8>, tensor<21xi32>, tensor<1xi8>, tensor<1xi8>) -> tensor<1x4x8x21x34xi32>
   return %0 : tensor<1x4x8x21x34xi32>
 }
 
diff --git a/mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir b/mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
index fe9da2ac09650..c6ac8074c0326 100644
--- a/mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
+++ b/mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
@@ -824,27 +824,27 @@ func.func @conv2d_strided(%input: tensor<1x13x15x1xf32>, %weights: tensor<1x1x1x
 // -----
 
 // CHECK-LABEL: @conv3d_static
-func.func @conv3d_static(%input: tensor<2x8x9x10x3xf32>, %weights: tensor<5x3x6x4x3xf32>, %bias: tensor<5xf32>, %input_zp: tensor<1xf32>, %weight_zp: tensor<1xf32>) -> () {
+func.func @conv3d_static(%input: tensor<2x8x9x10x3xf32>, %weights: tensor<5x3x6x4x3xf32>, %bias: tensor<7xf32>, %input_zp: tensor<1xf32>, %weight_zp: tensor<1xf32>) -> () {
   // CHECK: -> tensor<2x6x4x7x5xf32>
-  %0 = tosa.conv3d %input, %weights, %bias, %input_zp, %weight_zp {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>} : (tensor<2x8x9x10x3xf32>, tensor<5x3x6x4x3xf32>, tensor<5xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<?x?x?x?x?xf32>
+  %0 = tosa.conv3d %input, %weights, %bias, %input_zp, %weight_zp {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>} : (tensor<2x8x9x10x3xf32>, tensor<5x3x6x4x3xf32>, tensor<7xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<?x?x?x?x?xf32>
   return
 }
 
 // -----
 
 // CHECK-LABEL: @conv3d_dynamic_input
-func.func @conv3d_dynamic_input(%arg0: tensor<?x?x?x?x?xf32>, %arg1: tensor<5x3x6x4x3xf32>, %arg2: tensor<5xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) {
+func.func @conv3d_dynamic_input(%arg0: tensor<?x?x?x?x?xf32>, %arg1: tensor<5x3x6x4x3xf32>, %arg2: tensor<7xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) {
   // CHECK: -> tensor<?x?x?x?x5xf32>
-  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>} : (tensor<?x?x?x?x?xf32>, tensor<5x3x6x4x3xf32>, tensor<5xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<?x?x?x?x?xf32>
+  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>} : (tensor<?x?x?x?x?xf32>, tensor<5x3x6x4x3xf32>, tensor<7xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<?x?x?x?x?xf32>
   return
 }
 
 // -----
 
 // CHECK-LABEL: @conv3d_dynamic_weight
-func.func @conv3d_dynamic_weight(%arg0: tensor<2x8x9x10x3xf32>, %arg1: tensor<?x?x?x?x?xf32>, %arg2: tensor<5xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) {
-  // CHECK: -> tensor<2x?x?x?x5xf32>
-  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>} : (tensor<2x8x9x10x3xf32>, tensor<?x?x?x?x?xf32>, tensor<5xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<?x?x?x?x?xf32>
+func.func @conv3d_dynamic_weight(%arg0: tensor<2x8x9x10x3xf32>, %arg1: tensor<?x?x?x?x?xf32>, %arg2: tensor<7xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) {
+  // CHECK: -> tensor<2x?x?x?x7xf32>
+  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>} : (tensor<2x8x9x10x3xf32>, tensor<?x?x?x?x?xf32>, tensor<7xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<?x?x?x?x?xf32>
   return
 }
 
@@ -860,27 +860,27 @@ func.func @conv3d_dynamic_bias(%arg0: tensor<2x8x9x10x3xf32>, %arg1: tensor<5x3x
 // -----
 
 // CHECK-LABEL: @conv3d_padded
-func.func @conv3d_padded(%arg0: tensor<2x8x9x10x3xf32>, %arg1: tensor<5x3x6x4x3xf32>, %arg2: tensor<5xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) {
+func.func @conv3d_padded(%arg0: tensor<2x8x9x10x3xf32>, %arg1: tensor<5x3x6x4x3xf32>, %arg2: tensor<18xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) {
   // CHECK: -> tensor<2x9x11x18x5xf32>
-  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 1, 2, 3, 4, 5, 6>, stride = array<i64: 1, 1, 1>} : (tensor<2x8x9x10x3xf32>, tensor<5x3x6x4x3xf32>, tensor<5xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<?x?x?x?x?xf32>
+  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 1, 2, 3, 4, 5, 6>, stride = array<i64: 1, 1, 1>} : (tensor<2x8x9x10x3xf32>, tensor<5x3x6x4x3xf32>, tensor<18xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<?x?x?x?x?xf32>
   return
 }
 
 // -----
 
 // CHECK-LABEL: @conv3d_dilated
-func.func @conv3d_dilated(%arg0: tensor<2x12x14x16x3xf32>, %arg1: tensor<5x3x6x2x3xf32>, %arg2: tensor<5xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) {
+func.func @conv3d_dilated(%arg0: tensor<2x12x14x16x3xf32>, %arg1: tensor<5x3x6x2x3xf32>, %arg2: tensor<12xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) {
   // CHECK: -> tensor<2x6x4x12x5xf32>
-  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 3, 2, 4>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>} : (tensor<2x12x14x16x3xf32>, tensor<5x3x6x2x3xf32>, tensor<5xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<?x?x?x?x?xf32>
+  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 3, 2, 4>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>} : (tensor<2x12x14x16x3xf32>, tensor<5x3x6x2x3xf32>, tensor<12xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<?x?x?x?x?xf32>
   return
 }
 
 // -----
 
 // CHECK-LABEL: @conv3d_strided
-func.func @conv3d_strided(%arg0: tensor<1x13x14x15x1xf32>, %arg1: tensor<1x1x1x1x1xf32>, %arg2: tensor<1xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) {
-  // CHECK: -> tensor<1x5x7x4x1xf32>
-  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 3, 2, 4>} : (tensor<1x13x14x15x1xf32>, tensor<1x1x1x1x1xf32>, tensor<1xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<?x?x?x?x?xf32>
+func.func @conv3d_strided(%arg0: tensor<1x13x17x17x1xf32>, %arg1: tensor<1x1x1x1x1xf32>, %arg2: tensor<1xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) {
+  // CHECK: -> tensor<1x5x9x5x1xf32>
+  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 3, 2, 4>} : (tensor<1x13x17x17x1xf32>, tensor<1x1x1x1x1xf32>, tensor<1xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<?x?x?x?x?xf32>
   return
 }
 
@@ -941,9 +941,9 @@ func.func @depthwise_conv2d_dilated(%arg0: tensor<2x12x14x3xf32>, %arg1: tensor<
 // -----
 
 // CHECK-LABEL: @depthwise_conv2d_strided
-func.func @depthwise_conv2d_strided(%arg0: tensor<1x13x14x1xf32>, %arg1: tensor<1x1x1x1xf32>, %arg2: tensor<1xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) {
-  // CHECK: -> tensor<1x5x7x1xf32>
-  %0 = tosa.depthwise_conv2d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1>, pad = array<i64: 0, 0, 0, 0>, stride = array<i64: 3, 2>} : (tensor<1x13x14x1xf32>, tensor<1x1x1x1xf32>, tensor<1xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x5x7x1xf32>
+func.func @depthwise_conv2d_strided(%arg0: tensor<1x13x15x1xf32>, %arg1: tensor<1x1x1x1xf32>, %arg2: tensor<1xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) {
+  // CHECK: -> tensor<1x5x8x1xf32>
+  %0 = tosa.depthwise_conv2d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1>, pad = array<i64: 0, 0, 0, 0>, stride = array<i64: 3, 2>} : (tensor<1x13x15x1xf32>, tensor<1x1x1x1xf32>, tensor<1xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x5x8x1xf32>
   return
 }
 
@@ -1396,7 +1396,6 @@ func.func @test_dynamic_batch_fft2d(%arg0: tensor<?x4x8xf32>, %arg1: tensor<?x4x
 func.func @test_unranked_equal(%arg0 : tensor<*xf32>, %arg1 : tensor<f32>) -> () {
   // CHECK: tosa.equal %arg0, %arg1 : (tensor<*xf32>, tensor<f32>) -> tensor<*xi1>
   %0 = tosa.equal %arg0, %arg1 : (tensor<*xf32>, tensor<f32>) -> tensor<*xi1>
-
   return
 }
 
diff --git a/mlir/test/Dialect/Tosa/variables.mlir b/mlir/test/Dialect/Tosa/variables.mlir
index 9a26aa0bc8bf4..6fa6b26155461 100644
--- a/mlir/test/Dialect/Tosa/variables.mlir
+++ b/mlir/test/Dialect/Tosa/variables.mlir
@@ -8,12 +8,12 @@
 func.func @test_variable_scalar(%arg0: tensor<f32>) -> () {
   // CHECK:           tosa.variable @stored_var = dense<3.140000e+00> : tensor<f32>
   tosa.variable @stored_var = dense<3.14> : tensor<f32>
-  // CHECK:           %[[STORED_VAL:.*]] = tosa.variable.read @stored_var : tensor<f32>
-  %0 = tosa.variable.read @stored_var : tensor<f32>
+  // CHECK:           %[[STORED_VAL:.*]] = tosa.variable_read @stored_var : tensor<f32>
+  %0 = tosa.variable_read @stored_var : tensor<f32>
   // CHECK:           %[[RESULT_ADD:.*]] = tosa.add %[[ADD_VAL]], %[[STORED_VAL]] : (tensor<f32>, tensor<f32>) -> tensor<f32>
   %1 = "tosa.add"(%arg0, %0) : (tensor<f32>, tensor<f32>) -> tensor<f32>
-  // CHECK:           tosa.variable.write @stored_var, %[[RESULT_ADD]] : tensor<f32>
-  tosa.variable.write @stored_var, %1 : tensor<f32>
+  // CHECK:           tosa.variable_write @stored_var, %[[RESULT_ADD]] : tensor<f32>
+  tosa.variable_write @stored_var, %1 : tensor<f32>
   return
 }
 
@@ -23,11 +23,11 @@ func.func @test_variable_scalar(%arg0: tensor<f32>) -> () {
 func.func @test_variable_tensor(%arg0: tensor<2x4x8xi32>) -> () {
   // CHECK:           tosa.variable @stored_var = dense<-1> : tensor<2x4x8xi32>
   tosa.variable @stored_var = dense<-1> : tensor<2x4x8xi32>
-  // CHECK:           %[[STORED_VAL:.*]] = tosa.variable.read @stored_var : tensor<2x4x8xi32>
-  %0 = tosa.variable.read @stored_var : tensor<2x4x8xi32>
+  // CHECK:           %[[STORED_VAL:.*]] = tosa.variable_read @stored_var : tensor<2x4x8xi32>
+  %0 = tosa.variable_read @stored_var : tensor<2x4x8xi32>
   // CHECK:           %[[RESULT_ADD:.*]] = tosa.add %[[ADD_VAL]], %[[STORED_VAL]] : (tensor<2x4x8xi32>, tensor<2x4x8xi32>) -> tensor<2x4x8xi32>
   %1 = "tosa.add"(%arg0, %0) : (tensor<2x4x8xi32>, tensor<2x4x8xi32>) -> tensor<2x4x8xi32>
-  // CHECK:           tosa.variable.write @stored_var, %[[RESULT_ADD]] : tensor<2x4x8xi32>
-  tosa.variable.write @stored_var, %1 : tensor<2x4x8xi32>
+  // CHECK:           tosa.variable_write @stored_var, %[[RESULT_ADD]] : tensor<2x4x8xi32>
+  tosa.variable_write @stored_var, %1 : tensor<2x4x8xi32>
   return
 }
diff --git a/mlir/test/Dialect/Tosa/verifier.mlir b/mlir/test/Dialect/Tosa/verifier.mlir
index efdd26a9346fb..262e6d4265ea6 100644
--- a/mlir/test/Dialect/Tosa/verifier.mlir
+++ b/mlir/test/Dialect/Tosa/verifier.mlir
@@ -167,3 +167,194 @@ func.func @test_scalar_slice(%arg0: tensor<f32>) -> tensor<f32> {
   %2 = tosa.slice %arg0, %0, %1 : (tensor<f32>, !tosa.shape<0>, !tosa.shape<0>) -> tensor<f32>
   return %2 : tensor<f32>
 }
+
+// -----
+
+func.func @test_depthwise_conv2d_invalid_padding(%arg0: tensor<1x4x4x4xf32>, %arg1: tensor<1x1x8x4xf32>, %arg2: tensor<8xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x4x4x8xf32> {
+  // expected-error@+1 {{'tosa.depthwise_conv2d' op expect all padding values to be >= 0, got 0, 0, -1, 0}}
+  %0 = tosa.depthwise_conv2d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1>, pad = array<i64: 0, 0, -1, 0>, stride = array<i64: 1, 1>, local_bound = true}
+    : (tensor<1x4x4x4xf32>, tensor<1x1x8x4xf32>, tensor<8xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x4x4x8xf32>
+  return %0 : tensor<1x4x4x8xf32>
+}
+
+// -----
+
+func.func @test_depthwise_conv2d_invalid_stride(%arg0: tensor<1x4x4x4xf32>, %arg1: tensor<1x1x8x4xf32>, %arg2: tensor<8xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x4x4x8xf32> {
+  // expected-error@+1 {{'tosa.depthwise_conv2d' op expect all stride values to be >= 1, got 0, 1}}
+  %0 = tosa.depthwise_conv2d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1>, pad = array<i64: 0, 0, 0, 0>, stride = array<i64: 0, 1>, local_bound = true}
+    : (tensor<1x4x4x4xf32>, tensor<1x1x8x4xf32>, tensor<8xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x4x4x8xf32>
+  return %0 : tensor<1x4x4x8xf32>
+}
+
+// -----
+
+func.func @test_depthwise_conv2d_invalid_dilation(%arg0: tensor<1x4x4x4xf32>, %arg1: tensor<1x1x8x4xf32>, %arg2: tensor<8xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x4x4x8xf32> {
+  // expected-error@+1 {{'tosa.depthwise_conv2d' op expect all dilation values to be >= 1, got 1, 0}}
+  %0 = tosa.depthwise_conv2d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 0>, pad = array<i64: 0, 0, 0, 0>, stride = array<i64: 1, 1>, local_bound = true}
+    : (tensor<1x4x4x4xf32>, tensor<1x1x8x4xf32>, tensor<8xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x4x4x8xf32>
+  return %0 : tensor<1x4x4x8xf32>
+}
+
+// -----
+
+func.func @test_depthwise_conv2d_wholly_divisible_height(%arg0: tensor<1x4x4x4xf32>, %arg1: tensor<1x1x8x4xf32>, %arg2: tensor<8xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x4x4x8xf32> {
+  // expected-error@+1 {{'tosa.depthwise_conv2d' op expected input_height - 1 + pad_top + pad_bottom - (kernel_height - 1) * dilation_y to be wholly divisible by stride_y, got (4 - 1 + 0 + 0 - (1 - 1) * 1) / 2}}
+  %0 = tosa.depthwise_conv2d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1>, pad = array<i64: 0, 0, 0, 0>, stride = array<i64: 2, 1>, local_bound = true}
+    : (tensor<1x4x4x4xf32>, tensor<1x1x8x4xf32>, tensor<8xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x4x4x8xf32>
+  return %0 : tensor<1x4x4x8xf32>
+}
+
+// -----
+
+func.func @test_depthwise_conv2d_wholly_divisible_width(%arg0: tensor<1x4x4x4xf32>, %arg1: tensor<1x1x8x4xf32>, %arg2: tensor<8xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x4x4x8xf32> {
+  // expected-error@+1 {{'tosa.depthwise_conv2d' op expected input_width - 1 + pad_left + pad_right - (kernel_width - 1) * dilation_x to be wholly divisible by stride_x, got (4 - 1 + 0 + 0 - (1 - 1) * 1) / 2}}
+  %0 = tosa.depthwise_conv2d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1>, pad = array<i64: 0, 0, 0, 0>, stride = array<i64: 1, 2>, local_bound = true}
+    : (tensor<1x4x4x4xf32>, tensor<1x1x8x4xf32>, tensor<8xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x4x4x8xf32>
+  return %0 : tensor<1x4x4x8xf32>
+}
+
+// -----
+
+func.func @test_depthwise_conv2d_unexpected_output_height(%arg0: tensor<1x4x4x4xf32>, %arg1: tensor<1x1x8x4xf32>, %arg2: tensor<8xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x6x4x8xf32> {
+  // expected-error@+1 {{'tosa.depthwise_conv2d' op calculated output height did not match expected: calculated=4, expected=6}}
+  %0 = tosa.depthwise_conv2d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1>, pad = array<i64: 0, 0, 0, 0>, stride = array<i64: 1, 1>, local_bound = true}
+    : (tensor<1x4x4x4xf32>, tensor<1x1x8x4xf32>, tensor<8xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x6x4x8xf32>
+  return %0 : tensor<1x6x4x8xf32>
+}
+
+// -----
+
+func.func @test_depthwise_conv2d_unexpected_output_width(%arg0: tensor<1x4x4x4xf32>, %arg1: tensor<1x1x8x4xf32>, %arg2: tensor<8xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x4x6x8xf32> {
+  // expected-error@+1 {{'tosa.depthwise_conv2d' op calculated output width did not match expected: calculated=4, expected=6}}
+  %0 = tosa.depthwise_conv2d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1>, pad = array<i64: 0, 0, 0, 0>, stride = array<i64: 1, 1>, local_bound = true}
+    : (tensor<1x4x4x4xf32>, tensor<1x1x8x4xf32>, tensor<8xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x4x6x8xf32>
+  return %0 : tensor<1x4x6x8xf32>
+}
+
+// -----
+
+func.func @test_depthwise_conv2d_invalid_bias_size(%arg0: tensor<1x4x4x4xf32>, %arg1: tensor<1x1x8x4xf32>, %arg2: tensor<7xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x4x4x8xf32> {
+  // expected-error@+1 {{'tosa.depthwise_conv2d' op bias channels expected to be equal to output channels (8) or 1, got 7}}
+  %0 = tosa.depthwise_conv2d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1>, pad = array<i64: 0, 0, 0, 0>, stride = array<i64: 1, 1>, local_bound = true}
+    : (tensor<1x4x4x4xf32>, tensor<1x1x8x4xf32>, tensor<7xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x4x4x8xf32>
+  return %0 : tensor<1x4x4x8xf32>
+}
+
+// -----
+
+func.func @test_conv3d_invalid_padding(%arg0: tensor<1x4x8x21x17xf32>, %arg1: tensor<34x1x1x1x17xf32>, %arg2: tensor<21xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x4x8x21x34xf32> {
+  // expected-error@+1 {{'tosa.conv3d' op expect all padding values to be >= 0, got 0, -1, 0, -1, 0, 0}}
+  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 2, 1>, pad = array<i64: 0, -1, 0, -1, 0, 0>, stride = array<i64: 1, 1, 1>}
+    : (tensor<1x4x8x21x17xf32>, tensor<34x1x1x1x17xf32>, tensor<21xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x4x8x21x34xf32>
+  return %0 : tensor<1x4x8x21x34xf32>
+}
+// -----
+
+func.func @test_conv3d_invalid_stride(%arg0: tensor<1x4x8x21x17xf32>, %arg1: tensor<34x1x1x1x17xf32>, %arg2: tensor<21xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x4x8x21x34xf32> {
+  // expected-error@+1 {{'tosa.conv3d' op expect all stride values to be >= 1, got 0, 1, 1}}
+  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 0, 1, 1>}
+    : (tensor<1x4x8x21x17xf32>, tensor<34x1x1x1x17xf32>, tensor<21xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x4x8x21x34xf32>
+  return %0 : tensor<1x4x8x21x34xf32>
+}
+
+// -----
+
+func.func @test_conv3d_invalid_dilation(%arg0: tensor<1x4x8x21x17xf32>, %arg1: tensor<34x1x1x1x17xf32>, %arg2: tensor<21xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x4x8x21x34xf32> {
+  // expected-error@+1 {{'tosa.conv3d' op expect all dilation values to be >= 1, got 1, 0, 1}}
+  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 0, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>}
+    : (tensor<1x4x8x21x17xf32>, tensor<34x1x1x1x17xf32>, tensor<21xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x4x8x21x34xf32>
+  return %0 : tensor<1x4x8x21x34xf32>
+}
+
+// -----
+
+func.func @test_conv3d_wholly_divisible_input_depth(%arg0: tensor<1x4x16x21x17xf32>, %arg1: tensor<34x1x1x1x17xf32>, %arg2: tensor<21xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x4x8x21x34xf32> {
+  // expected-error@+1 {{'tosa.conv3d' op expected input_depth - 1 + pad_front + pad_back - (kernel_depth - 1) * dilation_d to be wholly divisible by stride_d, got (4 - 1 + 0 + 0 - (1 - 1) * 1) / 2}}
+  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 2, 1, 1>}
+    : (tensor<1x4x16x21x17xf32>, tensor<34x1x1x1x17xf32>, tensor<21xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x4x8x21x34xf32>
+  return %0 : tensor<1x4x8x21x34xf32>
+}
+
+// -----
+
+func.func @test_conv3d_wholly_divisible_input_height(%arg0: tensor<1x4x10x21x17xf32>, %arg1: tensor<34x1x1x1x17xf32>, %arg2: tensor<21xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x4x8x21x34xf32> {
+  // expected-error@+1 {{'tosa.conv3d' op expected input_height - 1 + pad_top + pad_bottom - (kernel_height - 1) * dilation_y to be wholly divisible by stride_y, got (10 - 1 + 0 + 0 - (1 - 1) * 1) / 4}}
+  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 4, 1>}
+    : (tensor<1x4x10x21x17xf32>, tensor<34x1x1x1x17xf32>, tensor<21xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x4x8x21x34xf32>
+  return %0 : tensor<1x4x8x21x34xf32>
+}
+
+// -----
+
+func.func @test_conv3d_wholly_divisible_input_width(%arg0: tensor<1x4x8x21x19xf32>, %arg1: tensor<34x1x1x1x17xf32>, %arg2: tensor<21xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x4x8x21x34xf32> {
+  // expected-error@+1 {{'tosa.conv3d' op expected input_width - 1 + pad_left + pad_right - (kernel_width - 1) * dilation_x to be wholly divisible by stride_x, got (21 - 1 + 0 + 0 - (1 - 1) * 1) / 8}}
+  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 8>}
+    : (tensor<1x4x8x21x19xf32>, tensor<34x1x1x1x17xf32>, tensor<21xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x4x8x21x34xf32>
+  return %0 : tensor<1x4x8x21x34xf32>
+}
+
+// -----
+
+func.func @test_conv3d_wholly_divisible_output_depth(%arg0: tensor<1x4x10x21x17xf32>, %arg1: tensor<34x1x1x1x17xf32>, %arg2: tensor<21xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x3x10x21x34xf32> {
+  // expected-error@+1 {{'tosa.conv3d' op calculated output depth did not match expected: calculated=4, expected=3}}
+  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>}
+    : (tensor<1x4x10x21x17xf32>, tensor<34x1x1x1x17xf32>, tensor<21xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x3x10x21x34xf32>
+  return %0 : tensor<1x3x10x21x34xf32>
+}
+
+// -----
+
+func.func @test_conv3d_wholly_divisible_output_height(%arg0: tensor<1x4x16x21x17xf32>, %arg1: tensor<34x1x1x1x17xf32>, %arg2: tensor<21xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x4x8x21x34xf32> {
+  // expected-error@+1 {{'tosa.conv3d' op calculated output height did not match expected: calculated=16, expected=8}}
+  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>}
+    : (tensor<1x4x16x21x17xf32>, tensor<34x1x1x1x17xf32>, tensor<21xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x4x8x21x34xf32>
+  return %0 : tensor<1x4x8x21x34xf32>
+}
+
+// -----
+
+func.func @test_conv3d_wholly_divisible_output_width(%arg0: tensor<1x4x8x21x19xf32>, %arg1: tensor<34x1x1x1x17xf32>, %arg2: tensor<21xf32>, %arg3: tensor<1xf32>, %arg4: tensor<1xf32>) -> tensor<1x4x8x19x34xf32> {
+  // expected-error@+1 {{'tosa.conv3d' op calculated output width did not match expected: calculated=21, expected=19}}
+  %0 = tosa.conv3d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array<i64: 1, 1, 1>, pad = array<i64: 0, 0, 0, 0, 0, 0>, stride = array<i64: 1, 1, 1>}
+    : (tensor<1x4x8x21x19xf32>, tensor<34x1x1x1x17xf32>, tensor<21xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x4x8x19x34xf32>
+  return %0 : tensor<1x4x8x19x34xf32>
+}
+
+// -----
+
+func.func @test_concat_element_type_mismatch(%arg0 : tensor<1x2xf32>, %arg1 : tensor<2x2xf32>) -> tensor<?x?xi8> {
+  // expected-error@+1 {{'tosa.concat' op expect input and output to have same element type, got 'f32' and 'i8'}}
+  %0 = tosa.concat %arg0, %arg1 {axis = 0 : i32} : (tensor<1x2xf32>, tensor<2x2xf32>) -> tensor<?x?xi8>
+  return %0 : tensor<?x?xi8>
+}
+
+// -----
+
+func.func @test_concat_zero_inputs() {
+  // expected-error@+1 {{'tosa.concat' op expect at least one input}}
+  %0 = tosa.concat {axis = 0 : i32} : () -> tensor<*xf32>
+}
+
+// -----
+
+func.func @test_concat_axis_negative(%arg0: tensor<1x2xf32>, %arg1: tensor<2x2xf32>) -> tensor<2x2xf32> {
+  // expected-error@+1 {{'tosa.concat' op expect axis to be within range 0 < axis < rank(input1[firstRankedTensorIdx]), got -1}}
+  %0 = tosa.concat %arg0, %arg1 {axis = -1 : i32} : (tensor<1x2xf32>, tensor<2x2xf32>) -> tensor<2x2xf32>
+  return %0 : tensor<2x2xf32>
+}
+
+// -----
+
+func.func @test_concat_axis_out_of_range(%arg0: tensor<1x2xf32>, %arg1: tensor<2x2xf32>) -> tensor<2x2xf32> {
+  // expected-error@+1 {{'tosa.concat' op expect axis to be within range 0 < axis < rank(input1[firstRankedTensorIdx]), got 3}}
+  %0 = tosa.concat %arg0, %arg1 {axis = 3 : i32} : (tensor<1x2xf32>, tensor<2x2xf32>) -> tensor<2x2xf32>
+  return %0 : tensor<2x2xf32>
+}
+
+// -----
+
+func.func @test_concat_axis_sum_error(%arg0: tensor<1x2xf32>, %arg1: tensor<2x?xf32>) -> tensor<2x?xf32> {
+  // expected-error@+1 {{'tosa.concat' op requires sum of axis dimensions of input1 equal to output axis dimension, got 3 and 2}}
+  %0 = tosa.concat %arg0, %arg1 {axis = 0 : i32} : (tensor<1x2xf32>, tensor<2x?xf32>) -> tensor<2x?xf32>
+  return %0 : tensor<2x?xf32>
+}
diff --git a/mlir/test/Dialect/Vector/canonicalize.mlir b/mlir/test/Dialect/Vector/canonicalize.mlir
index 2d365ac2b4287..29a11f47481c8 100644
--- a/mlir/test/Dialect/Vector/canonicalize.mlir
+++ b/mlir/test/Dialect/Vector/canonicalize.mlir
@@ -165,6 +165,33 @@ func.func @extract_scalar_poison_idx(%a: vector<4x5xf32>) -> f32 {
   return %0 : f32
 }
 
+// -----
+
+// Similar to the test above, but the index is not a static constant.
+
+// CHECK-LABEL: @extract_scalar_poison_idx_non_cst
+func.func @extract_scalar_poison_idx_non_cst(%a: vector<4x5xf32>) -> f32 {
+  // CHECK-NEXT: %[[UB:.*]] = ub.poison : f32
+  //  CHECK-NOT: vector.extract
+  // CHECK-NEXT: return %[[UB]] : f32
+  %c_neg_1 = arith.constant -1 : index
+  %0 = vector.extract %a[%c_neg_1, 0] : f32 from vector<4x5xf32>
+  return %0 : f32
+}
+
+// -----
+
+// Similar to test above, but now the index is out-of-bounds.
+
+// CHECK-LABEL: @no_fold_extract_scalar_oob_idx
+func.func @no_fold_extract_scalar_oob_idx(%a: vector<4x5xf32>) -> f32 {
+  //  CHECK: vector.extract
+  %c_neg_2 = arith.constant -2 : index
+  %0 = vector.extract %a[%c_neg_2, 0] : f32 from vector<4x5xf32>
+  return %0 : f32
+}
+
+
 // -----
 
 // CHECK-LABEL: @extract_vector_poison_idx
@@ -3062,6 +3089,34 @@ func.func @insert_vector_poison_idx(%a: vector<4x5xf32>, %b: vector<5xf32>)
 
 // -----
 
+// Similar to the test above, but the index is not a static constant.
+
+// CHECK-LABEL: @insert_vector_poison_idx_non_cst
+func.func @insert_vector_poison_idx_non_cst(%a: vector<4x5xf32>, %b: vector<5xf32>)
+    -> vector<4x5xf32> {
+  // CHECK-NEXT: %[[UB:.*]] = ub.poison : vector<4x5xf32>
+  //  CHECK-NOT: vector.insert
+  // CHECK-NEXT: return %[[UB]] : vector<4x5xf32>
+  %c_neg_1 = arith.constant -1 : index
+  %0 = vector.insert %b, %a[%c_neg_1] : vector<5xf32> into vector<4x5xf32>
+  return %0 : vector<4x5xf32>
+}
+
+// -----
+
+// Similar to test above, but now the index is out-of-bounds.
+
+// CHECK-LABEL: @no_fold_insert_scalar_idx_oob
+func.func @no_fold_insert_scalar_idx_oob(%a: vector<4x5xf32>, %b: vector<5xf32>)
+    -> vector<4x5xf32> {
+  //  CHECK: vector.insert
+  %c_neg_2 = arith.constant -2 : index
+  %0 = vector.insert %b, %a[%c_neg_2] : vector<5xf32> into vector<4x5xf32>
+  return %0 : vector<4x5xf32>
+}
+
+// -----
+
 // CHECK-LABEL: @insert_multiple_poison_idx
 func.func @insert_multiple_poison_idx(%a: vector<4x5x8xf32>, %b: vector<8xf32>)
     -> vector<4x5x8xf32> {
@@ -3311,41 +3366,3 @@ func.func @fold_insert_constant_indices(%arg : vector<4x1xi32>) -> vector<4x1xi3
   %res = vector.insert %1, %arg[%0, %0] : i32 into vector<4x1xi32>
   return %res : vector<4x1xi32>
 }
-
-// -----
-
-// Check that out of bounds indices are not folded for vector.insert.
-
-// CHECK-LABEL: @fold_insert_oob
-//  CHECK-SAME:   %[[ARG:.*]]: vector<4x1x2xi32>) -> vector<4x1x2xi32> {
-//       CHECK:   %[[OOB1:.*]] = arith.constant -2 : index
-//       CHECK:   %[[OOB2:.*]] = arith.constant 2 : index
-//       CHECK:   %[[VAL:.*]] = arith.constant 1 : i32
-//       CHECK:   %[[RES:.*]] = vector.insert %[[VAL]], %[[ARG]] [0, %[[OOB1]], %[[OOB2]]] : i32 into vector<4x1x2xi32>
-//       CHECK:   return %[[RES]] : vector<4x1x2xi32>
-func.func @fold_insert_oob(%arg : vector<4x1x2xi32>) -> vector<4x1x2xi32> {
-  %c0 = arith.constant 0 : index
-  %c-2 = arith.constant -2 : index
-  %c2 = arith.constant 2 : index
-  %c1 = arith.constant 1 : i32
-  %res = vector.insert %c1, %arg[%c0, %c-2, %c2] : i32 into vector<4x1x2xi32>
-  return %res : vector<4x1x2xi32>
-}
-
-// -----
-
-// Check that out of bounds indices are not folded for vector.extract.
-
-// CHECK-LABEL: @fold_extract_oob
-//  CHECK-SAME:   %[[ARG:.*]]: vector<4x1x2xi32>) -> i32 {
-//       CHECK:   %[[OOB1:.*]] = arith.constant -2 : index
-//       CHECK:   %[[OOB2:.*]] = arith.constant 2 : index
-//       CHECK:   %[[RES:.*]] = vector.extract %[[ARG]][0, %[[OOB1]], %[[OOB2]]] : i32 from vector<4x1x2xi32>
-//       CHECK:   return %[[RES]] : i32
-func.func @fold_extract_oob(%arg : vector<4x1x2xi32>) -> i32 {
-  %c0 = arith.constant 0 : index
-  %c-2 = arith.constant -2 : index
-  %c2 = arith.constant 2 : index
-  %res = vector.extract %arg[%c0, %c-2, %c2] : i32 from vector<4x1x2xi32>
-  return %res : i32
-}
diff --git a/mlir/test/Dialect/Vector/invalid.mlir b/mlir/test/Dialect/Vector/invalid.mlir
index 3a8320971bac4..19096f0e4c895 100644
--- a/mlir/test/Dialect/Vector/invalid.mlir
+++ b/mlir/test/Dialect/Vector/invalid.mlir
@@ -525,6 +525,15 @@ func.func @test_vector.transfer_read(%arg0: memref<?x?xvector<2x3xf32>>) {
 
 // -----
 
+func.func @test_vector.transfer_read(%arg1: memref<?xindex>) -> vector<3x4xindex> {
+  %c3 = arith.constant 3 : index
+  // expected-error@+1 {{expected a custom permutation_map when rank(source) != rank(destination)}}
+  %0 = vector.transfer_read %arg1[%c3, %c3], %c3 : memref<?xindex>, vector<3x4xindex>
+  return %0 : vector<3x4xindex>
+}
+
+// -----
+
 func.func @test_vector.transfer_write(%arg0: memref<?x?xf32>) {
   %c3 = arith.constant 3 : index
   %cst = arith.constant 3.0 : f32
@@ -646,6 +655,14 @@ func.func @test_vector.transfer_write(%arg0: memref<?xf32>, %arg1: vector<7xf32>
 
 // -----
 
+func.func @test_vector.transfer_write(%vec_to_write: vector<3x4xindex>, %output_memref: memref<?xindex>) {
+  %c3 = arith.constant 3 : index
+  // expected-error@+1 {{expected a custom permutation_map when rank(source) != rank(destination)}}
+  vector.transfer_write %vec_to_write, %output_memref[%c3, %c3] : vector<3x4xindex>, memref<?xindex>
+}
+
+// -----
+
 func.func @insert_strided_slice(%a: vector<4x4xf32>, %b: vector<4x8x16xf32>) {
   // expected-error@+1 {{expected offsets of same size as destination vector rank}}
   %1 = vector.insert_strided_slice %a, %b {offsets = [100], strides = [1, 1]} : vector<4x4xf32> into vector<4x8x16xf32>
diff --git a/mlir/test/Dialect/Vector/vector-emulate-narrow-type-unaligned.mlir b/mlir/test/Dialect/Vector/vector-emulate-narrow-type-unaligned.mlir
index 6fc974200c6f3..21f073efc49b2 100644
--- a/mlir/test/Dialect/Vector/vector-emulate-narrow-type-unaligned.mlir
+++ b/mlir/test/Dialect/Vector/vector-emulate-narrow-type-unaligned.mlir
@@ -361,6 +361,74 @@ func.func @vector_maskedload_i2_constant_mask_unaligned(%passthru: vector<5xi2>)
 /// vector.store
 ///----------------------------------------------------------------------------------------
 
+// -----
+
+// Most basic example to demonstrate where partial stores are not needed.
+
+func.func @vector_store_i2_const_index_no_partial_store(%arg0: vector<4xi2>) {
+    %0 = memref.alloc() : memref<13xi2>
+    %c4 = arith.constant 4 : index
+    vector.store %arg0, %0[%c4] : memref<13xi2>, vector<4xi2>
+    return
+}
+// CHECK-LABEL:   func.func @vector_store_i2_const_index_no_partial_store(
+// CHECK-SAME:      %[[ARG_0:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: vector<4xi2>) {
+// CHECK-NOT:       memref.generic_atomic_rmw
+// CHECK:           %[[ALLOC:.*]] = memref.alloc() : memref<4xi8>
+// CHECK:           %[[UPCAST:.*]] = vector.bitcast %[[ARG_0]] : vector<4xi2> to vector<1xi8>
+// CHECK:           %[[C1:.*]] = arith.constant 1 : index
+// CHECK:           vector.store %[[UPCAST]], %[[ALLOC]]{{\[}}%[[C1]]] : memref<4xi8>, vector<1xi8>
+
+// -----
+
+// Small modification of the example above to demonstrate where partial stores
+// are needed.
+
+func.func @vector_store_i2_const_index_two_partial_stores(%arg0: vector<4xi2>) {
+    %0 = memref.alloc() : memref<13xi2>
+    %c3 = arith.constant 3 : index
+    vector.store %arg0, %0[%c3] : memref<13xi2>, vector<4xi2>
+    return
+}
+
+// CHECK-LABEL:   func.func @vector_store_i2_const_index_two_partial_stores(
+// CHECK-SAME:      %[[ARG_0:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: vector<4xi2>) {
+// CHECK:           %[[VAL_1:.*]] = memref.alloc() : memref<4xi8>
+
+// First atomic RMW:
+// CHECK:           %[[IDX_1:.*]] = arith.constant 0 : index
+// CHECK:           %[[MASK_1:.*]] = arith.constant dense<[false, false, false, true]> : vector<4xi1>
+// CHECK:           %[[INIT:.*]] = arith.constant dense<0> : vector<4xi2>
+// CHECK:           %[[SLICE_1:.*]] = vector.extract_strided_slice %[[ARG_0]] {offsets = [0], sizes = [1], strides = [1]} : vector<4xi2> to vector<1xi2>
+// CHECK:           %[[V1:.*]] = vector.insert_strided_slice %[[SLICE_1]], %[[INIT]] {offsets = [3], strides = [1]} : vector<1xi2> into vector<4xi2>
+// CHECK:           memref.generic_atomic_rmw %[[VAL_1]]{{\[}}%[[IDX_1]]] : memref<4xi8> {
+// CHECK:           ^bb0(%[[VAL_8:.*]]: i8):
+// CHECK:             %[[VAL_9:.*]] = vector.from_elements %[[VAL_8]] : vector<1xi8>
+// CHECK:             %[[DOWNCAST_1:.*]] = vector.bitcast %[[VAL_9]] : vector<1xi8> to vector<4xi2>
+// CHECK:             %[[SELECT_1:.*]] = arith.select %[[MASK_1]], %[[V1]], %[[DOWNCAST_1]] : vector<4xi1>, vector<4xi2>
+// CHECK:             %[[UPCAST_1:.*]] = vector.bitcast %[[SELECT_1]] : vector<4xi2> to vector<1xi8>
+// CHECK:             %[[RES_1:.*]] = vector.extract %[[UPCAST_1]][0] : i8 from vector<1xi8>
+// CHECK:             memref.atomic_yield %[[RES_1]] : i8
+// CHECK:           }
+
+// Second atomic RMW:
+// CHECK:           %[[VAL_14:.*]] = arith.constant 1 : index
+// CHECK:           %[[IDX_2:.*]] = arith.addi %[[IDX_1]], %[[VAL_14]] : index
+// CHECK:           %[[VAL_16:.*]] = vector.extract_strided_slice %[[ARG_0]] {offsets = [1], sizes = [3], strides = [1]} : vector<4xi2> to vector<3xi2>
+// CHECK:           %[[V2:.*]] = vector.insert_strided_slice %[[VAL_16]], %[[INIT]] {offsets = [0], strides = [1]} : vector<3xi2> into vector<4xi2>
+// CHECK:           %[[MASK_2:.*]] = arith.constant dense<[true, true, true, false]> : vector<4xi1>
+// CHECK:            memref.generic_atomic_rmw %[[VAL_1]]{{\[}}%[[IDX_2]]] : memref<4xi8> {
+// CHECK:           ^bb0(%[[VAL_20:.*]]: i8):
+// CHECK:             %[[VAL_21:.*]] = vector.from_elements %[[VAL_20]] : vector<1xi8>
+// CHECK:             %[[DONWCAST_2:.*]] = vector.bitcast %[[VAL_21]] : vector<1xi8> to vector<4xi2>
+// CHECK:             %[[SELECT_2:.*]] = arith.select %[[MASK_2]], %[[V2]], %[[DONWCAST_2]] : vector<4xi1>, vector<4xi2>
+// CHECK:             %[[UPCAST_2:.*]] = vector.bitcast %[[SELECT_2]] : vector<4xi2> to vector<1xi8>
+// CHECK:             %[[RES_2:.*]] = vector.extract %[[UPCAST_2]][0] : i8 from vector<1xi8>
+// CHECK:             memref.atomic_yield %[[RES_2]] : i8
+// CHECK:           }
+
+// -----
+
 func.func @vector_store_i2_const_index_two_partial_stores(%arg0: vector<3xi2>) {
     %src = memref.alloc() : memref<3x3xi2>
     %c0 = arith.constant 0 : index
diff --git a/mlir/test/Dialect/Vector/vector-emulate-narrow-type.mlir b/mlir/test/Dialect/Vector/vector-emulate-narrow-type.mlir
index 9dc3eb6989c6c..9e2d131f421b7 100644
--- a/mlir/test/Dialect/Vector/vector-emulate-narrow-type.mlir
+++ b/mlir/test/Dialect/Vector/vector-emulate-narrow-type.mlir
@@ -439,6 +439,11 @@ func.func @vector_store_i4(%arg0: vector<8xi4>, %arg1: index, %arg2: index) {
 
 // -----
 
+// FIXME: This example assumes that the store happens at a byte boundary, but
+// that's not guaranteed. Below is a counter-example with specific dimensions:
+//    vector.store %arg0, %0[0, 3] : memref<2x13xi4>, vector<8xi4>
+// TODO: Revisit post #136797
+
 func.func @vector_store_i4_dynamic(%arg0: vector<8xi4>, %arg1: index, %arg2: index, %arg3: index, %arg4: index) {
     %0 = memref.alloc(%arg1, %arg2) : memref<?x?xi4>
     vector.store %arg0, %0[%arg3, %arg4] : memref<?x?xi4>, vector<8xi4>
diff --git a/mlir/test/Dialect/X86Vector/legalize-for-llvm.mlir b/mlir/test/Dialect/X86Vector/legalize-for-llvm.mlir
index df0be7bce83be..93b304c44de8e 100644
--- a/mlir/test/Dialect/X86Vector/legalize-for-llvm.mlir
+++ b/mlir/test/Dialect/X86Vector/legalize-for-llvm.mlir
@@ -95,6 +95,60 @@ func.func @avx512bf16_cvt_packed_f32_to_bf16_512(
   return %0 : vector<16xbf16>
 }
 
+// CHECK-LABEL: func @avxbf16_cvt_packed_even_indexed_bf16_to_f32_128
+func.func @avxbf16_cvt_packed_even_indexed_bf16_to_f32_128(
+  %a: memref<8xbf16>) -> vector<4xf32>
+{
+  // CHECK: llvm.call_intrinsic "llvm.x86.vcvtneebf162ps128"
+  %0 = x86vector.avx.cvt.packed.even.indexed.bf16_to_f32 %a : memref<8xbf16> -> vector<4xf32>
+  return %0 : vector<4xf32>
+}
+
+// CHECK-LABEL: func @avxbf16_cvt_packed_even_indexed_bf16_to_f32_256
+func.func @avxbf16_cvt_packed_even_indexed_bf16_to_f32_256(
+  %a: memref<16xbf16>) -> vector<8xf32>
+{
+  // CHECK: llvm.call_intrinsic "llvm.x86.vcvtneebf162ps256"
+  %0 = x86vector.avx.cvt.packed.even.indexed.bf16_to_f32 %a : memref<16xbf16> -> vector<8xf32>
+  return %0 : vector<8xf32>
+}
+
+// CHECK-LABEL: func @avxbf16_cvt_packed_odd_indexed_bf16_to_f32_128
+func.func @avxbf16_cvt_packed_odd_indexed_bf16_to_f32_128(
+  %a: memref<8xbf16>) -> vector<4xf32>
+{
+  // CHECK: llvm.call_intrinsic "llvm.x86.vcvtneobf162ps128"
+  %0 = x86vector.avx.cvt.packed.odd.indexed.bf16_to_f32 %a : memref<8xbf16> -> vector<4xf32>
+  return %0 : vector<4xf32>
+}
+
+// CHECK-LABEL: func @avxbf16_cvt_packed_odd_indexed_bf16_to_f32_256
+func.func @avxbf16_cvt_packed_odd_indexed_bf16_to_f32_256(
+  %a: memref<16xbf16>) -> vector<8xf32>
+{
+  // CHECK: llvm.call_intrinsic "llvm.x86.vcvtneobf162ps256"
+  %0 = x86vector.avx.cvt.packed.odd.indexed.bf16_to_f32 %a : memref<16xbf16> -> vector<8xf32>
+  return %0 : vector<8xf32>
+}
+
+// CHECK-LABEL: func @avxbf16_bsct_bf16_to_f32_packed_128
+func.func @avxbf16_bsct_bf16_to_f32_packed_128(
+  %a: memref<1xbf16>) -> vector<4xf32>
+{
+  // CHECK: llvm.call_intrinsic "llvm.x86.vbcstnebf162ps128"
+  %0 = x86vector.avx.bcst.bf16_to_f32.packed %a : memref<1xbf16> -> vector<4xf32>
+  return %0 : vector<4xf32>
+}
+
+// CHECK-LABEL: func @avxbf16_bsct_bf16_to_f32_packed_256
+func.func @avxbf16_bsct_bf16_to_f32_packed_256(
+  %a: memref<1xbf16>) -> vector<8xf32>
+{
+  // CHECK: llvm.call_intrinsic "llvm.x86.vbcstnebf162ps256"
+  %0 = x86vector.avx.bcst.bf16_to_f32.packed %a : memref<1xbf16> -> vector<8xf32>
+  return %0 : vector<8xf32>
+}
+
 // CHECK-LABEL: func @avx_rsqrt
 func.func @avx_rsqrt(%a: vector<8xf32>) -> (vector<8xf32>)
 {
diff --git a/mlir/test/Dialect/X86Vector/roundtrip.mlir b/mlir/test/Dialect/X86Vector/roundtrip.mlir
index 0d00448c63da8..b783cc869b981 100644
--- a/mlir/test/Dialect/X86Vector/roundtrip.mlir
+++ b/mlir/test/Dialect/X86Vector/roundtrip.mlir
@@ -94,6 +94,66 @@ func.func @avx512bf16_cvt_packed_f32_to_bf16_512(
   return %0 : vector<16xbf16>
 }
 
+// CHECK-LABEL: func @avxbf16_cvt_packed_even_indexed_bf16_to_f32_128
+func.func @avxbf16_cvt_packed_even_indexed_bf16_to_f32_128(
+  %a: memref<8xbf16>) -> vector<4xf32>
+{
+  // CHECK: x86vector.avx.cvt.packed.even.indexed.bf16_to_f32 {{.*}} :
+  // CHECK-SAME: memref<8xbf16> -> vector<4xf32>
+  %0 = x86vector.avx.cvt.packed.even.indexed.bf16_to_f32 %a : memref<8xbf16> -> vector<4xf32>
+  return %0 : vector<4xf32>
+}
+
+// CHECK-LABEL: func @avxbf16_cvt_packed_even_indexed_bf16_to_f32_256
+func.func @avxbf16_cvt_packed_even_indexed_bf16_to_f32_256(
+  %a: memref<16xbf16>) -> vector<8xf32>
+{
+  // CHECK: x86vector.avx.cvt.packed.even.indexed.bf16_to_f32 {{.*}} :
+  // CHECK-SAME: memref<16xbf16> -> vector<8xf32>
+  %0 = x86vector.avx.cvt.packed.even.indexed.bf16_to_f32 %a : memref<16xbf16> -> vector<8xf32>
+  return %0 : vector<8xf32>
+}
+
+// CHECK-LABEL: func @avxbf16_cvt_packed_odd_indexed_bf16_to_f32_128
+func.func @avxbf16_cvt_packed_odd_indexed_bf16_to_f32_128(
+  %a: memref<8xbf16>) -> vector<4xf32>
+{
+  // CHECK: x86vector.avx.cvt.packed.odd.indexed.bf16_to_f32 {{.*}} :
+  // CHECK-SAME: memref<8xbf16> -> vector<4xf32>
+  %0 = x86vector.avx.cvt.packed.odd.indexed.bf16_to_f32 %a : memref<8xbf16> -> vector<4xf32>
+  return %0 : vector<4xf32>
+}
+
+// CHECK-LABEL: func @avxbf16_cvt_packed_odd_indexed_bf16_to_f32_256
+func.func @avxbf16_cvt_packed_odd_indexed_bf16_to_f32_256(
+  %a: memref<16xbf16>) -> vector<8xf32>
+{
+  // CHECK: x86vector.avx.cvt.packed.odd.indexed.bf16_to_f32 {{.*}} :
+  // CHECK-SAME: memref<16xbf16> -> vector<8xf32>
+  %0 = x86vector.avx.cvt.packed.odd.indexed.bf16_to_f32 %a : memref<16xbf16> -> vector<8xf32>
+  return %0 : vector<8xf32>
+}
+
+// CHECK-LABEL: func @avxbf16_bcst_bf16_to_f32_128
+func.func @avxbf16_bcst_bf16_to_f32_128(
+  %a: memref<1xbf16>) -> vector<4xf32>
+{
+  // CHECK: x86vector.avx.bcst.bf16_to_f32.packed {{.*}} :
+  // CHECK-SAME: memref<1xbf16> -> vector<4xf32>
+  %0 = x86vector.avx.bcst.bf16_to_f32.packed %a : memref<1xbf16> -> vector<4xf32>
+  return %0 : vector<4xf32>
+}
+
+// CHECK-LABEL: func @avxbf16_bcst_bf16_to_f32_256
+func.func @avxbf16_bcst_bf16_to_f32_256(
+  %a: memref<1xbf16>) -> vector<8xf32>
+{
+  // CHECK: x86vector.avx.bcst.bf16_to_f32.packed {{.*}} :
+  // CHECK-SAME: memref<1xbf16> -> vector<8xf32>
+  %0 = x86vector.avx.bcst.bf16_to_f32.packed %a : memref<1xbf16> -> vector<8xf32>
+  return %0 : vector<8xf32>
+}
+
 // CHECK-LABEL: func @avx_rsqrt
 func.func @avx_rsqrt(%a: vector<8xf32>) -> (vector<8xf32>)
 {
diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/matmul.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/matmul.mlir
index bcfeef772743b..3368dd634d228 100644
--- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/matmul.mlir
+++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/matmul.mlir
@@ -107,6 +107,7 @@ module attributes {transform.with_named_sequence} {
       transform.apply_patterns.vector.reduction_to_contract
       transform.apply_patterns.vector.transfer_permutation_patterns
       transform.apply_patterns.vector.lower_masked_transfers
+      transform.apply_patterns.vector.sink_ops
     } : !transform.op<"func.func">
 
     // Step 4: Lower vector.contract to vector.fma
diff --git a/mlir/test/Target/LLVMIR/Import/module-flags.ll b/mlir/test/Target/LLVMIR/Import/module-flags.ll
index b7b686f94c7f4..e6bb2c0ffb32d 100644
--- a/mlir/test/Target/LLVMIR/Import/module-flags.ll
+++ b/mlir/test/Target/LLVMIR/Import/module-flags.ll
@@ -1,25 +1,27 @@
 ; RUN: mlir-translate -import-llvm -split-input-file -verify-diagnostics %s | FileCheck %s
 
-!llvm.module.flags = !{!0, !1, !2, !3, !4}
+!llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
 
 !0 = !{i32 1, !"wchar_size", i32 4}
 !1 = !{i32 8, !"PIC Level", i32 2}
 !2 = !{i32 7, !"PIE Level", i32 2}
 !3 = !{i32 7, !"uwtable", i32 2}
 !4 = !{i32 7, !"frame-pointer", i32 1}
+!5 = !{i32 4, !"probe-stack", !"inline-asm"}
 
 ; CHECK-LABEL: module attributes {{.*}} {
 ; CHECK: llvm.module_flags [
-; CHECK-SAME: #llvm.mlir.module_flag<error, "wchar_size", 4>,
-; CHECK-SAME: #llvm.mlir.module_flag<min, "PIC Level", 2>,
-; CHECK-SAME: #llvm.mlir.module_flag<max, "PIE Level", 2>,
-; CHECK-SAME: #llvm.mlir.module_flag<max, "uwtable", 2>,
-; CHECK-SAME: #llvm.mlir.module_flag<max, "frame-pointer", 1>]
-; CHECK: }
+; CHECK-SAME: #llvm.mlir.module_flag<error, "wchar_size", 4 : i32>,
+; CHECK-SAME: #llvm.mlir.module_flag<min, "PIC Level", 2 : i32>,
+; CHECK-SAME: #llvm.mlir.module_flag<max, "PIE Level", 2 : i32>,
+; CHECK-SAME: #llvm.mlir.module_flag<max, "uwtable", 2 : i32>,
+; CHECK-SAME: #llvm.mlir.module_flag<max, "frame-pointer", 1 : i32>,
+; CHECK-SAME: #llvm.mlir.module_flag<override, "probe-stack", "inline-asm">]
 
 ; // -----
-
-!llvm.module.flags = !{!0}
-
-; expected-warning@-5{{unsupported module flag value: !"yolo_more", only constant integer currently supported}}
-!0 = !{i32 1, !"yolo", !"yolo_more"}
+; expected-warning@-2 {{unsupported module flag value: !4 = !{!"foo", i32 1}}}
+!10 = !{ i32 1, !"foo", i32 1 }
+!11 = !{ i32 4, !"bar", i32 37 }
+!12 = !{ i32 2, !"qux", i32 42 }
+!13 = !{ i32 3, !"qux", !{ !"foo", i32 1 }}
+!llvm.module.flags = !{ !10, !11, !12, !13 }
diff --git a/mlir/test/Target/LLVMIR/llvmir.mlir b/mlir/test/Target/LLVMIR/llvmir.mlir
index 3cf08dbeeac8c..74fa327809864 100644
--- a/mlir/test/Target/LLVMIR/llvmir.mlir
+++ b/mlir/test/Target/LLVMIR/llvmir.mlir
@@ -2809,11 +2809,11 @@ llvm.func @call_intrin_with_opbundle(%arg0 : !llvm.ptr) {
 // -----
 
 module {
-  llvm.module_flags [#llvm.mlir.module_flag<error, "wchar_size", 4>,
-                     #llvm.mlir.module_flag<min, "PIC Level", 2>,
-                     #llvm.mlir.module_flag<max, "PIE Level", 2>,
-                     #llvm.mlir.module_flag<max, "uwtable", 2>,
-                     #llvm.mlir.module_flag<max, "frame-pointer", 1>]
+  llvm.module_flags [#llvm.mlir.module_flag<error, "wchar_size", 4 : i32>,
+                     #llvm.mlir.module_flag<min, "PIC Level", 2 : i32>,
+                     #llvm.mlir.module_flag<max, "PIE Level", 2 : i32>,
+                     #llvm.mlir.module_flag<max, "uwtable", 2 : i32>,
+                     #llvm.mlir.module_flag<max, "frame-pointer", 1 : i32>]
 }
 
 // CHECK: !llvm.module.flags = !{![[#WCHAR:]], ![[#PIC:]], ![[#PIE:]], ![[#UWTABLE:]], ![[#FrameP:]], ![[#DBG:]]}
@@ -2830,7 +2830,7 @@ module {
 // Verifies that the debug info version is not added twice, if it's already present initially.
 
 module {
-  llvm.module_flags [#llvm.mlir.module_flag<warning, "Debug Info Version", 3>]
+  llvm.module_flags [#llvm.mlir.module_flag<warning, "Debug Info Version", 3 : i32>]
 }
 
 // CHECK: !llvm.module.flags = !{![[#DBG:]]}
diff --git a/mlir/test/Target/LLVMIR/x86vector.mlir b/mlir/test/Target/LLVMIR/x86vector.mlir
index 85dad36334b1d..a8bc180d1d0ac 100644
--- a/mlir/test/Target/LLVMIR/x86vector.mlir
+++ b/mlir/test/Target/LLVMIR/x86vector.mlir
@@ -1,4 +1,4 @@
-// RUN: mlir-opt %s --convert-vector-to-llvm="enable-x86vector" --convert-to-llvm \
+// RUN: mlir-opt %s --convert-vector-to-llvm="enable-x86vector" --convert-to-llvm -reconcile-unrealized-casts \
 // RUN: | mlir-translate --mlir-to-llvmir \
 // RUN: | FileCheck %s
 
@@ -109,6 +109,60 @@ func.func @LLVM_x86_avx512bf16_cvtneps2bf16_512(
   return %0 : vector<16xbf16>
 }
 
+// CHECK-LABEL: define <4 x float> @LLVM_x86_avxbf16_vcvtneebf162ps128
+func.func @LLVM_x86_avxbf16_vcvtneebf162ps128(
+  %a: memref<8xbf16>) -> vector<4xf32>
+{
+  // CHECK: call <4 x float> @llvm.x86.vcvtneebf162ps128(
+  %0 = x86vector.avx.cvt.packed.even.indexed.bf16_to_f32 %a : memref<8xbf16> -> vector<4xf32>
+  return %0 : vector<4xf32>
+}
+
+// CHECK-LABEL: define <8 x float> @LLVM_x86_avxbf16_vcvtneebf162ps256
+func.func @LLVM_x86_avxbf16_vcvtneebf162ps256(
+  %a: memref<16xbf16>) -> vector<8xf32>
+{
+  // CHECK: call <8 x float> @llvm.x86.vcvtneebf162ps256(
+  %0 = x86vector.avx.cvt.packed.even.indexed.bf16_to_f32 %a : memref<16xbf16> -> vector<8xf32>
+  return %0 : vector<8xf32>
+}
+
+// CHECK-LABEL: define <4 x float> @LLVM_x86_avxbf16_vcvtneobf162ps128
+func.func @LLVM_x86_avxbf16_vcvtneobf162ps128(
+  %a: memref<8xbf16>) -> vector<4xf32>
+{
+  // CHECK: call <4 x float> @llvm.x86.vcvtneobf162ps128(
+  %0 = x86vector.avx.cvt.packed.odd.indexed.bf16_to_f32 %a : memref<8xbf16> -> vector<4xf32>
+  return %0 : vector<4xf32>
+}
+
+// CHECK-LABEL: define <8 x float> @LLVM_x86_avxbf16_vcvtneobf162ps256
+func.func @LLVM_x86_avxbf16_vcvtneobf162ps256(
+  %a: memref<16xbf16>) -> vector<8xf32>
+{
+  // CHECK: call <8 x float> @llvm.x86.vcvtneobf162ps256(
+  %0 = x86vector.avx.cvt.packed.odd.indexed.bf16_to_f32 %a : memref<16xbf16> -> vector<8xf32>
+  return %0 : vector<8xf32>
+}
+
+// CHECK-LABEL: define <4 x float> @LLVM_x86_avxbf16_vbcstnebf162ps128
+func.func @LLVM_x86_avxbf16_vbcstnebf162ps128(
+  %a: memref<1xbf16>) -> vector<4xf32>
+{
+  // CHECK: call <4 x float> @llvm.x86.vbcstnebf162ps128(
+  %0 = x86vector.avx.bcst.bf16_to_f32.packed %a : memref<1xbf16> -> vector<4xf32>
+  return %0 : vector<4xf32>
+}
+
+// CHECK-LABEL: define <8 x float> @LLVM_x86_avxbf16_vbcstnebf162ps256
+func.func @LLVM_x86_avxbf16_vbcstnebf162ps256(
+  %a: memref<1xbf16>) -> vector<8xf32>
+{
+  // CHECK: call <8 x float> @llvm.x86.vbcstnebf162ps256(
+  %0 = x86vector.avx.bcst.bf16_to_f32.packed %a : memref<1xbf16> -> vector<8xf32>
+  return %0 : vector<8xf32>
+}
+
 // CHECK-LABEL: define <8 x float> @LLVM_x86_avx_rsqrt_ps_256
 func.func @LLVM_x86_avx_rsqrt_ps_256(%a: vector <8xf32>) -> vector<8xf32>
 {
diff --git a/mlir/test/lib/Dialect/Affine/TestAffineDataCopy.cpp b/mlir/test/lib/Dialect/Affine/TestAffineDataCopy.cpp
index d6aaa6faf94cb..2a54e0c28f71f 100644
--- a/mlir/test/lib/Dialect/Affine/TestAffineDataCopy.cpp
+++ b/mlir/test/lib/Dialect/Affine/TestAffineDataCopy.cpp
@@ -144,7 +144,7 @@ void TestAffineDataCopy::runOnOperation() {
     }
   }
   GreedyRewriteConfig config;
-  config.strictMode = GreedyRewriteStrictness::ExistingAndNewOps;
+  config.setStrictness(GreedyRewriteStrictness::ExistingAndNewOps);
   (void)applyOpPatternsGreedily(copyOps, std::move(patterns), config);
 }
 
diff --git a/mlir/test/lib/Dialect/GPU/TestGpuRewrite.cpp b/mlir/test/lib/Dialect/GPU/TestGpuRewrite.cpp
index a49d304baf5c6..fe402da4cc105 100644
--- a/mlir/test/lib/Dialect/GPU/TestGpuRewrite.cpp
+++ b/mlir/test/lib/Dialect/GPU/TestGpuRewrite.cpp
@@ -10,10 +10,13 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "mlir/Dialect/AMDGPU/IR/AMDGPUDialect.h"
+#include "mlir/Dialect/AMDGPU/Utils/Chipset.h"
 #include "mlir/Dialect/Arith/IR/Arith.h"
 #include "mlir/Dialect/Func/IR/FuncOps.h"
 #include "mlir/Dialect/GPU/Transforms/Passes.h"
 #include "mlir/Dialect/Index/IR/IndexDialect.h"
+#include "mlir/Dialect/LLVMIR/ROCDLDialect.h"
 #include "mlir/Dialect/MemRef/IR/MemRef.h"
 #include "mlir/Dialect/Vector/IR/VectorOps.h"
 #include "mlir/IR/PatternMatch.h"
@@ -54,7 +57,9 @@ struct TestGpuSubgroupReduceLoweringPass
       : PassWrapper(pass) {}
 
   void getDependentDialects(DialectRegistry &registry) const override {
-    registry.insert<arith::ArithDialect, vector::VectorDialect>();
+    registry
+        .insert<amdgpu::AMDGPUDialect, arith::ArithDialect, LLVM::LLVMDialect,
+                ROCDL::ROCDLDialect, vector::VectorDialect>();
   }
 
   StringRef getArgument() const final {
@@ -70,6 +75,12 @@ struct TestGpuSubgroupReduceLoweringPass
       llvm::cl::desc("Expand subgroup_reduce ops to shuffle ops."),
       llvm::cl::init(false)};
 
+  Option<std::string> target{
+      *this, "target",
+      llvm::cl::desc("Target backend name which will be used to provide "
+                     "compatible lowerings of subgroup reduce."),
+      llvm::cl::init("")};
+
   void runOnOperation() override {
     RewritePatternSet patterns(&getContext());
 
@@ -77,8 +88,15 @@ struct TestGpuSubgroupReduceLoweringPass
     // perform fewer failing matches.
     populateGpuBreakDownSubgroupReducePatterns(patterns,
                                                /*maxShuffleBitwidth=*/32,
-                                               PatternBenefit(2));
+                                               PatternBenefit(3));
     if (expandToShuffles) {
+      auto maybeChipset = amdgpu::Chipset::parse(target);
+      if (succeeded(maybeChipset)) {
+        populateGpuLowerSubgroupReduceToDPPPatterns(
+            patterns, /*subgroupSize=*/64, *maybeChipset, PatternBenefit(2));
+        populateGpuLowerClusteredSubgroupReduceToDPPPatterns(
+            patterns, /*subgroupSize=*/64, *maybeChipset, PatternBenefit(2));
+      }
       populateGpuLowerSubgroupReduceToShufflePatterns(
           patterns, /*subgroupSize=*/32, /*shuffleBitwidth=*/32);
       populateGpuLowerClusteredSubgroupReduceToShufflePatterns(
diff --git a/mlir/test/lib/Dialect/Test/TestPatterns.cpp b/mlir/test/lib/Dialect/Test/TestPatterns.cpp
index db02a122872d9..d073843484d81 100644
--- a/mlir/test/lib/Dialect/Test/TestPatterns.cpp
+++ b/mlir/test/lib/Dialect/Test/TestPatterns.cpp
@@ -386,26 +386,26 @@ struct TestGreedyPatternDriver
     patterns.insert<IncrementIntAttribute<3>>(&getContext());
 
     GreedyRewriteConfig config;
-    config.useTopDownTraversal = this->useTopDownTraversal;
-    config.maxIterations = this->maxIterations;
-    config.fold = this->fold;
-    config.cseConstants = this->cseConstants;
+    config.setUseTopDownTraversal(useTopDownTraversal)
+        .setMaxIterations(this->maxIterations)
+        .enableFolding(this->fold)
+        .enableConstantCSE(this->cseConstants);
     (void)applyPatternsGreedily(getOperation(), std::move(patterns), config);
   }
 
   Option<bool> useTopDownTraversal{
       *this, "top-down",
       llvm::cl::desc("Seed the worklist in general top-down order"),
-      llvm::cl::init(GreedyRewriteConfig().useTopDownTraversal)};
+      llvm::cl::init(GreedyRewriteConfig().getUseTopDownTraversal())};
   Option<int> maxIterations{
       *this, "max-iterations",
       llvm::cl::desc("Max. iterations in the GreedyRewriteConfig"),
-      llvm::cl::init(GreedyRewriteConfig().maxIterations)};
+      llvm::cl::init(GreedyRewriteConfig().getMaxIterations())};
   Option<bool> fold{*this, "fold", llvm::cl::desc("Whether to fold"),
-                    llvm::cl::init(GreedyRewriteConfig().fold)};
-  Option<bool> cseConstants{*this, "cse-constants",
-                            llvm::cl::desc("Whether to CSE constants"),
-                            llvm::cl::init(GreedyRewriteConfig().cseConstants)};
+                    llvm::cl::init(GreedyRewriteConfig().isFoldingEnabled())};
+  Option<bool> cseConstants{
+      *this, "cse-constants", llvm::cl::desc("Whether to CSE constants"),
+      llvm::cl::init(GreedyRewriteConfig().isConstantCSEEnabled())};
 };
 
 struct DumpNotifications : public RewriterBase::Listener {
@@ -501,13 +501,13 @@ struct TestStrictPatternDriver
 
     DumpNotifications dumpNotifications;
     GreedyRewriteConfig config;
-    config.listener = &dumpNotifications;
+    config.setListener(&dumpNotifications);
     if (strictMode == "AnyOp") {
-      config.strictMode = GreedyRewriteStrictness::AnyOp;
+      config.setStrictness(GreedyRewriteStrictness::AnyOp);
     } else if (strictMode == "ExistingAndNewOps") {
-      config.strictMode = GreedyRewriteStrictness::ExistingAndNewOps;
+      config.setStrictness(GreedyRewriteStrictness::ExistingAndNewOps);
     } else if (strictMode == "ExistingOps") {
-      config.strictMode = GreedyRewriteStrictness::ExistingOps;
+      config.setStrictness(GreedyRewriteStrictness::ExistingOps);
     } else {
       llvm_unreachable("invalid strictness option");
     }
diff --git a/mlir/test/python/pass_manager.py b/mlir/test/python/pass_manager.py
index ecac57e3302f0..85d2eb304882e 100644
--- a/mlir/test/python/pass_manager.py
+++ b/mlir/test/python/pass_manager.py
@@ -130,7 +130,7 @@ def testInvalidNesting():
         try:
             pm = PassManager.parse("func.func(normalize-memrefs)")
         except ValueError as e:
-            # CHECK: ValueError exception: Can't add pass 'NormalizeMemRefs' restricted to 'builtin.module' on a PassManager intended to run on 'func.func', did you intend to nest?
+            # CHECK: ValueError exception: Can't add pass 'NormalizeMemRefsPass' restricted to 'builtin.module' on a PassManager intended to run on 'func.func', did you intend to nest?
             log("ValueError exception:", e)
         else:
             log("Exception not produced")
diff --git a/mlir/utils/generate-test-checks.py b/mlir/utils/generate-test-checks.py
index f1dd7a2843893..d157af9c3cab7 100755
--- a/mlir/utils/generate-test-checks.py
+++ b/mlir/utils/generate-test-checks.py
@@ -408,8 +408,12 @@ def main():
             for argument in ssa_split[1:]:
                 output_line += "// " + args.check_prefix + "-SAME:  "
 
-                # Pad to align with the original position in the line.
-                output_line += " " * len(ssa_split[0])
+                # Pad to align with the original position in the line (i.e. where the label ends),
+                # unless the label is more than 20 chars long, in which case pad with 4 spaces
+                # (this is to avoid deep indentation).
+                label_length = len(ssa_split[0])
+                pad_depth = label_length if label_length < 21 else 4
+                output_line += " " * pad_depth
 
                 # Process the rest of the line.
                 output_line += process_line(
diff --git a/offload/DeviceRTL/CMakeLists.txt b/offload/DeviceRTL/CMakeLists.txt
index 12f53a30761f3..b1c48cbaefe16 100644
--- a/offload/DeviceRTL/CMakeLists.txt
+++ b/offload/DeviceRTL/CMakeLists.txt
@@ -137,7 +137,7 @@ function(compileDeviceRTLLibrary target_name target_triple)
                       "-r" "-nostdlib" "-flto" "-Wl,--lto-emit-llvm" "-march=")
   install(TARGETS libomptarget-${target_name}
           PERMISSIONS OWNER_WRITE OWNER_READ GROUP_READ WORLD_READ
-          DESTINATION ${OFFLOAD_INSTALL_LIBDIR})
+          DESTINATION "lib${LLVM_LIBDIR_SUFFIX}/${target_triple}")
 
   add_library(omptarget.${target_name}.all_objs OBJECT IMPORTED)
   set_property(TARGET omptarget.${target_name}.all_objs APPEND PROPERTY IMPORTED_OBJECTS
diff --git a/offload/DeviceRTL/src/Kernel.cpp b/offload/DeviceRTL/src/Kernel.cpp
index eac68a15538c4..467e44a65276c 100644
--- a/offload/DeviceRTL/src/Kernel.cpp
+++ b/offload/DeviceRTL/src/Kernel.cpp
@@ -26,6 +26,7 @@ using namespace ompx;
 // These flags are copied from "llvm/Frontend/OpenMP/OMPDeviceConstants.h" and
 // must be kept in-sync.
 enum OMPTgtExecModeFlags : unsigned char {
+  OMP_TGT_EXEC_MODE_BARE = 0,
   OMP_TGT_EXEC_MODE_GENERIC = 1 << 0,
   OMP_TGT_EXEC_MODE_SPMD = 1 << 1,
   OMP_TGT_EXEC_MODE_GENERIC_SPMD =
diff --git a/offload/plugins-nextgen/common/include/PluginInterface.h b/offload/plugins-nextgen/common/include/PluginInterface.h
index a30589e039468..e54a8afdd3f4f 100644
--- a/offload/plugins-nextgen/common/include/PluginInterface.h
+++ b/offload/plugins-nextgen/common/include/PluginInterface.h
@@ -297,6 +297,7 @@ struct GenericKernelTy {
   /// Indicate whether an execution mode is valid.
   static bool isValidExecutionMode(OMPTgtExecModeFlags ExecutionMode) {
     switch (ExecutionMode) {
+    case OMP_TGT_EXEC_MODE_BARE:
     case OMP_TGT_EXEC_MODE_SPMD:
     case OMP_TGT_EXEC_MODE_GENERIC:
     case OMP_TGT_EXEC_MODE_GENERIC_SPMD:
@@ -309,6 +310,8 @@ struct GenericKernelTy {
   /// Get the execution mode name of the kernel.
   const char *getExecutionModeName() const {
     switch (KernelEnvironment.Configuration.ExecMode) {
+    case OMP_TGT_EXEC_MODE_BARE:
+      return "BARE";
     case OMP_TGT_EXEC_MODE_SPMD:
       return "SPMD";
     case OMP_TGT_EXEC_MODE_GENERIC:
@@ -364,6 +367,9 @@ struct GenericKernelTy {
   bool isSPMDMode() const {
     return KernelEnvironment.Configuration.ExecMode == OMP_TGT_EXEC_MODE_SPMD;
   }
+  bool isBareMode() const {
+    return KernelEnvironment.Configuration.ExecMode == OMP_TGT_EXEC_MODE_BARE;
+  }
 
   /// The kernel name.
   const char *Name;
diff --git a/offload/plugins-nextgen/common/src/PluginInterface.cpp b/offload/plugins-nextgen/common/src/PluginInterface.cpp
index 4d2ebcbc7be8e..059f14f59c38b 100644
--- a/offload/plugins-nextgen/common/src/PluginInterface.cpp
+++ b/offload/plugins-nextgen/common/src/PluginInterface.cpp
@@ -440,18 +440,19 @@ Error GenericKernelTy::init(GenericDeviceTy &GenericDevice,
   ImagePtr = &Image;
 
   // Retrieve kernel environment object for the kernel.
-  GlobalTy KernelEnv(std::string(Name) + "_kernel_environment",
-                     sizeof(KernelEnvironment), &KernelEnvironment);
+  std::string EnvironmentName = std::string(Name) + "_kernel_environment";
   GenericGlobalHandlerTy &GHandler = GenericDevice.Plugin.getGlobalHandler();
-  if (auto Err =
-          GHandler.readGlobalFromImage(GenericDevice, *ImagePtr, KernelEnv)) {
-    [[maybe_unused]] std::string ErrStr = toString(std::move(Err));
-    DP("Failed to read kernel environment for '%s': %s\n"
-       "Using default SPMD (2) execution mode\n",
-       Name, ErrStr.data());
-    assert(KernelEnvironment.Configuration.ReductionDataSize == 0 &&
-           "Default initialization failed.");
-    IsBareKernel = true;
+  if (GHandler.isSymbolInImage(GenericDevice, Image, EnvironmentName)) {
+    GlobalTy KernelEnv(EnvironmentName, sizeof(KernelEnvironment),
+                       &KernelEnvironment);
+    if (auto Err =
+            GHandler.readGlobalFromImage(GenericDevice, *ImagePtr, KernelEnv))
+      return Err;
+  } else {
+    KernelEnvironment = KernelEnvironmentTy{};
+    DP("Failed to read kernel environment for '%s' Using default Bare (0) "
+       "execution mode\n",
+       Name);
   }
 
   // Max = Config.Max > 0 ? min(Config.Max, Device.Max) : Device.Max;
@@ -573,7 +574,7 @@ Error GenericKernelTy::launch(GenericDeviceTy &GenericDevice, void **ArgPtrs,
                             KernelArgs.ThreadLimit[2]};
   uint32_t NumBlocks[3] = {KernelArgs.NumTeams[0], KernelArgs.NumTeams[1],
                            KernelArgs.NumTeams[2]};
-  if (!IsBareKernel) {
+  if (!isBareMode()) {
     NumThreads[0] = getNumThreads(GenericDevice, NumThreads);
     NumBlocks[0] = getNumBlocks(GenericDevice, NumBlocks, KernelArgs.Tripcount,
                                 NumThreads[0], KernelArgs.ThreadLimit[0] > 0);
@@ -627,7 +628,7 @@ KernelLaunchParamsTy GenericKernelTy::prepareArgs(
 
 uint32_t GenericKernelTy::getNumThreads(GenericDeviceTy &GenericDevice,
                                         uint32_t ThreadLimitClause[3]) const {
-  assert(!IsBareKernel && "bare kernel should not call this function");
+  assert(!isBareMode() && "bare kernel should not call this function");
 
   assert(ThreadLimitClause[1] == 1 && ThreadLimitClause[2] == 1 &&
          "Multi dimensional launch not supported yet.");
@@ -645,7 +646,7 @@ uint32_t GenericKernelTy::getNumBlocks(GenericDeviceTy &GenericDevice,
                                        uint64_t LoopTripCount,
                                        uint32_t &NumThreads,
                                        bool IsNumThreadsFromUser) const {
-  assert(!IsBareKernel && "bare kernel should not call this function");
+  assert(!isBareMode() && "bare kernel should not call this function");
 
   assert(NumTeamsClause[1] == 1 && NumTeamsClause[2] == 1 &&
          "Multi dimensional launch not supported yet.");
diff --git a/offload/test/offloading/ompx_bare.c b/offload/test/offloading/ompx_bare.c
index 6a6ada9617cf5..9c8addf03c4dc 100644
--- a/offload/test/offloading/ompx_bare.c
+++ b/offload/test/offloading/ompx_bare.c
@@ -15,7 +15,7 @@ int main(int argc, char *argv[]) {
   const int N = num_blocks * block_size;
   int *data = (int *)malloc(N * sizeof(int));
 
-  // CHECK: "PluginInterface" device 0 info: Launching kernel __omp_offloading_{{.*}} with [64,1,1] blocks and [64,1,1] threads in SPMD mode
+  // CHECK: "PluginInterface" device 0 info: Launching kernel __omp_offloading_{{.*}} with [64,1,1] blocks and [64,1,1] threads in BARE mode
 
 #pragma omp target teams ompx_bare num_teams(num_blocks) thread_limit(block_size) map(from: data[0:N])
   {
diff --git a/offload/test/offloading/ompx_bare_multi_dim.cpp b/offload/test/offloading/ompx_bare_multi_dim.cpp
index d37278525fdb0..3a726f89f7dfb 100644
--- a/offload/test/offloading/ompx_bare_multi_dim.cpp
+++ b/offload/test/offloading/ompx_bare_multi_dim.cpp
@@ -7,7 +7,7 @@
 #include <cassert>
 #include <vector>
 
-// CHECK: "PluginInterface" device 0 info: Launching kernel __omp_offloading_{{.*}} with [2,4,6] blocks and [32,4,2] threads in SPMD mode
+// CHECK: "PluginInterface" device 0 info: Launching kernel __omp_offloading_{{.*}} with [2,4,6] blocks and [32,4,2] threads in BARE mode
 
 int main(int argc, char *argv[]) {
   int bs[3] = {32u, 4u, 2u};
diff --git a/openmp/runtime/src/kmp_tasking.cpp b/openmp/runtime/src/kmp_tasking.cpp
index 563aa29f6265e..ea123dcb05a63 100644
--- a/openmp/runtime/src/kmp_tasking.cpp
+++ b/openmp/runtime/src/kmp_tasking.cpp
@@ -5452,7 +5452,6 @@ bool __kmpc_omp_has_task_team(kmp_int32 gtid) {
 
 #if OMPX_TASKGRAPH
 // __kmp_find_tdg: identify a TDG through its ID
-// gtid:   Global Thread ID
 // tdg_id: ID of the TDG
 // returns: If a TDG corresponding to this ID is found and not
 // its initial state, return the pointer to it, otherwise nullptr
@@ -5505,7 +5504,7 @@ void __kmp_print_tdg_dot(kmp_tdg_info_t *tdg, kmp_int32 gtid) {
   KA_TRACE(10, ("__kmp_print_tdg_dot(exit): T#%d tdg_id=%d \n", gtid, tdg_id));
 }
 
-// __kmp_start_record: launch the execution of a previous
+// __kmp_exec_tdg: launch the execution of a previous
 // recorded TDG
 // gtid:   Global Thread ID
 // tdg:    ID of the TDG
diff --git a/polly/lib/CodeGen/BlockGenerators.cpp b/polly/lib/CodeGen/BlockGenerators.cpp
index cf2cc65e0f042..3c6909f3eb702 100644
--- a/polly/lib/CodeGen/BlockGenerators.cpp
+++ b/polly/lib/CodeGen/BlockGenerators.cpp
@@ -420,7 +420,7 @@ BasicBlock *BlockGenerator::copyBB(ScopStmt &Stmt, BasicBlock *BB,
                                    ValueMapT &BBMap, LoopToScevMapT &LTS,
                                    isl_id_to_ast_expr *NewAccesses) {
   BasicBlock *CopyBB = splitBB(BB);
-  Builder.SetInsertPoint(&CopyBB->front());
+  Builder.SetInsertPoint(CopyBB, CopyBB->begin());
   generateScalarLoads(Stmt, LTS, BBMap, NewAccesses);
   generateBeginStmtTrace(Stmt, LTS, BBMap);
 
@@ -795,7 +795,7 @@ void BlockGenerator::createScalarInitialization(Scop &S) {
   BasicBlock *ExitBB = S.getExit();
   BasicBlock *PreEntryBB = S.getEnteringBlock();
 
-  Builder.SetInsertPoint(&*StartBlock->begin());
+  Builder.SetInsertPoint(StartBlock, StartBlock->begin());
 
   for (auto &Array : S.arrays()) {
     if (Array->getNumberOfDimensions() != 0)
@@ -850,7 +850,7 @@ void BlockGenerator::createScalarFinalization(Scop &S) {
   if (OptExitBB == ExitBB)
     OptExitBB = *(++pred_begin(MergeBB));
 
-  Builder.SetInsertPoint(OptExitBB->getTerminator());
+  Builder.SetInsertPoint(OptExitBB, OptExitBB->getTerminator()->getIterator());
   for (const auto &EscapeMapping : EscapeMap) {
     // Extract the escaping instruction and the escaping users as well as the
     // alloca the instruction was demoted to.
@@ -921,7 +921,7 @@ void BlockGenerator::createExitPHINodeMerges(Scop &S) {
   if (OptExitBB == ExitBB)
     OptExitBB = *(++pred_begin(MergeBB));
 
-  Builder.SetInsertPoint(OptExitBB->getTerminator());
+  Builder.SetInsertPoint(OptExitBB, OptExitBB->getTerminator()->getIterator());
 
   for (auto &SAI : S.arrays()) {
     auto *Val = SAI->getBasePtr();
@@ -1072,7 +1072,7 @@ void RegionGenerator::copyStmt(ScopStmt &Stmt, LoopToScevMapT &LTS,
   BasicBlock *EntryBBCopy = SplitBlock(
       Builder.GetInsertBlock(), &*Builder.GetInsertPoint(), GenDT, GenLI);
   EntryBBCopy->setName("polly.stmt." + EntryBB->getName() + ".entry");
-  Builder.SetInsertPoint(&EntryBBCopy->front());
+  Builder.SetInsertPoint(EntryBBCopy, EntryBBCopy->begin());
 
   ValueMapT &EntryBBMap = RegionMaps[EntryBBCopy];
   generateScalarLoads(Stmt, LTS, EntryBBMap, IdToAstExp);
@@ -1112,7 +1112,7 @@ void RegionGenerator::copyStmt(ScopStmt &Stmt, LoopToScevMapT &LTS,
     ValueMapT &RegionMap = Inserted.first->second;
 
     // Copy the block with the BlockGenerator.
-    Builder.SetInsertPoint(&BBCopy->front());
+    Builder.SetInsertPoint(BBCopy, BBCopy->begin());
     copyBB(Stmt, BB, BBCopy, RegionMap, LTS, IdToAstExp);
 
     // In order to remap PHI nodes we store also basic block mappings.
@@ -1166,7 +1166,7 @@ void RegionGenerator::copyStmt(ScopStmt &Stmt, LoopToScevMapT &LTS,
     ValueMapT &RegionMap = RegionMaps[BBCopyStart];
     RegionMap.insert_range(StartBlockMap);
 
-    Builder.SetInsertPoint(BICopy);
+    Builder.SetInsertPoint(BBCopyEnd, BICopy->getIterator());
     copyInstScalar(Stmt, TI, RegionMap, LTS);
     BICopy->eraseFromParent();
   }
@@ -1204,7 +1204,7 @@ void RegionGenerator::copyStmt(ScopStmt &Stmt, LoopToScevMapT &LTS,
   }
 
   // Continue generating code in the exit block.
-  Builder.SetInsertPoint(&*ExitBBCopy->getFirstInsertionPt());
+  Builder.SetInsertPoint(ExitBBCopy, ExitBBCopy->getFirstInsertionPt());
 
   // Write values visible to other statements.
   generateScalarStores(Stmt, LTS, ValueMap, IdToAstExp);
@@ -1241,7 +1241,8 @@ PHINode *RegionGenerator::buildExitPHI(MemoryAccess *MA, LoopToScevMapT &LTS,
     BasicBlock *OrigIncomingBlock = Pair.first;
     BasicBlock *NewIncomingBlockStart = StartBlockMap.lookup(OrigIncomingBlock);
     BasicBlock *NewIncomingBlockEnd = EndBlockMap.lookup(OrigIncomingBlock);
-    Builder.SetInsertPoint(NewIncomingBlockEnd->getTerminator());
+    Builder.SetInsertPoint(NewIncomingBlockEnd,
+                           NewIncomingBlockEnd->getTerminator()->getIterator());
     assert(RegionMaps.count(NewIncomingBlockStart));
     assert(RegionMaps.count(NewIncomingBlockEnd));
     ValueMapT *LocalBBMap = &RegionMaps[NewIncomingBlockStart];
@@ -1358,10 +1359,11 @@ void RegionGenerator::addOperandToPHI(ScopStmt &Stmt, PHINode *PHI,
     // change it, otherwise do not.
     auto IP = Builder.GetInsertPoint();
     if (IP->getParent() != BBCopyEnd)
-      Builder.SetInsertPoint(BBCopyEnd->getTerminator());
+      Builder.SetInsertPoint(BBCopyEnd,
+                             BBCopyEnd->getTerminator()->getIterator());
     OpCopy = getNewValue(Stmt, Op, BBCopyMap, LTS, getLoopForStmt(Stmt));
     if (IP->getParent() != BBCopyEnd)
-      Builder.SetInsertPoint(&*IP);
+      Builder.SetInsertPoint(IP);
   } else {
     // All edges from outside the non-affine region become a single edge
     // in the new copy of the non-affine region. Make sure to only add the
diff --git a/polly/lib/CodeGen/CodeGeneration.cpp b/polly/lib/CodeGen/CodeGeneration.cpp
index f5e29c38e2903..2d8b393cc039c 100644
--- a/polly/lib/CodeGen/CodeGeneration.cpp
+++ b/polly/lib/CodeGen/CodeGeneration.cpp
@@ -77,8 +77,8 @@ namespace polly {
 /// Marks the basic block @p Block unreachable by equipping it with an
 /// UnreachableInst.
 void markBlockUnreachable(BasicBlock &Block, PollyIRBuilder &Builder) {
-  auto *OrigTerminator = Block.getTerminator();
-  Builder.SetInsertPoint(OrigTerminator);
+  auto OrigTerminator = Block.getTerminator()->getIterator();
+  Builder.SetInsertPoint(&Block, OrigTerminator);
   Builder.CreateUnreachable();
   OrigTerminator->eraseFromParent();
 }
@@ -211,7 +211,8 @@ static bool generateCode(Scop &S, IslAstInfo &AI, LoopInfo &LI,
   assert(EnteringBB);
   PollyIRBuilder Builder(EnteringBB->getContext(), ConstantFolder(),
                          IRInserter(Annotator));
-  Builder.SetInsertPoint(EnteringBB->getTerminator());
+  Builder.SetInsertPoint(EnteringBB,
+                         EnteringBB->getTerminator()->getIterator());
 
   // Only build the run-time condition and parameters _after_ having
   // introduced the conditional branch. This is important as the conditional
@@ -257,7 +258,8 @@ static bool generateCode(Scop &S, IslAstInfo &AI, LoopInfo &LI,
   // might reference the hoisted loads. Finally, build the runtime check
   // that might reference both hoisted loads as well as parameters.
   // If the hoisting fails we have to bail and execute the original code.
-  Builder.SetInsertPoint(SplitBlock->getTerminator());
+  Builder.SetInsertPoint(SplitBlock,
+                         SplitBlock->getTerminator()->getIterator());
   if (!NodeBuilder.preloadInvariantLoads()) {
     // Patch the introduced branch condition to ensure that we always execute
     // the original SCoP.
@@ -289,7 +291,8 @@ static bool generateCode(Scop &S, IslAstInfo &AI, LoopInfo &LI,
     // Ideally we would just split the block during allocation of the new
     // arrays, but this would break the assumption that there are no blocks
     // between polly.start and polly.exiting (at this point).
-    Builder.SetInsertPoint(StartBlock->getTerminator());
+    Builder.SetInsertPoint(StartBlock,
+                           StartBlock->getTerminator()->getIterator());
 
     NodeBuilder.create(AstRoot.release());
     NodeBuilder.finalize();
diff --git a/polly/lib/CodeGen/IslExprBuilder.cpp b/polly/lib/CodeGen/IslExprBuilder.cpp
index 8c54436f295b3..eecc616724b88 100644
--- a/polly/lib/CodeGen/IslExprBuilder.cpp
+++ b/polly/lib/CodeGen/IslExprBuilder.cpp
@@ -625,7 +625,7 @@ IslExprBuilder::createOpBooleanConditional(__isl_take isl_ast_expr *Expr) {
   Builder.SetInsertPoint(CondBB);
   Builder.CreateBr(NextBB);
 
-  Builder.SetInsertPoint(InsertBB->getTerminator());
+  Builder.SetInsertPoint(InsertBB, InsertBB->getTerminator()->getIterator());
 
   LHS = create(isl_ast_expr_get_op_arg(Expr, 0));
   if (!LHS->getType()->isIntegerTy(1))
@@ -637,13 +637,13 @@ IslExprBuilder::createOpBooleanConditional(__isl_take isl_ast_expr *Expr) {
   else
     BR->setCondition(LHS);
 
-  Builder.SetInsertPoint(CondBB->getTerminator());
+  Builder.SetInsertPoint(CondBB, CondBB->getTerminator()->getIterator());
   RHS = create(isl_ast_expr_get_op_arg(Expr, 1));
   if (!RHS->getType()->isIntegerTy(1))
     RHS = Builder.CreateIsNotNull(RHS);
   auto RightBB = Builder.GetInsertBlock();
 
-  Builder.SetInsertPoint(NextBB->getTerminator());
+  Builder.SetInsertPoint(NextBB, NextBB->getTerminator()->getIterator());
   auto PHI = Builder.CreatePHI(Builder.getInt1Ty(), 2);
   PHI->addIncoming(OpType == isl_ast_op_and_then ? Builder.getFalse()
                                                  : Builder.getTrue(),
diff --git a/polly/lib/CodeGen/IslNodeBuilder.cpp b/polly/lib/CodeGen/IslNodeBuilder.cpp
index e818dab4f9c0c..1217b620eed89 100644
--- a/polly/lib/CodeGen/IslNodeBuilder.cpp
+++ b/polly/lib/CodeGen/IslNodeBuilder.cpp
@@ -488,7 +488,7 @@ void IslNodeBuilder::createForSequential(isl::ast_node_for For,
 
   IDToValue.erase(IDToValue.find(IteratorID.get()));
 
-  Builder.SetInsertPoint(&ExitBlock->front());
+  Builder.SetInsertPoint(ExitBlock, ExitBlock->begin());
 
   SequentialLoops++;
 }
@@ -508,7 +508,7 @@ void IslNodeBuilder::createForParallel(__isl_take isl_ast_node *For) {
   BasicBlock *ParBB = SplitBlock(Builder.GetInsertBlock(),
                                  &*Builder.GetInsertPoint(), &DT, &LI);
   ParBB->setName("polly.parallel.for");
-  Builder.SetInsertPoint(&ParBB->front());
+  Builder.SetInsertPoint(ParBB, ParBB->begin());
 
   Body = isl_ast_node_for_get_body(For);
   Init = isl_ast_node_for_get_init(For);
@@ -612,7 +612,7 @@ void IslNodeBuilder::createForParallel(__isl_take isl_ast_node *For) {
   BlockGen.switchGeneratedFunc(SubFn, GenDT, GenLI, GenSE);
   RegionGen.switchGeneratedFunc(SubFn, GenDT, GenLI, GenSE);
   ExprBuilder.switchGeneratedFunc(SubFn, GenDT, GenLI, GenSE);
-  Builder.SetInsertPoint(&*LoopBody);
+  Builder.SetInsertPoint(LoopBody);
 
   // Update the ValueMap to use instructions in the subfunction. Note that
   // "GlobalMap" used in BlockGenerator/IslExprBuilder is a reference to this
@@ -682,7 +682,7 @@ void IslNodeBuilder::createForParallel(__isl_take isl_ast_node *For) {
   ExprBuilder.switchGeneratedFunc(CallerFn, CallerDT, CallerLI, CallerSE);
   RegionGen.switchGeneratedFunc(CallerFn, CallerDT, CallerLI, CallerSE);
   BlockGen.switchGeneratedFunc(CallerFn, CallerDT, CallerLI, CallerSE);
-  Builder.SetInsertPoint(&*AfterLoop);
+  Builder.SetInsertPoint(AfterLoop);
 
   for (const Loop *L : Loops)
     OutsideLoopIterations.erase(L);
@@ -737,16 +737,16 @@ void IslNodeBuilder::createIf(__isl_take isl_ast_node *If) {
   Builder.CreateBr(MergeBB);
   Builder.SetInsertPoint(ElseBB);
   Builder.CreateBr(MergeBB);
-  Builder.SetInsertPoint(&ThenBB->front());
+  Builder.SetInsertPoint(ThenBB, ThenBB->begin());
 
   create(isl_ast_node_if_get_then(If));
 
-  Builder.SetInsertPoint(&ElseBB->front());
+  Builder.SetInsertPoint(ElseBB, ElseBB->begin());
 
   if (isl_ast_node_if_has_else(If))
     create(isl_ast_node_if_get_else(If));
 
-  Builder.SetInsertPoint(&MergeBB->front());
+  Builder.SetInsertPoint(MergeBB, MergeBB->begin());
 
   isl_ast_node_free(If);
 
@@ -1126,16 +1126,16 @@ Value *IslNodeBuilder::preloadInvariantLoad(const MemoryAccess &MA,
     L->addBasicBlockToLoop(ExecBB, *GenLI);
 
   auto *CondBBTerminator = CondBB->getTerminator();
-  Builder.SetInsertPoint(CondBBTerminator);
+  Builder.SetInsertPoint(CondBB, CondBBTerminator->getIterator());
   Builder.CreateCondBr(Cond, ExecBB, MergeBB);
   CondBBTerminator->eraseFromParent();
 
   Builder.SetInsertPoint(ExecBB);
   Builder.CreateBr(MergeBB);
 
-  Builder.SetInsertPoint(ExecBB->getTerminator());
+  Builder.SetInsertPoint(ExecBB, ExecBB->getTerminator()->getIterator());
   Value *PreAccInst = preloadUnconditionally(AccessRange, Build, AccInst);
-  Builder.SetInsertPoint(MergeBB->getTerminator());
+  Builder.SetInsertPoint(MergeBB, MergeBB->getTerminator()->getIterator());
   auto *MergePHI = Builder.CreatePHI(
       AccInstTy, 2, "polly.preload." + AccInst->getName() + ".merge");
   PreloadVal = MergePHI;
@@ -1315,7 +1315,9 @@ void IslNodeBuilder::allocateNewArrays(BBPair StartExitBlocks) {
       unsigned Size = SAI->getElemSizeInBytes();
 
       // Insert the malloc call at polly.start
-      Builder.SetInsertPoint(std::get<0>(StartExitBlocks)->getTerminator());
+      BasicBlock *StartBlock = std::get<0>(StartExitBlocks);
+      Builder.SetInsertPoint(StartBlock,
+                             StartBlock->getTerminator()->getIterator());
       auto *CreatedArray = Builder.CreateMalloc(
           IntPtrTy, SAI->getElementType(),
           ConstantInt::get(Type::getInt64Ty(Ctx), Size),
@@ -1325,7 +1327,9 @@ void IslNodeBuilder::allocateNewArrays(BBPair StartExitBlocks) {
       SAI->setBasePtr(CreatedArray);
 
       // Insert the free call at polly.exiting
-      Builder.SetInsertPoint(std::get<1>(StartExitBlocks)->getTerminator());
+      BasicBlock *ExitingBlock = std::get<1>(StartExitBlocks);
+      Builder.SetInsertPoint(ExitingBlock,
+                             ExitingBlock->getTerminator()->getIterator());
       Builder.CreateFree(CreatedArray);
     } else {
       auto InstIt = Builder.GetInsertBlock()
@@ -1351,7 +1355,7 @@ bool IslNodeBuilder::preloadInvariantLoads() {
   BasicBlock *PreLoadBB = SplitBlock(Builder.GetInsertBlock(),
                                      &*Builder.GetInsertPoint(), GenDT, GenLI);
   PreLoadBB->setName("polly.preload.begin");
-  Builder.SetInsertPoint(&PreLoadBB->front());
+  Builder.SetInsertPoint(PreLoadBB, PreLoadBB->begin());
 
   for (auto &IAClass : InvariantEquivClasses)
     if (!preloadInvariantEquivClass(IAClass))
diff --git a/polly/lib/CodeGen/LoopGenerators.cpp b/polly/lib/CodeGen/LoopGenerators.cpp
index f3975ccee44fa..10d96eb10b708 100644
--- a/polly/lib/CodeGen/LoopGenerators.cpp
+++ b/polly/lib/CodeGen/LoopGenerators.cpp
@@ -200,7 +200,7 @@ Value *ParallelLoopGenerator::createParallelLoop(
   Function *SubFn;
   std::tie(IV, SubFn) = createSubFn(Stride, Struct, UsedValues, Map);
   *LoopBody = Builder.GetInsertPoint();
-  Builder.SetInsertPoint(&*BeforeLoop);
+  Builder.SetInsertPoint(BeforeLoop);
 
   // Add one as the upper bound provided by OpenMP is a < comparison
   // whereas the codegenForSequential function creates a <= comparison.
diff --git a/polly/lib/CodeGen/LoopGeneratorsGOMP.cpp b/polly/lib/CodeGen/LoopGeneratorsGOMP.cpp
index 61c153d2ccfa5..7b6d63a8ae186 100644
--- a/polly/lib/CodeGen/LoopGeneratorsGOMP.cpp
+++ b/polly/lib/CodeGen/LoopGeneratorsGOMP.cpp
@@ -148,7 +148,7 @@ ParallelLoopGeneratorGOMP::createSubFn(Value *Stride, AllocaInst *StructData,
                          "polly.par.UBAdjusted");
 
   Builder.CreateBr(CheckNextBB);
-  Builder.SetInsertPoint(&*--Builder.GetInsertPoint());
+  Builder.SetInsertPoint(--Builder.GetInsertPoint());
   BasicBlock *AfterBB;
   Value *IV =
       createLoop(LB, UB, Stride, Builder, *SubFnLI, *SubFnDT, AfterBB,
@@ -161,7 +161,7 @@ ParallelLoopGeneratorGOMP::createSubFn(Value *Stride, AllocaInst *StructData,
   createCallCleanupThread();
   Builder.CreateRetVoid();
 
-  Builder.SetInsertPoint(&*LoopBody);
+  Builder.SetInsertPoint(LoopBody);
 
   // FIXME: Call SubFnDT->verify() and SubFnLI->verify() to check that the
   // DominatorTree/LoopInfo has been created correctly. Alternatively, recreate
diff --git a/polly/lib/CodeGen/LoopGeneratorsKMP.cpp b/polly/lib/CodeGen/LoopGeneratorsKMP.cpp
index 0cfe18b0c1217..0973191e003c9 100644
--- a/polly/lib/CodeGen/LoopGeneratorsKMP.cpp
+++ b/polly/lib/CodeGen/LoopGeneratorsKMP.cpp
@@ -282,7 +282,7 @@ ParallelLoopGeneratorKMP::createSubFn(Value *SequentialLoopStride,
   }
 
   Builder.CreateBr(CheckNextBB);
-  Builder.SetInsertPoint(&*--Builder.GetInsertPoint());
+  Builder.SetInsertPoint(--Builder.GetInsertPoint());
   BasicBlock *AfterBB;
   Value *IV = createLoop(LB, UB, SequentialLoopStride, Builder, *SubFnLI,
                          *SubFnDT, AfterBB, ICmpInst::ICMP_SLE, nullptr, true,
@@ -298,7 +298,7 @@ ParallelLoopGeneratorKMP::createSubFn(Value *SequentialLoopStride,
     createCallStaticFini(ID);
   }
   Builder.CreateRetVoid();
-  Builder.SetInsertPoint(&*LoopBody);
+  Builder.SetInsertPoint(LoopBody);
 
   // FIXME: Call SubFnDT->verify() and SubFnLI->verify() to check that the
   // DominatorTree/LoopInfo has been created correctly. Alternatively, recreate
diff --git a/polly/lib/CodeGen/PerfMonitor.cpp b/polly/lib/CodeGen/PerfMonitor.cpp
index 4c1eab0050848..7b559e990b7c0 100644
--- a/polly/lib/CodeGen/PerfMonitor.cpp
+++ b/polly/lib/CodeGen/PerfMonitor.cpp
@@ -267,7 +267,7 @@ void PerfMonitor::insertRegionStart(Instruction *InsertBefore) {
   if (!Supported)
     return;
 
-  Builder.SetInsertPoint(InsertBefore);
+  Builder.SetInsertPoint(InsertBefore->getIterator());
   Function *RDTSCPFn = getRDTSCP();
   Value *CurrentCycles =
       Builder.CreateExtractValue(Builder.CreateCall(RDTSCPFn), {0});
@@ -278,7 +278,7 @@ void PerfMonitor::insertRegionEnd(Instruction *InsertBefore) {
   if (!Supported)
     return;
 
-  Builder.SetInsertPoint(InsertBefore);
+  Builder.SetInsertPoint(InsertBefore->getIterator());
   Function *RDTSCPFn = getRDTSCP();
   Type *Int64Ty = Builder.getInt64Ty();
   LoadInst *CyclesStart =
diff --git a/utils/bazel/llvm-project-overlay/lldb/BUILD.bazel b/utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
index d1bacf9d03360..809dbefcef5e9 100644
--- a/utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
+++ b/utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
@@ -484,10 +484,8 @@ cc_library(
 
 objc_library(
     name = "HostMacOSXObjCXX",
-    srcs = glob([
-        "source/Host/macosx/objcxx/*.mm",
-    ]),
     copts = OBJCPP_COPTS,
+    non_arc_srcs = glob(["source/Host/macosx/objcxx/*.mm"]),
     tags = ["nobuildkite"],
     target_compatible_with = select({
         "@platforms//os:macos": [],
@@ -832,9 +830,9 @@ cc_binary(
     deps = [
         ":APIHeaders",
         ":Host",
+        ":UtilityHeaders",
         ":liblldb.wrapper",
         ":lldb_options_inc_gen",
-        ":UtilityHeaders",
         "//llvm:Option",
         "//llvm:Support",
     ],
@@ -855,8 +853,8 @@ cc_library(
 
 objc_library(
     name = "DebugServerMacOSX",
-    srcs = glob(["tools/debugserver/source/MacOSX/*.mm"]),
     copts = OBJCPP_COPTS,
+    non_arc_srcs = glob(["tools/debugserver/source/MacOSX/*.mm"]),
     tags = ["nobuildkite"],
     target_compatible_with = select({
         "@platforms//os:macos": [],
diff --git a/utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel b/utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
index b204d8fa04584..f01023bfff6e4 100644
--- a/utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
+++ b/utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
@@ -238,8 +238,8 @@ cc_library(
 
 objc_library(
     name = "PluginPlatformMacOSXObjCXX",
-    srcs = glob(["Platform/MacOSX/objcxx/*.mm"]),
     copts = OBJCPP_COPTS,
+    non_arc_srcs = glob(["Platform/MacOSX/objcxx/*.mm"]),
     tags = ["nobuildkite"],
     target_compatible_with = select({
         "@platforms//os:macos": [],
diff --git a/utils/bazel/llvm-project-overlay/lldb/source/Plugins/plugin_config.bzl b/utils/bazel/llvm-project-overlay/lldb/source/Plugins/plugin_config.bzl
index 5949d2d7a504c..2a8bba52c2a6a 100644
--- a/utils/bazel/llvm-project-overlay/lldb/source/Plugins/plugin_config.bzl
+++ b/utils/bazel/llvm-project-overlay/lldb/source/Plugins/plugin_config.bzl
@@ -99,6 +99,5 @@ DEFAULT_SCRIPT_PLUGINS = [
 OBJCPP_COPTS = [
     "-std=c++{}".format(CMAKE_CXX_STANDARD),
     "-fno-objc-exceptions",
-    "-fno-objc-arc",
     "-Wno-shorten-64-to-32",
 ]
diff --git a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
index f79c3656dda92..0f4f5fadffa3e 100644
--- a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+++ b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
@@ -1586,15 +1586,12 @@ cc_library(
         ":ArithDialect",
         ":ArithUtils",
         ":ControlFlowDialect",
-        ":FuncDialect",
-        ":GPUDialect",
         ":IR",
         ":LLVMSupportHeaders",
         ":MemRefDialect",
         ":MemRefUtils",
         ":Pass",
         ":SCFDialect",
-        ":SideEffectInterfaces",
         ":Support",
         ":TransformUtils",
         ":VectorDialect",
@@ -1819,7 +1816,6 @@ cc_library(
         ":FuncDialect",
         ":IR",
         ":LLVMDialect",
-        ":Support",
         ":TransformUtils",
         ":VectorDialect",
     ],
@@ -1958,10 +1954,7 @@ cc_library(
     includes = ["include"],
     deps = [
         ":ArmSMEOpInterfacesIncGen",
-        ":IR",
-        ":Support",
         ":VectorDialect",
-        "//llvm:Support",
     ],
 )
 
@@ -2034,7 +2027,6 @@ cc_library(
         ":IR",
         ":IndexDialect",
         ":LLVMCommonConversion",
-        ":LLVMDialect",
         ":MemRefDialect",
         ":Pass",
         ":SCFDialect",
@@ -2316,6 +2308,7 @@ cc_library(
         ":BytecodeOpInterface",
         ":IR",
         ":InferTypeOpInterface",
+        ":LLVMCommonConversion",
         ":LLVMDialect",
         ":SideEffectInterfaces",
         ":X86VectorIncGen",
@@ -2884,22 +2877,16 @@ cc_library(
         "include/mlir/Dialect/SparseTensor/Pipelines/Passes.h",
     ],
     includes = ["include"],
-    local_defines = if_cuda_available(["MLIR_GPU_TO_CUBIN_PASS_ENABLE"]),
     deps = [
-        ":ArithToLLVM",
         ":ArithTransforms",
         ":BufferizationTransforms",
-        ":ControlFlowToLLVM",
         ":ConversionPasses",
         ":FuncDialect",
         ":GPUDialect",
-        ":GPUToNVVMTransforms",
         ":GPUTransforms",
         ":LinalgTransforms",
         ":MemRefTransforms",
-        ":NVVMDialect",
         ":Pass",
-        ":SparseTensorDialect",
         ":SparseTensorTransforms",
         ":Transforms",
         ":VectorToLLVM",
@@ -3002,7 +2989,6 @@ cc_library(
         ":MeshDialect",
         ":MeshShardingInterfaceIncGen",
         ":Support",
-        ":TensorDialect",
         "//llvm:Support",
     ],
 )
@@ -3097,7 +3083,6 @@ cc_library(
         ":Support",
         ":TensorDialect",
         ":TransformUtils",
-        "//llvm:Support",
     ],
 )
 
@@ -3286,7 +3271,6 @@ cc_library(
         ":NVGPUPassIncGen",
         ":Pass",
         ":SideEffectInterfaces",
-        ":Support",
         ":VectorDialect",
         "//llvm:Support",
     ],
@@ -3389,10 +3373,8 @@ cc_library(
         ":BytecodeOpInterface",
         ":DialectUtils",
         ":IR",
-        ":MaskableOpInterface",
         ":ShapedOpInterfaces",
         ":SideEffectInterfaces",
-        ":Support",
         ":VectorDialect",
         ":ViewLikeInterface",
         ":XeGPUEnumsIncGen",
@@ -3429,8 +3411,6 @@ cc_library(
         ":IR",
         ":MemRefDialect",
         ":Pass",
-        ":SideEffectInterfaces",
-        ":Support",
         ":TransformUtils",
         ":VectorDialect",
         ":XeGPUDialect",
@@ -3805,7 +3785,6 @@ cc_library(
         ":IndexToLLVM",
         ":IndexToSPIRV",
         ":LinalgToStandard",
-        ":MPIToLLVM",
         ":MathToEmitC",
         ":MathToFuncs",
         ":MathToLLVM",
@@ -3844,7 +3823,6 @@ cc_library(
         ":VectorToSCF",
         ":VectorToSPIRV",
         ":VectorToXeGPU",
-        ":VectorTransforms",
     ],
 )
 
@@ -3924,7 +3902,6 @@ cc_library(
         ":SCFDeviceMappingInterfacesIncGen",
         ":SCFIncGen",
         ":SideEffectInterfaces",
-        ":Support",
         ":TensorDialect",
         ":ValueBoundsOpInterface",
         ":ViewLikeInterface",
@@ -4221,10 +4198,8 @@ cc_library(
         ":ArithDialect",
         ":BufferizationDialect",
         ":BufferizationInterfaces",
-        ":BufferizationTransforms",
         ":FuncDialect",
         ":IR",
-        ":MemRefDialect",
         ":Pass",
         ":ShapeDialect",
         ":ShapeTransformsPassIncGen",
@@ -4290,7 +4265,6 @@ cc_library(
         ":IR",
         ":InliningUtils",
         ":SideEffectInterfaces",
-        ":Support",
         "//llvm:Support",
     ],
 )
@@ -4337,7 +4311,6 @@ cc_library(
         ":InferTypeOpInterface",
         ":InliningUtils",
         ":SideEffectInterfaces",
-        ":Support",
         "//llvm:Support",
     ],
 )
@@ -4473,12 +4446,9 @@ cc_library(
     hdrs = glob(["include/mlir/Dialect/Func/Transforms/*.h"]),
     includes = ["include"],
     deps = [
-        ":BufferizationDialect",
-        ":BufferizationTransforms",
         ":FuncDialect",
         ":FuncTransformsPassIncGen",
         ":IR",
-        ":MemRefDialect",
         ":Pass",
         ":Support",
         ":TransformUtils",
@@ -4603,7 +4573,6 @@ cc_library(
         ":ArithUtils",
         ":BufferizationDialect",
         ":BufferizationInterfaces",
-        ":BufferizationTransforms",
         ":DialectUtils",
         ":FuncDialect",
         ":FunctionInterfaces",
@@ -4617,7 +4586,6 @@ cc_library(
         ":SCFDialect",
         ":SideEffectInterfaces",
         ":SubsetOpInterface",
-        ":Support",
         ":TensorDialect",
         ":TransformUtils",
         ":UBDialect",
@@ -4833,7 +4801,6 @@ cc_library(
     deps = [
         ":BytecodeOpInterface",
         ":IR",
-        ":Support",
         "//llvm:Support",
         "//llvm:config",
     ],
@@ -5206,6 +5173,8 @@ cc_library(
     hdrs = glob(["include/mlir/Dialect/GPU/Transforms/*.h"]),
     includes = ["include"],
     deps = [
+        ":AMDGPUDialect",
+        ":AMDGPUUtils",
         ":AffineDialect",
         ":AffineUtils",
         ":ArithDialect",
@@ -5423,14 +5392,11 @@ cc_library(
     ]),
     includes = ["include"],
     deps = [
-        ":ArithToLLVM",
         ":ControlFlowDialect",
-        ":ControlFlowToLLVM",
         ":ConversionPassIncGen",
         ":ConvertToLLVM",
         ":ConvertToLLVMInterface",
         ":FuncDialect",
-        ":FuncToLLVM",
         ":GPUCommonTransforms",
         ":GPUDialect",
         ":GPUToGPURuntimeTransforms",
@@ -5441,11 +5407,9 @@ cc_library(
         ":LLVMDialect",
         ":MathDialect",
         ":MemRefDialect",
-        ":MemRefToLLVM",
         ":NVGPUDialect",
         ":NVVMDialect",
         ":TransformUtils",
-        ":VectorToLLVM",
     ],
 )
 
@@ -5514,7 +5478,6 @@ cc_library(
         ":Pass",
         ":SPIRVConversion",
         ":SPIRVDialect",
-        ":Support",
         ":TransformUtils",
         ":UBDialect",
         ":UBToSPIRV",
@@ -5545,15 +5508,12 @@ cc_library(
     includes = ["include"],
     deps = [
         ":AMDGPUToROCDL",
-        ":ArithToLLVM",
         ":ArithTransforms",
         ":ControlFlowDialect",
-        ":ControlFlowToLLVM",
         ":ConversionPassIncGen",
         ":ConvertToLLVM",
         ":ConvertToLLVMInterface",
         ":FuncDialect",
-        ":FuncToLLVM",
         ":GPUCommonTransforms",
         ":GPUDialect",
         ":GPUToGPURuntimeTransforms",
@@ -5566,13 +5526,11 @@ cc_library(
         ":MathToLLVM",
         ":MathToROCDL",
         ":MemRefDialect",
-        ":MemRefToLLVM",
         ":Pass",
         ":ROCDLDialect",
         ":TransformUtils",
         ":Transforms",
         ":VectorDialect",
-        ":VectorToLLVM",
         "//llvm:Support",
     ],
 )
@@ -5641,7 +5599,6 @@ cc_library(
         ":SCFToSPIRV",
         ":SPIRVConversion",
         ":SPIRVDialect",
-        ":Support",
         ":TransformUtils",
         ":VectorToSPIRV",
         "//llvm:Support",
@@ -5693,9 +5650,7 @@ cc_library(
         ":Pass",
         ":SPIRVCommonAttrToLLVMConversion",
         ":SPIRVDialect",
-        ":SPIRVImageInterfaces",
         ":SPIRVUtils",
-        ":Support",
         ":TransformUtils",
         "//llvm:Support",
     ],
@@ -6271,6 +6226,7 @@ td_library(
         ":BuiltinDialectTdFiles",
         ":DataLayoutInterfacesTdFiles",
         ":OpBaseTdFiles",
+        ":ViewLikeInterfaceTdFiles",
     ],
 )
 
@@ -6364,6 +6320,8 @@ cc_library(
         ":PtrMemorySpaceInterfacesIncGen",
         ":PtrOpsEnumsGen",
         ":PtrOpsIncGen",
+        ":SideEffectInterfaces",
+        ":ViewLikeInterface",
         "//llvm:Support",
     ],
 )
@@ -6497,7 +6455,6 @@ cc_library(
     deps = [
         ":IR",
         ":SPIRVImageInterfacesIncGen",
-        "//llvm:Support",
     ],
 )
 
@@ -6678,7 +6635,6 @@ cc_library(
         ":SPIRVDialect",
         ":SPIRVPassIncGen",
         ":SPIRVUtils",
-        ":Support",
         ":TransformUtils",
         "//llvm:Support",
     ],
@@ -6799,7 +6755,6 @@ cc_library(
         ":SPIRVConversion",
         ":SPIRVDialect",
         ":SPIRVUtils",
-        ":Support",
         ":TransformUtils",
         "//llvm:Support",
     ],
@@ -6824,7 +6779,6 @@ cc_library(
         ":LinalgDialect",
         ":LinalgTransforms",
         ":Pass",
-        ":Support",
         ":TensorDialect",
         ":TransformUtils",
         "//llvm:Support",
@@ -6853,7 +6807,6 @@ cc_library(
         ":SPIRVConversion",
         ":SPIRVDialect",
         ":SPIRVUtils",
-        ":Support",
         ":TensorDialect",
         ":TransformUtils",
         "//llvm:Support",
@@ -7070,12 +7023,8 @@ cc_library(
     hdrs = glob(["include/mlir/Dialect/Tensor/Extensions/*.h"]),
     includes = ["include"],
     deps = [
-        ":DialectUtils",
         ":IR",
-        ":MeshDialect",
         ":MeshShardingInterface",
-        ":MeshShardingInterfaceIncGen",
-        ":Support",
         ":TensorDialect",
         "//llvm:Support",
     ],
@@ -7125,9 +7074,7 @@ cc_library(
         ":ArithUtils",
         ":BufferizationDialect",
         ":BufferizationInterfaces",
-        ":BufferizationTransforms",
         ":DialectUtils",
-        ":FuncDialect",
         ":IR",
         ":LinalgDialect",
         ":MemRefDialect",
@@ -7659,7 +7606,6 @@ cc_library(
     includes = ["include"],
     deps = [
         ":IR",
-        ":Support",
         ":ToLLVMInterfaceIncGen",
         "//llvm:Support",
     ],
@@ -7753,7 +7699,6 @@ cc_library(
         ":ControlFlowDialect",
         ":ConversionPassIncGen",
         ":FuncDialect",
-        ":LLVMDialect",
         ":Pass",
         ":SCFDialect",
         ":TransformUtils",
@@ -7797,7 +7742,6 @@ cc_library(
         ":SPIRVConversion",
         ":SPIRVDialect",
         ":SPIRVUtils",
-        ":Support",
         ":TransformUtils",
         "//llvm:Support",
     ],
@@ -7842,7 +7786,6 @@ cc_library(
         ":MemRefDialect",
         ":MemRefUtils",
         ":Pass",
-        ":Support",
         "//llvm:Support",
     ],
 )
@@ -7868,7 +7811,6 @@ cc_library(
         ":Pass",
         ":SPIRVConversion",
         ":SPIRVDialect",
-        ":Support",
         ":TransformUtils",
         "//llvm:Support",
     ],
@@ -7900,7 +7842,6 @@ cc_library(
         ":LLVMDialect",
         ":Pass",
         ":ROCDLDialect",
-        ":Support",
         ":TransformUtils",
         ":VectorDialect",
     ],
@@ -7943,7 +7884,6 @@ cc_library(
         ":EmitCTransforms",
         ":IR",
         ":Pass",
-        ":Support",
         ":TransformUtils",
     ],
 )
@@ -8068,7 +8008,6 @@ cc_library(
     deps = [
         ":BytecodeOpInterfaceIncGen",
         ":IR",
-        ":Support",
         "//llvm:Support",
     ],
 )
@@ -8554,11 +8493,9 @@ cc_library(
         ":LLVMIRToLLVMTranslation",
         ":LLVMIRToNVVMTranslation",
         ":LLVMToLLVMIRTranslation",
-        ":NVVMTarget",
         ":NVVMToLLVMIRTranslation",
         ":OpenACCToLLVMIRTranslation",
         ":OpenMPToLLVMIRTranslation",
-        ":ROCDLTarget",
         ":ROCDLToLLVMIRTranslation",
         ":SPIRVToLLVMIRTranslation",
         ":VCIXToLLVMIRTranslation",
@@ -8921,10 +8858,8 @@ cc_binary(
     deps = [
         ":AllExtensions",
         ":AllPassesAndDialects",
-        ":BytecodeWriter",
         ":IR",
         ":MlirLspServerLib",
-        ":Parser",
     ],
 )
 
@@ -9351,8 +9286,6 @@ cc_binary(
         ":IR",
         ":Support",
         "//llvm:Support",
-        "//llvm:TableGen",
-        "//llvm:config",
     ],
 )
 
@@ -9823,7 +9756,6 @@ cc_library(
         ":QuantDialectBytecodeGen",
         ":QuantOpsIncGen",
         ":SideEffectInterfaces",
-        ":Support",
         "//llvm:Support",
     ],
 )
@@ -10333,7 +10265,6 @@ cc_library(
         ":MemRefDialect",
         ":MeshShardingInterface",
         ":Parser",
-        ":RelayoutOpInterfaceIncGen",
         ":SCFDialect",
         ":SideEffectInterfaces",
         ":SparseTensorDialect",
@@ -10817,7 +10748,6 @@ cc_library(
         ":NVGPUUtils",
         ":Pass",
         ":SCFDialect",
-        ":Support",
         ":TransformUtils",
         ":Transforms",
         ":VectorDialect",
@@ -10841,7 +10771,6 @@ cc_library(
         ":ArithDialect",
         ":ConversionPassIncGen",
         ":IR",
-        ":LLVMDialect",
         ":MemRefDialect",
         ":Pass",
         ":SCFDialect",
@@ -11593,13 +11522,10 @@ cc_library(
     ]),
     includes = ["include"],
     deps = [
-        ":ArithAttrToLLVMConversion",
         ":ArithDialect",
-        ":ComplexDialect",
         ":LLVMCommonConversion",
         ":LLVMDialect",
         ":MathDialect",
-        ":Pass",
     ],
 )
 
@@ -11816,7 +11742,6 @@ cc_library(
         ":ControlFlowInterfaces",
         ":ConvertToLLVMInterface",
         ":DestinationStyleOpInterface",
-        ":FunctionInterfaces",
         ":IR",
         ":InferIntRangeCommon",
         ":InferIntRangeInterface",
@@ -11864,11 +11789,9 @@ cc_library(
         ":FuncTransforms",
         ":IR",
         ":MemRefDialect",
-        ":MeshDialect",
         ":MeshShardingInterface",
         ":Pass",
         ":SideEffectInterfaces",
-        ":Support",
         ":TensorDialect",
         ":TransformUtils",
         ":ValueBoundsOpInterface",
@@ -12107,7 +12030,6 @@ cc_library(
         ":RuntimeVerifiableOpInterface",
         ":ShapedOpInterfaces",
         ":SideEffectInterfaces",
-        ":Support",
         ":ValueBoundsOpInterface",
         ":ViewLikeInterface",
         "//llvm:Support",
@@ -12648,7 +12570,6 @@ cc_library(
         ":BufferizableOpInterfaceIncGen",
         ":BufferizationEnumsIncGen",
         ":BufferizationTypeInterfacesIncGen",
-        ":FunctionInterfaces",
         ":IR",
         ":Support",
         "//llvm:Support",
@@ -12738,7 +12659,6 @@ cc_library(
         ":SCFDialect",
         ":SideEffectInterfaces",
         ":SubsetOpInterface",
-        ":Support",
         ":TensorDialect",
         ":TransformUtils",
         ":Transforms",
@@ -12766,7 +12686,6 @@ cc_library(
         ":MemRefDialect",
         ":Pass",
         ":SCFDialect",
-        ":Support",
         ":TransformUtils",
     ],
 )
@@ -12917,7 +12836,6 @@ cc_library(
         ":Pass",
         ":ReducerIncGen",
         ":Rewrite",
-        ":Support",
         ":TransformUtils",
         "//llvm:Support",
     ],
@@ -12950,7 +12868,6 @@ cc_binary(
         ":AllPassesAndDialects",
         ":IR",
         ":MlirReduceLib",
-        "//llvm:Support",
         "//mlir/test:TestDialect",
     ],
 )
@@ -13008,7 +12925,6 @@ cc_binary(
         ":IR",
         ":MlirQueryLib",
         ":MlirQueryUtils",
-        "//llvm:Support",
         "//mlir/test:TestDialect",
     ],
 )
@@ -13098,7 +13014,6 @@ cc_binary(
         ":PDLLParser",
         ":Support",
         "//llvm:Support",
-        "//llvm:config",
     ],
 )
 
diff --git a/utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel b/utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
index b07c6f98a5ea0..95fb5fb537678 100644
--- a/utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
+++ b/utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
@@ -698,6 +698,8 @@ cc_library(
     deps = [
         "//llvm:NVPTXCodeGen",
         "//llvm:Support",
+        "//mlir:AMDGPUDialect",
+        "//mlir:AMDGPUUtils",
         "//mlir:AffineDialect",
         "//mlir:AffineToStandard",
         "//mlir:ArithDialect",
@@ -721,6 +723,7 @@ cc_library(
         "//mlir:NVVMToLLVM",
         "//mlir:NVVMToLLVMIRTranslation",
         "//mlir:Pass",
+        "//mlir:ROCDLDialect",
         "//mlir:ROCDLToLLVMIRTranslation",
         "//mlir:ReconcileUnrealizedCasts",
         "//mlir:SCFDialect",